CY8C20110-LDX2I

CY8C20110 CapSense Express™-10 Configurable IOs Features ■ Overview The CapSense ExpressTM controller allows the control of 10 IOs configurable as capacitive sensing buttons or as GPIOs for driving LEDs or interrupt signals based on various button conditions. The GPIOs are also configurable for waking up the device from sleep based on an interrupt input. The user has the ability to configure buttons, outputs, and parameters, through specific commands sent to the I2C port. The IOs have the flexibility in mapping to capacitive buttons and as standard GPIO functions such as interrupt output or input, LED drive and digital mapping of input to output using simple logical operations. This enables easy PCB trace routing and reduces the PCB size and stack up. CapSense Express products are designed for easy integration into complex products. 10 configurable IOs supporting ❐ CapSense buttons ❐ LED drive ❐ Interrupt outputs ❐ WAKE on interrupt input ❐ User defined input or output 2.4V to 5.25V operating voltage Industrial temperature range: –40°C to +85°C I2C slave interface for configuration and communication ❐ Selectable to 50 kHz, 100 kHz and 400 kHz Reduce BOM cost ❐ Internal oscillator - no external oscillators or crystal ❐ Free development tool - no external tuning components Low operating current ❐ Active current: continuous sensor scan: 1.5 mA ❐ Sleep current: no scan, continuous sleep: 2.6 uA Available in 16-pin COL and 16-pin SOIC packages ■ ■ ■ ■ Architecture The logic block diagram illustrates the internal architecture of CY8C20110. The user is able to configure registers with parameters needed to adjust the operation and sensitivity of the CapSense system. CY8C20110 supports a standard I2C serial communication interface that allows the host to configure the device and to read sensor information in real time through easy register access. ■ ■ The CapSense Express Core The CapSense Express Core has a powerful configuration and control block. It encompasses SRAM for data storage, an interrupt controller, along with sleep and watchdog timers. System resources provide additional capability, such as a configurable I2C slave communication interface and various system resets. The Analog system contains the CapSense PSoC block which supports capacitive sensing of up to 10 inputs. Cypress Semiconductor Corporation Document Number: 001-17345 Rev. *B • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 11, 2008 [+] Feedback CY8C20110 Logic Block Diagram External Vcc 2.4 - 5.25V CapSense ExpressTM Core 10 Configurable IOs 2KB Flash 512B SRAM Document Number: 001-17345 Rev. *B Page 2 of 12 [+] Feedback CY8C20110 Pinouts Figure 1. Pin Diagram - 16 Pin COL Table 1. Pin Definitions - 16 Pin COL Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I Name GP0[0] GP0[1] 2C Description Configurable as CapSense or GPIO Configurable as CapSense or GPIO I2C clock I2C data Configurable as CapSense or GPIO Configurable as CapSense or GPIO Ground connection Configurable as CapSense or GPIO Configurable as CapSense or GPIO Configurable as Capsense or GPIO Active HIGH external reset with internal pull down Configurable as CapSense or GPIO Supply voltage Configurable as CapSense or GPIO Integrating Capacitor Input. The external capacitance is required only if 5:1 SNR cannot be achieved. Typical range is 10-100 nF. Configurable as CapSense or GPIO SCL I2C SDA GP1[0] GP1[1] VSS GP1[2] GP1[3] GP1[4] XRES GP0[2] VDD GP0[3] CSInt GP0[4] Document Number: 001-17345 Rev. *B Page 3 of 12 [+] Feedback CY8C20110 Figure 2. Pin Diagram - 16 Pin SOIC GP0[3] CSInt GP0[4] GP0[0] GP0[1] I2CSCL I2CSDA GP1[0] 1 2 3 4 5 6 7 8 16 15 14 VDD GP0[2] XRES GP1[4] GP1[3] GP1[2] VSS GP1[1] SOIC (Top View) 13 12 11 10 9 Table 2. Pin Definitions - 16 Pin SOIC Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name GP0[3] CSInt GP0[4] GP0[0] GP0[1] I2C SCL I2C SDA GP1[0] GP1[1] VSS GP1[2] GP1[3] GP1[4] XRES GP0[2] VDD Description Configurable as CapSense or GPIO Integrating Capacitor Input.The external capacitance is required only if 5:1 SNR cannot be achieved. Typical range is 10-100 nF. Configurable as CapSense or GPIO Configurable as CapSense or GPIO Configurable as CapSense or GPIO I2C clock I2C data Configurable as CapSense or GPIO Configurable as CapSense or GPIO Ground connection Configurable as CapSense or GPIO Configurable as CapSense or GPIO Configurable as CapSense or GPIO Active HIGH external reset with internal pull down. Configurable as CapSense or GPIO Supply voltage Document Number: 001-17345 Rev. *B Page 4 of 12 [+] Feedback CY8C20110 The CapSense Analog System The CapSense analog system contains the capacitive sensing hardware which supports CapSense Successive Approximation (CSA) algorithm. This hardware performs capacitive sensing and scanning without external components. Capacitive sensing is configurable on each pin. I2C Interface The two modes of operation for the I2C interface are: ■ ■ Device register configuration and status read or write for controller Command execution Additional System Resources System Resources provide additional capability useful to complete systems. Additional resources are low voltage detection and Power On Reset (POR). ■ ■ The I2C address is programmable during configuration. It can be locked to prevent accidental change by setting a flag in a configuration register. CapSense Express Software Tool An easy to use software tool integrated with PSoC Express is available for configuring and tuning CapSense Express devices. Refer to the Application Note AN42137 for details of the software tool. The I C slave provides 50, 100, or 400 kHz communication over two wires. Low Voltage Detection (LVD) interrupts signal the application of falling voltage levels and the advanced POR circuit eliminates the need for a system supervisor. 2 CapSense Express Register Map CapSense Express supports user configurable registers through which the device functionality and parameters are configured. For details, refer to CY8C201xx Register Reference document. An internal 1.8V reference provides a stable internal reference so that capacitive sensing functionality is not affected by minor VDD changes. Electrical Specifications Absolute Maximum Ratings Parameter TSTG Description Storage temperature Min –55 Typ 25 Max +100 Unit °C Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is +25°C ± 25°C (0°C to 50°C). Extended duration storage temperatures above 65°C degrades reliability. TA VDD VIO VIOZ IMIO ESD LU Ambient temperature with power applied Supply voltage on VDD relative to VSS DC input voltage DC voltage applied to tri-state Maximum current into any GPIO pin Electrostatic discharge voltage Latch up current –40 –0.5 VSS – 0.5 VSS – 0.5 –25 2000 - – – – – – – – +85 +6.0 VDD + 0.5 VDD + 0.5 +50 200 °C V V V mA V mA Human body model ESD Operating Temperature Parameter TA TJ Description Ambient temperature Junction temperature Min –40 –40 Typ – – Max +85 +100 Unit ºC ºC Notes Document Number: 001-17345 Rev. *B Page 5 of 12 [+] Feedback CY8C20110 DC Electrical Characteristics DC Chip Level Specifications Parameter VDD IDD ISB ISB ISB Description Supply voltage Supply current Sleep mode current with POR and LVD active. Mid temperature range Sleep mode current with POR and LVD active. Sleep mode current with POR and LVD active. Min 2.40 – – – – Typ – 1.5 2.6 2.8 5.2 Max 5.25 2.5 4 5 6.4 Unit V mA µA µA µA Conditions are VDD = 3.0V, TA = 25°C VDD = 2.55V, 0°C < TA < 40°C VDD = 3.3V, –40°C < TA < 85°C VDD = 5.25V, –40°C < TA < 85°C Notes 5V and 3.3V DC General Purpose IO Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C 3.0V, maximum of 20 mA source current in all IOs. IOH < 10 µA, VDD > 3.0V, maximum of 10 mA source current in all IOs. IOH = 5 mA, VDD > 3.0V, maximum of 20 mA source current in all IOs. IOH < 10 µA, VDD > 3.1V, maximum of 4 IOs all sourcing 5mA. IOH = 5 mA, VDD > 3.1V, maximum of 20 mA source current in all IOs. IOH < 10 µA, VDD > 3.0V, maximum of 20 mA source current in all IOs. IOH < 200 µA,VDD > 3.0V, maximum of 20 mA source current in all IOs. IOL = 20 mA, VDD > 3V, maximum of 60 mA sink current on even port pins and 60 mA sink current on odd port pins VDD = 3 to 3.6V VDD = 3 to 3.6V VDD = 3.6 to 5.25V VDD = 3.6 to 5.25V Gross tested to 1 µA. Notes VOH6 2.2 – – V VOL – – 0.75 V VIL VIH VIL VIH VH IIL Input low voltage Input high voltage Input low voltage Input high voltage Input hysteresis voltage Input leakage – 1.6 – 2.0 – – – – – – 140 1 0.75 – 0.8 – – – V V V V mV nA Document Number: 001-17345 Rev. *B Page 6 of 12 [+] Feedback CY8C20110 5V and 3.3V DC General Purpose IO Specifications (continued) This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C