CY8C20110_0809

CY8C20110 CapSense Express™-10 Configurable GPIOs with PWM Control Features ■ Overview The CapSense ExpressTM controller allows the control of 10 IOs configurable as capacitive sensing buttons or as GPIOs for driving LEDs or interrupt signals based on various button conditions. The CY8C20110 is optimized for dimming LEDs in 15 selectable duty cycles for back light applications. The device can be configured to have up to 10 GPIOs connected to the PWM output. The PWM duty cycle is programmable for variable LED intensities. The user has the ability to configure buttons, outputs, and parameters through specific commands sent to the I2C port. The IOs have the flexibility of mapping to capacitive buttons and as standard GPIO functions such as interrupt output or input, LED drive, and digital mapping of input to output using simple logical operations. This enables easy PCB trace routing and reduces the PCB size and stack up. CapSense Express products are designed for easy integration into complex products. 10 configurable IOs supporting ❐ CapSenseTM buttons ❐ LED drive ❐ All GPIOs support LED dimming with configurable delay option ❐ Interrupt outputs. ❐ WAKE on interrupt input ❐ Bi-directional sleep control pin ❐ User defined input or output 2.4V to 3.6V and 4.75V to 5.25V operating voltage Industrial temperature range: –40°C to +85°C I2C slave interface for configuration and communication ❐ I2C data transfer rate up to 400 kbps Reduce BOM cost ❐ Internal oscillator - no external oscillators or crystal ❐ Free development tool - no external tuning components Low operating current ❐ Active current: continuous sensor scan: 1.5 mA ❐ Deep sleep current: 4 uA Available in 16-pin COL and 16-pin SOIC packages ■ ■ ■ ■ Architecture The logic block diagram illustrates the internal architecture of CY8C20110. The user is able to configure registers with parameters needed to adjust the operation and sensitivity of the CapSense system. CY8C20110 supports a standard I2C serial communication interface that allows the host to configure the device and to read sensor information in real time through easy register access. ■ ■ The CapSense Express Core The CapSense Express Core has a powerful configuration and control block. It encompasses SRAM for data storage, an interrupt controller, along with sleep and watchdog timers. System resources provide additional capability, such as a configurable I2C slave communication interface and various system resets. The Analog system contains the CapSense PSoC block which supports capacitive sensing of up to 10 inputs. Cypress Semiconductor Corporation Document Number: 001-17345 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised September 06, 2008 [+] Feedback CY8C20110 Logic Block Diagram External Vcc 2.4 - 5.25V CapSense ExpressTM Core 10 Configurable IOs with PWM Control SYSTEM BUS 512B SRAM Interrupt Controller 2KB Flash Configuration and Control Engine Sleep and Watchdog Clock Sources (Internal Main Oscillator) SYSTEM BUS CapSense Block I2C Slave Voltage and Current Reference System Resets POR/ LVD Document Number: 001-17345 Rev. *E Page 2 of 18 [+] Feedback CY8C20110 Pinouts Figure 1. Pin Diagram - 16 Pin COL COL (TOP VIEW) Table 1. Pin Definitions - 16 Pin COL Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name GP0[0] GP0[1] I2C SCL I2C SDA GP1[0] GP1[1] VSS GP1[2] GP1[3] GP1[4] XRES GP0[2] VDD GP0[3] CSInt GP0[4] Description Configurable as CapSense or GPIO Configurable as CapSense or GPIO I2C clock I2C data Configurable as CapSense or GPIO Configurable as CapSense or GPIO Ground connection Configurable as CapSense or GPIO Configurable as CapSense or GPIO Configurable as Capsense or GPIO Active HIGH external reset with internal pull down Configurable as CapSense or GPIO Supply voltage Configurable as CapSense or GPIO Integrating Capacitor Input. The external capacitance is required only if 5:1 SNR cannot be achieved. Typical range is 10-100 nF Configurable as CapSense or GPIO Document Number: 001-17345 Rev. *E Page 3 of 18 [+] Feedback CY8C20110 Figure 2. Pin Diagram - 16 Pin SOIC GP0[3] CSInt GP0[4] GP0[0] GP0[1] I2CSCL I2CSDA GP1[0] Table 2. Pin Definitions - 16 Pin SOIC Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name GP0[3] CSInt GP0[4] GP0[0] GP0[1] I 2C 1 2 3 4 5 6 7 8 16 15 14 VDD GP0[2] XRES GP1[4] GP1[3] GP1[2] VSS GP1[1] SOIC (Top View) 13 12 11 10 9 Description Configurable as CapSense or GPIO Integrating Capacitor Input.The external capacitance is required only if 5:1 SNR cannot be achieved. Typical range is 10-100 nF. Configurable as CapSense or GPIO Configurable as CapSense or GPIO Configurable as CapSense or GPIO I2C clock I2C data Configurable as CapSense or GPIO Configurable as CapSense or GPIO Ground connection Configurable as CapSense or GPIO Configurable as CapSense or GPIO Configurable as CapSense or GPIO Active HIGH external reset with internal pull down. Configurable as CapSense or GPIO Supply voltage SCL I2C SDA GP1[0] GP1[1] VSS GP1[2] GP1[3] GP1[4] XRES GP0[2] VDD Document Number: 001-17345 Rev. *E Page 4 of 18 [+] Feedback CY8C20110 The CapSense Analog System The CapSense analog system contains the capacitive sensing hardware which supports CapSense Successive Approximation (CSA) algorithm. This hardware performs capacitive sensing and scanning without external components. Capacitive sensing is configurable on each pin. CapSense Express Software Tool An easy to use software tool integrated with PSoC Express is available for configuring and tuning CapSense Express devices. Refer to the Application Note “CapSense (TM) Express Software Tool - AN42137” for details of the software tool. Additional System Resources System Resources provide additional capability useful to complete systems. Additional resources are low voltage detection and Power On Reset (POR). ■ ■ CapSense Express Register Map CapSense Express supports user configurable registers through which the device functionality and parameters are configured. For details, refer to “CY8C201xx Register Reference Guide” document. The I2C slave provides 50, 100, or 400 kHz communication over two wires. Low Voltage Detection (LVD) interrupts signal the application of falling voltage levels and the advanced POR circuit eliminates the need for a system supervisor. LED Dimming To change the brightness and intensity of the LEDs, the host master (MCU, MPU, DSP, and so on) must send I2C commands and program the PWM registers to enable output pins, set duty cycle, and mode configuration. The single PWM source is connected to all GPIO pins and have a common user defined duty cycle. Each PWM enabled pin has two possible outputs: PWM and 0/1 (depending on the configuration). Four different modes of LED dimming are possible, as shown in Figure 3 to Figure 6. The operation mode of the PWM enabled pins is common. This means that one pin cannot behave as in Mode1 and another pin as in Mode 2. An internal 1.8V reference provides a stable internal reference so that capacitive sensing functionality is not affected by minor VDD changes. I2C Interface The two modes of operation for the I2C interface are: ■ ■ Device register configuration and status read or write for controller Command execution The I2C address is programmable during configuration. It is locked to prevent accidental change by setting a flag in a configuration register. Document Number: 001-17345 Rev. *E Page 5 of 18 [+] Feedback CY8C20110 Figure 3. LED Dimming Mode 1: Change Intensity on ON/OFF Button Status Document Number: 001-17345 Rev. *E Page 6 of 18 [+] Feedback CY8C20110 Figure 4. LED Dimming Mode 2: Flash Intensity on ON Button Status Figure 5. LED Dimming Mode 3: Hold Intensity After ON→OFF Button Transition Document Number: 001-17345 Rev. *E Page 7 of 18 [+] Feedback CY8C20110 Figure 6. LED Dimming Mode 4: Toggle Intensity on ON→OFF or OFF→ON Button Transitions Modes of Operation CapSense Express devices are configured to operate in any of the following three modes to meet different power consumption requirements: ■ ■ ■ Deep Sleep Mode Deep sleep mode provides the lowest power consumption because there is no operation running. In this mode, the device is woken up only using an external GPIO interrupt. A sleep timer interrupt cannot wake up a device from deep sleep mode. This is treated as a continuous sleep mode without periodic wakeups. Refer to the Application Note “CapSense Express Power and Sleep Considerations - AN44209” for details on different sleep modes. Active Mode Sleep Mode Deep Sleep Mode Bi-Directional Sleep Control Pin The CY8C20110 requires a dedicated sleep control pin to allow reliable I2C communication in case any sleep mode is enabled. This is achieved by pulling the sleep control pin LOW to wake up the device and start I2C communication. The sleep control pin is configured on any of the GPIO. If sleep control feature is enabled, the device have one less GPIO available for CapSense/GPIO functions. The sleep control pin can also be configured as interrupt output pin from CY8C20110 to the host to acknowledge finger press on any button. Active Mode In the active mode, all the device blocks including the CapSense sub system are powered. Typical active current consumption of the device across the operating voltage range is 1.5 mA Sleep Mode Sleep mode provides an intermediate power operation mode. It is enabled by configuring the corresponding device register. When enabled, the device enters sleep mode and wakes up after a specified sleep interval. It scans the capacitive sensors before going back to sleep again. The device can also wake up from sleep mode with a GPIO interrupt. The following sleep intervals are supported in CapSense Express. The sleep interval is configured through registers. ■ ■ ■ ■ 1.95 ms (512 Hz) 15.6 ms (64 Hz) 125 ms (8 Hz) 1s (1 Hz) Document Number: 001-17345 Rev. *E Page 8 of 18 [+] Feedback CY8C20110 Electrical Specifications Absolute Maximum Ratings Parameter TSTG Description Storage temperature Min –55 Typ 25 Max +100 Unit °C Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is +25°C ± 25°C (0°C to 50°C). Extended duration storage temperatures above 65°C degrades reliability. TA VDD VIO VIOZ IMIO ESD LU Ambient temperature with power applied Supply voltage on VDD relative to VSS DC input voltage DC voltage applied to tri-state Maximum current into any GPIO pin Electrostatic discharge voltage Latch up current –40 –0.5 VSS – 0.5 VSS – 0.5 –25 2000 - – – – – – – – +85 +6.0 VDD + 0.5 VDD + 0.5 +50 200 °C V V V mA V mA Human body model ESD Operating Temperature Parameter TA TJ Description Ambient temperature Junction temperature Min –40 –40 Typ – – Max +85 +100 Unit ºC ºC Notes DC Electrical Characteristics DC Chip Level Specifications Parameter VDD IDD ISB ISB ISB Description Supply voltage Supply current Deep Sleep mode current with POR and LVD active. Deep Sleep mode current with POR and LVD active. Deep Sleep mode current with POR and LVD active. Min 2.40 – – – – Typ – 1.5 2.6 2.8 5.2 Max 5.25 2.5 4 5 6.4 Unit V mA µA µA µA Conditions are VDD = 3.0V, TA = 25°C VDD = 2.55V, 0°C < TA < 40°C VDD = 3.3V, –40°C < TA < 85°C VDD = 5.25V, –40°C < TA < 85°C Notes Document Number: 001-17345 Rev. *E Page 9 of 18 [+] Feedback CY8C20110 5V and 3.3V DC General Purpose IO Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C 3.0V, maximum of 20 mA source current in all IOs. IOH < 10 µA, VDD > 3.0V, maximum of 10 mA source current in all IOs. IOH = 5 mA, VDD > 3.0V, maximum of 20 mA source current in all IOs. IOH < 10 µA, VDD > 3.1V, maximum of 4 IOs all sourcing 5mA. IOH = 5 mA, VDD > 3.1V, maximum of 20 mA source current in all IOs. IOH < 10 µA, VDD > 3.0V, maximum of 20 mA source current in all IOs. IOH < 200 µA,VDD > 3.0V, maximum of 20 mA source current in all IOs. IOL = 20 mA, VDD > 3V, maximum of 60 mA sink current on even port pins and 60 mA sink current on odd port pins VDD = 3 to 3.6V VDD = 3 to 3.6V VDD = 4.75V to 5.25V VDD = 4.75V to 5.25V Gross tested to 1 µA. Package and pin dependent. Temp = 25°C Package and pin dependent. Temp = 25°C Notes VOH6 2.2 – – V VOL – – 0.75 V VIL VIH VIL VIH VH IIL CIN COUT Input low voltage Input high voltage Input low voltage Input high voltage Input hysteresis voltage Input leakage Capacitive load on pins as input Capacitive load on pins as output – 1.6 – 2.0 – – 0.5 0.5 – – – – 140 1 1.7 1.7 0.75 – 0.8 – – – 5 5 V V V V mV nA pF pF Document Number: 001-17345 Rev. *E Page 10 of 18 [+] Feedback CY8C20110 2.7V DC General Purpose IO Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4V to 3.0V and -40°C