CY8C20110_09

CY8C20110/CY8C20180/CY8C20160 CY8C20140/CY8C20142 CapSense® Express™ Button Capacitive Controllers Features ■ ■ 10/8/6/4 Capacitive Button Input ❐ Robust sensing algorithm ❐ High sensitivity, low noise ❐ Immunity to RF and AC noise ❐ Low radiated EMC noise ❐ Supports wide range of input capacitance, sensor shapes, and sizes Target Applications ❐ Printers ❐ Cellular handsets ❐ LCD monitors ❐ Portable DVD players Low Operating Current ❐ Active current: continuous sensor scan: 1.5 mA ❐ Deep sleep current: 4 uA Industry's Best Configurability ❐ Custom sensor tuning, one optional capacitor ❐ Output supports strong drive for LED 2 ❐ Output state can be controlled through I C or directly from ® input state CapSense 2 ❐ Run time re-configurable over I C Advanced Features ❐ All GPIOs support LED dimming with configurable delay option in CY8C21110 ❐ Interrupt outputs ❐ User defined Inputs ❐ Wake on interrupt input ❐ Sleep control pin ❐ Nonvolatile storage of custom settings ❐ Easy integration into existing products – configure output to match system ❐ No external components required ❐ World class free configuration tool Wide Range of Operating Voltages ❐ 2.4V to 2.9V ❐ 3.10V to 3.6V ❐ 4.75V to 5.25V I2C Communication ❐ Supported from 1.8V ❐ Internal pull up resistor support option ❐ Data rate up to 400 kbps 2 ❐ Configurable I C addressing Industrial temperature range: –40°C to +85°C. Available in16-pin COL, 8-pin, and 16-pin SOIC Packages ■ ■ ■ ■ Overview These CapSense Express™ controllers support 4 to 10 capacitive sensing (CapSense buttons). The device functionality is configured through an I2C port and can be stored in onboard nonvolatile memory for automatic loading at power on. The CY8C20110 is optimized for dimming LEDs in 15 selectable duty cycles for back light applications. The device can be configured to have up to 10 GPIOs connected to the PWM output. The PWM duty cycle is programmable for variable LED intensities. The four key blocks that make up these devices are: a robust capacitive sensing core with high immunity against radiated and conductive noise, control registers with nonvolatile storage, configurable outputs, and I2C communications. The user can configure registers with parameters needed to adjust the operation and sensitivity of the CapSense buttons and outputs and permanently store the settings. The standard I2C serial communication interface enables the host to configure the device and read sensor information in real time. The I2C address is fully configurable without any external hardware strapping. ■ ■ ■ Cypress Semiconductor Corporation Document Number: 001-54606 Rev. ** • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 12, 2009 [+] Feedback CY8C20110/CY8C20180/CY8C20160 CY8C20140/CY8C20142 Pinouts Figure 1. Pin Diagram - 16 COL- CY8C20110 (10 Buttons)/CY8C20180 (8 Buttons) CY8C20160 (6 Buttons)/CY8C20140 (4 Buttons)   Table 1. Pin Definitions – 16 COL- CY8C20110 (10 Buttons)/CY8C20180 (8 Buttons) CY8C20160 (6 Buttons)/CY8C20140 (4 Buttons)[1] Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name GP0[0] GP0[1] I2C SCL I2C SDA GP1[0] GP1[1] VSS GP1[2] GP1[3] GP1[4] XRES GP0[2] VDD GP0[3] CSInt GP0[4] Description Configurable as CapSense or GPIO Configurable as CapSense or GPIO I2C Clock I2C Data Configurable as CapSense or GPIO Configurable as CapSense or GPIO Ground Connection Configurable as CapSense or GPIO Configurable as CapSense or GPIO Configurable as CapSense or GPIO Active high external reset with internal pull up Configurable as CapSense or GPIO Supply voltage Configurable as CapSense or GPIO Integrating Capacitor Input. The external capacitance is required only if 5:1 SNR cannot be achieved. Typical range is 1 nF to 4.7 nF Configurable as CapSense or GPIO Note 1. 8/6/4 available configurable IOs can be configured to any of the 10 IOs of the package. After any of the 8/6/4 IOs are chosen, the remaining 2/4/6 IOs of the package are not available for any functionality. Document Number: 001-54606 Rev. ** Page 2 of 29 [+] [+] Feedback CY8C20110/CY8C20180/CY8C20160 CY8C20140/CY8C20142 Figure 2. Pin Diagram – 16 SOIC– CY8C20110 (10 Buttons)/CY8C20180 (8 Buttons) CY8C20160 (6 Buttons)/CY8C20140 (4 Buttons)   Table 2. Pin Definitions – 16 SOIC– CY8C20110 (10 Buttons)/CY8C20180 (8 Buttons) CY8C20160 (6 Buttons)/CY8C20140 (4 Buttons)1] Pin No 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name GP0[3] CSint GP0[4] GP0[0] GP0[1] I2C SCL I2C SDA GP1[0] GP1[1] VSS GP1[2] GP1[3] GP1[4] XRES GP0[2] VDD Description Configurable as CapSense or GPIO Integrating Capacitor Input. The external capacitance is required only if 5:1 SNR cannot be achieved. Typical range is 1 nF to 4.7 nF Configurable as CapSense or GPIO Configurable as CapSense or GPIO Configurable as CapSense or GPIO I2C Clock I2C Data Configurable as CapSense or GPIO Configurable as CapSense or GPIO Ground Connection Configurable as CapSense or GPIO Configurable as CapSense or GPIO Configurable as CapSense or GPIO Active high external reset with internal pull up Configurable as CapSense or GPIO Supply voltage Document Number: 001-54606 Rev. ** Page 3 of 29 [+] [+] Feedback CY8C20110/CY8C20180/CY8C20160 CY8C20140/CY8C20142 Figure 3. Pin Diagram - 8-Pin SOIC- CY8C20142 (4 Button)   Table 3. Pin Definitions - 8-Pin SOIC - CY8C20142 (4 Button) Pin No 1 2 3 4 5 6 7 8 Name VSS I2C SCL I2C SDA GP1[0] GP1[1] GP0[0] GP0[1] VDD Ground I2C Clock I2C Data Configurable as CapSense or GPIO Configurable as CapSense or GPIO Configurable as CapSense or GPIO Configurable as CapSense or GPIO Supply voltage Description Document Number: 001-54606 Rev. ** Page 4 of 29 [+] [+] Feedback CY8C20110/CY8C20180/CY8C20160 CY8C20140/CY8C20142 Typical Circuits Circuit-1: Five Button and Five LED with I2C Interface   Circuit 2 - Two Buttons and Two LEDs with I2C Interface   Document Number: 001-54606 Rev. ** Page 5 of 29 [+] [+] Feedback CY8C20110/CY8C20180/CY8C20160 CY8C20140/CY8C20142 Circuit 3 - Compatibility with 1.8V I2C Signaling   Note 1.8V ≤ VDD_I2C ≤ VDD_CE and 2.4V ≤ VDD_CE ≤ 5.25V Circuit 4 - Powering Down CapSense Express Device for Low Power Requirements Output enable LDO Output VDD LED I2C Pull UPs Master Or Host CapSense Express SDA I2C BUS SCL For low power requirements, if Vdd is to be turned off, this concept can be used. The requirement is that the Vdds of CapSense Express, I2C pull ups, and LEDs should be from the same source such that turning off the Vdd ensures that no signal is applied to the device while it is unpowered. The I2C signals should not be driven high by the master in this situation. If a port pin or group of port pins of the master can cater to the power supply requirements of the circuit, the LDO can be avoided. Document Number: 001-54606 Rev. ** Page 6 of 29 [+] [+] Feedback CY8C20110/CY8C20180/CY8C20160 CY8C20140/CY8C20142 I2C Interface The CapSense Express devices support the industry standard I2C protocol, which can be used for: ■ ■ ■ ■ Configuring the device Reading the status and data registers of the device Controlling device operation Executing commands The I2C address can be modified during configuration. I C Device Addressing The device uses a seven bit addressing protocol. The I2C data transfer is always initiated by the master sending a one byte address: the first 7 bits contain the address and the LSB indicates the data transfer direction. Zero in the LSB bit indicates the write transaction from master and one indicates read transfer by the master. The following table shows examples for different I2C addresses. Table 4. I2C Address Examples 7 Bit Slave Address 1 1 75 75 D7 0 0 1 1 D6 0 0 0 0 D5 0 0 0 0 D4 0 0 1 1 D3 0 0 0 0 D2 0 0 1 1 D1 1 1 1 1 D0 0(W) 1(R) 0(W) 1(W) 8 Bit Slave Address 02 03 96 97 2 I2C Clock Stretching ‘Clock stretching’ or ‘bus stalling’ in communication protocol is a state in which the slave holds the SCL line low to indicate that it is busy. In this condition, the master is expected to wait till the SCL is released by the slave. When an I2C master communicates with the CapSense Express device, the CapSense Express stalls the I2C bus after the reception of each byte (that is, just before the ACK/NAK bit) until processing of the byte is complete and critical internal functions are executed. Use a fully I2C compliant master to communicate with the CapSense Express device. I2C If the I2C master does not support clock stretching (a bit banged software I2C Master), the master must wait for a specific amount of time (as specified in “Format for Register Write and Read” on page 8) for each register write and read operation before the next bit is transmitted. The I2C master must check the SCL status (it should be high) before the I2C master initiates any data transfer with CapSense Express. If the master fails to do so and continues to communicate, the communication is erroneous. The following diagrams represent the ACK time delays shown in “Format for Register Write and Read” on page 8 for write and read. Document Number: 001-54606 Rev. ** Page 7 of 29 [+] [+] Feedback CY8C20110/CY8C20180/CY8C20160 CY8C20140/CY8C20142 Figure 4. Write ACK Time Representation[2] Figure 5. Read ACK Time Representation[3] Format for Register Write and Read Register write format Start Slave Addr + W Register read format Start Slave Addr + W Start Slave Addr + R Legends: Master Slave A - ACK N- NAK A A A Reg Addr Reg Addr Data A A A Data Stop Data A Data A ..... Data A Stop A ..... Data N Stop Notes 2. Time to process the received data 3. Time taken for the device to send next byte Document Number: 001-54606 Rev. ** Page 8 of 29 [+] [+] Feedback CY8C20110/CY8C20180/CY8C20160 CY8C20140/CY8C20142 Operating Modes of I2C Commands Normal Mode In normal mode of operation, the acknowledgment time is optimized. The timings remain approximately the same for different configurations of the slave. To reduce the acknowledgment times in normal mode, the registers 0x06-0x09, 0x0C, 0x0D, 0x10-0x17, 0x50, 0x51, 0x57-0x60, 0x7E are given only read access. Write to these registers can be done only in setup mode. Deep Sleep Mode Deep sleep mode provides the lowest power consumption because there is no operation running. All CapSense scanning is disabled during this mode. In this mode, the device wakes up only using an external GPIO interrupt. A sleep timer interrupt cannot wake up a device from deep sleep mode. This is treated as a continuous sleep mode without periodic wakeups. Refer to the application note CapSense Express Power and Sleep Considerations - AN44209 for details on different sleep modes. To get the lowest power during this mode the sleep timer frequency should be set to 1 Hz. Setup Mode All registers have read and write access (except those which are read only) in this mode. The acknowledgment times are longer compared to normal mode. When CapSense scanning is disabled (command code 0x0A in command register 0xA0), the acknowledgment times can be improved to values similar to the normal mode of operation. Sleep Control Pin The devices require a dedicated sleep control pin to enable reliable I2C communication in case any sleep mode is enabled. This is achieved by pulling the sleep control pin low to wake up the device and start I2C communication. The sleep control pin can be configured on any GPIO. Device Operation Modes CapSense Express devices are configured to operate in any of the following three modes to meet different power consumption requirements: ■ ■ ■ Interrupt Pin to Master To inform the master of any button press a GPIO can be configured as interrupt output and all CapSense buttons can be connected to this GPIO with an OR logic operator. This can be configured using the software tool. Active Mode Periodic Sleep Mode Deep Sleep Mode LED Dimming To change the brightness and intensity of the LEDs, the host master (MCU, MPU, DSP, and so on) must send I2C commands and program the PWM registers to enable output pins, set duty cycle, and mode configuration. The single PWM source is connected to all GPIO pins and has a common user defined duty cycle. Each PWM enabled pin has two possible outputs: PWM and 0/1 (depending on the configuration). Four different modes of LED dimming are possible, as shown in “LED Dimming Mode 1: Change Intensity on ON/OFF Button Status” on page 10 to “LED Dimming Mode 4: Toggle Intensity on ON/OFF or OFF/ON Button Transitions” on page 11. The operation mode and duty cycle of the PWM enabled pins is common. This means that one pin cannot behave as in Mode1 and another pin as in Mode 2. Active Mode In the active mode, all the device blocks including the CapSense sub system are powered. Typical active current consumption of the device across the operating voltage range is 1.5 mA. Periodic Sleep Mode Sleep mode provides an intermediate power operation mode. It is enabled by configuring the corresponding device registers (0x7E, 0x7F). The device goes into sleep after there is no event for stay awake counter (Reg 0x80) number of sleep intervals. The device wakes up on sleep interval and It scans the capacitive sensors before going back to sleep again. If any sensor is active, then the device wakes up. The device can also wake up from sleep mode with a GPIO interrupt. The following sleep intervals are supported in CapSense Express. The sleep interval is configured through registers. ■ ■ ■ ■ 1.95 ms (512 Hz) 15.6 ms (64 Hz) 125 ms (8 Hz) 1s (1 Hz) Document Number: 001-54606 Rev. ** Page 9 of 29 [+] [+] Feedback CY8C20110/CY8C20180/CY8C20160 CY8C20140/CY8C20142 LED Dimming Mode 1: Change Intensity on ON/OFF Button Status   LED Dimming Mode 2: Flash Intensity on ON Button Status   Document Number: 001-54606 Rev. ** Page 10 of 29 [+] [+] Feedback CY8C20110/CY8C20180/CY8C20160 CY8C20140/CY8C20142 LED Dimming Mode 3: Hold Intensity After ON/OFF Button Transition   LED Dimming Mode 4: Toggle Intensity on ON/OFF or OFF/ON Button Transitions   Note LED DIMMING is available only in CY8C20110. Document Number: 001-54606 Rev. ** Page 11 of 29 [+] [+] Feedback CY8C20110/CY8C20180/CY8C20160 CY8C20140/CY8C20142 Register Map Name Register Address (in Hex) Access Writable Only in SETUP Mode[4] Factory Default Values I2C Max ACK Time in I2C Max ACK Time of Registers Normal Mode (ms) in Setup Mode (ms) (in Hex) INPUT_PORT0 INPUT_PORT1 STATUS_POR0 STATUS_POR1 OUTPUT_PORT0 OUTPUT_PORT1 CS_ENABL0 CS_ENABLE GPIO_ENABLE0 GPIO_ENABLE1 INVERSION_MASK0 INVERSION_MASK1 INT_MASK0 INT_MASK1 STATUS_HOLD_MSK0 STATUS_HOLD_MSK1 DM_PULL_UP0 DM_STRONG0 DM_HIGHZ0 DM_OD_LOW0 DM_PULL_UP1 DM_STRONG1 DM_HIGHZ1 DM_OD_LOW1 PWM_ENABLE0[8] PWM_ENABLE1[8] PWM_MODE_DC[8] PWM_DELAY[8] OP_SEL_00 OPR1_PRT0_00 OPR1_PRT1_00 OPR2_PRT0_00 OPR2_PRT1_00 OP_SEL_01 OPR1_PRT0_01 OPR1_PRT1_01 OPR2_PRT0_01 OPR2_PRT1_01 OP_SEL_02 OPR1_PRT0_02 OPR1_PRT1_02 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 R R R R W W RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW YES YES YES YES YES YES YES YES YES YES YES YES YES YES 00 00 00 00 00 00 00 00 00 00 00 00 00 00 03/1F[5] 03/1F[5] 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 0.1 0.1 0.1 0.1 0.1 0.1 11 11 11 11 0.11 0.11 11 11 0.11 0.11 11 11 11 11 11 11 11 11 0.1 0.1 0.1 0.1 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 11 11 11 11 11 11 11 11 11 11 11 11 11 Document Number: 001-54606 Rev. ** Page 12 of 29 [+] Feedback CY8C20110/CY8C20180/CY8C20160 CY8C20140/CY8C20142 Register Map (continued) Name Register Address (in Hex) Access Writable Only in SETUP Mode[4] Factory Default Values I2C Max ACK Time in I2C Max ACK Time of Registers Normal Mode (ms) in Setup Mode (ms) (in Hex) OPR2_PRT0_02 OPR2_PRT1_02 OP_SEL_03 OPR1_PRT0_03 OPR1_PRT1_03 OPR2_PRT0_03 OPR2_PRT1_03 OP_SEL_04 OPR1_PRT0_04 OPR1_PRT1_04 OPR2_PRT0_04 OPR2_PRT1_04 OP_SEL_10 OPR1_PRT0_10 OPR1_PRT1_10 OPR2_PRT0_10 OPR2_PRT1_10 OP_SEL_11 OPR1_PRT0_11 OPR1_PRT1_11 OPR2_PRT0_11 OPR2_PRT1_11 OP_SEL_12 OPR1_PRT0_12 OPR1_PRT1_12 OPR2_PRT0_12 OPR2_PRT1_12 OP_SEL_13 OPR1_PRT0_13 OPR1_PRT1_13 OPR2_PRT0_13 OPR2_PRT1_13 OP_SEL_14 OPR1_PRT0_14 OPR1_PRT1_14 OPR2_PRT0_14 OPR2_PRT1_14 CS_NOISE_TH CS_BL_UPD_TH CS_SETL_TIME CS_OTH_SET CS_HYSTERISIS 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW YES YES 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 28 64 A0 00 0A 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.11 0.11 0.11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 35 35 11 Document Number: 001-54606 Rev. ** Page 13 of 29 [+] [+] Feedback CY8C20110/CY8C20180/CY8C20160 CY8C20140/CY8C20142 Register Map (continued) Name Register Address (in Hex) Access Writable Only in SETUP Mode[4] Factory Default Values I2C Max ACK Time in I2C Max ACK Time of Registers Normal Mode (ms) in Setup Mode (ms) (in Hex) CS_DEBOUNCE CS_NEG_NOISE_TH CS_LOW_BL_RST CS_FILTERING CS_SCAN_POS_00 CS_SCAN_POS_01 CS_SCAN_POS_02 CS_SCAN_POS_03 CS_SCAN_POS_04 CS_SCAN_POS_10 CS_SCAN_POS_11 CS_SCAN_POS_12 CS_SCAN_POS_13 CS_SCAN_POS_14 CS_FINGER_TH_00 CS_FINGER_TH_01 CS_FINGER_TH_02 CS_FINGER_TH_03 CS_FINGER_TH_04 CS_FINGER_TH_10 CS_FINGER_TH_11 CS_FINGER_TH_12 CS_FINGER_TH_13 CS_FINGER_TH_14 CS_IDAC_00 CS_IDAC_01 CS_IDAC_02 CS_IDAC_03 CS_IDAC_04 CS_IDAC_10 CS_IDAC_11 CS_IDAC_12 CS_IDAC_13 CS_IDAC_14 I2C_ADDR_LOCK DEVICE_ID DEVICE_STATUS I2C_ADDR_DM 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75[6] 76[6] 77[6] 78[6] 79 7A 7B 7C RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW YES YES YES YES YES YES YES YES YES YES 03 14 14 20 FF FF FF FF FF FF FF FF FF FF 64 64 64 64 64 64 64 64 64 64 0A 0A 0A 0A 0A 0A 0A 0A 0A 0A 0.11 0.11 0.11 0.11 0.14 0.14 0.14 0.14 0.14 0.14 0.14 0.14 0.14 0.14 0.14 0.14 0.14 0.14 0.14 0.14 0.14 0.14 0.14 0.14 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 RW R R RW 01 42/40/60/80/10[7] 03 00 0.11 0.11 0.11 0.11 11 11 11 11 Document Number: 001-54606 Rev. ** Page 14 of 29 [+] [+] Feedback CY8C20110/CY8C20180/CY8C20160 CY8C20140/CY8C20142 Register Map (continued) Name Register Address (in Hex) Access Writable Only in SETUP Mode[4] Factory Default Values I2C Max ACK Time in I2C Max ACK Time of Registers Normal Mode (ms) in Setup Mode (ms) (in Hex) SLEEP_PIN SLEEP_CTRL SLEEP_SA_CNTR CS_READ_BUTTON CS_READ_BLM CS_READ_BLL CS_READ_DIFFM CS_READ_DIFFL CS_READ_RAWM CS_READ_RAWL CS_READ_STATUSM CS_READ_STATUSL COMMAND_REG 7D[6] 7E 7F 80 81 82 83 84 85 86 87 88 89 8A[6] 8B[6] 8C[6] 8D[6] A0 RW RW RW RW R R R R R R R R YES 00 00 00 00 00 00 00 00 00 00 00 00 0.1 0.1 0.1 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 11 11 11 11 11 11 11 11 11 11 11 11 W 00 0.1 11 Table 5. Device IDs Part Number CY8C 20142 CY8C 20140 CY8C 20160 CY8C 20180 CY8C 20110 Device ID 42 40 60 80 10 Note All the Ack times specified are maximum values with all buttons enabled and filer enabled with maximum order. Notes 4. These registers are writable only after entering into setup mode. All the other registers available for read and write in Normal as well as in Setup mode. 5. The factory defaults of Reg 0x0E and 0x0F is 0x03 for 20142 device and 0x1F for 20140/60/80/10 devices. 6. The register 0x75- 0x78, 0x7D and 0x8A-0x8D are reserved. 7. The Device ID for different devices are tabulated in Table 5. 8. These registers are available only in CY8C20110. Document Number: 001-54606 Rev. ** Page 15 of 29 [+] [+] Feedback CY8C20110/CY8C20180/CY8C20160 CY8C20140/CY8C20142 CapSense Express Commands Command[9] W 00 A0 00 W 00 A0 01 W 00 A0 02 W 00 A0 03 W 00 A0 04 W 00 A0 05 W 00 A0 06 W 00 A0 07 W 00 A0 08 W 00 A0 09 W 00 A0 0A W 00 A0 0B Description Get firmware revision Store current configuration to NVM Restore factory configuration Write NVM POR defaults Read NVM POR defaults Read current configurations (RAM) Reconfigure device (POR) Set Normal mode of operation Set Setup mode of operation Start scan Stop scan Get CapSense scan status Executable Mode Setup/Normal Setup/Normal Setup/Normal Setup/Normal Setup/Normal Setup/Normal Setup Setup/Normal Setup/Normal Setup/Normal Setup/Normal Setup/Normal Duration the Device is not accessible after ACK (in ms) 0 120 120 120 5 5 5 0 0 10 5 0 Register Conventions This table lists the register conventions that are specific to this section. Convention RW R Description Register has both read and write access Register has only read access Note 9. The ‘W’ indicates the write transfer. The next byte of data represents the 7 bit I2C address. Document Number: 001-54606 Rev. ** Page 16 of 29 [+] [+] Feedback CY8C20110/CY8C20180/CY8C20160 CY8C20140/CY8C20142 Layout Guidelines and Best Practices CapSense Button Shapes   Button Layout Design X: Button to ground clearance (Refer to Table 6 on page 18) Y: Button to button clearance (Refer to Table 6 on page 18) Recommended via Hole Placement Document Number: 001-54606 Rev. ** Page 17 of 29 [+] [+] Feedback CY8C20110/CY8C20180/CY8C20160 CY8C20140/CY8C20142 Table 6. Recommended Layout Guidelines and Best Practices Sl 1 2 3 Category Button Shape Button Size Button-Button Spacing 5 mm = Button Ground Clearance 0.5 mm 2 mm 15 mm Min Max Recommendations/Remarks Solid round pattern, round with LED hole, rectangle with round corners 10 mm 8 mm [X] 4 5 6 7 8 9 Button Ground Clearance Ground Flood - Top Layer Ground Flood - Bottom Layer Trace Length from Sensor to PSoC - Buttons Trace Width Trace Routing Button ground clearance = Overlay Thickness [Y] Hatched ground 7 mil trace and 45 mil grid (15% filling) Hatched ground 7 mil trace and 70 mil grid (10% filling) 200 mm 0.17 mm 0.20 mm