CY8C20111-SX1I

PRELIMINARY CY8C20111, CY8C20121 CapSense Express™ - One Button and Two Button Capacitive Controllers 1. Features ■ 2. Overview The CapSense Express™ controllers support two capacitive sensing (CapSense) buttons and two general purpose outputs in CY8C20121 and one CapSense button and one general purpose output in CY8C20111. The device functionality is configured through the I2C port and can be stored in on-board nonvolatile memory for automatic loading at power on. The digital outputs are controlled from CapSense inputs in factory default settings, but are user configurable for direct control through I2C. The four key blocks that make up the CY8C20111 and CY8C20121 controllers are: a robust capacitive sensing core with high immunity against radiated and conductive noise, control registers with nonvolatile storage, configurable outputs, and I2C communications. The user can configure registers with parameters needed to adjust the operation and sensitivity of the CapSense buttons and outputs and permanently store the settings. The standard I2C serial communication interface allows the host to configure the device and read sensor information in real time. I2C address is fully configurable without any external hardware strapping. Capacitive Button Input tied to a Configurable Output ❐ Robust sensing algorithm ❐ High sensitivity, low noise ❐ Immunity to RF and AC noise ❐ Low radiated EMC noise ❐ Supports wide range of input capacitance, sensor shapes, and sizes Target Applications ❐ Printers ❐ Cellular handsets ❐ LCD monitors ❐ Portable DVD players Industry's Best Configurability ❐ ❐ ❐ ❐ ■ ■ Custom sensor tuning Output supports strong 20 mA sink current Output state can be controlled through I2C or directly from CapSense input state Run time reconfigurable over I2C ■ Advanced Features ❐ Plug-and-play with factory defaults – tuned to support up to 1 mm overlay ❐ Nonvolatile storage of custom settings ❐ Easy integration into existing products – configure output to match system ❐ No external components required ❐ World class free configuration tool Wide Range of Operating Voltages ❐ 2.45V to 2.9V ❐ 3.10V to 3.6V ❐ 4.75V to 5.25V I2C Communication ❐ Supported from 1.8V ❐ Internal pull up resistor support option ❐ Data rate up to 400 kbps. 2 ❐ Configurable I C addressing Industrial Temperature Range: –40°C to +85°C Available in 8-Pin SOIC Package ■ ■ ■ ■ Cypress Semiconductor Corporation Document Number: 001-53516 Rev. ** • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 20, 2009 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 3. Pinouts Figure 1. CY8C20111 Pin Diagram - 8 SOIC - 1 Button Table 1. Pin Definitions – 8 SOIC- 1 Button Pin No 1 2 3 4 5 6 7 8 Name VSS I2C SCL I2C SDA CS0 NC DIG0 NC VDD Ground I2C Clock I2C Data CapSense Input No Connect Digital Output No Connect Supply Voltage Figure 2. CY8C20121 Pin Diagram – 8 SOIC- 2 Button Description Table 2. Pin Definitions – 8 SOIC- 2 Button Pin No 1 2 3 4 5 6 7 8 Name VSS I2C SCL I2C SDA CS0 CS1 DIG0 DIG1 VDD Ground I2C Clock I2C Data CapSense Input CapSense Input Digital Output Digital Output Supply Voltage Page 2 of 34 Description Document Number: 001-53516 Rev. ** [+] Feedback PRELIMINARY CY8C20111, CY8C20121 4. Typical Circuits 4.1 Circuit-1: One Button and One LED[1]   4.2 Circuit-2: One Button and One LED with I2C Interface   Note 1. The sensors are factory tuned to work with 1 mm plastic or glass overlay. Document Number: 001-53516 Rev. ** Page 3 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 4.3 Circuit-3: Two Buttons and Two LEDs with I2C Interface   4.4 Circuit-4: Compatibility with 1.8V I2C Signaling[2]   Note 2. 1.8V < VDD_I2C < VDD_CE and 2.4V < VDD_CE < 5.25V. Document Number: 001-53516 Rev. ** Page 4 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 4.5 Circuit-5: Powering Down CapSense Express Device for Low Power Requirements Output enable Output VDD LDO LED I2C Pull UPs Master Or Host CapSense Express SDA I2C BUS SCL For low power requirements, if Vdd is to be turned off, the above concept can be used. The Vdds of CapSense Express, I2C pull ups, and LEDs must be from the same source. Turning off the Vdd ensures that no signal is applied to the device while it is unpowered. The I2C signals should not be driven high by the master in this situation. If a port pin or group of port pins can cater to the power supply requirement of the circuit, the LDO can be avoided. 6. I2C Interface The CapSense Express devices support the industry standard I2C protocol, which can be used to: ■ ■ ■ ■ Configure the device Read the status and data registers of the device Control device operation Execute commands 5. Operating Modes 5.1 Normal Mode In normal mode of operation, the acknowledgment time is optimized. The timings remain approximately the same for different configurations of the slave. To reduce the acknowledgment times in normal mode, the registers 0x07, 0x08, 0x11, 0x50, 0x51, 0x5C, 0x5D are given only read access. Writing to these registers can be done only in setup mode. The I2C address can be modified during configuration. 6.1 I C Device Addressing The device uses a seven bit addressing protocol. The I2C data transfer is always initiated by the master sending one byte address; first 7-bit contains address and LSb indicates the data transfer direction. Zero in the LSb indicates the write transaction form master and one indicates read transfer by the master. Table 3 shows example for different I2C addresses. 2 5.2 Setup Mode All registers have read and write access (except those which are read only) in this mode. The acknowledgment times are longer compared to normal mode. When CapSense scanning is disabled (command code 0x0A in command register 0xA0), the acknowledgment times can be improved to values similar to the normal mode of operation. Table 3. I2C Addresses 7 Bit Slave Address (in Dec) 1 1 75 75 D7 0 0 1 1 D6 0 0 0 0 D5 0 0 0 0 D4 0 0 1 1 D3 0 0 0 0 D2 0 0 1 1 D1 1 1 1 1 D0 0(W) 1(R) 0(W) 1(W) 8 Bit Slave Address (in Hex) 02 03 96 97 Page 5 of 34 Document Number: 001-53516 Rev. ** [+] Feedback PRELIMINARY CY8C20111, CY8C20121 6.2 I2C Clock Stretching “Clock stretching” or “bus stalling” in I2C communication protocol is a state in which the slave holds the SCL line low to indicate that it is busy. In this condition, the master is expected to wait until the SCL is released by the slave. When an I2C master communicates with the CapSense Express device, the CapSense Express stalls the I2C bus after the reception of each byte (that is, just before the ACK/NAK bit) until processing of the byte is complete and critical internal functions are executed. Use a fully I2C compliant master to communicate with the CapSense Express device. An I2C master which does not support clock stretching (a bit banged software I2C Master) must wait for a specific amount of time specified (as shown in the section Format for Register Write and Read) for each register write and read operation before the next bit is transmitted. It is mandatory to check the SCL status (it should be high) before I2C master initiates any data transfer with CapSense Express. If the master fails to do so and continues to communicate, the communication is erroneous. The following diagrams represent the ACK time delays shown in the Register Map on page 7. Figure 3. Write ACK Time Representation Figure 4. Read ACK Time Representation 6.3 Format for Register Write and Read Register write format. Start Slave Addr + W Register read format. Start Slave Addr + W Start Slave Addr + R Legends: Master Slave A - ACK N- NAK A A A Reg Addr Reg Addr Data A A A Data Stop Data A Data A ..... Data A Stop A ..... Data N Stop 7. Registers Table 4. Register Conventions Convention RW R WPR FD Description Register have both read and write access Register have only read access Write register with pass code Factory defaults Document Number: 001-53516 Rev. ** Page 6 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 Table 5. Register Map Name Register Address (in Hex) 04 07 08 11 1C 1E 21 23 4E 4F 50 51 52 53 54 55 56 5C 5D 66 67 70 71 79 7A 7B 7C 81 82 83 84 85 86 87 88 A0 Access Writable Only in Setup Mode[3] Factory Default Values of Registers (in Hex) 1 Button 01 Yes Yes Yes 01 01 01 82 01 2 Button 03 03 03 03 82 01 82 02 28 64 Yes Yes A0 00 0A 03 14 14 20 Yes Yes 64 00 28 64 A0 00 0A 03 14 14 20 00 01 64 64 0A 0A 0A 00 11 03 00 00 00 00 00 00 00 00 00 00 00 21 03 00 00 00 00 00 00 00 00 00 00 0.14 0.14 0.14 0.14 0.11 0.11 0.11 0.11 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.10 0.11 0.11 0.11 0.11 0.11 0.12 0.12 0.12 0.12 0.11 0.11 I2C Max ACK Time in Normal Mode (ms)[5] 0.10 11 11 11 11 11 11 11 11 11 35 35 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 I2C Max ACK Time in Setup Mode (ms)[5] Page No. OUTPUT_PORT CS_ENABLE DIG_ENABLE SET_STRONG_DM OP_SEL_0 LOGICAL_OPR_INPUT0 OP_SEL_1[4] LOGICAL_OPR_INPUT1[4] CS_NOISE_TH CS_BL_UPD_TH CS_SETL_TIME CS_OTH_SET CS_HYSTERISIS CS_DEBOUNCE CS_NEG_NOISE_TH CS_LOW_BL_RST CS_FILTERING CS_SCAN_POS_0 CS_SCAN_POS_1[4] CS_FINGER_TH_0 CS_FINGER_TH_1[4] CS_IDAC_0 CS_IDAC_1[4] I2C_ADDR_LOCK DEVICE_ID DEVICE_STATUS I2C_ADDR_DM CS_READ_BUTTON CS_READ_BLM CS_READ_BLL CS_READ_DIFFM CS_READ_DIFFL CS_READ_RAWM CS_READ_RAWL CS_READ_STATUS COMMAND_REG W RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R R RW RW R R R R R R R W 9 9 10 10 12 12 12 12 13 13 13 14 14 15 15 15 16 16 16 17 17 17 17 17 18 18 19 19 20 20 20 20 20 20 21 21 Notes 3. These registers are writable only after entering into setup mode. All other registers are available for read and write in normal and setup mode. 4. These registers are available only in CY8C20121 device. 5. The Ack times specified are 1x I2C Ack times. Document Number: 001-53516 Rev. ** Page 7 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 Table 6. CapSense Express Commands Command [5] W 00 A0 00 W 00 A0 01 W 00 A0 02 W 00 A0 03 W 00 A0 04 W 00 A0 05 W 00 A0 06 W 00 A0 07 W 00 A0 08 W 00 A0 09 W 00 A0 0A W 00 A0 0B Description Get firmware revision Store current configuration to NVM Restore factory configuration Write NVM POR defaults Read NVM POR defaults Read current configurations (RAM) Reconfigure device (POR) Set Normal mode of operation Set Setup mode of operation Start scan Stop scan Get CapSense scan status Executable Mode Setup/Normal Setup/Normal Setup/Normal Setup/Normal Setup/Normal Setup/Normal Setup Setup/Normal Setup/Normal Setup/Normal Setup/Normal Setup/Normal Duration the Device is NOT Accessible after ACK (in ms)[5] 0 120 120 120 5 5 5 0 0 10 5 0 Note 6. ‘W’ indicates the write transfer. The next byte of data represents the 7 bit I2C address. Document Number: 001-53516 Rev. ** Page 8 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 7.1 OUTPUT_PORT Output Port Register OUTPUT_PORT: 04h 1 Button 7 Access: FD Bit Name 2 Button Access: FD Bit Name 7 6 5 4 3 2 1 W:03 DIG[1:0] 6 5 4 3 2 1 0 W:01 DIG[0] 0 This register is used to write data to DIG output port. Pins defined as output of combinational logic (in OP_SEL_x register) cannot be changed using this register. Bit 1:0 Name DIG [1:0] Description A bit set in this register sets the logic level of the output. 0 Logic ‘0’ 1 Logic ‘1’ 7.2 CS_ENABLE Select CapSense Input Register CS_ENABLE: 07h (Writable only in Setup mode) 1 Button Access: FD Bit Name 2 Button Access: FD Bit Name 7 6 5 4 3 2 1 0 RW:01 CS[0] 7 6 5 4 3 2 1 RW:03 CS[1:0] 0 This register is used to enable CapSense inputs. This register should be set before setting finger threshold (0x66, 0x67) and IDAC setting (0x70, 0x71) registers. Bit 1:0 Name CS [1:0] Description These bits are used to enable CapSense inputs. 0 Disable CapSense input 1 Enable CapSense input Document Number: 001-53516 Rev. ** Page 9 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 7.3 DIG_ENABLE Select DIG Output Register GPO_ENABLE: 08h (Writable only in Setup mode) 1 Button 7 Access: FD Bit Name 6 5 4 3 2 1 0 RW:01 DIG[0] 2 Button Access: FD Bit Name 7 6 5 4 3 2 1 RW:03 DIG [1:0] 0 This register is used to enable DIG (Digital) outputs. If DIG output is enabled, the strong drive mode register (11h) should also be set. If DIG output is disabled the drive mode of these pins is High Z. Bit 1:0 Name DIG [1:0] Description These bits are used to enable DIG outputs. 0 Disable DIG output 1 Enable DIG output 7.4 SET_STRONG_DM Sets Strong Drive Mode for DIG Outputs. SET_STRONG_DM: 11h (Writable only in Setup mode) 1 Button 7 Access: FD Bit Name 6 5 4 3 2 1 0 RW:01 DM [0] 2 Button Access: FD Bit Name 7 6 5 4 3 2 1 RW:03 DM [1:0] 0 This register sets strong drive mode for DIG (Digital) outputs. To set strong drive mode the pin should be enabled as GP output. Bit 1:0 Name DM [1:0] Description These bits are used to set the strong drive mode to DIG outputs. 0 Strong drive mode not set 1 Strong drive mode set Document Number: 001-53516 Rev. ** Page 10 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 Figure 5. CY8C20111 Digital Logic Diagram OUTPUT_PORT [0] LOGICAL_OPR_INPUT0 [0] INVERSION LOGIC A AND / OR Logic selection DIG0 ENB CS0 B S OP_SEL_0 [0] OP_SEL_0 [7] OP_SEL_0 [1] Figure 6. CY8C20121 Digital Logic Diagram LOGICAL_OPR_INPUTx [0] OUTPUT_PORT [x] ENB CS0 A A INVERSION LOGIC AND / OR Logic selection DIGx LOGICAL_OPR_INPUTx [1] AND / OR Logic selection B S ENB CS1 B S OP_SEL_x [7] OP_SEL_x [0] OP_SEL_x [1] INPUT SELECTION LOGIC Document Number: 001-53516 Rev. ** Page 11 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 7.5 OP_SEL_x Logic Operation Selection Registers OP_SEL_0: 1Ch OP_SEL_1: 21h (Not available for 1 Button) 1/2Button Access: FD Bit Name 7 RW: 0 Op_En 6 5 4 3 2 1 RW: 0 InvOp 0 RW: 0 Operator This register is used to enable logic operation on GP outputs. OP_SEL_0 should be configured to get the logic operation output on DIG0 output and OP_SEL_1 for DIG1 output. Write to these registers during the disable state of respective DIG output pins does not have any effect. The input to the logic operation can be selected in LOGIC_OPRX registers. The selected inputs can be ORed or ANDed. The output of logic operation can also be inverted. Bit 7 Name Op_En Description This bit enables or disables logic operation. 0 Disable logic operation 1 Enable logic operation This bit enables or disables logic operation output inversion. 0 Logic operation output not inverted 1 Logic operation output inverted This bit selects which operator should be used to compute logic operation. 0 Logic operator OR is used on inputs 1 Logic operator AND is used on inputs 1 InvOp 0 Operator 7.6 LOGICAL_OPR_INPUTx Selects Input for Logic Operation LOGICAL_OPR_INPUT0: 1Eh LOGICAL_OPR_INPUT0 1 Button 7 Access: FD Bit Name LOGICAL_OPR_INPUT1: 23h (Not available for 1 button) 6 5 4 3 2 1 0 RW:01 CSL[0] 0 RW:01 CSL [1:0] 2 Button Access: FD Bit Name 7 6 5 4 3 2 1 LOGICAL_OPR_INPUT1 2 Button 7 Access: FD Bit Name 6 5 4 3 2 1 RW:02 CSL [1:0] 0 These registers are used to give the input to logic operation block. The inputs can be only CapSense input status. Bit 1:0 Name CSL [1:0] Description These bits selects the input for logic operation block. Document Number: 001-53516 Rev. ** Page 12 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 7.7 CS_NOISE_TH Noise Threshold Register CS_NOISE_TH: 4Eh 1/2 Button 7 Access: FD Bit Name 6 5 4 RW:28 NT[7:0] 3 2 1 0 This register sets the noise threshold value. For individual sensors, count values above this threshold do not update the baseline. This count is relative to baseline. This parameter is common for all sensors. The range is 3 to 255 and it should satisfy the equation NT < Min (Finger Threshold – Hysteresis – 5). Recommended value is 40% of finger threshold. Bit 7:0 Name NT [7:0] Description These bits are used to set the noise threshold value. 7.8 CS_BL_UPD_TH Baseline Update Threshold Register CS_BL_UPD_TH: 4Fh 1/2 Button 7 Access: FD Bit Name 6 5 4 RW:64 BLUT[7:0] 3 2 1 0 When the new raw count value is above the current baseline and the difference is below the noise threshold, the difference between the current baseline and the raw count is accumulated into a “bucket.” When the bucket fills, the baseline increments and the bucket is emptied. This parameter sets the threshold that the bucket must reach for the baseline to increment. In other words, lower value provides faster baseline update rate and vice versa. This parameter is common for all sensors. The range is 0 to 255. Bit 7:0 Name BLUT [7:0] Description These bits set the threshold that the bucket must reach for baseline to increment. 7.9 CS_SETL_TIME Settling Time Register CS_SETL_TIME: 50h (Writable only in Setup mode) 1/2 Button 7 Access: FD Bit Name 6 5 3 RW:A0 STLNG_TM[7:0] 4 2 1 0 The settling time parameter controls the duration of the capacitance-to-voltage conversion phase. The parameter setting controls a software delay that allows the voltage on the integrating capacitor to stabilize. This parameter is common for all sensors. This register should be set before setting finger threshold (0x66, 0x67) and IDAC setting (0x70, 0x71) registers. The range is 2 to 255. Bit 7:0 Name STLNG_TM [7:0] Description These bits are used to set the settling time value. Document Number: 001-53516 Rev. ** Page 13 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 7.10 CS_OTH_SET CapSense Clock Select, Sensor Auto Reset Register CS_OTH_SET: 51h (Writable only in Setup mode) 1/2 Button 7 Access: FD Bit Name 6 RW: 00 5 4 3 RW: 0 Sns_Ar 2 1 0 CS_CLK[1:0] The registers set the CapSense module frequency of operation and enables or disables the sensor auto reset. CS_CLK bits provides option to select variable clock input for the CapSense block. A sensor design having higher paratactic requires lower clock for better performance and vice versa. Sensor Auto Reset determines whether the baseline is updated at all times or only when the signal difference is below the noise threshold. When set to ‘1’ (enabled), the baseline is updated constantly. This setting limits the maximum time duration of the sensor, but it prevents the sensors from permanently turning on when the raw count suddenly rises without anything touching the sensor. This sudden rise can be caused by a large power supply voltage fluctuation, a high energy RF noise source, or a very quick temperature change. When the parameter is set to ‘0’ (disabled), the baseline is updated only when raw count and baseline difference is below the noise threshold parameter. This parameter may be enabled unless there is a demand to keep the sensors in the on state for a long time. This parameter is common for all sensors. Bit 6:5 Name CS_CLK[1:0] Description These bits selects the CapSense clock. CS_CLK[1:0] 00 01 10 11 Frequency of Operation IMO IMO/2 IMO/4 IMO/8 3 Sns_Ar This bit is used to enable or disable sensor auto reset. 0 Disable Sensor auto reset 1 Enable Sensor auto reset 7.11 CS_HYSTERISIS Hysteresis Register CS_HYSTERISIS: 52h 1/2 Button 7 Access: FD Bit Name 6 5 4 RW:0A HYS[7:0] 3 2 1 0 The Hysteresis parameter adds to or subtracts from the finger threshold depending on whether the sensor is currently active or inactive. If the sensor is off, the difference count must overcome the ‘finger threshold + hysteresis’. If the sensor is on, the difference count must go below the ‘finger threshold – hysteresis’. It is used to add debouncing and “stickiness” to the finger detection algorithm. This parameter is common for all sensors. Possible values are 0 to 255. However, the setting must be lower than the finger threshold parameter setting. Recommended value for hysteresis is 15 percent of finger threshold. Bit 7:0 Name HYS [7:0] Description These bits are used to set the hysteresis value. Document Number: 001-53516 Rev. ** Page 14 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 7.12 CS_DEBOUNCE Debounce Register. CS_DEBOUNCE: 53h 1/2 Button Access: FD Bit Name 7 6 5 4 RW:0A DB[7:0] 3 2 1 0 The Debounce parameter adds a debounce counter to the ‘sensor active transition’. For the sensor to transition from inactive to active, the consecutive samples of difference count value must stay above the ‘finger threshold + hysteresis’ for the number specified. This parameter is common for all sensors. Possible values are 1 to 255. A setting of ‘1’ provides no debouncing. Bit 7:0 Name DB [7:0] Description These bits are used to set the debounce value. 7.13 CS_NEG_NOISE_TH Negative Noise Threshold Register CS_NEG_NOISE_TH: 54h 1/2 Button 7 Access: FD Bit Name 6 5 4 RW:0A NNT[7:0] 3 2 1 0 This parameter adds a negative difference count threshold. If the current raw count is below the baseline and the difference between them is greater than this threshold, the baseline is not updated. However, if the current raw count stays in the low state (difference greater than the threshold) for the number of samples specified by the Low Baseline Reset parameter, the baseline is reset. This parameter is common for all sensors. Bit 7:0 Name NNT [7:0] Description These bits are used to set the negative noise value. 7.14 CS_LOW_BL_RST Low Baseline Reset Register CS_LOW_BL_RST: 55h 1/2 Button 7 Access: FD Bit Name 6 5 4 RW:0A LBR[7:0] 3 2 1 0 This parameter works together with the Negative Noise Threshold parameter. If the sample count values are below the baseline minus the negative noise threshold for the specified number of samples, the baseline is set to the new raw count value. It essentially counts the number of abnormally low samples required to reset the baseline. It is generally used to correct the finger-on-at-startup condition. This parameter is common for all sensors. Bit 7:0 Name LBR [7:0] Description These bits are used to set the Low Baseline Reset value. Document Number: 001-53516 Rev. ** Page 15 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 7.15 CS_FILTERING CapSense Filtering Register CS_FILTERING: 56h 1/2 Button 7 Access: FD RW: 0 RstBl Bit Name 6 5 RW: 1 I2C_DS 4 RW: 0 Avg_En 3 2 0 RW: 00 Avg_Order[1:0] 1 This register provides an option for forced baseline reset and to enable and configure two different types of software filters. Bit 7 Name RstBl Description This bit resets all the baselines and it is auto cleared to ‘0’. 0 All Baselines are not reset 1 All baselines are reset When this bit is set to ‘1’ the CapSense scan sample is dropped if I2C communication was active during scanning. 0 Disable the I2C drop sample filer 1 Enable the I2C drop sample filter This bit enables average filter on raw counts. 0 Disable the average filter 1 Enable the average filter These bits are used to select the number of CapSense samples to average: Avg_Order[1:0] in Hex 00 01 10 11 Samples to Average 2 4 8 16 5 I2C_DS 4 Avg_En [1:0] Avg_Order[1:0] 7.16 CS_SCAN_POS_x Scan Position Registers CS_SCAN_POS_0: 5Ch (Writable only in Setup mode) 1/2 Button 7 Access: FD Bit Name CS_SCAN_POS_1: 5Dh (Not available for 1 Button) (Writable only in Setup mode) 6 5 4 3 2 1 0 RW: 0 Scan_Pstn 2 Button Access: FD Bit Name 7 6 5 4 3 2 1 0 RW: 1 Scan_Pstn This register is used to set the position of the sensors in the switch table for proper scanning sequence because the CapSense sensors are scanned in sequence. This register should be set after setting 0x07, 0x50, and 0x51 registers. Bit 0 Name Scan_Pstn Description This bit sets the scan position. Document Number: 001-53516 Rev. ** Page 16 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 7.17 CS_FINGER_TH_x Finger Threshold Registers CS_FINGER_TH_0: 66h CS_FINGER_TH_1: 67h (Not available in 1 Button) 1/2 Button Access: FD Bit Name 7 6 5 4 RW: 64 FT[7:0] 3 2 1 0 This register sets the finger threshold value for CapSense inputs. Possible values are 3 to 255. This parameter should be configured individually for each CapSense inputs. This register should be set after setting 0x07, 0x50, and 0x51 registers. Bit [7:0] Name FT [7:0] Description These bit set the finger threshold for CapSense inputs. 7.18 CS_IDAC_x IDAC Setting Registers CS_IDAC_0: 70h CS_IDAC_1: 71h (Not available in 1 Button) 1/2 Button 7 6 5 4 Access: FD Bit Name RW: 0A IDAC[7:0] 3 2 1 0 The IDAC register controls the sensitivity of the CapSense algorithm. This register is used to tune the CapSense input for specific design or overlays. Decreasing the value of this register increases the sensitivity of the CapSense buttons and vice versa. Decreasing the value of IDAC increases noise and vice versa. Possible values are 1 to 255. If the value is set to 0 then the value is reset to default value 10. The recommended value is greater than 4. Setting value < 4 creates excessive amount of noise. This register should be set after setting 0x07, 0x50, and 0x51 registers. Bit [7:0] Name IDAC [7:0] Description These bit set the IDAC values. 7.19 I2C_ADDR_LOCK I2C Address Lock Registers I2C_ADDR_LOCK: 79h 1/2 Button 7 Access: FD Bit Name 2 2 6 5 4 3 2 1 0 WPR: 0 I2CAL This register is used to unlock and lock the I C address register (7Ch) access. The device I C address should be modified by writing new address to register 7Ch after unlocking the access using this register. Write to the 7C register during the locked state does not have any effect and the new address take effect only after the access is locked. To lock or unlock the I2C AL bit, the following three bytes must be written to register 79h: ■ ■ unlock I2CAL: 3Ch A5h 69h lock I2CAL: 96h 5Ah C3h Reading the I2CAL bit from register 79h indicates the current access state. Bit 0 Name I2CAL Description This bit gives the lock/unlock status of I2C address. 0 Unlocked 1 Locked Document Number: 001-53516 Rev. ** Page 17 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 7.20 DEVICE_ID Device ID Register DEVICE_ID: 7Ah 1 Button Access: FD Bit Name 7 6 5 4 3 R: 11 DEV_ID[7:0] 3 R: 21 DEV_ID[7:0] 2 1 0 2 Button Access: FD Bit Name 7 6 5 4 2 1 0 This register contains the device and product ID. The device and product ID corresponds to “xx” in CY8C201xx. Bit 7:0 Name DEV_ID [7:0] Description These bits contain the device and product ID. Part No CY8C20111 CY8C20121 Device/Product ID 11 21 7.21 DEVICE_STATUS Device Status Register DEVICE_STATUS: 7Bh 1/2 Button 7 6 Access: FD R : 00 Bit Name Ip_Volt[1:0] This register contains the device status. 5 R: 0 IRES 4 R:0 Load_FD 3 R: 0 No_NVM_Wr 2 1 R: 0 CSE 0 R: 0 DIGE Bit 7:6 Name Ip_Volt [1:0] Description Supply voltage is automatically detected and these bits are set accordingly. Ip_Volt[1:0] 00 01 10 11 Supply Voltage 5 3.3 2.7 Reserved 5 IRES 4 Load_FD 3 1 No_NVM_Wr CSE 0 DIGE When set to ‘1’, this bit indicates that an internal reset occurred. 0 indicates the last system reset was not internal reset 1 indicates the last system reset was internal reset This bit indicates whether factory defaults are loaded during power up. 0 User default configuration is loaded during power up 1 Factory default configuration is loaded during power up When set to ‘1’, this bit indicates that the supply voltage applied to the device Is too low for a write to nonvolatile memory operation, and no write is performed. This bit must be checked before any Store or Write POR command. This bit indicates whether CapSense function is enabled or disabled. 0 Functionality of CapSense block is disabled 1 Functionality of CapSense block is enabled This bit indicates whether GP Output function is enabled or disabled. 0 Functionality of Digital output block is disabled 1 Functionality of Digital output block is enabled Document Number: 001-53516 Rev. ** Page 18 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 7.22 I2C_ADDR_DM Device I2C Address and I2C Pin Drive Mode Register I2C_ADDR_DM: 7Ch 1 Button 7 Access: FD Bit Name RW: 0 I2CIP_EN 6 5 4 3 RW: 00 I2C_ADDR[6:0] 2 1 0 This register sets the drive mode of I2C pins and I2C slave address. To write to this register, register 79h must first be unlocked. The value written to register 7Ch is applied only after locking register 79h again. Bit 7 Name I2CIP_EN Description This bit is used to set the I2C pins drive mode. 0 Internal pull up enabled 1 Internal pull up disabled Used to set the device I2C address. 6:0 I2C_ADDR [6:0] 7.23 CS_READ_BUTTON Button Select Register I2C_ADDR_DM: 81h 1 Button 7 Access: FD Bit Name RW: 0 RD_EN 6 5 4 3 2 1 0 RW: 0 CSBN[0] 2 Button Access: FD Bit Name 7 RW: 0 RD_EN 6 5 4 3 2 1 RW: 00 CSBN[1:0] 0 The scan result of a CapSense input (raw count, difference count, and baseline) can be read only for one input at a time using 82h-87h registers. This register is used to select a CapSense input to read the raw count, difference count, and baseline. Only the pins defined as CapSense inputs in register 07h can be used with this register. Trying to select other pins not defined as CapSense does not have any change. Bit 7 Name RD_EN Description This bit enables the CapSense raw data reading. 0 Disable CapSense scan result reading 1 Enable CapSense scan result reading These bits decide which CapSense button scan result are read. When writing to this register, the bitmask must contain only one bit set to ’1’, otherwise the data is discarded. CSBN [1:0] 01 10 CapSense Button No 1 2 1:0 CSBN [1:0] Document Number: 001-53516 Rev. ** Page 19 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 7.24 CS_READ_BLx Baseline Value MSB/LSB Registers CS_READ_BLM: 82h CS_READ_BLL: 83h 1/2 Button Access: FD Bit Name 7 6 5 4 R: 00 BL [7:0] 3 2 1 0 Reading from this register returns the 2-byte current baseline value for the selected CapSense input. Bit 7:0 Name BL [7:0] Description These bits represent the baseline value. 7.25 CS_READ_DIFFx Difference Count Value MSB/LSB Registers CS_READ_DIFFM: 82h CS_READ_DIFFL: 83h 1/2 Button Access: FD Bit Name 7 6 5 4 R: 00 DIF [7:0] 3 2 1 0 Reading from this register returns the 2-byte current difference count for the selected CapSense input. Bit 7:0 Name DIF [7:0] Description These bits represent the sensor difference count. 7.26 CS_READ_RAWx Difference Count Value MSB/LSB Registers CS_READ_RAWM: 82h CS_READ_RAWL: 83h 1/2 Button Access: FD Bit Name 7 6 5 4 R: 00 RC [7:0] 3 2 1 0 Reading from this register returns the 2-byte current raw count value for the selected CapSense input. Bit 7:0 Name RC [7:0] Description These bits represent the raw count value. Document Number: 001-53516 Rev. ** Page 20 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 7.27 CS_READ_STATUS Sensor On Status Register CS_READ_STATUS: 88h 1 Button 7 Access: FD Bit Name 6 5 4 3 2 1 0 R: 0 BT_ST[0] 2 Button Access: FD Bit Name 7 6 5 4 3 2 1 R: 00 BT_ST[1:0] 0 This register gives the sensor ON/OFF status. A bit ‘1’ indicates sensor is ON and ‘0’ indicates sensor is OFF. Bit 1:0 Name BT_ST [1:0] Description These bits used to represent sensor status. 0 Sensor OFF 1 Sensor ON 7.28 COMMAND_REG Command Register COMMAND_REG: A0h 1/2 Button 7 Access: FD Bit Name 6 5 4 W: 00 Cmnd [7:0] 3 2 1 0 Commands are executed by writing the command code to the command register. Bit 7:0 Name Cmnd [7:0] Description Refer to the following table for command register opcodes. Command Code 00h Name Get Firmware Revision Description The I2C buffer is loaded with the one byte firmware revision value. Reading one byte after writing this command returns the firmware revision. The upper nibble of the firmware revision byte is the major revision number and the lower nibble is the minor revision number. The current register settings are saved in nonvolatile memory (Flash). This setting is automatically loaded after the next device reset/power up or if the Reconfigure Device (06h) command is issued. Replaces the saved user configuration with the factory default configuration. Current settings are unaffected by this command. New settings are loaded after the next device reset/power up or if the 06h command is issued. Sends new power up defaults to the CapSense controller without changing current settings unless the 06h command is issued afterwards. This command is followed by 123 data bytes according to the POR Default Data Structure table. The CRC is calculated as the XOR of the 122 data bytes (00h-79h). If the CRC check fails or an incomplete block is sent, the slave responds with an ACK and the data is NOT saved to Flash. To define new POR defaults: ■ ■ ■ 01h Store Current Configuration to NVM Restore Factory Configuration Write POR Defaults 02h 03h Write command 03h Write 122 data bytes with new values of registers (use the _flash.iic file generated from s/w tool) Write one CRC byte calculated as XOR of previous 122 data bytes Document Number: 001-53516 Rev. ** Page 21 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 Command Code 04h Name Read POR Defaults Description Reads the POR settings stored in the nonvolatile memory. To read POR defaults: ■ ■ ■ Write command 04h Read 122 data bytes Read one CRC byte 05h Read Device Configuration (RAM) Reads the current device configuration. Gives the user "flat-address-space" access to all device settings. To read device configuration: ■ ■ ■ Write command 05h Read 122 data bytes Read one CRC byte 06h Reconfigure Device (POR) Set Normal Operation Mode Set Setup Operation Mode Start CapSense Scanning Stop CapSense Scanning Immediately reconfigures the device with actual POR defaults from Flash. Has the same effect on the registers as a POR. This command can only be executed in setup operation mode (command code 08). Sets the device in normal operation mode. In this mode, CapSense pin assignments cannot be modified; settling time, IDAC setting, external capacitor, and sensor auto-reset also cannot be modified. Sets the device in setup operation mode. In this mode, CapSense pin assignments can be changed along with other parameters. Allows the user to start CSA scanning after it has been stopped using command 0x0A. Note that at POR, scanning is enabled and started by default if one or more sensors are enabled. Allows the user to stop CSA scanning. A system host controller might initiate this command before powering down the device to make sure that during power down no CapSense touches are detected. When CSA scanning is stopped by the user and the device is still in the valid VCC operating range, the following behavior is supported: ■ ■ ■ 07h 08h 09h 0Ah Any change to configuration can still be done (as long as VCC is in operating range). Command code 0x06 overrides the status of stop/scan by enabling and starting CSA scanning if one or more sensors are enabled. CapSense read-back values return 0x00. 0Bh Returns CapSense Scanning Status The I2C buffer is loaded with the one-byte CSA scanning status value. After writing the value 0Bh to the A0h register, reading one byte returns the CSA scanning status. It returns the LVD_STOP_SCAN and STOP_SCAN bits. LVD_STOP_SCAN is bit 3 - Set when CSA is stopped because VCC is outside the valid operating range. STOP_SCAN is bit 2 - Set when CSA is stopped by the user by writing command 0x0A. Document Number: 001-53516 Rev. ** Page 22 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 8. Layout Guidelines and Best Practices Sl. No. 1 2 3 Category Button Shape Button Size Button Button Spacing Min Max Recommendations/Remarks Solid round pattern, round with LED hole, rectangle with round corners 5 mm = Button Ground Clearance 0.5 mm 15 mm 10 mm 8 mm 4 5 6 7 8 9 Button Ground Clearance Ground Flood - Top Layer Ground Flood - Bottom Layer Trace Length from Sensor to PSoC - Buttons Trace Width Trace Routing 2 mm Button ground clearance = Overlay Thickness Hatched ground 7 mil trace and 45 mil grid (15% filling) Hatched ground 7 mil trace and 70 mil grid (10% filling) 200 mm 0.17 mm 0.20 mm < 100 mm. 0.17 mm (7 mil) Traces should be routed on the non sensor side. If any non CapSense trace crosses CapSense trace, ensure that intersection is orthogonal. Via should be placed near the edge of the button/slider to reduce trace length thereby increasing sensitivity. 10 mil 10 11 12 13 Via Position for the Sensors Via Hole Size for Sensor Traces No. of Via on Sensor Trace CapSense Series Resistor Placement Distance between any CapSense Trace to Ground Flood Device Placement 10 mil 1 2 10mm 1 Place CapSense series resistors close to PSoC for noise suppression.CapSense resistors have highest priority place them first. 20 mil 14 20 mil 15 Mount the device on the layer opposite to sensor. The CapSense trace length between the device and sensors should be minimum Top layer-sensor pads and bottom layer-PSoC, other components and traces. Top layer-sensor pads, second layer – CapSense traces, third layer-hatched ground, bottom layer- PSoC, other components and non CapSense traces 0 mm 2 mm 1 mm Should to be non conductive material. Glass, ABS Plastic, Formica Adhesive should be non conductive and dielectrically homogenous. 467MP and 468MP adhesives made by 3M are recommended. Cut a hole in the sensor pad and use rear mountable LEDs. Refer Example PCB Layout Design with Two CapSense Buttons and Two LEDs on page 26. Standard board thickness for CapSense FR4 based designs is 1.6 mm. 16 17 Placement of Components in 2 Layer PCB Placement of Components in 4 Layer PCB Overlay Thickness - Buttons Overlay Material Overlay Adhesives 18 19 20 21 LED Back Lighting 22 Board Thickness Document Number: 001-53516 Rev. ** Page 23 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 Figure 7. Button Shapes   Figure 8. Button Layout Design X: Button to ground clearance Y: Button to button clearance Figure 9. Recommended Via-hole Placement   Document Number: 001-53516 Rev. ** Page 24 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 8.1 Example PCB Layout Design with Two CapSense Buttons and Two LEDs Figure 10. Top Layer   Figure 11. Bottom Layer   Document Number: 001-53516 Rev. ** Page 25 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 9. Operating Voltages For details on I2C 1x Ack time, refer Register Map on page 7 and CapSense Express Commands on page 8. I2C 4x Ack time is approximately four times the values mentioned in these tables. 10. CapSense Constraints Parameter Parasitic Capacitance (CP) of the CapSense Sensor Overlay Thickness Supply Voltage Variation (VDD) 0 1 Min Typ Max 30 2 ± 5% Units pF mm Notes All layout best practices followed, properly tuned and noise free condition. Document Number: 001-53516 Rev. ** Page 26 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 11. Electrical Specifications 11.1 Absolute Maximum Ratings Parameter TSTG Description Storage temperature Min –55 Typ 25 Max +100 Unit °C Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is +25°C ± 25°C (0°C to 50°C). Extended duration storage temperatures above 65°C degrade reliability TA VDD VIO VIOZ IMIO ESD LU Ambient temperature with power applied Supply voltage on VDD relative to VSS DC input voltage DC voltage applied to tri-state Maximum current into any GPIO pin Electro static discharge voltage Latch up current –40 –0.5 VSS – 0.5 VSS – 0.5 –25 2000 – – – – – – – – +85 +6.0 VDD + 0.5 VDD + 0.5 +50 – 200 °C V V V mA V mA Human body model ESD 11.2 Operating Temperature Parameter TA TJ Description Ambient temperature Junction temperature Min –40 –40 Typ – – Max +85 +100 Unit °C °C Notes Document Number: 001-53516 Rev. ** Page 27 of 34 [+] Feedback PRELIMINARY CY8C20111, CY8C20121 11.3 DC Electrical Characteristics 11.3.1 DC Chip Level Specifications Parameter VDD IDD Description Supply voltage Supply current Min 2.40 – Typ – 1.5 Max 5.25 2.5 Unit V mA Notes Conditions are VDD = 3.10V, TA = 25°C 11.3.2 5V and 3.3V DC General Purpose I/O Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C