CY8C20111_11

CY8C20111, CY8C20121 CapSense® Express™ – One Button and Two Button Capacitive Controllers 1. Features ■ ■ Capacitive button input tied to a configurable output ❐ Robust sensing algorithm ❐ High sensitivity, low noise ❐ Immunity to RF and AC noise ❐ Low radiated EMC noise ❐ Supports wide range of input capacitance, sensor shapes, and sizes Target Applications ❐ Printers ❐ Cellular handsets ❐ LCD monitors ❐ Portable DVD players Industry's best configurability ❐ ❐ ❐ ❐ I2C communication ❐ Supported from 1.8 V ❐ Internal pull-up resistor support option ❐ Data rate up to 400 kbps. 2 ❐ Configurable I C addressing Industrial temperature range: –40 °C to +85 °C Available in 8-Pin SOIC package ■ ■ ■ 2. Overview The CapSense® Express™ controllers support two capacitive sensing (CapSense) buttons and two general purpose outputs in CY8C20121 and one CapSense button and one general purpose output in CY8C20111. The device functionality is configured through the I2C port and can be stored in on-board nonvolatile memory for automatic loading at power on. The digital outputs are controlled from CapSense inputs in factory default settings, but are user configurable for direct control through I2C. The four key blocks that make up the CY8C20111 and CY8C20121 controllers are: a robust capacitive sensing core with high immunity against radiated and conductive noise, control registers with nonvolatile storage, configurable outputs, and I2C communications. The user can configure registers with parameters needed to adjust the operation and sensitivity of the CapSense buttons and outputs and permanently store the settings. The standard I2C serial communication interface allows the host to configure the device and read sensor information in real time. I2C address is fully configurable without any external hardware strapping. ■ Custom sensor tuning Output supports strong 20 mA sink current Output state can be controlled through I2C or directly from CapSense input state Run time reconfigurable over I2C ■ Advanced features ❐ Plug-and-play with factory defaults – tuned to support up to 1 mm overlay ❐ Nonvolatile storage of custom settings ❐ Easy integration into existing products – configure output to match system ❐ No external components required ❐ World class free configuration tool Wide range of operating voltages ❐ 2.45 V to 2.9 V ❐ 3.10 V to 3.6 V ❐ 4.75 V to 5.25 V ■ Cypress Semiconductor Corporation Document Number: 001-53516 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 24, 2011 [+] Feedback CY8C20111, CY8C20121 3. Contents Pinouts .............................................................................. 3 Typical Circuits ................................................................. 4 Circuit-1: One Button and One LED[1] ........................ 4 Circuit-2: One Button and One LED with I2C Interface ................................................................ 4 Circuit-3: Two Buttons and Two LEDs with I2C Interface ................................................................ 5 Circuit-4: Compatibility with 1.8 V I2C Signaling[2] ..... 5 Circuit-5: Powering Down CapSense Express Device for Low Power Requirements .......................... 6 Operating Modes .............................................................. 6 Normal Mode ............................................................... 6 Setup Mode ................................................................. 6 I2C Interface ...................................................................... 6 I2C Device Addressing ................................................ 6 I2C Clock Stretching .................................................... 7 Format for Register Write and Read ........................... 7 Registers ........................................................................... 7 OUTPUT_STATUS ................................................... 10 OUTPUT_PORT ........................................................ 10 CS_ENABLE ............................................................. 10 DIG_ENABLE ............................................................ 11 SET_STRONG_DM .................................................. 11 OP_SEL_x ................................................................. 13 LOGICAL_OPR_INPUTx .......................................... 13 CS_NOISE_TH ......................................................... 14 CS_BL_UPD_TH ....................................................... 14 CS_SETL_TIME ........................................................ 14 CS_OTH_SET ........................................................... 15 CS_HYSTERISIS ...................................................... 15 CS_DEBOUNCE ....................................................... 16 CS_NEG_NOISE_TH ................................................ 16 CS_LOW_BL_RST .................................................... 16 CS_FILTERING ......................................................... 17 CS_SCAN_POS_x .................................................... 17 CS_FINGER_TH_x ................................................... 18 CS_IDAC_x ............................................................... 18 I2C_ADDR_LOCK ..................................................... 18 DEVICE_ID ............................................................... 19 DEVICE_STATUS ..................................................... 19 I2C_ADDR_DM ......................................................... 20 CS_READ_BUTTON ................................................. 20 CS_READ_BLx ......................................................... 21 CS_READ_DIFFx ...................................................... 21 CS_READ_RAWx ..................................................... 21 CS_READ_STATUS ................................................. 22 COMMAND_REG ...................................................... 22 Layout Guidelines and Best Practices ......................... 24 Example PCB Layout Design with Two CapSense Buttons and Two LEDs .................... 26 Operating Voltages ......................................................... 27 CapSense Constraints ................................................... 27 Electrical Specifications ................................................ 28 Absolute Maximum Ratings ....................................... 28 Operating Temperature ............................................. 28 DC Electrical Characteristics ..................................... 28 DC Chip Level Specifications .................................... 28 DC GPIO Specifications ............................................ 28 DC POR and LVD Specifications .............................. 29 DC Flash Write Specifications ................................... 29 DC I2C Specifications ............................................... 30 CapSense Electrical Characteristics ......................... 30 AC Electrical Specifications ....................................... 31 AC Chip-Level Specifications .................................... 31 AC GPIO Specifications ............................................ 31 AC I2C Specifications ................................................ 31 Examples of Frequently Used I2C Commands ............ 33 Ordering Information ...................................................... 34 Ordering Code Definitions ......................................... 34 Thermal Impedances ...................................................... 34 Solder Reflow Specifications ........................................ 34 Package Diagram ............................................................ 35 Acronyms ........................................................................ 36 Acronyms Used .............................................................. 36 Document Conventions ................................................. 36 Units of Measure ....................................................... 36 Numeric Conventions ................................................ 36 Glossary .......................................................................... 37 Document History Page ................................................. 42 Sales, Solutions, and Legal Information ...................... 43 Worldwide Sales and Design Support ....................... 43 Products .................................................................... 43 PSoC Solutions ......................................................... 43 Document Number: 001-53516 Rev. *G Page 2 of 43 [+] Feedback CY8C20111, CY8C20121 4. Pinouts Figure 1. CY8C20111 Pin Diagram - 8 SOIC - 1 Button Table 1. Pin Definitions – 8 SOIC- 1 Button Pin No 1 2 3 4 5 6 7 8 Name VSS I2C SCL I2C SDA CS0 NC DIG0 NC VDD Ground I2C Clock I2C Data CapSense Input No Connect Digital Output No Connect Supply Voltage Figure 2. CY8C20121 Pin Diagram – 8 SOIC- 2 Button Description Table 2. Pin Definitions – 8 SOIC- 2 Button Pin No 1 2 3 4 5 6 7 8 Name VSS I2C SCL I2C SDA CS0 CS1 DIG0 DIG1 VDD Ground I2C Clock I2C Data CapSense Input CapSense Input Digital Output Digital Output Supply Voltage Page 3 of 43 Description Document Number: 001-53516 Rev. *G [+] Feedback CY8C20111, CY8C20121 5. Typical Circuits 5.1 Circuit-1: One Button and One LED[1]   5.2 Circuit-2: One Button and One LED with I2C Interface   Note 1. The sensors are factory tuned to work with 1 mm plastic or glass overlay. Document Number: 001-53516 Rev. *G Page 4 of 43 [+] Feedback CY8C20111, CY8C20121 5.3 Circuit-3: Two Buttons and Two LEDs with I2C Interface   5.4 Circuit-4: Compatibility with 1.8 V I2C Signaling[2]   Note 2. 1.8 V ≤ VDD_I2C ≤ VDD_CE and 2.4 V ≤ VDD_CE ≤ 5.25 V. Document Number: 001-53516 Rev. *G Page 5 of 43 [+] Feedback CY8C20111, CY8C20121 5.5 Circuit-5: Powering Down CapSense Express Device for Low Power Requirements Output enable Output VDD LDO LED I2C Pull UPs Master Or Host CapSense Express SDA I2C BUS SCL For low power requirements, if VDD is to be turned off, the above concept can be used. The VDDs of CapSense Express, I2C pull-ups, and LEDs must be from the same source. Turning off the VDD ensures that no signal is applied to the device while it is unpowered. The I2C signals should not be driven high by the master in this situation. If a port pin or group of port pins can cater to the power supply requirement of the circuit, the LDO can be avoided. 7. I2C Interface The CapSense Express devices support the industry standard I2C protocol, which can be used to: ■ ■ ■ ■ Configure the device Read the status and data registers of the device Control device operation Execute commands 6. Operating Modes 6.1 Normal Mode In normal mode of operation, the acknowledgment time is optimized. The timings remain approximately the same for different configurations of the slave. To reduce the acknowledgment times in normal mode, the registers 0x07, 0x08, 0x11, 0x50, 0x51, 0x5C, 0x5D are given only read access. Writing to these registers can be done only in setup mode. The I2C address can be modified during configuration. 7.1 I2C Device Addressing The device uses a seven bit addressing protocol. The I2C data transfer is always initiated by the master sending one byte address; first 7-bit contains address and LSb indicates the data transfer direction. Zero in the LSb indicates the write transaction form master and one indicates read transfer by the master. Table 3 shows example for different I2C addresses. 6.2 Setup Mode All registers have read and write access (except those which are read only) in this mode. The acknowledgment times are longer compared to normal mode. When CapSense scanning is disabled (command code 0x0A in command register 0xA0), the acknowledgment times can be improved to values similar to the normal mode of operation. Table 3. I2C Addresses 7 Bit Slave Address (in Dec) 1 1 75 75 D7 0 0 1 1 D6 0 0 0 0 D5 0 0 0 0 D4 0 0 1 1 D3 0 0 0 0 D2 0 0 1 1 D1 1 1 1 1 D0 0(W) 1(R) 0(W) 1(W) 8 Bit Slave Address (in Hex) 02 03 96 97 Page 6 of 43 Document Number: 001-53516 Rev. *G [+] Feedback CY8C20111, CY8C20121 7.2 I2C Clock Stretching “Clock stretching” or “bus stalling” in I2C communication protocol is a state in which the slave holds the SCL line low to indicate that it is busy. In this condition, the master is expected to wait until the SCL is released by the slave. When an I2C master communicates with the CapSense Express device, the CapSense Express stalls the I2C bus after the reception of each byte (that is, just before the ACK/NAK bit) until processing of the byte is complete and critical internal functions are executed. Use a fully I2C compliant master to communicate with the CapSense Express device. An I2C master which does not support clock stretching (a bit banged software I2C Master) must wait for a specific amount of time specified (as shown in the section Format for Register Write and Read) for each register write and read operation before the next bit is transmitted. It is mandatory to check the SCL status (it should be high) before I2C master initiates any data transfer with CapSense Express. If the master fails to do so and continues to communicate, the communication is erroneous. The following diagrams represent the ACK time delays shown in the Register Map on page 7. Figure 3. Write ACK Time Representation Figure 4. Read ACK Time Representation 7.3 Format for Register Write and Read Register write format. Start Slave Addr + W Register read format. Start Slave Addr + W Start Slave Addr + R Legends: Master Slave A - ACK N- NAK A A A Reg Addr Reg Addr Data A A A Data Stop Data A Data A ..... Data A Stop A ..... Data N Stop 8. Registers Table 4. Register Conventions Convention RW R WPR FD Description Register have both read and write access Register have only read access Write register with pass code Factory defaults Document Number: 001-53516 Rev. *G Page 7 of 43 [+] Feedback CY8C20111, CY8C20121 Table 5. Register Map Name Register Address (in Hex) 04 07 08 11 1C 1E 21 23 4E 4F 50 51 52 53 54 55 56 5C 5D 66 67 70 71 79 7A 7B 7C 81 82 83 84 85 86 87 88 A0 Access Writable Only in Setup Mode[3] Factory Default Values of Registers (in Hex) 1 Button 01 Yes Yes Yes 01 01 01 82 01 2 Button 03 03 03 03 82 01 82 02 28 64 Yes Yes A0 00 0A 03 14 14 20 Yes Yes 64 00 28 64 A0 00 0A 03 14 14 20 00 01 64 64 0A 0A 0A 01 11 03 80 81 NA NA NA NA NA NA NA 00 01 21 03 80 81 NA NA NA NA NA NA NA 00 0.14 0.14 0.14 0.14 0.11 0.11 0.11 0.11 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.12 0.10 0.11 0.11 0.11 0.11 0.11 0.12 0.12 0.12 0.12 0.11 0.11 I2C Max ACK Time in Normal Mode (ms)[5] 0.10 11 11 11 11 11 11 11 11 11 35 35 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 11 I2C Max ACK Time in Setup Mode (ms)[5] Page No. OUTPUT_PORT CS_ENABLE DIG_ENABLE SET_STRONG_DM OP_SEL_0 LOGICAL_OPR_INPUT0 OP_SEL_1[4] LOGICAL_OPR_INPUT1[4] CS_NOISE_TH CS_BL_UPD_TH CS_SETL_TIME CS_OTH_SET CS_HYSTERISIS CS_DEBOUNCE CS_NEG_NOISE_TH CS_LOW_BL_RST CS_FILTERING CS_SCAN_POS_0 CS_SCAN_POS_1[4] CS_FINGER_TH_0 CS_FINGER_TH_1[4] CS_IDAC_0 CS_IDAC_1[4] I2C_ADDR_LOCK DEVICE_ID DEVICE_STATUS I2C_ADDR_DM CS_READ_BUTTON CS_READ_BLM CS_READ_BLL CS_READ_DIFFM CS_READ_DIFFL CS_READ_RAWM CS_READ_RAWL CS_READ_STATUS COMMAND_REG W RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R R RW RW R R R R R R R W 10 10 11 11 13 13 13 13 14 14 14 15 15 16 16 16 17 17 17 18 18 18 18 18 19 19 20 20 21 21 21 21 21 21 22 22 Notes 3. These registers are writable only after entering into setup mode. All other registers are available for read and write in normal and setup mode. 4. These registers are available only in CY8C20121 device. 5. The Ack times specified are 1x I2C Ack times. Document Number: 001-53516 Rev. *G Page 8 of 43 [+] Feedback CY8C20111, CY8C20121 Table 6. CapSense Express Commands Command [6] W 00 A0 00 W 00 A0 01 W 00 A0 02 W 00 A0 03 W 00 A0 04 W 00 A0 05 W 00 A0 06 W 00 A0 07 W 00 A0 08 W 00 A0 09 W 00 A0 0A W 00 A0 0B Description Get firmware revision Store current configuration to NVM Restore factory configuration Write NVM POR defaults Read NVM POR defaults Read current configurations (RAM) Reconfigure device (POR) Set Normal mode of operation Set Setup mode of operation Start scan Stop scan Get CapSense scan status Executable Mode Setup/Normal Setup/Normal Setup/Normal Setup/Normal Setup/Normal Setup/Normal Setup Setup/Normal Setup/Normal Setup/Normal Setup/Normal Setup/Normal Duration the Device is NOT Accessible after ACK (in ms)[5] 0 120 120 120 5 5 5 0 0 10 5 0 Note 6. ‘W’ indicates the write transfer. The next byte of data represents the 7 bit I2C address. Document Number: 001-53516 Rev. *G Page 9 of 43 [+] Feedback CY8C20111, CY8C20121 8.1 OUTPUT_STATUS Output Status Register OUTPUT_STATUS: 00h 1 Button 7 Access: FD Bit Name 2 Button Access: FD Bit Name The Output Status register represents the actual logical levels on the output pins. Bit 1:0 6 5 4 3 2 1 0 R:01 STS[0] 7 6 5 4 3 2 1 R:03 STS[1:0] 0 Name STS [1:0] Description Used to represent the output status 0 Output low 1 Output high 8.2 OUTPUT_PORT Output Port Register OUTPUT_PORT: 04h 1 Button 7 Access: FD Bit Name 2 Button Access: FD Bit Name 7 6 5 4 3 2 1 W:03 DIG[1:0] 6 5 4 3 2 1 0 W:01 DIG[0] 0 This register is used to write data to DIG output port. Pins defined as output of combinational logic (in OP_SEL_x register) cannot be changed using this register. Bit 1:0 Name DIG [1:0] Description A bit set in this register sets the logic level of the output. 0 Logic ‘0’ 1 Logic ‘1’ 8.3 CS_ENABLE Select CapSense Input Register CS_ENABLE: 07h (Writable only in Setup mode) 1 Button Access: FD Bit Name 2 Button Access: FD Bit Name 7 6 5 4 3 2 1 0 RW:01 CS[0] 7 6 5 4 3 2 1 RW:03 CS[1:0] 0 Document Number: 001-53516 Rev. *G Page 10 of 43 [+] Feedback CY8C20111, CY8C20121 This register is used to enable CapSense inputs. This register should be set before setting finger threshold (0x66, 0x67) and IDAC setting (0x70, 0x71) registers. Bit 1:0 Name CS [1:0] Description These bits are used to enable CapSense inputs. 0 Disable CapSense input 1 Enable CapSense input 8.4 DIG_ENABLE Select DIG Output Register GPO_ENABLE: 08h (Writable only in Setup mode) 1 Button 7 Access: FD Bit Name 6 5 4 3 2 1 0 RW:01 DIG[0] 2 Button Access: FD Bit Name 7 6 5 4 3 2 1 RW:03 DIG [1:0] 0 This register is used to enable DIG (Digital) outputs. If DIG output is enabled, the strong drive mode register (11h) should also be set. If DIG output is disabled the drive mode of these pins is High Z. Bit 1:0 Name DIG [1:0] Description These bits are used to enable DIG outputs. 0 Disable DIG output 1 Enable DIG output 8.5 SET_STRONG_DM Sets Strong Drive Mode for DIG Outputs. SET_STRONG_DM: 11h (Writable only in Setup mode) 1 Button 7 Access: FD Bit Name 6 5 4 3 2 1 0 RW:01 DM [0] 2 Button Access: FD Bit Name 7 6 5 4 3 2 1 RW:03 DM [1:0] 0 This register sets strong drive mode for DIG (Digital) outputs. To set strong drive mode the pin should be enabled as GP output. Bit 1:0 Name DM [1:0] Description These bits are used to set the strong drive mode to DIG outputs. 0 Strong drive mode not set 1 Strong drive mode set Document Number: 001-53516 Rev. *G Page 11 of 43 [+] Feedback CY8C20111, CY8C20121 Figure 5. CY8C20111 Digital Logic Diagram OUTPUT_PORT [0] LOGICAL_OPR_INPUT0 [0] INVERSION LOGIC A AND / OR Logic selection DIG0 ENB CS0 B S OP_SEL_0 [0] OP_SEL_0 [7] OP_SEL_0 [1] Figure 6. CY8C20121 Digital Logic Diagram LOGICAL_OPR_INPUTx [0] OUTPUT_PORT [x] ENB CS0 A A INVERSION LOGIC AND / OR Logic selection DIGx LOGICAL_OPR_INPUTx [1] AND / OR Logic selection B S ENB CS1 B S OP_SEL_x [7] OP_SEL_x [0] OP_SEL_x [1] INPUT SELECTION LOGIC Document Number: 001-53516 Rev. *G Page 12 of 43 [+] Feedback CY8C20111, CY8C20121 8.6 OP_SEL_x Logic Operation Selection Registers OP_SEL_0: 1Ch 1/2Button Access: FD Bit Name 7 RW: 0 Op_En OP_SEL_1: 21h (Not available for 1 Button) 6 5 4 3 2 1 RW: 0 InvOp 0 RW: 0 Operator This register is used to enable logic operation on GP outputs. OP_SEL_0 should be configured to get the logic operation output on DIG0 output and OP_SEL_1 for DIG1 output. Write to these registers during the disable state of respective DIG output pins does not have any effect. The input to the logic operation can be selected in LOGIC_OPRX registers. The selected inputs can be ORed or ANDed. The output of logic operation can also be inverted. Bit 7 Name Op_En Description This bit enables or disables logic operation. 0 Disable logic operation 1 Enable logic operation This bit enables or disables logic operation output inversion. 0 Logic operation output not inverted 1 Logic operation output inverted This bit selects which operator should be used to compute logic operation. 0 Logic operator OR is used on inputs 1 Logic operator AND is used on inputs 1 InvOp 0 Operator 8.7 LOGICAL_OPR_INPUTx Selects Input for Logic Operation LOGICAL_OPR_INPUT0: 1Eh LOGICAL_OPR_INPUT0 1 Button 7 Access: FD Bit Name 2 Button Access: FD Bit Name 7 LOGICAL_OPR_INPUT1: 23h (Not available for 1 button) 6 5 4 3 2 1 0 RW:01 CSL[0] 0 RW:01 CSL [1:0] 6 5 4 3 2 1 RW:02 CSL [1:0] 0 6 5 4 3 2 1 LOGICAL_OPR_INPUT1 2 Button 7 Access: FD Bit Name These registers are used to give the input to logic operation block. The inputs can be only CapSense input status. Bit 1:0 Name CSL [1:0] Description These bits selects the input for logic operation block. Document Number: 001-53516 Rev. *G Page 13 of 43 [+] Feedback CY8C20111, CY8C20121 8.8 CS_NOISE_TH Noise Threshold Register CS_NOISE_TH: 4Eh 1/2 Button 7 Access: FD Bit Name 6 5 4 RW:28 NT[7:0] 3 2 1 0 This register sets the noise threshold value. For individual sensors, count values above this threshold do not update the baseline. This count is relative to baseline. This parameter is common for all sensors. The range is 3 to 255 and it should satisfy the equation NT < Min (Finger Threshold – Hysteresis – 5). Recommended value is 40% of finger threshold. Bit 7:0 Name NT [7:0] Description These bits are used to set the noise threshold value. 8.9 CS_BL_UPD_TH Baseline Update Threshold Register CS_BL_UPD_TH: 4Fh 1/2 Button 7 Access: FD Bit Name 6 5 4 RW:64 BLUT[7:0] 3 2 1 0 When the new raw count value is above the current baseline and the difference is below the noise threshold, the difference between the current baseline and the raw count is accumulated into a “bucket.” When the bucket fills, the baseline increments and the bucket is emptied. This parameter sets the threshold that the bucket must reach for the baseline to increment. In other words, lower value provides faster baseline update rate and vice versa. This parameter is common for all sensors. The range is 0 to 255. Bit 7:0 Name BLUT [7:0] Description These bits set the threshold that the bucket must reach for baseline to increment. 8.10 CS_SETL_TIME Settling Time Register CS_SETL_TIME: 50h (Writable only in Setup mode) 1/2 Button 7 Access: FD Bit Name 6 5 3 RW:A0 STLNG_TM[7:0] 4 2 1 0 The settling time parameter controls the duration of the capacitance-to-voltage conversion phase. The parameter setting controls a software delay that allows the voltage on the integrating capacitor to stabilize. This parameter is common for all sensors. This register should be set before setting finger threshold (0x66, 0x67) and IDAC setting (0x70, 0x71) registers. The range is 2 to 255. Bit 7:0 Name STLNG_TM [7:0] Description These bits are used to set the settling time value. Document Number: 001-53516 Rev. *G Page 14 of 43 [+] Feedback CY8C20111, CY8C20121 8.11 CS_OTH_SET CapSense Clock Select, Sensor Auto Reset Register CS_OTH_SET: 51h (Writable only in Setup mode) 1/2 Button 7 Access: FD Bit Name 6 RW: 00 CS_CLK[1:0] 5 4 3 RW: 0 Sns_Ar 2 1 0 The registers set the CapSense module frequency of operation and enables or disables the sensor auto reset. CS_CLK bits provides option to select variable clock input for the CapSense block. A sensor design having higher paratactic requires lower clock for better performance and vice versa. Sensor Auto Reset determines whether the baseline is updated at all times or only when the signal difference is below the noise threshold. When set to ‘1’ (enabled), the baseline is updated constantly. This setting limits the maximum time duration of the sensor, but it prevents the sensors from permanently turning on when the raw count suddenly rises without anything touching the sensor. This sudden rise can be caused by a large power supply voltage fluctuation, a high energy RF noise source, or a very quick temperature change. When the parameter is set to ‘0’ (disabled), the baseline is updated only when raw count and baseline difference is below the noise threshold parameter. This parameter may be enabled unless there is a demand to keep the sensors in the on state for a long time. This parameter is common for all sensors. Bit 6:5 Name CS_CLK[1:0] Description These bits selects the CapSense clock. CS_CLK[1:0] 00 01 10 11 Frequency of Operation IMO IMO/2 IMO/4 IMO/8 3 Sns_Ar This bit is used to enable or disable sensor auto reset. 0 Disable Sensor auto reset 1 Enable Sensor auto reset 8.12 CS_HYSTERISIS Hysteresis Register CS_HYSTERISIS: 52h 1/2 Button 7 Access: FD Bit Name 6 5 4 RW:0A HYS[7:0] 3 2 1 0 The Hysteresis parameter adds to or subtracts from the finger threshold depending on whether the sensor is currently active or inactive. If the sensor is off, the difference count must overcome the ‘finger threshold + hysteresis’. If the sensor is on, the difference count must go below the ‘finger threshold – hysteresis’. It is used to add debouncing and “stickiness” to the finger detection algorithm. This parameter is common for all sensors. Possible values are 0 to 255. However, the setting must be lower than the finger threshold parameter setting. Recommended value for hysteresis is 15 percent of finger threshold. Bit 7:0 Name HYS [7:0] Description These bits are used to set the hysteresis value. Document Number: 001-53516 Rev. *G Page 15 of 43 [+] Feedback CY8C20111, CY8C20121 8.13 CS_DEBOUNCE Debounce Register. CS_DEBOUNCE: 53h 1/2 Button Access: FD Bit Name 7 6 5 4 RW:0A DB[7:0] 3 2 1 0 The Debounce parameter adds a debounce counter to the ‘sensor active transition’. For the sensor to transition from inactive to active, the consecutive samples of difference count value must stay above the ‘finger threshold + hysteresis’ for the number specified. This parameter is common for all sensors. Possible values are 1 to 255. A setting of ‘1’ provides no debouncing. Bit 7:0 Name DB [7:0] Description These bits are used to set the debounce value. 8.14 CS_NEG_NOISE_TH Negative Noise Threshold Register CS_NEG_NOISE_TH: 54h 1/2 Button 7 Access: FD Bit Name 6 5 4 RW:0A NNT[7:0] 3 2 1 0 This parameter adds a negative difference count threshold. If the current raw count is below the baseline and the difference between them is greater than this threshold, the baseline is not updated. However, if the current raw count stays in the low state (difference greater than the threshold) for the number of samples specified by the Low Baseline Reset parameter, the baseline is reset. This parameter is common for all sensors. Bit 7:0 Name NNT [7:0] Description These bits are used to set the negative noise value. 8.15 CS_LOW_BL_RST Low Baseline Reset Register CS_LOW_BL_RST: 55h 1/2 Button 7 Access: FD Bit Name 6 5 4 RW:0A LBR[7:0] 3 2 1 0 This parameter works together with the Negative Noise Threshold parameter. If the sample count values are below the baseline minus the negative noise threshold for the specified number of samples, the baseline is set to the new raw count value. It essentially counts the number of abnormally low samples required to reset the baseline. It is generally used to correct the finger-on-at-startup condition. This parameter is common for all sensors. Bit 7:0 Name LBR [7:0] Description These bits are used to set the Low Baseline Reset value. Document Number: 001-53516 Rev. *G Page 16 of 43 [+] Feedback CY8C20111, CY8C20121 8.16 CS_FILTERING CapSense Filtering Register CS_FILTERING: 56h 1/2 Button 7 Access: FD RW: 0 RstBl Bit Name 6 5 RW: 1 I2C_DS 4 RW: 0 Avg_En 3 2 0 RW: 00 Avg_Order[1:0] 1 This register provides an option for forced baseline reset and to enable and configure two different types of software filters. Bit 7 Name RstBl Description This bit resets all the baselines and it is auto cleared to ‘0’. 0 All Baselines are not reset 1 All baselines are reset When this bit is set to ‘1’ the CapSense scan sample is dropped if I2C communication was active during scanning. 0 Disable the I2C drop sample filer 1 Enable the I2C drop sample filter This bit enables average filter on raw counts. 0 Disable the average filter 1 Enable the average filter These bits are used to select the number of CapSense samples to average: Avg_Order[1:0] in Hex 00 01 10 11 Samples to Average 2 4 8 16 5 I2C_DS 4 Avg_En [1:0] Avg_Order[1:0] 8.17 CS_SCAN_POS_x Scan Position Registers CS_SCAN_POS_0: 5Ch (Writable only in Setup mode) 1/2 Button 7 Access: FD Bit Name CS_SCAN_POS_1: 5Dh (Not available for 1 Button) (Writable only in Setup mode) 2 Button Access: FD Bit Name 7 6 5 4 3 2 1 0 RW: 1 Scan_Pstn 6 5 4 3 2 1 0 RW: 0 Scan_Pstn This register is used to set the position of the sensors in the switch table for proper scanning sequence because the CapSense sensors are scanned in sequence. This register should be set after setting 0x07, 0x50, and 0x51 registers. Bit 0 Name Scan_Pstn Description This bit sets the scan position. Document Number: 001-53516 Rev. *G Page 17 of 43 [+] Feedback CY8C20111, CY8C20121 8.18 CS_FINGER_TH_x Finger Threshold Registers CS_FINGER_TH_0: 66h 1/2 Button Access: FD Bit Name 7 CS_FINGER_TH_1: 67h (Not available in 1 Button) 6 5 4 RW: 64 FT[7:0] 3 2 1 0 This register sets the finger threshold value for CapSense inputs. Possible values are 3 to 255. This parameter should be configured individually for each CapSense inputs. This register should be set after setting 0x07, 0x50, and 0x51 registers. Bit [7:0] Name FT [7:0] Description These bit set the finger threshold for CapSense inputs. 8.19 CS_IDAC_x IDAC Setting Registers CS_IDAC_0: 70h CS_IDAC_1: 71h (Not available in 1 Button) 1/2 Button 7 6 5 4 Access: FD Bit Name RW: 0A IDAC[7:0] 3 2 1 0 The IDAC register controls the sensitivity of the CapSense algorithm. This register is used to tune the CapSense input for specific design or overlays. Decreasing the value of this register increases the sensitivity of the CapSense buttons and vice versa. Decreasing the value of IDAC increases noise and vice versa. Possible values are 1 to 255. If the value is set to 0 then the value is reset to default value 10. The recommended value is greater than 4. Setting value ≤ 4 creates excessive amount of noise. This register should be set after setting 0x07, 0x50, and 0x51 registers. Bit [7:0] Name IDAC [7:0] Description These bit set the IDAC values. 8.20 I2C_ADDR_LOCK I2C Address Lock Registers I2C_ADDR_LOCK: 79h 1/2 Button 7 Access: FD Bit Name I2C I2C 6 5 4 3 2 1 0 WPR: 0 I2CAL This register is used to unlock and lock the address register (7Ch) access. The device address should be modified by writing new address to register 7Ch after unlocking the access using this register. Write to the 7C register during the locked state does not have any effect and the new address take effect only after the access is locked. To lock or unlock the I2C AL bit, the following three bytes must be written to register 79h: ■ ■ unlock I2CAL: 3Ch A5h 69h lock I2CAL: 96h 5Ah C3h Reading the I2CAL bit from register 79h indicates the current access state. Bit 0 Name I2CAL Description This bit gives the lock/unlock status of I2C address. 0 Unlocked 1 Locked Document Number: 001-53516 Rev. *G Page 18 of 43 [+] Feedback CY8C20111, CY8C20121 8.21 DEVICE_ID Device ID Register DEVICE_ID: 7Ah 1 Button Access: FD Bit Name 2 Button Access: FD Bit Name 7 6 5 4 3 R: 11 DEV_ID[7:0] 3 R: 21 DEV_ID[7:0] 2 1 0 7 6 5 4 2 1 0 This register contains the device and product ID. The device and product ID corresponds to “xx” in CY8C201xx. Bit 7:0 Name DEV_ID [7:0] Description These bits contain the device and product ID. Part No CY8C20111 CY8C20121 Device/Product ID 11 21 8.22 DEVICE_STATUS Device Status Register DEVICE_STATUS: 7Bh 1/2 Button 7 6 R : 00 Access: FD Bit Name Ip_Volt[1:0] This register contains the device status. Bit 7:6 5 R: 0 IRES 4 R:0 Load_FD 3 R: 0 No_NVM_Wr 2 1 R: 0 CSE 0 R: 0 DIGE Name Ip_Volt [1:0] Description Supply voltage is automatically detected and these bits are set accordingly. Ip_Volt[1:0] Supply Voltage 00 5 01 3.3 10 2.7 11 this bit indicates that ed internal reset occurred. Reser an When set to ‘1’, 0 indicates the last system reset was not internal reset 1 indicates the last system reset was internal reset This bit indicates whether factory defaults are loaded during power-up. 0 User default configuration is loaded during power-up 1 Factory default configuration is loaded during power-up When set to ‘1’, this bit indicates that the supply voltage applied to the device Is too low for a write to nonvolatile memory operation, and no write is performed. This bit must be checked before any Store or Write POR command. This bit indicates whether CapSense function is enabled or disabled. 0 Functionality of CapSense block is disabled 1 Functionality of CapSense block is enabled This bit indicates whether GP Output function is enabled or disabled. 0 Functionality of Digital output block is disabled 1 Functionality of Digital output block is enabled 5 IRES 4 Load_FD 3 1 No_NVM_Wr CSE 0 DIGE Document Number: 001-53516 Rev. *G Page 19 of 43 [+] Feedback CY8C20111, CY8C20121 8.23 I2C_ADDR_DM Device I2C Address and I2C Pin Drive Mode Register I2C_ADDR_DM: 7Ch 1 Button 7 Access: FD Bit Name RW: 0 I2CIP_EN 6 5 4 3 RW: 00 I2C_ADDR[6:0] 2 1 0 This register sets the drive mode of I2C pins and I2C slave address. To write to this register, register 79h must first be unlocked. The value written to register 7Ch is applied only after locking register 79h again. Bit 7 Name I2CIP_EN Description This bit is used to set the I2C pins drive mode. 0 Internal pull-up enabled 1 Internal pull-up disabled Used to set the device I2C address. 6:0 I2C_ADDR [6:0] 8.24 CS_READ_BUTTON Button Select Register I2C_ADDR_DM: 81h 1 Button 7 Access: FD Bit Name 2 Button Access: FD Bit Name RW: 0 RD_EN 7 RW: 0 RD_EN 6 5 4 3 2 1 RW: 00 CSBN[1:0] 6 5 4 3 2 1 0 RW: 0 CSBN[0] 0 The scan result of a CapSense input (raw count, difference count, and baseline) can be read only for one input at a time using 82h-87h registers. This register is used to select a CapSense input to read the raw count, difference count, and baseline. Only the pins defined as CapSense inputs in register 07h can be used with this register. Trying to select other pins not defined as CapSense does not have any change. Bit 7 Name RD_EN Description This bit enables the CapSense raw data reading. 0 Disable CapSense scan result reading 1 Enable CapSense scan result reading These bits decide which CapSense button scan result are read. When writing to this register, the bitmask must contain only one bit set to ’1’, otherwise the data is discarded. CSBN [1:0] 01 10 CapSense Button No 1 2 1:0 CSBN [1:0] Document Number: 001-53516 Rev. *G Page 20 of 43 [+] Feedback CY8C20111, CY8C20121 8.25 CS_READ_BLx Baseline Value MSB/LSB Registers CS_READ_BLM: 82h 1/2 Button Access: FD Bit Name 7 CS_READ_BLL: 83h 6 5 4 R: 00 BL [7:0] 3 2 1 0 Reading from this register returns the 2-byte current baseline value for the selected CapSense input. Bit 7:0 Name BL [7:0] Description These bits represent the baseline value. 8.26 CS_READ_DIFFx Difference Count Value MSB/LSB Registers CS_READ_DIFFM: 82h 1/2 Button Access: FD Bit Name 7 CS_READ_DIFFL: 83h 6 5 4 R: 00 DIF [7:0] 3 2 1 0 Reading from this register returns the 2-byte current difference count for the selected CapSense input. Bit 7:0 Name DIF [7:0] Description These bits represent the sensor difference count. 8.27 CS_READ_RAWx Difference Count Value MSB/LSB Registers CS_READ_RAWM: 82h 1/2 Button Access: FD Bit Name 7 CS_READ_RAWL: 83h 6 5 4 R: 00 RC [7:0] 3 2 1 0 Reading from this register returns the 2-byte current raw count value for the selected CapSense input. Bit 7:0 Name RC [7:0] Description These bits represent the raw count value. Document Number: 001-53516 Rev. *G Page 21 of 43 [+] Feedback CY8C20111, CY8C20121 8.28 CS_READ_STATUS Sensor On Status Register CS_READ_STATUS: 88h 1 Button 7 Access: FD Bit Name 2 Button Access: FD Bit Name 7 6 5 4 3 2 1 R: 00 BT_ST[1:0] 6 5 4 3 2 1 0 R: 0 BT_ST[0] 0 This register gives the sensor ON/OFF status. A bit ‘1’ indicates sensor is ON and ‘0’ indicates sensor is OFF. Bit 1:0 Name BT_ST [1:0] Description These bits used to represent sensor status. 0 Sensor OFF 1 Sensor ON 8.29 COMMAND_REG Command Register COMMAND_REG: A0h 1/2 Button 7 Access: FD Bit Name 6 5 4 W: 00 Cmnd [7:0] 3 2 1 0 Commands are executed by writing the command code to the command register. Bit 7:0 Name Cmnd [7:0] Description Refer to the following table for command register opcodes. Command Code 00h Name Get Firmware Revision Description The I2C buffer is loaded with the one byte firmware revision value. Reading one byte after writing this command returns the firmware revision. The upper nibble of the firmware revision byte is the major revision number and the lower nibble is the minor revision number. The current register settings are saved in nonvolatile memory (flash). This setting is automatically loaded after the next device reset/power-up or if the Reconfigure Device (06h) command is issued. Replaces the saved user configuration with the factory default configuration. Current settings are unaffected by this command. New settings are loaded after the next device reset/power-up or if the 06h command is issued. Sends new power-up defaults to the CapSense controller without changing current settings unless the 06h command is issued afterwards. This command is followed by 123 data bytes according to the POR Default Data Structure table. The CRC is calculated as the XOR of the 122 data bytes (00h-79h). If the CRC check fails or an incomplete block is sent, the slave responds with an ACK and the data is NOT saved to flash. To define new POR defaults: ■ ■ ■ 01h Store Current Configuration to NVM Restore Factory Configuration Write POR Defaults 02h 03h Write command 03h Write 122 data bytes with new values of registers (use the _flash.iic file generated from s/w tool) Write one CRC byte calculated as XOR of previous 122 data bytes Document Number: 001-53516 Rev. *G Page 22 of 43 [+] Feedback CY8C20111, CY8C20121 Command Code 04h Name Read POR Defaults Description Reads the POR settings stored in the nonvolatile memory. To read POR defaults: ■ ■ ■ Write command 04h Read 122 data bytes Read one CRC byte 05h Read Device Configuration (RAM) Reads the current device configuration. Gives the user "flat-address-space" access to all device settings. To read device configuration: ■ ■ ■ Write command 05h Read 122 data bytes Read one CRC byte 06h Reconfigure Device (POR) Set Normal Operation Mode Set Setup Operation Mode Start CapSense Scanning Stop CapSense Scanning Immediately reconfigures the device with actual POR defaults from flash. Has the same effect on the registers as a POR. This command can only be executed in setup operation mode (command code 08). Sets the device in normal operation mode. In this mode, CapSense pin assignments cannot be modified; settling time, IDAC setting, external capacitor, and sensor auto-reset also cannot be modified. Sets the device in setup operation mode. In this mode, CapSense pin assignments can be changed along with other parameters. Allows the user to start CSA scanning after it has been stopped using command 0x0A. Note that at POR, scanning is enabled and started by default if one or more sensors are enabled. Allows the user to stop CSA scanning. A system host controller might initiate this command before powering down the device to make sure that during power-down no CapSense touches are detected. When CSA scanning is stopped by the user and the device is still in the valid VCC operating range, the following behavior is supported: ■ ■ ■ 07h 08h 09h 0Ah Any change to configuration can still be done (as long as VCC is in operating range). Command code 0x06 overrides the status of stop/scan by enabling and starting CSA scanning if one or more sensors are enabled. CapSense read-back values return 0x00. 0Bh Returns CapSense Scanning Status The I2C buffer is loaded with the one-byte CSA scanning status value. After writing the value 0Bh to the A0h register, reading one byte returns the CSA scanning status. It returns the LVD_STOP_SCAN and STOP_SCAN bits. LVD_STOP_SCAN is bit 3 - Set when CSA is stopped because VCC is outside the valid operating range. STOP_SCAN is bit 2 - Set when CSA is stopped by the user by writing command 0x0A. Document Number: 001-53516 Rev. *G Page 23 of 43 [+] Feedback CY8C20111, CY8C20121 9. Layout Guidelines and Best Practices Sl. No. 1 2 3 Category Button Shape Button Size Button Button Spacing 5 mm = Button Ground Clearance 0.5 mm 2 mm 15 mm Min Max Recommendations/Remarks Solid round pattern, round with LED hole, rectangle with round corners 10 mm 8 mm 4 5 6 7 8 9 Button Ground Clearance Ground Flood - Top Layer Ground Flood - Bottom Layer Trace Length from Sensor to PSoC - Buttons Trace Width Trace Routing Button ground clearance = Overlay Thickness Hatched ground 7 mil trace and 45 mil grid (15% filling) Hatched ground 7 mil trace and 70 mil grid (10% filling) 200 mm 0.17 mm 0.20 mm < 100 mm. 0.17 mm (7 mil) Traces should be routed on the non sensor side. If any non CapSense trace crosses CapSense trace, ensure that intersection is orthogonal. Via should be placed near the edge of the button/slider to reduce trace length thereby increasing sensitivity. 10 mil 10 11 12 13 Via Position for the Sensors Via Hole Size for Sensor Traces No. of Via on Sensor Trace CapSense Series Resistor Placement Distance between any CapSense Trace to Ground Flood Device Placement 10 mil 1 2 10mm 1 Place CapSense series resistors close to PSoC for noise suppression.CapSense resistors have highest priority place them first. 20 mil 14 20 mil 15 Mount the device on the layer opposite to sensor. The CapSense trace length between the device and sensors should be minimum Top layer-sensor pads and bottom layer-PSoC, other components and traces. Top layer-sensor pads, second layer – CapSense traces, third layer-hatched ground, bottom layer- PSoC, other components and non CapSense traces Should to be non conductive material. Glass, ABS Plastic, Formica Adhesive should be non conductive and dielectrically homogenous. 467MP and 468MP adhesives made by 3M are recommended. Cut a hole in the sensor pad and use rear mountable LEDs. Refer Example PCB Layout Design with Two CapSense Buttons and Two LEDs on page 26. Standard board thickness for CapSense FR4 based designs is 1.6 mm. 16 17 Placement of Components in 2 Layer PCB Placement of Components in 4 Layer PCB Overlay Material Overlay Adhesives 18 19 20 LED Back Lighting 21 Board Thickness The Recommended maximum overlay thickness is 2 mm. For more details refer to AN53490, section The Integrating Capacitor. Document Number: 001-53516 Rev. *G Page 24 of 43 [+] Feedback CY8C20111, CY8C20121 Figure 7. Button Shapes   Figure 8. Button Layout Design X: Button to ground clearance Y: Button to button clearance Figure 9. Recommended Via-hole Placement   Document Number: 001-53516 Rev. *G Page 25 of 43 [+] Feedback CY8C20111, CY8C20121 9.1 Example PCB Layout Design with Two CapSense Buttons and Two LEDs Figure 10. Top Layer   Figure 11. Bottom Layer   Document Number: 001-53516 Rev. *G Page 26 of 43 [+] Feedback CY8C20111, CY8C20121 10. Operating Voltages For details on I2C 1x Ack time, refer Register Map on page 7 and CapSense Express Commands on page 8. I2C 4x Ack time is approximately four times the values mentioned in these tables. 11. CapSense Constraints Parameter Parasitic Capacitance (CP) of the CapSense Sensor Supply Voltage Variation (VDD) Min Typ Max 30 ± 5% Units pF Notes Document Number: 001-53516 Rev. *G Page 27 of 43 [+] Feedback CY8C20111, CY8C20121 12. Electrical Specifications 12.1 Absolute Maximum Ratings Parameter TSTG Description Storage temperature Min –55 Typ 25 Max +100 Unit °C Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is +25 °C ± 25 °C (0 °C to 50 °C). Extended duration storage temperatures above 65 °C degrade reliability TBAKETEMP Bake Temperature – 125 See Package label 72 °C tBAKETIME Bake Time See package label –40 –0.5 VSS – 0.5 VSS – 0.5 –25 2000 – – Hours TA VDD VIO VIOZ IMIO ESD LU Ambient temperature with power applied Supply voltage on VDD relative to VSS DC input voltage DC voltage applied to tri-state Maximum current into any GPIO pin Electro static discharge voltage Latch up current – – – – – – – +85 +6.0 VDD + 0.5 VDD + 0.5 +50 – 200 °C V V V mA V mA Human body model ESD 12.2 Operating Temperature Parameter TA TJ Description Ambient temperature Junction temperature Min –40 –40 Typ – – Max +85 +100 Unit °C °C Notes 13. DC Electrical Characteristics 13.1 DC Chip Level Specifications Parameter VDD IDD Description Supply voltage Supply current Min 2.40 – Typ – 1.5 Max 5.25 2.5 Unit V mA Conditions are VDD = 3.10 V, TA = 25 °C Notes Document Number: 001-53516 Rev. *G Page 28 of 43 [+] Feedback CY8C20111, CY8C20121 13.2 DC GPIO Specifications 13.2.1 5-V and 3.3-V DC GPIO Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, 3.10 V to 3.6 V –40 °C ≤ TA ≤ 85 °C. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Parameter VOH1 VOH2 VOL IOH IOL1 COUT Description High output voltage High output voltage Low output voltage High output current Low output current on Port 0 pins Capacitive load on pins as output Min VDD – 0.2 VDD – 0.9 – 0.01 – 0.5 Typ – – – – – 1.7 Max – – 0.75 1 10 5 Unit V V V mA mA pF Notes IOH ≤ 10 µA/pin, VDD ≥ 3.10 V IOH = 1 mA/pin, VDD ≥ 3.10 V IOL = 20 mA/pin, VDD > 3.10 V, maximum of 40 mA sink current VDD ≥ 3.1 V VDD ≥ 3.1 V, maximum of 40 mA sink current Package and pin dependent. Temp = 25 °C. 13.2.2 2.7-V DC GPIO Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4 V to 2.90 V and –40 °C < TA < 85 °C, respectively. Typical parameters apply to 2.7 V at 25 °C and are for design guidance only. Parameter VOH1 VOH2 VOL IOH IOL1 COUT Description High output voltage High output voltage Low output voltage High output current Low output current on Port 0 pins Capacitive load on pins as output Min VDD – 0.2 VDD – 0.5 – 0.01 – 0.5 Typ – – – – – 1.7 Max – – 0.75 0.2 10 5 Unit V V V mA mA pF IOH ≤ 10 µA/pin IOH = 0.2 mA/pin IOL = 10 mA/pin, maximum of 20 mA sink current VDD ≤ 2.9 V VDD ≤ 2.9 V, maximum of 20 mA sink current Package and pin dependent. Temp = 25 °C. Notes 13.3 DC POR and LVD Specifications Parameter VPPOR0 VPPOR1 Description VDD Value for PPOR Trip VDD= 2.7 V VDD= 3.3 V, 5 V Min – – Typ 2.36 2.60 Max 2.40 2.65 Unit V V Notes VDD must be greater than or equal to 2.5 V during startup or reset from watchdog. 13.4 DC Flash Write Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C < TA < 85 °C, 3.10 V to 3.6 V and –40 °C < TA < 85 °C or 2.4 V to 2.90 V and –40 °C < TA < 85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Flash Endurance and Retention specifications are valid only within the range: 25 °C±20 °C during the flash write operation. It is at the user’s own risk to operate out of this temperature range. If flash writing is done out of this temperature range, the endurance and data retention reduces. Symbol VDDIWRITE IDDP FlashENPB FlashDR Description Supply Voltage for Flash Write Operations[7] Supply Current for Flash Write Operations Flash Endurance Flash Data Retention Min 2.7 – 50,000 10 Typ – 5 – – Max – 25 – – Units V mA – Years Notes Erase/write cycles Note 7. Commands involving flash writes (0x01, 0x02, 0x03) and flash read (0x04) must be executed only within the same VCC voltage range detected at POR (power on, or command 0x06) and above 2.7 V. Document Number: 001-53516 Rev. *G Page 29 of 43 [+] Feedback CY8C20111, CY8C20121 13.5 DC I2C Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C < TA < 85 °C, 3.10 V to 3.6 V and –40 °C < TA < 85 °C or 2.4 V to 2.90 V and –40 °C < TA < 85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Table 7. DC I2C Specifications[9] Symbol VILI2C VIHI2C VOLP Description Input low level Input high level Low output voltage Min – – 0.7 × VDD – Typ – – – – Max 0.3 × VDD 0.25 × VDD – 0.4 Units V V V V Notes 2.4 V ≤ VDD ≤ 3.6 V 4.75 V ≤ VDD ≤ 5.25 V 2.4 V ≤ VDD ≤ 5.25 V IOL=5 mA/pin, maximum of 10 mA device sink current 2.4 ≤ VDD ≤ 2.9 V and 3.1 ≤ VDD ≤ 3.6 V. Package and pin dependent. Temp = 25 °C. CI2C RPU Capacitive load on I2C pins Pull-up resistor 0.5 4 1.7 5.6 5 8 pF kΩ 13.6 CapSense Electrical Characteristics Max (V) 3.6 Typ (V) 3.3 Min (V) 3.1 Conditions for Supply Voltage < 2.9 > 2.9 or < 3.10 2.90 2.7 2.45 < 2.45 V > 3.10 < 2.4 V 5.25 5.0 4.75 < 4.73 V Result The device automatically reconfigures itself to work in 2.7 V mode of operation. This range is not recommended for CapSense usage. The scanning for CapSense parameters shuts down until the voltage returns to over 2.45 V. The device automatically reconfigures itself to work in 3.3 V mode of operation. The device goes into reset. The scanning for CapSense parameters shuts down until the voltage returns to over 4.73 V. Notes 8. A maximum of 36 × 50,000 block endurance cycles is allowed. This is balanced between operations on 36 × 1 blocks of 50,000 maximum cycles each, 36 × 2 blocks of 25,000 maximum cycles each, or 36 × 4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36 × 50,000 and that no single block ever sees more than 50,000 cycles). 9. All GPIO meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I2C GPIO pins also meet the above specs. Document Number: 001-53516 Rev. *G Page 30 of 43 [+] Feedback CY8C20111, CY8C20121 14. AC Electrical Specifications 14.1 AC Chip-Level Specifications 14.1.1 5-V and 3.3-V AC Chip-Level Specifications Parameter F32K1 tXRST tPOWERUP SRPOWER_ UP Description Internal low-speed oscillator (ILO) frequency External reset pulse width Time from end of POR to CPU executing code Power supply slew rate Min 15 10 – – Typ 32 – 150 – Max 64 – – 250 Units kHz Us ms V/ms Notes Calculations during sleep operations are done based on ILO frequency. 14.1.2 2.7-V AC Chip-Level Specifications Parameter F32K1 tXRST tPOWERUP SRPOWER_ UP Description Internal low-speed oscillator (ILO) frequency External reset pulse width Time from end of POR to CPU executing code Power supply slew rate Min 8 10 – – Typ 32 – 600 – Max 96 – – 250 Units kHz Us ms V/ms Notes Calculations during sleep operations are done based on ILO frequency. 14.2 AC GPIO Specifications 14.2.1 5-V and 3.3-V AC GPIO Specifications Parameter tRise tFall Description Rise time, strong mode, Cload = 50 pF Fall time, strong mode, Cload = 50 pF Min 15 10 Max 80 50 Unit ns ns Notes VDD = 3.10 V to 3.6 V and 4.75 V to 5.25 V, 10% to 90% VDD = 3.10 V to 3.6 V and 4.75 V to 5.25 V, 10% to 90% 14.2.2 2.7-V AC GPIO Specifications Parameter tRise tFall Description Rise time, strong mode, Cload = 50 pF Fall time, strong mode, Cload = 50 pF Min 15 10 Max 100 70 Unit ns ns Notes VDD = 2.4 V to 2.90 V, 10% to 90% VDD = 2.4 V to 2.90 V, 10% to 90% 14.3 AC I2C Specifications Parameter FSCLI2C tHDSTAI2C tLOWI2C tHIGHI2C tSUSTAI2C Description SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Setup time for a repeated START condition Standard Mode Min 0 4.0 4.7 4.0 4.7 Max 100 – – – – Fast Mode Min 0 0.6 1.3 0.6 0.6 Max 400 – – – – kbps µs µs µs µs Fast mode not supported for VDD < 3.0 V Units Notes Document Number: 001-53516 Rev. *G Page 31 of 43 [+] Feedback CY8C20111, CY8C20121 14.3 AC I2C Specifications (continued) Parameter tHDDATI2C tSUDATI2C tSUSTOI2C tBUFI2C tSPI2C Data hold time Data setup time Setup time for STOP condition BUS free time between a STOP and START condition Pulse width of spikes suppressed by the input filter Description Standard Mode Min 0 250 4.0 4.7 – Max – – – – – Fast Mode Min 0 100 0.6 1.3 0 Max – – – – 50 µs ns µs µs ns Units Notes Figure 12. Definition of Timing for Fast/Standard Mode on the I2C Bus I2C_SDA TSUDATI2C THDSTAI2C I2C_SCL TSPI2C THDDATI2CTSUSTAI2C TBUFI2C THIGHI2C TLOWI2C S START Condition Sr Repeated START Condition TSUSTOI2C P STOP Condition S Document Number: 001-53516 Rev. *G Page 32 of 43 [+] Feedback CY8C20111, CY8C20121 15. Examples of Frequently Used I2C Commands Sl. No. 1 2 3 4 5 6 Requirement Enter into setup mode Enter into normal mode Load factory defaults to RAM registers Do a software reset Save current configuration to flash Load factory defaults to RAM registers and save as user configuration I2C Commands[10] W 00 A0 08 W 00 A0 07 W 00 A0 02 W 00 A0 08 W 00 A0 06 W 00 A0 01 W W W W 00 A0 08 00 A0 02 00 A0 01 00 A0 06 ; Enter into setup mode ; Load factory defaults to SRAM ; Save the configuration to flash. Wait for time specified in Table 6. ; Do software reset ; Enter into setup mode ; Do software reset Comment 7 8 9 10 11 12 13 Disable combinational logic output to DIG0 Disable combinational logic output to DIG1 Clearing (logic 0) the both DIG0 and DIG1 outputs Setting (logic 1) the DIG0 and clearing (Logic 0) the DIG1 outputs Clearing (logic 0) the DIG0 and Setting (Logic 1) the DIG1 outputs Setting (logic 1) the both DIG0 and DIG1 outputs Change CapSense clock to IMO/2 W 00 1C 00 W 00 21 00 W 00 04 00 W 00 04 01 W 00 04 02 W 00 04 03 W 00 A0 08 W 00 51 20 W 00 A0 07 W 00 70 x W 00 71 y W 00 70 x y W 00 66 x W 00 67 y W 00 66 x y W 00 4E x W 00 81 81 W 00 82 R 00 RD RD RD RD W 00 88 R 00 RD ; Select CapSense button for reading scan result ; Set the read point to 82h ; Consecutive 6 reads gets baseline, difference count and raw count (all two byte each) ; Set the read pointer to 88 ; Reading a byte gets status CapSense inputs ; Enter into setup mode ; CapSense clock is set as IMO/2 ; Enter into normal mode ‘x’ represents new value of IDAC register ‘y’ represents new value of IDAC register ‘x’ and ‘y’ represents new value of IDAC register ‘x’ represents new value of FT register ‘y’ represents new value of FT register ‘x’ and ‘y’ represents new value of FT registers Combinational logic output on DIG0 and DIG1 should be disabled before dong this operation (SL# 7 and 8) 14 15 16 17 18 19 20 21 Change value of IDAC0 to ‘x’h Change value of IDAC1 to ‘y’h Change value of IDAC0 and IDAC1 to ‘x’h and ‘y’h Change the value FT0 to ‘x’h Change the value FT1 to ‘y’h Change the value FT0 and FT1 to ‘x’h and ‘y’h Change noise threshold to ‘x’h Read CapSense button CS0 scan results RD RD 22 Read CapSense button status register Note 10. The ‘W’ indicates the write transfer and the next byte of data represents the 7-bit I2C address. The I2C address is assumed to be ‘0’ in the above examples. Similarly ‘R’ indicates the read transfer followed by 7-bit address and data byte read operations. Document Number: 001-53516 Rev. *G Page 33 of 43 [+] Feedback CY8C20111, CY8C20121 16. Ordering Information Ordering Code CY8C20111-SX1I CY8C20111-SX1IT CY8C20121-SX1I CY8C20121-SX1IT Package Diagram 51-85066 51-85066 51-85066 51-85066 Package Type 8-Pin SOIC 8-Pin SOIC (tape and reel) 8-Pin SOIC 8-Pin SOIC (tape and reel) Operating Temperature Industrial Industrial Industrial Industrial CapSense Blocks Yes Yes Yes Yes CapSense Inputs 1 1 2 2 Digital Outputs 1 1 2 2 XRES Pin No No No No Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE). 16.1 Ordering Code Definitions CY 8 C 201 xx - SX 1 I T Tape and Reel Thermal Rating : Industrial 8 pin pinout Package Type : SOIC Pb- Free Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress Semiconductors Company ID: CY = Cypress Thermal Impedances Table 16-1. Thermal Impedance by Package Package 8-Pin SOIC Typical θJA [11] Solder Reflow Specifications Table 16-2. Solder Reflow Specifications Package 8-Pin SOIC Maximum Peak Temperature (TC) 260 °C Maximum Time above TC – 5 °C 30 seconds 127.22 °C/W Note 11. TJ = TA + Power x θJA. Document Number: 001-53516 Rev. *G Page 34 of 43 [+] Feedback CY8C20111, CY8C20121 17. Package Diagram Figure 13. 8-Pin (150-Mil) SOIC (51-85066) 51-85066 *E Document Number: 001-53516 Rev. *G Page 35 of 43 [+] Feedback CY8C20111, CY8C20121 18. Acronyms 18.1 Acronyms Used Table 8 lists the acronyms that are used in this document. Table 8. Acronyms Used in this Datasheet Acronym Description Acronym Description AC CMOS CRC CSA CSD DC EEPROM EMC GPIO I/O IDAC ILO IMO LCD LDO LED LSB alternating current complementary metal oxide semiconductor cyclic redundancy check capsense successive approximation capsense sigma delta direct current electrically erasable programmable read-only memory electromagnetic compatibility general-purpose I/O input/output current DAC internal low speed oscillator internal main oscillator liquid crystal display low dropout regulator light-emitting diode least-significant bit LVD PCB PGA POR PPOR PSoC® PWM QFN SLIMO SPITM SRAM SROM SSOP USB WDT WLCSP XRES low voltage detect printed circuit board programmable gain amplifier power on reset precision power on reset Programmable System-on-Chip pulse width modulator quad flat no leads slow IMO serial peripheral interface static random access memory supervisory read only memory shrink small-outline package universal serial bus watchdog timer wafer level chip scale package external reset 19. Document Conventions 19.1 Units of Measure Table 9 lists the units of measures. Table 9. Units of Measure Symbol Unit of Measure Symbol Unit of Measure °C kbps kHz kΩ LSB µA µs mA degree Celsius kilo bits per second kilohertz kilohm least significant bit microampere microsecond milliampere mm ms nA ns % pF V W millimeter millisecond nanoampere nanosecond percent picofarad volts watt 19.2 Numeric Conventions Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals. Document Number: 001-53516 Rev. *G Page 36 of 43 [+] Feedback CY8C20111, CY8C20121 20. Glossary active high 1. A logic signal having its asserted state as the logic 1 state. 2. A logic signal having the logic 1 state as the higher voltage of the two states. The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more. A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation. A series of software routines that comprise an interface between a computer application and lower level services and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create software applications. A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. A stable voltage reference design that matches the positive temperature coefficient of VT with the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference. 1. The frequency range of a message or information processing system measured in hertz. 2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. 1. A systematic deviation of a value from a reference value. 2. The amount by which the average of a set of values departs from a reference value. 3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. 1. A functional unit that performs a single function, such as an oscillator. 2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or an analog PSoC block. 1. A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for I/O operations, into which data is read, or from which data is written. 2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. An amplifier used to lower the output impedance of a system. 1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0]. 3. One or more conductors that serve as a common connection for a group of related devices. The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks. An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. analog blocks analog-to-digital (ADC) Application programming interface (API) asynchronous Bandgap reference bandwidth bias block buffer bus clock comparator Document Number: 001-53516 Rev. *G Page 37 of 43 [+] Feedback CY8C20111, CY8C20121 20. Glossary (continued) compiler configuration space crystal oscillator A program that translates a high level language, such as C, into machine language. In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’. An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear check (CRC) feedback shift register. Similar calculations may be used for a variety of other purposes such as data compression. data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions. A hardware and software system that allows you to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. A period of time when neither of two or more signals are in their active state or in transition. The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator, pseudo-random number generator, or SPI. A device that changes a digital signal to an analog signal of corresponding magnitude. The analogto-digital (ADC) converter performs the reverse operation. The relationship of a clock period high time to its low time, expressed as a percent. Duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop and return to a pre-defined state. An electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is OFF. The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash space that may be protected. A Flash block holds 64 bytes. The number of cycles or events per unit of time, for a periodic function. The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually expressed in dB. A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5V and pulled high with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. debugger dead band digital blocks digital-to-analog (DAC) duty cycle emulator External Reset (XRES) Flash Flash block frequency gain I2C Document Number: 001-53516 Rev. *G Page 38 of 43 [+] Feedback CY8C20111, CY8C20121 20. Glossary (continued) ICE The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (PSoC Designer). input/output (I/O) A device that introduces data into or extracts data from a system. interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends with the RETI instruction, returning the device to the point in the program where it left normal program execution. 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on serial data streams. 2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles. interrupt service routine (ISR) jitter low-voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a selected threshold. (LVD) M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the Flash, SRAM, and register space. A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device. An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and I/O circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor. The reference to a circuit containing both analog and digital techniques and components. A device that imposes a signal on a carrier. 1. A disturbance that affects a signal and that may distort the information carried by the signal. 2. The random variations of one or more characteristics of any entity such as voltage, current, or data. A circuit that may be crystal controlled and is used to generate a clock frequency. A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names. Page 39 of 43 master device microcontroller mixed-signal modulator noise oscillator parity Phase-locked loop (PLL) pinouts Document Number: 001-53516 Rev. *G [+] Feedback CY8C20111, CY8C20121 20. Glossary (continued) port Power on reset (POR) PSoC® A group of pins, usually eight. A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is a type of hardware reset. Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark of Cypress. PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology. pulse width An output in the form of duty cycle which varies as a function of the applied measurand modulator (PWM) RAM An acronym for random access memory. A data-storage device from which data can be read out and new data can be written in. A storage device with a specific capacity, such as a bit or byte. A means of bringing a system back to a know state. See hardware reset and software reset. An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in. 1. Pertaining to a process in which all events occur one after the other. 2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. The time it takes for an output signal or value to stabilize after the input has changed from one value to another. A memory storage device that sequentially shifts a word either left or right to output a stream of serial data. A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. The controlling device is called the master device. An acronym for static random access memory. A memory device where you can store and retrieve data at a high rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is removed from the device. An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code, operating from Flash. A signal following a character or block that prepares the receiving device to receive the next character or block. 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. A system whose operation is synchronized by a clock signal. register reset ROM serial settling time shift register slave device SRAM SROM stop bit synchronous Document Number: 001-53516 Rev. *G Page 40 of 43 [+] Feedback CY8C20111, CY8C20121 20. Glossary (continued) tri-state A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming Interface) for the peripheral function. The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program. A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V. A name for a power net meaning "voltage source." The most negative power supply signal. A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time. UART user modules user space VDD VSS watchdog timer Document Number: 001-53516 Rev. *G Page 41 of 43 [+] Feedback CY8C20111, CY8C20121 21. Document History Page Document Title: CY8C20111, CY8C20121 CapSense® Express™ - One Button and Two Button Capacitive Controllers Document Number: 001-53516 Rev. ** *A ECN No. 2709248 2821828 Orig. of Change SLAN/PYRS SSHH/FSU Submission Date See ECN 12/4/2009 New data sheet - Added Contents - Changed values in the Registers table. - Added the OUTPUT_STATUS register. - The note about flash writes must be performed at POR voltage also applies to flash reads. - Added new electrical specs including Tpowerup and output current. Description of Change *B *C 2868929 2892629 SLAN NJF 01/28/2010 Converted from Preliminary to Final. Updated package diagram. 03/15/2010 Added TBAKETEMP and TBAKETIME parameters in Absolute Maximum Ratings. Added the following tables: Thermal Impedance by Package and Solder Reflow Specifications. 09/30/10 Removed F32ku and tpowerup rows from Absolute Maximum Ratings table. Included “AC Chip-Level Specifications” section under “AC Electrical Specifications” section Removed section “2.7-V DC Spec for I2C Line with 1.8 V External Pull-up”. Added DC I2C Specifications table and DC Programming Specifications. Updated Units of Measure, Acronyms, and Glossary sections. Updated solder reflow specifications. No specific changes were made to I2C Timing Diagram. Updated for clearer understanding. Template and styles update. In table under 9th section, deleted the 18th row (Overlay thickness-buttons) In “CapSense Constraints” table, deleted the 2nd row (Overlay thickness) Added following statement after table under 9th section - “The Recommended maximum overlay thickness is 2 mm. For more details refer to AN53490, section: The Integrating Capacitor.” Updated Solder reflow specifications. Posting to external web. *D 3043236 ARVM *E 3087790 NJF 11/16/10 *F 3148656 ARVM 01/20/11 *G 3287607 ARVM 06/20/11 Document Number: 001-53516 Rev. *G Page 42 of 43 [+] Feedback CY8C20111, CY8C20121 22. Sales, Solutions, and Legal Information 22.1 Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-53516 Rev. *G Revised June 24, 2011 Page 43 of 43 CapSense Express™, PSoC Designer™, and Programmable System-on-Chip™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback