CY8C20160-LDX2I

CY8C20160 CapSense Express™ - 6 Configurable IOs Features ■ Overview The CapSense Express™ controller allows the control of six IOs configurable as capacitive sensing buttons or as GPIOs for driving LEDs or interrupt signals based on various button conditions. The GPIOs are also configurable for waking up the device from sleep based on an interrupt input. The user has the ability to configure buttons, outputs, and parameters, through specific commands sent to the I2C port. The IOs have the flexibility of mapping to capacitive buttons and as standard GPIO functions such as interrupt output or input, LED drive, and digital mapping of input to output using simple logical operations. This enables easy PCB trace routing and reduces the PCB size and stack up. CapSense Express products are designed for easy integration into complex products. 6 configurable IOs supporting ❐ CapSense™ buttons ❐ LED drive ❐ Interrupt outputs ❐ WAKE on interrupt input ❐ Bi-directional sleep control pin ❐ User defined input or output 2.4V to 2.9V, 3.10V to 3.6V, and 4.75V to 5.25V operating voltage Industrial temperature range: –40°C to +85°C I2C slave interface for configuration 2 ❐ I C data transfer rate up to 400 kbps Reduce BOM cost ❐ Internal oscillator - no external oscillators or crystal ❐ Free development tool - no external tuning components Low operating current ❐ Active current: 1.5 mA ❐ Deep sleep current: 2.6 uA Available in 16-pin COL and 16-pin SOIC packages ■ ■ ■ ■ Architecture The logic block diagram shows the internal architecture of CY8C20160. The user can configure registers with parameters needed to adjust the operation and sensitivity of the CapSense system. CY8C20160 supports a standard I²C serial communication interface that allows the host to configure the device and to read sensor information in real time through easy register access. ■ ■ The CapSense Express Core The CapSense Express core has a powerful configuration and control block. It encompasses SRAM for data storage, an interrupt controller, and sleep and watchdog timers. System resources provide additional capability, such as a configurable I2C slave communication interface and various system resets. The Analog System contains the CapSense PSoC block which supports capacitive sensing of up to six inputs. Cypress Semiconductor Corporation Document Number:001-17347 Rev. *F • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 28, 2009 [+] Feedback CY8C20160 Logic Block Diagram External VCC 2.40V to 2.90V, 3.10V to 3.60V, 4.75V to 5.25V CapSense ExpressTM Core SYSTEM BUS 6 Configurable IOs 512B SRAM 2 KB Flash Interrupt Controller Configuration and Control Engine Sleep and Watchdog Clock Sources (Internal Main Oscillator) SYSTEM BUS CapSense Block I2C Slave Voltage & Current Reference System Reset POR/LVD Document Number:001-17347 Rev. *F Page 2 of 15 [+] Feedback CY8C20160 Pinouts Figure 1. Pin Diagram - 16 Pin COL COL (TOP VIEW) Table 1. Pin Definitions - 16 Pin COL[1] Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name GP0[0] GP0[1] I 2C Description Configurable as CapSense or GPIO Configurable as CapSense or GPIO I2C clock I2C data Configurable as CapSense or GPIO Configurable as CapSense or GPIO Ground connection Configurable as CapSense or GPIO Configurable as CapSense or GPIO Configurable as CapSense or GPIO Active HIGH external reset with internal pull down Configurable as CapSense or GPIO Supply voltage Configurable as CapSense or GPIO Integrating capacitor input. The external capacitance is required only if 5:1 SNR cannot be achieved. Typical range is 10 nF to 100 nF Configurable as CapSense or GPIO SCL I2C SDA GP1[0] GP1[1] VSS GP1[2] GP1[3] GP1[4] XRES GP0[2] VDD GP0[3] CSInt GP0[4] Note 1. 6 available Configurable IOs can be configured to any of the 10 IOs of the package. After any of the 6 IOs are chosen, the remaining 4 IOs of the package get locked and is not available for any functionality. Document Number:001-17347 Rev. *F Page 3 of 15 [+] Feedback CY8C20160 Figure 2. Pin Diagram - 16 Pin SOIC GP0[3] CSInt GP0[4] GP0[0] GP0[1] I2CSCL I2CSDA GP1[0] Table 2. Pin Definitions - 16 Pin SOIC[1] Pin Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I Name GP0[3] CSInt GP0[4] GP0[0] GP0[1] 2C 1 2 3 4 5 6 7 8 16 15 14 VDD GP0[2] XRES GP1[4] GP1[3] GP1[2] VSS GP1[1] SOIC (Top View) 13 12 11 10 9 Description Configurable as CapSense or GPIO Integrating Capacitor Input. The external capacitance is required only if 5:1 SNR cannot be achieved. Typical range is 10 nF to 100 nF Configurable as CapSense or GPIO Configurable as CapSense or GPIO Configurable as CapSense or GPIO I2C clock I2C data Configurable as CapSense or GPIO Configurable as CapSense or GPIO Ground connection Configurable as CapSense or GPIO Configurable as CapSense or GPIO Configurable as CapSense or GPIO Active HIGH external reset with internal pull down Configurable as CapSense or GPIO Supply voltage SCL I2C SDA GP1[0] GP1[1] VSS GP1[2] GP1[3] GP1[4] XRES GP0[2] VDD Document Number:001-17347 Rev. *F Page 4 of 15 [+] Feedback CY8C20160 The CapSense Analog System The CapSense analog system contains the capacitive sensing hardware which supports CapSense Successive Approximation (CSA) algorithm. This hardware performs capacitive sensing and scanning without external components. Capacitive sensing is configurable on each pin. I2C Interface The two modes of operation for the I2C interface are: ■ ■ Device register configuration and status read or write for controller Command execution Additional System Resources System Resources provide additional capability useful to complete systems. Additional resources are low voltage detection and Power On Reset (POR). ■ ■ The I2C address is programmable during configuration. It can be locked to prevent accidental change by setting a flag in a configuration register. I2C Device Addressing I2C device address is contained in the upper seven bits of the first byte of a read or write transaction. The first byte of the transaction is used by the I2C master to address the slave. The LSB of the byte contains the R/W bit. If this bit is 0, the master performs write operation to the addressed slave. If this bit is 1, the master performs read operation from the addressed slave. The LSB(B0) is eliminated when fixing the device address. For example, if the slave address is 02h, then the required address is 0000010 (7 bit) excluding LSB. If write operation is performed, the LSB is 0 and the address is 00000100(04h). If read operation is performed, the LSB is 1 and the address is 00000101(05h). Table 3 provides examples of I2C addressing. The I2C slave provides 50, 100, or 400 kHz communication over two wires. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels and the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.8V reference provides a stable internal reference so that capacitive sensing functionality is not affected by minor VDD changes. Table 3. Examples of I2C Addressing Slave Address Defined 0 0 1 1 10 10 75 75 127 127 B7 0 0 0 0 0 0 1 1 1 1 B6 0 0 0 0 0 0 0 0 1 1 B5 0 0 0 0 0 0 0 0 1 1 B4 0 0 0 0 1 1 1 1 1 1 B3 0 0 0 0 0 0 0 0 1 1 B2 0 0 0 0 1 1 1 1 1 1 B1 0 0 1 1 0 0 1 1 1 1 B0 0(W) 1(R) 0(W) 1(R) 0(W) 1(R) 0(W) 1(R) 0(W) 1(R) Address to be sent (in Hex) by Master 00 01 02 03 14 15 96 97 FE FF CapSense Express Software Tool An easy to use software tool integrated with PSoC Express is available for configuring and tuning CapSense Express devices. Refer to the application note “CapSense™ Express Software Tool - AN42137” for details of the software tool. CapSense Express Register Map CapSense Express supports user configurable registers through which the device functionality and parameters are configured. For details, refer to the CY8C201xx Register Reference Guide. Document Number:001-17347 Rev. *F Page 5 of 15 [+] Feedback CY8C20160 Modes of Operation CapSense Express devices are configured to operate in any of the following three modes to meet different power consumption requirements: ■ ■ ■ Deep Sleep Mode Deep sleep mode provides the lowest power consumption because there is no operation running. In this mode, the device is woken up only using an external GPIO interrupt. A sleep timer interrupt cannot wake up a device from deep sleep mode. This can be treated as a continuous sleep mode without periodic wakeups. Refer to the application note “CapSense Express Power and Sleep Considerations - AN44209” for details on different sleep modes. Active Mode Sleep Mode Deep Sleep Mode Active Mode In the active mode, all the device blocks including the CapSense sub system are powered. Typical active current consumption of the device across the operating voltage range is 1.5 mA. Bi-Directional Sleep Control Pin The CY8C20160 requires a dedicated sleep control pin to allow reliable I2C communication in case any sleep mode is enabled. This is achieved by pulling the sleep control pin LOW to wake up the device and start I2C communication. The sleep control pin can be configured on any of the GPIO. If sleep control feature is enabled, the device has one less GPIO available for CapSense and GPIO functions. The sleep control pin can also be configured as interrupt output pin from CY8C20160 to the host to acknowledge finger press on any button. To enable bi-directional feature, user must use I2C-USB bridge program. Sleep Mode Sleep mode provides an intermediate power operation mode. It is enabled by configuring the corresponding device register. When enabled, the device enters sleep mode and wakes up after a specified sleep interval. It scans the capacitive sensors before going back to sleep again. The device can also wake up from sleep mode with a GPIO interrupt. The following sleep intervals are supported in CapSense Express. The sleep interval is configured through registers. ■ ■ ■ ■ 1.95 ms (512 Hz) 15.6 ms (64 Hz) 125 ms (8 Hz) 1s (1 Hz) Document Number:001-17347 Rev. *F Page 6 of 15 [+] Feedback CY8C20160 Electrical Specifications Absolute Maximum Ratings Parameter TSTG Description Storage temperature Min –55 Typ 25 Max +100 Unit °C Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is +25°C ± 25°C (0°C to 50°C). Extended duration storage temperatures above 65°C degrade reliability TA VDD VIO VIOZ IMIO ESD LU Ambient temperature with power applied Supply voltage on VDD relative to VSS DC input voltage DC voltage applied to tri-state Maximum current into any GPIO pin Electro static discharge voltage Latch up current –40 –0.5 VSS – 0.5 VSS – 0.5 –25 2000 – – – – – – – – +85 +6.0 VDD + 0.5 VDD + 0.5 +50 – 200 °C V V V mA V mA Human body model ESD Operating Temperature Parameter TA TJ Description Ambient temperature Junction temperature Min –40 °40 Typ – – Max +85 +100 Unit °C °C Notes DC Electrical Characteristics DC Chip Level Specifications Parameter VDD IDD ISB Description Supply voltage Supply current Deep sleep mode current with POR and LVD active. Mid temperature range Deep seep mode current with POR and LVD active Deep sleep mode current with POR and LVD active Min 2.40 – – Typ – 1.5 2.6 Max 5.25 2.5 4 Unit V mA µA Conditions are VDD = 3.10V, TA = 25°C VDD = 2.55V, 0°C < TA < 40°C Notes ISB ISB – – 2.8 5.2 5 6.4 µA µA VDD = 3.3V, –40°C < TA < 85°C VDD = 5.25V, –40°C < TA < 85°C Document Number:001-17347 Rev. *F Page 7 of 15 [+] Feedback CY8C20160 5V and 3.3V DC General Purpose IO Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C 3.10V, maximum of 20 mA source current in all IOs. IOL = 20 mA, VDD> 3.10V, maximum of 60 mA sink current on even port pins and 60 mA sink current on odd port pins. VDD = 3.10V to 3.6V. Gross tested to 1 µA. Package and pin dependent. Temp = 25°C. Package and pin dependent. Temp = 25°C. Notes VIL IL CIN COUT Input low voltage Input leakage Capacitive load on pins as input Capacitive load on pins as output – – 0.5 0.5 – 1 1.7 1.7 0.75 – 5 5 V nA pF pF 2.7V DC General Purpose IO Specifications This table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 2.4V to 2.90V and -40°C