CY8C20224_11

CapSense PSoC Programmable System-on-Chip™ CapSense® PSoC® Programmable System-on-Chip CY8C20224, CY8C20324 CY8C20424, CY8C20524 ® ® Features ■ ■ Low power, configurable CapSense® ❐ Configurable capacitive sensing elements ❐ operating voltage ❐ Operating voltage: 2.4 V to 5.25 V ❐ Low operating current • Active 1.5 mA (at 3.0 V, 12 MHz) • Sleep 2.8 µA (at 3.3 V) ❐ Supports up to 25 capacitive buttons ❐ Supports one slider ❐ Up to 10 cm proximity sensing ❐ Supports up to 28 general-purpose I/O (GPIO) pins • Drive LEDs and other outputs ❐ Configurable LED behavior (fading, strobing) ❐ LED color mixing (RBG LEDs) ❐ Pull-up, high Z, open-drain, and CMOS drive modes on all GPIOs ❐ Internal ±5.0% 6 or12 MHz main oscillator ❐ Internal low-speed oscillator at 32 kHz ❐ Low external component count • No external crystal or oscillator components • No external voltage regulator required High-performance CapSense ❐ Ultra fast scan speed —1 kHz (nominal) ❐ Reliable finger detection through 5 mm thick acrylic ❐ Excellent EMI and AC noise immunity Industry best flexibility ❐ 8 KB flash program storage 50,000 erase and write cycles ❐ 512-bytes SRAM data storage ❐ Bootloader for ease of field reprogramming ❐ Partial flash updates ❐ Flexible flash protection modes ❐ Interrupt controller ❐ In-system serial programming (ISSP) ❐ Free complete development tool (PSoC Designer™) ❐ Full-featured, in-circuit emulator and programmer • Full-speed emulation • Complex breakpoint structure • 128 KB trace memory Additional system resources ❐ Configurable communication speeds 2 ❐ I C slave ❐ SPI master and SPI slave ❐ Watchdog and sleep timers ❐ Internal voltage reference ❐ Integrated supervisory circuit ■ ■ Logic Block Diagram Port 3 Port 2 Port 1 Port 0 3V LDO PSoC CORE System Bus Global Analog Interconnect SRAM 512 Bytes Interrupt Controller SROM Flash 8K Sleep and Watchdog CPU Core (M8C) 6/12 MHz Internal Main Oscillator ANALOG SYSTEM CapSense Basic Block Analog Ref. I2C Slave/SPI Master-Slave POR and LVD System Resets Analog Mux SYSTEM RESOURCES Cypress Semiconductor Corporation Document Number: 001-41947 Rev. *K • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 1, 2011 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 Contents CapSense® PSoC® Programmable System-on-Chip .... 1 Features ............................................................................. 1 Logic Block Diagram ........................................................ 1 PSoC® Functional Overview ............................................ 3 PSoC Core .................................................................. 3 CapSense Analog System .......................................... 3 Additional System Resources ..................................... 4 Getting Started .................................................................. 4 Application Notes ........................................................ 4 Development Kits ........................................................ 4 Training ....................................................................... 4 CYPros Consultants .................................................... 4 Solutions Library .......................................................... 4 Technical Support ....................................................... 4 Development Tools .......................................................... 5 PSoC Designer Software Subsystems ........................ 5 Designing with PSoC Designer ....................................... 6 Select User Modules ................................................... 6 Configure User Modules .............................................. 6 Organize and Connect ................................................ 6 Generate, Verify, and Debug ....................................... 6 Pinouts .............................................................................. 7 16-pin Part Pinout ........................................................ 7 24-pin Part Pinout ........................................................ 8 28-pin Part Pinout ........................................................ 9 32-pin Part Pinout ...................................................... 10 48-pin OCD Part Pinout ............................................. 12 Electrical Specifications ................................................ 14 Absolute Maximum Ratings .......................................... 14 Operating Temperature .................................................. 14 DC Electrical Characteristics ........................................ 15 AC Electrical Characteristics ........................................ 19 Ordering Information ...................................................... 26 Ordering Code Definitions ......................................... 26 Packaging Dimensions .................................................. 27 Thermal Impedances ................................................ 30 Solder Reflow Peak Temperature ............................. 30 Development Tool Selection ......................................... 31 Software .................................................................... 31 Development Kits ...................................................... 31 Evaluation Tools ........................................................ 31 Device Programmers ................................................. 32 Accessories (Emulation and Programming) .............. 32 Acronyms ........................................................................ 33 Acronyms Used ......................................................... 33 Reference Documents .................................................... 33 Document Conventions ................................................. 34 Units of Measure ....................................................... 34 Numeric Conventions ................................................ 34 Glossary .......................................................................... 34 Document History Page ................................................. 39 Sales, Solutions, and Legal Information ...................... 40 Worldwide Sales and Design Support ....................... 40 Products .................................................................... 40 PSoC Solutions ......................................................... 40 Document Number: 001-41947 Rev. *K Page 2 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 PSoC® Functional Overview The PSoC family consists of many programmable system-on-chips with on-chip controller devices. These devices are designed to replace multiple traditional MCU based system components with one, low cost single chip programmable component. A PSoC device includes configurable analog and digital blocks, and programmable interconnect. This architecture enables the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. The PSoC architecture for this device family is comprised of three main areas: core, system resources, and CapSense analog system. A common, versatile bus enables connection between I/O and the analog system. Each CY8C20x24 PSoC device includes a dedicated CapSense block that provides sensing and scanning control circuitry for capacitive sensing applications. Depending on the PSoC package, up to 28 GPIOs are also included. The GPIOs provide access to the MCU and analog mux. Figure 1. Analog System Block Diagram IDAC Analog Global Bus Vr Reference Buffer Cinternal Comparator Mux Mux Refs PSoC Core The PSoC core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and internal main oscillator (IMO) and internal low-speed oscillator (ILO). The CPU core, called the M8C, is a powerful processor with speeds up to 12 MHz. The M8C is a 2-MIPS, 8-bit Harvard-architecture microprocessor. System resources provide additional capability, such as a configurable I2C slave or SPI master-slave communication interface and various system resets supported by the M8C. The analog system is composed of the CapSense PSoC block and an internal 1.8-V analog reference. Together, they support capacitive sensing of up to 28 inputs. Cap Sense Counters CSCLK IMO CapSense Clock Select Relaxation Oscillator (RO) Analog Multiplexer System The analog mux bus connects to every GPIO pin. Pins are connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with the CapSense block comparator. Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. The analog multiplexer system in the CY8C20x24 device family is optimized for basic CapSense functionality. It supports sensing of CapSense buttons, proximity sensors, and a single slider. Other multiplexer applications include: ■ ■ ■ CapSense Analog System The analog system contains the capacitive sensing hardware. Several hardware algorithms are supported. This hardware performs capacitive sensing and scanning without requiring external components. Capacitive sensing is configurable on each GPIO pin. Scanning of enabled CapSense pins are completed quickly and easily across multiple ports. Capacitive slider interface. Chip-wide mux that enables analog input from any I/O pin. Crosspoint connection between any I/O pin combinations. When designing capacitive sensing applications, refer to the latest signal to noise signal level requirements application notes, which are found in http://www.cypress.com > Design Resources > Application Notes. In general, and unless otherwise noted in the relevant application notes, the minimum signal-to-noise ratio (SNR) requirement for CapSense applications is 5:1. Document Number: 001-41947 Rev. *K Page 3 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 Typical Application Figure 2 illustrates a typical application: CapSense multimedia keys for a notebook computer with a slider, four buttons, and four LEDs. Figure 2. CapSense Multimedia Button-Board Application Getting Started This datasheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, see the PSoC® CY8C20x24, CY8C20x34 Technical Reference Manual (TRM) for this PSoC device. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device data sheets on the web at http://www.cypress.com. Application Notes Application notes are an excellent introduction to the wide variety of possible PSoC designs and are available at http://www.cypress.com. Additional System Resources System resources, some of which are previously listed, provide additional capability useful to complete systems. Additional resources include low voltage detection (LVD) and power on reset (POR). Brief statements describing the merits of each system resource follow. ■ Development Kits PSoC development kits are available online from Cypress at http://www.cypress.com and through a growing number of regional and global distributors, including Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Training Free PSoC technical training (on demand, webinars, and workshops) is available online at http://www.cypress.com. The training covers a wide variety of topics and skill levels to assist you in your designs. The slave and SPI master-slave module provides 50, 100, or 400 kHz communication over two wires. SPI communication over three or four wires runs at speeds of 46.9 kHz to 3 MHz (lower for a slower system clock). LVD interrupts signal the application of falling voltage levels, while the advanced POR circuit eliminates the need for a system supervisor. An internal 1.8-V reference provides an absolute reference for capacitive sensing. The 5 V maximum input, 3 V fixed output, low dropout regulator (LDO) provides regulation for I/Os. A register controlled bypass mode enables the user to disable the LDO. I2C ■ CYPros Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant, go to http://www.cypress.com and look for CYPros Consultants. ■ ■ Solutions Library Visit our growing library of solution-focused designs at http://www.cypress.com. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Technical Support For assistance with technical issues, search KnowledgeBase articles and forums at http://www.cypress.com. If you cannot find an answer to your question, call technical support at 1-800-541-4736. Document Number: 001-41947 Rev. *K Page 4 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 Development Tools PSoC Designer™ is the revolutionary Integrated Design Environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes: ■ ■ ■ ■ ■ ■ ■ Code Generation Tools The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. You can develop your design in C, assembly, or a combination of the two. Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows you to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer. In-Circuit Emulator A low-cost, high-functionality In-Circuit Emulator (ICE) is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24-MHz) operation. Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration Extensive user module catalog Integrated source-code editor (C and assembly) Free C compiler with no size restrictions or time limits Built-in debugger In-circuit emulation Built-in support for communication interfaces: 2 ❐ Hardware and software I C slaves and masters ❐ Full-speed USB 2.0 ❐ Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7. PSoC Designer Software Subsystems Design Entry In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use the PSoC blocks, which are called user modules. Examples of user modules are analog-to-digital converters (ADCs), digital-to-analog converters (DACs), amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this allows you to use more than 100 percent of PSoC's resources for a given application. Document Number: 001-41947 Rev. *K Page 5 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed-function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and lowering inventory costs. These configurable resources, called PSoC blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is: 1. Select user modules. 2. Configure user modules. 3. Organize and connect. 4. Generate, verify, and debug. Organize and Connect Build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. Perform the selection, configuration, and routing so that you have complete control over all on-chip resources. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, perform the “Generate Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides APIs with high-level functions to control and respond to hardware events at run time, and interrupt service routines that you can adapt as needed. A complete code development environment allows you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside PSoC Designer's Debugger (accessed by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer. It allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals Select User Modules PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called “user modules.” User modules make selecting and implementing peripheral devices, both analog and digital, simple. Configure User Modules Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a Pulse Width Modulator (PWM) User Module configures one or more digital PSoC blocks, one for each eight bits of resolution. Using these parameters, you can establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All of the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module data sheets explain the internal operation of the user module and provide performance specifications. Each datasheet describes the use of each user module parameter, and other information that you may need to successfully implement your design. Document Number: 001-41947 Rev. *K Page 6 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 Pinouts This section describes, lists, and illustrates the CY8C20224, CY8C20324, CY8C20424, and CY8C20524 PSoC device pins and pinout configurations. The CY8C20x24 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of digital I/O and connection to the common analog bus. However, VSS, VDD, and XRES are not capable of Digital I/O. 16-pin Part Pinout Figure 3. CY8C20224 16-pin PSoC Device P0[3], AI 15 P0[1], AI P0[7], AI 14 16 A I, P 2 [5 ] A I, P 2 [1 ] A I, I2 C S C L , S P I S S , P 1 [7 ] A I, I2 C S D A , S P I M IS O , P 1 [5 ] 5 6 7 CLK, I2C SCL, SPI MOSI P1[1] AI, SPI CLK, P1[3] Vss Table 1. 16-pin Part Pinout (COL) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Digital I/O I/O IOH IOH IOH IOH Power IOH IOH IOH Input I/O Power I/O I/O I/O I I I I I I I Analog I I I I I I Name P2[5] P2[1] P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] XRES P0[4] VDD P0[7] P0[3] P0[1] Description I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK CLK[1], I2C SCL, SPI MOSI Ground connection DATA[1], I2C SDA Optional external clock input (EXTCLK) Active high external reset with internal pull-down Supply voltage Integrating input Integrating input A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive Note 1. These are the ISSP pins, that are not high Z at POR (Power on reset). Refer the PSoC Programmable System-on-Chip Technical Reference Manual for details. Document Number: 001-41947 Rev. *K AI, DATA, I2C SDA, P1[0] 8 1 2 3 4 13 Vdd 12 9 P 0 [4 ], A I XRES P 1 [4 ], A I, E X T C L K P 1 [2 ], A I QFN 11 (T o p V ie w ) 1 0 Page 7 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 24-pin Part Pinout Figure 4. CY8C20324 24-pin PSoC Device P0[1], AI P0[3], AI P0[5], AI P0[7], AI Vdd P0[6], AI 20 19 AI, EXTCLK, P1[4] 10 11 12 18 17 16 15 14 13 P0[4], AI P0[2], AI P0[0], AI P2[0], AI XRES P1[6], AI Table 2. 24-pin Part Pinout (QFN [2]) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CP Digital I/O I/O I/O IOH IOH IOH IOH Power IOH IOH IOH IOH Input I/O I/O I/O I/O I/O Power I/O I/O I/O I/O Power I I I I I I I I I I I I I Analog I I I I I I I Name P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] NC VSS P1[0] P1[2] P1[4] P1[6] XRES P2[0] P0[0] P0[2] P0[4] P0[6] VDD P0[7] P0[5] P0[3] P0[1] Vss Description I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK CLK[3], I2C SCL, SPI MOSI No connection Ground connection DATA[3], I2C SDA Optional external clock input (EXTCLK) Active high external reset with internal pull-down Supply voltage Integrating input Integrating input Center pad is connected to ground A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive Notes 2. The center pad on the QFN package is connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it is electrically floated and not connected to any other signal. 3. These are the ISSP pins, that are not high Z at POR (Power on reset). Refer the PSoC Programmable System-on-Chip Technical Reference Manual for details. Document Number: 001-41947 Rev. *K Vss AI, DATA*, I2C SDA, P1[0] AI, P1[2] AI, CLK*, I2C SCL SPI MOSI, P1[1] NC 7 8 9 AI, AI, AI, AI, I2C SCL, SPI SS, AI, I2C SDA, SPI MISO, AI, SPI CLK, P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] 1 2 QFN 3 4 (Top View) 5 6 24 23 22 21 Page 8 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 28-pin Part Pinout Figure 5. CY8C20524 28-pin PSoC Device Table 3. 28-pin Part Pinout (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Digital Analog I/O I I/O I I/O I I/O I I/O I I/O I I/O I I/O I Power IOH I IOH IOH IOH Power IOH IOH IOH IOH Input I/O I/O I/O I/O I/O I/O I/O I/O Power I I I I I I I I I I I I I I I Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] VSS P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD Description Integrating input Integrating input Ground connection I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK CLK[4], I2C SCL, SPL MOSI Ground connection Data[4], I2C SDA Optional external clock input (EXTCLK) Active high external reset with internal pull-down Supply voltage A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive Note 4. These are the ISSP pins, that are not high Z at POR (Power on reset). Refer the PSoC Programmable System-on-Chip Technical Reference Manual for details. Document Number: 001-41947 Rev. *K Page 9 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 32-pin Part Pinout Figure 6. CY8C20424 32-pin PSoC Device P0[3], AI P0[7], AI P0[6], AI 27 P0[4], AI 26 P0[5], AI P0[2], AI 25 31 32 30 29 A I, A I, A I, A I, A I, A I, P 0 [1 ] P 2 [7 ] P 2 [5 ] P 2 [3 ] P 2 [1 ] P 3 [3 ] 28 Vdd Vss A I, P 3 [1 ] S P I S S , P 1 [7 ] A I, I2 C S C L 1 2 3 4 5 6 7 8 Q FN (T o p V ie w ) 13 14 15 10 11 AI, I2C SDA, SPI MISO, P1[5] AI, SPI CLK, P1[3] 12 AI, CLK*, I2C SCL, SPI MOSI, P1[1] AI, DATA*, I2C SDA, P1[0] AI, EXTCLK, P1[4] AI, P1[2] Table 4. 32-pin Part Pinout (QFN [5]) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 I/O I/O I/O I/O IOH IOH IOH IOH Input I I I I Digital I/O I/O I/O I/O I/O I/O I/O IOH IOH IOH IOH Power I I I I Analog I I I I I I I I I I I Name P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2] Active high external reset with internal pull-down Optional external clock input (EXTCLK) I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK CLK[6], I2C SCL, SPI MOSI Ground connection DATA[6], I2C SDA Integrating Input Description Notes 5. The center pad on the QFN package is connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it is electrically floated and not connected to any other signal. 6. These are the ISSP pins, that are not high Z at POR (Power on reset). Refer the PSoC Programmable System-on-Chip Technical Reference Manual for details. Document Number: 001-41947 Rev. *K AI, P1[6] Vss 16 9 24 23 22 21 20 19 18 17 P 0 [0 ], A I P 2 [6 ], A I P 2 [4 ], A I P 2 [2 ], A I P 2 [0 ], A I P 3 [2 ], A I P 3 [0 ], A I XRES Page 10 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 Table 4. 32-pin Part Pinout (QFN [5]) (continued) Pin No. 22 23 24 25 26 27 28 29 30 31 32 CP I/O I/O I/O Power Power Digital I/O I/O I/O I/O I/O I/O Power I I I Analog I I I I I I Name P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD P0[7] P0[5] P0[3] VSS VSS Integrating input Ground connection Center pad is connected to ground Supply voltage Description A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive Document Number: 001-41947 Rev. *K Page 11 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 48-pin OCD Part Pinout The 48-pin QFN part table and pin diagram is for the CY8C20024 On-Chip Debug (OCD) PSoC device. This part is only used for in-circuit debugging. It is NOT available for production. Figure 7. CY8C20024 OCD PSoC Device NC Vss P0[3], AI P0[5], AI P0[7], AI P0[6], AI NC 39 OCDO Vdd OCDE NC 38 NC 37 36 35 34 33 32 31 30 29 28 27 26 25 P0[4], AI P0[2], AI P0[0], AI P2[6], AI P2[4], AI P2[2], AI P2[0], AI P3[2], AI P3[0], AI XRES P1[6], AI P1[4], EXTCLK, AI 48 47 46 45 44 17 43 13 14 15 16 18 19 20 21 AI, P1[2] AI, DATA*, I2C SDA, P1[0] HCLK NC NC AI, CLK*, I2C SCL, SPI MOSI, P1[1] Vss AI, SPI CLK, P1[3] NC Table 5. 48-pin OCD Part Pinout (QFN [7]) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IOH I IOH IOH Power I I I/O I/O I/O I/O I/O I/O I/O IOH IOH I I I I I I I I I Digital Analog Name NC P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] P1[7] P1[5] NC NC NC NC P1[3] P1[1] Vss CCLK HCLK P1[0] I2C SCL, SPI SS I2C SDA, SPI MISO No connection No connection No connection No connection SPI CLK CLK[8], I2C SCL, SPI MOSI Ground connection OCD CPU clock output OCD high speed clock output DATA[8], I2C SDA No connection Integrating Input Description Notes 7. The center pad on the QFN package is connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it is electrically floated and not connected to any other signal. 8. These are the ISSP pins, that are not high Z at POR (Power on reset). Refer the PSoC Programmable System-on-Chip Technical Reference Manual for details. Document Number: 001-41947 Rev. *K CCLK NC NC 22 23 24 NC AI, P0[1] AI, P2[7] AI, P2[5] AI, P2[3] AI, P2[1] AI, P3[3] AI, P3[1] AI, I2C SCL, SPI SS, P1[7] AI, I2C SDA, SPI MISO, P1[5] NC NC 1 2 3 4 5 6 7 8 9 10 11 12 OCD QFN (Top View) 42 41 40 Page 12 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 Table 5. 48-pin OCD Part Pinout (QFN [7]) (continued) Pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 CP Power I/O I/O I/O Power I I I I/O Power I I/O I/O I/O I/O I/O I/O I/O I/O I/O IOH IOH Input I I I I I I I I I I I Digital IOH Analog I Name P1[2] NC NC NC P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] NC NC NC P0[6] VDD OCDO OCDE P0[7] P0[5] P0[3] VSS NC VSS Integrating input Ground connection No connection Center pad is connected to ground Supply voltage OCD odd data output OCD even data I/O No connection No connection No connection Active high external reset with internal pull-down No connection No connection No connection Optional external clock input (EXTCLK) Description A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive. Document Number: 001-41947 Rev. *K Page 13 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C20224, CY8C20324, CY8C20424, and CY8C20524 PSoC devices. For the latest electrical specifications, visit the web at http://www.cypress.com/psoc. Specifications are valid for –40 °C  TA  85 °C and TJ  100 °C as specified, except where noted. Refer to Table 16 on page 19 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode. Figure 8. Voltage versus CPU Frequency and IMO Frequency Trim Options 5.25 5.25 SLIMO SLIMO SLIMO Mode=1 Mode=1 Mode=0 4.75 Vdd Voltage 4.75 Vdd Voltage O lid ng Va rati n pe gio Re 3.60 3.00 2.70 2.40 750 kHz 3 MHz 6 MHz 12 MHz 3.00 2.70 2.40 750 kHz 3 MHz SLIMO SLIMO Mode=1 Mode=0 SLIMO Mode=1 SLIMO Mode=0 6 MHz 12 MHz CPU Frequency IMO Frequency Absolute Maximum Ratings Table 6. Absolute Maximum Ratings Symbol TSTG Description Storage temperature Min –55 Typ 25 Max +100 Units °C Notes Higher storage temperatures reduces data retention time. Recommended storage temperature is +25 °C ± 25 °C. Extended duration storage temperatures above 65 °C degrades reliability. TA VDD VIO VIOZ IMIO ESD LU Ambient temperature with power applied Supply voltage on VDD relative to VSS DC input voltage DC voltage applied to tri-state Maximum current into any port pin Electrostatic discharge voltage Latch-up current –40 –0.5 VSS – 0.5 VSS – 0.5 –25 2000 – – – – – – – – +85 +6.0 VDD + 0.5 VDD + 0.5 +50 – 200 °C V V V mA V mA Human Body Model ESD. Operating Temperature Table 7. Operating Temperature Symbol TA TJ Description Ambient temperature Junction temperature Min –40 –40 Typ – – Max +85 +100 Units °C °C Notes The temperature rise from ambient to junction is package specific. See Table 31 on page 30. The user must limit the power consumption to comply with this requirement. Document Number: 001-41947 Rev. *K Page 14 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 DC Electrical Characteristics DC Chip Level Specifications Table 8 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Table 8. DC Chip Level Specifications Symbol VDD IDD12 IDD6 ISB27 ISB Description Supply voltage Supply current, IMO = 12 MHz Supply current, IMO = 6 MHz Sleep (Mode) current with POR, LVD, sleep timer, WDT, and internal slow oscillator active. Mid temperature range. Sleep (Mode) current with POR, LVD, sleep timer, WDT, and internal slow oscillator active. Min 2.40 – – – – Typ – 1.5 1 2.6 2.8 Max 5.25 2.5 1.5 4 5 Units V mA mA µA µA Notes Conditions are VDD = 3.0 V, TA = 25 °C, CPU = 12 MHz. Conditions are VDD = 3.0 V, TA = 25 °C, CPU = 6 MHz. VDD = 2.55 V, 0 °C TA  40 °C. VDD = 3.3 V, –40 °C TA  85 °C. DC GPIO Specifications Unless otherwise noted, Table 9 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, and 2.7 V at 25 °C. These are for design guidance only. Table 9. 5-V and 3.3-V DC GPIO Specifications Symbol RPU VOH1 VOH2 VOH3 VOH4 VOH5 VOH6 VOH7 VOH8 VOH9 Description Pull-up resistor High output voltage port 0, 2, or 3 pins High output voltage port 0, 2, or 3 pins High output voltage port 1 pins with LDO regulator disabled High output voltage port 1 pins with LDO regulator disabled High output voltage port 1 pins with 3.0 V LDO regulator enabled High output voltage port 1 pins with 3.0 V LDO regulator enabled High output voltage port 1 pins with 2.4 V LDO regulator enabled High output voltage port 1 pins with 2.4 V LDO regulator enabled High output voltage port 1 pins with 1.8 V LDO regulator enabled Min 4 VDD – 0.2 VDD – 0.9 VDD – 0.2 VDD – 0.9 2.7 2.2 2.1 2.0 1.6 Typ 5.6 – – – – 3.0 – 2.4 – 1.8 Max 8 – – – – 3.3 – 2.7 – 2.0 Units k V V V V V V V V V Notes IOH < 10 µA, VDD > 3.0 V, maximum of 20 mA source current in all I/Os. IOH = 1 mA, VDD > 3.0 V, maximum of 20 mA source current in all I/Os. IOH < 10 µA, VDD > 3.0 V, maximum of 10 mA source current in all I/Os. IOH = 5 mA, VDD > 3.0 V, maximum of 20 mA source current in all I/Os. IOH < 10 µA, VDD > 3.1 V, maximum of 4 I/Os all sourcing 5 mA. IOH = 5 mA, VDD > 3.1 V, maximum of 20 mA source current in all I/Os. IOH < 10 µA, VDD > 3.0 V, maximum of 20 mA source current in all I/Os. IOH < 200 µA, VDD > 3.0 V, maximum of 20 mA source current in all I/Os. IOH < 10 µA 3.0 V VDD 3.6 V 0 °C TA85 °C Maximum of 20 mA source current in all I/Os. IOH < 100 µA 3.0 V VDD 3.6 V 0 °C TA85 °C Maximum of 20 mA source current in all I/Os. IOL = 20 mA, VDD > 3.0V, maximum of 60 mA sink current on even port pins (for example, P0[2] and P1[4]) and 60 mA sink current on odd port pins (for example, P0[3] and P1[5]). VOH10 High output voltage port 1 pins with 1.8 V LDO regulator enabled 1.5 – – V VOL Low output voltage – – 0.75 V Document Number: 001-41947 Rev. *K Page 15 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 Table 9. 5-V and 3.3-V DC GPIO Specifications (continued) Symbol IOH2 IOH4 IOL VIL VIH VH IIL CIN COUT Description High level source current port 0, 2, or 3 pins High level source current port 1 pins with LDO regulator disabled Low level sink current Input low voltage Input high voltage Input hysteresis voltage Input leakage (absolute value) Capacitive load on pins as input Capacitive load on pins as output Min 1 5 20 – 2.0 – – 0.5 0.5 Typ – – – – – 140 1 1.7 1.7 Max – – – 0.8 – – 5 5 Units mA mA mA V V mV nA pF pF Notes VOH = VDD – 0.9, for the limitations of the total current and IOH at other VOH levels see the notes for VOH. VOH = VDD – 0.9, for the limitations of the total current and IOH at other VOH levels see the notes for VOH. VOH = 0.75 V, see the limitations of the total current in the note for VOL. 3.0 V  VDD  5.25 V 3.0 V  VDD  5.25 V Gross tested to 1 µA Package and pin dependent temperature = 25 °C Package and pin dependent temperature = 25 °C Table 10. 2.7-V DC GPIO Specifications Symbol RPU VOH1 VOH2 VOL Description Pull-up resistor High output voltage port 1 pins with LDO regulator disabled High output voltage port 1 pins with LDO regulator disabled Low output voltage Min 4 VDD – 0.2 VDD – 0.5 – Typ 5.6 – – – Max 8 – – 0.75 Units k V V V Notes IOH < 10 µA, maximum of 10 mA source current in all I/Os. IOH = 2 mA, maximum of 10 mA source current in all I/Os. IOL = 10 mA, maximum of 30 mA sink current on even port pins (for example, P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5]). VOH = VDD – 0.5, for the limitations of the total current and IOH at other VOH levels see the notes for VOH. VOH = 0.75 V, see the limitations of the total current in the note for VOL. IOL = 5 mA Maximum of 50 mA sink current on even port pins (for example, P0[2] and P3[4]) and 50 mA sink current on odd port pins (for example, P0[3] and P2[5]). 2.4 V  VDD  3.0 V 2.4 V  VDD  3.0 V 2.4 V  VDD  2.7 V 2.7 V  VDD  3.0 V Gross tested to 1 µA Package and pin dependent temperature = 25 °C Package and pin dependent temperature = 25 °C IOH2 High level source current port 1 pins with LDO regulator disabled Low level sink current Low output voltage port 1 pins 2 – – mA IOL VOLP1 10 – – – – 0.4 mA V VIL VIH1 VIH2 VH IIL CIN COUT Input low voltage Input high voltage Input high voltage Input hysteresis voltage Input leakage (absolute value) Capacitive load on pins as input Capacitive load on pins as output – 1.4 1.6 – – 0.5 0.5 – – – 60 1 1.7 1.7 0.75 – – – – 5 5 V V V mV nA pF pF Document Number: 001-41947 Rev. *K Page 16 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 DC Analog Mux Bus Specifications Table 11 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Table 11. DC Analog Mux Bus Specifications Symbol RSW Description Switch resistance to common analog bus Min – Typ – Max 400 800 Units   Notes Vdd  2.7 V 2.4 V Vdd 2.7 V DC Low Power Comparator Specifications Table 12 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V at 25 °C. These are for design guidance only. Table 12. DC Low Power Comparator Specifications Symbol VREFLPC ISLPC VOSLPC Description Low power comparator (LPC) reference voltage range LPC supply current LPC voltage offset Min 0.2 – – Typ – 10 2.5 Max VDD – 1.0 40 30 Units V µA mV Notes DC POR and LVD Specifications Table 13 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Table 13. DC POR and LVD Specifications Symbol VPPOR0 VPPOR1 VPPOR2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Description VDD value for PPOR trip PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b VDD value for LVD trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min – – – 2.39 2.54 2.75 2.85 2.96 – – 4.52 Typ 2.36 2.60 2.82 2.45 2.71 2.92 3.02 3.13 – – 4.73 Max 2.40 2.65 2.95 2.51[9] 2.78[10] 2.99[11] 3.09 3.20 – – 4.83 Units V V V V V V V V V V V Notes VDD is greater than or equal to 2.5 V during startup, reset from the XRES pin, or reset from Watchdog. Notes 9. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply. 10. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply. 11. Always greater than 50 mV above VPPOR (PORLEV = 10) for falling supply. 12. A maximum of 36 × 50,000 block endurance cycles is allowed. This is balanced between operations on 36 × 1 blocks of 50,000 maximum cycles each, 36 × 2 blocks of 25,000 maximum cycles each, or 36 × 4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36 × 50,000 and that no single block ever sees more than 50,000 cycles). 13. The 50,000 cycle flash endurance per block will only be guaranteed if the flash is operating within one voltage range. Voltage ranges are 2.4 V to 3.0 V, 3.0 V to 3.6 V and 4.75 V to 5.25 V. Document Number: 001-41947 Rev. *K Page 17 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 DC Programming Specifications Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Table 14. DC Programming Specifications Symbol VDDP Description VDD for programming and erase Min 4.5 Typ 5 Max 5.5 Units V Notes This specification applies to the functional requirements of external programmer tools This specification applies to the functional requirements of external programmer tools This specification applies to the functional requirements of external programmer tools This specification applies to this device when it is executing internal flash writes VDDLV Low VDD for verify 2.4 2.5 2.6 V VDDHV High VDD for verify 5.1 5.2 5.3 V VDDIWRITE Supply voltage for flash write operation 2.7 – 5.25 V IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR Supply current during programming or verify Input low voltage during programming or verify Input high voltage during programming or verify Input current when applying Vilp to P1[0] or P1[1] during programming or verify Input current when applying Vihp to P1[0] or P1[1] during programming or verify Output low voltage during programming or verify Output high voltage during programming or verify Flash endurance (per block)[13] Flash endurance (total)[12] Flash data retention – – 2.2 – – – VDD – 1.0 50,000 1,800,000 10 5 – – – – – – – – – 25 0.8 – 0.2 1.5 VSS + 0.75 VDD – – – mA V V mA mA V V – – Years Driving internal pull-down resistor. Driving internal pull-down resistor. Erase/write cycles per block. Erase/write cycles. DC I2C Specifications Table 15 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Table 15. DC I2C Specifications[14] Symbol VILI2C VIHI2C Description Input low level Input high level Min – – 0.7 × VDD Typ – – – Max 0.3 × VDD 0.25 × VDD – Units V V V Notes 2.4 V VDD  3.6 V 4.75 V  VDD  5.25 V 2.4 V  VDD  5.25 V Notes 14. All GPIO meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I2C GPIO pins also meet the above specs. 15. 0 °C to 70 °C ambient, VDD = 3.3 V. Document Number: 001-41947 Rev. *K Page 18 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 AC Electrical Characteristics AC Chip Level Specifications Table 16 and Table 17 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Table 16. 5-V and 3.3-V AC Chip-Level Specifications Symbol FCPU1 F32K1 F32K_U Description CPU frequency (3.3 V nominal) ILO frequency ILO untrimmed frequency Min 0.75 15 5 Typ – 32 – Max 12.6 64 100 Units MHz kHz kHz Notes 12 MHz only for SLIMO Mode = 0 After a reset and before the M8C starts to run, the ILO is not trimmed. See the System Resets section of the PSoC Technical Reference Manual for details on this timing. Trimmed for 3.3 V operation using factory trim values. See Figure 8 on page 14, SLIMO Mode = 0. Trimmed for 3.3 V operation using factory trim values. See Figure 8 on page 14, SLIMO Mode = 1. FIMO12 IMO stability for 12 MHz (Commercial temperature)[15] IMO stability for 6 MHz (Commercial temperature) Duty cycle of IMO ILO duty cycle Supply ramp time External reset pulse width Time from end of POR to CPU executing code 12 MHz IMO cycle-to-cycle jitter (RMS) 12 MHz IMO long term N cycle-to-cycle jitter (RMS) 12 MHz IMO period jitter (RMS) 11.4 12 12.6 MHz FIMO6 5.5 6.0 6.5 MHz DCIMO DCILO tRAMP tXRST tPOWERUP tjit_IMO[16] 40 20 0 10 – – – – 50 50 – – 16 200 600 100 60 80 – – 100 1600 1400 900 % % µs µs ms ps ps ps Power up from 0 V. See the System Resets section of the PSoC Technical Reference Manual. N = 32 Table 17. 2.7-V AC Chip Level Specifications Symbol FCPU1A FCPU1B F32K1 F32K_U Description CPU frequency (2.7 V nominal) CPU frequency (2.7 V minimum) ILO frequency ILO untrimmed frequency Min 0.75 0.75 8 5 Typ – – 32 – Max 3.25 6.3 96 – Units MHz MHz kHz kHz Notes 2.4 V < VDD < 3.0 V. 2.7 V < VDD < 3.0 V. After a reset and before the M8C starts to run, the ILO is not trimmed. See the System Resets section of the PSoC Technical Reference Manual for details on this timing. Trimmed for 2.7 V operation using factory trim values. See Figure 8 on page 14, SLIMO Mode = 0. Trimmed for 2.7 V operation using factory trim values. See Figure 8 on page 14, SLIMO Mode = 1. FIMO12 FIMO6 IMO stability for 12 MHz (Commercial temperature)[15] IMO stability for 6 MHz (Commercial temperature) Duty cycle of IMO ILO duty cycle Supply ramp time External reset pulse width 11.0 5.5 12 6.0 12.9 6.5 MHz MHz DCIMO DCILO tRAMP tXRST 40 20 0 10 50 50 – – 60 80 – – % % µs µs Note 16. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products - AN5054 for more information Document Number: 001-41947 Rev. *K Page 19 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 Table 17. 2.7-V AC Chip Level Specifications (continued) Symbol tPOWERUP tjit_IMO[16] Description Min – – – – Typ 16 500 800 300 Max 100 900 1400 500 Units ms ps ps ps Notes Power-up from 0 V. See the System Resets section of the PSoC Technical Reference Manual. N = 32 12 MHz IMO cycle-to-cycle jitter (RMS) 12 MHz IMO long term N cycle-to-cycle jitter (RMS) 12 MHz IMO period jitter (RMS) AC GPIO Specifications Table 18 an d Table 19 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Table 18. 5 V and 3.3 V AC GPIO Specifications Symbol FGPIO tRise023 tRise1 tFall Description GPIO operating frequency Rise time, strong mode, Cload = 50 pF ports 0, 2, 3 Rise time, strong mode, Cload = 50 pF port 1 Fall time, strong mode, Cload = 50 pF all ports Min 0 15 10 10 Typ – – – – Max 6 80 50 50 Units MHz ns ns ns Notes Normal strong mode, Port 1. VDD = 3.0 V to 3.6 V and 4.75 V to 5.25 V, 10% to 90% VDD = 3.0 V to 3.6 V, 10% to 90% VDD = 3.0 V to 3.6 V and 4.75 V to 5.25 V, 10% to 90% Table 19. 2.7 V AC GPIO Specifications Symbol FGPIO tRise023 tRise1 tFall Description GPIO operating frequency Rise time, strong mode, Cload = 50 pF ports 0, 2, 3 Rise time, strong mode, Cload = 50 pF port 1 Fall time, strong mode, Cload = 50 pF all ports Min 0 15 10 10 Typ – – – – Max 1.5 100 70 70 Units MHz ns ns ns Notes Normal Strong Mode, Port 1. VDD = 2.4 V to 3.0 V, 10% to 90% VDD = 2.4 V to 3.0 V, 10% to 90% VDD = 2.4 V to 3.0 V, 10% to 90% Figure 9. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRise023 TRise1 TFall Document Number: 001-41947 Rev. *K Page 20 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 AC Comparator Specifications Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Table 20. AC Comparator Specifications Symbol tCOMP Description Comparator response time, 50 mV overdrive Min – Typ – Max 100 200 Units ns ns Notes VDD  3.0 V 2.4 V < VCC > Evaluation Boards. Pin Package 16-pin COL 24-pin QFN 28-pin SSOP Flex-Pod Kit [20] Not available CY3250-20334QFN CY3250-20534 Foot Kit [21] Not available CY3250-24QFN-FK CY3250-28SSOP-FK Prototyping Module CY3210-20X34 CY3210-20X34 CY3210-20X34 Adapter [22] AS-24-28-01ML-6 - Build a PSoC Emulator into Your Board For details on emulating the circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, refer application note AN2323 “Build a PSoC Emulator into Your Board”. Notes 20. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. 21. Foot kit includes surface mount feet that is soldered to the target PCB. 22. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters is found at http://www.emulation.com. Document Number: 001-41947 Rev. *K Page 32 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 Acronyms Acronyms Used Table 34 lists the acronyms that are used in this document. Table 34. Acronyms Used in this Datasheet Acronym AC ADC API CMOS CPU EEPROM GPIO ICE IDAC IDE ILO IMO I/O ISSP LCD LDO LED LVD MCU light-emitting diode low voltage detect microcontroller unit alternating current analog-to-digital converter application programming interface complementary metal oxide semiconductor central processing unit electrically erasable programmable read-only memory general purpose I/O in-circuit emulator current DAC integrated development environment internal low speed oscillator internal main oscillator input/output in-system serial programming liquid crystal display Description Acronym MIPS OCD PCB PGA POR PPOR PSoC® PWM QFN SLIMO SPITM SRAM SROM SSOP USB WDT WLCSP XRES on-chip debug printed circuit board programmable gain amplifier power on reset precision power on reset Programmable System-on-Chip pulse width modulator quad flat no leads slow IMO serial peripheral interface static random access memory supervisory read only memory shrink small-outline package universal serial bus watchdog timer wafer level chip scale package external reset Description million instructions per second Reference Documents PSoC® CY8C20x34 and PSoC® CY8C20x24 Technical Reference Manual (TRM) – 001-13033 Design Aids – Reading and Writing PSoC® Flash – AN2015 (001-40459) Adjusting PSoC® Trims for 3.3 V and 2.7 V Operation – AN2012 (001-17397) Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 (001-14503) Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com. Document Number: 001-41947 Rev. *K Page 33 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 Document Conventions Units of Measure Table 35 lists the units of measures. Table 35. Units of Measure Symbol °C pF kHz MHz k  µA mA nA µs picofarad kilohertz megahertz kilohm ohm microampere milliampere nanoampere microsecond Unit of Measure degree Celsius Symbol ms ns ps µV mV V W mm % millisecond nanosecond picosecond microvolts millivolts volts watt millimeter percent Unit of Measure Numeric Conventions Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals. Glossary active high 1. A logic signal having its asserted state as the logic 1 state. 2. A logic signal having the logic 1 state as the higher voltage of the two states. The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more. A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation. A series of software routines that comprise an interface between a computer application and lower level services and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create software applications. A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. A stable voltage reference design that matches the positive temperature coefficient of VT with the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference. 1. The frequency range of a message or information processing system measured in hertz. 2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. 1. A systematic deviation of a value from a reference value. 2. The amount by which the average of a set of values departs from a reference value. 3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. Page 34 of 40 analog blocks analog-to-digital (ADC) Application programming interface (API) asynchronous Bandgap reference bandwidth bias Document Number: 001-41947 Rev. *K [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 Glossary (continued) block 1. A functional unit that performs a single function, such as an oscillator. 2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or an analog PSoC block. 1. A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for I/O operations, into which data is read, or from which data is written. 2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. An amplifier used to lower the output impedance of a system. 1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0]. 3. One or more conductors that serve as a common connection for a group of related devices. The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks. An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. A program that translates a high level language, such as C, into machine language. In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’. An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. buffer bus clock comparator compiler configuration space crystal oscillator cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear check (CRC) feedback shift register. Similar calculations may be used for a variety of other purposes such as data compression. data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions. A hardware and software system that allows you to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. A period of time when neither of two or more signals are in their active state or in transition. The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator, pseudo-random number generator, or SPI. A device that changes a digital signal to an analog signal of corresponding magnitude. The analogto-digital (ADC) converter performs the reverse operation. The relationship of a clock period high time to its low time, expressed as a percent. debugger dead band digital blocks digital-to-analog (DAC) duty cycle Document Number: 001-41947 Rev. *K Page 35 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 Glossary (continued) emulator Duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop and return to a pre-defined state. An electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is OFF. The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash space that may be protected. A Flash block holds 64 bytes. The number of cycles or events per unit of time, for a periodic function. The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually expressed in dB. A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5V and pulled high with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (PSoC Designer). External Reset (XRES) Flash Flash block frequency gain I2C ICE input/output (I/O) A device that introduces data into or extracts data from a system. interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends with the RETI instruction, returning the device to the point in the program where it left normal program execution. 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on serial data streams. 2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles. interrupt service routine (ISR) jitter low-voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a selected threshold. (LVD) M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the Flash, SRAM, and register space. A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device. master device Document Number: 001-41947 Rev. *K Page 36 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 Glossary (continued) microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and I/O circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor. The reference to a circuit containing both analog and digital techniques and components. A device that imposes a signal on a carrier. 1. A disturbance that affects a signal and that may distort the information carried by the signal. 2. The random variations of one or more characteristics of any entity such as voltage, current, or data. A circuit that may be crystal controlled and is used to generate a clock frequency. A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names. A group of pins, usually eight. A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is a type of hardware reset. Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-onChip™ is a trademark of Cypress. mixed-signal modulator noise oscillator parity Phase-locked loop (PLL) pinouts port Power on reset (POR) PSoC® PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology. pulse width An output in the form of duty cycle which varies as a function of the applied measurand modulator (PWM) RAM An acronym for random access memory. A data-storage device from which data can be read out and new data can be written in. A storage device with a specific capacity, such as a bit or byte. A means of bringing a system back to a know state. See hardware reset and software reset. An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in. 1. Pertaining to a process in which all events occur one after the other. 2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. register reset ROM serial Document Number: 001-41947 Rev. *K Page 37 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 Glossary (continued) settling time The time it takes for an output signal or value to stabilize after the input has changed from one value to another. A memory storage device that sequentially shifts a word either left or right to output a stream of serial data. A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. The controlling device is called the master device. An acronym for static random access memory. A memory device where you can store and retrieve data at a high rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is removed from the device. An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code, operating from Flash. A signal following a character or block that prepares the receiving device to receive the next character or block. 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. A system whose operation is synchronized by a clock signal. A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming Interface) for the peripheral function. The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program. A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V. A name for a power net meaning "voltage source." The most negative power supply signal. A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time. shift register slave device SRAM SROM stop bit synchronous tri-state UART user modules user space VDD VSS watchdog timer Document Number: 001-41947 Rev. *K Page 38 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 Document History Page Document Title: CY8C20224, CY8C20324, CY8C20424, CY8C20524 CapSense® PSoC® Programmable System-on-Chip™ Document Number: 001-41947 Revision ECN No. ** *A *B *C 1734104 2542938 2610469 2634376 Orig. of Change YHW/AESA RLRM/AESA SNV/PYRS DRSW Submission Date See ECN 07/28/2008 11/20/08 01/12/09 Description of Change New parts and document (Revision **). Corrected Ordering Information format. Updated package diagram 001-13937 to Rev *B. Updated data sheet template. Updated VOH5, VOH7, and VOH9 specifications. Removed the part number CY3250-20234QFN from the 'CY8C20224-12LKXI' flex-pod kit Changed title from CapSense™ Multimedia PSoC® Mixed-Signal Array to CapSense™ Multimedia PSoC® Programmable System-on-Chip™ Added -12 to the CY8C20524 parts in the Ordering Information table Updated ‘Development Tools’ and ‘Designing with PSoC Designer’ sections on pages 4 and 5 Updated ‘Development Tools Selection’ section on page 30 Changed status from ‘Preliminary’ to ‘Final’ Changed 16-Pin from QFN to COL Added 32-Pin Sawn QFN package diagram Added devices CY8C20424-12LQXI and CY8C20424-12LQXIT in the Ordering Information table Updated AC Chip-Level, and AC Programming Specifications as follows: Modified FIMO6 (page 19), TWRITE specifications (page 22) Added IOH & IOL (page 16), Flash endurance note (page 18), DCILO (page 19), F32K_U (page 19), TPOWERUP (page 19), TERASEALL (page 22), TPROGRAM_HOT (page 22), and TPROGRAM_COLD (page 22) specifications Added AC SPI Master and Slave Specifications Updated Package Diagrams Updated Ordering Information Updated title to read AC Comparator Specifications and also updated table caption to read “AC Comparator Specifications” in the same section. Minor edits and updated in new template. Removed AC analog mux bus specifications. Updated Development Tools and Designing with PSoC Designer sections. Added PSoC Device Characteristics table. Added DC I2C Specifications table. Added F32K_U max limit. Added Tjit_IMO specification, removed existing jitter specifications. Updated Units of Measure, Acronyms, Glossary, and References sections. Updated solder reflow specifications. No specific changed were made to I2C Timing Diagram. Updated for clearer understanding. Template and styles update. Removed pruned part CY8C20424-12LKXIT from the ordering information table. No Change *D 2693024 DPT/PYRS 04/16/2009 *E 2717566 DRSW/AESA 06/11/2009 *F *G 2899195 3037121 CFW/ISW CFW 03/26/2010 09/24/2010 *H *I 3049675 3072668 BTK NJF 10/06/2010 10/27/10 *J *K 3112469 3182773 ARVM MATT 12/16/10 03/01/11 Document Number: 001-41947 Rev. *K Page 39 of 40 [+] Feedback CY8C20224, CY8C20324 CY8C20424, CY8C20524 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2008-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-41947 Rev. *K Revised March 1, 2011 Page 40 of 40 PSoC Designer™ is a trademark and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback