CY8C20234-12LKXAT

Automotive PSoC Programmable System-on-Chip Features ■ ■ CY8C20234 ® Automotive Electronics Council (AEC) Q100 qualified Low power CapSense block ❐ Configurable capacitive sensing elements ❐ Supports combination of CapSense buttons, sliders, touchpads, and proximity sensors Powerful Harvard-architecture processor ❐ M8C processor speeds up to 12 MHz ❐ Low power at high speed ❐ Operating voltage: 3.0 V to 5.25 V ❐ Automotive temperature range: –40 °C to +85 °C Flexible on-chip memory ❐ 8 KB of flash program storage, 1000 erase/write cycles ❐ 512 bytes of SRAM data storage ❐ Partial flash updates ❐ Flexible protection modes ❐ In-system serial programming (ISSP) Complete development tools ❐ Free development tool (PSoC Designer™) ❐ Full featured, in-circuit emulator (ICE) and programmer ❐ Full-speed emulation ❐ Complex breakpoint structure ❐ 128 KB trace memory Precision, programmable clocking ❐ Internal ±5% 6-/12-MHz oscillator ❐ Internal low-speed, low-power oscillator for watchdog and sleep functionality Programmable pin configurations ❐ 20 mA sink on all general purpose I/Os (GPIOs) ❐ Pull-up, high Z, open drain, or strong drive modes on all GPIOs ❐ Up to 13 analog inputs on GPIOs ❐ Configurable interrupt on all GPIOs ❐ Selectable, regulated digital I/O on Port 1 • 3.0 V, 2.4 V, and 1.8 V regulation available • Up to 5 mA source on Port 1 GPIOs Versatile analog mux ❐ Common internal analog bus ❐ Simultaneous connection of I/O combinations ❐ Comparator noise immunity ® ■ ■ Additional system resources ❐ Configurable communication speeds • I2C™ slave operation up to 400 kHz • SPI master or slave operation between 46.9 kHz and 12 MHz ❐ Watchdog and sleep timers ❐ Internal voltage reference ❐ Integrated supervisory circuit Logic Block Diagram Port 3 Port 2 Port 1 Port 0 Config LDO ■ PSoC CORE System Bus ■ Global Analog Interconnect SRAM 512 Bytes Interrupt Controller SROM Flash 8K Sleep and Watchdog CPU Core (M8C) ■ 6/12 MHz Internal Main Oscillator ■ ANALOG SYSTEM CapSense Block Analog Ref. ■ I2C Slave/SPI Master-Slave POR and LVD System Resets Analog Mux SYSTEM RESOURCES Cypress Semiconductor Corporation Document Number: 001-54650 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 10, 2011 [+] Feedback CY8C20234 Contents PSoC® Functional Overview ........................................... 3 PSoC Core .................................................................. 3 CapSense Analog System .......................................... 3 Additional System Resources ..................................... 4 PSoC Device Characteristics ...................................... 4 Getting Started .................................................................. 5 Application Notes ........................................................ 5 Development Kits ........................................................ 5 Training ....................................................................... 5 CYPros Consultants .................................................... 5 Solutions Library .......................................................... 5 Technical Support ....................................................... 5 Development Tools .......................................................... 6 PSoC Designer Software Subsystems ........................ 6 Designing with PSoC Designer ....................................... 7 Select User Modules ................................................... 7 Configure User Modules .............................................. 7 Organize and Connect ................................................ 7 Generate, Verify, and Debug ....................................... 7 Pinouts .............................................................................. 8 16-Pin Part Pinout ....................................................... 8 Electrical Specifications .................................................. 9 Absolute Maximum Ratings ....................................... 10 Operating Temperature ............................................. 10 DC Electrical Characteristics ..................................... 11 AC Electrical Characteristics ..................................... 14 Packaging Information ................................................... 18 Thermal Impedances ................................................. 18 Solder Reflow Specifications ..................................... 18 Tape and Reel Information ........................................ 19 Development Tool Selection ......................................... 20 Software .................................................................... 20 Development Kits ...................................................... 20 Evaluation Tools ........................................................ 20 Device Programmers ................................................. 21 Accessories (Emulation and Programming) .............. 21 Ordering Information ...................................................... 22 Ordering Code Definitions ......................................... 22 Reference Information ................................................... 23 Acronyms .................................................................. 23 Reference Documents ............................................... 23 Document Conventions ............................................. 24 Glossary .................................................................... 24 Document History Page ................................................. 29 Sales, Solutions, and Legal Information ...................... 30 Worldwide Sales and Design Support ....................... 30 Products .................................................................... 30 PSoC Solutions ......................................................... 30 Document Number: 001-54650 Rev. *E Page 2 of 30 [+] Feedback CY8C20234 PSoC® Functional Overview The PSoC family consists of many Programmable System-on-Chip with on-chip controller devices. These devices are designed to replace multiple traditional microcontroller unit (MCU)-based system components with one low cost single chip programmable component. A PSoC device includes configurable analog and digital blocks and programmable interconnect. This architecture enables the user to create customized peripheral configurations to match the requirements of each individual application. Additionally, a fast CPU, flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. The PSoC architecture for this device family, as shown in “Logic Block Diagram” on page 1, consists of three main areas: the PSoC core, the system resources, and the CapSense analog system. A common versatile bus enables connection between I/O and the analog system. Each CY8C20x34 PSoC device includes a dedicated CapSense block that provides sensing and scanning control circuitry for capacitive sensing applications. Depending on the PSoC package, up to 13 GPIOs are also included. The GPIOs provide access to the MCU and analog mux. Figure 1. Analog System Block Diagram ID AC Analog Global Bus Vr R eferenc e Buffer C internal C om parator Mux Mux R efs PSoC Core The PSoC core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, internal main oscillator (IMO), and internal low-speed oscillator (ILO). The CPU core, called the M8C, is a powerful processor with speeds up to 12 MHz. The M8C is a two-MIPS, 8-bit Harvardarchitecture microprocessor. System resources provide additional capability such as a configurable I2C slave, SPI slave, or SPI master communication interface and various system resets supported by the M8C. The CapSense analog system consists of the CapSense® PSoC block and an internal analog reference. Together they support capacitive sensing of up to 13 inputs. IMO C ap Sens e C ounters C SC LK C apSens e C lock Selec t R elaxation O s c illator (RO) Analog Multiplexer System The analog mux bus connects to every GPIO pin. Pins are connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with the CapSense block comparator. Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include: ■ ■ ■ CapSense Analog System The CapSense analog system contains the capacitive sensing hardware. Several hardware algorithms are supported. This hardware performs capacitive sensing and scanning without requiring external components. Capacitive sensing is configurable on each GPIO pin. Scanning of enabled CapSense pins is completed quickly and easily across multiple ports. Complex capacitive sensing interfaces such as sliders and touch pads Chip-wide mux that enables analog input from any I/O pin Crosspoint connection between any I/O pin combination Document Number: 001-54650 Rev. *E Page 3 of 30 [+] Feedback CY8C20234 Additional System Resources System resources provide additional capability useful for complete systems. Additional resources include low voltage detection (LVD) and power-on reset (POR). Brief statements describing the merits of each system resource are presented below. ■ ■ LVD interrupts signal the application of falling voltage levels, while the advanced POR circuit eliminates the need for a system supervisor. An internal voltage reference provides an absolute reference for capacitive sensing. The 3.0-V/2.4-V/1.8-V fixed output, low dropout regulator (LDO) provides regulation for I/Os. A register controlled bypass mode enables the user to disable the LDO. ■ ■ There is a digital module in CY8C20x34 devices that implements an I2C slave, SPI slave, or SPI master interface.The I2C slave mode provides 0 to 400 kHz communication over two wires. The SPI master and slave modes provide communication over three or four wires at frequencies of 46.9 kHz to 12 MHz (lower for a slower system clock). PSoC Device Characteristics Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, 4, or 0 digital blocks and 12, 6, 4, or 0 analog blocks. The following table lists the resources available for specific PSoC device groups. The device covered by this datasheet is shown in the highlighted row of the table. Table 1. PSoC Device Characteristics PSoC Part Number CY8C29x66[1] CY8C28xxx CY8C27x43 CY8C24x94[1] CY8C24x23A [1] Digital I/O up to 64 up to 44 up to 44 up to 56 up to 24 up to 26 up to 38 up to 24 up to 28 up to 16 up to 28 up to 36 Digital Rows 4 up to 3 2 1 1 1 2 1 1 1 0 0 Digital Blocks 16 up to 12 8 4 4 4 8 4 4 4 0 0 Analog Inputs up to 12 up to 44 up to 12 up to 48 up to 12 up to 12 up to 38 up to 24 up to 28 up to 8 up to 28 up to 36 Analog Outputs 4 up to 4 4 2 2 2 0 0 0 0 0 0 Analog Columns 4 up to 6 4 2 2 2 4 4 2 2 0 0 Analog Blocks 12 up to 12 + 4[2] 12 6 6 4 6[2] 6 [2] SRAM Size 2K 1K 256 1K 256 256 1K 512 512 256 512 up to 2 K Flash Size 32 K 16 K 16 K 16 K 4K 8K 16 K 8K 8K 4K 8K up to 32 K CY8C23x33 CY8C22x45 CY8C21x45 CY8C21x34[1] CY8C21x23 CY8C20x34 [1] 4[2] 4[2] 3 [2,3] CY8C20xx6 3[2,3] Notes 1. Automotive qualified devices available in this group. 2. Limited analog functionality. 3. Two analog blocks and one CapSense® block. Document Number: 001-54650 Rev. *E Page 4 of 30 [+] Feedback CY8C20234 Getting Started For in depth information, along with detailed programming details, see the PSoC® Technical Reference Manual. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device datasheets on the web. covers a wide variety of topics and skill levels to assist you in your designs. CYPros Consultants Certified PSoC consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC consultant go to the CYPros Consultants web site. Application Notes Cypress application notes are an excellent introduction to the wide variety of possible PSoC designs. Solutions Library Visit our growing library of solution focused designs. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Development Kits PSoC Development Kits are available online from and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Technical Support Technical support – including a searchable Knowledge Base articles and technical forums – is also available online. If you cannot find an answer to your question, call our Technical Support hotline at 1-800-541-4736. Training Free PSoC technical training (on demand, webinars, and workshops), which is available online via www.cypress.com, Document Number: 001-54650 Rev. *E Page 5 of 30 [+] Feedback CY8C20234 Development Tools PSoC Designer™ is the revolutionary Integrated Design Environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of pre-characterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes: ■ ■ ■ ■ ■ ■ ■ Code Generation Tools The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. You can develop your design in C, assembly, or a combination of the two. Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows you to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer. In-Circuit Emulator A low-cost, high-functionality In-Circuit Emulator (ICE) is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24-MHz) operation. Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration Extensive user module catalog Integrated source-code editor (C and assembly) Free C compiler with no size restrictions or time limits Built-in debugger In-circuit emulation Built-in support for communication interfaces: 2 ❐ Hardware and software I C slaves and masters ❐ Full-speed USB 2.0 ❐ Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7. PSoC Designer Software Subsystems Design Entry In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use the PSoC blocks, which are called user modules. Examples of user modules are analog-to-digital converters (ADCs), digital-to-analog converters (DACs), amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This pre-populates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this allows you to use more than 100 percent of PSoC's resources for a given application. Document Number: 001-54650 Rev. *E Page 6 of 30 [+] Feedback CY8C20234 Designing with PSoC Designer The development process for the PSoC® device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is summarized in four steps: 1. Select User Modules. 2. Configure user modules. 3. Organize and connect. 4. Generate, verify, and debug. provide performance specifications. Each datasheet describes the use of each user module parameter, and other information you may need to successfully implement your design. Organize and Connect You build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. You perform the selection, configuration, and routing so that you have complete control over all on-chip resources. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, you perform the “Generate Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides application programming interfaces (APIs) with high-level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. A complete code development environment allows you to develop and customize your applications in either C, assembly language, or both. The last step in the development process takes place inside PSoC Designer’s debugger (access by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. Select User Modules PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called “user modules.” User modules make selecting and implementing peripheral devices, both analog and digital, simple. Configure User Modules Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a pulse width modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the internal operation of the user module and Document Number: 001-54650 Rev. *E Page 7 of 30 [+] Feedback CY8C20234 Pinouts This section describes, lists, and illustrates the automotive CY8C20x34 PSoC device pins and pinout configurations. The automotive CY8C20x34 PSoC device is available in the packages listed and shown in the following tables. Every port pin (labeled with a “P”) is capable of digital I/O and can connect to the common analog bus. However, VSS, VDD, and XRES are not capable of digital I/O. 16-Pin Part Pinout Figure 2. CY8C20234 16-Pin PSoC Device P0[1], AI P0[3], AI P0[7], AI VDD AI, P2[5] AI, P2[1] I2C SCL, SPI SS, AI, P1[7] I2C SDA, SPI MISO, AI, P1[5] 1 2 3 4 16 15 14 13 QFN 5 6 7 8 12 11 10 9 P0[4], AI XRES P1[4], AI, EXTCLK P1[2], AI Table 2. Pin Definitions – CY8C20234 16-Pin (QFN) Pin No. Type Digital Analog Name Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I/O I/O I/OH I/OH I/OH I/OH Power I/OH I/OH I/OH Input I/O Power I/O I/O I/O I I I I I I I I I I I I I P2[5] P2[1] P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] XRES P0[4] VDD P0[7] P0[3] P0[1] Integrating input Supply voltage Optional external clock (EXTCLK) input Active high external reset with internal pull-down I2C serial clock (SCL), SPI slave select (SS) I2C serial data (SDA), SPI master-in-slave-out (MISO) SPI serial clock (SCLK) ISSP-SCLK[4], I2C serial clock (SCL), SPI master-out-slave-in (MOSI) Ground connection ISSP-SDATA[4], I2C serial data (SDA) A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive Note 4. These are the ISSP pins, that are not High Z after exiting a reset state. See the PSoC Technical Reference Manual for CY8C20x34 devices for details. Document Number: 001-54650 Rev. *E SPI SCLK, AI, P1[3] I2C SCL, SPI MOSI, AI, P1[1] VSS I2C SDA, AI, P1[0] Page 8 of 30 [+] Feedback CY8C20234 Electrical Specifications This section presents the DC and AC electrical specifications of the automotive CY8C20x34 PSoC device. For the latest electrical specifications, check the most recent data sheet by visiting the web at http://www.cypress.com. Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100°C as specified, except where mentioned. Refer to Table 11 on page 14 for the electrical specifications on the IMO using SLIMO mode. Figure 3. Voltage versus CPU Frequency Figure 4. IMO Frequency Trim Options 5.25 5.25 SLIMO Mode=1 lid ing V a ra t n pe io O eg R 4.75 VDD Voltage (V) SLIMO Mode=0 4.75 VDD Voltage (V) 3.6 SLIMO Mode=1 3.0 SLIMO Mode=0 3.0 0 750 kHz 3 MHz CPU Frequency (nominal setting) 6 MHz 12 MHz 0 6 MHz IMO Frequency 12 MHz Document Number: 001-54650 Rev. *E Page 9 of 30 [+] Feedback CY8C20234 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 3. Absolute Maximum Ratings Symbol TSTG Description Storage temperature Min -55 Typ 25 Max +100 Units Notes °C Higher storage temperatures reduce data retention time. Recommended storage temperature is +25 °C ± 25 °C. Time spent in storage at a temperature greater than 65 °C counts toward the FlashDR electrical specification in Table 10 on page 13. °C TBAKETEMP Bake temperature – 125 tBAKETIME Bake time TA VDD VIO VIOZ IMIO ESD LU Ambient temperature with power applied Supply voltage on VDD relative to VSS DC input voltage DC voltage applied to tri-state Maximum current into any port pin Electrostatic discharge voltage Latch-up current See package label –40 –0.5 VSS – 0.5 VSS – 0.5 –25 2000 – – See package label 72 Hours °C V V V mA V mA – – – – – – – +85 +6.0 VDD + 0.5 VDD + 0.5 +50 – 200 Human Body Model ESD. Operating Temperature Table 4. Operating Temperature Symbol TA TJ Description Ambient temperature Junction temperature Min –40 –40 Typ – – Max +85 +100 Units Notes °C °C The temperature rise from ambient to junction is package specific. See Table 19 on page 18. The user must limit the power consumption to comply with this requirement. Document Number: 001-54650 Rev. *E Page 10 of 30 [+] Feedback CY8C20234 DC Electrical Characteristics DC Chip Level Specifications Table 5 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C. These are for design guidance only. Table 5. DC Chip Level Specifications Symbol VDD IDD12 IDD6 ISB Description Supply voltage Supply current, IMO = 12 MHz Supply current, IMO = 6 MHz Sleep (mode) current with POR, LVD, sleep timer, WDT, and ILO active. Min 3.0 – – – Typ – 1.5 1 2.8 Max 5.25 2.5 1.5 5 Units V mA mA μA Notes See Table 8 on page 12. Conditions are VDD = 3.0 V, TA = 25 °C, CPU = 12 MHz. Conditions are VDD = 3.0 V, TA = 25 °C, CPU = 6 MHz VDD = 3.3 V, –40 °C ≤ TA ≤ 85 °C DC GPIO Specifications Table 6 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C. These are for design guidance only. Table 6. DC GPIO Specifications Symbol RPU RPD VOH1 VOH2 VOH3 VOH4 VOH5 VOH6 VOH7 VOH8 VOH9 Description Pull-up resistor Internal pull-down resistor on XRES pin High output voltage Port 0, 2, or 3 pins High output voltage Port 0, 2, or 3 pins High output voltage Port 1 pins with LDO disabled High output voltage Port 1 pins with LDO disabled High output voltage Port 1 pins with 3.0-V LDO enabled High output voltage Port 1 pins with 3.0-V LDO enabled High output voltage Port 1 pins with 2.4-V LDO enabled High output voltage Port 1 pins with 2.4-V LDO enabled High output voltage Port 1 pins with 1.8-V LDO enabled Min 4 4 VDD – 0.2 VDD – 0.9 VDD – 0.2 VDD – 0.9 2.7 2.2 2.1 2.0 1.6 Typ 5.6 5.6 – – – – 3.0 – 2.4 – 1.8 Max 8 8 – – – – 3.3 – 2.7 – 2.0 Units Notes kΩ kΩ V IOH ≤ 10 μA, VDD ≥ 3.0 V, maximum of 20 mA source current in all I/Os. V IOH ≤ 1 mA, VDD ≥ 3.0 V, maximum of 20 mA source current in all I/Os. V IOH ≤ 10 μA, VDD ≥ 3.0 V, maximum of 10 mA source current in all I/Os. V IOH ≤ 5 mA, VDD ≥ 3.0 V, maximum of 20 mA source current in all I/Os. V IOH ≤ 10 μA, VDD ≥ 3.1 V, maximum of 4 I/Os all sourcing 5 mA. V IOH ≤ 5 mA, VDD ≥ 3.1 V, maximum of 20 mA source current in all I/Os. V IOH ≤ 10 μA, VDD ≥ 3.0 V, maximum of 20 mA source current in all I/Os. V IOH ≤ 200 μA, VDD ≥ 3.0 V, maximum of 20 mA source current in all I/Os. V IOH ≤ 10 μA 3.0 V ≤ VDD ≤ 3.6 V 0°C ≤ TA ≤ 85 °C Maximum of 20 mA source current in all I/Os. V IOH ≤ 100 μA. 3.0 V ≤ VDD ≤ 3.6 V. 0°C ≤ TA ≤ 85 °C. Maximum of 20 mA source current in all I/Os. VOH10 High output voltage Port 1 pins with 1.8-V LDO enabled 1.5 – – Document Number: 001-54650 Rev. *E Page 11 of 30 [+] Feedback CY8C20234 Table 6. DC GPIO Specifications (continued) Symbol VOL Description Low output voltage Min – Typ – Max 0.75 Units Notes V IOL ≤ 20 mA, VDD ≥ 3.0 V, maximum of 60 mA sink current on even port pins (for example, P0[4] and P1[4]) and 60 mA sink current on odd port pins (for example, P0[3] and P1[5]). V V mV nA Gross tested to 1 μA pF Package and pin dependent TA = 25 °C pF Package and pin dependent TA = 25 °C VIL VIH VH IIL CIN COUT Input low voltage Input high voltage Input hysteresis voltage Input leakage (absolute value) Capacitive load on pins as input Capacitive load on pins as output – 2.0 – – 0.5 0.5 – – 140 1 1.7 1.7 0.8 – – 5 5 DC Analog Mux Bus Specifications Table 7 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C. These are for design guidance only. Table 7. DC Analog Mux Bus Specifications Symbol RSW Description Switch resistance to common analog bus Min – Typ – Max 450 Units Ω Notes DC POR and LVD Specifications Table 8 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C. These are for design guidance only. Table 8. DC POR and LVD Specifications Symbol VPPOR0 VPPOR1 VPPOR2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Description VDD value for PPOR trip PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b VDD value for LVD trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min – – – 2.34 2.54 2.75 2.85 2.96 – – 4.44 Typ 2.36 2.60 2.82 2.45 2.71 2.92 3.02 3.13 – – 4.73 Max 2.40 2.65 2.95 2.51[5] 2.78[6] 2.99[7] 3.09 3.20 – – 4.93 Units V V V V V V V V V V V Notes VDD must be greater than or equal to 2.5 V during startup, reset from the XRES pin, or reset from watchdog. Notes 5. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply. 6. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply. 7. Always greater than 50 mV above VPPOR (PORLEV = 10) for falling supply. Document Number: 001-54650 Rev. *E Page 12 of 30 [+] Feedback CY8C20234 DC Analog Reference Specifications Table 9 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C. These are for design guidance only. Table 9. DC Analog Reference Specifications Symbol BG Description Bandgap reference voltage Min 1.274 Typ 1.30 Max 1.326 Units V Notes DC Programming Specifications Table 10 lists the guaranteed minimum and maximum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C. These are for design guidance only. Flash Endurance and Retention specifications with the use of the EEPROM User Module are valid only within the range: 25 °C ± 20 °C during the Flash Write operation. Refer to the EEPROM User Module data sheet instructions for EEPROM Flash Write requirements outside of the 25 °C ± 20 °C temperature window. Table 10. DC Programming Specifications Symbol VDDP VDDLV VDDHV Description VDD for programming and erase Low VDD for verify High VDD for verify Min 4.5 Typ 5 Max 5.5 Units Notes V This specification applies to the functional requirements of external programmer tools V This specification applies to the functional requirements of external programmer tools V This specification applies to the functional requirements of external programmer tools V This specification applies to this device when it is executing internal flash writes mA V V mA mA V V – Erase/write cycles per block. – Erase/write cycles. Years Driving internal pull-down resistor. Driving internal pull-down resistor. 3.0 3.1 3.2 5.1 5.2 5.3 VDDIWRITE Supply voltage for flash write operation IDDP VILP VIHP IILP IIHP VOLV VOHV Supply current during programming or verify Input low voltage during programming or verify Input high voltage during programming or verify Input current when applying VILP to P1[0] or P1[1] during programming or verify Input current when applying VIHP to P1[0] or P1[1] during programming or verify Output low voltage during programming or verify 3.0 – 5.25 – – 2.2 – – – VDD – 1.0 1,000 128,000 10 5 – – – – – – – – – 25 0.8 – 0.2 1.5 0.75 VDD – – – Output high voltage during programming or verify FlashENPB Flash endurance (per block)[8] FlashENT Flash endurance (total)[9] FlashDR Flash data retention Notes 8. The erase/write cycle limit per block (FlashENPB) is only guaranteed if the device operates within one voltage range. Voltage ranges are 3.0 V to 3.6 V and 4.75 V to 5.25 V. 9. The maximum total number of allowed erase/write cycles is the minimum FlashENPB value multiplied by the number of flash blocks in the device. Document Number: 001-54650 Rev. *E Page 13 of 30 [+] Feedback CY8C20234 AC Electrical Characteristics AC Chip Level Specifications Table 11 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C. These are for design guidance only. Table 11. AC Chip-Level Specifications Symbol FCPU1 F32K1 F32KU FIMO12 CPU frequency ILO frequency ILO untrimmed frequency Description Min 0.71 15 5 Typ – 32 – Max 12.6 64 100 Units MHz kHz kHz Notes 12 MHz only for SLIMO Mode = 0 This specification applies when the ILO has been trimmed. After a reset and before the M8C processor starts to execute, the ILO is not trimmed. Trimmed using factory trim values. See Figure 4 on page 9, SLIMO Mode = 0. Trimmed using factory trim values. See Figure 4 on page 9, SLIMO Mode = 1. IMO frequency for 12 MHz 11.4 12 12.6 MHz FIMO6 IMO frequency for 6 MHz 5.5 6.0 6.5 MHz DCIMO DCILO tXRST tPOWERUP tJIT_IMO [10] IMO duty cycle ILO duty cycle External reset pulse width Time between end of POR state and CPU code execution 12 MHz IMO cycle-to-cycle jitter (RMS) 12 MHz IMO long-term N cycle-to-cycle jitter (RMS) 12 MHz IMO period jitter (RMS) 40 20 10 – – – – – 50 50 – – 16 200 600 100 60 80 – 250 100 1600 1400 900 % % μs V/ms ms ps ps ps N = 32 VDD slew rate during power-up. Power-up from 0 V. SRPOWERUP Power supply slew rate Note 10. Refer to Cypress Jitter Specifications Application Note – AN5054 at http://www.cypress.com for more information. Document Number: 001-54650 Rev. *E Page 14 of 30 [+] Feedback CY8C20234 AC GPIO Specifications Table 12 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C. These are for design guidance only. Table 12. AC GPIO Specifications Symbol FGPIO tRISE023 tRISE1 tFALL Description GPIO operating frequency Rise time, strong mode, Cload = 50 pF Ports 0, 2, 3 Rise time, strong mode, Cload = 50 pF Port 1 Fall time, strong mode, Cload = 50 pF all Ports Min 0 15 10 10 Typ – – – – Max 6.30 80 50 50 Units MHz ns ns ns Notes Normal strong mode, Port 1. VDD = 3.0 V to 3.6 V and 4.75 V to 5.25 V, 10% - 90% VDD = 3.0 V to 3.6 V, 10% - 90% VDD = 3.0 V to 3.6 V and 4.75 V to 5.25 V, 10% - 90% Figure 5. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% tRISE023 TRise023 tRISE1 TRise1 tTFall FALL AC Comparator Specifications Table 13 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C. These are for design guidance only. Table 13. AC Comparator Specifications Symbol tCOMP Description Comparator response time, 50 mV overdrive Min – – Typ – – Max 100 200 Units ns ns Notes VDD > 3.6 V 3.0 V ≤ VDD ≤ 3.6 V AC External Clock Specifications Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40°C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C. These are for design guidance only. Table 14. AC External Clock Specifications Symbol FOSCEXT – – – Frequency High period Low period Power-up IMO to switch Description Min 0.750 38 38 150 Typ – – – – Max 12.6 5300 – – Units MHz ns ns μs Notes Document Number: 001-54650 Rev. *E Page 15 of 30 [+] Feedback CY8C20234 AC Programming Specifications Table 15 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40°C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C. These are for design guidance only. Table 15. AC Programming Specifications Symbol tRSCLK tFSCLK tSSCLK tHSCLK FSCLK tERASEB tWRITE tDSCLK tDSCLK3 tPRGH tPRGC Description Rise time of SCLK Fall time of SCLK Data setup time to falling edge of SCLK Data hold time from falling edge of SCLK Frequency of SCLK Flash erase time (block) Flash block write time Data out delay from falling edge of SCLK Data out delay from falling edge of SCLK Total flash block program time (tERASEB + tWRITE), hot Total flash block program time (tERASEB + tWRITE), cold Min 1 1 40 40 0 – – – – – – Typ – – – – – 10 40 – – – – Max 20 20 – – 8 40 160 45 50 100 200 Units ns ns ns ns MHz ms ms ns ns ms ms VDD > 3.6 V 3.0 V ≤ VDD ≤ 3.6 V TJ ≥ 0 °C TJ < 0 °C Notes AC SPI Specifications Table 16 and Table 17 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C. These are for design guidance only. Table 16. SPI Master AC Specifications Symbol FSCLK DCSCLK tSETUP tHOLD tOUT_VAL tOUT_HIGH Parameter SCLK clock frequency SCLK duty cycle MISO to SCLK setup time SCLK to MISO hold time SCLK to MOSI valid time MOSI high time Min – – 40 40 – 40 Typ – 50 – – – – Max 12.6 – – – 40 – Units MHz % ns ns ns ns Notes Table 17. SPI Slave AC Specifications Symbol FSCLK tLOW tHIGH tSETUP tHOLD tSS_MISO tSCLK_MISO tSS_HIGH tSS_SCLK tSCLK_SS Parameter SCLK clock frequency SCLK low time SCLK high time MOSI to SCLK setup time SCLK to MOSI hold time SS low to MISO valid SCLK to MISO valid SS high time Time from SS low to first SCLK Time from last SCLK to SS high Min – 39.6 39.6 30 50 – – 50 2/FSCLK 2/FSCLK Typ – – – – – – – – – – Max 12.6 – – – – 153 125 – – – Units MHz ns ns ns ns ns ns ns ns ns Notes Document Number: 001-54650 Rev. *E Page 16 of 30 [+] Feedback CY8C20234 AC I2C Specifications Table 18 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C. These are for design guidance only. Table 18. AC Characteristics of the I2C SDA and SCL Pins Symbol FSCLI2C tHDSTAI2C tLOWI2C tHIGHI2C tSUSTAI2C tHDDATI2C tSUDATI2C tSUSTOI2C tBUFI2C tSPI2C SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated LOW period of the SCL clock HIGH period of the SCL clock Setup time for a repeated START condition Data hold time Data setup time Setup time for STOP condition Bus free time between a STOP and START condition Pulse width of spikes are suppressed by the input filter Description Standard Mode Min 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 – Max 100[11] – – – – – – – – – Fast Mode Min 0 0.6 1.3 0.6 0.6 0 100[12] 0.6 1.3 0 Max 400[11] – – – – – – – – 50 Units kHz μs μs μs μs μs ns μs μs ns Figure 6. Definition for Timing for Fast/Standard Mode on the I2C Bus I2C_SDA tSUDATI2C tHDSTAI2C I2C_SCL tSPI2C tHDDATI2C tSUSTAI2C tBUFI2C tHIGHI2C S START Condition tLOWI2C Sr Repeated START Condition tSUSTOI2C P STOP Condition S Notes 11. FSCLI2C is derived from SysClk of the PSoC. This specification assumes that SysClk is operating at 12 MHz, nominal. If SysClk is at a lower frequency, then the FSCLI2C specification adjusts accordingly. 12. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSUDATI2C ≥ 250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSUDATI2C = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 001-54650 Rev. *E Page 17 of 30 [+] Feedback CY8C20234 Packaging Information This section illustrates the packaging specifications for the automotive CY8C20x34 PSoC device along with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com. For information on the preferred dimensions for mounting QFN packages, see the application note “Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages” available at http://www.amkor.com. Figure 7. 16-Pin (3 × 3 × 0.60 mm) QFN (Sawn) 001-09116 *E Thermal Impedances Table 19 illustrates the minimum solder reflow peak temperature to achieve good solderability. Table 19. Thermal Impedances Per Package Package 16-pin QFN Typical θJA [12] 46 °C/W Solder Reflow Specifications Table 20 shows the solder reflow temperature limits that must not be exceeded. Table 20. Solder Reflow Specifications Package 16-pin QFN Maximum Peak Temperature (TC) 260 °C Maximum Time above TC – 5 °C 30 seconds Note 12. TJ = TA + Power × θJA Document Number: 001-54650 Rev. *E Page 18 of 30 [+] Feedback CY8C20234 Tape and Reel Information Figure 8. 16-Pin QFN Carrier Tape Drawing ALL DIMENSIONS ARE IN MILLIMETERS 001-11785 ** Table 21. Tape and Reel Specifications Package 16-Pin QFN Cover Tape Width (mm) 9.2 Hub Size (inches) 7 Minimum Leading Empty Pockets 63 Minimum Trailing Empty Pockets 38 Standard Full Reel Quantity 2500 Document Number: 001-54650 Rev. *E Page 19 of 30 [+] Feedback CY8C20234 Development Tool Selection This section presents the development tools available for the automotive CY8C20x34 family. Software PSoC Designer At the core of the PSoC development software suite is PSoC Designer, used to generate PSoC firmware applications. PSoC Designer is available free of charge at http://www.cypress.com and includes a free C compiler. PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free of charge at http://www.cypress.com. Evaluation Tools All evaluation tools can be purchased from the Cypress Online Store. The online store also has the most up to date information on kit contents, descriptions, and availability. CY3210-PSoCEval1 The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, an RS-232 port, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: ■ ■ ■ ■ ■ ■ Evaluation Board with LCD Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2) PSoC Designer Software CD Getting Started Guide USB 2.0 Cable Development Kits All development kits can be purchased from the Cypress Online Store. The online store also has the most up to date information on kit contents, descriptions, and availability. CY3215-DK Basic Development Kit The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. PSoC Designer also supports the advance emulation features. The kit includes: ■ ICE-Cube Unit ■ 28-Pin PDIP Emulation Pod for CY8C29466-24PXI ■ 28-Pin CY8C29466-24PXI PDIP PSoC Device Samples (two) ■ PSoC Designer Software CD ■ ISSP Cable ■ MiniEval Socket Programming and Evaluation board ■ Backward Compatibility Cable (for connecting to legacy Pods) ■ Universal 110/220 Power Supply (12 V) ■ European Plug Adapter ■ USB 2.0 Cable ■ Getting Started Guide ■ Development Kit Registration form CY3280-BK1 The CY3280-BK1 Universal CapSense Control Kit is designed for easy prototyping and debug of CapSense designs with pre defined control circuitry and plug-in hardware. The kit comes with a control boards for CY8C20x34 and CY8C21x34 devices as well as a breadboard module and a button(5)/slider module. CY3210-20X34 Evaluation Pod (EvalPod) PSoC EvalPods are pods that connect to the ICE In-Circuit Emulator (CY3215-DK kit) to allow debugging capability. They can also function as a standalone device without debugging capability. The EvalPod has a 28-pin DIP footprint on the bottom for easy connection to development kits or other hardware. The top of the EvalPod has prototyping headers for easy connection to the device's pins. CY3210-20X34 provides evaluation of the CY8C20x34 PSoC device family. Document Number: 001-54650 Rev. *E Page 20 of 30 [+] Feedback CY8C20234 Device Programmers All device programmers are purchased from the Cypress Online Store. CY3210-MiniProg1 The CY3210-MiniProg1 kit allows a user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes: ■ ■ ■ ■ ■ ■ CY3207ISSP In-System Serial Programmer (ISSP) The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. Note CY3207ISSP needs special software and is not compatible with PSoC Programmer. This software is free and can be downloaded from http://www.cypress.com. The kit includes: ■ ■ ■ ■ CY3207 Programmer Unit PSoC ISSP Software CD 110 ~ 240 V Power Supply, Euro-Plug Adapter USB 2.0 Cable MiniProg Programming Unit MiniEval Socket Programming and Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample PSoC Designer Software CD Getting Started Guide USB 2.0 Cable Accessories (Emulation and Programming) Table 22. Emulation and Programming Accessories Part Number CY8C20234-12LKXA Pin Package 16-pin QFN Pod Kit [13] – Foot Kit [14] – Prototyping Module CY3210-20X34 Adapter [15] – Notes 13. Pod kit contains an emulation pod, a flex-cable (connects the pod to the ICE), two feet, and device samples. 14. Foot kit includes surface mount feet that is soldered to the target PCB. 15. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters is found at http://www.emulation.com. Document Number: 001-54650 Rev. *E Page 21 of 30 [+] Feedback CY8C20234 Ordering Information Table 23 lists the automotive CY8C20x34 PSoC device key package features and ordering codes. Table 23. PSoC Device Key Features and Ordering Information Package 16-pin (3 × 3 × 0.6 mm) QFN, sawn Ordering Code CY8C20234-12LKXA Flash SRAM Digital CapSense Digital Analog Analog XRES (Bytes) (Bytes) Blocks Blocks I/O Pins Inputs Outputs Pin 8K 8K 512 512 0 0 1 1 13 13 13 13 0 0 Yes Yes 16-pin (3 × 3 × 0.6 mm) CY8C20234-12LKXAT QFN, sawn (tape and reel) Ordering Code Definitions CY 8 C 20 xxx- 12 xx Package Type: Thermal Rating: PX = PDIP Pb-free A = Automotive –40 °C to +85 °C SX = SOIC Pb-free C = Commercial PVX = SSOP Pb-free E = Automotive Extended –40 °C to +125 °C LFX/LKX = QFN Pb-free I = Industrial AX = TQFP Pb-free CPU Speed: 12 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = PSoC Company ID: CY = Cypress Document Number: 001-54650 Rev. *E Page 22 of 30 [+] Feedback CY8C20234 Reference Information Acronyms Table 24 lists the acronyms that are used in this document. Table 24. Acronyms Used in this Datasheet Acronym AC ADC AEC API CMOS CPU DAC DC EEPROM GPIO I/O ICE IDE ILO IMO ISSP LCD LDO LED Description alternating current analog-to-digital converter Automotive Electronics Council application programming interface complementary metal oxide semiconductor central processing unit digital-to-analog converter direct current electrically erasable programmable read-only memory general-purpose I/O input/output in-circuit emulator integrated development environment internal low-speed oscillator internal main oscillator in-system serial programming liquid crystal display low dropout regulator light-emitting diode Acronym LVD MCU MIPS PCB PDIP PGA POR PPOR PSoC® PWM QFN RMS SLIMO SPI SRAM SROM USB WDT XRES Description low voltage detect microcontroller unit million instructions per second printed circuit board plastic dual inline package programmable gain amplifier power-on reset precision (POR) Programmable System-on-Chip pulse-width modulator quad flat no leads root mean square slow IMO serial peripheral interface static random-access memory supervisory read-only memory universal serial bus watchdog timer external reset Reference Documents PSoC® CY8C20x34 and PSoC® CY8C20x24 Technical Reference Manual (TRM) (001-13033) Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 (001-14503) Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com. Document Number: 001-54650 Rev. *E Page 23 of 30 [+] Feedback CY8C20234 Document Conventions Units of Measure Table 25 lists the units of measures. Table 25. Units of Measure Symbol °C KB kHz kΩ MHz µA µs mA mm ms 1024 bytes kilohertz kilohm megahertz microampere microsecond milliampere millimeter millisecond Unit of Measure degree Celsius mV nA ns Ω % pF ps V W Symbol millivolt nanoampere nanosecond ohm percent picofarad picosecond volt watt Unit of Measure Numeric Conventions Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals. Glossary active high 1. A logic signal having its asserted state as the logic 1 state. 2. A logic signal having the logic 1 state as the higher voltage of the two states. The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more. A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation. A series of software routines that comprise an interface between a computer application and lower level services and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create software applications. A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. A stable voltage reference design that matches the positive temperature coefficient of VT with the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference. 1. The frequency range of a message or information processing system measured in hertz. 2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. 1. A systematic deviation of a value from a reference value. 2. The amount by which the average of a set of values departs from a reference value. 3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. analog blocks analog-to-digital (ADC) API (Application Programming Interface) asynchronous bandgap reference bandwidth bias Document Number: 001-54650 Rev. *E Page 24 of 30 [+] Feedback CY8C20234 Glossary (continued) block 1. A functional unit that performs a single function, such as an oscillator. 2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or an analog PSoC block. 1. A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which data is written. 2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. An amplifier used to lower the output impedance of a system. 1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0]. 3. One or more conductors that serve as a common connection for a group of related devices. The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks. An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. A program that translates a high level language, such as C, into machine language. In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’. An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. buffer bus clock comparator compiler configuration space crystal oscillator cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear check (CRC) feedback shift register. Similar calculations may be used for a variety of other purposes such as data compression. data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions. A hardware and software system that allows the user to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. A period of time when neither of two or more signals are in their active state or in transition. The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator, pseudo-random number generator, or SPI. A device that changes a digital signal to an analog signal of corresponding magnitude. The analogto-digital (ADC) converter performs the reverse operation. The relationship of a clock period high time to its low time, expressed as a percent. debugger dead band digital blocks digital-to-analog (DAC) duty cycle Document Number: 001-54650 Rev. *E Page 25 of 30 [+] Feedback CY8C20234 Glossary (continued) emulator Duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop and return to a pre-defined state. An electrically programmable and erasable, non-volatile technology that provides users with the programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is off. The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash space that may be protected. A Flash block holds 64 bytes. The number of cycles or events per unit of time, for a periodic function. The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually expressed in dB. A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5 V and pulled high with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. The in-circuit emulator that allows users to test the project in a hardware environment, while viewing the debugging device activity in a software environment (PSoC Designer). external reset (XRES) flash Flash block frequency gain I2C ICE input/output (I/O) A device that introduces data into or extracts data from a system. interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends with the RETI instruction, returning the device to the point in the program where it left normal program execution. 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on serial data streams. 2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles. interrupt service routine (ISR) jitter low-voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls below a (LVD) selected threshold. M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the Flash, SRAM, and register space. A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device. master device Document Number: 001-54650 Rev. *E Page 26 of 30 [+] Feedback CY8C20234 Glossary (continued) microcontroller An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor. The reference to a circuit containing both analog and digital techniques and components. A device that imposes a signal on a carrier. 1. A disturbance that affects a signal and that may distort the information carried by the signal. 2. The random variations of one or more characteristics of any entity such as voltage, current, or data. A circuit that may be crystal controlled and is used to generate a clock frequency. A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names. A group of pins, usually eight. A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is one type of hardware reset. Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-onChip™ is a trademark of Cypress. mixed-signal modulator noise oscillator parity phase-locked loop (PLL) pinouts port power on reset (POR) PSoC® PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology. pulse width An output in the form of duty cycle which varies as a function of the applied measurand modulator (PWM) RAM An acronym for random access memory. A data-storage device from which data can be read out and new data can be written in. A storage device with a specific capacity, such as a bit or byte. A means of bringing a system back to a know state. See hardware reset and software reset. An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in. 1. Pertaining to a process in which all events occur one after the other. 2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. register reset ROM serial Document Number: 001-54650 Rev. *E Page 27 of 30 [+] Feedback CY8C20234 Glossary (continued) settling time The time it takes for an output signal or value to stabilize after the input has changed from one value to another. A memory storage device that sequentially shifts a word either left or right to output a stream of serial data. A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. The controlling device is called the master device. An acronym for static random access memory. A memory device allowing users to store and retrieve data at a high rate of speed. The term static is used because, after a value has been loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is removed from the device. An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code, operating from Flash. A signal following a character or block that prepares the receiving device to receive the next character or block. 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. A system whose operation is synchronized by a clock signal. A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming Interface) for the peripheral function. The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program. A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V. A name for a power net meaning "voltage source." The most negative power supply signal. A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time. shift register slave device SRAM SROM stop bit synchronous tri-state UART user modules user space VDD VSS watchdog timer Document Number: 001-54650 Rev. *E Page 28 of 30 [+] Feedback CY8C20234 Document History Page Document Title: CY8C20234 Automotive PSoC® Programmable System-on-Chip Document Number: 001-54650 Revision ** *A ECN 2743436 2799448 Orig. of Change MASJ/AESA BTK Submission Date 07/24/09 11/05/09 New data sheet. Updated Features section. Updated text of PSoC Functional Overview section. Updated Getting Started section. Made corrections and minor text edits to Pinouts section. Changed the name of some sections to improve consistency. Added clarifying comments to some electrical specifications. Fixed all AC specifications to conform to a ±5% IMO accuracy. Made other miscellaneous minor text edits. Deleted some non-applicable or redundant information. Improved and edited content in Development Tool Selection section. Improved the bookmark structure. Changed FlashENT, FOSCEXT, TERASEB, and TWRITE electrical specifications according to MASJ input. Added and slightly modified the expanded SPI AC specifications from 001-05356 Rev *I. Added a table of contents. Added TPRGH, TPRGC, F32KU, DCILO, and TPOWERUP electrical specifications. Updated the footnotes for Table 10, “DC Programming Specifications,” on page 13. Added maximum values and updated typical values for TERASEB and TWRITE electrical specifications. Replaced TRAMP electrical specification with SRPOWERUP electrical specification. Changed FIMO6 electrical specification to have an 8.33% accuracy instead of 5%. Added “Contents” on page 2. Updated Cypress website links. Updated CapSense Analog System. Removed PSoC Designer 4.4 reference in PSoC Designer Software Subsystems. Added TBAKETEMP and TBAKETIME parameters in Absolute Maximum Ratings. Removed DC Low Power Comparator Specifications, AC Analog Mux Bus Specifications, and AC Low Power Comparator Specifications. Updated Packaging Information. Added Solder Reflow Peak Temperature. Removed Third Party Tools and Build a PSoC Emulator into Your Board. Updated links in Sales, Solutions, and Legal Information. Under section “AC Comparator Amplifier Specifications”, the caption for spec table changed from “AC Operational Amplifier Specifications” to “AC Comparator Specifications”. Also the section heading changed to AC Comparator specifications. Updated I2C timing diagram to improve clarity. Added VDDP, VDDLV, and VDDHV electrical specifications to give more information for programming the device. Updated solder reflow temperature specifications to give more clarity. Updated the jitter specifications. Added PSoC Device Characteristics table. Updated the F32KU electrical specification. Added RPD electrical specification. Updated note for the TSTG electrical specification to add more clarity. Updated Units of Measure, Acronyms, Glossary, and References sections. Added Tape and Reel Specifications section. Description of Change *B 2822792 BTK/AESA 12/07/2009 *C 2888007 NJF 03/30/2010 *D 3043236 ARVM 09/30/10 *E 3272879 BTK/NJF 06/10/11 Document Number: 001-54650 Rev. *E Page 29 of 30 [+] Feedback CY8C20234 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-54650 Rev. *E Revised June 10, 2011 Page 30 of 30 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback