CY8C20236A-24LKXI

CapSense Applications CapSense Applications CY8C20X36A/46A/66A/96A ® Features ■ Operating Range: 1.71 V to 5.5 V ® ■ Low power CapSense block ❐ Configurable capacitive sensing elements ❐ Supports SmartSense ❐ Supports a combination of CapSense buttons, sliders, touchpads, touchscreens, and proximity sensors ■ Powerful Harvard-architecture processor ❐ M8C CPU speed can be up to 24 MHz or sourced by an external crystal, resonator, or clock signal ❐ Low power at high speed ❐ Interrupt controller ❐ Temperature range: –40 °C to +85 °C ■ Flexible on-chip memory ❐ Three program/data storage size options: • CY8C20x36A: 8 KB flash / 1 KB SRAM • CY8C20x46A, CY8C20x96A: 16 KB flash/2 KB SRAM • CY8C20x66A: 32 KB flash/2 KB SRAM ❐ 50,000 flash erase/write cycles ❐ Partial flash updates ❐ Flexible protection modes ❐ In-system serial programming (ISSP) ■ Full-speed USB ❐ Available on CY8C20646A, CY8C20666A, CY8C20x96A only ❐ 12 Mbps USB 2.0 compliant ❐ Eight unidirectional endpoints ❐ One bidirectional control endpoint ❐ Dedicated 512 byte buffer ❐ Internally regulated at 3.3 V ■ Precision, programmable clocking ❐ Internal main oscillator (IMO): 6/12/24 MHz ± 5% ❐ Internal low speed oscillator (ILO) at 32 kHz for watchdog and sleep timers ❐ Precision 32 kHz oscillator for optional external crystal ❐ 0.25% accuracy for USB with no external components (CY8C20646A, CY8C20666A, CY8C20x96A only) ■ Programmable pin configurations ❐ Up to 36 general-purpose I/Os (GPIOs) (depending on package) ❐ Dual mode GPIO: All GPIOs support digital I/O and analog inputs ❐ 25-mA sink current on each GPIO • 120 mA total sink current on all GPIOs ❐ Pull-up, high Z, open-drain modes on all GPIOs ❐ CMOS drive mode – 5 mA source current on ports 0 and 1 and 1 mA on ports 2, 3, and 4 • 20 mA total source current on all GPIOs ❐ Selectable, regulated digital I/O on port 1 ❐ Configurable input threshold on port 1 ❐ Hot-swap capability on all Port 1 GPIO ■ Versatile analog mux ❐ Common internal analog bus ❐ Simultaneous connection of I/O ❐ High power supply rejection ratio (PSRR) comparator ❐ Low-dropout voltage regulator for all analog resources Additional system resources 2 ❐ I C Slave: • Selectable to 50 kHz, 100 kHz, or 400 kHz • No clock stretching (under most conditions) • Implementation during sleep modes with less than 100 µA • Hardware address validation ❐ SPI master and slave: Configurable 46.9 kHz to 12 MHz ❐ Three 16-bit timers ❐ Watchdog and sleep timers ❐ Internal voltage reference ❐ Integrated supervisory circuit ❐ 8 to 10-bit incremental analog-to-digital converter (ADC) • Not available on CY8x20xx6AN versions ❐ Two general-purpose high speed, low power analog comparators Complete development tools ❐ Free development tool (PSoC Designer™) ❐ Full-featured, in-circuit emulator (ICE) and programmer ❐ Full-speed emulation ❐ Complex breakpoint structure ❐ 128 KB trace memory Package options ❐ CY8C20x36A: • 16-Pin 3 × 3 × 0.6 mm QFN • 24-Pin 4 × 4 × 0.6 mm QFN • 32-Pin 5 × 5 × 0.6 mm QFN • 48-Pin SSOP • 48-Pin 7 × 7 × 1.0 mm QFN ❐ CY8C20x46A: • 16-Pin 3 × 3 × 0.6 mm QFN • 24-Pin 4 × 4 × 0.6 mm QFN • 30-Ball WLCSP • 32-Pin 5 × 5 × 0.6 mm QFN • 48-Pin SSOP • 48-Pin 7 × 7 × 1.0 mm QFN (with USB) ❐ CY8C20x96A: • 24-Pin 4 × 4 × 0.6 mm QFN (with USB) • 32-Pin 5 × 5 × 0.6 mm QFN (with USB) ❐ CY8C20x66A: • 32-Pin 5 × 5 × 0.6 mm QFN • 48-Pin 7 × 7 × 1.0 mm QFN (with USB) • 48-Pin SSOP • 30-Ball WLCSP • San Jose, CA 95134-1709 • 408-943-2600 Revised September 30, 2010 [+] Feedback ■ ■ ■ Cypress Semiconductor Corporation Document Number: 001-54459 Rev. *E • 198 Champion Court CY8C20X36A/46A/66A/96A Logic Block Diagram Port 4 Port 3 Port 2 Port 1 Port 0 1.8/2.5/3V LDO PWRSYS [1] (Regulator) PSoC CORE SYSTEM BUS Global Analog Interconnect 1K/2K SRAM Interrupt Controller 8K/16K/32K Flash Nonvolatile Memory Sleep and Watchdog Supervisory ROM (SROM) CPU Core (M8C) 6/12/24 MHz Internal Main Oscillator (IMO) Internal Low Speed Oscillator (ILO) Multiple Clock Sources CAPSENSE SYSTEM CapSense Module Two Comparators Analog Reference Analog Mux SYSTEM BUS USB I2C Slave Internal Voltage References System Resets POR and LVD SPI Master/ Slave Three 16-Bit Programmable Timers Digital Clocks SYSTEM RESOURCES Note 1. Internal voltage regulator for internal circuitry Document Number: 001-54459 Rev. *E Page 2 of 43 [+] Feedback CY8C20X36A/46A/66A/96A Contents CapSense Applications .................................................... 1 Features ............................................................................. 1 Logic Block Diagram ........................................................ 2 PSoC® Functional Overview ............................................ 4 PSoC Core .................................................................. 4 CapSense System ....................................................... 4 Additional System Resources ..................................... 5 Getting Started .................................................................. 5 Application Notes ........................................................ 5 Development Kits ........................................................ 5 Training ....................................................................... 5 CYPros Consultants .................................................... 5 Solutions Library .......................................................... 5 Technical Support ....................................................... 5 Designing with PSoC Designer ....................................... 6 Select Components ..................................................... 6 Configure Components ............................................... 6 Organize and Connect ................................................ 6 Generate, Verify, and Debug ....................................... 6 Pinouts .............................................................................. 7 16-Pin QFN (No E-Pad) ............................................ 7 24-Pin QFN .............................................................. 8 24-Pin QFN with USB ................................................. 9 30-Ball Part Pinout .................................................... 10 32-Pin QFN ............................................................. 11 32-Pin QFN (with USB) ............................................ 12 48-Pin SSOP ............................................................ 13 48-Pin QFN ............................................................. 14 48-Pin QFN with USB .............................................. 15 48-Pin QFN OCD ...................................................... 16 Electrical Specifications ................................................ 17 Absolute Maximum Ratings ....................................... 17 Operating Temperature ............................................. 17 DC Chip-Level Specifications .................................... 18 DC GPIO Specifications ............................................ 19 DC Analog Mux Bus Specifications ........................... 21 DC Low Power Comparator Specifications ............... 21 Comparator User Module Electrical Specifications ... 22 ADC Electrical Specifications ................................... 22 DC POR and LVD Specifications .............................. 23 DC Programming Specifications ............................... 23 AC Chip-Level Specifications .................................... 24 AC General Purpose I/O Specifications .................... 25 AC Comparator Specifications .................................. 26 AC External Clock Specifications .............................. 26 AC Programming Specifications ................................ 27 AC I2C Specifications ................................................ 28 Packaging Information ................................................... 31 Thermal Impedances ................................................ 34 Capacitance on Crystal Pins .................................... 34 Solder Reflow Peak Temperature ............................. 34 Development Tool Selection ......................................... 35 Software .................................................................... 35 Development Kits ...................................................... 35 Evaluation Tools ............................................................. 36 Device Programmers ................................................. 36 Accessories (Emulation and Programming) .............. 37 Third Party Tools ....................................................... 37 Build a PSoC Emulator into Your Board .................... 37 Ordering Information ...................................................... 38 Ordering Code Definitions ............................................ 39 Acronymns ...................................................................... 40 Acronyms Used ......................................................... 40 Reference Documents .................................................... 40 Document Conventions ............................................. 40 Units of Measure ....................................................... 40 Numeric Naming ........................................................ 41 Glossary .......................................................................... 41 Document History Page ................................................. 42 Sales, Solutions, and Legal Information ...................... 43 Worldwide Sales and Design Support ....................... 43 Products .................................................................... 43 PSoC Solutions ......................................................... 43 Document Number: 001-54459 Rev. *E Page 3 of 43 [+] Feedback CY8C20X36A/46A/66A/96A PSoC® Functional Overview The PSoC family consists of on-chip controller devices, which are designed to replace multiple traditional microcontroller unit (MCU)-based components with one, low cost single-chip programmable component. A PSoC device includes configurable analog and digital blocks, and programmable interconnect. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. The architecture for this device family, as shown in the Logic Block Diagram on page 2, consists of three main areas: ■ ■ ■ Figure 1. CapSense System Block Diagram CS1 IDAC Analog Global Bus CS2 CSN Vr Reference Buffer The Core CapSense Analog System System Resources (including a full-speed USB port). Cinternal Comparator Mux Mux Cexternal (P0[1] or P0[3]) A common, versatile bus allows connection between I/O and the analog system. Each CY8C20x36A/46A/66A/96A PSoC device includes a dedicated CapSense block that provides sensing and scanning control circuitry for capacitive sensing applications. Depending on the PSoC package, up to 36 GPIO are also included. The GPIO provides access to the MCU and analog mux. Refs Cap Sense Counters CSCLK PSoC Core The PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO and ILO. The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a 4-MIPS, 8-bit Harvard-architecture microprocessor. IMO CapSense Clock Select Oscillator Analog Multiplexer System The Analog Mux Bus can connect to every GPIO pin. Pins are connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with the CapSense block comparator. Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include: ■ ■ ■ CapSense System The analog system contains the capacitive sensing hardware. Several hardware algorithms are supported. This hardware performs capacitive sensing and scanning without requiring external components. The analog system is composed of the CapSense PSoC block and an internal 1 V or 1.2 V analog reference, which together support capacitive sensing of up to 33 inputs[2]. Capacitive sensing is configurable on each GPIO pin. Scanning of enabled CapSense pins are completed quickly and easily across multiple ports. SmartSense™ SmartSense is an innovative solution from Cypress that removes manual tuning of CapSense applications. This solution is easy to use and provides a robust noise immunity. It is the only autotuning solution that establishes, monitors, and maintains all required tuning parameters. SmartSense allows engineers to go from prototyping to mass production without re-tuning for manufacturing variations in PCB and/or overlay material properties. Complex capacitive sensing interfaces, such as sliders and touchpads. Chip-wide mux that allows analog input from any I/O pin. Crosspoint connection between any I/O pin combinations. Note 2. 36 GPIOs = 33 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor. Document Number: 001-54459 Rev. *E Page 4 of 43 [+] Feedback CY8C20X36A/46A/66A/96A Additional System Resources System resources provide additional capability, such as configurable USB and I2C slave, SPI master/slave communication interface, three 16-bit programmable timers, and various system resets supported by the M8C. These system resources provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. The merits of each system resource are listed here: ■ Getting Started The quickest way to understand PSoC silicon is to read this datasheet and then use the PSoC Designer Integrated Development Environment (IDE). This datasheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in depth information, along with detailed programming details, see the Technical Reference Manual for the CY8C20x36A/46A/66A/96A PSoC devices. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device datasheets on the web at www.cypress.com/psoc. The I2C slave/SPI master-slave module provides 50/100/400 kHz communication over two wires. SPI communication over three or four wires runs at speeds of 46.9 kHz to 3 MHz (lower for a slower system clock). The I2C hardware address recognition feature reduces the already low power consumption by eliminating the need for CPU intervention until a packet addressed to the target device is received. The I2C enhanced slave interface appears as a 32-byte RAM buffer to the external I2C master. Using a simple predefined protocol, the master controls the read and write pointers into the RAM. When this method is enabled, the slave does not stall the bus when receiving data bytes in active mode. For usage details, refer to the application note I2C Enhanced Slave Operation - AN56007. Low-voltage detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced poweron-reset (POR) circuit eliminates the need for a system supervisor. An internal reference provides an absolute reference for capacitive sensing. A register-controlled bypass mode allows the user to disable the LDO regulator. ■ Application Notes Application notes are an excellent introduction to the wide variety of possible PSoC designs. They are located at www.cypress.com/psoc. Select Application Notes under the Documentation tab. ■ Development Kits PSoC Development Kits are available online from Cypress at www.cypress.com/shop and through a growing number of regional and global distributors, which include Arrow, Avnet, DigiKey, Farnell, Future Electronics, and Newark. Refer to Development Kits on page 35. ■ Training Free PSoC and CapSense technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training. The training covers a wide variety of topics and skill levels to assist you in your designs. ■ ■ CYPros Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to www.cypress.com/cypros. Solutions Library Visit our growing library of solution focused designs at www.cypress.com/solutions. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Technical Support For assistance with technical issues, search KnowledgeBase articles and forums at www.cypress.com/support. If you cannot find an answer to your question, create a technical support case or call technical support at 1-800-541-4736. Document Number: 001-54459 Rev. *E Page 5 of 43 [+] Feedback CY8C20X36A/46A/66A/96A Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is summarized in the following four steps: 1. Select components 2. Configure components 3. Organize and connect 4. Generate, verify, and debug Organize and Connect You build signal chains by interconnecting user modules to each other and the I/O pins. You perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources. Generate, Verify, and Debug When you are ready to test the hardware configuration or move to developing code for the project, you perform the ‘Generate Configuration Files’ step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. Based on your design, software is generated. Application programming interfaces (APIs) are provided with high level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. A complete code development environment allows you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside PSoC Designer’s Debugger (access by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. Select Components PSoC Designer provides a library of prebuilt, pretested hardware peripheral components. These components are called user modules. User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and programmable system-on-chip varieties. Configure Components Each of the components you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a Timer User Module configures one digital PSoC block. The user module parameters permit you to establish the period, mode, and timer clock. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. User modules are documented in datasheets that are viewed directly in PSoC Designer. These datasheets explain the internal operation of the component and provide performance specifications. Each datasheet describes the use of each user module parameter and other information you may need to successfully implement your design. Document Number: 001-54459 Rev. *E Page 6 of 43 [+] Feedback CY8C20X36A/46A/66A/96A Pinouts The CY8C20x36A/46A/66A/96A PSoC device is available in a variety of packages, which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. However, VSS, VDD, and XRES are not capable of Digital I/O. 16-Pin QFN (No E-Pad) Table 1. Pin Definitions – CY8C20236A, CY8C20246A PSoC Device Digital I/O I/O IOHR IOHR IOHR IOHR Power IOHR IOHR IOHR Input IOH Power IOH IOH IOH I I I I I I I Analog I I I I I I P0[1], AI P0[3], AI P0[7], AI Vdd 16 15 AI, XOut, P2[5] AI , XIn, P2[3] AI , I2 C SCL, SPI SS, P1[7] AI , I2 C SDA, SPI MISO, P1[5] 1 2 14 13 12 10 9 K AI, SPI CL , P1[3] AI, ISSP CLK SPI MOSI, P1[1] , Vss [3,4] K AI, ISSP DATA , I2C SDA, SPI CL , P1[0] [3] Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type Name Description Figure 2. CY8C20236A, CY8C20246A PSoC Device P2[5] Crystal output (XOut) P2[3] Crystal input (XIn) P1[7] I2C SCL, SPI SS P1[5] I C SDA, SPI MISO P1[3] SPI CLK P1[1] ISSP CLK[3], I2C SCL, SPI MOSI VSS Ground connection P1[0] ISSP DATA[3], I2C SDA, SPI CLK[4] P1[2] P1[4] Optional external clock (EXTCLK) XRES Active high external reset with internal pull-down P0[4] VDD P0[7] P0[3] Integrating input P0[1] Integrating input Supply voltage 2 LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output. Notes 3. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 4. Alternate SPI clock. Document Number: 001-54459 Rev. *E 5 6 7 8 3 4 QFN ( Top View 11 ) P0[4] , AI XRES P1[4] , EXTCLK, AI P1[2] , AI Page 7 of 43 [+] Feedback CY8C20X36A/46A/66A/96A 24-Pin QFN Table 2. Pin Definitions š CY8C20336A, CY8C20346A [5] Type Pin No. Digital Analog Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CP IOH IOH IOH IOH Power I/O IOH IOH IOH IOH Power I I I I Power IOHR IOHR IOHR IOHR Input I I I I I I I I I I/O I/O I/O IOHR IOHR IOHR IOHR I I I I I I I P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] NC VSS P1[0] P1[2] P1[4] P1[6] XRES P2[0] P0[0] P0[2] P0[4] P0[6] Active high external reset with internal pull-down [6, 7] Description Crystal output (XOut) Figure 3. CY8C20336A, CY8C20346A PSoC Device P0[7], AI 21 P0[1], AI P0[3], AI Crystal input (XIn) I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK ISSP CLK[6], I2C SCL, SPI MOSI No connection Ground connection ISSP DATA[6], I2C SDA, SPI CLK[7] Optional external clock input (EXTCLK) P0[5], AI 24 22 23 20 19 P0[6], AI 18 17 16 15 14 13 Vdd A I, X O u t, P 2 [5] A I, X In , P 2 [3 ] 1 2 3 4 5 6 11 AI, ISSP DATA , I2C SDA, SPI CLK, P1[0] 10 SPI MOSI, P1[1] AI, P1[2] AI, ISSP CLK , I2C SCL VDD P0[7] P0[5] P0[3] P0[1] VSS Supply voltage Integrating input Integrating input Center pad must be connected to ground LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output. Notes 5. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 6. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 7. Alternate SPI clock. Document Number: 001-54459 Rev. *E 2 AI, EXTCLK, P1[4] NC 2 Vss 12 7 8 9 A I, A I, I2 C S C L , S P I S S , A I, I2 C S D A , S P I M IS O , A I, S P I C L K , P 2 [1 ] P 1 [7 ] P 1 [5 ] P 1 [3 ] QFN (T o p V ie w ) P 0 [4 ], A I P 0 [2 ], A I P 0 [0 ], A I P 2 [0 ], A I XRES P 1 [6 ], A I Page 8 of 43 [+] Feedback CY8C20X36A/46A/66A/96A 24-Pin QFN with USB Table 3. Pin Definitions – CY8C20396A PSoC Device [8] Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CP Type Digital I/O I/O I/O IOHR IOHR IOHR IOHR Power I/O I/O Power IOHR IOHR IOHR IOHR I I I I I I Analog I I I I I I I Name P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] VSS D+ DVDD P1[0] P1[2] P1[4] P1[6] XRES P0[0] P0[2] P0[4] P0[6] P0[7] P0[5] P0[3] P0[1] VSS Integrating input Integrating input Thermal pad must be connected to Ground Active high external reset with internal pull-down [9] Description Figure 4. CY8C20396A PSoC Device P0[1], AI P0[3], AI P0[5], AI P0[7], AI P0[6], AI P0[4], AI I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK ISSP CLK , I C SCL, SPI MOSI Ground USB D+ USB DSupply ISSP DATA[9], I2C SDA, SPI CLK[10] Optional external clock input (EXTCLK) [9] 2 24 23 22 21 P2[5], AI P2[3], AI 20 19 1 2 3 4 5 6 18 17 16 14 AI, ISSP CLK, I2C SCL, SPI MOSI, P1[1] Vss D+ DVDD 9 10 RESET INPUT IOH IOH IOH IOH IOH IOH IOH IOH Power I I I I I I I I LEGEND I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output Notes 8. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 9. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 10. Alternate SPI clock. Document Number: 001-54459 Rev. *E [9, 10] AI, ISSP DATA, I2C SDA, SPI CLK, P1[0] 11 12 7 8 P2[1], AI AI, I 2 C SCL, SPI SS,P1[7] AI, I2C SDA , SPI MISOP1[5] , AI, SPI CLK ,P1[3] QFN (Top View) 15 13 P0[2], AI P0[0], AI XRES P1[6], AI P1[4] , AI, EXTCLK P1[2 ], AI Page 9 of 43 [+] Feedback CY8C20X36A/46A/66A/96A 30-Ball Part Pinout Table 4. Pin Definitions – CY8C20766A, CY8C20746A 30-Ball Part Pinout (WLCSP) Pin No. A1 A2 A3 A4 A5 B1 B2 B3 B4 B5 C1 C2 C3 C4 C5 D1 D2 D3 D4 D5 E1 E2 E3 E4 E5 F1 F2 F3 F4 F5 IOH I/O I/O IOH IOH IOH I/O I/O I/O IOH IOH I/O I/O I/O I/O I/O I/O Input IOHR IOHR IOHR IOHR IOHR IOHR Power IOHR IOHR I I I I I I I I IOH IOH Power I I I I I I I I I I I I I I I I I Type Digital Analog I I P0[2] P0[6] VDD P0[1] P2[7] P2[6] P0[0] P0[4] P0[3] P2[5] P2[2] P2[4] P0[7] P0[5] P2[3] P2[0] P3[0] P3[1] P3[3] P2[1] XRES P1[6] P1[4] P1[7] P1[5] P1[2] P1[0] VSS B C F C D 5 Name Description Figure 5. CY8C20766A 30-Ball WLCSP Bottom View 4 3 2 1 A B Supply voltage Integrating Input Integrating Input Crystal Output (Xout) E Top View Crystal Input (Xin) A 1 2 3 4 5 Active high external reset with internal pull-down Optional external clock input (EXT CLK) I2C SCL, SPI SS I2C SDA, SPI MISO ISSP DATA[11], I2C SDA, SPI CLK[12] Supply ground ISSP CLK[11], I2C SCL, SPI MOSI SPI CLK D E F P1[1] P1[3] Notes 11. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 12. Alternate SPI clock. Document Number: 001-54459 Rev. *E Page 10 of 43 [+] Feedback CY8C20X36A/46A/66A/96A 32-Pin QFN Table 5. Pin Definitions – CY8C20436A, CY8C20446A, CY8C20466A PSoC Device [13] Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CP IOH IOH IOH Power Power I/O I/O I/O I/O I/O I/O IOH IOH IOH IOH Power I I I IOHR IOHR IOHR IOHR Input I I I I I I I I I I Type Digital IOH I/O I/O I/O I/O I/O I/O IOHR IOHR IOHR IOHR Power I I I I Analog I I I I I I I I I I I Name P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD P0[7] P0[5] P0[3] VSS VSS Description Integrating input Crystal output (XOut) Crystal input (XIn) Figure 6. CY8C20436A, CY8C20446A, CY8C20466A PSoC Device Vss P0 [3 ], AI P0 [5 ], AI P0 [7 ], AI Vd d P0 [6 ], AI 28 27 P0 [4 ], AI P0 [2 ], AI 26 25 32 31 I C SCL, SPI SS I2C SDA, SPI MISO SPI CLK. ISSP CLK[14], I2C SCL, SPI MOSI. Ground connection. ISSP DATA[14], I2C SDA, SPI CLK[15] Optional external clock input (EXTCLK) Active high external reset with internal pull-down 2 AI, P0[1] AI, P2[7] AI , XOut, P2[5] AI, XIn, P2[3] AI, P2[1] AI, P3[3] AI, P3[1] AI, I2 C SCL, SPI SS, P1[7] 30 29 9 10 11 12 13 14 A I,ISSP CLK , I2C SCL, SPI MOSI, P1[1] Vss [14] AI , ISSP DATA , I2C SDA, SPI CLK, P1[0] AI, P 1[2] AI, I2C SDA, SPI MISO, P 1[5] AI, SPI CLK, P 1[3] Supply voltage Integrating input Ground connection Center pad must be connected to ground LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output. Notes 13. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 14. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 15. Alternate SPI clock. Document Number: 001-54459 Rev. *E [14] AI, E XTCLK, P 1[4] AI, P 1[6] 15 16 1 2 3 4 5 6 7 8 QFN ( Top View ) 24 23 22 21 20 19 18 17 P0[0] , AI P2[6] , AI P2[4] , AI P2[2] , AI P2[0] , AI P3[2] , AI P3[0] , AI XRES Page 11 of 43 [+] Feedback CY8C20X36A/46A/66A/96A 32-Pin QFN (with USB) Table 6. Pin Definitions – CY8C20496A PSoC Device [16] Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 IOH IOH IOH Power I/O I/O I/O I/O I/O I/O IOH IOH IOH IOH Power I I I IOHR IOHR IOHR IOHR Input I I I I I I I I I I Type Digital IOH I/O I/O I/O IOHR IOHR IOHR IOHR Power I I Power I I I I Vss P0 [3], AI P0 [5], AI P0 [7], AI Vd d P0 [6], AI 28 27 I I I I I I I I P0[1] P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] VSS D+ DVDD P1[0] P1[2] P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD P0[7] P0[5] P0[3] VSS Integrating Input XTAL Out XTAL In I2C SCL, SPI SS I C SDA, SPI MISO SPI CLK ISSP CLK[17], I2C SCL, SPI MOSI Ground Pin USB D+ USB DPower pin ISSP DATA[17], I2C SDA, SPI CLKI[18] Optional external clock input (EXTCLK) Active high external reset with internal pull-down 2 AI , P 0[ 1] XTAL OUT, P 2 [ 5] XTAL IN , P 2[ 3] AI , P 2[ 1] I2C SCL, SPI SS , P 1[ 7] I2C SDA, SPI MISO , P 1[ 5] SPI CLK , P 1[3] [17] ISSP CLK, I2C SCL, SPI MOSI,P1[ 1 ] 32 31 30 29 26 25 P0 [4], AI P0 [2], AI Analog Name Description Figure 7. CY8C20496A PSoC Device 9 10 11 12 13 14 Vdd ISSPDATA, I2C SDA, SPI CLK, P1[0] , AI, P 1[2] Power Pin Integrating Input Ground Pin LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output. Notes 16. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 17. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 18. Alternate SPI clock. Document Number: 001-54459 Rev. *E [17, 18] AI, E XTCLK, P 1[4] AI, P 1[6] Vss USB PHY, D+ USB D- 15 16 1 2 3 4 5 6 7 8 QFN ( Top View ) 24 23 22 21 20 19 18 17 P0[0] , AI P2[6] , AI P2[4] , AI P2[2] , AI P2[0] , AI P3[2] , AI P3[0] , AI XRES Page 12 of 43 [+] Feedback CY8C20X36A/46A/66A/96A 48-Pin SSOP Table 7. Pin Definitions – CY8C20536A, CY8C20546A, and CY8C20566A PSoC Device[19] Description Pin No. Analog Digital Name Figure 8. CY8C20536A, CY8C20546A, and CY8C20566A PSoC Device AI, P0[7] AI, P0[5] AI, P0[3] AI P0[1] AI, P2[7] XTALOUT, P2[5] XTALIN, P2[3] AI , P2[1] NC NC AI, P4[3] AI, P4[1] NC AI, P3[7] AI, P3[5] AI, P3[3] AI, P3[1] NC NC I2 C SCL, SPI SS, P1[7] I2 C SDA, SPI MISO, P1[5 ] SPI CLK, P1[3] [19] ISSP CLK, I2 C SCL, SPI MOSI, P1[ ] 1 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 IOH IOH IOH IOH I/O I/O I/O I/O I I I I I I I I I/O I/O I/O I/O I/O I/O I I I I I I IOHR IOHR IOHR IOHR IOHR IOHR IOHR IOHR I I I I I I I I P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] NC NC P4[3] P4[1] NC P3[7] P3[5] P3[3] P3[1] NC NC P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] P1[6] NC NC NC NC Integrating Input Integrating Input XTAL Out XTAL In No connection No connection SSOP No connection 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDD P0[6] , AI P0[4] , AI P0[2] , AI P0[0] , AI P2[6] , AI P2[4] , AI P2[2] , AI P2[0] , AI P3[6] , AI P3[4] , AI P3[2] , AI P3[0] , AI XRES NC NC NC NC NC NC P1[6] , AI P1[4] , EXT CLK P1[2] , AI [19, 20] P1[0] , ISSP DATA, I2C SDA, SPI CLK No connection No connection I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK ISSP CLK[19], I2C SCL, SPI MOSI Ground Pin ISSP DATA[19], I2C SDA, SPI CLK[20] Optional external clock input (EXT CLK) No connection No connection No connection No connection Pin No. Analog Digital Name 33 34 35 No connection 41 I/O I P2[2] No connection 42 I/O I P2[4] Active high external reset with internal pull- 43 I/O I P2[6] down 36 I/O I P3[0] 44 IOH I P0[0] 37 I/O I P3[2] 45 IOH I P0[2] 38 I/O I P3[4] 46 IOH I P0[4] 39 I/O I P3[6] 47 IOH I P0[6] 40 I/O I P2[0] 48 Power VDD Power Pin LEGEND A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive, R = Regulated Output Option. NC NC XRES Notes 19. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 20. Alternate SPI clock. Document Number: 001-54459 Rev. *E Description Page 13 of 43 [+] Feedback CY8C20X36A/46A/66A/96A 48-Pin QFN Table 8. Pin Definitions – CY8C20636A PSoC Device [21, 22] Description Figure 9. CY8C20636A PSoC Device P0[1], AI Vss P0[3], AI P0[5], AI P0[7], AI NC NC 48 47 46 45 44 43 Vdd P0[6], AI P0[4], AI P0[2], AI P0[0], AI 36 35 34 33 32 31 30 29 28 27 26 25 P2[6] ,AI P2[4] AI , P2[2] , AI P2[0] AI , P4[2] ,AI P4[0] , AI P3[6] , AI P3[4] , AI P3[2] ,AI P3[0] , AI XRES P1[6] , AI Pin No. Analog Digital IOHR I IOHR I Power Power IOHR I IOHR IOHR I I Supply voltage ISSP DATA[21], I2C SDA, SPI CLK[23] Optional external clock input (EXTCLK) Active high external reset with internal pull-down 23 24 25 26 27 28 29 P1[2] P1[4] P1[6] XRES P3[0] P3[2] P3[4] IOHR I Input I/O I/O I/O I I I 30 31 32 33 34 35 36 37 38 39 I/O I/O I/O I/O I/O I/O I/O IOH IOH IOH I I I I I I I I I I P3[6] P4[0] P4[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] 40 41 42 43 44 45 46 47 48 CP IOH I Power IOH I IOH I IOH I Power IOH I Power P0[6] VDD NC NC P0[7] P0[5] P0[3] VSS P0[1] VSS Supply voltage No connection No connection Integrating input Ground connection Center pad must be connected to ground LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output. Notes 21. On power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives resistive low for 512 sleep clock cycles and both the pins transition to high impedance state. On reset, after XRES de-asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 22. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal 23. Alternate SPI clock. Document Number: 001-54459 Rev. *E Description Pin No. Analog Digital Name I2C SDA, SPI MISO, A I, P1[5] NC NC SPI CLK, AI, P1[3] [21] AI, ISSP CLK, I2C SCL, SPI MOSI, P1[1] Vss DNU DNU [21, 23] Vdd AI, ISSP DATA1 , I2C SDA, SPI CLK, P1[0] AI, P1[2] AI, EXTCLK, P1[4] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IOHR IOHR I I I I I I I I I I I I NC P2[7] P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] NC NC P1[3] P1[1] VSS DNU DNU VDD P1[0] Name No connection Crystal output (XOut) Crystal input (XIn) SCL, SPI SS I2C SDA, SPI MISO No connection No connection SPI CLK ISSP CLK[21], I2C SCL, SPI MOSI Ground connection I2C NC AI ,P2[7] AI , XOut,P2[5] AI , XIn ,P2[3] AI ,P2[1] AI ,P4[3] AI ,P4[1] AI ,P3[7] AI ,P3[5] AI ,P3[3] AI P3[1] AI ,I2 C SCL, SPI SS,P1[7] 1 2 3 4 5 6 7 8 9 10 11 12 QFN ( Top View ) 13 14 15 16 17 18 19 20 21 22 23 24 42 41 40 39 38 37 Page 14 of 43 [+] Feedback CY8C20X36A/46A/66A/96A 48-Pin QFN with USB Description Table 9. Pin Definitions – CY8C20646A, CY8C20666A PSoC Device [24, 25] Figure 10. CY8C20646A, CY8C20666A PSoC Device Pin No. Analog Digital Name P0[1], AI Vss P0[3], AI P0[5 ], AI P0[7], AI NC NC Vdd P0[6], AI P0[4], AI P0[2], AI P0[0], AI 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IOHR IOHR I I I I I I I I I I I I IOHR IOHR Power I/O I/O Power IOHR IOHR IOHR IOHR Input I/O I/O I/O I I I I I I NC P2[7] P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] NC NC P1[3] P1[1] VSS D+ DVDD P1[0] P1[2] P1[4] P1[6] XRES P3[0] P3[2] P3[4] 48 47 46 45 44 43 No connection Crystal output (XOut) Crystal input (XIn) NC AI , P2[7] AI, XOut, P2[5] AI, XIn , P2[3] AI , P2[1] AI , P4[3] AI , P4[1] AI , P3[7] AI , P3[5] AI , P3[3] AI , P3[1] AI, I2 C SCL, SPI SS, P1[7] 1 2 3 4 5 6 QFN ( Top View ) Optional external clock input (EXTCLK) Active high external reset with internal pull-down 30 I/O I P3[6] 40 IOH I P0[6] 31 I/O I P4[0] 41 Power VDD Supply voltage 32 I/O I P4[2] 42 NC No connection 33 I/O I P2[0] 43 NC No connection 34 I/O I P2[2] 44 IOH I P0[7] 35 I/O I P2[4] 45 IOH I P0[5] 36 I/O I P2[6] 46 IOH I P0[3] Integrating input 37 IOH I P0[0] 47 Power VSS Ground connection 38 IOH I P0[2] 48 IOH I P0[1] 39 IOH I P0[4] CP Power VSS Center pad must be connected to ground LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output. Notes 24. On Power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives resistive low for 512 sleep clock cycles and both the pins transition to High impedance state . On reset, after XRES de- asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. In both cases, a pull-up resistance on these lines combines with the pull-down resistance (5.6K ohm) and form a potential divider. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 25. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 26. Alternate SPI clock. Document Number: 001-54459 Rev. *E Description I I I Pin No. Analog Digital Name I2C SDA, SPI MISO, A I, P1[5] NC NC SPI CLK, A I, P1[3] [24] AI,ISSP CLK , I2C SCL, SPI MOSI, P1[1] Vss D+ DVdd [24, 26] AI ,ISSP DATA, I2C SDA, SPI CLK, P1[0] AI, P 1[2] AI, EXTCLK, P1[4] I2C SCL, SPI SS I2C SDA, SPI MISO No connection No connection SPI CLK ISSP CLK[24], I2C SCL, SPI MOSI Ground connection USB D+ USB DSupply voltage ISSP DATA[24], I2C SDA, SPI CLK[26] 13 14 15 16 17 18 19 20 21 22 23 24 7 8 9 10 11 12 36 35 34 33 32 31 30 29 28 27 26 25 P2[6] , AI P2[4] ,AI P2[2] ,AI P2[0] ,AI P4[2] ,AI P4[0] ,AI P3[6] ,AI P3[4] , AI P3[2] ,AI P3[0] , AI XRES P1[6] , AI Page 15 of 43 [+] Feedback CY8C20X36A/46A/66A/96A 48-Pin QFN OCD The 48-pin QFN part is for the CY8C20066A On-Chip Debug (OCD) PSoC device. Note that this part is only used for in-circuit debugging. Table 10. Pin Definitions – CY8C20066A PSoC Device [27, 28] Description Figure 11. CY8C20066A PSoC Device P0[1], AI OCDO Vdd P0[6], AI P0[4], AI P0[2], AI P0[0], AI 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P2[6] , AI P2[4] , AI P2[2] , AI P2[0] , AI P4[2] , AI P4[0] , AI P3[6] , AI P3[4] , AI P3[2] , AI P3[0] , AI XRES P1[6] , AI Vss P0[3], AI P0[5 ], AI P0[7], AI OCDE Pin No. Analog Digital Name IOHR I IOHR I Power I/O I/O Power IOHR I IOHR I I2C SCL, SPI SS I2C SDA, SPI MISO OCD CPU clock output OCD high speed clock output SPI CLK. ISSP CLK[29], I2C SCL, SPI MOSI Ground connection USB D+ USB DSupply voltage ISSP DATA[29], I2C SDA, SPI CLK[30] Pin No. Analog Digital Name 24 25 26 27 28 29 30 31 32 33 34 35 36 IOHR I P1[4] P1[6] XRES P3[0] P3[2] P3[4] P3[6] P4[0] P4[2] P2[0] P2[2] P2[4] P2[6] Optional external clock input (EXTCLK) Active high external reset with internal pull-down 37 38 39 40 41 42 43 44 45 46 47 48 CP IOH IOH IOH I I I P0[0] P0[2] P0[4] P0[6] VDD OCDO OCDE P0[7] P0[5] P0[3] VSS P0[1] VSS IOHR I Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I IOH I Power Supply voltage OCD even data I/O OCD odd data output IOH IOH IOH Power IOH Power I I I I Integrating input Ground connection Center pad must be connected to ground LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output. Notes 27. This part is available in limited quantities for In-Circuit Debugging during prototype development. It is not available in production volumes. 28. The center pad (CP) on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 29. On Power-up , the SDA(P1[0]) drives a strong high for 256 sleep clock cycles and drives resistive low for the next 256 sleep clock cycles. The SCL(P1[1])line drives resistive low for 512 sleep clock cycles and both the pins transition to High impedance state . On reset, after XRES de- asserts, the SDA and the SCL lines drive resistive low for 8 sleep clock cycles and transition to high impedance state. In both cases, a pull-up resistance on these lines combines with the pull-down resistance (5.6K ohm) and form a potential divider. Hence, during power-up or reset event, P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter issues. 30. Alternate SPI clock. Document Number: 001-54459 Rev. *E Description 23 P1[2] I2C SDA, SPI MISO, AI, P1[5] CCLK HCLK SPI CLK, A I, P1[3] [29] AI,ISSP CLK6, I2C SCL, SPI MOSI, P1[1] Vss D+ D[29, 30] Vdd AI,ISSP DATA1, I2C SDA, SPI CLK, P1[0] AI, P 1[2] AI, EXTCLK, P1[4] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IOHR IOHR I I I I I I I I I I I I OCDOE P2[7] P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] CCLK HCLK P1[3] P1[1] VSS D+ DVDD P1[0] OCD mode direction pin Crystal output (XOut) Crystal input (XIn) 13 14 15 16 17 18 19 20 21 22 23 24 OCDO AE , P2[7] I AI, XOut, P2[5] AI, XIn , P2[3] AI , P2[1] AI , P4[3] AI , P4[1] AI , P3[7] AI, P3[5] AI, P3[3] AI, P3[1] AI, I2 C SCL, SPI SS, P1[7] 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 QFN ( Top View ) Page 16 of 43 [+] Feedback CY8C20X36A/46A/66A/96A Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C20x36A/46A/66A/96A PSoC devices. For the latest electrical specifications, confirm that you have the most recent datasheet by visiting the web at http://www.cypress.com/psoc. Figure 12. Voltage versus CPU Frequency 5.5V li d ng Va rati n e io Op Reg Vdd Voltage 1.71V 750 kHz 3 MHz CPU Frequency 24 MHz Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 11. Absolute Maximum Ratings Symbol TSTG Description Storage temperature Conditions Higher storage temperatures reduce data retention time. Recommended Storage Temperature is +25 °C ± 25 °C. Extended duration storage temperatures above 85 °C degrades reliability. – – – – Human body model ESD In accordance with JESD78 standard Min –55 Typ +25 Max +125 Units °C VDD VIO VIOZ IMIO ESD LU Supply voltage relative to VSS DC input voltage DC voltage applied to tristate Maximum current into any port pin Electro static discharge voltage Latch-up current –0.5 VSS – 0.5 VSS – 0.5 –25 2000 – – – – – – – +6.0 VDD + 0.5 VDD + 0.5 +50 – 200 V V V mA V mA Operating Temperature Table 12. Operating Temperature Symbol TA TC TJ Description Ambient temperature Commercial temperature range Operational die temperature – – The temperature rise from ambient to junction is package specific. Refer the table Thermal Impedances per Package on page 34. The user must limit the power consumption to comply with this requirement. Conditions Min –40 0 Typ – Max +85 70 Units °C °C –40 – +100 °C Document Number: 001-54459 Rev. *E Page 17 of 43 [+] Feedback CY8C20X36A/46A/66A/96A DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 13. DC Chip-Level Specifications Symbol VDD [31, 32, 33, 34] Description Supply voltage Conditions Refer the table DC POR and LVD Specifications on page 23 Min 1.71 – Typ – 3.32 Max 5.50 4.00 Units V mA IDD24 Supply current, IMO = 24 MHz Conditions are VDD ≤ 3.0 V, TA = 25 °C, CPU = 24 MHz. CapSense running at 12 MHz, no I/O sourcing current Supply current, IMO = 12 MHz Conditions are VDD ≤ 3.0 V, TA = 25 °C, CPU = 12 MHz. CapSense running at 12 MHz, no I/O sourcing current Supply current, IMO = 6 MHz Conditions are VDD ≤ 3.0 V, TA = 25 °C, CPU = 6 MHz. CapSense running at 6 MHz, no I/O sourcing current VDD ≤ 3.0 V, TA = 25 °C, I/O regulator turned off IDD12 – 1.86 2.60 mA IDD6 – 1.13 1.80 mA ISB0 ISB1 Deep sleep current – – 0.10 1.07 0.50 1.50 μA μA Standby current with POR, LVD VDD ≤ 3.0 V, TA = 25 °C, I/O regulator turned off and sleep timer Notes 31. When VDD remains in the range from 1.71 V to 1.9 V for more than 50 µsec, the slew rate when moving from the 1.71 V to 1.9 V range to greater than 2 V must be slower than 1 V/500 usec to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SRPOWER_UP parameter. 32. If powering down in standby sleep mode, to properly detect and recover from a VDD brown out condition any of the following actions must be taken: a. Bring the device out of sleep before powering down. b. Assure that VDD falls below 100 mV before powering back up. c. Set the No Buzz bit in the OSC_CR0 register to keep the voltage monitoring circuit powered during sleep. d. Increase the buzz rate to assure that the falling edge of VDD is captured. The rate is configured through the PSSDC bits in the SLP_CFG register. For the referenced registers, refer to the CY8C20x36 Technical Reference Manual. In deep sleep mode, additional low power voltage monitoring circuitry allows VDD brown out conditions to be detected for edge rates slower than 1V/ms. 33. AFor USB mode, the VDD supply for bus-powered application should be limited to 4.35V-5.35V. For self-powered application, VDD should be 3.15 V-3.45 V. 34. For proper CapSense block functionality, if the drop in VDD exceeds 5% of the base VDD , the rate at which VDD drops should not exceed 200 mV/s. Base VDD can be between 1.8 V and 5.5 V Document Number: 001-54459 Rev. *E Page 18 of 43 [+] Feedback CY8C20X36A/46A/66A/96A DC GPIO Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and –40 °C ≤ TA ≤ 85 °C, 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, or 1.71 V to 2.4 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5V and 3.3 V at 25 C and are for design guidance only. Table 14. 3.0-V to 5.5-V DC GPIO Specifications Symbol RPU VOH1 VOH2 VOH3 Description Pull-up resistor High output voltage Port 2 or 3 pins High output voltage Port 2 or 3 Pins High output voltage Port 0 or 1 pins with LDO regulator Disabled for port 1 High output voltage Port 0 or 1 pins with LDO regulator Disabled for port 1 High output voltage Port 1 Pins with LDO Regulator Enabled for 3 V out – IOH < 10 μA, maximum of 10 mA source current in all I/Os IOH = 1 mA, maximum of 20 mA source current in all I/Os IOH < 10 μA, maximum of 10 mA source current in all I/Os IOH = 5 mA, maximum of 20 mA source current in all I/Os IOH < 10 μA, VDD > 3.1 V, maximum of 4 I/Os all sourcing 5 mA Conditions Min 4 VDD – 0.20 VDD – 0.90 VDD – 0.20 Typ 5.60 – – – Max 8 – – – Units kΩ V V V VOH4 VDD – 0.90 – – V VOH5 2.85 3.00 3.30 V VOH6 High output voltage IOH = 5 mA, VDD > 3.1V, maximum of Port 1 pins with LDO regulator enabled 20 mA source current in all I/Os for 3 V out High output voltage IOH < 10 μA, VDD > 2.7 V, maximum of Port 1 pins with LDO enabled for 2.5 V 20 mA source current in all I/Os out IOH = 2 mA, VDD > 2.7 V, maximum of High output voltage Port 1 pins with LDO enabled for 2.5 V 20 mA source current in all I/Os out High output voltage IOH < 10 μA, VDD > 2.7 V, maximum of Port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os out High output voltage IOH = 1 mA, VDD > 2.7 V, maximum of Port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os out Low output voltage IOL = 25 mA, VDD > 3.3 V, maximum of 60 mA sink current on even port pins (for example, P0[2] and P1[4]) and 60 mA sink current on odd port pins (for example, P0[3] and P1[5]) – – – – Package and pin dependent Temp = 25 °C 2.20 – – V VOH7 2.35 2.50 2.75 V VOH8 1.90 – – V VOH9 1.60 1.80 2.10 V VOH10 1.20 – – V VOL – – 0.75 V VIL VIH VH IIL CPIN Input low voltage Input high voltage Input hysteresis voltage Input leakage (Absolute Value) Pin capacitance – 2.00 – – 0.50 – – 80 0.001 1.70 0.80 – – 1 7 V V mV μA pF Document Number: 001-54459 Rev. *E Page 19 of 43 [+] Feedback CY8C20X36A/46A/66A/96A Table 15. 2.4V to 3.0V DC GPIO Specifications Symbol RPU VOH1 VOH2 VOH3 Description Pull-up resistor High output voltage Port 2 or 3 pins High output voltage Port 2 or 3 Pins High output voltage Port 0 or 1 pins with LDO regulator Disabled for port 1 High output voltage Port 0 or 1 pins with LDO regulator Disabled for Port 1 – IOH < 10 μA, maximum of 10 mA source current in all I/Os IOH = 0.2 mA, maximum of 10 mA source current in all I/Os IOH < 10 μA, maximum of 10 mA source current in all I/Os Conditions Min 4 VDD - 0.20 VDD - 0.40 VDD - 0.20 Typ 5.60 – – – Max 8 – – – Units kΩ V V V VOH4 IOH = 2 mA, maximum of 10 mA source VDD - 0.50 current in all I/Os 1.50 – – V VOH5A High output voltage IOH < 10 μA, VDD > 2.4 V, maximum of Port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os out High output voltage IOH = 1 mA, VDD > 2.4 V, maximum of Port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os out Low output voltage IOL = 10 mA, maximum of 30 mA sink current on even port pins (for example, P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5]) – – – – Package and pin dependent Temp = 25 °C 1.80 2.10 V VOH6A 1.20 – – V VOL – – 0.75 V VIL VIH VH IIL CPIN Input low voltage Input high voltage Input hysteresis voltage Input leakage (absolute value) Capacitive load on pins – 1.40 – – 0.50 – – 80 1 1.70 0.72 – 1000 7 V V mV nA pF Table 16. 1.71-V to 2.4-V DC GPIO Specifications Symbol RPU VOH1 VOH2 VOH3 Description Pull-up resistor High output voltage Port 2 or 3 pins High output voltage Port 2 or 3 pins High output voltage Port 0 or 1 pins with LDO regulator Disabled for Port 1 High output voltage Port 0 or 1 Pins with LDO Regulator Disabled for Port 1 Low output voltage – IOH = 10 μA, maximum of 10 mA source current in all I/Os IOH = 0.5 mA, maximum of 10 mA source current in all I/Os IOH = 100 μA, maximum of 10 mA source current in all I/Os Conditions Min 4 VDD – 0.20 VDD – 0.50 VDD – 0.20 Typ 5.60 – – – Max 8 – – – Units kΩ V V V VOH4 IOH = 2 mA, maximum of 10 mA source VDD – 0.50 current in all I/Os IOL = 5 mA, maximum of 20 mA sink current on even port pins (for example, P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5]) – – – – – V VOL – 0.40 V VIL VIH Input low voltage Input high voltage – 0.65 × VDD – – 0.30 × VDD – V V Document Number: 001-54459 Rev. *E Page 20 of 43 [+] Feedback CY8C20X36A/46A/66A/96A Table 16. 1.71-V to 2.4-V DC GPIO Specifications (continued) Symbol VH IIL CPIN Description Input hysteresis voltage Input leakage (absolute value) Capacitive load on pins – – Package and pin dependent temp = 25 oC Conditions Min – – 0.50 Typ 80 1 1.70 Max – 1000 7 Units mV nA pF Table 17. DC Characteristics – USB Interface Symbol RUSBI RUSBA VOHUSB VOLUSB VDI VCM VSE CIN IIO RPS2 REXT Description USB D+ pull-up resistance USB D+ pull-up resistance Static output high Static output low Differential input sensitivity Single ended receiver threshold Transceiver capacitance High Z state data line leakage PS/2 pull-up resistance External USB series resistor With idle bus While receiving traffic – – – – – On D+ or D- line – In series with each USB pin Conditions Min 900 1425 2.8 – 0.2 0.8 0.8 – –10 3000 21.78 Typ – – – – – – – – – 5000 22.0 2.5 2.0 50 +10 7000 22.22 Max 1575 3090 3.6 0.3 Units Ω Ω V V V V V pF μA Ω Ω Differential input common mode range – DC Analog Mux Bus Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 18. DC Analog Mux Bus Specifications Symbol RSW RGND Description Switch resistance to common analog bus Resistance of initialization switch to VSS – – Conditions Min – – Typ – – Max 800 800 Units Ω Ω The maximum pin voltage for measuring RSW and RGND is 1.8 V DC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 19. DC Comparator Specifications Symbol VLPC ILPC VOSLPC Description Conditions Min 0.0 – – Typ – 10 2.5 Max 1.8 40 30 Units V μA mV Low power comparator (LPC) common Maximum voltage limited to VDD mode LPC supply current LPC voltage offset – – Document Number: 001-54459 Rev. *E Page 21 of 43 [+] Feedback CY8C20X36A/46A/66A/96A Comparator User Module Electrical Specifications The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the entire device voltage and temperature operating range: –40°C