CY8C20334-12LQXIT

CY8C20234, CY8C20334 CY8C20434, CY8C20534 PSoC® Programmable System-0n-Chip™ Features ■ Low Power CapSense™ Block ❐ Configurable Capacitive Sensing Elements ❐ Supports Combination of CapSense Buttons, Sliders, Touchpads, and Proximity Sensors Powerful Harvard Architecture Processor ❐ M8C Processor Speeds Running up to 12 MHz ❐ Low Power at High Speed ❐ 2.4V to 5.25V Operating Voltage ❐ Industrial Temperature Range: -40°C to +85°C Flexible On-Chip Memory ❐ 8K Flash Program Storage 50,000 Erase/Write Cycles ❐ 512 Bytes SRAM Data Storage ❐ Partial Flash Updates ❐ Flexible Protection Modes ❐ Interrupt Controller ❐ In-System Serial Programming (ISSP) Complete Development Tools ❐ Free Development Tool (PSoC Designer™) ❐ Full Featured, In-Circuit Emulator, and Programmer ❐ Full Speed Emulation ❐ Complex Breakpoint Structure ❐ 128K Trace Memory Precision, Programmable Clocking ❐ Internal ±5.0% 6/12 MHz Main Oscillator ❐ Internal Low Speed Oscillator at 32 kHz for Watchdog and Sleep Programmable Pin Configurations ❐ Pull Up, High Z, Open Drain, and CMOS Drive Modes on All GPIO ❐ Up to 28 Analog Inputs on GPIO ❐ Configurable Inputs on All GPIO ❐ Selectable, Regulated Digital I/O on Port 1 • 3.0V, 20 mA Total Port 1 Source Current • 5 mA Strong Drive Mode on Port 1 Versatile Analog Mux ❐ Common Internal Analog Bus ❐ Simultaneous Connection of I/O Combinations ❐ Comparator Noise Immunity ❐ Low Dropout Voltage Regulator for the Analog Array ■ ■ Additional System Resources ❐ Configurable Communication Speeds • I2C: Selectable to 50 kHz, 100 kHz, or 400 kHz • SPI: Configurable between 46.9 kHz and 3 MHz 2 ❐ I C Slave ❐ SPI Master and SPI Slave ❐ Watchdog and Sleep Timers ❐ Internal Voltage Reference ❐ Integrated Supervisory Circuit ■ Logic Block Diagram Port 3 Port 2 Port 1 Port 0 Config LDO PSoC CORE System Bus ■ Global Analog Interconnect SRAM 512 Bytes Interrupt Controller SROM Flash 8K Sleep and Watchdog CPU Core (M8C) 6/12 MHz Internal Main Oscillator ■ ■ ANALOG SYSTEM CapSense Block Analog Ref. I2C Slave/SPI Master-Slave POR and LVD System Resets Analog Mux SYSTEM RESOURCES Cypress Semiconductor Corporation Document Number: 001-05356 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 16, 2009 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 PSoC® Functional Overview The PSoCfamily consists of many Programmable System-on-Chips with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU based system components with one low cost single chip programmable component. A PSoC device includes configurable analog and digital blocks and programmable interconnect. This architecture enables the user to create customized peripheral configurations to match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. The PSoC architecture for this device family, as shown in Figure 1, consists of three main areas: the Core, the System Resources, and the CapSense Analog System. A common versatile bus enables connection between I/O and the analog system. Each CY8C20x34 PSoC device includes a dedicated CapSense block that provides sensing and scanning control circuitry for capacitive sensing applications. Depending on the PSoC package, up to 28 general purpose IO (GPIO) are also included. The GPIO provide access to the MCU and analog mux. Figure 1. Analog System Block Diagram ID AC Analog Global Bus Vr R eferenc e Buffer C internal C om parator Mux Mux R efs PSoC Core The PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, IMO (Internal Main Oscillator), and ILO (Internal Low speed Oscillator). The CPU core, called the M8C, is a powerful processor with speeds up to 12 MHz. The M8C is a two MIPS, 8-bit Harvard architecture microprocessor. System Resources provide additional capability such as a configurable I2C slave or SPI master-slave communication interface and various system resets supported by the M8C. The Analog System consists of the CapSense PSoC block and an internal 1.8V analog reference. Together they support capacitive sensing of up to 28 inputs. C ap Sens e C ounters C SC LK IMO C apSens e C lock Selec t R elaxation O s c illator (RO) Analog Multiplexer System The Analog Mux Bus connects to every GPIO pin. Pins are connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with the CapSense block comparator. Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include: ■ ■ ■ CapSense Analog System The Analog System contains the capacitive sensing hardware. Several hardware algorithms are supported. This hardware performs capacitive sensing and scanning without requiring external components. Capacitive sensing is configurable on each GPIO pin. Scanning of enabled CapSense pins is completed quickly and easily across multiple ports. Complex capacitive sensing interfaces such as sliders and touch pads Chip-wide mux that enables analog input from any I/O pin Crosspoint connection between any I/O pin combinations When designing capacitive sensing applications, refer to the latest signal-to-noise signal level requirements Application Notes, found under http://www.cypress.com >> DESIGN RESOURCES >> Application Notes. In general, unless otherwise noted in the relevant Application Notes, the minimum signal-to-noise ratio (SNR) requirement for CapSense applications is 5:1. Document Number: 001-05356 Rev. *H Page 2 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 Additional System Resources System Resources provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. Brief statements describing the merits of each system resource are presented below. ■ Application Notes Application notes are an excellent introduction to the wide variety of possible PSoC designs. They are located here: www.cypress.com/psoc. Select Application Notes under the Documentation tab. The I2C slave or SPI master-slave module provides 50/100/400 kHz communication over two wires. SPI communication over three or four wires run at speeds of 46.9 kHz to 3 MHz (lower for a slower system clock). Low Voltage Detection (LVD) interrupts signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.8V reference provides an absolute reference for capacitive sensing. The 5V maximum input, 3V fixed output, low dropout regulator (LDO) provides regulation for I/Os. A register controlled bypass mode enables the user to disable the LDO. Development Kits PSoC Development Kits are available online from Cypress at www.cypress.com/shop and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. ■ Training Free PSoC technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training. The training covers a wide variety of topics and skill levels to assist you in your designs. ■ ■ Cypros Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to www.cypress.com/cypros. Getting Started The quickest way to understand PSoC silicon is to read this data sheet and then use the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in depth information, along with detailed programming information, see the PSoC® Programmable System-on-Chip Technical Reference Manual for CY8C28xxx PSoC devices. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device data sheets on the web at www.cypress.com/psoc. Solutions Library Visit our growing library of solution focused designs at www.cypress.com/solutions. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Technical Support For assistance with technical issues, search KnowledgeBase articles and forums at www.cypress.com/support. If you cannot find an answer to your question, call technical support at 1-800-541-4736. Document Number: 001-05356 Rev. *H Page 3 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 Development Tools PSoC Designer is a Microsoft® Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE runs on Windows XP or Windows Vista. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built-in support for third-party assemblers and C compilers. PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family. Code Generation Tools PSoC Designer supports multiple third party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours. Assemblers. The assemblers allow assembly code to merge seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write I/O registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. PSoC Designer Software Subsystems System-Level View A drag-and-drop visual embedded system design environment based on PSoC Express. In the system level view you create a model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state based upon any or all other system devices. Based upon the design, PSoC Designer automatically selects one or more PSoC Mixed-Signal Controllers that match your system requirements. PSoC Designer generates all embedded code, then compiles and links it into a programming file for a specific PSoC device. Chip-Level View The chip-level view is a more traditional integrated development environment (IDE) based on PSoC Designer 4.4. Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time. Hybrid Designs You can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. All views of the project share a common code editor, builder, and common debug, emulation, and programming tools. In-Circuit Emulator A low cost, high functionality In-Circuit Emulator (ICE) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. Document Number: 001-05356 Rev. *H Page 4 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process can be summarized in the following four steps: 1. Select components 2. Configure components 3. Organize and Connect 4. Generate, Verify, and Debug Organize and Connect You can build signal chains at the chip level by interconnecting user modules to each other and the I/O pins, or connect system level inputs, outputs, and communication interfaces to each other with valuator functions. In the system-level view, selecting a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects, places, routes, and configures a programmable gain amplifier (PGA) to buffer the input from the potentiometer, an analog to digital converter (ADC) to convert the potentiometer’s output to a digital signal, and a PWM to control the fan. In the chip-level view, perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources. Select Components Both the system-level and chip-level views provide a library of prebuilt, pretested hardware peripheral components. In the system-level view, these components are called “drivers” and correspond to inputs (a thermistor, for example), outputs (a brushless DC fan, for example), communication interfaces (I2C-bus, for example), and the logic to control how they interact with one another (called valuators). In the chip-level view, the components are called “user modules”. User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, perform the “Generate Application” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. Both system-level and chip-level designs generate software based on your design. The chip-level design provides application programming interfaces (APIs) with high level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed. The system-level design also generates a C main() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code. A complete code development environment allows you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the ICE where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. Configure Components Each of the components you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a Pulse Width Modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. Both the system-level drivers and chip-level user modules are documented in data sheets that are viewed directly in PSoC Designer. These data sheets explain the internal operation of the component and provide performance specifications. Each data sheet describes the use of each user module parameter or driver property, and other information you may need to successfully implement your design. Document Number: 001-05356 Rev. *H Page 5 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 Document Conventions Table 1 lists the acronyms that are used in this document. Table 1. Acronyms Used Acronym AC API CPU DC GPIO GUI ICE ILO IMO I/O LSb LVD MSb POR PPOR PSoC® SLIMO SRAM Description Alternating Current Application Programming Interface Central Processing Unit Direct Current General Purpose IO Graphical User Interface In-Circuit Emulator Internal Low Speed Oscillator Internal Main Oscillator Input Or Output Least Significant Bit Low Voltage Detect Most Significant Bit Power On Reset Precision Power On Reset Programmable System-on-Chip™ Slow IMO Static Random Access Memory Units of Measure A units of measure table is located in the Electrical Specifications section. Table 7 on page 14 lists all the abbreviations used to measure the PSoC devices. Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers are also represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b or 01000011b). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimals. Document Number: 001-05356 Rev. *H Page 6 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 Pin Information This section describes, lists, and illustrates the CY8C20234, CY8C20334, CY8C20434, and CY8C20534 PSoC device pins and pinout configurations. The CY8C20x34 PSoC device is available in a variety of packages that are listed and shown in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. However, Vss, Vdd, and XRES are not capable of Digital I/O. 16-Pin Part Pinout Figure 2. CY8C20234 16-Pin PSoC Device P0[1], AI AI, P2[5] AI, P2[1] AI, I2C SCL, SPI SS, P1[7] AI, I2C SDA, SPI MISO, P1[5] 1 2 3 4 P0[3], AI P0[7], AI Vdd 14 13 8 12 9 P0[4], AI XRES P1[4], AI, EXTCLK P1[2], AI CLK, I2C SCL, SPI MOSI P1[1] Vss AI, DATA, I2C SDA, P1[0] Table 2. Pin Definitions - CY8C20234 16-Pin (QFN) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type Digital I/O I/O IOH IOH IOH IOH Power IOH IOH IOH Input I/O Power I/O I/O I/O I I I I I I I I I I I I I Analog Name P2[5] P2[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] XRES P0[4] Vdd P0[7] P0[3] P0[1] Integrating Input Supply Voltage Optional External Clock Input (EXTCLK) Active High External Reset with Internal Pull Down I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK CLK[1], I2C SCL, SPI MOSI Ground Connection DATA[1], I2C SDA Description A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive Note 1. These are the ISSP pins, that are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for details. Document Number: 001-05356 Rev. *H AI, SPI CLK, P1[3] 5 6 7 16 15 QFN 11 (Top View)10 Page 7 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 24-Pin Part Pinout Figure 3. CY8C20334 24-Pin PSoC Device P0[1], AI AI, P2[5] AI, P2[3] AI, P2[1] AI, I2C SCL, SPI SS, P1[7] AI, I2C SDA, SPI MISO, P1[5] AI, SPI CLK, P1[3] P0[3], AI P0[5], AI P0[7], AI Vdd P0[6], AI 18 17 16 15 14 13 P0[4], AI P0[2], AI P0[0], AI P2[0], AI XRES P1[6], AI Table 3. Pin Definitions - CY8C20334 24-Pin (QFN) [2] Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CP Type Digital I/O I/O I/O IOH IOH IOH IOH Power IOH IOH IOH IOH Input I/O I/O I/O I/O I/O Power I/O I/O I/O I/O Power Analog I I I I I I I Name P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] NC Vss P1[0] P1[2] P1[4] P1[6] XRES P2[0] P0[0] P0[2] P0[4] P0[6] Vdd P0[7] P0[5] P0[3] P0[1] Vss Description I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK CLK[1], I2C SCL, SPI MOSI No Connection Ground Connection DATA[1], I2C SDA Optional External Clock Input (EXTCLK) Active High External Reset with Internal Pull Down I I I I I I I I I I I I I Analog Bypass Supply Voltage Integrating Input Center Pad is connected to Ground A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive Note 2. The center pad on the QFN package is connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it is electrically floated and not connected to any other signal. Document Number: 001-05356 Rev. *H AI, CLK*, I2C SCL SPI MOSI, P1[1] NC Vss AI, DATA*, I2C SDA, P1[0] AI, P1[2] AI, EXTCLK, P1[4] 7 8 9 10 11 12 1 2 QFN 3 4 (Top View) 5 6 24 23 22 21 20 19 Page 8 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 28-Pin Part Pinout Figure 4. CY8C20534 28-Pin PSoC Device AI P0[7] AI P0[5] AI P0[3] AI P0[1] AI P2[7] AI P2[5] AI P2[3] AI P2[1] Vss AI, I2C SCL P1[7] AI, I2C SDA P1[5] AI P1[3] AI, I2C SCL P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd P0[6] AI P0[4] AI P0[2] AI P0[0] AI P2[6] AI P2[4] AI P2[2] AI P2[0] AI XRES P1[6] AI P1[4] EXTCLK, AI P1[2] AI P1[0] I2C SDA, AI Table 4. Pin Definitions - CY8C20534 28-Pin (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Type Digital I/O I/O I/O I/O I/O I/O I/O I/O Power I/O I/O I/O I/O Power I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O Power I I I I I I I I I I I I I I I I I I I I I I I I Analog Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] Vss P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Analog Column Mux Input Analog Column Mux Input Analog Column Mux Input Analog Column Mux Input Supply Voltage I2C Serial Clock (SCL), ISSP-SCLK[1] Ground Connection Direct Switched Capacitor Block Input Direct Switched Capacitor Block Input Ground Connection I2C Serial Clock (SCL) I2C Serial Data (SDA) Analog Column Mux Input Description Analog Column Mux Input and Column Output Analog Column Mux Input and Column Output, Integrating Input Analog Column Mux Input, Integrating Input I2C Serial Data (SDA), ISSP-SDATA[1] Optional External Clock Input (EXTCLK) Active High External Reset with Internal Pull Down Direct Switched Capacitor Block Input Direct Switched Capacitor Block Input A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive. Document Number: 001-05356 Rev. *H Page 9 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 32-Pin Part Pinout Figure 5. CY8C20434 32-Pin PSoC Device Vss P0[3], AI P0[5], AI P0[7], AI Vdd P0[6], AI P0[4], AI P0[2], AI AI, P0[1] AI, P2[7] AI, P2[5] AI, P2[3] AI, P2[1] AI, P3[3] AI, P3[1] SPI SS, P1[7] AI, I2C SCL 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 QFN (Top View) Table 5. Pin Definitions - CY8C20434 32-Pin (QFN) [2] Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 Type Digital Analog I/O I I/O I I/O I I/O I I/O I I/O I I/O I IOH I IOH IOH IOH Power IOH IOH IOH IOH Input I/O I/O I/O I/O I/O I I I I I I I I I I I I Name P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2] P2[4] Description I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK CLK[1], I2C SCL, SPI MOSI Ground Connection DATA[1], I2C SDA Optional External Clock Input (EXTCLK) Active High External Reset With Internal Pull Down Document Number: 001-05356 Rev. *H AI, I2C SDA, SPI MISO, P1[5] AI, SPI CLK, P1[3] AI, CLK*, I2C SCL, SPI MOSI, P1[1] Vss AI, DATA*, I2C SDA, P1[0] AI, P1[2] AI, EXTCLK, P1[4] AI, P1[6] 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 P0[0], AI P2[6], AI P2[4], AI P2[2], AI P2[0], AI P3[2], AI P3[0], AI XRES Page 10 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 Table 5. Pin Definitions - CY8C20434 32-Pin (QFN) [2] (continued) Pin No. 23 24 25 26 27 28 29 30 31 32 CP Digital I/O I/O I/O I/O I/O Power I/O I/O I/O Power Power Type Analog I I I I I I I I Name P2[6] P0[0] P0[2] P0[4] P0[6] Vdd P0[7] P0[5] P0[3] Vss Vss Description Analog Bypass Supply Voltage Integrating Input Ground Connection Center Pad Is Connected to Ground A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive. Document Number: 001-05356 Rev. *H Page 11 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 48-Pin OCD Part Pinout The 48-Pin QFN part table and pin diagram is for the CY8C20000 On-Chip Debug (OCD) PSoC device. This part is only used for in-circuit debugging. It is NOT available for production. Figure 6. CY8C20000 48-Pin OCD PSoC Device NC Vss P0[3], AI P0[5], AI P0[7], AI P0[6], AI NC 39 OCDO Vdd OCDE NC 38 48 47 46 45 44 43 42 41 40 37 NC 36 35 34 33 32 31 30 29 28 27 26 25 P0[4], AI P0[2], AI P0[0], AI P2[6], AI P2[4], AI P2[2], AI P2[0], AI P3[2], AI P3[0], AI XRES P1[6], AI P1[4], EXTCLK, AI 13 14 15 16 17 18 19 20 21 AI, DATA*, I2C SDA, P1[0] AI, P1[2] AI, CLK*, I2C SCL, SPI MOSI, P1[1] Vss AI, SPI CLK, P1[3] NC NC NC CCLK Table 6. Pin Definitions - CY8C20000 48-Pin OCD (QFN) [2] Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 IOH IOH Power I I I/O I/O I/O I/O I/O I/O I/O IOH IOH I/O I I I I I I I I I I Digital Analog NC P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] P1[7] P1[5] P0[1] NC NC NC NC P1[3] P1[1] Vss No Connection No Connection No Connection No Connection SPI CLK CLK[1], I2C SCL, SPI MOSI Ground Connection I2C SCL, SPI SS I2C SDA, SPI MISO Name No Connection Description Document Number: 001-05356 Rev. *H HCLK NC NC 22 23 24 NC AI, P0[1] AI, P2[7] AI, P2[5] AI, P2[3] AI, P2[1] AI, P3[3] AI, P3[1] AI, I2C SCL, SPI SS, P1[7] AI, I2C SDA, SPI MISO, P1[5] NC NC 1 2 3 4 5 6 7 8 9 10 11 12 OCD QFN Page 12 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 Table 6. Pin Definitions - CY8C20000 48-Pin OCD (QFN) [2] (continued) Pin No. 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 CP Power I/O I/O I/O Power I I I I/O Power I IOH IOH Input I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I IOH IOH I I Digital Analog Name CCLK HCLK P1[0] P1[2] NC NC NC P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] NC NC NC P0[6] Vdd OCDO OCDE P0[7] P0[5] P0[3] Vss NC Vss Integrating Input Ground Connection No Connection Center Pad is connected to Ground No Connection No Connection No Connection Analog Bypass Supply Voltage OCD Odd Data Output OCD Even Data I/O Active High External Reset with Internal Pull Down No Connection No Connection No Connection Optional External Clock Input (EXTCLK) OCD CPU Clock Output OCD High Speed Clock Output DATA[1], I2C SDA Description A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive. Document Number: 001-05356 Rev. *H Page 13 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C20234, CY8C20334, CY8C20434, and CY8C20534 PSoC devices. For the latest electrical specifications, check the most recent data sheet by visiting the web at http://www.cypress.com/psoc. Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC as specified, except where mentioned. Refer to Table 17 on page 20 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode. Figure 7. Voltage versus CPU Frequency and IMO Frequency Trim Options 5.25 5.25 SLIMO SLIMO SLIMO Mode=1 Mode=1 Mode=0 4.75 Vdd Voltage 4.75 Vdd Voltage O lid ng Va rati n pe gio Re 3.60 3.00 2.70 2.40 750 kHz 3 MHz 6 MHz 12 MHz 3.00 2.70 2.40 750 kHz 3 MHz SLIMO SLIMO Mode=1 Mode=0 SLIMO Mode=1 SLIMO Mode=0 6 MHz 12 MHz CPU Frequency IMO Frequency Table 7 lists the units of measure that are used in this section. Table 7. Units of Measure C dB fF Hz KB Kbit kHz kΩ MHz MΩ μA μF μH μs μV μVrms Symbol o Unit of Measure Symbol Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square μW mA ms mV nA ns nV W pA pF pp ppm ps sps s V microwatts milliampere millisecond millivolts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts Document Number: 001-05356 Rev. *H Page 14 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 Absolute Maximum Ratings Table 8. Absolute Maximum Ratings Symbol TSTG Description Storage Temperature Min -55 Typ 25 Units Notes C Higher storage temperatures reduces data retention time. Recommended storage temperature is +25oC ± 25oC. Extended duration storage temperatures above 65oC degrades reliability. o +85 C +6.0 V Vdd + 0.5 V Vdd + 0.5 V +50 mA – V Human Body Model ESD. 200 mA o Max +100 TA Vdd VIO VIOZ IMIO ESD LU Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Electro Static Discharge Voltage Latch-up Current -40 -0.5 Vss - 0.5 Vss - 0.5 -25 2000 – – – – – – – – Operating Temperature Table 9. Operating Temperature Symbol TA TJ Description Ambient Temperature Junction Temperature Min -40 -40 Typ – – Max +85 +100 Units oC oC Notes The temperature rise from ambient to junction is package specific. See Table 15 on page 18. The user must limit the power consumption to comply with this requirement. Document Number: 001-05356 Rev. *H Page 15 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 DC Electrical Characteristics DC Chip Level Specifications Table 10 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only. Table 10. DC Chip Level Specifications Symbol Vdd IDD12 IDD6 ISB27 ISB Description Supply Voltage Supply Current, IMO = 12 MHz Supply Current, IMO = 6 MHz Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and Internal Slow Oscillator Active. Mid Temperature Range. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and Internal Slow Oscillator Active. Min 2.40 – – – Typ – 1.5 1 2.6 Max 5.25 2.5 1.5 4. Units V mA mA μA μA Notes See Table 15 on page 18. Conditions are Vdd = 3.0V, TA = 25oC, CPU = 12 MHz. Conditions are Vdd = 3.0V, TA = 25oC, CPU = 6 MHz Vdd = 2.55V, 0oC ≤ TA ≤ 40oC Vdd = 3.3V, -40oC ≤ TA ≤ 85oC – 2.8 5 DC General Purpose IO Specifications Unless otherwise noted, Table 11 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, and 2.7V at 25°C. These are for design guidance only. Table 11. 5V and 3.3V DC GPIO Specifications Symbol RPU VOH1 VOH2 VOH3 VOH4 VOH5 VOH6 VOH7 VOH8 VOH9 Description Pull Up Resistor High Output Voltage Port 0, 2, or 3 Pins High Output Voltage Port 0, 2, or 3 Pins High Output Voltage Port 1 Pins with LDO Regulator Disabled High Output Voltage Port 1 Pins with LDO Regulator Disabled High Output Voltage Port 1 Pins with 3.0V LDO Regulator Enabled High Output Voltage Port 1 Pins with 3.0V LDO Regulator Enabled High Output Voltage Port 1 Pins with 2.4V LDO Regulator Enabled High Output Voltage Port 1 Pins with 2.4V LDO Regulator Enabled High Output Voltage Port 1 Pins with 1.8V LDO Regulator Enabled Min 4 Vdd - 0.2 Vdd - 0.9 Vdd - 0.2 Vdd - 0.9 2.7 Typ 5.6 – – – – 3.0 Max 8 – – – – 3.3 Units Notes kΩ V IOH < 10 μA, Vdd > 3.0V, maximum of 20 mA source current in all IOs. V IOH = 1 mA, Vdd > 3.0V, maximum of 20 mA source current in all IOs. V IOH < 10 μA, Vdd > 3.0V, maximum of 10 mA source current in all IOs. V IOH = 5 mA, Vdd > 3.0V, maximum of 20 mA source current in all IOs. V IOH < 10 μA, Vdd > 3.1V, maximum of 4 IOs all sourcing 5 mA. V IOH = 5 mA, Vdd > 3.1V, maximum of 20 mA source current in all IOs. IOH < 10 μA, Vdd > 3.0V, maximum of 20 mA source current in all IOs. IOH < 200 μA, Vdd > 3.0V, maximum of 20 mA source current in all IOs. IOH < 10 μA 3.0V ≤ Vdd ≤ 3.6V 0oC ≤ TA ≤ 85oC Maximum of 20 mA source current in all IOs. Page 16 of 34 2.2 – – 2.1 2.4 2.7 V 2.0 – – V 1.6 1.8 2.0 V Document Number: 001-05356 Rev. *H [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 Table 11. 5V and 3.3V DC GPIO Specifications (continued) Symbol VOH10 Description High Output Voltage Port 1 Pins with 1.8V LDO Regulator Enabled Min 1.5 Typ – Max – Units Notes V IOH < 100 μA. 3.0V ≤ Vdd ≤ 3.6V. 0oC ≤ TA ≤ 85oC. Maximum of 20 mA source current in all IOs. V IOL = 20 mA, Vdd > 3.0V, maximum of 60 mA sink current on even port pins (for example, P0[2] and P1[4]) and 60 mA sink current on odd port pins (for example, P0[3] and P1[5]). V 3.6V ≤ Vdd ≤ 5.25V V 3.6V ≤ Vdd ≤ 5.25V mV nA Gross tested to 1 μA pF Package and pin dependent Temperature = 25oC pF Package and pin dependent Temperature = 25oC VOL Low Output Voltage – – 0.75 VIL VIH VH IIL CIN COUT Input Low Voltage Input High Voltage Input Hysteresis Voltage Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output – 2.0 – – 0.5 0.5 – – 140 1 1.7 1.7 0.8 – – 5 5 Table 12. 2.7V DC GPIO Specifications Symbol RPU VOH1 VOH2 VOL Description Pull Up Resistor High Output Voltage Port 1 Pins with LDO Regulator Disabled High Output Voltage Port 1 Pins with LDO Regulator Disabled Low Output Voltage Min 4 Vdd - 0.2 Vdd - 0.5 – Typ 5.6 – – – Max 8 – – 0.75 Units Notes kΩ V IOH < 10 μA, maximum of 10 mA source current in all IOs. V IOH = 2 mA, maximum of 10 mA source current in all IOs. V IOL = 10 mA, maximum of 30 mA sink current on even port pins (for example, P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5]). V IOL=5 mA Maximum of 50 mA sink current on even port pins (for example, P0[2] and P3[4]) and 50 mA sink current on odd port pins (for example, P0[3] and P2[5]). 2.4V ≤ Vdd < 3.6V V 2.4V ≤ Vdd < 3.6V V 2.4V ≤ Vdd < 2.7V V 2.7V ≤ Vdd < 3.6V mV nA Gross tested to 1 μA pF Package and pin dependent Temperature = 25oC pF Package and pin dependent Temperature = 25oC VOLP1 Low Output Voltage Port 1 Pins – – 0.4 VIL VIH1 VIH2 VH IIL CIN COUT Input Low Voltage Input High Voltage Input High Voltage Input Hysteresis Voltage Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output – 1.4 1.6 – – 0.5 0.5 – – – 60 1 1.7 1.7 0.75 – – – – 5 5 Document Number: 001-05356 Rev. *H Page 17 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 DC Analog Mux Bus Specifications Table 13 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only. Table 13. DC Analog Mux Bus Specifications Symbol RSW Description Switch Resistance to Common Analog Bus Min – Typ – Max 400 800 Units W W Notes Vdd ≥ 2.7V 2.4V ≤ Vdd ≤ 2.7V DC Low Power Comparator Specifications Table 14 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V at 25°C. These are for design guidance only. Table 14. DC Low Power Comparator Specifications Symbol VREFLPC ISLPC VOSLPC Description Low power comparator (LPC) reference voltage range LPC supply current LPC voltage offset Min 0.2 – – Typ – 10 2.5 Max Units Vdd – 1 V 40 30 μA mV Notes DC POR and LVD Specifications Table 15 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only. Table 15. DC POR and LVD Specifications Symbol VPPOR0 VPPOR1 VPPOR2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Description Vdd Value for PPOR Trip PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min – – – 2.39 2.54 2.75 2.85 2.96 – – 4.52 Typ 2.36 2.60 2.82 2.45 2.71 2.92 3.02 3.13 – – 4.73 Max 2.40 2.65 2.95 2.51[3] 2.78[4] 2.99[5] 3.09 3.20 – – 4.83 Units V V V V V V V V V V V Notes Vdd is greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from Watchdog. Notes 3. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply. 4. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply. 5. Always greater than 50 mV above VPPOR (PORLEV = 10) for falling supply. Document Number: 001-05356 Rev. *H Page 18 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 DC Programming Specifications Table 16 lists the guaranteed minimum and maximum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only. Flash Endurance and Retention specifications with the use of the EEPROM User Module are valid only within the range: 25°C +/-20C during the Flash Write operation. Reference the EEPROM User Module data sheet instructions for EEPROM Flash Write requirements outside of the 25°C +/-20°C temperature window. Table 16. DC Programming Specifications Symbol Description VddIWRITE Supply Voltage for Flash Write Operations IDDP Supply Current During Programming or Verify VILP Input Low Voltage During Programming or Verify VIHP Input High Voltage During Programming or Verify IILP Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify IIHP Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify VOLV Output Low Voltage During Programming or Verify VOHV Output High Voltage During Programming or Verify FlashENPB Flash Endurance (per block) FlashENT Flash Endurance (total)[6] FlashDR Flash Data Retention Min 2.70 – – 2.2 – – – Vdd –1.0 50,000 1,800,000 10 Typ – 5 – – – – – – – – – Max – 25 0.8 – 0.2 1.5 Units V mA V V mA mA Driving internal pull down resistor. Driving internal pull down resistor. Notes Vss + 0.75 V Vdd – – – V – Erase/write cycles per block. – Erase/write cycles. Years Note 6. A maximum of 36 x 50,000 block endurance cycles is allowed. This is balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). Document Number: 001-05356 Rev. *H Page 19 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 AC Electrical Characteristics AC Chip Level Specifications Table 17, Table 18, and Table 19 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only. Table 17. 5V and 3.3V AC Chip-Level Specifications Symbol FCPU1 F32K1 FIMO12 Description CPU Frequency (3.3V Nominal) Internal Low Speed Oscillator Frequency Internal Main Oscillator Stability for 12 MHz (Commercial Temperature)[7] Min 0.75 15 11.4 Typ – 32 12 Max 12.6 64 12.6 Units MHz kHz MHz Trimmed for 3.3V operation using factory trim values. See Figure 7 on page 14, SLIMO Mode = 0. Trimmed for 3.3V operation using factory trim values. See Figure 7 on page 14, SLIMO Mode = 1. Notes 12 MHz only for SLIMO Mode = 0 FIMO6 Internal Main Oscillator Stability for 6 MHz (Commercial Temperature) 5.70 6.0 6.30 MHz DCIMO TRAMP TXRST Duty Cycle of IMO Supply Ramp Time External Reset Pulse Width 40 0 10 50 – – 60 – – % μs μs Table 18. 2.7V AC Chip Level Specifications Symbol FCPU1 F32K1 FIMO12 Description CPU Frequency (2.7V Nominal) Internal Low Speed Oscillator Frequency Internal Main Oscillator Stability for 12 MHz (Commercial Temperature)[7] Min 0.75 8 11.0 Typ – 32 12 Max 3.25 96 12.9 Units MHz kHz MHz Trimmed for 2.7V operation using factory trim values. See Figure 7 on page 14, SLIMO Mode = 0. Trimmed for 2.7V operation using factory trim values. See Figure 7 on page 14, SLIMO Mode = 1. Notes FIMO6 Internal Main Oscillator Stability for 6 MHz (Commercial Temperature) 5.60 6.0 6.40 MHz DCIMO TRAMP TXRST Duty Cycle of IMO Supply Ramp Time External Reset Pulse Width 40 0 10 50 – – 60 – – % μs μs Note 7. 0 to 70 °C ambient, Vdd = 3.3 V. Document Number: 001-05356 Rev. *H Page 20 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 Table 19. 2.7V AC Chip Level Specifications Symbol FCPU1 F32K1 FIMO12 Description CPU Frequency (2.7V Minimum) Internal Low Speed Oscillator Frequency Internal Main Oscillator Stability for 12 MHz (Commercial Temperature)[7] Min 0.75 8 11.0 Typ – 32 12 Max 6.3 96 12.9 Units MHz kHz MHz Trimmed for 2.7V operation using factory trim values. See Figure 7 on page 14, SLIMO Mode = 0. Trimmed for 2.7V operation using factory trim values. See Figure 7 on page 14, SLIMO Mode = 1. Notes FIMO6 Internal Main Oscillator Stability for 6 MHz (Commercial Temperature) 5.60 6.0 6.40 MHz DCIMO TRAMP TXRST Duty Cycle of IMO Supply Ramp Time External Reset Pulse Width 40 0 10 50 – – 60 – – % μs μs AC General Purpose IO Specifications Table 20 and Table 21 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only. Table 20. 5V and 3.3V AC GPIO Specifications Symbol FGPIO TRise023 TRise1 TFall Description GPIO Operating Frequency Rise Time, Strong Mode, Cload = 50 pF Ports 0, 2, 3 Rise Time, Strong Mode, Cload = 50 pF Port 1 Fall Time, Strong Mode, Cload = 50 pF All Ports Min 0 15 10 10 Typ – – – – Max 6 80 50 50 Units MHz ns ns ns Notes Normal Strong Mode, Port 1. Vdd = 3.0 to 3.6V and 4.75V to 5.25V, 10% - 90% Vdd = 3.0 to 3.6V, 10% - 90% Vdd = 3.0 to 3.6V and 4.75V to 5.25V, 10% - 90% Table 21. 2.7V AC GPIO Specifications Symbol FGPIO TRise023 TRise1 TFall Description GPIO Operating Frequency Rise Time, Strong Mode, Cload = 50 pF Ports 0, 2, 3 Rise Time, Strong Mode, Cload = 50 pF Port 1 Fall Time, Strong Mode, Cload = 50 pF All Ports Min 0 15 10 10 Typ – – – – Max 1.5 100 70 70 Units MHz ns ns ns Notes Normal Strong Mode, Port 1. Vdd = 2.4 to 3.0V, 10% - 90% Vdd = 2.4 to 3.0V, 10% - 90% Vdd = 2.4 to 3.0V, 10% - 90% Figure 8. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRise023 TRise1 TFall Document Number: 001-05356 Rev. *H Page 21 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 AC Comparator Amplifier Specifications Table 22 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only. Table 22. AC Operational Amplifier Specifications Symbol TCOMP Description Comparator Response Time, 50 mV Overdrive Min Typ Max 100 200 Units ns ns Notes Vdd ≥ 3.0V. 2.4V < Vcc < 3.0V. AC Analog Mux Bus Specifications Table 23 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only. Table 23. AC Analog Mux Bus Specifications Symbol FSW Switch Rate Description Min – Typ – Max 3.17 Units MHz Notes AC Low Power Comparator Specifications Table 24 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V at 25°C. These are for design guidance only. Table 24. AC Low Power Comparator Specifications Symbol TRLPC Description LPC response time Min – Typ – Max 50 Units μs Notes ≥ 50 mV overdrive comparator reference set within VREFLPC. AC External Clock Specifications Table 25, Table 26, Table 27, and Table 28 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only. Table 25. 5V AC External Clock Specifications Symbol FOSCEXT – – – Frequency High Period Low Period Power Up IMO to Switch Description Min 0.750 38 38 150 Typ – – – – Max 12.6 5300 – – Units MHz ns ns μs Notes Table 26. 3.3V AC External Clock Specifications Symbol FOSCEXT Description Frequency with CPU Clock divide by 1 Min 0.750 Typ – Max 12.6 Units MHz Notes Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. – – – High Period with CPU Clock divide by 1 Low Period with CPU Clock divide by 1 Power Up IMO to Switch 41.7 41.7 150 – – – 5300 – – ns ns μs Document Number: 001-05356 Rev. *H Page 22 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 Table 27. 2.7V (Nominal) AC External Clock Specifications Symbol FOSCEXT Description Frequency with CPU Clock divide by 1 Min 0.750 Typ – Max 3.080 Units MHz Notes Maximum CPU frequency is 3 MHz at 2.7V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. If the frequency of the external clock is greater than 3 MHz, the CPU clock divider is set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met. FOSCEXT Frequency with CPU Clock divide by 2 or greater 0.15 – 6.35 MHz – – – High Period with CPU Clock divide by 1 Low Period with CPU Clock divide by 1 Power Up IMO to Switch 160 160 150 – – – 5300 – – ns ns μs Table 28. 2.7V (Minimum) AC External Clock Specifications Symbol FOSCEXT Description Frequency with CPU Clock divide by 1 Min 0.750 Typ – Max 6.30 Units MHz Notes Maximum CPU frequency is 6 MHz at 2.7V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. If the frequency of the external clock is greater than 6 MHz, the CPU clock divider is set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met. FOSCEXT Frequency with CPU Clock divide by 2 or greater 0.15 – 12.6 MHz – – – High Period with CPU Clock divide by 1 Low Period with CPU Clock divide by 1 Power Up IMO to Switch 160 160 150 – – – 5300 – – ns ns μs AC Programming Specifications Table 29 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only. Table 29. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 TDSCLK2 Description Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Min 1 1 40 40 0 – – – – – Typ – – – – – 15 30 – – – Max 20 20 – – 8 – – 45 50 70 Units ns ns ns ns MHz ms ms ns ns ns 3.6 < Vdd 3.0 ≤ Vdd ≤ 3.6 2.4 ≤ Vdd ≤ 3.0 Notes Document Number: 001-05356 Rev. *H Page 23 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 AC SPI Specifications Table 30 and Table 31 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only. Table 30. 5V and 3.3V AC SPI Specifications Symbol FSPIM FSPIS TSS Description Maximum Input Clock Frequency Selection, Master Maximum Input Clock Frequency Selection, Slave Width of SS_ Negated Between Transmissions Min – – 50 Typ – – – Max 6.3 2.05 – Units MHz MHz ns Notes Output clock frequency is half of input clock rate. Table 31. 2.7V AC SPI Specifications Symbol FSPIM FSPIS TSS Description Maximum Input Clock Frequency Selection, Master Maximum Input Clock Frequency Selection, Slave Width of SS_ Negated Between Transmissions Min – – 50 Typ – – – Max 3.15 Units MHz Notes Output clock frequency is half of input clock rate. 1.025 MHz – ns AC I2C Specifications Table 32 and Table 33 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C respectively. Typical parameters apply to 5V, 3.3V, or 2.7V at 25°C. These are for design guidance only. Table 32. AC Characteristics of the I2C SDA and SCL Pins for Vdd ≥ 3.0V Symbol FSCLI2C Description SCL Clock Frequency Standard Mode Min 0 4.0 Max 100 – Fast Mode Min 0 0.6 Max 400 – Units kHz μs THDSTAI2C Hold Time (repeated) START Condition. After this period, the first clock pulse is generated TLOWI2C THIGHI C TSUSTAI2C 2 LOW Period of the SCL Clock HIGH Period of the SCL Clock Setup Time for a Repeated START Condition Data Setup Time Setup Time for STOP Condition Bus Free Time Between a STOP and START Condition Pulse Width of spikes are suppressed by the input filter 4.7 4.0 4.7 0 250 4.0 4.7 – – – – – – – – – 1.3 0.6 0.6 0 100 [8] – – – – – – – 50 μs μs μs μs ns μs μs ns THDDATI2C Data Hold Time TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C 0.6 1.3 0 Note 8. A Fast Mode I2C bus device is used in a Standard Mode I2C bus system but the requirement tSU; DAT Š 250 ns is met. This automatically is the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU; DAT = 1000 + 250 = 1250 ns (according to the Standard Mode I2C bus specification) before the SCL line is released. Document Number: 001-05356 Rev. *H Page 24 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 Table 33. 2.7V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported) Symbol FSCLI2C 2 Description SCL Clock Frequency. Standard Mode Min 0 4.0 Max 100 – Fast Mode Min – – Max – – Units kHz μs THDSTAI C Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. TLOWI2C THIGHI2C LOW Period of the SCL Clock. HIGH Period of the SCL Clock 4.7 4.0 4.7 0 250 4.0 4.7 – – – – – – – – – – – – – – – – – – – – – – – – – μs μs μs μs ns μs μs ns TSUSTAI2C Setup Time for a Repeated START Condition. THDDATI2C Data Hold Time. TSUDATI2C Data Setup Time. TSUSTOI2C Setup Time for STOP Condition. TBUFI2C TSPI2C Bus Free Time Between a STOP and START Condition. Pulse Width of spikes are suppressed by the input filter. Figure 9. Definition for Timing for Fast/Standard Mode on the I2C Bus SDA T LOWI2C T SUDATI2C T HDSTAI2C T SPI2C T BUFI2C SCL S T HDSTAI2C T HDDATI2C T HIGHI2C T SUSTAI2C Sr T SUSTOI2C P S Document Number: 001-05356 Rev. *H Page 25 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 Packaging Dimensions This section illustrates the packaging specifications for the CY8C20234, CY8C20334, CY8C20434, and CY8C20534 PSoC devices along with the thermal impedances for each package. It is important to note that emulation tools require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161. Figure 10. 16-Pin Chip On Lead 3 X 3 mm Package Outline (Sawn) 001-09116 *D Document Number: 001-05356 Rev. *H Page 26 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 Figure 11. 24-Pin (4 x 4 x 0.6 mm) Sawn QFN 19 24 18 1 13 6 12 7 NO TES : 1. H A T C H IS S O L D E R A B L E E X P O S E D M E T A L . 2 . R E F E R E N C E J E D E C # M O -2 4 8 3 . U N IT P A C K A G E W E IG H T : 0 .0 2 4 g ra m s 4 . A L L D IM E N S IO N S A R E IN M IL L IM E T E R S 001-13937 *B Figure 12. 28-Pin (210-Mil) SSOP 51-85079 *C Document Number: 001-05356 Rev. *H Page 27 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 Figure 13. 32-Pin QFN 5 x 5 mmX 0.60 Max (Sawn) 001-48913 *A Figure 14. 32-Pin (5 x 5 mm 0.60 MAX) QFN 001-06392 *A Document Number: 001-05356 Rev. *H Page 28 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 Figure 15. 48-Pin (7 x 7 mm) QFN SOLDERABLE EXPOSED PAD NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED METAL. 2. REFERENCE JEDEC#: MO-220 3. PACKAGE WEIGHT: 0.13g 4. ALL DIMENSIONS ARE IN MM [MIN/MAX] 5. PACKAGE CODE PART # LF48A LY48A DESCRIPTION STANDARD LEAD FREE UNLESS OTHERWISE SPECIFIED ALL DIMENSIONS ARE IN INCHES [MILLIMETERS] STANDARD TOLERANCES ON: DECIMALS ANGLES + + .XX .XXX + .XXXX + DESIGNED BY DRAWN CHK BY APPROVED BY APPROVED BY DATE DATE JSO 02/02/07 DATE CYPRESS COMPANY CONFIDENTIAL TITLE DATE DATE 48LD QFN 7 X 7mm PACKAGE OUTLINE (SUBCON PUNCH TYPE PKG with 5.1 X 5.1 EPAD) PART NO. DWG NO MATERIAL SIZE 001-12919 *AREV SEE NOTES 001-12919 *A For information on the preferred dimensions for mounting the QFN packages, see the application note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. It is important to note that pinned vias for thermal conduction are not required for the low power 24, 32, and 48-pin QFN PSoC devices. Thermal Impedances Table 34 illustrates the minimum solder reflow peak temperature to achieve good solderability. Table 34. Thermal Impedances Per Package Package 16 QFN 24 QFN[10] 28 SSOP 32 QFN[10] [10] Solder Reflow Peak Temperature Table 35 illustrates the minimum solder reflow peak temperature to achieve good solderability. Table 35. Solder Reflow Peak Temperature Package 16 QFN 24 QFN 28 SSOP 32 QFN 48 QFN Min Peak Temperature [11] 240oC 240oC 240oC 240oC 240oC Max Peak Temperature 260oC 260oC 260oC 260oC 260oC Typical θJA 46 oC/W [9] 25 oC/W 96 oC/W 27 oC/W o 48 QFN 28 C/W Notes 9. TJ = TA + Power x θJA. 10. To achieve the thermal impedance specified for the QFN package, the center thermal pad is soldered to the PCB ground plane. 11. Higher temperatures is required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. Document Number: 001-05356 Rev. *H Page 29 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 Development Tool Selection Software PSoC Designer™ At the core of the PSoC development software suite is PSoC Designer. This is used by thousands of PSoC developers. This robust software is facilitating PSoC designs for half a decade. PSoC Designer is available free of charge at http://www.cypress.com under DESIGN RESOURCES >> Software and Drivers. PSoC Programmer PSoC Programmer is flexible enough and is used on the bench in development and also suitable for factory programming. PSoC Programmer works either as a standalone programming application or operates directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free of charge at http://www.cypress.com/psocprogrammer. C Compilers PSoC Designer comes with a free HI-TECH C Lite C compiler. The HI-TECH C Lite compiler is free, supports all PSoC devices, integrates fully with PSoC Designer and PSoC Express, and runs on Windows versions up to 32-bit Vista. Compilers with additional features are available at additional cost from their manufactures. ■ HI-TECH C PRO for the PSoC is available from http://www.htsoft.com. ■ ImageCraft Cypress Edition Compiler is available from http://www.imagecraft.com. CY3210-ExpressDK PSoC Express Development Kit The CY3210-ExpressDK is for advanced prototyping and development with PSoC Express (used with ICE-Cube In-Circuit Emulator). It provides access to I2C buses, voltage reference, switches, upgradeable modules, and more. The kit includes: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ PSoC Express Software CD Express Development Board Four Fan Modules Two Proto Modules MiniProg In-System Serial Programmer MiniEval PCB Evaluation Board Jumper Wire Kit USB 2.0 Cable Serial Cable (DB9) 110 ~ 240V Power Supply, Euro-Plug Adapter 2 CY8C24423A-24PXI 28-PDIP Chip Samples 2 CY8C27443-24PXI 28-PDIP Chip Samples 2 CY8C29466-24PXI 28-PDIP Chip Samples Evaluation Tools All evaluation tools are sold at the Cypress Online Store. CY3210-MiniProg1 The CY3210-MiniProg1 kit enables the user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes: ■ ■ ■ ■ ■ ■ ■ Development Kits All development kits are sold at the Cypress Online Store. CY3215-DK Basic Development Kit The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface enables users to run, halt, and single step the processor and view the content of specific memory locations. PSoC Designer supports the advance emulation features also. The kit includes: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ MiniProg Programming Unit MiniEval Socket Programming and Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software CD Getting Started Guide USB 2.0 Cable PSoC Designer Software CD ICE-Cube In-Circuit Emulator ICE Flex-Pod for CY8C29x66 Family Cat-5 Adapter Mini-Eval Programming Board 110 ~ 240V Power Supply, Euro-Plug Adapter iMAGEcraft C Compiler (Registration Required) ISSP Cable USB 2.0 Cable and Blue Cat-5 Cable 2 CY8C29466-24PXI 28-PDIP Chip Samples Document Number: 001-05356 Rev. *H Page 30 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 CY3210-PSoCEval1 The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ MIniProg Programming Unit Mini USB Cable PSoC Designer and Example Projects CD Getting Started Guide Wire Pack Evaluation Board with LCD Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2) PSoC Designer Software CD Getting Started Guide USB 2.0 Cable Device Programmers All device programmers are purchased from the Cypress Online Store. CY3216 Modular Programmer The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes: ■ ■ ■ ■ ■ ■ CY3214-PSoCEvalUSB The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special features of the board include both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of bread boarding space to meet all of your evaluation needs. The kit includes: ■ ■ Modular Programmer Base 3 Programming Module Cards MiniProg Programming Unit PSoC Designer Software CD Getting Started Guide USB 2.0 Cable PSoCEvalUSB Board LCD Module CY3207ISSP In-System Serial Programmer (ISSP) The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production programming environment. Note that CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes: ■ ■ ■ ■ CY3207 Programmer Unit PSoC ISSP Software CD 110 ~ 240V Power Supply, Euro-Plug Adapter USB 2.0 Cable Accessories (Emulation and Programming) Table 36. Emulation and Programming Accessories Part Number CY8C20234-12LKXI CY8C20334-12LQXI CY8C20534-12PVXI CY8C20434-12LKXI Third Party Tools Several tools are specially designed by the following third party vendors to accompany PSoC devices during development and production. Specific details of each of these tools are found at http://www.cypress.com under DESIGN RESOURCES >> Evaluation Boards. Pin Package 16 SOIC 24 QFN 28 SSOP 32 QFN Flex-Pod Kit [12] CY3250-20334QFN CY3250-20434QFN Foot Kit [13] CY3250-16QFN-FK CY3250-24QFN-FK CY3250-28SSOP-FK CY3250-32QFN-FK Prototyping Module CY3210-0X34 CY3210-0X34 CY3210-0X34 CY3210-0X34 Adapter [14] AS-24-28-01ML-6 AS-32-28-03ML-6 Build a PSoC Emulator into Your Board For details on emulating the circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, see Application Note AN2323 “Debugging - Build a PSoC Emulator into Your Board” at http://www.cypress.com. Notes 12. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. 13. Foot kit includes surface mount feet that is soldered to the target PCB. 14. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters is found at http://www.emulation.com. Document Number: 001-05356 Rev. *H Page 31 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 Ordering Information Table 37 lists the CY8C20234, CY8C20334, CY8C20434, and CY8C20534 PSoC device’s key package features and ordering codes. Table 37. PSoC Device Key Features and Ordering Information Ordering Code CY8C20234-12LKXI Package 16-Pin (3x3 mm 0.60 MAX) Sawn QFN Flash (Bytes) 8K 8K SRAM (Bytes) 512 512 Digital CapSense Digital Blocks Blocks I/O Pins 0 0 1 1 13 13 Analog Inputs 13[15] 13[15] 20[15] 20[15] 28[15] 28[15] 28 28 Analog XRES Outputs Pin 0 0 Yes Yes CY8C20234-12LKXIT 16-Pin (3x3 mm 0.60 MAX) Sawn QFN (Tape and Reel) CY8C20334-12LQXI 24-Pin (4x4 mm 0.60 MAX) SAWN QFN 8K 8K 512 512 0 0 1 1 20 20 0 0 Yes Yes CY8C20334-12LQXIT 24-Pin (4x4 mm 0.60 MAX) Sawn QFN (Tape and Reel) CY8C20434-12LKXI 32-Pin (5x5 mm 0.60 MAX) QFN 8K 8K 512 512 0 0 1 1 28 28 0 0 Yes Yes CY8C20434-12LKXIT 32-Pin (5x5 mm 0.60 MAX) QFN (Tape and Reel) CY8C20434-12LQXI 32-Pin (5x5 mm 0.60 MAX) Thin Sawn QFN 8K 8K 512 512 0 0 1 1 28 28 0 0 Yes Yes CY8C20434-12LQXIT 32-Pin (5x5 mm 0.60 MAX) Thin Sawn QFN (Tape and Reel) CY8C20534-PVXI CY8C20534-PVXIT CY8C20000-12LFXI 28-Pin (210-Mil) SSOP 28-Pin (210-Mil) SSOP (Tape and Reel) 48-Pin OCD QFN[16] 8K 8K 8K 512 512 512 0 0 0 1 1 1 24 24 28 24 24 28[15] 0 0 0 Yes Yes Yes Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE). Figure 16. Ordering Code Definitions CY 8 C 20 xxx- 12 xx Package Type: PX = PDIP Pb-Free C = Commercial SX = SOIC Pb-Free I = Industrial PVX = SSOP Pb-Free E = Extended LFX/LKX/LQX = QFN Pb-Free AX = TQFP Pb-Free Thermal Rating: Speed: 12 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress Notes 15. Dual function Digital I/O Pins also connect to the common analog mux. 16. This part may be used for in-circuit debugging. It is NOT available for production. Document Number: 001-05356 Rev. *H Page 32 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 Document History Page Document Title: CY8C20234/CY8C20334/CY8C20434/CY8C20534 PSoC® Programmable System-on-Chip™ Document Number: 001-05356 Revision ** *A ECN 404571 418513 Orig. of Change HMT HMT Submission Date See ECN See ECN Description of Change New silicon and document (Revision **). Updated Electrical Specifications, including Storage Temperature and Maximum Input Clock Frequency. Updated Features and Analog System Overview. Modified 32-pin QFN E-PAD dimensions. Added new 32-pin QFN. Add High Output Drive indicator to all P1[x] pinouts. Updated trademarks. Made data sheet “Final”. Added new Development Tool section. Added OCD pinout and package diagram. Added 16-pin QFN. Updated 24-pin and 32-pin QFN package diagrams to 0.60 MAX thickness. Changed from commercial to industrial temperature range. Updated Storage Temperature specification and notes. Updated thermal resistance data. Added development tool kit part numbers. Finetuned features and electrical specifications. Added CapSense SNR requirement reference. Added Low Power Comparator (LPC) AC/DC electrical specifications tables. Added 2.7V minimum specifications. Updated figure standards. Updated Technical Training paragraph. Added QFN package clarifications and dimensions. Updated ECN-ed Amkor dimensioned QFN package diagram revisions. Updated 24-pin QFN Theta JA. Added External Reset Pulse Width, TXRST, specification. Fixed 48-pin QFN.vsd. Updated the table introduction and high output voltage description in section two. The sentence: "Exceeding maximum ratings may shorten the battery life of the device.” does not apply to all data sheets. Therefore, the word "battery" is changed to "useful.” Took out tabs after table and figure numbers in titles and added two hard spaces. Updated the section, DC General Purpose IO Specifications on page 16 with new text. Updated VOH5 and VOH6 to say, ”High Output Voltage, Port 1 Pins with 3.0V LDO Regulator Enabled.” Updated VOH7 and VOH8 with the text, “maximum of 20 mA source current in all IOs.”Added 28-pin SSOP part, pinout, package. Updated specs. Modified dev. tool part numbers. *B 490071 HMT See ECN *C 788177 HMT See ECN *D 1356805 HMT/SFVTMP See ECN 3/HCL/SFV Document Number: 001-05356 Rev. *H Page 33 of 34 [+] Feedback CY8C20234, CY8C20334 CY8C20434, CY8C20534 Document History Page Orig. of Change UVS/AESA (continued) Document Title: CY8C20234/CY8C20334/CY8C20434/CY8C20534 PSoC® Programmable System-on-Chip™ Document Number: 001-05356 Revision *E ECN 2197347 Submission Date See ECN Description of Change Added 32-pin Sawn QFN Pin diagram Removed package diagram: 32-Pin (5 X 5 mm) SAWN QFN(001-42168 *A) Updated Ordering Information table with CY8C20434-12LQXI and CY8C20434-12LQXIT ordering details. Corrected Table 16. DC Programming Specifications - Included above the table "Flash Endurance and Retention specifications with the use of the EEPROM User Module are valid only within the range: 25°C +/-20C during the Flash Write operation. Refer the EEPROM User Module data sheet instructions for EEPROM Flash Write requirements outside of the 25°C +/-20°C temperature window." Corrected Ordering Information format. Updated package diagrams 001-13937 and 001-30999. Updated data sheet template. Corrected Figure 6 (28-pin diagram). Updated VOH5, VOH7, and VOH9 specifications Changed title from PSoC® Mixed Signal Array to PSoC® Programmable System-on-Chip™ Replaced package outline drawing for 32-Pin Sawn QFN Updated “Development Tool Selection” on page 30 Updated “Development Tools” on page 4 and “Designing with PSoC Designer” on page 5 Updated “Getting Started” on page 3 *F 2542938 RLRM/AESA 07/30/2008 *G *H 2610469 2693024 SNV/PYRS DPT/PYRS 11/20/08 04/16/2009 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at cypress.com/sales. Products PSoC Clocks & Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com PSoC Solutions General Low Power/Low Voltage Precision Analog LCD Drive CAN 2.0b USB psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/precision-analog psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb © Cypress Semiconductor Corporation, 2005-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-05356 Rev. *H Revised April 16, 2009 Page 34 of 34 PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations.Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback