CY8C20336H

Haptics Enabled CapSense Controller Features ■ ■ CY8C20336H, CY8C20446H ® 1.71-V to 5.5-V operating range Low power CapSense® block ❐ Configurable capacitive sensing elements ❐ Supports combination of CapSense buttons, sliders, touchpads, touchscreens, and proximity sensors ■ Powerful Harvard-architecture processor ❐ M8C CPU speed can be up to 24 MHz or sourced by an external crystal, resonator, or clock signal ❐ Low power at high speed ❐ Interrupt controller ❐ Temperature range: –40 °C to +85 °C ■ Flexible on-chip memory ❐ Two program/data storage size options: • CY8C20336H: 8 KB flash / 1 KB SRAM • CY8C20446H: 16 KB flash / 2 KB SRAM ❐ 50,000 flash erase/write cycles ❐ Partial flash updates ❐ Flexible protection modes ❐ In-System Serial Programming (ISSP) ■ ■ ■ Integrates Immersion TS2000 Haptics technology for ERM drive control Versatile analog mux ❐ Common internal analog bus ❐ Simultaneous connection of I/O ❐ High Power supply rejection ratio (PSRR) comparator ❐ Low dropout voltage regulator for all analog resources Additional system resources ❐ I2C slave: • Selectable to 50 kHz, 100 kHz, or 400 kHz • No clock stretching (under most conditions) • Implementation during sleep modes with less than 100 µA • Hardware address validation ❐ SPI master and slave: Configurable 46.9 kHz to 12 MHz ❐ Three 16-bit timers ❐ Watchdog and sleep timers ❐ Internal voltage reference ❐ Integrated supervisory circuit ❐ 8- to 10-bit incremental analog-to-digital converter (ADC) ❐ Two general-purpose high-speed, low-power analog comparators Complete development tools ❐ Free development tool (PSoC Designer™) ❐ Full featured, In-Circuit Emulator (ICE) and programmer ❐ Full-speed emulation ❐ Complex breakpoint structure ❐ 128 KB trace memory Package options ❐ CY8C20336H: • 24-pin 4 × 4 × 0.6 mm QFN ❐ CY8C20446H: • 32-pin 5 × 5 × 0.6 mm QFN ■ Precision, programmable clocking ❐ Internal main oscillator (IMO): 6/12/24 MHz ± 5% ❐ Internal low-speed oscillator (ILO) at 32 kHz for watchdog and sleep timers ❐ Precision 32-kHz oscillator for optional external crystal ■ Programmable pin configurations ❐ Up to 28 general-purpose I/Os (GPIOs) (depending on the package) ❐ Dual-mode GPIO: All GPIOs support digital I/O and analog inputs ❐ 25-mA sink current on each GPIO • 120-mA total sink current on all GPIOs ❐ Pull-up, high Z, open drain modes on all GPIOs ❐ CMOS drive mode: 5-mA source current on ports 0 and 1 and 1 mA on ports 2, 3, and 4 • 20-mA total source current on all GPIOs ❐ Selectable, regulated digital I/O on port 1 ❐ Configurable input threshold on port 1 ❐ Hot swap capability on all port 1 GPIOs ■ ■ Cypress Semiconductor Corporation Document Number: 001-56223 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 •408-943-2600 Revised March 24, 2011 [+] Feedback CY8C20336H, CY8C20446H Logic Block Diagram Port 4 Port 3 Port 2 Port 1 Port 0 1.8/2.5/3V LDO PWRSYS [1] (Regulator) PSoC CORE SYSTEM BUS Global Analog Interconnect 1K/2K SRAM Interrupt Controller 8K/16K Flash Nonvolatile Memory Sleep and Watchdog Supervisory ROM (SROM) CPU Core (M8C) 6/12/24 MHz Internal Main Oscillator (IMO) Internal Low Speed Oscillator (ILO) Multiple Clock Sources CAPSENSE SYSTEM CapSense Module Two Comparators Analog Reference Analog Mux SYSTEM BUS I2C Slave Internal Voltage References System Resets POR and LVD SPI Master/ Slave Three 16-Bit Programmable Timers Digital Clocks SYSTEM RESOURCES Note 1. Internal voltage regulator for internal circuitry Document Number: 001-56223 Rev. *C Page 2 of 33 [+] Feedback CY8C20336H, CY8C20446H Contents PSoC® Functional Overview............................................ 4 PSoC Core .................................................................. 4 CapSense System....................................................... 4 Haptics TS2000 Controller .......................................... 4 Additional System Resources ..................................... 5 Getting Started.................................................................. 5 Application Notes ........................................................ 5 Development Kits ........................................................ 5 Training ....................................................................... 5 CYPros Consultants .................................................... 5 Solutions Library.......................................................... 5 Technical Support ....................................................... 5 Designing with PSoC Designer ....................................... 6 Select User Modules ................................................... 6 Configure User Modules.............................................. 6 Organize and Connect ................................................ 6 Generate, Verify, and Debug....................................... 6 Pinouts .............................................................................. 7 24-Pin QFN ................................................................ 7 32-Pin QFN ................................................................ 8 48-Pin QFN OCD ........................................................ 9 Electrical Specifications ................................................ 10 Absolute Maximum Ratings....................................... 10 Operating Temperature ............................................. 10 DC Chip-Level Specifications.................................... 11 DC General Purpose I/O Specifications .................... 12 DC Analog Mux Bus Specifications........................... 14 DC Low Power Comparator Specifications ............... 14 Comparator User Module Electrical Specifications ... 15 ADC Electrical Specifications ................................... 15 DC POR and LVD Specifications .............................. 16 DC Programming Specifications ............................... 16 AC Chip-Level Specifications .................................... 17 AC General Purpose I/O Specifications .................... AC Comparator Specifications .................................. AC External Clock Specifications .............................. AC Programming Specifications................................ AC I2C Specifications ................................................ Packaging Information................................................... Thermal Impedances ................................................ Capacitance on Crystal Pins .................................... Solder Reflow Peak Temperature ............................. Development Tool Selection ......................................... Software .................................................................... Development Kits ...................................................... Evaluation Tools............................................................. Device Programmers................................................. Accessories (Emulation and Programming) .............. Third Party Tools ....................................................... Build a PSoC Emulator into Your Board.................... Ordering Information...................................................... Ordering Code Definitions............................................. Document Conventions ................................................. Acronyms Used ......................................................... Units of Measure ....................................................... Numeric Naming........................................................ Glossary .......................................................................... Reference Documents.................................................... Document History Page ................................................. Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC Solutions ......................................................... 18 19 19 20 21 25 27 27 27 28 28 28 29 29 30 30 30 30 30 31 31 31 31 32 32 33 33 33 33 33 Document Number: 001-56223 Rev. *C Page 3 of 33 [+] Feedback CY8C20336H, CY8C20446H PSoC® Functional Overview The PSoC family consists of on-chip controller devices, which are designed to replace multiple traditional microcontroller unit (MCU)-based components with one, low-cost single-chip programmable component. A PSoC device includes configurable analog and digital blocks, and programmable interconnect. This architecture allows the user to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast CPU, flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. The architecture for this device family, as shown in the Logic Block Diagram on page 2, consists of three main areas: ■ ■ ■ Figure 1. CapSense System Block Diagram CS1 IDAC Analog Global Bus CS2 CSN Vr Reference Buffer The core CapSense analog system System resources (including a full-speed USB port). Cinternal Comparator Mux Mux Cexternal (P0[1] or P0[3]) A common, versatile bus allows connection between the I/O and the analog system. Each CY8C20336H/446H PSoC device includes a dedicated CapSense block that provides sensing and scanning control circuitry for capacitive sensing applications. Depending on the PSoC package, up to 28 GPIOs are also included. The GPIOs provide access to the MCU and analog mux. Refs Cap Sense Counters CSCLK PSoC Core The PSoC core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and IMO and ILO. The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a 4-MIPS, 8-bit Harvardarchitecture microprocessor. IMO CapSense Clock Select Oscillator Analog Multiplexer System The analog mux bus can connect to every GPIO pin. Pins are connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with the CapSense block comparator. Switch-control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include: ■ ■ ■ CapSense System The analog system contains the capacitive sensing hardware. Several hardware algorithms are supported. This hardware performs capacitive sensing and scanning without requiring external components. The analog system is composed of the CapSense PSoC block and an internal 1-V or 1.2-V analog reference, which together support capacitive sensing of up to 28 inputs[2]. Capacitive sensing is configurable on each GPIO pin. Scanning of enabled CapSense pins are completed quickly and easily across multiple ports. SmartSense™ SmartSense is an innovative solution from Cypress that removes manual tuning of CapSense applications. This solution is easyto-use and provides a robust noise immunity. It is the only autotuning solution that establishes, monitors, and maintains all required tuning parameters. SmartSense allows engineers to go from prototyping to mass production without re-tuning for manufacturing variations in PCB and/or overlay material properties. Complex capacitive sensing interfaces, such as sliders and touchpads. Chip-wide mux that allows analog input from any I/O pin. Crosspoint connection between any I/O pin combinations. Haptics TS2000 Controller The CY8C20336H/CY8C20446H family of devices feature an easy-to-use Haptics controller resource with up to 14 different effects. These effects are available for use with three different, selectable ERM modules. Note 2. 36 GPIOs = 33 pins for capacitive sensing + 2 pins for I2C + 1 pin for modulator capacitor. Document Number: 001-56223 Rev. *C Page 4 of 33 [+] Feedback CY8C20336H, CY8C20446H Additional System Resources System resources provide additional capability, such as configurable USB and I2C slave, SPI master/slave communication interface, three 16-bit programmable timers, and various system resets supported by the M8C. These system resources provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. The merits of each system resource are listed here: ■ Application Notes Application notes are an excellent introduction to the wide variety of possible PSoC designs. They are located at www.cypress.com/psoc. Select Application Notes under the Documentation tab. Development Kits PSoC Development Kits are available online from Cypress at www.cypress.com/shop and through a growing number of regional and global distributors, which include Arrow, Avnet, DigiKey, Farnell, Future Electronics, and Newark. Refer to Development Kits on page 28. The I2C slave/SPI master-slave module provides 50/100/400 kHz communication over two wires. SPI communication over three or four wires runs at speeds of 46.9 kHz to 3 MHz (lower for a slower system clock). The I2C hardware address recognition feature reduces the already low power consumption by eliminating the need for CPU intervention until a packet addressed to the target device is received. The I2C enhanced slave interface appears as a 32-byte RAM buffer to the external I2C master. Using a simple predefined protocol, the master controls the read and write pointers into the RAM. When this method is enabled, the slave does not stall the bus when receiving data bytes in active mode. For usage details, refer to the application note I2C Enhanced Slave Operation - AN56007. Low voltage detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced poweron-reset (POR) circuit eliminates the need for a system supervisor. An internal reference provides an absolute reference for capacitive sensing. A register-controlled bypass mode allows the user to disable the LDO regulator. Training Free PSoC and CapSense technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training. The training covers a wide variety of topics and skill levels to assist you in your designs. ■ ■ CYPros Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to www.cypress.com/cypros. Solutions Library Visit our growing library of solution focused designs at www.cypress.com/solutions. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. ■ ■ ■ Technical Support For assistance with technical issues, search KnowledgeBase articles and forums at www.cypress.com/support. If you cannot find an answer to your question, create a technical support case or call technical support at 1-800-541-4736. In-Circuit Emulator A low-cost, high-functionality In-Circuit Emulator (ICE) is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24MHz) operation. Getting Started The quickest way to understand PSoC silicon is to read this datasheet and then use the PSoC Designer Integrated Development Environment (IDE). This datasheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in depth information, along with detailed programming details, see the Technical Reference Manual for the CY8C20336H/446H PSoC devices. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device datasheets on the web at http://www.cypress.com/psoc. Document Number: 001-56223 Rev. *C Page 5 of 33 [+] Feedback CY8C20336H, CY8C20446H Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed-function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and lowering inventory costs. These configurable resources, called PSoC blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is: 1. Select user modules. 2. Configure user modules. 3. Organize and connect. 4. Generate, verify, and debug. Organize and Connect Build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. Perform the selection, configuration, and routing so that you have complete control over all on-chip resources. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, perform the “Generate Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides APIs with high-level functions to control and respond to hardware events at run time, and interrupt service routines that you can adapt as needed. A complete code development environment allows you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside PSoC Designer's Debugger (accessed by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer. It allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals. Select User Modules PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called “user modules.” User modules make selecting and implementing peripheral devices, both analog and digital, simple. Configure User Modules Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a Pulse Width Modulator (PWM) User Module configures one or more digital PSoC blocks, one for each eight bits of resolution. Using these parameters, you can establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All of the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the internal operation of the user module and provide performance specifications. Each datasheet describes the use of each user module parameter, and other information that you may need to successfully implement your design. Document Number: 001-56223 Rev. *C Page 6 of 33 [+] Feedback CY8C20336H, CY8C20446H Pinouts The CY8C20336H/CY8C20446H PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of digital I/O and connection to the common analog bus. However, VSS, VDD, and XRES are not capable of digital I/O. 24-Pin QFN Table 1. Pin Definitions - CY8C20336H [3, 4] Type Pin No. Digital Analog Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CP IOH IOH IOH IOH Power I/O IOH IOH IOH IOH Power I I I I Power IOHR IOHR IOHR IOHR Input I I I I I I I I I I/O I/O I/O IOHR IOHR IOHR IOHR I I I I I I I P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] NC Vss P1[0] P1[2] P1[4] P1[6] XRES P2[0] P0[0] P0[2] P0[4] P0[6] VDD P0[7] P0[5] P0[3] P0[1] VSS Integrating input Integrating input Center pad must be connected to ground Supply voltage Active high external reset with internal pull down Optional external clock input (EXTCLK) I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK ISSP CLK[5], I2C SCL, SPI MOSI No connection Ground connection ISSP DATA[5], I2C SDA, SPI CLK Description Crystal output (XOut) Crystal input (XIn) Figure 2. CY8C20336H PSoC Device P0[1], AI P0[3], AI P0[5], AI P0[7], AI VDD P0[6], AI 21 24 22 23 20 19 18 17 16 15 14 11 10 12 8 9 13 AI , XOut, P2[5] AI , XIn, P2[3] 1 2 3 4 5 7 6 AI , P2[1] AI , I2 C SCL, SPI SS, P1[7] AI , I2 C SDA, SPI MISO, P1[5] AI , SPI CLK, P1[3] QFN ( Top View ) P0[4] , AI P0[2] , AI P0[0] , AI P2[0] , AI XRES P1[6] , AI AI, ISSP CLK, I2C SCL, SPI MOSI, P1[1] NC Vss LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output. Notes 3. During power-up or reset event, device P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter any issues. 4. The center pad (CP) on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 5. These are the ISSP pins, which are not High Z at POR (Power On Reset). Document Number: 001-56223 Rev. *C AI, ISSP DATA, I 2 C SDA, SPI CLK, P1[0] AI, P1[2] AI, EXTCLK, P1[4] Page 7 of 33 [+] Feedback CY8C20336H, CY8C20446H 32-Pin QFN Table 2. Pin Definitions - CY8C20446H PSoC Device [6, 7] Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 CP IOH IOH IOH Power Power I/O I/O I/O I/O I/O I/O IOH IOH IOH IOH Power I I I IOHR IOHR IOHR IOHR Input I I I I I I I I I I Type Digital IOH I/O I/O I/O I/O I/O I/O IOHR IOHR IOHR IOHR Power I I I I VSS P0 [3], AI P0 [5], AI P0 [7], AI VDD P0 [6], AI 28 27 I I I I I I I I I I I P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD P0[7] P0[5] P0[3] VSS VSS Integrating input Crystal output (XOut) Crystal input (XIn) AI , P0[1] AI , P2[7] AI , XOut, P2[5] AI , XIn, P2[3] AI , P2[1] AI , P3[3] AI , P3[1] AI , I2 C SCL, SPI SS, P1[7] 1 2 3 4 5 6 7 8 32 31 30 29 26 25 P0 [4], AI P0 [2], AI Analog Name Description Figure 3. CY8C20446H PSoC Device QFN (Top View) I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK. ISSP CLK[8], I2C SCL, SPI MOSI. Ground connection. ISSP DATA[8], I2C SDA., SPI CLK Optional external clock input (EXTCLK) Active high external reset with internal pull down 9 10 11 12 13 14 AI, ISSP CLK, I2C SCL, SPI MOSI,P1[1] VSS AI, ISSP DATA, I 2 C SDA, SPI CLK, P1[0] AI, P 1[2] AI, I2C SDA, SPI MISO, P 1[5] AI, SPI CLK, P 1[3] Supply voltage Integrating input Ground connection Center pad must be connected to ground LEGEND A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive, R = Regulated Output. Notes 6. During power-up or reset event, device P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter any issues. 7. The center pad (CP) on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 8. These are the ISSP pins, which are not High Z at POR (Power On Reset). Document Number: 001-56223 Rev. *C AI, E XTCLK, P 1[4] AI, P 1[6] 15 16 24 23 22 21 20 19 18 17 P0[0] , AI P2[6] , AI P2[4] , AI P2[2] , AI P2[0] , AI P3[2] , AI P3[0] , AI XRES Page 8 of 33 [+] Feedback CY8C20336H, CY8C20446H 48-Pin QFN OCD The 48-pin QFN part is for the CY8C20066A On-Chip Debug (OCD) PSoC device. Note that this part is only used for in-circuit debugging.[9] Table 3. Pin Definitions - CY8C20066A PSoC Device [10, 11] Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 IOHR IOHR Power I/O I/O Power IOHR IOHR I I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IOHR IOHR I I I I I I I I I I I I Analog Digital Figure 4. CY8C20066A PSoC Device P0[1], AI OCDO VDD P0[6], AI P0[4], AI P0[2], AI P0[0], AI 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P2[6] , AI P2[4] , AI P2[2] , AI P2[0] , AI P4[2] , AI P4[0] , AI P3[6] , AI P3[4] , AI P3[2] , AI P3[0] , AI XRES P1[6] , AI Name Description VSS P0[3], AI P0[5 ], AI P0[7], AI OCDE OCDOE OCD mode direction pin P2[7] P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] CCLK HCLK P1[3] P1[1] Vss D+ DVDD P1[0] P1[2] I2C SCL, SPI SS I2C SDA, SPI MISO OCD CPU clock output OCD high speed clock output SPI CLK. ISSP CLK[12], I2C SCL, SPI MOSI Ground connection USB D+ USB DSupply voltage ISSP DATA(12), I2C SDA, SPI CLK Crystal output (XOut) Crystal input (XIn) OCDOE AI, P2[7] AI, XOut, P2[5] AI, XIn , P2[3] AI , P2[1] AI , P4[3] AI , P4[1] AI , P3[7] AI , P3[5] AI , P3[3] AI , P3[1] AI, I2 C SCL, SPI SS, P1[7] 1 2 3 4 5 6 Pin No. 24 25 26 27 28 29 30 31 32 33 34 35 36 IOHR IOHR Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I I I P1[4] P1[6] XRES P3[0] P3[2] P3[4] P3[6] P4[0] P4[2] P2[0] P2[2] P2[4] P2[6] Active high external reset with internal pull down Optional external clock input (EXTCLK) 37 38 39 40 41 42 43 44 45 46 47 48 CP Analog Digital Name P0[0] P0[2] P0[4] P0[6] VDD OCDO OCDE Supply voltage IOH IOH IOH IOH Power I I I I IOH IOH IOH Power IOH Power I I I I P0[7] P0[5] P0[3] VSS P0[1] VSS Center pad must be connected to ground Integrating input Ground connection LEGEND A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive, R = Regulated Output. Notes 9. This part is available in limited quantities for In-Circuit Debugging during prototype development. It is not available in production volumes. 10. During power-up or reset event, device P1[1] and P1[0] may disturb the I2C bus. Use alternate pins if you encounter any issues. 11. The center pad (CP) on the QFN package must be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 12. These are the ISSP pins, which are not High Z at power on reset (POR). Document Number: 001-56223 Rev. *C I 2 C SDA, SPI MISO, AI, P1[5] CCLK HCLK SPI CLK, A I, P1[3] AI, ISSP CLK, I 2 C SCL, SPI MOSI, P1[1] Vss D+ DVDD AI, DATA1, I 2 C SDA, SPI CLK, P1[0] AI, P 1[2] AI, EXTCLK, P1[4] 13 14 15 16 17 18 19 20 21 22 23 24 7 8 9 10 11 12 48 47 46 45 44 43 QFN (Top View) Description OCD even data I/O OCD odd data output Page 9 of 33 [+] Feedback CY8C20336H, CY8C20446H Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C20x36H/46H PSoC devices. For the latest electrical specifications, confirm that you have the most recent data sheet by visiting the web at http://www.cypress.com/psoc. Figure 5. Voltage versus CPU Frequency 5.5V li d ng Va rati n e io Op Reg Vdd Voltage 1.71V 750 kHz 3 MHz CPU Frequency 24 MHz Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 4. Absolute Maximum Ratings Symbol TSTG Description Storage temperature Conditions Higher storage temperatures reduce data retention time. Recommended Storage Temperature is +25 °C ± 25 °C. Extended duration storage temperatures above 85 °C degrades reliability. Min –55 Typ +25 Max +125 Units °C VDD VIO VIOZ IMIO ESD LU Supply voltage relative to VSS DC input voltage DC voltage applied to tristate Maximum current into any port pin Electrostatic discharge voltage Latch up current Human body model ESD In accordance with JESD78 standard –0.5 VSS – 0.5 VSS –0.5 –25 2000 – – – – – – – +6.0 VDD + 0.5 VDD + 0.5 +50 – 200 V V V mA V mA Operating Temperature Table 5. Operating Temperature Symbol TA TC TJ Description Ambient temperature Commercial temperature range Operational die temperature The temperature rise from ambient to junction is package specific. Refer the table Thermal Impedances per Package on page 27. The user must limit the power consumption to comply with this requirement. Conditions Min –40 0 Typ – – Max +85 70 Units °C °C –40 – +100 °C Document Number: 001-56223 Rev. *C Page 10 of 33 [+] Feedback CY8C20336H, CY8C20446H DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 6. DC Chip-Level Specifications Symbol VDD [13] Description Supply voltage Supply current, IMO = 24 MHz Conditions Refer the table DC POR and LVD Specifications on page 16 Conditions are VDD ≤ 3.0 V, TA = 25 °C, CPU = 24 MHz. CapSense running at 12 MHz, no I/O sourcing current Conditions are VDD ≤ 3.0 V, TA = 25 °C, CPU = 12 MHz. CapSense running at 12 MHz, no I/O sourcing current Conditions are VDD ≤ 3.0 V, TA = 25 °C, CPU = 6 MHz. CapSense running at 6 MHz, no I/O sourcing current VDD ≤ 3.0 V, TA = 25 °C, I/O regulator turned off VDD ≤ 3.0 V, TA = 25 °C, I/O regulator turned off Min 1.71 – Typ – 3.32 Max 5.50 4.00 Units V mA IDD24 IDD12 Supply current, IMO = 12 MHz – 1.86 2.60 mA IDD6 Supply current, IMO = 6 MHz – 1.13 1.80 mA ISB0 ISB1 Deep sleep current Standby current with POR, LVD, and sleep timer – – 0.10 1.07 0.50 1.50 μA μA Note 13. When VDD remains in the range from 1.71 V to 1.9 V for more than 50 µsec, the slew rate when moving from the 1.71 V to 1.9 V range to greater than 2 V must be slower than 1 V/500 usec to avoid triggering POR. The only other restriction on slew rates for any other voltage range or transition is the SRPOWER_UP parameter. Document Number: 001-56223 Rev. *C Page 11 of 33 [+] Feedback CY8C20336H, CY8C20446H DC General Purpose I/O Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 V to 5.5 V and –40 °C ≤ TA ≤ 85°C, 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, or 1.71 V to 2.4 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 7. 3.0 V to 5.5 V DC GPIO Specifications Symbol RPU VOH1 VOH2 VOH3 Description Pull-up resistor High output voltage port 2 or 3 pins High output voltage port 2 or 3 pins High output voltage port 0 or 1 pins with LDO regulator disabled for port 1 High output voltage port 0 or 1 pins with LDO regulator disabled for port 1 High output voltage port 1 pins with LDO regulator enabled for 3 V out High output voltage port 1 pins with LDO regulator enabled for 3 V out IOH < 10 μA, maximum of 10 mA source current in all I/Os IOH = 1 mA, maximum of 20 mA source current in all I/Os IOH < 10 μA, maximum of 10 mA source current in all I/Os IOH = 5 mA, maximum of 20 mA source current in all I/Os IOH < 10 μA, VDD > 3.1 V, maximum of 4 I/Os all sourcing 5 mA IOH = 5 mA, VDD > 3.1 V, maximum of 20 mA source current in all I/Os Conditions Min 4 VDD – 0.20 VDD – 0.90 VDD – 0.20 Typ 5.60 – – – Max 8 – – – Units kΩ V V V VOH4 VDD – 0.90 – – V VOH5 2.85 3.00 3.30 V VOH6 2.20 – – V VOH7 High output voltage IOH < 10 μA, VDD > 2.7 V, maximum of port 1 pins with LDO enabled for 2.5 V 20 mA source current in all I/Os out IOH = 2 mA, VDD > 2.7 V, maximum of High output voltage port 1 pins with LDO enabled for 2.5 V 20 mA source current in all I/Os out High output voltage IOH < 10 μA, VDD > 2.7 V, maximum of port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os out High output voltage IOH = 1 mA, VDD > 2.7 V, maximum of port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os out Low output voltage IOL = 25 mA, VDD > 3.3 V, maximum of 60 mA sink current on even port pins (for example, P0[2] and P1[4]) and 60 mA sink current on odd port pins (for example, P0[3] and P1[5]) 2.35 2.50 2.75 V VOH8 1.90 – – V VOH9 1.60 1.80 2.10 V VOH10 1.20 – – V VOL – – 0.75 V VIL VIH VH IIL CPIN Input low voltage Input high voltage Input hysteresis voltage Input leakage (absolute value) Pin capacitance Package and pin dependent Temp = 25 °C – 2.00 – – 0.50 – – 80 0.001 1.70 0.80 – – 1 7 V V mV μA pF Document Number: 001-56223 Rev. *C Page 12 of 33 [+] Feedback CY8C20336H, CY8C20446H Table 8. 2.4 V to 3.0 V DC GPIO Specifications Symbol RPU VOH1 VOH2 VOH3 Description Pull-up resistor High output voltage port 2 or 3 pins High output voltage port 2 or 3 pins High output voltage port 0 or 1 pins with LDO regulator disabled for port 1 High output voltage port 0 or 1 pins with LDO regulator disabled for port 1 Conditions Min 4 IOH < 10 μA, maximum of 10 mA source VDD – 0.20 current in all I/Os IOH = 0.2 mA, maximum of 10 mA source current in all I/Os VDD – 0.40 Typ 5.60 – – – Max 8 – – – Units kΩ V V V IOH < 10 μA, maximum of 10 mA source VDD – 0.20 current in all I/Os IOH = 2 mA, maximum of 10 mA source VDD – 0.50 current in all I/Os 1.50 VOH4 – – V VOH5A High output voltage IOH < 10 μA, VDD > 2.4 V, maximum of port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os out High output voltage IOH = 1 mA, VDD > 2.4 V, maximum of port 1 pins with LDO enabled for 1.8 V 20 mA source current in all I/Os out Low output voltage IOL = 10 mA, maximum of 30 mA sink current on even port pins (for example, P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5]) 1.80 2.10 V VOH6A 1.20 – – V VOL – – 0.75 V VIL VIH VH IIL CPIN Input low voltage Input high voltage Input hysteresis voltage Input leakage (absolute value) Capacitive load on pins Package and pin dependent Temp = 25 °C – 1.40 – – 0.50 – – 80 1 1.70 0.72 – – 1000 7 V V mV nA pF Table 9. 1.71 V to 2.4 V DC GPIO Specifications Symbol RPU VOH1 VOH2 VOH3 Description Pull-up resistor High output voltage port 2 or 3 pins High output voltage port 2 or 3 pins High output voltage port 0 or 1 pins with LDO regulator disabled for port 1 High output voltage port 0 or 1 pins with LDO regulator disabled for port 1 Low output voltage Conditions Min 4 IOH = 10 μA, maximum of 10 mA source VDD – 0.20 current in all I/Os IOH = 0.5 mA, maximum of 10 mA source current in all I/Os IOH = 100 μA, maximum of 10 mA source current in all I/Os VDD – 0.50 VDD – 0.20 Typ 5.60 – – – Max 8 – – – Units kΩ V V V VOH4 IOH = 2 mA, maximum of 10 mA source VDD – 0.50 current in all I/Os IOL = 5 mA, maximum of 20 mA sink current on even port pins (for example, P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5]) – – – V VOL – 0.40 V VIL VIH Input low voltage Input high voltage – 0.65 × VDD – – 0.30 × VDD – V V Document Number: 001-56223 Rev. *C Page 13 of 33 [+] Feedback CY8C20336H, CY8C20446H Table 9. 1.71 V to 2.4 V DC GPIO Specifications (continued) Symbol VH IIL CPIN Description Input hysteresis voltage Input leakage (absolute value) Capacitive load on pins Package and pin dependent Temp = 25 °C Conditions Min – – 0.50 Typ 80 1 1.70 Max – 1000 7 Units mV nA pF Table 10.DC Characteristics – USB Interface Symbol Rusbi Rusba Vohusb Volusb Vdi Vcm Vse Cin Iio Rps2 Rext Description USB D+ pull-up resistance USB D+ pull-up resistance Static output high Static output low Differential input sensitivity Differential input common mode range Single-ended receiver threshold Transceiver capacitance High-Z state data line leakage PS/2 pull-up resistance External USB series resistor In series with each USB pin On D+ or D- line With idle bus While receiving traffic Conditions Min 900 1425 2.8 – 0.2 0.8 0.8 – –10 3000 21.78 Typ – – – – – – – – – 5000 22.0 Max 1575 3090 3.6 0.3 – 2.5 2.0 50 +10 7000 22.22 Units Ω Ω V V V V V pF μA Ω Ω DC Analog Mux Bus Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 11. DC Analog Mux Bus Specifications Symbol RSW RGND Description Switch resistance to common analog bus Resistance of initialization switch to VSS Conditions Min – – Typ – – Max 800 800 Units Ω Ω The maximum pin voltage for measuring RSW and RGND is 1.8 V DC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 12. DC Comparator Specifications Symbol VLPC ILPC VOSLPC Description Conditions Min 0.0 – – Typ – 10 2.5 Max 1.8 40 30 Units V μA mV Low power comparator (LPC) common Maximum voltage limited to VDD mode LPC supply current LPC voltage offset Document Number: 001-56223 Rev. *C Page 14 of 33 [+] Feedback CY8C20336H, CY8C20446H Comparator User Module Electrical Specifications The following table lists the guaranteed maximum and minimum specifications. Unless stated otherwise, the specifications are for the entire device voltage and temperature operating range: –40 °C ≤ TA ≤ 85 °C, 1.71 V ≤ VDD ≤ 5.5 V. Table 13. Comparator User Module Electrical Specifications Symbol TCOMP Offset Current Supply voltage > 2 V Supply voltage < 2 V Description Comparator response time Conditions 50-mV overdrive Valid from 0.2 V to VDD – 0.2 V Average DC current, 50 mV overdrive Power supply rejection ratio Power supply rejection ratio Min – – – – – 0 Typ 70 2.5 20 80 40 – Max 100 30 80 – – 1.5 Units ns mV µA dB dB V PSRR Input Range ADC Electrical Specifications Table 14.ADC User Module Electrical Specifications Symbol Input VIN CIIN RIN Input voltage range Input capacitance Input resistance Equivalent switched cap input resistance for 8-, 9-, or 10-bit resolution 0 – 1/(500fF × data clock) – – 1/(400fF × data clock) VREFADC 5 1/(300fF × data clock) V pF Ω Description Conditions Min Typ Max Units Reference VREFADC Conversion Rate FCLK Data clock Source is chip’s internal main oscillator. See AC Chip-Level Specifications on page 17 for accuracy Data clock set to 6 MHz. Sample Rate = 0.001/ (2^Resolution/Data clock) Data clock set to 6 MHz. Sample Rate = 0.001/ (2^Resolution/Data clock) Can be set to 8-, 9-, or 10-bit 2.25 – 6 MHz ADC reference voltage 1.14 – 1.26 V S8 8-bit sample rate – 23.43 – ksps S10 10-bit sample rate – 5.85 – ksps DC Accuracy RES DNL INL EOFFSET EGAIN Power IADC PSRR Operating current Power supply rejection ratio PSRR (VDD > 3.0 V) PSRR (VDD < 3.0 V) – – – 2.10 24 30 2.60 – – mA dB dB Resolution Differential nonlinearity Integral nonlinearity Offset error Gain error 8-bit resolution 10-bit resolution For any resolution 8 –1 –2 0 0 –5 – – – 3.20 12.80 – 10 +2 +2 19.20 76.80 +5 bits LSB LSB LSB LSB %FSR Document Number: 001-56223 Rev. *C Page 15 of 33 [+] Feedback CY8C20336H, CY8C20446H DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 15. DC POR and LVD Specifications Symbol VPOR0 VPOR1 VPOR2 VPOR3 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Description Conditions Min 1.61 – – – 2.40 2.64[14] 2.85[15] 2.95[16] 3.06 1.84 1.75[17] 4.62 Typ 1.66 2.36 2.60 2.82 2.45 2.71 2.92 3.02 3.13 1.90 1.80 4.73 Max 1.71 2.41 2.66 2.95 2.51 2.78 2.99 3.09 3.20 2.32 1.84 4.83 V Units V 1.66 V selected in PSoC Designer VDD must be greater than or equal to 1.71 V 2.36 V selected in PSoC Designer during startup, reset from the XRES pin, or reset from watchdog. 2.60 V selected in PSoC Designer 2.82 V selected in PSoC Designer 2.45 V selected in PSoC Designer 2.71 V selected in PSoC Designer 2.92 V selected in PSoC Designer 3.02 V selected in PSoC Designer 3.13 V selected in PSoC Designer 1.90 V selected in PSoC Designer 1.80 V selected in PSoC Designer 4.73 V selected in PSoC Designer DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 16. DC Programming Specifications Symbol Description VddIWRITE Supply voltage for flash write operations IDDP Supply current during programming or verify VILP Input low voltage during programming or verify VIHP Input high voltage during programming or verify Conditions Min 1.71 – – VIH Typ – 5 – – Max 5.25 25 VIL – Units V mA V V See the appropriate DC General Purpose I/O Specifications on page 12 See appropriate DC General Purpose I/O Specifications on page 12 table on pages 15 or 16 IILP Input current when applying VILP Driving internal pull-down resistor to P1[0] or P1[1] during programming or verify IIHP Input current when applying VIHP Driving internal pull-down resistor to P1[0] or P1[1] during programming or verify VOLP Output low voltage during programming or verify VOHP Output high voltage during See appropriate DC General Purpose I/O programming or verify Specifications on page 12 table on page 16. For VDD > 3 V use VOH4 in Table 5 on page 10. FlashENPB Flash write endurance Erase/write cycles per block FlashDR Flash data retention Following maximum flash write cycles; ambient temperature of 55 °C Notes 14. Always greater than 50 mV above VPPOR1 voltage for falling supply. 15. Always greater than 50 mV above VPPOR2 voltage for falling supply. 16. Always greater than 50 mV above VPPOR3 voltage for falling supply. 17. Always greater than 50 mV above VPPOR0 voltage for falling supply. – – 0.2 mA – – 1.5 mA – VOH – – VSS + 0.75 VDD V V 50,000 10 – 20 – – Years Document Number: 001-56223 Rev. *C Page 16 of 33 [+] Feedback CY8C20336H, CY8C20446H AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 17. AC Chip-Level Specifications Symbol FIMO24 FIMO12 FIMO6 FCPU F32K1 F32K_U DCIMO DCILO TXRST TXRST2 Description IMO frequency at 24-MHz setting IMO frequency at 12-MHz setting IMO frequency at 6-MHz setting CPU frequency ILO frequency ILO untrimmed frequency Duty cycle of IMO ILO duty cycle VDD slew rate during power-up After supply voltage is valid Applies after part has booted power-up[18] External reset pulse width at power-up External reset pulse width after Conditions Min 22.8 11.4 5.7 0.75 19 13 40 40 – 1 10 Typ 24 12 6.0 – 32 32 50 50 – – – Max 25.2 12.6 6.3 25.20 50 82 60 60 250 – – Units MHz MHz MHz MHz kHz kHz % % V/ms ms μs SRPOWER_UP Power supply slew rate Note 18. The minimum required XRES pulse length is longer when programming the device (see Table 23 on page 20). Document Number: 001-56223 Rev. *C Page 17 of 33 [+] Feedback CY8C20336H, CY8C20446H AC General Purpose I/O Specifications The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges. Table 18. AC GPIO Specifications Symbol FGPIO Description GPIO operating frequency Conditions Normal strong mode port 0, 1 Min 0 0 15 15 10 10 10 10 Typ – – – – – – – – Max Units 6 MHz for MHz 1.71 V Evaluation Boards. Build a PSoC Emulator into Your Board For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, refer Application Note “Debugging - Build a PSoC Emulator into Your Board - AN2323” at http://www.cypress.com/?rID2748. Ordering Information The following table lists the CY8C20336H/CY8C20446H PSoC devices' key package features and ordering codes. Table 31. PSoC Device Key Features and Ordering Information Package Ordering Code Flash (KB) SRAM (KB) CapSense Blocks Digital I/O Pins Analog Inputs[27] XRES Pin USB 24-pin (4x4x0.6mm) QFN 32 pin (5x5 x 0.6 mm) QFN 48 pin (7x7 mm) QFN (OCD)[28] CY8C20336H-24LQXI CY8C20446H-24LQXI CY8C20066A-24LTXI 8 16 32 1 2 2 1 1 1 20 28 36 20 28 36 Yes Yes Yes No No Yes Ordering Code Definitions CY 8 C 20 XX6H- SP XXX I Temperature range: Industrial Package type: LQX/LTX: QFN Pb-free Speed: 24 MHz Part number Family code Technology code: C = CMOS Marketing Code: 8 = PSoC Company ID: CY = Cypress Notes 24. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. 25. Foot kit includes surface mount feet that can be soldered to the target PCB. 26. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com. 27. Dual-function digital I/O pins also connect to the common analog mux. 28. This part is available in limited quantities for in-circuit debugging during prototype development. It is not available in production volumes. Document Number: 001-56223 Rev. *C Page 30 of 33 [+] Feedback CY8C20336H, CY8C20446H Document Conventions Acronyms Used The following table lists the acronyms that are used in this document. Acronym AC ADC API CMOS CPU DAC DC EOP FSR GPIO GUI I 2C ICE IDAC ILO IMO I/O ISSP LCD LDO LSB LVD MCU MIPS MISO MOSI MSB OCD POR PPOR PSRR PWRSYS PSoC® SLIMO SRAM SNR QFN SCL SDA SDATA SPI SS SSOP TC USB USB D+ USB DWLCSP XTAL Description alternating current analog-to-digital converter application programming interface complementary metal oxide semiconductor central processing unit digital-to-analog converter direct current end of packet full scale range general purpose input/output graphical user interface inter-integrated circuit in-circuit emulator digital analog converter current internal low speed oscillator internal main oscillator input/output in-system serial programming liquid crystal display low dropout (regulator) least-significant bit low voltage detect micro-controller unit mega instructions per second master in slave out master out slave in most-significant bit on-chip debugger power on reset precision power on reset power supply rejection ratio power system Programmable System-on-Chip slow internal main oscillator static random access memory signal to noise ratio quad flat no-lead serial I2C clock serial I2C data serial ISSP data serial peripheral interface slave select shrink small outline package test controller universal serial bus USB Data + USB Datawafer level chip scale package crystal Units of Measure Table 32 lists all the abbreviations used to measure the PSoC devices. Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal. Table 32. Units of Measure Symbol °C dB fF g Hz KB Kbit KHz Ksps kΩ MHz MΩ μA μF μH μs μW mA ms mV nA ns nV Ω pA pF pp ppm ps sps s V W Unit of Measure degree Celsius decibels femto farad gram hertz 1024 bytes 1024 bits kilohertz kilo samples per second kilohm megahertz megaohm microampere microfarad microhenry microsecond microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts watt Document Number: 001-56223 Rev. *C Page 31 of 33 [+] Feedback CY8C20336H, CY8C20446H Glossary Crosspoint connection Differential non-linearity Connection between any GPIO combination via analog multiplexer bus. Ideally, any two adjacent digital codes correspond to output analog voltages that are exactly one LSB apart. Differential non-linearity is a measure of the worst case deviation from the ideal 1 LSB step. Hold time is the time following a clock event during which the data input to a latch or flipflop must remain stable in order to guarantee that the latched data is correct. It is a serial multi-master bus used to connect low speed peripherals to MCU. It is a term describing the maximum deviation between the ideal output of a DAC/ADC and the actual output level. Current at which the latch up test is conducted according to JESD78 standard (at 125 °C) Hold time I2C Integral nonlinearity Latch up current Power supply rejection ratio (PSRR) The PSRR is defined as the ratio of the change in supply voltage to the corresponding change in output voltage of the device. Scan Setup time Signal-to-noise ratio SPI The conversion of all sensor capacitances to digital values. Period required to prepare a device, machine, process, or system for it to be ready to function. The ratio between a capacitive finger signal and system noise. Serial peripheral interface is a synchronous serial data link standard. Reference Documents ■ ■ ■ Technical reference manual for CY8C20xx6 devices In-system Serial Programming (ISSP) protocol for 20xx6 – AN2026C Host Sourced Serial Programming for 20xx6 devices – AN59389 Document Number: 001-56223 Rev. *C Page 32 of 33 [+] Feedback CY8C20336H, CY8C20446H Document History Page Document Title: CY8C20336H/CY8C20446H Haptics Enabled CapSense® Controller Document Number: 001-56223 Origin of Submission Revision ECN Description of Change Change Date ** 2787411 VZD/AESA 10/15/2009 New datasheet. *A 3016550 KEJO/KPOL 08/26/2010 Added CY8C20346H part. Updated 24-pin QFN and 32-pin QFN package diagrams. Content and format updated to match latest template. *B 3089844 JPM 11/18/10 In Table 26, modified TLOW and THIGH min values to 42. Updated TSS_HIGH min value to 50; removed max value. *C 3180479 YVA 02/23/11 Removed CY8C20346H part Changed title from CapSense Applications to Haptics Enabled CapSense Controller Updated Table 29 with Time at Maximum Temperature information Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2009-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-56223 Rev. *C Revised March 24, 2011 2 Page 33 of 33 PSoC Designer™ is a trademark and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation. Purchase of I C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback