CY8C20534-12PVXI

CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 PSoC® Programmable System-on-Chip™ PSoC® Programmable System-on-Chip™ Features ■ Low power CapSense® block ❐ Configurable capacitive sensing elements ❐ Supports combination of CapSense buttons, sliders, touchpads, and proximity sensors Powerful Harvard-architecture processor ❐ M8C processor speeds running up to 12 MHz ❐ Low power at high speed ❐ Operating voltage: 2.4 V to 5.25 V ❐ Industrial temperature range: –40 °C to +85 °C Flexible on-chip memory ❐ 8 KB flash program storage 50,000 erase/write cycles ❐ 512-Bytes SRAM data storage ❐ Partial flash updates ❐ Flexible protection modes ❐ Interrupt controller ❐ In-system serial programming (ISSP) Complete development tools ❐ Free development tool (PSoC Designer™) ❐ Full-featured, in-circuit emulator, and programmer ❐ Full-speed emulation ❐ Complex breakpoint structure ❐ 128 KB trace memory Precision, programmable clocking ❐ Internal ±5.0% 6- / 12-MHz main oscillator ❐ Internal low speed oscillator at 32 kHz for watchdog and sleep Programmable pin configurations ❐ Pull-up, high Z, open-drain, and CMOS drive modes on all GPIOs ❐ Up to 28 analog inputs on all GPIOs ❐ Configurable inputs on all GPIOs ❐ 20-mA sink current on all GPIOs ❐ Selectable, regulated digital I/O on port 1 • 3.0 V, 20 mA total port 1 source current • 5 mA strong drive mode on port 1 versatile analog mux ❐ Common internal analog bus ❐ Simultaneous connection of I/O combinations ❐ Comparator noise immunity ❐ Low-dropout voltage regulator for the analog array ■ ■ Additional system resources ❐ Configurable communication speeds • I2C: selectable to 50 kHz, 100 kHz, or 400 kHz • SPI: configurable between 46.9 kHz and 3 MHz 2 ❐ I C slave ❐ SPI master and SPI slave ❐ Watchdog and sleep timers ❐ Internal voltage reference ❐ Integrated supervisory circuit ■ Logic Block Diagram Port 3 Port 2 Port 1 Port 0 Config LDO PSoC CORE System Bus ■ Global Analog Interconnect SRAM 512 Bytes Interrupt Controller SROM Flash 8K Sleep and Watchdog CPU Core (M8C) ■ 6/12 MHz Internal Main Oscillator ■ ANALOG SYSTEM CapSense Block Analog Ref. I2C Slave/SPI Master-Slave POR and LVD System Resets Analog Mux SYSTEM RESOURCES Cypress Semiconductor Corporation Document Number: 001-05356 Rev. *N • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 16, 2011 [+] Feedback CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 Contents PSoC® Programmable System-on-Chip™ ..................... 1 Features ............................................................................. 1 Logic Block Diagram ........................................................ 1 PSoC Functional Overview .............................................. 3 PSoC Core .................................................................. 3 CapSense Analog System .......................................... 3 Additional System Resources ..................................... 3 PSoC Device Characteristics ...................................... 4 Getting Started .................................................................. 4 Application Notes ........................................................ 4 Development Kits ........................................................ 4 Training ....................................................................... 4 Cypros Consultants ..................................................... 4 Solutions Library .......................................................... 4 Technical Support ....................................................... 4 Development Tools .......................................................... 5 PSoC Designer Software Subsystems ........................ 5 In-Circuit Emulator ....................................................... 5 Designing with PSoC Designer ....................................... 6 Select Components ..................................................... 6 Configure Components ............................................... 6 Organize and Connect ................................................ 6 Generate, Verify, and Debug ....................................... 6 Pin Information ................................................................. 7 8-Pin SOIC Pinout ....................................................... 7 16-Pin SOIC Pinout ..................................................... 8 48-Pin OCD Part Pinout .............................................. 9 16-Pin Part Pinout ..................................................... 11 24-Pin Part Pinout ..................................................... 12 32-Pin Part Pinout ..................................................... 13 28-Pin Part Pinout ..................................................... 15 30-Ball Part Pinout .................................................... 16 Electrical Specifications ................................................ 17 Absolute Maximum Ratings ....................................... 17 Operating Temperature ............................................. 18 DC Electrical Characteristics ..................................... 18 AC Electrical Characteristics ........................................ 23 Packaging Dimensions .................................................. 30 Thermal Impedances ................................................. 35 Solder Reflow Peak Temperature ............................. 35 Development Tool Selection ......................................... 36 Software .................................................................... 36 Development Kits ...................................................... 36 Evaluation Tools ............................................................. 36 Device Programmers ................................................. 37 Accessories (Emulation and Programming) .............. 37 Ordering Information ...................................................... 38 Ordering Code Definitions ............................................. 38 Acronyms ........................................................................ 39 Acronyms Used ......................................................... 39 Reference Documents .................................................... 39 Document Conventions ................................................. 40 Units of Measure ....................................................... 40 Numeric Conventions ................................................ 40 Glossary .......................................................................... 40 Document History Page ................................................. 45 Sales, Solutions, and Legal Information ...................... 47 Worldwide Sales and Design Support ....................... 47 Products .................................................................... 47 PSoC Solutions ......................................................... 47 Document Number: 001-05356 Rev. *N Page 2 of 47 [+] Feedback CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 PSoC Functional Overview The PSoC family consists of many Programmable System-on-Chips with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU based system components with one low cost single chip programmable component. A PSoC device includes configurable analog and digital blocks and programmable interconnect. This architecture enables the user to create customized peripheral configurations to match the requirements of each individual application. Additionally, a fast CPU, flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. The PSoC architecture for this device family, as shown in Figure 1, consists of three main areas: the Core, the System Resources, and the CapSense Analog System. A common versatile bus enables connection between I/O and the analog system. Each CY8C20x34 PSoC device includes a dedicated CapSense block that provides sensing and scanning control circuitry for capacitive sensing applications. Depending on the PSoC package, up to 28 general purpose I/O (GPIO) are also included. The GPIO provide access to the MCU and analog mux. Figure 1. Analog System Block Diagram ID AC Analog Global Bus Vr R eferenc e Buffer C internal C om parator Mux Mux PSoC Core The PSoC Core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, IMO , and ILO. The CPU core, called the M8C, is a powerful processor with speeds up to 12 MHz. The M8C is a two MIPS, 8-bit Harvard-architecture microprocessor. System Resources provide additional capability such as a configurable I2C slave or SPI master-slave communication interface and various system resets supported by the M8C. The Analog System consists of the CapSense PSoC block and an internal 1.8 V analog reference. Together they support capacitive sensing of up to 28 inputs. R efs C ap Sens e C ounters C SC LK IMO C apSens e C lock Selec t R elaxation O s c illator (RO) CapSense Analog System The Analog System contains the capacitive sensing hardware. Several hardware algorithms are supported. This hardware performs capacitive sensing and scanning without requiring external components. Capacitive sensing is configurable on each GPIO pin. Scanning of enabled CapSense pins is completed quickly and easily across multiple ports. Analog Multiplexer System The Analog Mux Bus connects to every GPIO pin. Pins are connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with the CapSense block comparator. Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include: ■ ■ ■ Complex capacitive sensing interfaces such as sliders and touch pads Chip-wide mux that enables analog input from any I/O pin Crosspoint connection between any I/O pin combinations Document Number: 001-05356 Rev. *N Page 3 of 47 [+] Feedback CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 Additional System Resources System Resources provide additional capability useful to complete systems. Additional resources include low voltage detection and power on reset. Brief statements describing the merits of each system resource follow: ■ ■ Low voltage detection (LVD) interrupts signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.8 V reference provides an absolute reference for capacitive sensing. The 5 V maximum input, 3 V fixed output, low dropout regulator (LDO) provides regulation for I/Os. A register controlled bypass mode enables the user to disable the LDO. The I2C slave or SPI master-slave module provides 50/100/400 kHz communication over two wires. SPI communication over three or four wires run at speeds of 46.9 kHz to 3 MHz (lower for a slower system clock). ■ ■ PSoC Device Characteristics Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks, and 12, 6, or 4 analog blocks. Table 1 lists the resources available for specific PSoC device groups. The PSoC device covered by this datasheet is highlighted. Table 1. PSoC Device Characteristics PSoC Part Number CY8C29x66 CY8C28xxx CY8C27x43 CY8C24x94 CY8C24x23A CY8C23x33 CY8C22x45 CY8C21x45 CY8C21x34 CY8C21x23 CY8C20x34 CY8C20xx6 Digital I/O up to 64 up to 44 up to 44 up to 56 up to 24 up to 26 up to 38 up to 24 up to 28 up to 16 up to 28 up to 36 Digital Rows 4 up to 3 2 1 1 1 2 1 1 1 0 0 Digital Blocks 16 up to 12 8 4 4 4 8 4 4 4 0 0 Analog Inputs up to 12 up to 44 up to 12 up to 48 up to 12 up to 12 up to 38 up to 24 up to 28 up to 8 up to 28 up to 36 Analog Outputs 4 up to 4 4 2 2 2 0 0 0 0 0 0 Analog Columns 4 up to 6 4 2 2 2 4 4 2 2 0 0 Analog Blocks 12 up to 12 + 4[1] 12 6 6 4 6[1] 6[1] 4 [1] SRAM Size 2K 1K 256 1K 256 256 1K 512 512 256 512 up to 2K Flash Size 32 K 16 K 16 K 16 K 4K 8K 16 K 8K 8K 4K 8K up to 32 K 4[1] 3[1,2] 3[1,2] Getting Started The quickest way to understand PSoC silicon is to read this datasheet and then use the PSoC Designer Integrated Development Environment (IDE). This datasheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in depth information, along with detailed programming information, see the Technical Reference Manual for this PSoC device. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device datasheets on the web at http://www.cypress.com. Development Kits PSoC Development Kits are available online from Cypress at http://www.cypress.com and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Training Free PSoC technical training (on demand, webinars, and workshops) is available online at http://www.cypress.com. The training covers a wide variety of topics and skill levels to assist you in your designs. Application Notes Application notes are an excellent introduction to the wide variety of possible PSoC designs and are available at http://www.cypress.com. Notes 1. Limited analog functionality 2. Two analog blocks and one CapSense®. Cypros Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant, go to http://www.cypress.com and refer to CYPros Consultants. Document Number: 001-05356 Rev. *N Page 4 of 47 [+] Feedback CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 Solutions Library Visit our growing library of solution focused designs at http://www.cypress.com. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Technical Support For assistance with technical issues, search KnowledgeBase articles and forums at http://www.cypress.com. If you cannot find an answer to your question, call technical support at 1-800-541-4736. Development Tools PSoC Designer is a Microsoft® Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE runs on Windows XP or Windows Vista. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built-in support for third-party assemblers and C compilers. PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family. Code Generation Tools PSoC Designer supports multiple third party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours. Assemblers. The assemblers enable assembly code to merge seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products enable you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands enable the designer to read and program and read and write data memory, read and write I/O registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also enables the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. PSoC Designer Software Subsystems System-Level View A drag-and-drop visual embedded system design environment based on PSoC Express. In the system level view you create a model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state based upon any or all other system devices. Based upon the design, PSoC Designer automatically selects one or more PSoC Mixed-Signal Controllers that match your system requirements. PSoC Designer generates all embedded code, then compiles and links it into a programming file for a specific PSoC device. Chip-Level View The chip-level view is a more traditional integrated development environment (IDE). Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration enables changing configurations at run time. Hybrid Designs You can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. All views of the project share a common code editor, builder, and common debug, emulation, and programming tools. In-Circuit Emulator A low cost, high functionality In-Circuit Emulator (ICE) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24 MHz) operation. Document Number: 001-05356 Rev. *N Page 5 of 47 [+] Feedback CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process can be summarized in the following four steps: 1. Select components 2. Configure components 3. Organize and Connect 4. Generate, Verify, and Debug Organize and Connect You can build signal chains at the chip level by interconnecting user modules to each other and the I/O pins, or connect system level inputs, outputs, and communication interfaces to each other with valuator functions. In the system-level view, selecting a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects, places, routes, and configures a programmable gain amplifier (PGA) to buffer the input from the potentiometer, an analog to digital converter (ADC) to convert the potentiometer’s output to a digital signal, and a PWM to control the fan. In the chip-level view, perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources. Select Components Both the system-level and chip-level views provide a library of prebuilt, pretested hardware peripheral components. In the system-level view, these components are called “drivers” and correspond to inputs (a thermistor, for example), outputs (a brushless DC fan, for example), communication interfaces (I2C-bus, for example), and the logic to control how they interact with one another (called valuators). In the chip-level view, the components are called “user modules”. User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, perform the “Generate Application” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. Both system-level and chip-level designs generate software based on your design. The chip-level design provides application programming interfaces (APIs) with high level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed. The system-level design also generates a C main() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code. A complete code development environment allows you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the ICE where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. Configure Components Each of the components you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that enable you to tailor their precise configuration to your particular application. For example, a PWM User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. Both the system-level drivers and chip-level user modules are documented in datasheets that are viewed directly in PSoC Designer. These datasheets explain the internal operation of the component and provide performance specifications. Each datasheet describes the use of each user module parameter or driver property, and other information you may need to successfully implement your design. Document Number: 001-05356 Rev. *N Page 6 of 47 [+] Feedback CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 Pin Information This section describes, lists, and illustrates the CY8C20234, CY8C20334, CY8C20434, CY8C20534, and CY8C20634 PSoC device pins and pinout configurations. The CY8C20x34 PSoC device is available in a variety of packages that are listed and shown in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. However, VSS, VDD, and XRES are not capable of Digital I/O. 8-Pin SOIC Pinout Figure 2. CY8C20134-12SXI 8-Pin SOIC Pinout VSS A, I, P0[5] AI, P0[1] A, I, P0[3] AI, I2C SCL, P1[7] I2C SCL, P1[1] AI, I2C SDA, P1[5] Vss 1 8 2 7 SOIC6 3 5 4 VDD Vdd P2[2],AI A, P0[4], I P1[0], I2C SDA, DATA *, AI P0[2], A, I P1[1], I2C SCL, CLK*, AI P1[0], I2CSDA Table 2. Pin Definitions – CY8C20134 8-Pin (SOIC) Pin No. 1 2 3 4 5 6 7 I/O I/O I/O I/O I/O I/O Digital Power I I I I I I Analog VSS P0[1] P1[7] P1[5] P1[1] P1[0] P2[2] Name Ground connection Analog column mux input, integrating input I2C serial clock(SCL) I2C serial data (SDA) I2C serial clock(SCL), ISSP-SCLK I2C serial data (SDA), ISSP-SDATA Analog column mux input Supply voltage Description 8 Power VDD A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive. Document Number: 001-05356 Rev. *N Page 7 of 47 [+] Feedback CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 16-Pin SOIC Pinout Figure 3. CY8C20234-12SXI 16-Pin SOIC Pinout AI, P0[7] A, I, P0[7] AI,P0[3] A, I, P0[5] AI,P0[1] A, I, P0[3] A, I, P0[1] AI,P2[5] AI,P2[1] SMP AI, I2C SCL, SPI SS, P1[7] Vss AI, I2C SDA, SPI I2CSCL,P1[5] MISO, P1[1] AI, SPI CLK, P1[3] Vss 1 2 3 4 5 6 7 8 SOIC 16 15 14 13 12 11 10 9 VDD Vdd P0[4],AI P0[6], A, I P0[4], A, I XRES P0[2], A, I P1[4],EXTCLK,AI P1[2],AI P0[0], A, I P1[0],I2C SDA, P1[4],EXTCLK DATA*, AI P1[2] Vss P1[0], I2CSDA P1[1],I2C SCL, SPI MOSI, CLK*,AL Table 3. Pin Definitions – CY8C20234 16-Pin (SOIC) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I/O I/O I/O I/O I/O I/O I/O I/O I/O Power I/O I/O I/O I/O I/O Power I I I I I Digital I I I I I I I I I Analog Name P0[7] P0[3] P0[1] P2[5] P2[1] P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] XRES P0[4] VDD Analog column mux input Analog column mux input and column input, integrating input Analog column mux input, integrating input Analog column mux input Analog column mux input I2C serial clock(SCL),SPI SS I2C serial data (SDA),SPI MISO Analog column mux input,SPI CLK I2C serial clock(SCL), ISSP-SCLK,SPI MOSI Ground connection I2C serial data (SDA), ISSP-SDATA Analog column mux input Analog column mux input ,optional external clock input(EXTCLK) XRES Analog column mux input Supply voltage Description A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive. Document Number: 001-05356 Rev. *N Page 8 of 47 [+] Feedback CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 48-Pin OCD Part Pinout The 48-Pin QFN part table and pin diagram is for the CY8C20000 On-Chip Debug (OCD) PSoC device. This part is only used for in-circuit debugging. It is NOT available for production. Figure 4. CY8C20000 48-Pin OCD PSoC Device NC Vss P0[3], AI P0[5], AI P0[7], AI P0[6], AI NC 39 OCDO Vdd OCDE NC 38 NC 37 36 35 34 33 32 31 30 29 28 27 26 25 P0[4], P0[2], P0[0], P2[6], P2[4], P2[2], 48 47 46 45 44 43 13 14 15 16 17 18 19 20 21 CCLK AI, CLK*, I2C SCL, SPI MOSI, P1[1] Vss HCLK AI, DATA*, I2C SDA, P1[0] AI, SPI CLK, P1[3] AI, P1[2] NC NC NC Table 4. Pin Definitions – CY8C20000 48-Pin OCD (QFN) [4] Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IOH IOH Power I I I/O I/O I/O I/O I/O I/O I/O IOH IOH I/O I I I I I I I I I I Digital Analog NC P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] P1[7] P1[5] P0[1] NC NC NC NC P1[3] P1[1] VSS CCLK HCLK No connection No Connection No Connection SPI CLK CLK[3], I2C SCL, SPI MOSI Ground connection OCD CPU clock output OCD high speed clock output DATA[3], I2C SDA I2C SCL, SPI SS I2C SDA, SPI MISO Name No connection Description Document Number: 001-05356 Rev. *N NC NC 22 23 24 NC AI, P0[1] AI, P2[7] AI, P2[5] AI, P2[3] AI, P2[1] AI, P3[3] AI, P3[1] AI, I2C SCL, SPI SS, P1[7] AI, I2C SDA, SPI MISO, P1[5] NC NC 42 41 40 1 2 3 4 5 6 7 8 9 10 11 12 OCD QFN AI AI AI AI AI AI P2[0], AI P3[2], AI P3[0], AI XRES P1[6], AI P1[4], EXTCLK, AI Page 9 of 47 [+] Feedback CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 Table 4. Pin Definitions – CY8C20000 48-Pin OCD (QFN) [4] Pin No. 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 CP Power I/O I/O I/O Power I I I I/O Power I IOH IOH Input I/O I/O I/O I/O I/O I/O I/O I/O I I I I I I I I I I IOH IOH Digital I I Analog Name P1[0] P1[2] NC NC NC P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] NC NC NC P0[6] VDD OCDO OCDE P0[7] P0[5] P0[3] VSS NC VSS Integrating Input Ground connection No connection Center pad is connected to ground No connection No connection No connection Analog bypass Supply voltage OCD odd data output OCD even data I/O Active high external reset with internal pull-down No connection No connection No connection Optional external clock input (EXTCLK) Description A = Analog, I = Input, O = Output, NC = No Connection H = 5 mA High Output Drive. Document Number: 001-05356 Rev. *N Page 10 of 47 [+] Feedback CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 16-Pin Part Pinout Figure 5. CY8C20234 16-Pin PSoC Device P0[1], AI AI, P2[5] AI, P2[1] AI, I2C SCL, SPI SS, P1[7] AI, I2C SDA, SPI MISO, P1[5] 1 2 3 4 P0[3], AI P0[7], AI VDD 14 13 8 12 9 P0[4], AI XRES P1[4], AI, EXTCLK P1[2], AI CLK, I2C SCL, SPI MOSI P1[1] VSS AI, DATA, I2C SDA, P1[0] Table 5. Pin Definitions – CY8C20234 16-Pin (QFN no e-pad) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type Digital I/O I/O IOH IOH IOH IOH Power IOH IOH IOH Input I/O Power I/O I/O I/O I I I I I I I I I I I I I Analog Name P2[5] P2[1] P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] XRES P0[4] VDD P0[7] P0[3] P0[1] Integrating Input Supply voltage Optional external clock input (EXTCLK) Active high external reset with internal pull-down I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK CLK[3], I2C SCL, SPI MOSI Ground connection DATA[3], I2C SDA Description A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive Note 3. These are the ISSP pins, that are not High Z at POR (Power-on-Reset). See the PSoC Technical Reference Manual for details. Document Number: 001-05356 Rev. *N AI, SPI CLK, P1[3] 5 6 7 16 15 QFN 11 (Top View)10 Page 11 of 47 [+] Feedback CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 24-Pin Part Pinout Figure 6. CY8C20334 24-Pin PSoC Device P0[1], AI AI, P2[5] AI, P2[3] AI, P2[1] AI, I2C SCL, SPI SS, P1[7] AI, I2C SDA, SPI MISO, P1[5] AI, SPI CLK, P1[3] P0[3], AI P0[5], AI P0[7], AI VDD P0[6], AI 18 17 16 15 14 13 P0[4], AI P0[2], AI P0[0], AI P2[0], AI XRES P1[6], AI Table 6. Pin Definitions – CY8C20334 24-Pin (QFN) [4] Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 CP Type Digital Analog I/O I I/O I I/O I IOH I IOH IOH IOH Power IOH IOH IOH IOH Input I/O I/O I/O I/O I/O Power I/O I/O I/O I/O Power I I I Name P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] NC VSS P1[0] P1[2] P1[4] P1[6] XRES P2[0] P0[0] P0[2] P0[4] P0[6] VDD P0[7] P0[5] P0[3] P0[1] VSS Description I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK CLK[3], I2C SCL, SPI MOSI No Connection Ground Connection DATA[3], I2C SDA Optional external clock input (EXTCLK) Active high external reset with internal pull-down I I I I I I I I I I I I I Analog bypass Supply voltage Integrating input Center pad is connected to ground A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive Document Number: 001-05356 Rev. *N AI, CLK*, I2C SCL SPI MOSI, P1[1] NC VSS AI, DATA*, I2C SDA, P1[0] AI, P1[2] AI, EXTCLK, P1[4] 7 8 9 10 11 12 1 2 QFN 3 4 (Top View) 5 6 24 23 22 21 20 19 Page 12 of 47 [+] Feedback CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 32-Pin Part Pinout Figure 7. CY8C20434 32-Pin PSoC Device Vss P0[3], AI P0[5], AI P0[7], AI Vdd P0[6], AI P0[4], AI P0[2], AI AI, P0[1] AI, P2[7] AI, P2[5] AI, P2[3] AI, P2[1] AI, P3[3] AI, P3[1] SPI SS, P1[7] AI, I2C SCL 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 QFN (Top View) Table 7. Pin Definitions – CY8C20434 32-Pin (QFN) [4] Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Digital I/O I/O I/O I/O I/O I/O I/O IOH IOH IOH IOH Power IOH IOH IOH IOH Input I/O I/O Type Analog I I I I I I I I I I I I I I I I I Name P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] P1[6] XRES P3[0] P3[2] Description I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK CLK[3], I2C SCL, SPI MOSI Ground Connection DATA[3], I2C SDA Optional external clock input (EXTCLK) Active high external reset with internal pull-down Note 4. The center pad on the QFN package is connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it is electrically floated and not connected to any other signal. Document Number: 001-05356 Rev. *N AI, I2C SDA, SPI MISO, P1[5] AI, SPI CLK, P1[3] AI, CLK*, I2C SCL, SPI MOSI, P1[1] Vss AI, DATA*, I2C SDA, P1[0] AI, P1[2] AI, EXTCLK, P1[4] AI, P1[6] 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 P0[0], AI P2[6], AI P2[4], AI P2[2], AI P2[0], AI P3[2], AI P3[0], AI XRES Page 13 of 47 [+] Feedback CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 Table 7. Pin Definitions – CY8C20434 32-Pin (QFN) [4] Type Name Description Digital Analog 20 I/O I P2[0] 21 I/O I P2[2] 22 I/O I P2[4] 23 I/O I P2[6] 24 I/O I P0[0] 25 I/O I P0[2] 26 I/O I P0[4] 27 I/O I P0[6] Analog bypass 28 Power VDD Supply voltage 29 I/O I P0[7] 30 I/O I P0[5] 31 I/O I P0[3] Integrating input 32 Power VSS Ground connection CP Power VSS Center pad is connected to ground A = Analog, I = Input, O = Output, OH = 5 mA high output drive. Pin No. Document Number: 001-05356 Rev. *N Page 14 of 47 [+] Feedback CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 28-Pin Part Pinout Figure 8. CY8C20534 28-Pin PSoC Device AI P0[7] AI P0[5] AI P0[3] AI P0[1] AI P2[7] AI P2[5] AI P2[3] AI P2[1] Vss AI, I2C SCL P1[7] AI, I2C SDA P1[5] AI P1[3] AI, I2C SCL P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd P0[6] AI P0[4] AI P0[2] AI P0[0] AI P2[6] AI P2[4] AI P2[2] AI P2[0] AI XRES P1[6] AI P1[4] EXTCLK, AI P1[2] AI P1[0] I2C SDA, AI Table 8. Pin Definitions – CY8C20534 28-Pin (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Digital I/O I/O I/O I/O I/O I/O I/O I/O Power I/O I/O I/O I/O Power I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O Power Type Analog I I I I I I I I I I I I I I I I I I I I I I I I Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] VSS P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD Description Analog column mux input Analog column mux input and column output Analog column mux input and column output, integrating input Analog column mux input, integrating input Direct switched capacitor block input Direct switched capacitor block input Ground connection I2C serial clock (SCL) I2C serial data (SDA) I2C serial clock (SCL), ISSP-SCLK[3] Ground connection I2C serial data (SDA), ISSP-SDATA[3] Optional external clock input (EXTCLK) Active high external reset with internal pull-down Direct switched capacitor block input Direct switched capacitor block input Analog column mux input Analog column mux input Analog column mux input Analog column mux input Supply voltage A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive. Document Number: 001-05356 Rev. *N Page 15 of 47 [+] Feedback CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 30-Ball Part Pinout Figure 9. CY8C20634 30-Ball PSoC Device 5 4 3 2 1 A B C D E F Table 9. 30-Ball Part Pinout (WLCSP) Pin No. A1 A2 A3 A4 A5 B1 B2 B3 B4 B5 C1 C2 C3 C4 C5 D1 D2 D3 D4 D5 E1 E2 E3 E4 E5 F1 F2 F3 F4 F5 Digital Power I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O IOH I/O Input IOH IOH IOH I/O Power IOH IOH IOH IOH Type Analog I I I I I I I I I I I I I I I I I I I I I I I I I I I Name VDD P0[6] P0[4] P0[3] P2[7] P0[2] P0[0] P2[6] P0[5] P0[1] P2[4] P2[2] P3[1] P0[7] P2[1] P2[0] P3[0] P3[2] P1[1] P2[3] XRES P1[6] P1[4] P1[5] P2[5] VSS P1[2] P1[0] P1[3] P1[7] Supply voltage Analog bypass Integrating input Description CLK[3], I2C SCL, SPI MOSI Active high external reset with internal pull-down Optional external clock input (EXTCLK) I2C SDA, SPI MISO Ground connection DATA[3], I2C SDA SPI CLK I2C SCL, SPI SS A = Analog, I = Input, O = Output, OH = 5 mA High Output Drive. Document Number: 001-05356 Rev. *N Page 16 of 47 [+] Feedback CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C20234, CY8C20334, CY8C20434, CY8C20534, and CY8C20634 PSoC devices. For the latest electrical specifications, check the most recent datasheet by visiting the web at http://www.cypress.com. Specifications are valid for –40 °C  TA  85 °C and TJ  100 °C as specified, except where mentioned. Refer to Table 19 on page 23 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode. Figure 10. Voltage versus CPU Frequency and IMO Frequency Trim Options 5.25 5.25 SLIMO SLIMO SLIMO Mode=1 Mode=1 Mode=0 4.75 Vdd Voltage 4.75 Vdd Voltage O lid ng Va rati n pe gio Re 3.60 3.00 2.70 2.40 750 kHz 3 MHz 6 MHz 12 MHz 3.00 2.70 2.40 750 kHz 3 MHz SLIMO SLIMO Mode=1 Mode=0 SLIMO Mode=1 SLIMO Mode=0 6 MHz 12 MHz CPU Frequency IMO Frequency Absolute Maximum Ratings Table 10. Absolute Maximum Ratings Symbol TSTG Description Storage Temperature Min –55 Typ 25 Max +100 Units °C Notes Higher storage temperatures reduces data retention time. Recommended storage temperature is +25 °C ± 25 °C. Extended duration storage temperatures above 65 °C degrades reliability. TBAKETEMP tBAKETIME TA VDD VIO VIOZ IMIO ESD LU Bake temperature Bake time Ambient temperature with power applied Supply voltage on VDD relative to VSS DC input voltage DC voltage applied to tri-state Maximum current into any port pin Electro static discharge voltage Latch-up current – See package label –40 –0.5 VSS – 0.5 VSS – 0.5 –25 2000 – 125 – – – – – – – – See package label 72 +85 +6.0 VDD + 0.5 VDD + 0.5 +50 – 200 °C Hours °C V V V mA V mA Human body model ESD. Document Number: 001-05356 Rev. *N Page 17 of 47 [+] Feedback CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 Operating Temperature Table 11. Operating Temperature Symbol TA TJ Description Ambient temperature Junction temperature Min –40 –40 Typ – – Max +85 +100 Units °C °C Notes The temperature rise from ambient to junction is package specific. See Table 16 on page 21. The user must limit the power consumption to comply with this requirement. DC Electrical Characteristics DC Chip Level Specifications Table 12 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0V to 3.6V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Table 12. DC Chip Level Specifications Symbol VDD IDD12 IDD6 ISB27 ISB Description Supply voltage Supply current, IMO = 12 MHz Supply current, IMO = 6 MHz Sleep (mode) current with POR, LVD, Sleep timer, WDT, and internal slow oscillator active. Mid temperature range. Sleep (mode) current with POR, LVD, Sleep timer, WDT, and internal slow oscillator active. Min 2.40 – – – – Typ – 1.5 1 2.6 2.8 Max 5.25 2.5 1.5 4 5 Units V mA mA µA µA Notes See Table 16 on page 21. Conditions are VDD = 3.0 V, TA = 25 °C, CPU = 12 MHz. Conditions are VDD = 3.0 V, TA = 25 °C, CPU = 6 MHz VDD = 2.55 V, 0 °C TA  40 °C VDD = 3.3 V, –40 °C TA  85 °C DC GPIO Specifications Unless otherwise noted, Table 13 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, and 2.7 V at 25 °C. These are for design guidance only. Table 13. 5-V and 3.3-V DC GPIO Specifications Symbol RPU VOH1 VOH2 VOH3 VOH4 VOH5 VOH6 VOH7 VOH8 Description Pull-up resistor High output voltage Port 0, 2, or 3 pins High output voltage Port 0, 2, or 3 pins High output voltage Port 1 pins with LDO regulator disabled High output voltage Port 1 pins with LDO regulator disabled High output voltage Port 1 pins with 3.0 V LDO regulator enabled High output voltage Port 1 pins with 3.0 V LDO regulator enabled High output voltage Port 1 pins with 2.4 V LDO regulator enabled High output voltage Port 1 pins with 2.4 V LDO regulator enabled Min 4 VDD – 0.2 VDD – 0.9 VDD – 0.2 VDD – 0.9 2.7 2.2 2.1 2.0 Typ 5.6 – – – – 3.0 – 2.4 – Max 8 – – – – 3.3 – 2.7 – Units k V V V V V V V V Notes IOH  10 µA, VDD  3.0 V, maximum of 20 mA source current in all I/Os. IOH = 1 mA, VDD  3.0 V, maximum of 20 mA source current in all I/Os. IOH < 10 µA, VDD  3.0 V, maximum of 10 mA source current in all I/Os. IOH = 5 mA, VDD  3.0 V, maximum of 20 mA source current in all I/Os. IOH < 10 µA, VDD  3.1 V, maximum of 4 I/Os all sourcing 5 mA. IOH = 5 mA, VDD  3.1 V, maximum of 20 mA source current in all I/Os. IOH < 10 µA, VDD  3.0 V , maximum of 20 mA source current in all I/Os. IOH < 200 µA, VDD  3.0 V, maximum of 20 mA source current in all I/Os. Document Number: 001-05356 Rev. *N Page 18 of 47 [+] Feedback CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 Table 13. 5-V and 3.3-V DC GPIO Specifications Symbol VOH9 Description High output voltage Port 1 pins with 1.8 V LDO regulator enabled Min 1.6 Typ 1.8 Max 2.0 Units V Notes IOH < 10 µA 3.0V  VDD  3.6 V 0 °C TA 85 °C Maximum of 20 mA source current in all I/Os. IOH < 100 µA. 3.0V  VDD  3.6 V. 0 °C TA 85 °C. Maximum of 20 mA source current in all I/Os. IOL = 20 mA, VDD > 3.0 V, maximum of 60 mA sink current on even port pins (for example, P0[2] and P1[4]) and 60 mA sink current on odd port pins (for example, P0[3] and P1[5]). VOH = VDD – 0.9. See the limitations of the total current in the Notes for VOH. VOH = VDD – 0.9, for the limitations of the total current and IOH at other VOH levels, see the Notes for VOH. VOH = VDD – 0.9, for the limitations of the total current and IOH at other VOH levels, see the Notes for VOH. VOL = 0.75 V, see the limitations of the total current in the Notes for VOL 3.6 V  VDD  5.25 V 3.6 V  VDD  5.25 V Gross tested to 1 µA Package and pin dependent Temperature = 25 °C Package and pin dependent Temperature = 25 °C VOH10 High output voltage Port 1 pins with 1.8 V LDO regulator enabled 1.5 – – V VOL Low output voltage – – 0.75 V IOH IOH2 IOH4 IOL VIL VIH VH IIL CIN COUT High level source current High level source current port 0, 2, or 3 pins High level source current port 1 Pins with LDO regulator disabled Low level sink current Input low voltage Input high voltage Input hysteresis voltage Input leakage (absolute value) Capacitive load on pins as input Capacitive load on pins as output – 1 5 20 – 2.0 – – 0.5 0.5 – – – – – – 140 1 1.7 1.7 20 – – – 0.8 – – – 5 5 mA mA mA mA V V mV nA pF pF Document Number: 001-05356 Rev. *N Page 19 of 47 [+] Feedback CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 Table 14. 2.7-V DC GPIO Specifications Symbol RPU VOH1 VOH2 VOL Description Pull-up resistor High output voltage Port 1 pins with LDO regulator disabled High output voltage Port 1 pins with LDO regulator disabled Low output voltage Min 4 VDD – 0.2 VDD – 0.5 – Typ 5.6 – – – Max 8 – – 0.75 Units k V V V Notes IOH < 10 µA, maximum of 10 mA source current in all I/Os. IOH = 2 mA, maximum of 10 mA source current in all I/Os. IOL = 10 mA, maximum of 30 mA sink current on even port pins (for example, P0[2] and P1[4]) and 30 mA sink current on odd port pins (for example, P0[3] and P1[5]). VOH = VDD – 0.5, for the limitations of the total current and IOH at other VOH levels see the notes for VOH. VOH = .75 V, see the limitations of the total current in the note for VOL IOL = 5 mA Maximum of 50 mA sink current on even port pins (for example, P0[2] and P3[4]) and 50 mA sink current on odd port pins (for example, P0[3] and P2[5]). 2.4 V  VDD  3.6 V 2.4 V  VDD  3.6 V 2.4 V  VDD  2.7 V 2.7 V  VDD  3.6 V Gross tested to 1 µA Package and pin dependent Temperature = 25 °C Package and pin dependent Temperature = 25 °C IOH2 IOL VOLP1 High level source current port 1 Pins with LDO regulator disabled Low level sink current Low output voltage port 1 pins 2 10 – – – – – – 0.4 mA mA V VIL VIH1 VIH2 VH IIL CIN COUT Input low voltage Input high voltage Input high voltage Input hysteresis voltage Input leakage (absolute value) Capacitive load on pins as input Capacitive load on pins as output – 1.4 1.6 – – 0.5 0.5 – – – 60 1 1.7 1.7 0.75 – – – – 5 5 V V V mV nA pF pF DC Analog Mux Bus Specifications Table 15 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Table 15. DC Analog Mux Bus Specifications Symbol RSW Description Switch resistance to common analog bus Min – Typ – Max 400 800 Units   Notes VDD  2.7 V 2.4 V VDD 2.7 V Document Number: 001-05356 Rev. *N Page 20 of 47 [+] Feedback CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 DC POR and LVD Specifications Table 16 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Table 16. DC POR and LVD Specifications Symbol VPPOR0 VPPOR1 VPPOR2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Description VDD value for PPOR trip PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b VDD value for LVD trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min – – – 2.39 2.54 2.75 2.85 2.96 – – 4.52 Typ 2.36 2.60 2.82 2.45 2.71 2.92 3.02 3.13 – – 4.73 Max 2.40 2.65 2.95 2.51[3] 2.78[4] 2.99[5] 3.09 3.20 – – 4.83 Units V V V V V V V V V V V Notes VDD is greater than or equal to 2.5 V during startup, reset from the XRES pin, or reset from watchdog. Notes 3. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply. 4. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply. 5. Always greater than 50 mV above VPPOR (PORLEV = 10) for falling supply. 6. A maximum of 36 × 50,000 block endurance cycles is allowed. This is balanced between operations on 36 × 1 blocks of 50,000 maximum cycles each, 36 × 2 blocks of 25,000 maximum cycles each, or 36 × 4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36 × 50,000 and that no single block ever sees more than 50,000 cycles). 7. The 50,000 cycle flash endurance per block is only guaranteed if the flash is operating within one voltage range. Voltage ranges are 2.4 V to 3.0 V, 3.0 V to 3.6 V and 4.75 V to 5.25 V. Document Number: 001-05356 Rev. *N Page 21 of 47 [+] Feedback CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 DC Programming Specifications Table 17 lists the guaranteed minimum and maximum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Flash endurance and retention specifications with the use of the EEPROM User Module are valid only within the range: 25 °C +/–20C during the Flash Write operation. Reference the EEPROM User Module datasheet instructions for EEPROM flash write requirements outside of the 25 °C +/–20 °C temperature window. Table 17. DC Programming Specifications Symbol VDDP VDDLV VDDHV VDDIWRITE IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR Description VDD for programming and erase Low VDD for verify High VDD for verify Supply voltage for flash write operation Supply current during programming or verify Input low voltage during programming or verify Input high voltage during programming or verify Input current when applying VILP to P1[0] or P1[1] during programming or verify Input current when applying VIHP to P1[0] or P1[1] during programming or verify Output low voltage during programming or verify Output high voltage during programming or verify Flash endurance (per block) Flash endurance (total)[6] Flash data retention Min 4.5 2.4 5.1 2.7 – – 2.2 – – – VDD – 1.0 50,000[7] 1,800,000 10 Typ 5 2.5 5.2 – 5 – – – – – – – – – Max 5.5 2.6 5.3 5.25 25 0.8 – 0.2 1.5 VSS + 0.75 VDD – – – Units Notes V This specification applies to the functional requirements of external programmer tools V This specification applies to the functional requirements of external programmer tools V This specification applies to the functional requirements of external programmer tools V This specification applies to this device when it is executing internal flash writes mA V V mA mA V V – Erase/write cycles per block. – Erase/write cycles. Years Driving internal pull-down resistor. Driving internal pull-down resistor. DC I2C Specifications Table 18 lists the guaranteed minimum and maximum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Flash endurance and retention specifications with the use of the EEPROM user module are valid only within the range: 25 °C +/–20C during the Flash Write operation. Reference the EEPROM User Module datasheet instructions for EEPROM flash Write requirements outside of the 25 °C +/–20 °C temperature window. Table 18. DC I2C Specifications[8] Symbol VILI2C VIHI2C Description Input low level Input high level Min – – 0.7 × VDD Typ – – – Max 0.3 × VDD 0.25 × VDD – Units V V V Notes 2.4 V VDD  3.6 V 4.75 V  VDD  5.25 V 2.4 V  VDD  5.25 V Notes 8. All GPIO meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I2C GPIO pins also meet the above specs. 9. 0 to 70 °C ambient, VDD = 3.3 V. Document Number: 001-05356 Rev. *N Page 22 of 47 [+] Feedback CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 AC Electrical Characteristics AC Chip Level Specifications Table 19, Table 20, and Table 21 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Table 19. 5-V and 3.3-V AC Chip-Level Specifications Symbol FCPU1 F32K1 F32K_U Description CPU frequency (3.3 V nominal) Internal low speed oscillator frequency Internal low speed oscillator (ILO) untrimmed frequency Min 0.75 15 5 Typ – 32 – Max 12.6 64 100 Units MHz kHz kHz Notes 12 MHz only for SLIMO Mode = 0. After a reset and before the M8C starts to run, the ILO is not trimmed. See the System Resets section of the PSoC Technical Reference Manual for details on this timing. Trimmed for 3.3 V operation using factory trim values. See Figure 10 on page 17, SLIMO mode = 0. Trimmed for 3.3 V operation using factory trim values. See Figure 10 on page 17, SLIMO mode = 1. FIMO12 Internal main oscillator stability for 12 MHz (commercial temperature)[9] Internal main oscillator stability for 6 MHz (commercial temperature) Duty cycle of IMO Internal low speed oscillator duty cycle External reset pulse width Time from end of POR to CPU executing code 11.4 12 12.6 MHz FIMO6 5.5 6.0 6.5 MHz DCIMO DCILO tXRST tPOWERUP 40 20 10 – – – – – 50 50 – 16 – 200 600 100 60 80 – 100 250 1600 1400 900 % % s ms V/ms ps ps ps Power-up from 0 V. See the System Resets section of the PSoC Technical Reference Manual. SRPOWER_UP Power supply slew rate tjit_IMO [11] 12 MHz IMO cycle-to-cycle jitter (RMS) 12 MHz IMO long term N cycle-to-cycle jitter (RMS) 12 MHz IMO period jitter (RMS) N = 32 Document Number: 001-05356 Rev. *N Page 23 of 47 [+] Feedback CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 Table 20. 2.7-V AC Chip Level Specifications Symbol FCPU1 F32K1 F32K_U Description CPU Frequency (2.7 V nominal) Internal low speed oscillator frequency Internal low speed oscillator (ILO) untrimmed frequency Min 0.75 8 5 Typ – 32 – Max 3.25 96 100 Units MHz kHz kHz Notes SLIMO mode = 0 After a reset and before the M8C starts to run, the ILO is not trimmed. See the System Resets section of the PSoC Technical Reference Manual for details on this timing. Trimmed for 2.7 V operation using factory trim values. See Figure 10 on page 17, SLIMO mode = 0. Trimmed for 2.7 V operation using factory trim values. See Figure 10 on page 17, SLIMO mode = 1. FIMO12 IMO stability for 12 MHz (commercial temperature)[10] IMO stability for 6 MHz (commercial temperature) Duty cycle of IMO Internal low speed oscillator duty cycle External reset pulse width Time from end of POR to CPU executing code Power supply slew rate 12 MHz IMO cycle-to-cycle jitter (RMS) 12 MHz IMO long term N cycle-to-cycle jitter (RMS) 12 MHz IMO period jitter (RMS) 11.0 12 12.9 MHz FIMO6 5.5 6.0 6.5 MHz DCIMO DCILO tXRST tPOWERUP SRPOWER_UP tjit_IMO [11] 40 20 10 – – – – – 50 50 – 16 – 500 800 300 60 80 – 100 250 900 1400 500 % % µs ms V/ms ps ps ps Power-up from 0 V. See the System Resets section of the PSoC Technical Reference Manual N = 32 Notes 10. 0 °C to 70 °C ambient, VDD = 3.3 V. 11. Refer to Cypress Jitter Specifications Application Note – AN5054 at http://www.cypress.com for more information. Document Number: 001-05356 Rev. *N Page 24 of 47 [+] Feedback CY8C20134, CY8C20234, CY8C20334 CY8C20434, CY8C20534, CY8C20634 AC GPIO Specifications Table 21 and Table 22 list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Table 21. 5-V and 3.3-V AC GPIO Specifications Symbol FGPIO tRise023 tRise1 tFall Description GPIO operating frequency Rise time, strong mode, Cload = 50 pF ports 0, 2, 3 Rise time, strong mode, Cload = 50 pF port 1 Fall time, strong mode, Cload = 50 pF all ports Min 0 15 10 10 Typ – – – – Max 6 80 50 50 Units MHz ns ns ns Notes Normal strong mode, port 1. VDD = 3.0 to 3.6 V and 4.75 V to 5.25 V, 10% to 90% VDD = 3.0 V to 3.6 V, 10% to 90% VDD = 3.0 V to 3.6 V and 4.75 V to 5.25 V, 10% to 90% Table 22. 2.7-V AC GPIO Specifications Symbol FGPIO tRise023 tRise1 tFall Description GPIO operating frequency Rise time, strong mode, Cload = 50 pF ports 0, 2, 3 Rise time, strong mode, Cload = 50 pF port 1 Fall time, strong mode, Cload = 50 pF all Ports Min 0 15 10 10 Typ – – – – Max 1.5 100 70 70 Units MHz ns ns ns Notes Normal strong mode, port 1. VDD = 2.4 V to 3.0 V, 10% to 90% VDD = 2.4 V to 3.0 V, 10% to 90% VDD = 2.4 V to 3.0 V, 10% to 90% Figure 11. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRise023 TRise1 TFall AC Comparator Specifications Table 23 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C  TA  85 °C, 3.0 V to 3.6 V and –40 °C  TA  85 °C, or 2.4 V to 3.0 V and –40 °C  TA  85 °C, respectively. Typical parameters apply to 5 V, 3.3 V, or 2.7 V at 25 °C. These are for design guidance only. Table 23. AC Comparator Specifications Symbol tCOMP Description Comparator response time, 50 mV overdrive Min – Typ – Max 100 200 Units ns ns Notes VDD  3.0 V. 2.4 V < VCC