PSoC CY8C20x34 TRM
PSoC® CY8C20x34 PSoC® CY8C20x24
Technical Reference Manual (TRM)
Document No. 001-13033 Rev. *A
Cypress Semiconductor 198 Champion Court San Jose, CA 95134-1709 Phone (USA): 800.858.1810 Phone (Intnl): 408.943.2600 http://www.cypress.com
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Copyrights
Copyrights Copyright © 2006-2008 Cypress Semiconductor Corporation. All rights reserved. PSoC® is a registered trademark and CapSense™, PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks of Cypress Semiconductor Corporation (Cypress), along with Cypress® and Cypress Semiconductor™. All other trademarks or registered trademarks referenced herein are the property of their respective owners. The information in this document is subject to change without notice and should not be construed as a commitment by Cypress. While reasonable precautions have been taken, Cypress assumes no responsibility for any errors that may appear in this document. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of Cypress. Made in the U.S.A. Disclaimer Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PSoC Device and User Module Data Sheets contain performance specifications and characterizations for critical parameters. Cypress Semiconductor does not recommend that you use unspecified or uncharacterized functions. If you need a device feature that is not completely specified or characterized, contact the Cypress PSoC Marketing organization through the support web site at http://www.cypress.com/support Use may be limited by and subject to the applicable Cypress software license agreement. Flash Code Protection Note the following details of the Flash code protection features on Cypress devices. Cypress products meet the specifications contained in their particular Cypress Data Sheets. Cypress believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress are committed to continuously improving the code protection features of our products.
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Contents Overview
Section A: Overview
1. 2. 3. 4. 5. 6. 7. 8. 9.
13 23
Pin Information .................................................................................................................... 19 CPU Core (M8C) ................................................................................................................. 25 RAM Paging ........................................................................................................................ 31 Supervisory ROM (SROM) ................................................................................................... 37 Interrupt Controller .............................................................................................................. 45 General Purpose IO (GPIO) ................................................................................................. 51 Internal Main Oscillator (IMO) .............................................................................................. 57 Internal Low Speed Oscillator (ILO) ..................................................................................... 59 Sleep and Watchdog ........................................................................................................... 61
Section B: PSoC Core
Section C: CapSense System
69
10. CapSense Module ............................................................................................................... 71 11. IO Analog Multiplexer .......................................................................................................... 81 12. Comparators ....................................................................................................................... 83
Section D: System Resources
13. 14. 15. 16. 17. 18. 19.
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Digital Clocks ...................................................................................................................... 89 I2C Slave ........................................................................................................................... 95 Internal Voltage References .............................................................................................. 105 System Resets .................................................................................................................. 107 POR and LVD .................................................................................................................... 113 Serial Peripheral Interface ................................................................................................. 115 Programmable Timer ......................................................................................................... 129
Section E: Registers Section F: Glossary Index
133 195 211
20. Register Reference ........................................................................................................... 137
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Contents
Section A: Overview
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Document Organization ......................................................................................................................13 Top-Level Architecture .........................................................................................................................14 PSoC Core ..............................................................................................................................14 CapSense System ..................................................................................................................14 System Resources ..................................................................................................................14 Getting Started ....................................................................................................................................16 Support ...................................................................................................................................16 Product Upgrades ...................................................................................................................16 Development Kits ...................................................................................................................16 Document History ................................................................................................................................16 Documentation Conventions ..............................................................................................................17 Register Conventions ............................................................................................................17 Numeric Naming ....................................................................................................................17 Units of Measure ..................................................................................................................17 Acronyms ...............................................................................................................................18 1. Pin Information .................................................................................................................. 19 1.1 Pinouts ...................................................................................................................................19 1.1.1 16-Pin Part Pinout..................................................................................................19 1.1.2 24-Pin Part Pinout ................................................................................................20 1.1.3 32-Pin Part Pinout .................................................................................................21 1.1.4 48-Pin OCD Part Pinout ........................................................................................22
Section B: PSoC Core
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Top Level Core Architecture ................................................................................................................23 Core Register Summary ......................................................................................................................24 2. CPU Core (M8C) ................................................................................................................. 25 2.1 Overview ..................................................................................................................................25 2.2 Internal Registers ..................................................................................................................25 2.3 Address Spaces .....................................................................................................................25 2.4 Instruction Set Summary..........................................................................................................26 2.5 Instruction Formats ................................................................................................................28 2.5.1 One-Byte Instructions ............................................................................................28 2.5.2 Two-Byte Instructions.............................................................................................28 2.5.3 Three-Byte Instructions..........................................................................................29 2.6 Register Definitions .................................................................................................................30 2.6.1 CPU_F Register ....................................................................................................30 2.6.2 Related Registers ..................................................................................................30 RAM Paging ....................................................................................................................... 31 3.1 Architectural Description .........................................................................................................31 3.1.1 Basic Paging .........................................................................................................31 3.1.2 Stack Operations ...................................................................................................32
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3.2
3.1.3 Interrupts ...............................................................................................................32 3.1.4 MVI Instructions .................................................................................................... 32 3.1.5 Current Page Pointer ............................................................................................ 32 3.1.6 Index Memory Page Pointer ................................................................................. 33 Register Definitions ................................................................................................................. 34 3.2.1 CUR_PP Register ................................................................................................. 34 3.2.2 STK_PP Register ................................................................................................. 34 3.2.3 IDX_PP Register .................................................................................................. 35 3.2.4 MVR_PP Register ................................................................................................ 35 3.2.5 MVW_PP Register ................................................................................................ 36 3.2.6 Related Registers .................................................................................................. 36
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Supervisory ROM (SROM) ................................................................................................. 37 4.1 Architectural Description ......................................................................................................... 37 4.1.1 Additional SROM Feature...................................................................................... 38 4.1.2 SROM Function Descriptions ............................................................................... 38 4.1.2.1 SWBootReset Function ....................................................................... 38 4.1.2.2 HWBootReset Function ....................................................................... 39 4.1.2.3 ReadBlock Function ............................................................................ 39 4.1.2.4 WriteBlock Function............................................................................. 40 4.1.2.5 EraseBlock Function............................................................................ 40 4.1.2.6 ProtectBlock Function.......................................................................... 40 4.1.2.7 TableRead Function ........................................................................... 41 4.1.2.8 EraseAll Function ................................................................................ 41 4.1.2.9 Checksum Function............................................................................. 41 4.1.2.10 Calibrate0 Function ............................................................................. 41 4.1.2.11 Calibrate1 Function ............................................................................. 42 4.1.2.12 WriteAndVerify Function...................................................................... 42 4.2 Register Definitions ................................................................................................................ 42 4.2.1 Related Registers .................................................................................................. 42 4.3 Clocking Strategy..................................................................................................................... 42 4.3.1 DELAY Parameter ................................................................................................. 42 4.3.2 CLOCK Parameter ................................................................................................ 43 Interrupt Controller ........................................................................................................... 45 5.1 Architectural Description.......................................................................................................... 45 5.1.1 Posted versus Pending Interrupts.......................................................................... 46 5.2 Application Overview ............................................................................................................... 47 5.3 Register Definitions ................................................................................................................. 48 5.3.1 INT_CLR0 Registers ............................................................................................ 48 5.3.2 INT_MSK0 Register ..............................................................................................49 5.3.3 INT_SW_EN Register ........................................................................................... 49 5.3.4 INT_VC Register .................................................................................................. 50 5.3.5 Related Registers .................................................................................................. 50 General Purpose IO (GPIO) ............................................................................................... 51 6.1 Architectural Description.......................................................................................................... 51 6.1.1 General Description ............................................................................................... 51 6.1.2 Digital IO ...............................................................................................................52 6.1.3 Analog and Digital Inputs ...................................................................................... 52 6.1.4 Port 1 Distinctions.................................................................................................. 52 6.1.5 GPIO Block Interrupts .......................................................................................... 52 6.1.5.1 Interrupt Modes ................................................................................... 54 6.1.6 Data Bypass .......................................................................................................... 54
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Register Definitions .................................................................................................................55 6.2.1 PRTxDR Registers ................................................................................................55 6.2.2 PRTxIE Registers .................................................................................................55 6.2.3 PRTxDMx Registers .............................................................................................56 6.2.4 IO_CFG Register ..................................................................................................56
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Internal Main Oscillator (IMO) ........................................................................................... 57 7.1 Architectural Description ..........................................................................................................57 7.2 Application Overview ...............................................................................................................57 7.2.1 Trimming the IMO ..................................................................................................57 7.2.2 Engaging Slow IMO ...............................................................................................57 7.3 Register Definitions .................................................................................................................58 7.3.1 IMO_TR Register ..................................................................................................58 7.3.2 Related Registers ..................................................................................................58 Internal Low Speed Oscillator (ILO) .................................................................................. 59 8.1 Architectural Description ..........................................................................................................59 8.2 Register Definitions .................................................................................................................59 8.2.1 ILO_TR Register ...................................................................................................59 Sleep and Watchdog.......................................................................................................... 61 9.1 Architectural Description ..........................................................................................................61 9.1.1 Sleep Timer .........................................................................................................61 9.2 Application Overview ...............................................................................................................62 9.3 Register Definitions .................................................................................................................63 9.3.1 RES_WDT Register ..............................................................................................63 9.3.2 SLP_CFG Register ...............................................................................................63 9.3.3 Related Registers ..................................................................................................63 9.4 Timing Diagrams ......................................................................................................................64 9.4.1 Sleep Sequence.....................................................................................................64 9.4.2 Wakeup Sequence.................................................................................................65 9.4.3 Bandgap Refresh ...................................................................................................66 9.4.4 Watchdog Timer.....................................................................................................66 9.5 Power Modes ...........................................................................................................................67
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Section C: CapSense System
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Top Level CapSense Architecture .......................................................................................................69 CapSense Register Summary .............................................................................................................70 10. CapSense Module .............................................................................................................. 71 10.1 Architectural Description ..........................................................................................................71 10.1.1 Types of CapSense Approaches ...........................................................................71 10.1.1.1 Relaxation Oscillator............................................................................71 10.1.1.2 IDAC ....................................................................................................72 10.1.2 CapSense Counter ................................................................................................72 10.1.3 Timer ......................................................................................................................73 10.1.3.1 Operation .............................................................................................73 10.2 Register Definitions .................................................................................................................74 10.2.1 CS_CR0 Register .................................................................................................74 10.2.2 CS_CR1 Register .................................................................................................75 10.2.3 CS_CR2 Register .................................................................................................75 10.2.4 CS_CR3 Register .................................................................................................76 10.2.5 CS_CNTL Register ...............................................................................................76 10.2.6 CS_CNTH Register ...............................................................................................76 10.2.7 CS_STAT Register ................................................................................................77
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10.2.8 CS_TIMER Register ............................................................................................. 77 10.2.9 CS_SLEW Register ..............................................................................................78 10.2.10 IDAC_D Register .................................................................................................. 78 Timing Diagrams...................................................................................................................... 79
11. IO Analog Multiplexer ....................................................................................................... 81 11.1 Architectural Description ......................................................................................................... 81 11.2 Application Overview ............................................................................................................... 81 11.3 Register Definitions ................................................................................................................. 82 11.3.1 AMUX_CFG Register ........................................................................................... 82 11.3.2 MUX_CRx Registers ............................................................................................ 82 12. Comparators ..................................................................................................................... 83 12.1 Architectural Description ......................................................................................................... 83 12.2 Register Definitions ................................................................................................................. 84 12.2.1 CMP_RDC Register ............................................................................................. 84 12.2.2 CMP_MUX Register ............................................................................................. 85 12.2.3 CMP_CR0 Register ..............................................................................................85 12.2.4 CMP_CR1 Register ..............................................................................................86 12.2.5 CMP_LUT Register ..............................................................................................86
Section D: System Resources
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Top Level System Resources Architecture .......................................................................................... 87 System Resources Register Summary ................................................................................................ 88 13. Digital Clocks .................................................................................................................... 89 13.1 Architectural Description.......................................................................................................... 89 13.1.1 Internal Main Oscillator ......................................................................................... 89 13.1.2 Internal Low Speed Oscillator ............................................................................... 89 13.1.3 External Clock ...................................................................................................... 90 13.1.3.1 Switch Operation ................................................................................. 90 13.2 Register Definitions ................................................................................................................. 92 13.2.1 OUT_P1 Register ................................................................................................. 92 13.2.2 OSC_CR0 Register ............................................................................................ 93 13.2.3 OSC_CR2 Register ............................................................................................ 94 13.2.4 Related Registers .................................................................................................. 94 14. I2C Slave .......................................................................................................................... 95 14.1 Architectural Description.......................................................................................................... 95 14.1.1 Basic I2C Data Transfer ........................................................................................ 96 14.2 Application Overview ............................................................................................................... 96 14.2.1 Slave Operation .................................................................................................... 96 14.3 Register Definitions ................................................................................................................. 98 14.3.1 I2C_CFG Register ................................................................................................ 98 14.3.2 I2C_SCR Register ................................................................................................ 99 14.3.3 I2C_DR Register ................................................................................................101 14.4 Timing Diagrams....................................................................................................................101 14.4.1 Clock Generation .................................................................................................101 14.4.2 Basic IO Timing ...................................................................................................102 14.4.3 Status Timing .......................................................................................................102 14.4.4 Slave Stall Timing ...............................................................................................103
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15. Internal Voltage References ............................................................................................ 105 15.1 Architectural Description ........................................................................................................105 15.2 Register Definitions ...............................................................................................................106 15.2.1 BDG_TR Register ...............................................................................................106 16. System Resets ................................................................................................................. 107 16.1 Architectural Description ........................................................................................................107 16.2 Pin Behavior During Reset.....................................................................................................107 16.2.1 GPIO Behavior on Power Up ...............................................................................107 16.2.2 GPIO Behavior on External Reset .......................................................................108 16.3 Register Definitions ...............................................................................................................108 16.3.1 CPU_SCR1 Register ..........................................................................................108 16.3.2 CPU_SCR0 Register ..........................................................................................109 16.4 Timing Diagrams ...................................................................................................................110 16.4.1 Power On Reset ..................................................................................................110 16.4.2 External Reset ....................................................................................................110 16.4.3 Watchdog Timer Reset .......................................................................................110 16.4.4 Reset Details........................................................................................................112 16.5 Power Modes ........................................................................................................................112 17. POR and LVD ................................................................................................................... 113 17.1 Architectural Description ........................................................................................................113 17.2 Register Definitions ...............................................................................................................113 17.2.1 VLT_CR Register ................................................................................................113 17.2.2 VLT_CMP Register .............................................................................................114 18. Serial Peripheral Interface .............................................................................................. 115 18.1 Architectural Description ........................................................................................................115 18.1.1 SPI Protocol Function .........................................................................................115 18.1.1.1 SPI Protocol Signal Definitions ..........................................................116 18.1.2 SPI Master Function ...........................................................................................116 18.1.2.1 Usability Exceptions...........................................................................116 18.1.2.2 Block Interrupt....................................................................................116 18.1.3 SPI Slave Function .............................................................................................116 18.1.3.1 Usability Exceptions...........................................................................117 18.1.3.2 Block Interrupt....................................................................................117 18.1.4 Input Synchronization ..........................................................................................117 18.2 Register Definitions ...............................................................................................................117 18.2.1 SPI_TXR Register ...............................................................................................117 18.2.2 SPI_RXR Register ..............................................................................................117 18.2.2.1 SPI Master Data Register Definitions ................................................118 18.2.2.2 SPI Slave Data Register Definitions ..................................................118 18.2.3 SPI_CR Register .................................................................................................119 18.2.3.1 SPI Control Register Definitions ........................................................119 18.2.4 SPI_CFG Register ..............................................................................................120 18.2.4.1 SPI Configuration Register Definitions ..............................................120 18.3 Timing Diagrams ....................................................................................................................121 18.3.1 SPI Mode Timing .................................................................................................121 18.3.2 SPIM Timing ........................................................................................................122 18.3.3 SPIS Timing .........................................................................................................125
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19. Programmable Timer....................................................................................................... 129 19.1 Architectural Description........................................................................................................129 19.1.1 Operation .............................................................................................................130 19.2 Register Definitions ...............................................................................................................131 19.2.1 PT_CFG Register ...............................................................................................131 19.2.2 PT_DATA1 Register ............................................................................................131 19.2.3 PT_DATA0 Register ............................................................................................131
Section E:
Registers
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Register General Conventions ...........................................................................................................133 Register Mapping Tables ...................................................................................................................133 Register Map Bank 0 Table: User Space ............................................................................134 Register Map Bank 1 Table: Configuration Space .............................................................135 20. Register Reference ......................................................................................................... 137 20.1 Maneuvering Around the Registers .......................................................................................137 20.2 Register Conventions ..........................................................................................................137 20.3 Bank 0 Registers ..................................................................................................................138 20.3.1 PRTxDR .............................................................................................................138 20.3.2 PRTxIE ...............................................................................................................139 20.3.3 SPI_TXR .............................................................................................................140 20.3.4 SPI_RXR ............................................................................................................141 20.3.5 SPI_CR ...............................................................................................................142 20.3.6 AMUX_CFG ........................................................................................................143 20.3.7 CMP_RDC ..........................................................................................................144 20.3.8 CMP_MUX ..........................................................................................................145 20.3.9 CMP_CR0 ..........................................................................................................146 20.3.10 CMP_CR1 ..........................................................................................................147 20.3.11 CMP_LUT ...........................................................................................................149 20.3.12 CS_CR0 .............................................................................................................150 20.3.13 CS_CR1 .............................................................................................................151 20.3.14 CS_CR2 .............................................................................................................152 20.3.15 CS_CR3 .............................................................................................................153 20.3.16 CS_CNTL ...........................................................................................................154 20.3.17 CS_CNTH ...........................................................................................................155 20.3.18 CS_STAT ...........................................................................................................156 20.3.19 CS_TIMER .........................................................................................................157 20.3.20 CS_SLEW ..........................................................................................................158 20.3.21 PT_CFG .............................................................................................................159 20.3.22 PT_DATA1 .........................................................................................................160 20.3.23 PT_DATA0 .........................................................................................................161 20.3.24 CUR_PP .............................................................................................................162 20.3.25 STK_PP ..............................................................................................................163 20.3.26 IDX_PP ...............................................................................................................164 20.3.27 MVR_PP .............................................................................................................165 20.3.28 MVW_PP ............................................................................................................166 20.3.29 I2C_CFG ............................................................................................................167 20.3.30 I2C_SCR ............................................................................................................168 20.3.31 I2C_DR ...............................................................................................................169 20.3.32 INT_CLR0 ...........................................................................................................170 20.3.33 INT_MSK0 ..........................................................................................................172 20.3.34 INT_SW_EN .......................................................................................................173 20.3.35 INT_VC ...............................................................................................................174
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20.4
20.3.36 RES_WDT ..........................................................................................................175 20.3.37 CPU_F ................................................................................................................176 20.3.38 IDAC_D ...............................................................................................................177 20.3.39 CPU_SCR1 .........................................................................................................178 20.3.40 CPU_SCR0 .........................................................................................................179 Bank 1 Registers ...................................................................................................................180 20.4.1 PRTxDM0 ...........................................................................................................180 20.4.2 PRTxDM1 ...........................................................................................................181 20.4.3 SPI_CFG .............................................................................................................182 20.4.4 MUX_CRx ...........................................................................................................183 20.4.5 IO_CFG ...............................................................................................................184 20.4.6 OUT_P1 ..............................................................................................................185 20.4.7 OSC_CR0 ...........................................................................................................186 20.4.8 OSC_CR2 ...........................................................................................................187 20.4.9 VLT_CR ..............................................................................................................188 20.4.10 VLT_CMP ...........................................................................................................189 20.4.11 IMO_TR ..............................................................................................................190 20.4.12 ILO_TR ...............................................................................................................191 20.4.13 BDG_TR .............................................................................................................192 20.4.14 SLP_CFG ............................................................................................................193
Section F: Index
Glossary
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Section A: Overview
The PSoC® family consists of many Mixed-Signal Array with On-Chip Controller devices. As described in this Technical Reference Manual (TRM), the CY8C20x34/24 PSoC device does not have regular digital PSoC blocks and global interconnects that are found in most PSoC devices. The CY8C20x34/24 devices have one analog resource and digital logic in addition to a fast CPU, Flash program memory, and SRAM data memory to support various CapSense™ algorithms. For the most up-to-date Ordering, Pinout, Packaging, or Electrical Specification information, refer to the PSoC device’s data sheet. For the most current technical reference manual information, refer to the addendum. To obtain the newest product documentation, go to the Cypress web site at http://www.cypress.com/psoc. This section contains this chapter:
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Pin Information on page 19.
Document Organization
This manual is organized into sections and chapters, according to PSoC functionality. Each section contains a top-level architectural diagram and a register summary (if applicable). Most chapters within the sections have an introduction, an architectural/application description, register definitions, and timing diagrams. The sections are:
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Overview – Presents the PSoC top-level architecture, helpful information to get started, and document history and conventions. The PSoC device pinouts are detailed in the Pin Information chapter. PSoC Core – Describes the heart of the PSoC device in various chapters, beginning with an architectural overview and a summary list of registers pertaining to the PSoC core. CapSense System – Describes the configurable PSoC CapSense system in various chapters, beginning with an architectural overview and a summary list of registers pertaining to the CapSense system. System Resources – Presents additional PSoC system resources, beginning with an overview and a summary list of registers pertaining to system resources. Registers – Lists all PSoC device registers in register mapping tables, and presents bit-level detail of each PSoC register in its own Register Reference chapter. Where applicable, detailed register descriptions are located in each chapter. Glossary – Defines the specialized terminology used in this manual. Glossary terms are presented in bold, italic font throughout this manual. Index – Lists the location of key topics and elements that constitute and empower the PSoC device.
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Section A: Overview
Top-Level Architecture
The PSoC block diagram on the next page illustrates the top-level architecture of the CY8C20x34/24 PSoC device. Each major grouping in the diagram is covered in this manual in its own section: PSoC Core, CapSense System, and the System Resources. Banding these three main areas together is the communication network of the system bus.
PSoC Core
The PSoC Core is a powerful engine that supports a rich instruction set. It encompasses the SRAM for data storage, an interrupt controller for easy program execution to new addresses, sleep and watchdog timers, a regulated 3.0V output option is provided for Port 1 IOs, and multiple clock sources that include the IMO (internal main oscillator) and ILO (internal low speed oscillator) for precision, programmable clocking. The CPU core, called the M8C, is a powerful processor with speeds up to 12 MHz. The M8C is a two MIPS 8-bit Harvard architecture microprocessor. Within the CPU core are the SROM and Flash memory components that provide flexible programming. The smallest PSoC devices have a slightly different analog configuration. PSoC GPIOs provide connection to the CPU and the CapSense resources of the device. Each pin’s drive mode may be selected from four options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on low level and change from last read.
CapSense System
The CapSense System is composed of comparators, reference drivers, IO multiplexers, and digital logic to support various capsensing algorithms. Various reference selections are provided. Digital logic is mainly comprised of counters and timers.
System Resources
The System Resources provide additional PSoC capability. These system resources include:
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Digital clocks to increase the flexibility of the PSoC mixed-signal arrays. I2C functionality for implementing I2C slave. Internal voltage references that provide an absolute value of 0.9V, 1.3V, and 1.8V to the CapSense subsystems. Various system resets supported by the M8C. Power-On-Reset (POR) circuit protection. SPI master and slave functionality. A programmable timer to provide periodic interrupts.
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Section A: Overview
PSoC Top-Level Block Diagram
Port 3
Port 2
Port 1
Port 0
3V LDO
PSoC CORE
SYSTEM BUS Global Analog Interconnect SRAM Interrupt Controller Supervisory ROM (SROM) Flash Nonvolatile Memory Sleep and Watchdog
CPU Core (M8C)
6/12 MHz Internal Main Oscillator (IMO)
Internal Low Speed Oscillator (ILO)
Multiple Clock Sources
CAPSENSE SYSTEM
CapSense Module Comparators
Analog Reference
Analog Mux
SYSTEM BUS
Digital Clocks
I2C Slave
Internal Voltage References
System Resets
POR and LVD
SPI Master/ Slave
Programmable Timer
SYSTEM RESOURCES
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Section A: Overview
Getting Started
The quickest path to understanding PSoC is by reading the PSoC device’s data sheet and using the PSoC Designer Integrated Development Environment (IDE). This manual is useful for understanding the details of the PSoC integrated circuit. Important Note: For the most up-to-date Ordering, Packaging, or Electrical Specification information, refer to the individual PSoC device’s data sheet or go to http://www.cypress.com/psoc.
Support
Free support for PSoC products is available online at http://www.cypress.com. Resources include Training Seminars, Discussion Forums, Application Notes, PSoC Consultants, TightLink Technical Support Email/Knowledge Base, and Application Support Technicians. Technical Support can be reached at http://www.cypress.com/support/.
Product Upgrades
Cypress provides scheduled upgrades and version enhancements for PSoC Designer free of charge. You can order the upgrades from your distributor on CD-ROM or download them directly from http://www.cypress.com under Software and Drivers. Also provided are critical updates to system documentation under Design Support > Design Resources > More Resources or go to http://www.cypress.com.
Development Kits
Development Kits are available from authorized distributors. The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items.
Document History
This section serves as a chronicle of the PSoC Mixed-Signal Array Technical Reference Manual. PSoC Technical Reference Manual History
Version/ Release Date Version 1.0 September 22, 2006 001-13033 Rev. ** April 24, 2007 001-13033, Rev. *A February 19, 2008 DSG Added CY8C20x24 parts, revised Table 4-11, corrected IMO Trim voltage ranges in Chapter 7 VED Originator VED Description of Change First release of the PSoC CY8C20x34 Technical Reference Manual. This release encompasses the CY8C20x34 PSoC device. Update values in Table 16-1.
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Section A: Overview
Documentation Conventions
There are only four distinguishing font types used in this manual, besides those found in the headings.
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Units of Measure
This table lists the units of measure used in this manual. Units of Measure
Symbol dB Hz k K KB Kbit kHz decibels hertz kilo, 1000 210, 1024 1024 bytes 1024 bits kilohertz (32.000) megahertz microampere microfarad microsecond microvolts milliampere millisecond millivolts nanosecond picofarad parts per million volts Unit of Measure
The first is the use of italics when referencing a document title or file name. The second is the use of bold italics when referencing a term described in the Glossary of this manual. The third is the use of Times New Roman font, distinguishing equation examples. The fourth is the use of Courier New font, distinguishing code examples.
Register Conventions
This table lists the register conventions that are specific to this manual. A more detailed set of register conventions is located in the Register Reference chapter on page 137. Register Conventions
Convention ‘x’ in a register name R W O L C 00 XX 0, 1, x, Empty, grayedout table cell Example PRTxIE R : 00 W : 00 RO : 00 RL : 00 RC : 00 RW : 00 RW : XX 0,04h 1,23h x,F7h Description Multiple instances/address ranges of the same register Read register or bit(s) Write register or bit(s) Only a read/write register or bit(s). Logical register or bit(s) Clearable register or bit(s) Reset value is 0x00 or 00h Register is not reset Register is in bank 0 Register is in bank 1 Register exists in register bank 0 and register bank 1 Reserved bit or group of bits, unless otherwise stated
MHz μA μF μs μV mA ms mV ns pF ppm V
Numeric Naming
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’) and hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.
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Section A: Overview
Acronyms
This table lists the acronyms that are used in this manual. Acronyms
Acronym ABUS AC ADC API BC BR BRA BRQ CBUS CI CMP CO CPU CRC CT DAC DC DI DMA DO ECO FB GIE GPIO ICE IDE ILO IMO IO IOR IOW IPOR IRQ ISR ISSP IVR LFSR LRb LRB LSb LSB LUT MISO MOSI MSb MSB PC PCH analog output bus alternating current analog-to-digital converter Application Programming Interface broadcast clock bit rate bus request acknowledge bus request comparator bus carry in compare carry out central processing unit cyclic redundancy check continuous time digital-to-analog converter direct current digital or data input direct memory access digital or data output external crystal oscillator feedback global interrupt enable general purpose IO in-circuit emulator integrated development environment internal low speed oscillator internal main oscillator input/output IO read IO write imprecise power on reset interrupt request interrupt service routine in system serial programming interrupt vector read linear feedback shift register last received bit last received byte least significant bit least significant byte look-up table master-in-slave-out master-out-slave-in most significant bit most significant byte program counter program counter high Description
Acronyms (continued)
Acronym PCL PD PMA POR PPOR PRS PSoC™ PSSDC PWM RAM RETI RO ROM RW SAR SC SIE SE0 SOF SP SPI SPIM SPIS SRAM SROM SSADC SSC TC USB WDT WDR XRES program counter low power down PSoC™ memory arbiter power on reset precision power on reset pseudo random sequence Programmable System-on-Chip™ power system sleep duty cycle pulse width modulator random access memory return from interrupt relaxation oscillator read only memory read/write successive approximation register switched capacitor serial interface engine single-ended zero start of frame stack pointer serial peripheral interconnect serial peripheral interconnect master serial peripheral interconnect slave static random access memory supervisory read only memory single slope ADC supervisory system call terminal count universal serial bus watchdog timer watchdog reset external reset Description
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1. Pin Information
This chapter lists, describes, and illustrates all pins and pinout configurations for the CY8C20x34/24 PSoC device. For up-todate ordering, pinout, and packaging information, refer to the individual PSoC device’s data sheet or go to http://www.cypress.com/psoc.
1.1
Pinouts
The CY8C20x34/24 PSoC devices are available in a variety of packages. Every port pin (labeled with a “P”), except for Vss and Vdd in the following tables and illustrations, is capable of Digital IO.
1.1.1
16-Pin Part Pinout
Type
Table 1-1: 16-Pin Part Pinout (QFN**)
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 IO IO IO IO IO Digital IO IO IO IO IO IO IO IO IO IO Reset I I I I I Analog I I I I I I I I I I Name P2[5] P2[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] XRES P0[4] Vdd P0[7] P0[3] P0[1] Integration Cap Supply Voltage EXTCLK Active high external reset with internal pull down I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK TC CLK, I2C SCL, SPI MOSI Ground Connection TC DATA, I2C SDA Description
CY8C20234, CY8C20224 PSoC Device
P0[1], AI P0[3], AI P0[7], AI Vdd AI, SPI CLK, P1[3] TC CLK, I2C SCL, SPI MOSI P1[1] Vss AI, TC DATA, I2C SDA, P1[0] 5 6 7 8 AI, P2[5] 1 12 AI, P2[1] 2 QFN 11 (Top View) 10 AI, I2C SCL, SPI SS, P1[7] 3 9 AI, I2C SDA, SPI MISO, P1[5] 4 16 15 14 13 P0[4], AI XRES P1[4], AI, EXT CLK P1[2], AI
LEGEND A = Analog, I = Input, O = Output, H = 5 mA High Output Drive. * These are the ISSP pins, which are not High Z at POR (Power On Reset). ** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal.
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Pin Information
1.1.2
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 IO IO IO IO IO IO IO IO IO
24-Pin Part Pinout
Type
Table 1-2. 24-Pin Part Pinout (QFN**)
Digital IO IO IO IOH IOH IOH IOH Power IOH IOH IOH IOH Input I I I I I Power I I I I I I I I Analog I I I I I I I Name P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] NC Vss P1[0] P1[2] P1[4] P1[6] XRES P2[0] P0[0] P0[2] P0[4] P0[6] Vdd P0[7] P0[5] P0[3] P0[1] Integrating input Analog bypass Supply voltage Active high external reset with internal pull down Optional external clock input (EXTCLK) I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK CLK*, I2C SCL, SPI MOSI No connection Ground connection DATA*, I2C SDA
AI, P2[5] AI, P2[3] AI, P2[1] AI, I2C SCL, SPI SS, P1[7] AI, I2C SDA, SPI MISO, P1[5] AI, SPI CLK, P1[3] 1 2 3 4 5 6 24 23 22 21 20 19 18 17 QFN 16 (Top View) 15 14 13 P0[4], AI P0[2], AI P0[0], AI P2[0], AI XRES P1[6], AI
Description
CY8C20334, CY8C20324 PSoC Device
P0[1], AI P0[3], AI P0[5], AI P0[7], AI Vdd P0[6], AI
LEGEND A = Analog, I = Input, O = Output, H = 5 mA High Output Drive. * These are the ISSP pins, which are not High Z at POR (Power On Reset). ** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal.
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AI, CLK*, I2C SCL, SPI MOSI, P1[1] NC Vss AI, DATA*, I2C SDA, P1[0] AI, P1[2] AI, EXTCLK, P1[4]
7 8 9 10 11 12
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Pin Information
1.1.3
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 IO IO IO IO IO IO IO IO IO IO IO IO IO
32-Pin Part Pinout
Type
Table 1-3. 32-Pin Part Pinout (QFN**)
Digital IO IO IO IO IO IO IO IOH IOH IOH IOH Power IOH IOH IOH IOH Input I I I I I I I I I I Power I I I Power I I I I Analog I I I I I I I I I I I Name P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd P0[7] P0[5] P0[3] Vss Integrating input Ground connection Analog bypass Supply voltage Active high external reset with internal pull down Optional external clock input (EXTCLK) I2C SCL, SPI SS I2C SDA, SPI MISO SPI CLK CLK*, I2C SCL, SPI MOSI Ground connection DATA*, I2C SDA Description
CY8C20434, CY8C20424 PSoC Device
Vss P0[3], AI P0[5], AI P0[7], AI Vdd P0[6], AI P0[4], AI P0[2], AI AI, P0[1] AI, P2[7] AI, P2[5] AI, P2[3] AI, P2[1] AI, P3[3] AI, P3[1] AI, I2C SCL, SPI SS, P1[7] 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8
QFN
(Top View)
LEGEND A = Analog, I = Input, O = Output, H = 5 mA High Output Drive. * These are the ISSP pins, which are not High Z at POR (Power On Reset). ** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal.
Spec. # 001-13033 Rev. *A, February 19, 2008
AI, I2C SDA, SPI MISO, P1[5] AI, SPI CLK, P1[3] AI, CLK*, I2C SCL, SPI MOSI, P1[1] Vss AI, DATA*, I2C SDA, P1[0] AI, P1[2] AI, EXTCLK, P1[4] AI, P1[6]
9 10 11 12 13 14 15 16
24 23 22 21 20 19 18 17
P0[0], AI P2[6], AI P2[4], AI P2[2], AI P2[0], AI P3[2], AI P3[0], AI XRES
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Pin Information
1.1.4
Digital
48-Pin OCD Part Pinout
Analog
Table 1-4. 48-Pin OCD Part Pinout (QFN**)
Pin No.
CY8C20000 OCD PSoC Device
Name Description
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 IO IO IO IO IO IOH IOH Input I I I I I I I IOH IOH I I IOH IOH Power I I IO IO IO IO IO IO IO IOH IOH I I I I I I I I I
NC P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] P1[7] P1[5] NC NC NC NC P1[3] P1[1] Vss CCLK HCLK P1[0] P1[2] NC NC NC P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2]
No internal connection
I2C SCL, SPI SS I2C SDA, SPI MISO No internal connection No internal connection No internal connection No internal connection SPI CLK CLK*, I2C SCL, SPI MOSI Ground connection OCD CPU clock output OCD high speed clock output DATA*, I2C SDA No internal connection No internal connection No internal connection Optional external clock input (EXTCLK) Active high external reset with internal pull down
Pin No.
Analog
Digital
P2[4]
Name
33 34 35 36 37 38 39 40
IO IO IO IO
I I I I
P2[6] P0[0] P0[2] P0[4] NC NC NC No internal connection No internal connection No internal connection Analog bypass
41 42 43 44 45 46 47 48
Power
Vdd OCDO OCDE
IO IO IO
I I I
P0[7] P0[5] P0[3] Vss NC Integrating input Ground connection No internal connection
Power
IO
I
P0[6]
LEGEND A = Analog, I = Input, O = Output, NC = No Connection, H = 5 mA High Output Drive. * ISSP pin which is not HiZ at POR. ** The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal.
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NC NC AI, SPI CLK, P1[3] AI, CLK*, I2C SCL, SPI MOSI, P1[1] Vss CCLK HCLK AI, DATA*, I2C SDA, P1[0] AI, P1[2] NC NC NC
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13 14 15 16 17 18 19 20 21 22 23 24
NC AI, P0[1] AI, P2[7] AI, P2[5] AI, P2[3] AI, P2[1] AI, P3[3] AI, P3[1] AI, I2C SCL, SPI SS, P1[7] AI, I2C SDA, SPI MISO, P1[5] NC NC
1 2 3 4 5 6
48 47 46 45 44 43 42 41 40 39 38 37
NC Vss P0[3], AI P0[5], AI P0[7], AI OCDE OCDO Vdd P0[6], AI NC NC NC
OCD QFN
(Top View)
7 8 9 10 11 12
36 35 34 33 32 31 30 29 28 27 26 25
P0[4], AI P0[2], AI P0[0], AI P2[6], AI P2[4], AI P2[2], AI P2[0], AI P3[2], AI P3[0], AI XRES P1[6], AI P1[4], EXTCLK, AI
NOT FOR PRODUCTION
Description
Supply voltage OCD even data IO OCD odd data output
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Section B: PSoC Core
The PSoC® Core section discusses the core components of a PSoC device with a base part number of CY8C20x34/24 and the registers associated with those components. The core section covers the heart of the PSoC device, which includes the M8C microcontroller; SROM, interrupt controller, GPIO, and SRAM paging; multiple clock sources such as IMO and ILO; and sleep and watchdog functionality. This section contains these chapters:
■ ■ ■ ■
CPU Core (M8C) on page 25. RAM Paging on page 31. Supervisory ROM (SROM) on page 37. Interrupt Controller on page 45.
■ ■ ■ ■
General Purpose IO (GPIO) on page 51. Internal Main Oscillator (IMO) on page 57. Internal Low Speed Oscillator (ILO) on page 59. Sleep and Watchdog on page 61.
Top Level Core Architecture
The figure below illustrates the top-level architecture of the PSoC’s core. Each figure component is discussed in detail in this section. PSoC Core Block Diagram
Port 3
Port 2
Port 1
Port 0
3V LDO
PSoC CORE
SYSTEM BUS
SRAM Interrupt Controller
Supervisory ROM (SROM)
Flash Nonvolatile Memory Sleep and Watchdog
CPU Core (M8C)
6/12 MHz Internal Main Oscillator (IMO)
Internal Low Speed Oscillator (ILO)
Multiple Clock Sources
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Section B: PSoC Core
Core Register Summary
This table lists all the PSoC registers for the CPU core in address order within their system resource configuration. The grayed bits are reserved bits. If these bits are written, always write them with a value of ‘0’. For the core registers, the first ‘x’ in some register addresses represents either bank 0 or bank 1. These registers are listed throughout this manual in bank 0, even though they are also available in bank 1. Summary Table of the Core Registers
Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Access M8C REGISTER (page 25)
x,F7h
CPU_F
PgMode[1:0]
XIO
RAM PAGING (SRAM) REGISTERS (page 31)
Carry
Zero
GIE
RL : 02
0,D0h 0,D1h 0,D3h 0,D4h 0,D5h
CUR_PP STK_PP IDX_PP MVR_PP MVW_PP
INTERRUPT CONTROLLER REGISTERS (page 45)
Page Bit Page Bit Page Bit Page Bit Page Bit
RW : 00 RW : 00 RW : 00 RW : 00 RW : 00
0,DAh 0,E0h 0,E1h 0,E2h
INT_CLR0 INT_MSK0 INT_SW_EN INT_VC
I2C I2C
Sleep Sleep
SPI SPI
GPIO GPIO
Timer Timer
CapSense CapSense
Analog Analog
V Monitor V Monitor ENSWINT
RW : 00 RW : 00 RW : 00 RC : 00
Pending Interrupt[7:0]
GENERAL PURPOSE IO (GPIO) REGISTERS (page 51)
0,00h 0,01h 0,04h 0,05h 0,08h 0,09h 0,0Ch 0,0Dh 1,00h 1,01h 1,04h 1,05h 1,08h 1,09h 1,0Ch 1,0Dh 1,DCh
PRT0DR PRT0IE PRT1DR PRT1IE PRT2DR PRT2IE PRT3DR PRT3IE PRT0DM0 PRT0DM1 PRT1DM0 PRT1DM1 PRT2DM0 PRT2DM1 PRT3DM0 PRT3DM1 IO_CFG
Data[7:0] Interrupt Enables[7:0] Data[7:0] Interrupt Enables[7:0] Data[7:0] Interrupt Enables[7:0] Data[7:0] Interrupt Enables[7:0] Drive Mode 0[7:0] Drive Mode 1[7:0] Drive Mode 0[7:0] Drive Mode 1[7:0] Drive Mode 0[7:0] Drive Mode 1[7:0] Drive Mode 0[7:0] Drive Mode 1[7:0] REG_EN
INTERNAL MAIN OSCILLATOR (IMO) REGISTER (page 57)
RW : 00 RW : 00 RW : 00 RW : 00 RW : 00 RW : 00 RW : 00 RW : 00 RW : 00 RW : FF RW : 00 RW : FF RW : 00 RW : FF RW : 00 RW : FF IOINT RW : 00
1,E8h
IMO_TR
Trim[7:0]
INTERNAL LOW SPEED OSCILLATOR (ILO) REGISTER (page 59)
W : 00
1,E9h
ILO_TR
Bias Trim[1:0]
SLEEP AND WATCHDOG REGISTERS (page 61)
Freq Trim[3:0]
W : 00
0,E3h 1,EBh
RES_WDT SLP_CFG PSSDC[1:0]
WDSL_Clear[7:0]
W : 00 RW : 00
LEGEND L The and f, expr; or f, expr; and xor f, expr instructions can be used to modify this register. x An “x” before the comma in the address field indicates that this register can be accessed or written to no matter what bank is used. C Clearable register or bit(s). R Read register or bit(s). W Write register or bit(s).
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2. CPU Core (M8C)
This chapter explains the CPU Core, called the M8C, and its associated register. It covers the internal M8C registers, address spaces, instruction set and formats. For additional information concerning the M8C instruction set, refer to the PSoC Designer Assembly Language User Guide available at the Cypress web site (http://www.cypress.com/psoc). For a quick reference of all PSoC registers in address order, refer to the Register Reference chapter on page 137.
2.1
Overview
The M8C is a two MIPS 8-bit Harvard architecture microprocessor. Selectable processor clock speeds up to 12 MHz allow you to adjust the M8C to a particular application’s performance and power requirements. The M8C supports a rich instruction set that allows for efficient low level language support.
With the exception of the F register, the M8C internal registers are not accessible via an explicit register address. The internal M8C registers are accessed using these instructions: ■ MOV A, expr ■ MOV X, expr ■ SWAP A, SP ■ OR F, expr ■ JMP LABEL The F register is read by using address F7h in either register bank.
2.2
Internal Registers
The M8C has five internal registers that are used in program execution. The registers are:
■ ■ ■ ■ ■
Accumulator (A) Index (X) Program Counter (PC) Stack Pointer (SP) Flags (F)
2.3
Address Spaces
The M8C has three address spaces: ROM, RAM, and registers. The ROM address space includes the supervisory ROM (SROM) and the Flash. The ROM address space is accessed through its own address and data bus. The ROM address space is composed of the Supervisory ROM and the on-chip Flash program store. Flash is organized into 64-byte blocks. Program store page boundaries are not a concern, since the M8C automatically increments the 16-bit PC on every instruction. This process makes the block boundaries invisible to user code. Instructions occurring on a 256-byte Flash page boundary (with the exception of JMP instructions) incur an extra M8C clock cycle as the upper byte of the PC is incremented. The register address space is used to configure the PSoC microcontroller’s programmable blocks. It consists of two banks of 256 bytes each. To switch between banks, the XIO bit in the Flag register is set or cleared (set for Bank1, cleared for Bank0). The common convention is to leave the bank set to Bank0 (XIO cleared), switch to Bank1 as necessary (set XIO), then switch back to Bank0.
All of the internal M8C registers are eight bits in width, except for the PC which is 16 bits wide. When reset, A, X, PC, and SP are reset to 00h. The Flag register (F) is reset to 02h, indicating that the Z flag is set. With each stack operation, the SP is automatically incremented or decremented so that it always points to the next stack byte in RAM. If the last byte in the stack is at address FFh, the stack pointer will wrap to RAM address 00h. It is the firmware developer’s responsibility to ensure that the stack does not overlap with user-defined variables in RAM.
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CPU Core (M8C)
2.4
Instruction Set Summary
The instruction set is summarized in both Table 2-1 and Table 2-2 (in numeric and mnemonic order, respectively), and serves as a quick reference. If more information is needed, the Instruction Set Summary tables are described in detail in the PSoC Designer Assembly Language User Guide (refer to the http://www.cypress.com/psoc web site). Table 2-1. Instruction Set Summary Sorted Numerically by Opcode
Opcode Hex Opcode Hex Opcode Hex Cycles Cycles Cycles Bytes Bytes Bytes
Instruction Format
Flags
Instruction Format
Flags
Instruction Format
Flags
00 15 01 02 03 04 05 06 08 09 0A 0B 0C 0D 0E 10 11 12 13 14 15 16 18 19 1A 1B 1C 1D 1E 20 21 22 23 24 25 26 4 6 7 7 8 9 4 4 6 7 7 8 9 4 4 6 7 7 8 9 5 4 6 7 7 8 9 5 4 6 7 7 8 9
1 SSC 2 ADD A, expr 2 ADD A, [expr] 2 ADD A, [X+expr] 2 ADD [expr], A 2 ADD [X+expr], A 3 ADD [expr], expr 3 ADD [X+expr], expr 1 PUSH A 2 ADC A, expr 2 ADC A, [expr] 2 ADC A, [X+expr] 2 ADC [expr], A 2 ADC [X+expr], A 3 ADC [expr], expr 3 ADC [X+expr], expr 1 PUSH X 2 SUB A, expr 2 SUB A, [expr] 2 SUB A, [X+expr] 2 SUB [expr], A 2 SUB [X+expr], A 3 SUB [expr], expr 3 SUB [X+expr], expr 1 POP A 2 SBB A, expr 2 SBB A, [expr] 2 SBB A, [X+expr] 2 SBB [expr], A 2 SBB [X+expr], A 3 SBB [expr], expr 3 SBB [X+expr], expr 1 POP X 2 AND A, expr 2 AND A, [expr] 2 AND A, [X+expr] 2 AND [expr], A 2 AND [X+expr], A 3 AND [expr], expr 3 AND [X+expr], expr 1 ROMX 2 OR A, expr 2 OR A, [expr] 2 OR A, [X+expr] 2 OR [expr], A Z Z Z Z Z Z Z Z Z Z Z Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z
2D 2E 30 31 32 33 34 35 36 38 39 3A 3B 3C 3D
8 9 9 4 6 7 7 8 9 5 5 7 8 8 9
2 OR [X+expr], A 3 OR [expr], expr 3 OR [X+expr], expr 1 HALT 2 XOR A, expr 2 XOR A, [expr] 2 XOR A, [X+expr] 2 XOR [expr], A 2 XOR [X+expr], A 3 XOR [expr], expr 3 XOR [X+expr], expr 2 ADD SP, expr 2 CMP A, expr 2 CMP A, [expr] 2 CMP A, [X+expr] 3 CMP [expr], expr 3 CMP [X+expr], expr 2 MVI A, [ [expr]++ ] 2 MVI [ [expr]++ ], A 1 NOP 3 AND reg[expr], expr 3 AND reg[X+expr], expr 3 OR reg[expr], expr 3 OR reg[X+expr], expr 3 XOR reg[expr], expr 3 XOR reg[X+expr], expr 3 TST [expr], expr 3 TST [X+expr], expr 3 TST reg[expr], expr 3 TST reg[X+expr], expr 1 SWAP A, X 2 SWAP A, [expr] 2 SWAP X, [expr] 1 SWAP A, SP 1 MOV X, SP 2 MOV A, expr 2 MOV A, [expr] 2 MOV A, [X+expr] 2 MOV [expr], A 2 MOV [X+expr], A 3 MOV [expr], expr 3 MOV [X+expr], expr 2 MOV X, expr 2 MOV X, [expr] 2 MOV X, [X+expr]
Z Z Z Z Z Z Z Z Z Z
5A 5B 5C 5D 5E 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D
5 4 4 6 7 5 6 8 9 4 7 8 4 7 8 4 7 8 4 7 8 4 4 4 4 4 4 7 8 4 4 7 8 7 8 5 5 5 5 5 7
2 MOV [expr], X 1 MOV A, X 1 MOV X, A 2 MOV A, reg[expr] 2 MOV A, reg[X+expr] 3 MOV [expr], [expr] 2 MOV reg[expr], A 2 MOV reg[X+expr], A 3 MOV reg[expr], expr 3 MOV reg[X+expr], expr 1 ASL A 2 ASL [expr] 2 ASL [X+expr] 1 ASR A 2 ASR [expr] 2 ASR [X+expr] 1 RLC A 2 RLC [expr] 2 RLC [X+expr] 1 RRC A 2 RRC [expr] 2 RRC [X+expr] 2 AND F, expr 2 OR F, expr 2 XOR F, expr 1 CPL A 1 INC A 1 INC X 2 INC [expr] 2 INC [X+expr] 1 DEC A 1 DEC X 2 DEC [expr] 2 DEC [X+expr] 3 LCALL 3 LJMP 1 RETI 1 RET 2 JMP 2 CALL 2 JZ 2 JNZ 2 JC 2 JNC 2 JACC 2 INDEX Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z C, Z Z Z Z
2F 10
5F 10
07 10
37 10
if (A=B) Z=1 if (A
