Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY8C21312
CY8C21512
®
Automotive Extended PSoC
Programmable System-on-Chip™
Automotive Extended PSoC® Programmable System-on-Chip™
Features
■
■
Automotive Electronics Council (AEC) Q100 qualified
Powerful Harvard-architecture processor
❐ M8C processor speeds up to 12 MHz
❐ Low power at high speed
❐ Operating voltage: 4.75 V to 5.25 V or 3 V to 3.6 V
❐ Automotive temperature range: –40 °C to +125 °C
■ Advanced peripherals
®
❐ One CapSense block:
• Provides configurable capacitive sensing elements
• Supports combination of CapSense buttons, sliders,
touchpads, and proximity sensors
®
❐ One limited digital PSoC block provides:
• 8-bit timer, counter, or pulse-width modulator (PWM)
• Half-duplex UART
• SPI slave
• Connectable to all general purpose I/O (GPIO) pins
■ Flexible on-chip memory
❐ 8 KB flash program storage
❐ 512 bytes SRAM data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ EEPROM emulation in flash
■ Complete development tools
❐ Free development software (PSoC Designer™)
❐ Full-featured in-circuit emulator (ICE) and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 KB trace memory
■ Precision, programmable clocking
❐ Internal 24 MHz oscillator
❐ Internal low-speed, low-power oscillator for Watchdog and
Sleep functionality
❐ Optional external oscillator, up to 24 MHz
■ Programmable pin configurations
❐ 25 mA sink, 10 mA drive on all GPIOs
❐ Pull-up, pull-down, high Z, strong, or open drain drive modes
on all GPIOs
❐ Analog input on all GPIOs
❐ Configurable interrupt on all GPIOs
■
Cypress Semiconductor Corporation
Document Number: 001-81890 Rev. *B
•
■
Versatile analog mux
❐ Common internal analog bus
❐ Simultaneous connection of I/O combinations
Additional system resources
2
❐ Inter-Integrated Circuit (I C™) master, slave, or multi-master
operation up to 400 kHz
❐ Watchdog and sleep timers
❐ User-configurable low-voltage detection (LVD)
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
Logic Block Diagram
198 Champion Court
Port 3
Port 2
Port 1
Port 0
PSoC CORE
System Bus
Global Digital
Interconnect
Global Analog Interconnect
SRAM
512B
SROM
Flash 8K
CPU Core (M8C)
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
ANALOG SYSTEM
Analog Input
Muxing
Digital Block
CapSense Block
Digital
Resources
Digital
Clocks
Analog
Resources
POR and LVD
I2C
System Resets
Internal
Voltage
Ref.
SYSTEM RESOURCES
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 29, 2014
CY8C21312
CY8C21512
Contents
PSoC Functional Overview.............................................. 3
The PSoC Core ........................................................... 3
The Digital System ...................................................... 3
The Analog System ..................................................... 4
Additional System Resources ..................................... 4
PSoC Device Characteristics ...................................... 5
Getting Started.................................................................. 5
Application Notes ........................................................ 5
Development Kits ........................................................ 5
Training ....................................................................... 5
CYPros Consultants .................................................... 5
Solutions Library.......................................................... 5
Technical Support ....................................................... 5
Development Tools .......................................................... 6
PSoC Designer Software Subsystems........................ 6
Designing with PSoC Designer ....................................... 7
Select Components ..................................................... 7
Configure Components ............................................... 7
Organize and Connect ................................................ 7
Generate, Verify, and Debug....................................... 7
Pinouts .............................................................................. 8
20-pin Part Pinout........................................................ 8
28-pin Part Pinout........................................................ 9
Registers ......................................................................... 10
Register Conventions ................................................ 10
Register Mapping Tables .......................................... 10
Absolute Maximum Ratings .......................................... 13
Operating Temperature.................................................. 13
Electrical Specifications ................................................ 14
Document Number: 001-81890 Rev. *B
DC Electrical Characteristics.....................................
AC Electrical Characteristics .....................................
Development Tool Selection .........................................
Software ....................................................................
Development Kits ......................................................
Evaluation Tools........................................................
Device Programmers.................................................
Accessories (Emulation and Programming) ..............
Ordering Information......................................................
Ordering Code Definitions .........................................
Packaging Information...................................................
Packaging Dimensions..............................................
Tape and Reel Information........................................
Thermal Impedances.................................................
Solder Reflow Specifications.....................................
Reference Information ...................................................
Reference Documents...............................................
Acronyms ........................................................................
Document Conventions .................................................
Units of Measure .......................................................
Numeric Conventions ....................................................
Glossary ..........................................................................
Document History Page .................................................
Sales, Solutions, and Legal Information ......................
Worldwide Sales and Design Support.......................
Products ....................................................................
PSoC Solutions .........................................................
15
18
23
23
23
23
23
24
25
25
26
26
28
30
30
31
31
32
32
32
32
33
37
38
38
38
38
Page 2 of 38
CY8C21312
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PSoC Functional Overview
The Digital System
The PSoC family consists of many devices with on-chip
controllers. These devices are designed to replace multiple
traditional
microcontroller
unit
(MCU)-based
system
components with one, low-cost single-chip programmable
component. A PSoC device includes configurable blocks of
analog and digital logic, and programmable interconnect. This
architecture makes it possible for you to create customized
peripheral configurations, to match the requirements of each
individual application. Additionally, a fast CPU, flash program
memory, SRAM data memory, and configurable I/O are included
in a range of convenient pinouts.
The digital system is composed of one digital block. This block
is an 8-bit resource that can implement various 8-bit digital
peripherals. Digital peripheral configurations include those listed.
The PSoC architecture, as illustrated in the Logic Block Diagram
on page 1, comprises of four main areas: the core, the system
resources, the digital system, and the analog system.
Configurable global bus resources allow all the device resources
to be combined into a complete custom system. Each
CY8C21x12 device includes one limited digital block and one
CapSense block. Depending on the PSoC package, up to 24
GPIOs are also included. The GPIOs provide access to the
global digital and analog interconnects.
■
PWM (8-bit)
■
Counter (8-bit)
■
Timer (8-bit)
■
Half-duplex 8-bit UART with selectable parity
■
SPI slave
■
I2C master, slave, or multi-master (implemented in a dedicated
I2C block)
The digital block can be connected to any GPIO through a series
of global buses that can route any signal to any pin. The buses
also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Figure 1. Digital System Block Diagram
The PSoC Core
Port 3
Digital Clocks
From Core
Port 0
To System Bus
DIGITAL SYSTEM
System Resources provide additional capability, such as digital
clocks for increased flexibility, I2C functionality for implementing
an I2C master, slave, or multi-master, an internal voltage
reference that provides an absolute value of 1.3 V to a number
of PSoC subsystems, and various system resets supported by
the M8C.
Digital Array
Row Input
Configuration
Row 0
8
4
CapSense0
LDB0
Analog
Digital
3
8
Row Output
Configuration
The Digital System is composed of a programmable limited
digital block and fixed-function digital resources inside the
CapSense block. The limited digital block can be configured into
a number of digital peripherals. The fixed-function digital
resources in the CapSense block provide external modulation
signals, measurement timing, and measurement conversion.
The digital resources can be connected to the GPIO through a
series of global buses that provide very flexible routing options.
Port 1
Port 2
The PSoC core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep, and watchdog timers, and an internal
main oscillator (IMO) and internal low-speed oscillator (ILO). The
CPU core, called the M8C, is a powerful processor with speeds
up to 24 MHz. The M8C is a four-million instructions per second
(MIPS) 8-bit Harvard-architecture microprocessor.
8
8
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
GOE[7:0]
GOO[7:0]
The Analog System is composed of a comparator and a filter that
are used in the CapSense block in order to implement capacitive
sensing measurement.
Document Number: 001-81890 Rev. *B
Page 3 of 38
CY8C21312
CY8C21512
The Analog System
The Analog Multiplexer System
The analog system is composed of analog resources inside of
the CapSense block. These resources are used to implement a
flexible capacitive sensing and measurement module. The
analog resources in the CapSense block are listed.
The analog mux bus can connect to every GPIO pin. Pins can
be connected to the bus individually or in any combination. The
bus also connects to the analog system. Switch-control logic
enables selected pins to precharge continuously under hardware
control. This enables capacitive measurement for applications
such as touch sensing. Other multiplexer applications include:
■
Comparator used in capacitance-to-digital conversion
■
Fixed, absolute reference or adjustable, ratiometric reference
can be used with the comparator
■
Low-pass filter converts a digital bit stream into the adjustable,
ratiometric analog reference
Figure 2. Analog System Block Diagram
CMP
...
Document Number: 001-81890 Rev. *B
■
Chip-wide mux that allows analog input from any I/O pin.
■
Crosspoint connection between any I/O pin combination.
System resources, some of which have been previously listed,
provide additional capability useful for complete systems. Brief
statements describing the merits of each system resource are
presented.
CapSense0
Analog
VREF
Track pad, finger sensing.
Additional System Resources
Analog System
All I/O
■
To Digital
Resources
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems.
■
The I2C module provides communication up to 400 kHz over
two wires. Slave, master, and multi-master modes are all
supported.
■
LVD interrupts can signal the application of falling voltage
levels, while the advanced power-on reset (POR) circuit
eliminates the need for a system supervisor.
■
An internal 1.3 V voltage reference provides an absolute
reference for the analog system.
■
Versatile analog multiplexer system.
Page 4 of 38
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PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have a varying number of digital and analog
blocks. Table 1 lists the resources available for specific PSoC device groups. The PSoC device covered by this datasheet is highlighted
in Table 1
Table 1. PSoC Device Characteristics
PSoC Part
Number
Digital I/O
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
up to 64
4
16
up to 12
4
4
12
2K
32 K
CY8C28xxx
up to 44
up to 3
up to 12
up to 44
up to 4
up to 6
up to
12 + 4 [2]
1K
16 K
CY8C29x66
[1]
SRAM Size Flash Size
CY8C27x43
up to 44
2
8
up to 12
4
4
12
256
16 K
CY8C24x94 [1]
up to 56
1
4
up to 48
2
2
6
1K
16 K
CY8C24x23A [1]
up to 24
1
4
up to 12
2
2
6
256
4K
CY8C23x33
up to 26
1
4
up to 12
2
2
4
256
8K
[2]
[1]
up to 38
2
8
up to 38
0
4
6
1K
16 K
CY8C21x45 [1]
up to 24
1
4
up to 24
0
4
6 [2]
512
8K
[2]
CY8C22x45
CY8C21x34
[1]
CY8C21x23
up to 28
1
4
28
0
2
4
512
8K
up to 16
1
4
up to 8
0
2
4 [2]
256
4K
[2]
[1]
up to 24
1
24
0
0
512
8K
CY8C20x34 [1]
up to 28
0
0
up to 28
0
0
3 [2, 3]
512
8K
CY8C20xx6
up to 36
0
0
up to 36
0
0
3 [2, 3]
up to 2 K
up to 32 K
CY8C21x12
1
[2]
1
Getting Started
CYPros Consultants
For in-depth information, along with detailed programming
details, see the PSoC® Technical Reference Manual.
Certified PSoC consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC consultant go to the CYPros Consultants web site.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web.
Solutions Library
Cypress application notes are an excellent introduction to the
wide variety of possible PSoC designs.
Visit our growing library of solution focused designs. Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
Development Kits
Technical Support
PSoC Development Kits are available online from and through a
growing number of regional and global distributors, which
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and
Newark.
Technical support – including a searchable Knowledge Base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
Application Notes
Training
Free PSoC technical training (on demand, webinars, and
workshops), which is available online via www.cypress.com,
covers a wide variety of topics and skill levels to assist you in
your designs.
Notes
1. Automotive qualified devices available in this group.
2. Limited analog functionality.
3. Two analog blocks and one CapSense® block.
Document Number: 001-81890 Rev. *B
Page 5 of 38
CY8C21312
CY8C21512
Development Tools
PSoC Designer™ is the revolutionary integrated design
environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
Code Generation Tools
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and are
linked with other software modules to get absolute addressing.
■
Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■
Extensive user module catalog
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
■
Integrated source-code editor (C and assembly)
Debugger
■
Free C compiler with no size restrictions or time limits
■
Built-in debugger
■
In-circuit emulation
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
You can read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also allows you to create a trace buffer of registers and memory
locations of interest.
■
Built-in support for communication interfaces:
2
❐ Hardware and software I C slaves and masters
❐ Full-speed USB 2.0
❐ Up
to
four
full-duplex
universal
asynchronous
receiver/transmitters (UARTs), SPI master and slave, and
wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
PSoC Designer Software Subsystems
Online Help System
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an online support Forum
to aid the designer.
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are ADCs, DACs, amplifiers, and filters. Configure
the user modules for your chosen application and connect them
to each other and to the proper pins. Then generate your project.
This prepopulates your project with APIs and libraries that you
can use to program your application.
The tool also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration makes it possible to change configurations at run
time. In essence, this allows you to use more than 100 percent
of PSoC's resources for an application.
Document Number: 001-81890 Rev. *B
In-Circuit Emulator
A low-cost, high-functionality in-circuit emulator (ICE) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24 MHz) operation.
Page 6 of 38
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Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process can be summarized in the
following four steps:
1. Select User Modules
2. Configure User Modules
3. Organize and Connect
4. Generate, Verify, and Debug
Select Components
PSoC Designer provides a library of pre-built, pre-tested
hardware peripheral components called "user modules”. User
modules make selecting and implementing peripheral devices,
both analog and digital, simple.
Configure Components
Each of the User Modules you select establishes the basic
register settings that implement the selected function. They also
provide parameters and properties that allow you to tailor their
precise configuration to your particular application. For example,
a PWM User Module configures one or more
digital PSoC blocks, one for each 8 bits of resolution. The user
module parameters permit you to establish the pulse width and
duty cycle. Configure the parameters and properties to
correspond to your chosen application. Enter values directly or
by selecting values from drop-down menus. All the user modules
are documented in datasheets that may be viewed directly in
Document Number: 001-81890 Rev. *B
PSoC Designer or on the Cypress website. These user module
datasheets explain the internal operation of the User Module and
provide performance specifications. Each datasheet describes
the use of each user module parameter, and other information
you may need to successfully implement your design.
Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. You perform the
selection, configuration, and routing so that you have complete
control over all on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the "Generate
Configuration Files" step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides application programming interfaces
(APIs) with high-level functions to control and respond to
hardware events at run time and interrupt service routines that
you can adapt as needed.
A complete code development environment allows you to
develop and customize your applications in C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer's Debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition
to traditional single-step, run-to-breakpoint and watch-variable
features, the debug interface provides a large trace buffer and
allows you to define complex breakpoint events that include
monitoring address and data bus values, memory locations and
external signals.
Page 7 of 38
CY8C21312
CY8C21512
Pinouts
The CY8C21x12 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port
pin (labeled with a “P”) is capable of digital I/O and connection to the common analog bus. However, VSS, VDD, and XRES are not
capable of digital I/O.
20-pin Part Pinout
Table 2. 20-pin Part Pinout (shrink small-outline package (SSOP))
Type
Pin
Name
No. Digital Analog
Description
1
I/O
I, M
P0[7]
Analog column mux input
2
I/O
I, M
P0[5]
Analog column mux input
3
I/O
I, M
P0[3]
Analog column mux input, CMOD capacitor pin
4
I/O
I, M
P0[1]
Analog column mux input, CMOD capacitor pin
VSS
Ground connection
5
Power
6
I/O
M
P1[7]
I2C serial clock (SCL)
7
I/O
M
P1[5]
I2C serial data (SDA)
8
I/O
M
P1[3]
9
I/O
M
P1[1]
I2C SCL, ISSP-SCLK[4]
VSS
Ground connection
I2C SDA, ISSP-SDATA[4]
10
Power
11
I/O
M
P1[0]
12
I/O
M
P1[2]
13
I/O
M
P1[4]
14
I/O
M
P1[6]
15
Input
XRES
Active high external reset with internal
pull-down
I/O
I, M
P0[0]
Analog column mux input
17
I/O
I, M
P0[2]
Analog column mux input
18
I/O
I, M
P0[4]
Analog column mux input
19
I/O
I, M
P0[6]
Analog column mux input
VDD
Supply voltage
Power
AI, M, P0[7] 1
AI, M, P0[5] 2
AI, M, P0[3] 3
AI, M, P0[1] 4
VSS 5
I2C SCL, M, P1[7] 6
I2C SDA, M, P1[5] 7
M, P1[3] 8
I2C SCL, M, P1[1] 9
VSS 10
SSOP
20
19
18
17
16
15
14
13
12
11
VDD
P0[6], M, AI
P0[4], M, AI
P0[2], M, AI
P0[0], M, AI
XRES
P1[6], M
P1[4], M, EXTCLK
P1[2], M
P1[0], M, I2C SDA
Optional external clock input (EXTCLK)
16
20
Figure 3. CY8C21312 20-pin PSoC Device
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Note
4. These are the ISSP pins, which are not high Z when coming out of POR. See the PSoC Technical Reference Manual for details.
Document Number: 001-81890 Rev. *B
Page 8 of 38
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28-pin Part Pinout
Table 3. 28-pin Part Pinout (SSOP)
Type
Pin
No.
Digital
Analog
1
I/O
I, M
P0[7]
Analog column mux input
2
I/O
I, M
P0[5]
Analog column mux input
3
I/O
I, M
P0[3]
Analog column mux input, CMOD capacitor pin
4
I/O
I, M
P0[1]
Analog column mux input, CMOD capacitor pin
5
I/O
M
P2[7]
6
I/O
M
P2[5]
7
I/O
M
P2[3]
8
I/O
M
P2[1]
Name
Description
VSS
Ground connection
10
I/O
M
P1[7]
I2C SCL
11
I/O
M
P1[5]
I2C SDA
12
I/O
M
P1[3]
13
I/O
M
P1[1]
I2C SCL, ISSP-SCLK[5]
VSS
Ground connection
I2C SDA, ISSP-SDATA[5]
9
14
Power
Power
15
I/O
M
P1[0]
16
I/O
M
P1[2]
17
I/O
M
P1[4]
18
I/O
M
P1[6]
19
Input
AI, M, P0[7]
AI, M, P0[5]
AI, M, P0[3]
AI, M, P0[1]
M, P2[7]
M, P2[5]
M, P2[3]
M, P2[1]
VSS
I2C SCL, M, P1[7]
I2C SDA, M, P1[5]
M, P1[3]
I2C SCL, M, P1[1]
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSOP
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VDD
P0[6], M, AI
P0[4], M, AI
P0[2], M, AI
P0[0], M, AI
P2[6], M
P2[4], M
P2[2], M
P2[0], M
XRES
P1[6], M
P1[4], M, EXTCLK
P1[2], M
P1[0], M, I2C SDA
Optional EXTCLK
XRES Active high external reset with internal
pull-down
20
I/O
M
P2[0]
21
I/O
M
P2[2]
22
I/O
M
P2[4]
23
I/O
M
P2[6]
24
I/O
I, M
P0[0]
Analog column mux input
25
I/O
I, M
P0[2]
Analog column mux input
26
I/O
I, M
P0[4]
Analog column mux input
27
I/O
I, M
P0[6]
Analog column mux input
VDD
Supply voltage
28
Figure 4. CY8C21512 28-pin PSoC Device
Power
LEGEND: A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Note
5. These are the ISSP pins, which are not high Z when coming out of POR. See the PSoC Technical Reference Manual for details.
Document Number: 001-81890 Rev. *B
Page 9 of 38
CY8C21312
CY8C21512
Registers
Register Mapping Tables
This section lists the registers of the CY8C21x12 PSoC device.
For detailed register information, refer to the PSoC Technical
Reference Manual.
The PSoC device has a total register address space of 512
bytes. The register space is referred to as I/O space and is
divided into two banks, bank 0 and bank 1. The XIO bit in the
Flag register (CPU_F) determines which bank the user is
currently in. When the XIO bit is set to ‘1’, the user is in bank 1.
The register conventions specific to this section are listed in the
following table.
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.
Register Conventions
Convention
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Document Number: 001-81890 Rev. *B
Page 10 of 38
CY8C21312
CY8C21512
Table 4. Register Map 0 Table: User Space
Addr
Access
Name
(0,Hex)
PRT0DR
00
RW
PRT0IE
01
RW
PRT0GS
02
RW
PRT0DM2
03
RW
PRT1DR
04
RW
PRT1IE
05
RW
PRT1GS
06
RW
PRT1DM2
07
RW
PRT2DR
08
RW
PRT2IE
09
RW
PRT2GS
0A
RW
PRT2DM2
0B
RW
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
CSCNT_DR0
20
#
CSCNT_DR1
21
W
AMUX_CFG
CSCNT_DR2
22
RW
CSCMP_CR0
CSCNT_CR0
23
#
CSMOD0_DR0
24
#
CSCMP_CR1
CSMOD0_DR1
25
W
CSMOD0_DR2
26
RW
CSCMP_CR2
CSMOD0_CR0
27
#
CSMOD1_DR0
28
#
CSMOD1_DR1
29
W
CSREF_CR0
CSMOD1_DR2
2A
RW
CSMOD1_CR0
2B
#
LDB0_DR0
2C
#
TMP_DR0
LDB0_DR1
2D
W
TMP_DR1
LDB0_DR2
2E
RW
TMP_DR2
LDB0_CR0
2F
#
TMP_DR3
30
31
32
33
34
35
36
CSCMP_CR3
37
CSCMP_CR4
38
39
3A
3B
3C
3D
3E
3F
Blank fields are Reserved and must not be accessed.
Name
Document Number: 001-81890 Rev. *B
Addr
(0,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
RW
RW
#
RW
#
RW
RW
RW
RW
RW
RW
Addr
(0,Hex)
80
81
82
83
CSREF_CR1
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
# Access is bit specific.
Name
Access
Name
RW
CUR_PP
STK_PP
IDX_PP
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR3
INT_MSK3
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
CSCMP_CR5
CSCMP_CR6
RW
RW
RW
RW
RW
RW
RW
CPU_F
CPU_SCR1
CPU_SCR0
Addr
(0,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
RW
RW
RW
RW
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RC
W
RW
RW
RL
#
#
Page 11 of 38
CY8C21312
CY8C21512
Table 5. Register Map 1 Table: Configuration Space
Addr
Access
Name
(1,Hex)
PRT0DM0
00
RW
PRT0DM1
01
RW
PRT0IC0
02
RW
PRT0IC1
03
RW
PRT1DM0
04
RW
PRT1DM1
05
RW
PRT1IC0
06
RW
PRT1IC1
07
RW
PRT2DM0
08
RW
PRT2DM1
09
RW
PRT2IC0
0A
RW
PRT2IC1
0B
RW
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
CSCNT_CR1
20
RW
CSCLK_CR0
CSCNT_CR2
21
RW
CSCLK_CR1
CSCNT_CR3
22
RW
23
CSREF_CR2
CSMOD0_CR1
24
RW
CSCMP_CR7
CSMOD0_CR2
25
RW
CSMOD0_CR3
26
RW
CSREF_CR3
27
CSCMP_CR8
CSMOD1_CR1
28
RW
CSMOD1_CR2
29
RW
CSMOD1_CR3
2A
RW
2B
CSCLK_CR2
LDB0_FN
2C
RW
TMP_DR0
LDB0_IN
2D
RW
TMP_DR1
LDB0_OU
2E
RW
TMP_DR2
2F
TMP_DR3
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
Blank fields are Reserved and must not be accessed.
Name
Document Number: 001-81890 Rev. *B
Addr
(1,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Addr
(1,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
# Access is bit specific.
Name
Access
Name
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
MUX_CR0
MUX_CR1
MUX_CR2
MUX_CR3
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
VLT_CMP
CSREF_CR4
IMO_TR
ILO_TR
BDG_TR
ECO_TR
RW
RW
RW
RW
RW
RW
RW
CPU_F
CPU_SCR1
CPU_SCR0
Addr
(1,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
RW
W
W
RW
W
RL
#
#
Page 12 of 38
CY8C21312
CY8C21512
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 6. Absolute Maximum Ratings
Symbol
Description
Min
Typ
Max
Units
Notes
–55
+25
+125
°C
Higher
storage
temperatures
reduce
data
retention
time.
Recommended
storage
temperature is +25 °C ± 25 °C. Time
spent in storage at a temperature
greater than 65 °C counts toward
the FlashDR electrical specification
in Table 13 on page 17.
Maximum combined storage and
operational time at +125 °C is 7000
hours.
–
125
See
package
label
°C
See
package
label
–
72
Hours
Ambient temperature with power
applied
–40
–
+125
°C
VDD
Supply voltage on VDD relative to
VSS
–0.5
–
+6.0
V
VIO
DC input voltage
VSS – 0.5
–
VDD + 0.5
V
VIOZ
DC voltage applied to tristate
VSS – 0.5
–
VDD + 0.5
V
IMIO
Maximum current into any port
pin
–25
–
+50
mA
ESD
Electrostatic discharge (ESD)
voltage
2000
–
–
V
LU
Latch-up current
–
–
200
mA
Min
Typ
Max
Units
TSTG
Storage temperature
TBAKETEMP
Bake temperature
tBAKETIME
Bake time
TA
Human body model ESD.
Operating Temperature
Table 7. Operating Temperature
Symbol
Description
TA
Ambient temperature
–40
–
+125
°C
TJ
Junction temperature
–40
–
+135
°C
Document Number: 001-81890 Rev. *B
Notes
The temperature rise from ambient
to junction is package specific. See
Table 24 on page 30. The user must
limit the power consumption to
comply with this requirement.
Page 13 of 38
CY8C21312
CY8C21512
Electrical Specifications
This section presents the DC and AC electrical specifications of the automotive CY8C21x12 PSoC device. For the most up to date
electrical specifications, confirm that you have the most recent datasheet by going to the web at http//www.cypress.com.
Specifications are valid for –40 °C ≤ TA ≤ 125 °C and TJ ≤ 135 °C as specified, except where noted. Refer to Table 14 on page 18 for
the electrical specifications for the IMO using slow IMO (SLIMO) mode.
Figure 5. Voltage versus CPU Frequency
5. 25
Figure 6. IMO Frequency Trim Options
lid ng
Va rati n
e io
Op eg
R
4. 75
5.25
SLIMO
Mode = 1
SLIMO
Mode = 0
SLIMO
Mode = 1
SLIMO
Mode = 0
3.6
.
V
al
O
3.0
id
p
a
er
ti
g
Re
n
VDD Voltage (V)
VDD Voltage (V)
4.75
g
io
n
3.6
3.0
0
93 kHz
CPU Frequency
(nominal setting)
12 MHz
24 MHz
0
6 MHz
12 MHz
24 MHz
IMO Frequency
Document Number: 001-81890 Rev. *B
Page 14 of 38
CY8C21312
CY8C21512
DC Electrical Characteristics
DC Chip-Level Specifications
Table 8 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ TA ≤ 125 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 125 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and
are for design guidance only.
Table 8. DC Chip-Level Specifications
Symbol
VDD
IDD
Description
Supply voltage
Supply current, IMO = 24 MHz
Min
3
–
Typ
–
4
Max
5.25
8
IDD3
Supply current, IMO = 24 MHz
–
4
8
ISB
Sleep (mode) current with POR,
LVD, sleep timer, WDT, and ILO
active. Mid temperature range.
Sleep (mode) current with POR,
LVD, sleep timer, WDT, and ILO
active. High temperature range.
Reference voltage (Bandgap)
–
5
12
–
5
100
μA
1.25
1.30
1.35
V
ISBH
VREF
Units
Notes
V See Table 12 on page 16.
mA Conditions are VDD = 5.25 V,
–40 °C ≤ TA ≤ 125 °C, CPU = 3 MHz,
48 MHz disabled. VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 0.366 kHz.
mA Conditions are VDD = 3.3 V,
–40 °C ≤ TA ≤ 125 °C, CPU = 3 MHz,
48 MHz disabled. VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 0.366 kHz.
μA VDD = 5.25 V, –40 °C ≤ TA ≤ 55 °C.
VDD = 5.25 V, 55 °C ≤ TA ≤ 125 °C.
DC GPIO Specifications
Table 9 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ TA ≤ 125 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 125 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and
are for design guidance only.
Table 9. DC GPIO Specifications
Symbol
RPU
RPD
Description
Pull-up resistor
Pull-down resistor
Min
4
4
Typ
5.6
5.6
Max
8
8
VOH
High output level
VDD – 1.0
–
–
VOL
Low output level
–
–
0.75
IOH
High level source current
10
–
–
IOL
Low level sink current
25
–
–
VIL
VIH
VH
IIL
CIN
Input low level
Input high level
Input hysteresis
Input leakage (absolute value)
Capacitive load on pins as input
–
2.1
–
–
–
–
–
60
1
3.5
0.8
COUT
Capacitive load on pins as output
–
3.5
10
Document Number: 001-81890 Rev. *B
–
–
10
Units
Notes
kΩ
kΩ Also applies to the internal pull-down
resistor on the XRES pin
V IOH = 10 mA, VDD = 4.75 to 5.25 V (8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])).
V IOL = 25 mA, VDD = 4.75 to 5.25 V (8
total loads, 4 on even port pins (for
example, P0[2], P1[4]), 4 on odd port
pins (for example, P0[3], P1[5])).
mA VOH ≥ VDD – 1.0 V, see the limitations
of the total current in the note for VOH.
mA VOL ≤ 0.75 V, see the limitations of the
total current in the note for VOL.
V
V
mV
nA Gross tested to 1 μA.
pF Package and pin dependent.
TA = 25 °C.
pF Package and pin dependent.
TA = 25 °C.
Page 15 of 38
CY8C21312
CY8C21512
DC Operational Amplifier Specifications
Table 10 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ TA ≤ 125 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 125 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and
are for design guidance only.
Table 10. DC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
2.5
15
mV
VOSOA
Input offset voltage (absolute
value)
–
Notes
TCVOSOA
Average input offset voltage drift
–
10
–
μV/°C
IEBOA[6]
Input leakage current (Port 0
analog pins)
–
200
–
pA
Gross tested to 1 μA.
CINOA
Input capacitance (Port 0 analog
pins)
–
4.5
9.5
pF
Package and pin dependent.
TA = 25 °C.
VCMOA
Common mode voltage range
0.0
–
VDD – 1
V
GOLOA
Open loop gain
–
80
–
dB
ISOA
Amplifier supply current
–
10
100
μA
DC Analog Mux Bus Specifications
Table 11 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ TA ≤ 125 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 125 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and
are for design guidance only.
Table 11. DC Analog Mux Bus Specifications
Min
Typ
Max
Units
RSW
Symbol
Switch resistance to common
analog bus
Description
–
–
400
Ω
RVDD
Resistance of initialization switch
to VDD
–
–
800
Ω
Notes
DC POR and LVD Specifications
Table 12 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ TA ≤ 125 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 125 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and
are for design guidance only.
Table 12. DC POR and LVD Specifications
Symbol
Description
VPPOR0
VPPOR1
VPPOR2
VDD value for PPOR trip
PORLEV[1:0] = 00b
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
VDD value for LVD trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
Min
Typ
Max
Units
Notes
VDD must be greater than or equal
to 2.5 V during startup, reset from
the XRES pin, or reset from
watchdog.
–
–
–
2.36
2.82
4.55
2.40
2.95
4.70
V
V
V
2.40
2.85
2.95
3.06
4.37
4.50
4.62
4.71
2.45
2.92
3.02
3.13
4.48
4.64
4.73
4.81
2.51[7]
2.99[8]
3.09
3.20
4.55
4.75
4.83
4.95
V
V
V
V
V
V
V
V
Notes
6. Atypical behavior: IEBOA of Port 0 Pin 0 is below 1 nA at 25 °C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 pA.
7. Always greater than 50 mV above VPPOR0 (PORLEV[1:0] = 00b) for falling supply.
8. Always greater than 50 mV above VPPOR1 (PORLEV[1:0] = 01b) for falling supply.
Document Number: 001-81890 Rev. *B
Page 16 of 38
CY8C21312
CY8C21512
DC Programming Specifications
Table 13 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ TA ≤ 125 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 125 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and
are for design guidance only.
Table 13. DC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VDDP
VDD for programming and erase
4.5
5
5.5
V
This specification applies to the
functional requirements of external
programmer tools
VDDLV
Low VDD for verify
3
3.1
3.2
V
This specification applies to the
functional requirements of external
programmer tools
VDDHV
High VDD for verify
5.1
5.2
5.3
V
This specification applies to the
functional requirements of external
programmer tools
VDDIWRITE
Supply voltage for flash write
operation
3
–
5.25
V
This specification applies to this
device when it is executing internal
flash writes
IDDP
Supply current during
programming or verify
–
5
25
mA
VILP
Input low voltage during
programming or verify
–
–
0.8
V
VIHP
Input high voltage during
programming or verify
2.2
–
–
V
IILP
Input current when applying VILP
to P1[0] or P1[1] during
programming or verify
–
–
0.2
mA
Driving internal pull-down resistor.
IIHP
Input current when applying VIHP
to P1[0] or P1[1] during
programming or verify
–
–
1.5
mA
Driving internal pull-down resistor.
VOLV
Output low voltage during
programming or verify
–
–
0.75
V
VOHV
Output high voltage during
programming or verify
VDD – 1
–
VDD
V
FlashENPB
Flash endurance (per block) [9]
FlashENT
Flash endurance (total) [9, 10]
FlashDR
Flash data retention
[11]
100
–
–
–
Erase/write cycles per block.
12,800
–
–
–
Erase/write cycles.
15
–
–
Years
Notes
9. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor, and feed the result to the
temperature argument before writing. Refer to the Flash APIs Application Note AN2015 for more information.
10. The maximum total number of allowed erase/write cycles is the minimum FlashENPB value multiplied by the number of flash blocks in the device.
11. Flash data retention based on the use condition of ≤ 7000 hours at TA ≤ 125 °C and the remaining time at TA ≤ 65 °C.
Document Number: 001-81890 Rev. *B
Page 17 of 38
CY8C21312
CY8C21512
AC Electrical Characteristics
AC Chip-Level Specifications
Table 14 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ TA ≤ 125 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 125 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and
are for design guidance only.
Table 14. AC Chip-Level Specifications
Min
Typ
Max
FIMO24
Symbol
IMO frequency for 24 MHz
Description
22.8 [12]
24
25.2 [12]
Units
MHz Trimmed using factory trim values.
See Figure 6 on page 14. SLIMO
mode = 0.
Notes
FIMO6
IMO frequency for 6 MHz
5.5 [12]
6
6.5 [12]
MHz Trimmed using factory trim values.
See Figure 6 on page 14. SLIMO
mode = 1.
FCPU1
CPU frequency (5 V VDD
nominal)
0.09 [12]
12
12.6 [12]
MHz SLIMO mode = 0.
FBLK5
Digital PSoC block
frequency0(5 V VDD nominal)
0
24
25.2 [12]
MHz Refer to Table 17 on page 20.
FBLK33
Digital PSoC block
frequency0(3.3 V VDD nominal)
0
24
25.2 [12]
MHz Refer to Table 17 on page 20.
F32K1
ILO frequency
15
32
64
kHz This specification applies when the
ILO has been trimmed.
F32KU
ILO untrimmed frequency
5
–
100
kHz After a reset and before the M8C
processor starts to execute, the ILO
is not trimmed.
tXRST
External reset pulse width
10
–
–
μs
DC24M
24 MHz duty cycle
40
50
60
%
DCILO
ILO duty cycle
20
50
80
%
Step24M
24 MHz trim step size
–
50
–
kHz
FMAX
Maximum frequency of signal on
row input or row output.
–
–
12.6 [12]
MHz
SRPOWERUP
Power supply slew rate
–
–
250
tPOWERUP
Time between end of POR state
and CPU code execution
–
16
100
ms
tJIT_IMO[13]
24 MHz IMO cycle-to-cycle jitter
(RMS)
–
200
700
ps
24 MHz IMO long term N
cycle-to-cycle jitter (RMS)
–
300
900
24 MHz IMO period jitter (RMS)
–
100
400
V/ms VDD slew rate during power up.
Power-up from 0 V.
N = 32
Notes
12. Accuracy derived from Internal Main Oscillator with appropriate trim for VDD range.
13. Refer to Cypress Jitter Specifications document, Understanding Datasheet Jitter Specifications for Cypress Timing Products, for more information.
Document Number: 001-81890 Rev. *B
Page 18 of 38
CY8C21312
CY8C21512
AC GPIO Specifications
Table 15 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ TA ≤ 125 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 125 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and
are for design guidance only.
Table 15. AC GPIO Specifications
Symbol
Description
Min
Typ
Max
FGPIO
GPIO operating frequency
0
–
tRISEF33
Rise time, normal strong mode,
Cload = 50 pF
2
–
30
2
–
22
Fall time, normal strong mode,
Cload = 50 pF
2
–
30
2
–
22
tRISES
Rise time, slow strong mode,
Cload = 50 pF
7
27
tFALLS
Fall time, slow strong mode,
Cload = 50 pF
7
22
tRISEF5
tFALLF33
tFALLF5
12.6
Units
[14]
Notes
MHz Normal Strong Mode
ns
10% to 90%
ns
10% to 90%
–
ns
10% to 90%
–
ns
10% to 90%
Figure 7. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
tRISEF
tRISES
tFALLF
tFALLS
AC Operational Amplifier Specifications
Table 16 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ TA ≤ 125 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 125 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and
are for design guidance only.
Table 16. AC Operational Amplifier Specifications
Symbol
tCOMP
Description
Comparator mode response
time, 50 mV overdrive
Min
Typ
Max
Units
–
–
150
ns
Notes
Note
14. Accuracy derived from Internal Main Oscillator with appropriate trim for VDD range.
Document Number: 001-81890 Rev. *B
Page 19 of 38
CY8C21312
CY8C21512
AC Digital Block Specifications
Table 17 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ TA ≤ 125 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 125 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and
are for design guidance only.
Table 17. AC Digital Block Specifications
Function
Description
All functions
Block input clock frequency
Timer
Input clock frequency
Max
Units
[15]
MHz
–
25.2
No capture
–
–
25.2 [15]
MHz
With capture
–
–
25.2 [15]
MHz
–
–
ns
50
[16]
Notes
Input clock frequency
No enable input
–
–
25.2 [15]
MHz
With enable input
–
–
25.2 [15]
MHz
–
–
ns
Enable input pulse width
Dead Band
Typ
–
Capture pulse width
Counter
Min
50
[16]
Kill pulse width
Asynchronous restart mode
20
–
–
ns
Synchronous restart mode
50 [16]
–
–
ns
Disable mode
50 [16]
–
–
ns
Input clock frequency
–
–
25.2 [15]
MHz
CRCPRS
(PRS Mode)
Input clock frequency
–
–
25.2 [15]
MHz
CRCPRS
(CRC Mode)
Input clock frequency
–
–
25.2 [15]
MHz
SPIM
Input clock frequency
–
–
4.2 [15]
MHz The SPI serial clock (SCLK)
frequency is equal to the input clock
frequency divided by 2.
SPIS
Input clock (SCLK) frequency
–
–
2.1 [15]
MHz The input clock is the SPI SCLK in
SPIS mode.
50 [16]
–
–
Width of SS_ negated between
transmissions
ns
Transmitter
Input clock frequency
–
–
8.4 [15]
MHz The baud rate is equal to the input
clock frequency divided by 8.
Receiver
Input clock frequency
–
–
25.2 [15]
MHz The baud rate is equal to the input
clock frequency divided by 8.
Notes
15. Accuracy derived from IMO with appropriate trim for VDD range.
16. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 001-81890 Rev. *B
Page 20 of 38
CY8C21312
CY8C21512
AC External Clock Specifications
Table 18 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ TA ≤ 125 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 125 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and
are for design guidance only.
Table 18. AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT
Frequency
0.093
–
24.24
MHz
–
High period
20.6
–
5300
ns
–
Low period
20.6
–
–
ns
–
Power-up IMO to switch
150
–
–
μs
Notes
AC Programming Specifications
Table 19 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ TA ≤ 125 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 125 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and
are for design guidance only.
Table 19. AC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
1
–
20
ns
Fall time of SCLK
1
–
20
ns
Data setup time to falling edge of
SCLK
40
–
–
ns
tHSCLK
Data hold time from falling edge
of SCLK
40
–
–
ns
FSCLK
Frequency of SCLK
0
–
8
MHz
tRSCLK
Rise time of SCLK
tFSCLK
tSSCLK
[17]
Notes
tERASEB
Flash erase time (block)
–
10
40
tWRITE
Flash block write time
–
40
160 [17]
ms
ms
tDSCLK
Data Out delay from falling edge
of SCLK
–
–
50
ns
tPRGH
Total flash block program time
(tERASEB + tWRITE), hot
–
–
100 [17]
ms
TJ ≥ 0 °C
tPRGC
Total flash block program time
(tERASEB + tWRITE), cold
–
–
200 [17]
ms
TJ < 0 °C
Note
17. For the full temperature range, the user must employ a temperature sensor user module (FlashTemp) or other temperature sensor, and feed the result to the
temperature argument before writing. Refer to the Flash APIs Application Note AN2015 for more information.
Document Number: 001-81890 Rev. *B
Page 21 of 38
CY8C21312
CY8C21512
AC I2C Specifications
Table 20 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C ≤ TA ≤ 125 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 125 °C, respectively. Typical parameters apply to 5 V or 3.3 V at 25 °C and
are for design guidance only.
Table 20. AC Characteristics of the I2C SDA and SCL Pins
Symbol
Standard Mode
Description
Fast Mode
Units
Min
Max
Min
Max
0
100 [18]
0
400 [18]
kHz
FSCLI2C
SCL clock frequency
tHDSTAI2C
Hold time (repeated) START
condition. After this period, the
first clock pulse is generated.
4.0
–
0.6
–
μs
tLOWI2C
LOW period of the SCL clock
4.7
–
1.3
–
μs
tHIGHI2C
HIGH period of the SCL clock
4.0
–
0.6
–
μs
tSUSTAI2C
Setup time for a repeated START
condition
4.7
–
0.6
–
μs
tHDDATI2C
Data hold time
0
–
0
–
μs
[19]
tSUDATI2C
Data setup time
250
–
–
ns
tSUSTOI2C
Setup time for STOP condition
4.0
–
0.6
–
μs
tBUFI2C
Bus free time between a STOP
and START condition
4.7
–
1.3
–
μs
tSPI2C
Pulse width of spikes are
suppressed by the input filter.
–
–
0
50
ns
100
Notes
Figure 8. Definition for Timing for Fast/Standard Mode on the I2C Bus
I2C_SDA
tSUDATI2C
tSPI2C
tHDDATI2C tSUSTAI2C
tHDSTAI2C
tBUFI2C
I2C_SCL
tHIGHI2C
S
START Condition
tLOWI2C
tSUSTOI2C
Sr
Repeated START Condition
P
S
STOP Condition
Notes
18. FSCLI2C is derived from SysClk of the PSoC. This specification assumes that SysClk is operating at 24 MHz, nominal. If SysClk is at a lower frequency, then the
FSCLI2C specification adjusts accordingly
19. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSUDATI2C ≥ 250 ns must then be met. This is automatically the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line trmax + tSUDATI2C = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 001-81890 Rev. *B
Page 22 of 38
CY8C21312
CY8C21512
Development Tool Selection
with a control boards for CY8C20x34 and CY8C21x34 devices
as well as a breadboard module and a button(5)/slider module.
This section presents the development tools available for the
CY8C21x12 family.
The CY8C21x34 on-chip debugger device that is part of this kit
is capable of emulating CY8C21x12 devices as well. Therefore,
this kit can be used to evaluate and develop projects for
CY8C21x12 devices.
Software
PSoC Designer
At the core of the PSoC development software suite is
PSoC Designer. Utilized by thousands of PSoC developers, this
robust software has been facilitating PSoC designs for years.
PSoC Designer
is
available
free
of
charge
at
http://www.cypress.com. PSoC Designer comes with a free C
compiler.
PSoC Programmer
Flexible enough to be used on the bench in development, yet
suitable for factory programming, PSoC Programmer works
either as a standalone programming application or it can operate
directly from PSoC Designer. PSoC Programmer software is
compatible with both PSoC ICE-Cube in-circuit emulator and
PSoC MiniProg. PSoC programmer is available free of charge at
http://www.cypress.com.
Development Kits
All development kits can be purchased from the Cypress Online
Store. The online store also has the most up-to-date information
on kit contents, descriptions, and availability.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit supports in-circuit emulation, and the software
interface allows you to run, halt, and single step the processor,
and view the contents of specific memory locations. Advanced
emulation features are also supported through PSoC Designer.
The kit includes:
Evaluation Tools
All evaluation tools can be purchased from the Cypress Online
Store.
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, an RS-232 port, and
plenty of breadboarding space to meet all of your evaluation
needs. The kit includes:
■
Evaluation board with LCD module
■
MiniProg programming unit
■
Two 28-pin CY8C29466-24PXI PDIP PSoC device samples
■
PSoC Designer software CD
■
Getting Started guide
■
USB 2.0 cable
CY3210-21X34 Evaluation Pod (EvalPod)
The CY3210-21X34 PSoC EvalPods are pods that connect to
the ICE in-circuit emulator (CY3215-DK kit) to allow debugging
capability. They can also function as a standalone device without
debugging capability. The EvalPod has a 28-pin DIP footprint on
the bottom for easy connection to development kits or other
hardware. The top of the EvalPod has prototyping headers for
easy connection to the device's pins. CY3210-21X34 provides
evaluation of the CY8C21x34 PSoC device family.
■
ICE-Cube unit
■
28-pin PDIP emulation pod for CY8C29466-24PXI
■
Two 28-pin CY8C29466-24PXI PDIP PSoC device samples
■
PSoC designer software CD
Device Programmers
■
ISSP cable
All device programmers can be purchased from the Cypress
Online Store.
■
MiniEval socket programming and evaluation board
■
Backward compatibility cable (for connecting to legacy pods)
■
Universal 110/220 power supply (12 V)
■
European plug adapter
■
USB 2.0 cable
■
MiniProg programming unit
■
Getting Started guide
■
MiniEval socket programming and evaluation board
■
Development kit registration form
■
28-pin CY8C29466-24PXI PDIP PSoC device sample
CY3280-BK1
■
PSoC Designer software CD
The CY3280-BK1 Universal CapSense Control Kit is designed
for easy prototyping and debug of CapSense designs with
pre-defined control circuitry and plug-in hardware. The kit comes
■
Getting Started guide
■
USB 2.0 cable
Document Number: 001-81890 Rev. *B
The CY8C21x34 on-chip debugger device that is part of this kit
is capable of emulating CY8C21x12 devices as well. Therefore,
this kit can be used to evaluate CY8C21x12 devices.
CY3210-MiniProg1
The CY3210-MiniProg1 kit allows a user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
via a provided USB 2.0 cable. The kit includes:
Page 23 of 38
CY8C21312
CY8C21512
Accessories (Emulation and Programming)
Table 21. Emulation and Programming Accessories
Part Number
Pin Package
Pod Kit [20]
Foot Kit [21]
CY8C21312-12PVXE
20-pin SSOP
CY3250-21X34
CY3250-20SSOP-FK
CY8C21512-12PVXE
28-pin SSOP
CY3250-21X34
CY3250-28SSOP-FK
Adapter [22]
Adapters are available at
http://www.emulation.com.
Notes
20. Pod kit contains an emulation pod, a flex-cable (connects the pod to the ICE), two feet, and device samples.
21. Foot kit includes surface mount feet that can be soldered to the target PCB.
22. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters are available at
http://www.emulation.com.
Document Number: 001-81890 Rev. *B
Page 24 of 38
CY8C21312
CY8C21512
Ordering Information
The following table lists the CY8C21x12 PSoC device’s key package features and ordering codes.
SRAM
(Bytes)
Temperature
Range
Limited Digital
Blocks
CapSense Blocks
Digital I/O
Pins
Analog
Inputs
Analog
Outputs
XRES Pin
20-pin (210-Mil) SSOP
CY8C21312-12PVXE
8K
512
–40 °C to +125 °C
1
1
16
16
0
Yes
20-pin (210-Mil) SSOP
(Tape and Reel)
CY8C21312-12PVXET
8K
512
–40 °C to +125 °C
1
1
16
16
0
Yes
28-pin (210-Mil) SSOP
CY8C21512-12PVXE
8K
512
–40 °C to +125 °C
1
1
24
24
0
Yes
28-pin (210-Mil) SSOP
(Tape and Reel)
CY8C21512-12PVXET
8K
512
–40 °C to +125 °C
1
1
24
24
0
Yes
Package
Ordering
Code
Flash
(Bytes)
Table 22. PSoC Device Key Features and Ordering Information
Ordering Code Definitions
CY
8
C
21 xxx - 12 PV
X
E
T
X = blank or T
blank = Tube; T = Tape and Reel
Temperature Range: E = Automotive Extended = –40 °C to +125 °C
Pb-free
Package Type:
PV = 20-pin SSOP
CPU Speed: 12 MHz
Part Number: xxx = 312 or 512
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = PSoC
Company ID: CY = Cypress
Document Number: 001-81890 Rev. *B
Page 25 of 38
CY8C21312
CY8C21512
Packaging Information
This section illustrates the packaging specifications for the CY8C21x12 PSoC device, along with the thermal impedances for each
package.
Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of
the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com.
Packaging Dimensions
Figure 9. 20-pin SSOP (210 Mils) O20.21 Package Outline, 51-85077
51-85077 *E
Document Number: 001-81890 Rev. *B
Page 26 of 38
CY8C21312
CY8C21512
Packaging Information (continued)
Figure 10. 28-pin SSOP (210 Mils) O28.21 Package Outline, 51-85079
51-85079 *E
Document Number: 001-81890 Rev. *B
Page 27 of 38
CY8C21312
CY8C21512
Packaging Information (continued)
Tape and Reel Information
Figure 11. 20-pin SSOP (209 Mils) – Advantek Carrier Tape Drawing, 51-51101
51-51101 *C
Document Number: 001-81890 Rev. *B
Page 28 of 38
CY8C21312
CY8C21512
Packaging Information (continued)
Figure 12. 28-pin SSOP (209 Mils) (C-Pak) Carrier Tape Drawing, 51-51100
51-51100 *C
Table 23. Tape and Reel Specifications
Package
20-pin SSOP
28-pin SSOP
Cover Tape Width
(mm)
13.3
13.3
Document Number: 001-81890 Rev. *B
Hub Size (inches)
4
7
Minimum Leading
Empty Pockets
42
42
Minimum Trailing Standard Full Reel
Empty Pockets
Quantity
25
2000
25
1000
Page 29 of 38
CY8C21312
CY8C21512
Thermal Impedances
Solder Reflow Specifications
Table 24. Thermal Impedances per Package
Package
20-pin SSOP
28-pin SSOP
Typical θJA
117 °C/W
96 °C/W
[23]
Typical θJC
41 °C/W
39 °C/W
Table 25 shows the solder reflow temperature limits that must
not be exceeded.
Table 25. Solder Reflow Specifications
Package
Maximum Peak
Temperature (TC)
Maximum Time
above TC – 5 °C
20-pin SSOP
260 °C
30 seconds
28-pin SSOP
260 °C
30 seconds
Note
23. TJ = TA + Power x θJA
Document Number: 001-81890 Rev. *B
Page 30 of 38
CY8C21312
CY8C21512
Reference Information
Reference Documents
CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34,
CY8C21x23, CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip Technical
Reference Manual (TRM) (001-14463)
Design Aids – Reading and Writing PSoC® Flash – AN2015 (001-40459)
Document Number: 001-81890 Rev. *B
Page 31 of 38
CY8C21312
CY8C21512
Acronyms
Table 26. Acronyms Used in this Datasheet (continued)
Table 26 lists the acronyms that are used in this document.
Table 26. Acronyms Used in this Datasheet
Acronym
Description
Acronym
Description
SSOP
shrink small-outline package
UART
universal asynchronous receiver / transmitter
USB
universal serial bus
WDT
watchdog timer
XRES
external reset
AC
alternating current
AEC
automotive electronics council
ADC
analog-to-digital converter
API
application programming interface
CPU
central processing unit
CRC
cyclic redundancy check
DAC
digital-to-analog converter
Units of Measure
DC
direct current or duty cycle
DIP
dual in-line package
The following table lists the units of measure that are used in this
document.
EEPROM
electrically erasable programmable read only
memory
ESD
electrostatic discharge
EXTCLK
external clock
GPIO
general-purpose input/output
GUI
graphical user interface
I2C
inter-integrated circuit
ICE
in-circuit emulator
IDE
integrated development environment
ILO
internal low-speed oscillator
IMO
internal main oscillator
I/O
input/output
ISSP
in-system serial programming
LCD
liquid crystal display
LED
light-emitting diode
LVD
low voltage detect
MCU
microcontroller unit
MIPS
million instructions per second
PCB
printed circuit board
PDIP
plastic dual in-line package
PLL
phase-locked loop
POR
power-on reset
PPOR
precision power-on reset
PSoC®
programmable system-on-chip
PWM
pulse width modulator
SCL /
SCLK
serial clock
SDA
serial data
SLIMO
slow internal main oscillator
SPI
serial peripheral interface
SRAM
static random access memory
Document Number: 001-81890 Rev. *B
Document Conventions
Table 27. Units of Measure
Symbol
°C
dB
KB
kbit
kHz
kΩ
MHz
μA
μs
μV
mA
ms
mV
nA
ns
Ω
%
pF
ps
V
W
Unit of Measure
degree Celsius
decibel
kilobyte
kilobit
kilohertz
kilohm
megahertz
microampere
microsecond
microvolt
milliampere
millisecond
millivolt
nanoampere
nanosecond
ohm
percent
picofarad
picosecond
volt
watt
Numeric Conventions
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, ‘01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or ‘0x’ are in
decimal format.
Page 32 of 38
CY8C21312
CY8C21512
Glossary
active high
1. A logic signal having its asserted state as the logic 1 state.
2. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks
The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks.
These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more.
analog-to-digital
converter (ADC)
A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts
a voltage to a digital number. The digital-to-analog converter (DAC) performs the reverse operation.
Application
programming
interface (API)
A series of software routines that comprise an interface between a computer application and lower level services
and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that
create software applications.
asynchronous
A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
bandgap
reference
A stable voltage reference design that matches the positive temperature coefficient of VT with the negative
temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference.
bandwidth
1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is
sometimes represented more specifically as, for example, full width at half maximum.
bias
1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to
operate the device.
block
1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or
an analog PSoC block.
buffer
1. A storage area for data that is used to compensate for a speed difference, when transferring data from one
device to another. Usually refers to an area reserved for I/O operations, into which data is read, or from which
data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received
from an external device.
3. An amplifier used to lower the output impedance of a system.
bus
1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing
patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented using vector
notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock
The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to
synchronize different logic blocks.
comparator
An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy
predetermined amplitude requirements.
compiler
A program that translates a high level language, such as C, into machine language.
configuration
space
In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’.
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crystal oscillator
An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less
sensitive to ambient temperature than other circuit components.
cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear feedback shift
check (CRC)
register. Similar calculations may be used for a variety of other purposes such as data compression.
data bus
A bi-directional set of signals used by a computer to convey information from a memory location to the central
processing unit and vice versa. More generally, a set of signals used to convey data between digital functions.
debugger
A hardware and software system that allows you to analyze the operation of the system under development. A
debugger usually allows the developer to step through the firmware one step at a time, set break points, and
analyze memory.
dead band
A period of time when neither of two or more signals are in their active state or in transition.
digital blocks
The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator,
pseudo-random number generator, or SPI.
digital-to-analog
converter (DAC)
A device that changes a digital signal to an analog signal of corresponding magnitude. The analog-to-digital
converter (ADC) performs the reverse operation.
duty cycle
The relationship of a clock period high time to its low time, expressed as a percent.
emulator
Duplicates (provides an emulation of) the functions of one system with a different system, so that the second
system appears to behave like the first system.
external reset
(XRES)
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop
and return to a pre-defined state.
flash
An electrically programmable and erasable, non-volatile technology that provides you the programmability and
data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is
off.
flash block
The smallest amount of flash ROM space that may be programmed at one time and the smallest amount of flash
space that may be protected.
frequency
The number of cycles or events per unit of time, for a periodic function.
gain
The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually
expressed in dB.
I2C
A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). It is used to connect
low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery
control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses
only two bi-directional pins, clock and data, both running at the VDD supply voltage and pulled high with resistors.
The bus operates up to100 kbits/second in standard mode and 400 kbits/second in fast mode.
ICE
The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging
device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt
A suspension of a process, such as the execution of a computer program, caused by an event external to that
process, and performed in such a way that the process can be resumed.
interrupt service
routine (ISR)
A block of code that normal code execution is diverted to when the CPU receives a hardware interrupt. Many
interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends
with the RETI instruction, returning the device to the point in the program where it left normal program execution.
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jitter
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls below a selected threshold.
(LVD)
M8C
An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by
interfacing to the flash, SRAM, and register space.
master device
A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in
width, the master device is the one that controls the timing for data exchanges between the cascaded devices
and an external interface. The controlled device is called the slave device.
microcontroller
An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a
microcontroller typically includes memory, timing circuits, and I/O circuitry. The reason for this is to permit the
realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This
in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for
general-purpose computation as is a microprocessor.
mixed-signal
The reference to a circuit containing both analog and digital techniques and components.
modulator
A device that imposes a signal on a carrier.
noise
1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator
A circuit that may be crystal controlled and is used to generate a clock frequency.
parity
A technique for testing transmitted data. Typically, a binary digit is added to the data to make the sum of all the
digits of the binary data either always even (even parity) or always odd (odd parity).
phase-locked
loop (PLL)
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference
signal.
pinouts
The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their
physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between
schematic and PCB design (both being computer generated files) and may also involve pin names.
port
A group of pins, usually eight.
power-on reset
(POR)
A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is one type of hardware
reset.
PSoC®
Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-on-Chip™ is a trademark
of Cypress.
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
An output in the form of duty cycle which varies as a function of the applied value.
modulator (PWM)
RAM
An acronym for random access memory. A data-storage device from which data can be read out and new data
can be written in.
register
A storage device with a specific capacity, such as a bit or byte.
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reset
A means of bringing a system back to a known state. See hardware reset and software reset.
ROM
An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot
be written in.
serial
1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time
The time it takes for an output signal or value to stabilize after the input has changed from one value to another.
shift register
A memory storage device that sequentially shifts a word either left or right to output a stream of serial data.
slave device
A device that allows another device to control the timing for data exchanges between two devices. Or when
devices are cascaded in width, the slave device is the one that allows another device to control the timing of data
exchanges between the cascaded devices and an external interface. The controlling device is called the master
device.
SRAM
An acronym for static random access memory. A memory device where you can store and retrieve data at a high
rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged
until it is explicitly altered or until power is removed from the device.
SROM
An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate
circuitry, and perform flash operations. The functions of the SROM may be accessed in normal user code,
operating from flash.
stop bit
A signal following a character or block that prepares the receiving device to receive the next character or block.
synchronous
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
tristate
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any
value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit,
allowing another output to drive the same net.
UART
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits.
user modules
Pre-built, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower
level analog and digital PSoC blocks. User modules also provide high level API (Application Programming
Interface) for the peripheral function.
user space
The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal
program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during
the initialization phase of the program.
VDD
A name for a power net meaning "voltage drain”. The most positive power supply signal. Usually 5 V or 3.3 V.
VSS
A name for a power net meaning "voltage source." The most negative power supply signal.
watchdog timer
A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.
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Document History Page
Document Title: CY8C21312/CY8C21512, Automotive Extended PSoC® Programmable System-on-Chip™
Document Number: 001-81890
Rev.
ECN No.
Orig. of
Change
Submission
Date
**
3705964
MASJ
08/09/2012
New data sheet.
*A
4008934
KAUL
05/23/2013
Updated Features.
Description of Change
Updated PSoC Functional Overview (Updated The Digital System).
Updated Electrical Specifications (Updated DC Electrical Characteristics
(Updated DC Chip-Level Specifications (Updated Table 8), updated DC GPIO
Specifications (Updated Table 9), updated DC Operational Amplifier
Specifications, updated DC Analog Mux Bus Specifications, updated DC POR
and LVD Specifications, updated DC Programming Specifications (Updated
Table 13)), updated AC Electrical Characteristics (Updated AC Chip-Level
Specifications (Updated Table 14), updated AC GPIO Specifications (Updated
Table 15), updated AC Operational Amplifier Specifications, updated AC Digital
Block Specifications (Updated Table 17), updated AC External Clock
Specifications, updated AC Programming Specifications, updated AC I2C
Specifications)).
Updated Packaging Information:
Updated Tape and Reel Information:
spec 51-51101 – Changed revision from *B to *C.
*B
4265204
JICG
Document Number: 001-81890 Rev. *B
01/28/2014
Removed ‘CY3207ISSP In-System Serial Programmer (ISSP)’ section.
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Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
Products
Automotive
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PSoC Solutions
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© Cypress Semiconductor Corporation, 2012-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-81890 Rev. *B
Revised January 29, 2014
All products and company names mentioned in this document may be the trademarks of their respective holders.
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