CY8C21345
CY8C22345
CY8C22545
PSoC® Programmable System-on-Chip
Features
■
■
■
Powerful Harvard-architecture processor:
❐ M8C processor speeds up to 24 MHz
❐ 8 × 8 multiply, 32-bit accumulate
❐ Low power at high speed
❐ 3.0 V to 5.25 V operating voltage
❐ Industrial temperature range: –40 °C to +85 °C
Advanced peripherals (PSoC® Blocks)
❐ Six analog type “E” PSoC blocks provide:
• Single or dual 8-Bit ADC
• Comparators (up to four)
❐ Up to eight digital PSoC blocks provide:
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width
modulators (PWMs)
• One shot, multi-shot mode support in timers and PWMs
• PWM with deadband support in one digital block
• Shift register, CRC, and PRS modules
• Full duplex UART
• Multiple SPI masters or slaves, variable data length
Support: 8- to 16-Bit
• Can be connected to all GPIO pins
❐ Complex peripherals by combining blocks
❐ Shift function support for FSK detection
❐ Powerful synchronize feature support. Analog module
operations can be synchronized by digital blocks or external
signals.
• CSD_CLK: 1/2/4/8/16/32/128/256 derive from SYSCLK
• CNT_CLK: 1/2/4/8 Derive from CSD_CLK
❐ Dedicated 16-bit timers/counters for CapSense scanning
❐ Support dual CSD channels simultaneous scanning
■
Programmable pin configurations:
❐ 25 mA sink, 10 mA source on all GPIOs
❐ Pull-up, pull-down, high Z, Strong, or open-drain drive modes
on all GPIOs
❐ Up to 38 analog inputs on GPIOs
❐ Configurable interrupt on all GPIOs
■
Additional system resources:
2
❐ I C slave, master, and multimaster to 400 kHz
❐ Supports hardware addressing feature
❐ Watchdog and sleep timers
❐ User configurable low voltage detection
❐ Integrated supervisory circuit
❐ On-Chip precision voltage reference
❐ Supports RTC block into digital peripheral logic
Top Level Block Diagram
Port 4
Global Digital Interconnect
SRAM
1K
High speed 10-bit SAR ADC with sample and hold optimized for
■
SROM
Analog
Drivers
Precision, programmable clocking:
[1] 24/48 MHz oscillator across the industrial
❐ Internal ± 5%
temperature range
❐ High accuracy 24 MHz with optional 32 kHz crystal and PLL
❐ Optional external oscillator, up to 24 MHz
❐ Internal/external oscillator for watchdog and sleep
Global Analog Interconnect
Flash 16K
CPU Core (M8C)
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
ANALOG SYSTEM
DIGITAL SYSTEM
Digital Block Array
Analog
Ref
Analog Input
Muxing(L,R)
DBC DBC DCC DCC
=
ROW 1
Flexible on-chip memory:
❐ Up to 16 KB flash program storage 50,000 erase/write cycles
❐ Up to 1-KB SRAM data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ EEPROM emulation in flash
Analog Block Array
DBC DBC DCC DCC
ROW 2
System Bus
■
Port 2 Port 1 Port 0
PSoC Core
embedded control
■
Port 3
Optimized CapSense® resource:
❐ Two IDAC support up to 640 µA source current to replace
external resistor
❐ Two dedicated clock resources for CapSense:
CapSense
Digital Resource
Digital
Clocks
MACs
CTE
CTE
SCE
SCE
CTE
CTE
10-bit SAR
ADC
I2C
POR and LVD
System Resets
Internal
Voltage
Ref.
SYSTEM RESOURCES
Errata: For information on silicon errata, see “Errata” on page 35. Details include trigger conditions, devices affected, and proposed workaround.
Note
1. Errata: When the device is operated within 0 °C to 70 °C, the frequency tolerance is reduced to ±2.5%, but if operated at extreme temperature (below 0 °C or above
70 °C), frequency tolerance deviates from ±2.5% to ±5%. For more information, see “Errata” on page 35.
Cypress Semiconductor Corporation
Document Number: 001-43084 Rev. *V
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 17, 2014
CY8C21345
CY8C22345
CY8C22545
Contents
PSoC Functional Overview .............................................. 3
PSoC Core .................................................................. 3
Digital System ............................................................. 3
Analog System ............................................................ 4
Additional System Resources ..................................... 4
PSoC Device Characteristics ...................................... 5
Getting Started .................................................................. 5
Application Notes ........................................................ 5
Development Kits ........................................................ 5
Training ....................................................................... 5
CYPros Consultants .................................................... 5
Solutions Library .......................................................... 5
Technical Support ....................................................... 5
Development Tools .......................................................... 6
PSoC Designer Software Subsystems ........................ 6
Designing with PSoC Designer ....................................... 7
Select User Modules ................................................... 7
Configure User Modules .............................................. 7
Organize and Connect ................................................ 7
Generate, Verify, and Debug ....................................... 7
Pinouts .............................................................................. 8
CY8C22345, CY8C21345 28-pin SOIC ...................... 8
CY8C22545 44-pin TQFP ........................................... 9
Registers ......................................................................... 10
Register Conventions ................................................ 10
Register Mapping Tables .......................................... 10
Document Number: 001-43084 Rev. *V
Electrical Specifications ................................................ 13
Absolute Maximum Ratings ....................................... 14
Operating Temperature ............................................. 14
DC Electrical Characteristics ..................................... 15
AC Electrical Characteristics ..................................... 21
Packaging Information ................................................... 27
Thermal Impedances ................................................. 28
Solder Reflow Specifications ..................................... 28
Ordering Information ...................................................... 28
Ordering Code Definitions ......................................... 28
Acronyms ........................................................................ 29
Reference Documents .................................................... 29
Document Conventions ................................................. 30
Units of Measure ....................................................... 30
Numeric Conventions .................................................... 30
Glossary .......................................................................... 30
Errata ............................................................................... 35
Part Numbers Affected .............................................. 35
CY8C21x45, CY8C22x45 Qualification Status .......... 35
Errata Summary ........................................................ 35
Document History Page ................................................. 37
Sales, Solutions, and Legal Information ...................... 40
Worldwide Sales and Design Support ....................... 40
Products .................................................................... 40
PSoC® Solutions ...................................................... 40
Cypress Developer Community ................................. 40
Technical Support ..................................................... 40
Page 2 of 40
CY8C21345
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PSoC Functional Overview
The PSoC family consists of many On-Chip Controller devices.
These devices are designed to replace multiple traditional
MCU-based system components with one low cost single-chip
programmable device. PSoC devices include configurable
blocks of analog and digital logic, and programmable
interconnects. This architecture enables the user to create
customized peripheral configurations that match the
requirements of each individual application. Additionally, a fast
CPU, Flash program memory, SRAM data memory, and
configurable I/O are included in a range of convenient pinouts
and packages.
Digital System
The Digital System is composed of eight digital PSoC blocks.
Each block is an 8-bit resource that may be used alone or
combined with other blocks to form 8, 16, 24, and 32-bit
peripherals, which are called user module references.
Figure 1. Digital System Block Diagram
Port 3
Port 2
To System Bus
Digital Clocks
From Core
The PSoC architecture, shown in Figure 1, consists of four main
areas: PSoC Core, Digital System, Analog System, and System
Resources. Configurable global busing allows the combining of
all the device resources into a complete custom system. The
PSoC family can have up to five I/O ports connecting to the
global digital and analog interconnects, providing access to eight
digital blocks and six analog blocks.
Port 0
To Analog
System
DIGITAL SYSTEM
Row 0
DBC00
DBC01
DCC02
4
DCC03
4
Row Output
Configuration
Row Input
Configuration
Digital PSoC Block Array
8
8
PSoC Core
8
Row Input
Configuration
8
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard architecture
microprocessor. The CPU uses an interrupt controller with 21
vectors, to simplify the programming of real time embedded
events.
Row 1
DBC00
GIE[7:0]
GIO[7:0]
Program execution is timed and protected using the included
Sleep and watchdog timers (WDT).
DBC01
DCC02
DCC03
Global Digital
Interconnect
Row Output
Configuration
The PSoC Core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
general-purpose I/O (GPIO).
Memory encompasses 16 KB of Flash for program storage, 1 K
bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the Flash. Program Flash uses four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
Port 1
Port 4
GOE[7:0]
GOO[7:0]
Digital peripheral configurations are:
■
PWMs (8- and 16-Bit)
■
PWMs with Dead band (8- and 16-Bit)
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz IMO (internal main oscillator). The 24 MHz
IMO can also be doubled to 48 MHz for use by the digital system.
A low power 32 kHz internal low-speed oscillator (ILO) is
provided for the Sleep timer and WDT. If crystal accuracy is
required, the ECO (32.768 kHz external crystal oscillator) is
available for use as a Real Time Clock (RTC), and can optionally
generate a crystal-accurate 24 MHz system clock using a PLL.
The clocks, together with programmable clock dividers (as a
System Resource), provide the flexibility to integrate almost any
timing requirement into the PSoC device.
■
Counters (8 to 32-Bit)
■
Timers (8 to 32-Bit)
■
UART 8 Bit with Selectable Parity (Up to Two)
■
SPI Master and Slave (Up to Two)
■
Shift Register (1 to 32-Bit)
■
I2C Slave and Master (One Available as a System Resource)
■
Cyclical Redundancy Checker/Generator (8 to 32-Bit)
PSoC GPIOs provide connection to the CPU, digital, and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external
interfacing. Every pin can also generate a system interrupt on
high level, low level, and change from last read.
■
IrDA (Up to Two)
■
Pseudo Random Sequence Generators (8 to 32-Bit)
The digital blocks may be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This provides a choice of
system resources for your application. Family resources are
shown in Table 1 on page 5.
Document Number: 001-43084 Rev. *V
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CY8C21345
CY8C22345
CY8C22545
Analog System
Additional System Resources
The Analog System consists of a 10-bit SAR ADC and six
configurable blocks.
System Resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a MAC, low voltage
detection, and power on reset. The merits of each system
resource are:
The programmable 10-bit SAR ADC is an optimized ADC that
can be run up to 200 ksps with ± 1.5 LSB DNL and ± 2.5 LSB INL
(true for VDD 3.0 V and Vref 3.0 V). External filters are
required on ADC input channels for antialiasing. This ensures
that any out-of-band content is not folded into the input signal
band.
Reconfigurable analog resources allow creating complex analog
signal flows. Analog peripherals are very flexible and may be
customized to support specific application requirements. Some
of the more common PSoC analog functions (most available as
user modules) are:
■
Analog-to-Digital converters (Single or Dual, with 8-bit
resolution)
■
Pin-to-pin Comparator
■
Single ended comparators with absolute (1.3 V) reference or
5-bit DAC reference
■
1.3 V reference (as a System Resource)
Analog blocks are provided in columns of four, which include
CT-E (Continuous Time) and SC-E (Switched Capacitor) blocks.
These devices provide limited functionality Type “E” analog
blocks.
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks may be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■
Additional Digital resources and clocks optimized for CSD.
■
Support “RTC” block into digital peripheral logic.
■
A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math and
digital filters.
■
The I2C module provides 100 and 400 kHz communication over
two wires. Slave, master, and multi-master modes are all
supported.
■
Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
■
An internal 1.3 V reference provides an absolute reference for
the analog system, including ADCs and DACs.
Figure 2. Analog System Block Diagram
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
ACI1[1:0]
ACI1[1:0]
ACE00
ACE01
ACE10
ACE11
ASE10
ASE11
Block Array
AmuxL
AmuxR
P0[0:7]
ACI2[3:0]
10 bit SAR ADC
Analog Reference
Interface to
Digital System
AGND
Reference
Generators
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-43084 Rev. *V
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CY8C21345
CY8C22345
CY8C22545
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3
analog blocks. The following table lists the resources available for specific PSoC device groups.
Table 1. PSoC Device Characteristics
PSoC Part
Number
Digital
I/O
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
Analog
Columns
Analog
Blocks
SRAM
Size
Flash
Size
CY8C29x66[2]
up to 64
4
16
up to 12
4
4
12
2K
32 K
CY8C28xxx
up to 44
up to 3
up to 12
up to 44
up to 4
up to 6
up to
12 + 4[3]
1K
16 K
CY8C27x43
up to 44
2
8
up to 12
4
4
12
256
16 K
CY8C24x94[2]
up to 56
1
4
up to 48
2
2
6
1K
16 K
CY8C24x23A
[2]
up to 24
1
4
up to 12
2
2
6
256
4K
CY8C23x33
up to 26
1
4
up to 12
2
2
4
256
8K
CY8C22x45[2]
up to 38
2
8
up to 38
0
4
6[3]
1K
16 K
[2]
up to 24
1
4
up to 24
0
4
6[3]
512
8K
CY8C21x34[2]
up to 28
1
4
up to 28
0
2
4[3]
512
8K
[3]
256
4K
CY8C21x45
CY8C21x23
up to 16
1
4
up to 8
0
2
CY8C20x34[2]
up to 28
0
0
up to 28
0
0
3[3,4]
4
512
8K
CY8C20xx6
up to 36
0
0
up to 36
0
0
3[3,4]
up to 2 K
up to 32 K
Getting Started
For in-depth information, along with detailed programming
details, see the CY8C22x45, CY8C21345: PSoC®
Programmable System-on-Chip™ Technical Reference Manual.
Training
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web.
Free PSoC technical training (on demand, webinars, and
workshops), which is available online via www.cypress.com,
covers a wide variety of topics and skill levels to assist you in
your designs.
Application Notes
CYPros Consultants
Cypress application notes are an excellent introduction to the
wide variety of possible PSoC designs. Use PSoC 1 Application
note finder to search application notes or example projects for a
specific application and/or family.
Certified PSoC consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
PSoC consultant go to the CYPros Consultants web site.
Development Kits
PSoC 1 kits are available online from Cypress and also available
through a growing number of regional and global distributors,
which include Arrow, Avnet, Digi-Key, Farnell, Future
Electronics, and Newark. The kit selector guide available in
cypress website offers the list of all available development kits,
programming and debugging kits for each PSoC 1 family.
Solutions Library
Visit our growing library of solution focused designs. Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
Technical Support
Technical support – including a searchable Knowledge Base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
Notes
2. Automotive qualified devices available in this group.
3. Limited analog functionality.
4. Two analog blocks and one CapSense® block.
Document Number: 001-43084 Rev. *V
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Development Tools
PSoC Designer™ is the revolutionary integrated design
environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
■
Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■
Extensive user module catalog
■
Integrated source-code editor (C and assembly)
■
Free C compiler with no size restrictions or time limits
■
Built-in debugger
■
In-circuit emulation
■
Built-in support for communication interfaces:
2
❐ Hardware and software I C slaves and masters
❐ Full-speed USB 2.0
❐ Up
to
four
full-duplex
universal
asynchronous
receiver/transmitters (UARTs), SPI master and slave, and
wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
PSoC Designer Software Subsystems
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are ADCs, DACs, amplifiers, and filters. Configure
the user modules for your chosen application and connect them
to each other and to the proper pins. Then generate your project.
This prepopulates your project with APIs and libraries that you
can use to program your application.
The tool also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration makes it possible to change configurations at run
Document Number: 001-43084 Rev. *V
time. In essence, this allows you to use more than 100 percent
of PSoC's resources for an application.
Code Generation Tools
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and are
linked with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
You can read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also allows you to create a trace buffer of registers and memory
locations of interest.
Online Help System
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an online support Forum
to aid the designer.
In-Circuit Emulator
A low-cost, high-functionality in-circuit emulator (ICE) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24 MHz) operation.
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Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process is summarized in four steps:
specifications. Each datasheet describes the use of each user
module parameter, and other information you may need to
successfully implement your design.
Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. You perform the
selection, configuration, and routing so that you have complete
control over all on-chip resources.
1. Select User Modules.
Generate, Verify, and Debug
2. Configure User Modules.
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides application programming interfaces
(APIs) with high-level functions to control and respond to
hardware events at run-time and interrupt service routines that
you can adapt as needed.
3. Organize and Connect.
4. Generate, Verify, and Debug.
Select User Modules
PSoC Designer provides a library of prebuilt, pretested hardware
peripheral components called “user modules.” User modules
make selecting and implementing peripheral devices, both
analog and digital, simple.
Configure User Modules
Each user module that you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a PWM
User Module configures one or more digital PSoC blocks, one
for each 8 bits of resolution. The user module parameters permit
you to establish the pulse width and duty cycle. Configure the
parameters and properties to correspond to your chosen
application. Enter values directly or by selecting values from
drop-down menus. All the user modules are documented in
datasheets that may be viewed directly in PSoC Designer or on
the Cypress website. These user module datasheets explain the
internal operation of the user module and provide performance
Document Number: 001-43084 Rev. *V
A complete code development environment allows you to
develop and customize your applications in either C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full speed. PSoC Designer debugging
capabilities rival those of systems costing many times more. In
addition to traditional single-step, run-to-breakpoint, and
watch-variable features, the debug interface provides a large
trace buffer and allows you to define complex breakpoint events.
These include monitoring address and data bus values, memory
locations, and external signals.
Page 7 of 40
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Pinouts
This PSoC device family is available in a variety of packages that are listed in the following tables. Every port pin (labeled with a “P”)
is capable of Digital I/O. However, Vss, Vdd, and XRES are not capable of Digital I/O.
CY8C22345, CY8C21345 28-pin SOIC
Table 2. Pin Definitions
Pin No.
Type
Digital Analog
Pin Name
Description
1
I/O
I, MR
P0[7]
Integration Capacitor for MR
2
I/O
I, ML
P0[5]
Integration Capacitor for ML
3
I/O
I, ML
P0[3]
4
I/O
I, ML
P0[1]
5
I/O
I, ML
P2[7]
To Compare Column 0
6
I/O
ML
P2[5]
Optional ADC External Vref
7
I/O
ML
P2[3]
8
I/O
ML
P2[1]
9
Power
Vss
Ground Connection [5]
10
I/O
ML
P1[7]
I2C serial clock (SCL)
I2C serial data (SDA)
11
I/O
ML
P1[5]
12
I/O
ML
P1[3]
13
I/O
ML
P1[1]
I2C serial clock (SCL),
ISSP-SCLK [6]
Vss
Ground Connection [5]
I2C serial Clock (SCL),
ISSP-SDATA [6]
14
Power
15
I/O
MR
P1[0]
16
I/O
MR
P1[2]
17
I/O
MR
P1[4]
18
I/O
19
MR
Input
I/O
MR
21
I/O
MR
P2[2]
22
I/O
MR
P2[4]
23
I/O
I, MR
P2[6]
24
I/O
I, MR
P0[0]
25
I/O
I, MR
P0[2]
26
I/O
I, MR
P0[4]
27
I/O
I, MR
P0[6]
Power
AI, MR, P0[7]
AI, ML, P0[5]
AI, ML, P0[3]
AI, ML, P0[1]
AI, ML, P2[7]
ADC_Ext_Vref, ML, P2[5]
ML, P2[3]
ML, P2[1]
Vss
I2C SCL, ML, P1[7]
I2C SDA, ML, P1[5]
ML, P1[3]
I2C SCL, ML, P1[1]
Vss
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SOIC
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vdd
P0[6], MR, AI
P0[4], MR, AI
P0[2], MR, AI
P0[0], MR, AI
P2[6], MR, AI
P2[4], MR
P2[2], MR
P2[0], MR
XRES
P1[6], MR
P1[4], MR, EXTCLK
P1[2], MR
P1[0], MR, I2C SDATA
Optional external clock input
(EXT-CLK)
P1[6]
XRES
20
28
Figure 3. Pin Diagram
Active High Pin Reset with
Internal Pull Down
P2[0]
Vdd
To Compare Column 1
Supply Voltage
LEGEND: A = Analog, I = Input, O = Output, M=Analog Mux input, MR= Analog Mux right input, ML= Analog Mux left input.
Notes
5. All VSS pins should be brought out to one common GND plane.
6. If ISSP is not used, pins P1[0] and P1[1] will respond differently to a POR or XRES event. After a POR or XRES event, both pins are pulled down to ground by going
into the resistive zero Drive mode, before reaching the High Z Drive mode.
Document Number: 001-43084 Rev. *V
Page 8 of 40
CY8C21345
CY8C22345
CY8C22545
CY8C22545 44-pin TQFP
Table 3. Pin Definitions [7]
Pin Name
I/O
MR
P1[2]
20
21
22
23
24
25
26
I/O
I/O
I/O
I/O
I/O
I/O
MR
MR
MR
MR
MR
MR
P1[4]
P1[6]
P3[0]
P3[2]
P3[4]
P3[6]
XRES
27
I/O
MR
P4[0]
28
I/O
MR
P4[2]
29
I/O
MR
P4[4]
Power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ML
ML
ML
ML
ML
ML
ML
ML
Power
Input
30
Power
Vss
31
I/O
MR
P2[0]
32
I/O
MR
P2[2]
33
I/O
MR
P2[4]
34
I/O
I, MR
P2[6]
35
I/O
I, MR
P0[0]
36
I/O
I, MR
P0[2]
37
I/O
I, MR
P0[4]
38
I/O
I, MR
P0[6]
39
Power
Supply Voltage
Ground Connection
I2C serial clock (SCL)
I2C serial data (SDA)
ADC_Ext_Vref, ML, P2[5]
ML, P2[3]
ML, P2[1]
Vdd
ML, P4[5]
ML, P4[3]
ML, P4[1]
Vss
ML, P3[7]
ML, P3[5]
ML, P3[3]
Crystal (XTALin), I2C SCL, ISSP SCLK[6]
Ground Connection
Crystal (XTALout),
I2C SDA, ISSP
]
SDATA[6
1
2
3
4
5
TQFP
6
7
8
9
10
11
33
32
31
30
29
28
27
26
25
24
23
P2[4], MR
P2[2], MR
P2[0], MR
Vss
P4[4], MR
P4[2], MR
P4[0], MR
XRES
P3[6], MR
P3[4], MR
P3[2], MR
MR, P1[6]
MR, P3[0]
19
ML
ML
ML
P0[5], ML, AI
P0[7], MR, AI
Vdd
P0[6], MR, AI
P0[4], MR, AI
P0[2], MR, AI
P0[0], MR, AI
P2[6], MR, AI
MR
Power
I/O
I/O
I/O
Optional ADC External Vref
41
40
I/O
P2[5]
P2[3]
P2[1]
Vdd
P4[5]
P4[3]
P4[1]
Vss
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
P1[5]
P1[3]
P1[1]
Vss
P1[0]
39
38
37
36
35
34
ML
ML
ML
P2[7], ML, AI
P0[1], ML, AI
P0[3], ML, AI
I/O
I/O
I/O
Figure 4. Pin Diagram
44
43
42
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Description
12
13
14
15
16
17
18
19
20
21
22
Analog
ML, P3[1]
Type
Digital
I2C SCL, ML, P1[7]
I2C SDA, ML, P1[5]
ML, P1[3]
I2C SCL, XTALin, ML, P1[1]
Vss
I2C SDA, XTALout, MR, P1[0]
MR, P1[2]
EXTCLK, MR, P1[4]
Pin No.
Optional external clock input (EXTCLK)
Active High Pin Reset with Internal Pull
Down
Ground Connection
To Compare Column 1
Vdd
Supply Voltage
40
I/O
I, MR
P0[7]
Integration Capacitor for MR
41
I/O
I, ML
P0[5]
Integration Capacitor for ML
42
I/O
I, ML
P0[3]
43
I/O
I, ML
P0[1]
44
I/O
I, ML
P2[7]
To Compare Column 0
LEGEND: A = Analog, I = Input, O = Output, M=Analog Mux input, MR= Analog Mux right input, ML= Analog Mux left input.
Note
7. All VSS pins should be brought out to one common GND plane.
Document Number: 001-43084 Rev. *V
Page 9 of 40
CY8C21345
CY8C22345
CY8C22545
Registers
This section lists the registers of this PSoC device family by mapping tables. For detailed register information, refer the PSoC
Programmable System-on Chip Technical Reference Manual.
Register Conventions
Register Mapping Tables
Table 4. Abbreviations
The PSoC device has a total register address space of 512
bytes. The register space is also referred to as I/O space and is
broken into two parts. The XIO bit in the Flag register determines
which bank the user is currently in. When the XIO bit is set, the
user is said to be in the “extended” address space or the
“configuration” registers.
Convention
Description
RW
Read and write register or bit(s)
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Document Number: 001-43084 Rev. *V
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.
Page 10 of 40
CY8C21345
CY8C22345
CY8C22545
Table 5. Register Map Bank 0 Table: User Space
Name
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
PRT4DR
PRT4IE
PRT4GS
PRT4DM2
Addr (0,Hex) Access
Name
00
RW
01
RW
02
RW
03
RW
04
RW
05
RW
06
RW
07
RW
08
RW
09
RW
0A
RW
0B
RW
0C
RW
0D
RW
0E
RW
0F
RW
10
RW
CSD0_DR0_L
11
RW
CSD0_DR1_L
12
RW
CSD0_CNT_L
13
RW
CSD0_CR0
14
RW
CSD0_DR0_H
15
RW
CSD0_DR1_H
16
RW
CSD0_CNT_H
17
RW
CSD0_CR1
18
RW
CSD1_DR0_L
19
RW
CSD1_DR1_L
1A
RW
CSD1_CNT_L
1B
RW
CSD1_CR0
1C
RW
CSD1_DR0_H
1D
RW
CSD1_DR1_H
1E
RW
CSD1_CNT_H
1F
RW
CSD_CR1
DBC00DR0
20
#
AMX_IN
DBC00DR1
21
W
AMUX_CFG
DBC00DR2
22
RW
PWM_CR
DBC00CR0
23
#
ARF_CR
DBC01DR0
24
#
CMP_CR0
DBC01DR1
25
W
ASY_CR
DBC01DR2
26
RW
CMP_CR1
DBC01CR0
27
#
DCC02DR0
28
#
ADC0_CR
DCC02DR1
29
W
ADC1_CR
DCC02DR2
2A
RW
SADC_DH
DCC02CR0
2B
#
SADC_DL
DCC03DR0
2C
#
TMP_DR0
DCC03DR1
2D
W
TMP_DR1
DCC03DR2
2E
RW
TMP_DR2
DCC03CR0
2F
#
TMP_DR3
DBC10DR0
30
#
DBC10DR1
31
W
DBC10DR2
32
RW
ACB00CR1*
DBC10CR0
33
#
ACB00CR2*
DBC11DR0
34
#
DBC11DR1
35
W
DBC11DR2
36
RW
ACB01CR1*
DBC11CR0
37
#
ACB01CR2*
DCC12DR0
38
#
DCC12DR1
39
W
DCC12DR2
3A
RW
DCC12CR0
3B
#
DCC13DR0
3C
#
DCC13DR1
3D
W
DCC13DR2
3E
RW
DCC13CR0
3F
#
Shaded fields are Reserved and must not be accessed.
Document Number: 001-43084 Rev. *V
Addr (0,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72*
73*
74
75
76*
77*
78
79
7A
7B
7C
7D
7E
7F
Access
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
R
W
R
#
R
W
R
RW
R
W
R
#
R
W
R
RW
RW
RW
RW
RW
#
#
RW
RW
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ASC10CR0*
Addr (0,Hex) Access
Name
80*
RW
81
RW
82
RW
83
RW
ASD11CR0*
84*
RW
85
RW
86
RW
87
RW
88
RW
PWMVREF0
89
RW
PWMVREF1
8A
RW
IDAC_MODE
8B
RW
PWM_SRC
8C
RW
TS_CR0
8D
RW
TS_CMPH
8E
RW
TS_CMPL
8F
RW
TS_CR1
90
RW
CUR PP
91
RW
STK_PP
92
RW
PRV PP
93
RW
IDX_PP
94
RW
MVR_PP
95
RW
MVW_PP
96
RW
I2C0_CFG
97
RW
I2C0_SCR
98
RW
I2C0_DR
99
RW
I2C0_MSCR
9A
RW
INT_CLR0
9B
RW
INT_CLR1
9C
RW
INT_CLR2
9D
RW
INT_CLR3
9E
RW
INT_MSK3
9F
RW
INT_MSK2
A0
INT_MSK0
A1
INT_MSK1
A2
INT_VC
A3
RES_WDT
A4
DEC_DH
A5
DEC_DL
A6
DEC _CR0*
A7
DEC_CR1*
A8
W
MUL0_X
A9
W
MUL0_Y
AA
R
MUL0_DH
AB
R
MUL0_DL
AC
RW
ACC0_DR1
AD
RW
ACC0_DR0
AE
RW
ACC0_DR3
AF
RW
ACC0_DR2
RDI0RI
B0
RW
CPU A
RDI0SYN
B1
RW
CPU_T1
RDI0IS
B2
RW
CPU_T2
RDI0LT0
B3
RW
CPU_X
RDI0LT1
B4
RW
CPU PCL
RDI0RO0
B5
RW
CPU_PCH
RDI0RO1
B6
RW
CPU_SP
RDI0DSM
B7
RW
CPU_F
RDI1RI
B8
RW
CPU_TST0
RDI1SYN
B9
RW
CPU_TST1
RDI1IS
BA
RW
CPU_TST2
RDI1LT0
BB
RW
CPU TST3
RDI1LT1
BC
RW
DAC1_D
RDI1RO0
BD
RW
DAC0_D
RDI1RO1
BE
RW
CPU_SCR1
RDI1DSM
BF
RW
CPU_SCR0
# Access is bit specific. * has a different meaning.
Addr (0,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
RW
RW
RW
RW
RW
RW
RW
#
#
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RC
W
RW
RW
RW
RW
W
W
R
R
RW
RW
RW
RW
#
#
#
#
#
#
#
I
RW
RW
RW
#
RW
RW
#
#
Page 11 of 40
CY8C21345
CY8C22345
CY8C22545
Table 6. Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
PRT4DM0
PRT4DM1
PRT4IC0
PRT4IC1
Addr (1,Hex) Access Name
0
RW
1
RW
2
RW
3
RW
4
RW
5
RW
6
RW
7
RW
8
RW
9
RW
0A
RW
0B
RW
0C
RW
0D
RW
0E
RW
0F
RW
10
RW
CMP0CR1
11
RW
CMP0CR2
12
RW
13
RW
VDAC50CR0
14
RW
CMP1CR1
15
RW
CMP1CR2
16
RW
17
RW
VDAC51CR0
18
RW
CSCMPCR0
19
RW
CSCMPGOEN
1A
RW
CSLUTCR0
1B
RW
CMPCOLMUX
1C
RW
CMPPWMCR
1D
RW
CMPFLTCR
1E
RW
CMPCLK1
1F
RW
CMPCLK0
DBC00FN
20
RW
CLK_CR0
DBC00IN
21
RW
CLK_CR1
DBC00OU
22
RW
ABF_CR0
DBC00CR1
23
RW
AMD_CR0
DBC01FN
24
RW
CMP_GO_EN
DBC01IN
25
RW
CMP_GO_EN1
DBC01OU
26
RW
AMD_CR1
DBC01CR1
27
RW
ALT_CR0
DCC02FN
28
RW
ALT_CR1
DCC02IN
29
RW
CLK_CR2
DCC02OU
2A
RW
DBC02CR1
2B
RW
CLK_CR3
DCC03FN
2C
RW
TMP_DR0
DCC03IN
2D
RW
TMP_DR1
DCC03OU
2E
RW
TMP_DR2
DBC03CR1
2F
RW
TMP_DR3
DBC10FN
30
RW
DBC10IN
31
RW
DBC10OU
32
RW
ACB00CR1*
DBC10CR1
33
RW
ACB00CR2*
DBC11FN
34
RW
DBC11IN
35
RW
DBC11OU
36
RW
ACB01CR1*
DBC11CR1
37
RW
ACB01CR2*
DCC12FN
38
RW
DCC12IN
39
RW
DCC12OU
3A
RW
DBC12CR1
3B
RW
DCC13FN
3C
RW
DCC13IN
3D
RW
DCC13OU
3E
RW
DBC13CR1
3F
RW
Shaded fields are Reserved and must not be accessed.
Document Number: 001-43084 Rev. *V
Addr (1,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76*
77*
78
79
7A
7B
7C
7D
7E
7F
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ASC10CR0*
Addr (1,Hex) Access Name
80*
RW
81
RW
82
RW
83
RW
ASD11CR0*
84*
RW
85
RW
86
RW
87
RW
88
RW
89
RW
8A
RW
8B
RW
8C
RW
8D
RW
8E
RW
8F
RW
90
RW
GDI_O_IN
91
RW
GDI_E_IN
92
RW
GDI_O_OU
93
RW
GDI_E_OU
94
RW
95
RW
96
RW
97
RW
98
RW
MUX_CR0
99
RW
MUX_CR1
9A
RW
MUX_CR2
9B
RW
MUX_CR3
9C
RW
DAC_CR1#
9D
RW
OSC_GO_EN
9E
RW
OSC_CR4
9F
RW
OSC_CR3
GDI_O_IN_CR
A0
RW
OSC_CR0
GDI_E_IN_CR
A1
RW
OSC_CR1
GDI_O_OU_CR A2
RW
OSC_CR2
GDI_E_OU_CR A3
RW
VLT_CR
RTC_H
A4
RW
VLT_CMP
RTC_M
A5
RW
ADC0_TR*
RTC_S
A6
RW
ADC1_TR*
RTC_CR
A7
RW
V2BG_TR
SADC_CR0
A8
RW
IMO_TR
SADC_CR1
A9
RW
ILO_TR
SADC_CR2
AA
RW
BDG_TR
SADC_CR3TRIM AB
RW
ECO_TR
SADC_CR4
AC
RW
MUX_CR4
I2C0_AD
AD
RW
MUX_CR5
AE
RW
MUX_CR6
AF
RW
MUX_CR7
RDI0RI
B0
RW
CPU A
RDI0SYN
B1
RW
CPU_T1
RDI0IS
B2
RW
CPU_T2
RDI0LT0
B3
RW
CPU_X
RDI0LT1
B4
RW
CPU_PCL
RDI0RO0
B5
RW
CPU_PCH
RDI0RO1
B6
RW
CPU_SP
RDI0DSM
B7
RW
CPU_F
RDI1RI
B8
RW
FLS_PR0
RDI1SYN
B9
RW
FLS TR
RDI1IS
BA
RW
FLS_PR1
RDI1LT0
BB
RW
RDI1LT1
BC
RW
FAC_CR0
RDI1RO0
BD
RW
DAC_CR0#
RDI1RO1
BE
RW
CPU_SCR1
RDI1DSM
BF
RW
CPU_SCR0
# Access is bit specific. * has a different meaning.
Addr (1,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
RW
RW
RW
RW
RW
RW
RW
#
RW
RW
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
RW
RW
RW
W
W
RW
W
RW
RW
RW
RW
#
#
#
#
#
#
#
I
RW
W
RW
SW
RW
#
#
Page 12 of 40
CY8C21345
CY8C22345
CY8C22545
Electrical Specifications
This section presents the DC and AC electrical specifications of this PSoC device family. For the latest electrical specifications, check
the most recent data sheet by visiting http://www.cypress.com.
Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications for devices running at greater
than 12 MHz are valid for –40 °C TA 70 °C and TJ 82 °C.
Figure 5. Voltage versus Operating Frequency
5.25
Vdd Voltage
lid n g
Va rati n
e io
Op Reg
4.75
3.00
93 kHz
12 MHz
24 MHz
CPU Frequency
Document Number: 001-43084 Rev. *V
Page 13 of 40
CY8C21345
CY8C22345
CY8C22545
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 7. Absolute Maximum Ratings
Symbol
Description
Min
Typ
Max
Units
–55
–
+100
°C
–
125
See Package
label
°C
See package
label
–
72
Hours
–40
–
+85
°C
–0.5
–
+6.0
V
Vss - 0.5
–
Vdd + 0.5
V
Vss - 0.5
–
Vdd + 0.5
V
Maximum current into any port pin
–25
–
+50
mA
ESD
Electr static discharge voltage
2000
–
–
V
LU
Latch up current
–
–
200
mA
TSTG
Storage temperature
TBAKETEMP
Bake temperature
TBAKETIME
Bake time
TA
Ambient temperature with power applied
Vdd
Supply voltage on Vdd relative to Vss
VIO
DC input voltage
VIOz
DC voltage applied to tristate
IMIO
Notes
Higher storage
temperatures reduce
data retention time
Human Body Model ESD
Operating Temperature
Table 8. Operating Temperature
Min
Typ
Max
Units
TA
Symbol
Ambient temperature
Description
–40
–
+85
°C
TJ
Junction temperature
–40
–
+100
°C
Document Number: 001-43084 Rev. *V
Notes
The temperature rise
from ambient to junction
is package specific. See
Table 30 on page 28. The
user must limit the power
consumption to comply
with this requirement.
Page 14 of 40
CY8C21345
CY8C22345
CY8C22545
DC Electrical Characteristics
DC Chip Level Specifications
Table 9 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and
–40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C, and
are for design guidance only, unless specified otherwise.
Table 9. DC Chip Level Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
Vdd
Supply voltage
3.0
–
5.25
V
See Table 17 on page 19
IDD
Supply current
–
7
12
mA
Conditions are Vdd = 5.0 V,
25°C, CPU = 3 MHz, 48 MHz disabled.
VC1 = 1.5 MHz
VC2 = 93.75 kHz
VC3 = 93.75 kHz
IDD3
Supply current
–
4
7
mA
Conditions are Vdd = 3.3 V
TA = 25 °C, CPU = 3 MHz
48 MHz = Disabled
VC1 = 1.5 MHz, VC2 = 93.75 kHz
VC3 = 93.75 kHz
ISB
Sleep (Mode) Current with POR, LVD,
Sleep Timer, and WDT[8]
–
3
6.5
A
Conditions are with internal slow speed
oscillator, Vdd = 3.3 V
–40°C
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