CY8C22345

CY8C21345, CY8C22345, CY8C22545 PSoC® Programmable System-on-Chip™ Features ■ ■ Powerful Harvard Architecture Processor: ❐ M8C Processor Speeds up to 24 MHz ❐ 8x8 Multiply, 32-Bit Accumulate ❐ Low Power at High Speed ❐ 3.0V to 5.25V Operating Voltage ❐ Industrial Temperature Range: -40°C to +85°C Advanced Peripherals (PSoC Blocks) ❐ Six Analog Type “E” PSoC Blocks provide: • Single or Dual 8-Bit ADC • Comparators (up to Four) ❐ Up to Eight Digital PSoC Blocks provide: • 8 to 32-Bit Timers, Counters, and PWMs • One Shot, Multi Shot Mode Support in Timers and PWMs • PWM with Deadband Support in One Digital Block • Shift Register, CRC, and PRS Modules • Full Duplex UART • Multiple SPI™ Masters or Slaves, Variable Data Length Support: 8, 9, ...,16-bit • Can be Connected to all GPIO Pins ❐ Complex Peripherals by Combining Blocks ❐ Shift Function Support for FSK Detection ❐ Powerful Synchronize Feature Support. Analog Module Operations can be Synchronized by Digital Blocks or External Signals. High Speed 10-Bit SAR ADC with Sample and Hold Optimized for Embedded Control Precision, Programmable Clocking: ❐ Internal ± 5% 24/48 MHz Oscillator across the Industrial Temperature Range ❐ High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL ❐ Optional External Oscillator, up to 24 MHz ❐ Internal/External Oscillator for Watchdog and Sleep Flexible On-Chip Memory: ❐ Up to 16K Bytes Flash Program Storage 50,000 Erase/Write Cycles ❐ Up to 1K Byte SRAM Data Storage ❐ In-System Serial Programming (ISSP™) ❐ Partial Flash Updates ❐ Flexible Protection Modes ❐ EEPROM Emulation in Flash Optimized CapSense Resource: ❐ Two IDAC Support up to 640 µA Source Current to Replace External Resistor ❐ Two Dedicated Clock Resources for CapSense: • CSD_CLK: 1/2/4/8/16/32/128/256 Derive from SYSCLK • CNT_CLK: 1/2/4/8 Derive from CSD_CLK ❐ Dedicated 16-Bit Timers/Counters for CapSense Scanning ❐ Support Dual CSD Channels Simultaneous Scanning Programmable Pin Configurations: ❐ 25 mA Sink on all GPIO ❐ Pull up, Pull down, High Z, Strong, or Open Drain Drive Modes on all GPIO ❐ Up to 38 Analog Inputs on GPIO ❐ Configurable Interrupt on all GPIO Additional System Resources: 2 ❐ I C™ Slave, Master, and MultiMaster to 400 kHz, Supports Hardware Addressing Feature ❐ Watchdog and Sleep Timers ❐ User Configurable Low Voltage Detection ❐ Integrated Supervisory Circuit ❐ On-Chip Precision Voltage Reference ❐ Supports RTC Block into Digital Peripheral Logic ■ ■ Top Level Block Diagram Port 4 Port 3 Port 2 Port 1 Port 0 Analog Drivers PSoC Core Global Digital Interconnect SRAM 1K Interrupt Controller SROM Global Analog Interconnect Flash 16K Sleep and Watchdog ■ ■ CPU Core (M8C) Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) DIGITAL SYSTEM Digital Block Array DBC DBC DCC DCC ANALOG SYSTEM Analog Input Muxing(L,R) Analog Ref ■ = ROW 1 DBC DBC DCC DCC Analog Block Array CTE SCE CTE SCE CTE CTE ROW 2 System Bus CapSense Digital Resource 10-bit SAR ADC ■ Digital Clocks MACs I2C POR and LVD System Resets Internal Voltage Ref. SYSTEM RESOURCES Cypress Semiconductor Corporation Document Number: 001-43084 Rev. *H • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised March 16, 2009 [+] Feedback CY8C21345, CY8C22345, CY8C22545 PSoC® Functional Overview The PSoC® family consists of many On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, and programmable interconnects. This architecture enables the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts and packages. The PSoC architecture, shown in Figure 1, consists of four main areas: PSoC Core, Digital System, Analog System, and System Resources. Configurable global busing allows the combining of all the device resources into a complete custom system. The PSoC family can have up to five IO ports connecting to the global digital and analog interconnects, providing access to eight digital blocks and six analog blocks. Digital System The Digital System is composed of eight digital PSoC blocks. Each block is an 8-bit resource that may be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Figure 1. Digital System Block Diagram Port 3 Port 4 Port 2 Port 1 Port 0 Digital Clocks From Core To System Bus To Analog System DIGITAL SYSTEM Digital PSoC Block Array Row Input Configuration Row 0 DBC00 DBC01 DCC02 4 DCC03 4 Row Output Configuration 8 PSoC Core The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO). The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with 21 vectors, to simplify the programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT). Memory encompasses 16 KB of Flash for program storage, 1K bytes of SRAM for data storage, and up to 2 KB of EEPROM emulated using the Flash. Program Flash uses four protection levels on blocks of 64 bytes, allowing customized software IP protection. The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator). The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. If crystal accuracy is required, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC), and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. PSoC GPIOs provide connection to the CPU, digital, and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin can also generate a system interrupt on high level, low level, and change from last read. 8 8 Row Input Configuration 8 Row 1 DBC00 DBC01 DCC02 DCC03 Row Output Configuration GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] Digital peripheral configurations are: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ PWMs (8 to 32-Bit) PWMs with Dead band (8 to 32-Bit) Counters (8 to 32-Bit) Timers (8 to 32-Bit) UART 8 Bit with Selectable Parity (Up to Two) SPI Master and Slave (Up to Two) Shift Register (1 to 32-Bit) I2C Slave and Master (One Available as a System Resource) Cyclical Redundancy Checker/Generator (8 to 32-Bit) IrDA (Up to Two) Pseudo Random Sequence Generators (8 to 32-Bit) The digital blocks may be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This provides a choice of system resources for your application. Family resources are shown in Table 1 on page 3. Document Number: 001-43084 Rev. *H Page 2 of 27 [+] Feedback CY8C21345, CY8C22345, CY8C22545 Analog System The Analog System consists of a 10-bit SAR ADC and six configurable blocks. The programmable 10-bit SAR ADC is an optimized ADC that could be run up to 200 ksps with ± 1.5 LSB DNL and ± 2.5 LSB INL (true for VDD ≥ 3.0V and Vref ≥ 3.0V). External filters are required on ADC input channels for antialiasing. This ensures that any out-of-band content is not folded into the input signal band. Reconfigurable analog resources allow creating complex analog signal flows. Analog peripherals are very flexible and may be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are: ■ ■ ■ ■ Additional System Resources System Resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. Additional resources include a MAC, low voltage detection, and power on reset. The merits of each system resource are: ■ Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks may be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. Additional Digital resources and clocks optimized for CSD. Support “RTC” block into digital peripheral logic. A multiply accumulate (MAC) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in both general math and digital filters. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3V reference provides an absolute reference for the analog system, including ADCs and DACs. ■ ■ ■ Analog-to-Digital converters (Single or Dual, with 8-bit resolution) Pin-to-pin Comparator Single ended comparators with absolute (1.3V) reference or 5-bit DAC reference 1.3V reference (as a System Resource) ■ ■ Analog blocks are provided in columns of four, which include CT-E (Continuous Time) and SC-E (Switched Capacitor) blocks. These devices provide limited functionality Type “E” analog blocks. Figure 2. Analog System Block Diagram Array Input Configuration ■ PSoC Device Characteristics Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3 analog blocks. The following table lists the resources available for specific PSoC device groups. Table 1. PSoC Device Characteristics PSoC Part Number Digital IO up to 64 up to 44 up to 44 up to 38 up to 28 up to 24 up to 24 up to 26 Analog Columns Analog Blocks 4 4 4 4 2 4 2 2 12 12 12 6a 4a 6a 6 4 Page 3 of 27 [+] Feedback ACE00 ASE10 ACE01 ASE11 ACE10 ACE11 CY8C29x66 CY8C27x66 CY8C27x43 CY8C22x45 CY8C21x34 CY8C21345 CY8C24x23 CY8C24x33 4 2 2 2 1 1 1 1 16 8 8 8 4 4 4 4 12 12 12 10 28 10 12 12 Block Array AmuxL AmuxR P0[0:7] ACI2[3:0] 10 bit SAR ADC Analog Reference Interface to Digital System Reference Generators a. Limited analog functionality. AGND Bandgap M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 001-43084 Rev. *H Analog Outputs 4 4 4 0 0 0 2 2 ACI0[1:0] ACI1[1:0] ACI1[1:0] ACI1[1:0] Analog Inputs Digital Blocks Digital Rows CY8C21345, CY8C22345, CY8C22545 Getting Started The quickest way to understand PSoC silicon is to read this data sheet and then use the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in depth information, along with detailed programming details, see the PSoC Programmable System-on-Chip Technical Reference Manual for CY8C28xxx PSoC devices. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device data sheets on the web at www.cypress.com/psoc. Development Tools PSoC Designer is a Microsoft® Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE runs on Windows XP or Windows Vista. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built-in support for third-party assemblers and C compilers. PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family. PSoC Designer Software Subsystems System-Level View A drag-and-drop visual embedded system design environment based on PSoC Express. In the system level view you create a model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state based upon any or all other system devices. Based upon the design, PSoC Designer automatically selects one or more PSoC programmable system-on-chip controllers that match your system requirements. PSoC Designer generates all embedded code, then compiles and links it into a programming file for a specific PSoC device. Chip-Level View The chip-level view is a more traditional integrated development environment (IDE) based on PSoC Designer 4.4. Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time. Hybrid Designs You can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. All views of the project share a common code editor, builder, and common debug, emulation, and programming tools. Application Notes Application notes are an excellent introduction to the wide variety of possible PSoC designs. They are located here: www.cypress.com/psoc. Select Application Notes under the Documentation tab. Development Kits PSoC Development Kits are available online from Cypress at www.cypress.com/shop and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Training Free PSoC technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training. The training covers a wide variety of topics and skill levels to assist you in your designs. CYPros Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to www.cypress.com/cypros. Solutions Library Visit our growing library of solution focused designs at www.cypress.com/solutions. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Technical Support For assistance with technical issues, search KnowledgeBase articles and forums at www.cypress.com/support. If you cannot find an answer to your question, call technical support at 1-800-541-4736. Document Number: 001-43084 Rev. *H Page 4 of 27 [+] Feedback CY8C21345, CY8C22345, CY8C22545 Code Generation Tools PSoC Designer supports multiple third party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours. Assemblers. The assemblers allow assembly code to merge seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process can be summarized in the following four steps: 1. Select components 2. Configure components 3. Organize and Connect 4. Generate, Verify, and Debug Select Components Both the system-level and chip-level views provide a library of prebuilt, pretested hardware peripheral components. In the system-level view, these components are called “drivers” and correspond to inputs (a thermistor, for example), outputs (a brushless DC fan, for example), communication interfaces (I2C-bus, for example), and the logic to control how they interact with one another (called valuators). In the chip-level view, the components are called “user modules”. User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and programmable system-on-chip varieties. Configure Components Each of the components you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a Pulse Width Modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop down menus. Both the system-level drivers and chip-level user modules are documented in data sheets that are viewed directly in the PSoC Designer. These data sheets explain the internal operation of the component and provide performance specifications. Each data sheet describes the use of each user module parameter or driver property, and other information you may need to successfully implement your design. In-Circuit Emulator A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. Document Number: 001-43084 Rev. *H Page 5 of 27 [+] Feedback CY8C21345, CY8C22345, CY8C22545 Organize and Connect You can build signal chains at the chip level by interconnecting user modules to each other and the IO pins, or connect system level inputs, outputs, and communication interfaces to each other with valuator functions. In the system-level view, selecting a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects, places, routes, and configures a programmable gain amplifier (PGA) to buffer the input from the potentiometer, an analog to digital converter (ADC) to convert the potentiometer’s output to a digital signal, and a PWM to control the fan. In the chip-level view, perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources. Document Conventions Acronyms Used The following table lists the acronyms that are used in this data sheet. Table 2. Acronyms Acronym AC ADC API CPU CT DAC DC EEPROM FSR GPIO ICE IDE IO IPOR LSb LVD MSb PC POR PPOR PSoC® PWM RAM ROM SC SMP Description alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current electrically erasable programmable read-only memory full scale range general purpose IO in-circuit emulator integrated development environment input/output imprecise power on reset least significant bit low voltage detect most significant bit program counter power on reset precision power on reset Programmable System-on-Chip pulse width modulator random access memory read only memory switched capacitor switch mode pump Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, perform the “Generate Application” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. Both system-level and chip-level designs generate software based on your design. The chip-level design provides application programming interfaces (APIs) with high level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed. The system-level design also generates a C main() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code. A complete code development environment allows you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside the PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. Units of Measure A units of measure table is located in the Electrical Specifications section. Table 5 on page 9 lists all the abbreviations used to measure the PSoC devices. Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal. Document Number: 001-43084 Rev. *H Page 6 of 27 [+] Feedback CY8C21345, CY8C22345, CY8C22545 Pinouts This PSoC device family is available in a variety of packages that are listed in the following tables. Every port pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, and XRES are not capable of Digital IO. CY8C22345, CY8C21345 28-Pin SOIC Table 3. Pin Definitions Type Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 IO IO IO IO IO IO IO IO IO IO IO IO Input MR MR MR I, MR I, MR I, MR I, MR I, MR Power IO IO IO IO Digital Analog IO IO IO IO IO IO IO IO I, MR I, ML I, ML I, ML I, ML ML ML ML Power ML ML ML ML Power MR MR MR MR Pin Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] Vss P1[7] P1[5] P1[3] P1[1]* Vss P1[0]* P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Supply Voltage To Compare Column 1 Active High Pin Reset with Internal Pull Down Optional External Clock Input (EXT-CLK) I2C Serial Clock (SCL), ISSP-SCLK Ground Connection I2C Serial Clock (SCL), ISSP-SDATA Ground Connection I2C Serial Clock (SCL) I2C Serial Data (SDA) To Compare Column 0 Optional ADC External Vref Description Integration Capacitor for MR Integration Capacitor for ML Figure 3. Pin Diagram AI, MR, P0[7] AI, ML, P0[5] AI, ML, P0[3] AI, ML, P0[1] AI, ML, P2[7] ADC_Ext_Vref, ML, P2[5] ML, P2[3] ML, P2[1] Vss I2C SCL, ML, P1[7] I2C SDA, ML, P1[5] ML, P1[3] I2C SCL, ML, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SOIC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd P0[6], MR, AI P0[4], MR, AI P0[2], MR, AI P0[0], MR, AI P2[6], MR, AI P2[4], MR P2[2], MR P2[0], MR XRES P1[6], MR P1[4], MR, EXTCLK P1[2], MR P1[0], MR, I2C SDATA LEGEND: A = Analog, I = Input, O = Output, M=Analog Mux input, MR= Analog Mux right input, ML= Analog Mux left input, * ISSP pin which is not HiZ at POR. Document Number: 001-43084 Rev. *H Page 7 of 27 [+] Feedback CY8C21345, CY8C22345, CY8C22545 CY8C22545 44-Pin TQFP Table 4. Pin Definitions Type Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 IO IO IO IO IO IO IO IO IO IO Power MR MR MR I, MR I, MR I, MR I, MR IO IO IO IO IO IO IO IO Input MR MR MR IO IO IO IO IO IO IO IO Power MR MR MR MR MR MR MR MR IO IO IO Power ML ML ML ML ML ML ML ML Digital IO IO IO Power ML ML ML Analog ML ML ML Pin Name P2[5] P2[3] P2[1] Vdd P4[5] P4[3] P4[1] Vss P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1]* Vss P1[0]* P1[2] P1[4] P1[6] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] Vss P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] To Compare Column 1 Ground Connection Active High Pin Reset with Internal Pull Down Optional External Clock Input (EXTCLK) Crystal (XTALin), I2C Serial Clock (SCL), TC SCLK Ground Connection Crystal (XTALout), I2C Serial Data (SDA), TC SDATA I2C Serial Clock (SCL) I2C Serial Data (SDA) Ground Connection Supply Voltage ADC_Ext_Vref, ML, P2[5] ML, P2[3] ML, P2[1] Vdd ML, P4[5] ML, P4[3] ML, P4[1] Vss ML, P3[7] ML, P3[5] ML, P3[3] 1 2 3 4 5 6 7 8 9 10 11 12 Figure 4. Pin Diagram Description P0[5], ML, AI P0[7], MR, AI Vdd P2[7], ML, AI P0[1], ML, AI P0[3], ML, AI P0[4], MR, AI P0[2], MR, AI P0[0], MR, AI P2[6], MR, AI 35 34 MR, P1[6] MR, P3[0] 21 22 33 32 31 30 29 28 27 26 25 24 23 P2[4], MR P2[2], MR P2[0], MR Vss P4[4], MR P4[2], MR P4[0], MR XRES P3[6], MR P3[4], MR P3[2], MR P0[6], MR, AI Optional ADC External Vref 44 43 42 41 40 TQFP 13 14 15 16 17 ML, P1[3] I2C SCL, XTALin, ML, P1[1] I2C SCL, ML, P1[7] I2C SDA, ML, P1[5] ML, P3[1] Document Number: 001-43084 Rev. *H Vss I2C SDA, XTALout, MR, P1[0] MR, P1[2] EXTCLK, MR, P1[4] 18 19 20 39 38 37 36 Page 8 of 27 [+] Feedback CY8C21345, CY8C22345, CY8C22545 Table 4. Pin Definitions (continued) Type Pin No. 38 39 40 41 42 43 44 IO IO IO IO IO Digital IO Power I, MR I, ML I, ML I, ML I, ML Analog I, MR Pin Name P0[6] Vdd P0[7] P0[5] P0[3] P0[1] P2[7] To Compare Column 0 Supply Voltage Integration Capacitor for MR Integration Capacitor for ML Description LEGEND: A = Analog, I = Input, O = Output, M=Analog Mux input, MR= Analog Mux right input, ML= Analog Mux left input, * ISSP pin which is not HiZ at POR. Register Reference This section lists the registers of this PSoC device family by mapping tables. For detailed register information, refer the PSoC Programmable System-on Chip Technical Reference Manual. Register Mapping Tables The PSoC device has a total register address space of 512 bytes. The register space is also referred to as IO space and is broken into two parts. The XOI bit in the Flag register determines which bank the user is currently in. When the XOI bit is set, the user is said to be in the “extended” address space or the “configuration” registers. Note In the following register mapping tables, blank fields are Reserved and must not be accessed. Register Conventions Abbreviations Used The register conventions specific to this section are listed in the following table. Table 5. Abbreviations Convention RW R W L C # Description Read and write register or bit(s) Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific Document Number: 001-43084 Rev. *H Page 9 of 27 [+] Feedback CY8C21345, CY8C22345, CY8C22545 Table 6. Register Map Bank 0 Table: User Space Access Access Access Access RW RW RW RW RW RW RW RW # # RW # RW RW RW RW RW RW RW RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W RW RW RW RW W W R R RW RW RW RW # # # # # # # I RW RW RW # RW Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC Name Name Name Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 00 RW 01 RW 02 RW 03 RW 04 RW 05 RW 06 RW 07 RW 08 RW 09 RW 0A RW 0B RW 0C RW 0D RW 0E RW 0F RW 10 RW CSD0_DR0_L 11 RW CSD0_DR1_L 12 RW CSD0_CNT_L 13 RW CSD0_CR0 14 RW CSD0_DR0_H 15 RW CSD0_DR1_H 16 RW CSD0_CNT_H 17 RW CSD0_CR1 18 RW CSD1_DR0_L 19 RW CSD1_DR1_L 1A RW CSD1_CNT_L 1B RW CSD1_CR0 1C RW CSD1_DR0_H 1D RW CSD1_DR1_H 1E RW CSD1_CNT_H 1F RW CSD_CR1 DBC00DR0 20 # AMX_IN DBC00DR1 21 W AMUX_CFG DBC00DR2 22 RW PWM_CR DBC00CR0 23 # ARF_CR DBC01DR0 24 # CMP_CR0 DBC01DR1 25 W ASY_CR DBC01DR2 26 RW CMP_CR1 DBC01CR0 27 # DCC02DR0 28 # ADC0_CR DCC02DR1 29 W ADC1_CR DCC02DR2 2A RW SADC_DH DCC02CR0 2B # SADC_DL DCC03DR0 2C # TMP_DR0 DCC03DR1 2D W TMP_DR1 DCC03DR2 2E RW TMP_DR2 DCC03CR0 2F # TMP_DR3 DBC10DR0 30 # DBC10DR1 31 W DBC10DR2 32 RW ACB00CR1* DBC10CR0 33 # ACB00CR2* DBC11DR0 34 # DBC11DR1 35 W DBC11DR2 36 RW ACB01CR1* DBC11CR0 37 # ACB01CR2* DCC12DR0 38 # DCC12DR1 39 W DCC12DR2 3A RW DCC12CR0 3B # DCC13DR0 3C # Shaded fields are Reserved and must not be accessed. 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72* 73* 74 75 76* 77* 78 79 7A 7B 7C # W RW # # W RW # # W RW # # W RW # R W R # R W R RW R W R # R W R RW RW RW RW RW # # RW RW # # RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ASC10CR0* 80* RW 81 RW 82 RW 83 RW ASD11CR0* 84* RW 85 RW 86 RW 87 RW 88 RW PWMVREF0 89 RW PWMVREF1 8A RW IDAC_MODE 8B RW PWM_SRC 8C RW TS_CR0 8D RW TS_CMPH 8E RW TS_CMPL 8F RW TS_CR1 90 RW CUR PP 91 RW STK_PP 92 RW PRV PP 93 RW IDX_PP 94 RW MVR_PP 95 RW MVW_PP 96 RW I2C0_CFG 97 RW I2C0_SCR 98 RW I2C0_DR 99 RW I2C0_MSCR 9A RW INT_CLR0 9B RW INT_CLR1 9C RW INT_CLR2 9D RW INT_CLR3 9E RW INT_MSK3 9F RW INT_MSK2 A0 INT_MSK0 A1 INT_MSK1 A2 INT_VC A3 RES_WDT A4 DEC_DH A5 DEC_DL A6 DEC _CR0* A7 DEC_CR1* A8 W MUL0_X A9 W MUL0_Y AA R MUL0_DH AB R MUL0_DL AC RW ACC0_DR1 AD RW ACC0_DR0 AE RW ACC0_DR3 AF RW ACC0_DR2 RDI0RI B0 RW CPU A RDI0SYN B1 RW CPU_T1 RDI0IS B2 RW CPU_T2 RDI0LT0 B3 RW CPU_X RDI0LT1 B4 RW CPU PCL RDI0RO0 B5 RW CPU_PCH RDI0RO1 B6 RW CPU_SP RDI0DSM B7 RW CPU_F RDI1RI B8 RW CPU_TST0 RDI1SYN B9 RW CPU_TST1 RDI1IS BA RW CPU_TST2 RDI1LT0 BB RW CPU TST3 RDI1LT1 BC RW DAC1_D # Access is bit specific. * has a different meaning. Document Number: 001-43084 Rev. *H Page 10 of 27 [+] Feedback CY8C21345, CY8C22345, CY8C22545 Table 6. Register Map Bank 0 Table: User Space (continued) Access Access Access Access RW # # RW RW RW RW RW RW RW RW # RW RW RW # RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R RW RW RW W W RW W RW RW RW RW # # # # Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) FD FE FF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 Addr (1,Hex) Name Name Name Name Name DCC13DR1 3D W DCC13DR2 3E RW DCC13CR0 3F # Shaded fields are Reserved and must not be accessed. 7D 7E 7F RW RW RW RDI1RO0 BD RW DAC0_D RDI1RO1 BE RW CPU_SCR1 RDI1DSM BF RW CPU_SCR0 # Access is bit specific. * has a different meaning. Table 7. Register Map Bank 1 Table: Configuration Space Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name ASC10CR0* PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 0 RW 1 RW 2 RW 3 RW 4 RW 5 RW 6 RW 7 RW 8 RW 9 RW 0A RW 0B RW 0C RW 0D RW 0E RW 0F RW 10 RW CMP0CR1 11 RW CMP0CR2 12 RW 13 RW VDAC50CR0 14 RW CMP1CR1 15 RW CMP1CR2 16 RW 17 RW VDAC51CR0 18 RW CSCMPCR0 19 RW CSCMPGOEN 1A RW CSLUTCR0 1B RW CMPCOLMUX 1C RW CMPPWMCR 1D RW CMPFLTCR 1E RW CMPCLK1 1F RW CMPCLK0 DBC00FN 20 RW CLK_CR0 DBC00IN 21 RW CLK_CR1 DBC00OU 22 RW ABF_CR0 DBC00CR1 23 RW AMD_CR0 DBC01FN 24 RW CMP_GO_EN DBC01IN 25 RW CMP_GO_EN1 DBC01OU 26 RW AMD_CR1 DBC01CR1 27 RW ALT_CR0 DCC02FN 28 RW ALT_CR1 DCC02IN 29 RW CLK_CR2 DCC02OU 2A RW DBC02CR1 2B RW CLK_CR3 DCC03FN 2C RW TMP_DR0 DCC03IN 2D RW TMP_DR1 DCC03OU 2E RW TMP_DR2 DBC03CR1 2F RW TMP_DR3 DBC10FN 30 RW DBC10IN 31 RW DBC10OU 32 RW ACB00CR1* DBC10CR1 33 RW ACB00CR2* Shaded fields are Reserved and must not be accessed. 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 80* RW 81 RW 82 RW 83 RW ASD11CR0* 84* RW 85 RW 86 RW 87 RW 88 RW 89 RW 8A RW 8B RW 8C RW 8D RW 8E RW 8F RW 90 RW GDI_O_IN 91 RW GDI_E_IN 92 RW GDI_O_OU 93 RW GDI_E_OU 94 RW 95 RW 96 RW 97 RW 98 RW MUX_CR0 99 RW MUX_CR1 9A RW MUX_CR2 9B RW MUX_CR3 9C RW DAC_CR1# 9D RW OSC_GO_EN 9E RW OSC_CR4 9F RW OSC_CR3 GDI_O_IN_CR A0 RW OSC_CR0 GDI_E_IN_CR A1 RW OSC_CR1 GDI_O_OU_CR A2 RW OSC_CR2 GDI_E_OU_CR A3 RW VLT_CR RTC_H A4 RW VLT_CMP RTC_M A5 RW ADC0_TR* RTC_S A6 RW ADC1_TR* RTC_CR A7 RW V2BG_TR SADC_CR0 A8 RW IMO_TR SADC_CR1 A9 RW ILO_TR SADC_CR2 AA RW BDG_TR SADC_CR3TRIM AB RW ECO_TR SADC_CR4 AC RW MUX_CR4 I2C0_AD AD RW MUX_CR5 AE RW MUX_CR6 AF RW MUX_CR7 RDI0RI B0 RW CPU A RDI0SYN B1 RW CPU_T1 RDI0IS B2 RW CPU_T2 RDI0LT0 B3 RW CPU_X # Access is bit specific. * has a different meaning. Document Number: 001-43084 Rev. *H Page 11 of 27 [+] Feedback CY8C21345, CY8C22345, CY8C22545 Table 7. Register Map Bank 1 Table: Configuration Space (continued) Access Access Access Access # # # I RW W RW SW RW # # Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Name Name Name Name DBC11FN 34 RW DBC11IN 35 RW DBC11OU 36 RW ACB01CR1* DBC11CR1 37 RW ACB01CR2* DCC12FN 38 RW DCC12IN 39 RW DCC12OU 3A RW DBC12CR1 3B RW DCC13FN 3C RW DCC13IN 3D RW DCC13OU 3E RW DBC13CR1 3F RW Shaded fields are Reserved and must not be accessed. 74 75 76* 77* 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RW RW RW RW RDI0LT1 B4 RW CPU_PCL RDI0RO0 B5 RW CPU_PCH RDI0RO1 B6 RW CPU_SP RDI0DSM B7 RW CPU_F RDI1RI B8 RW FLS_PR0 RDI1SYN B9 RW FLS TR RDI1IS BA RW FLS_PR1 RDI1LT0 BB RW RDI1LT1 BC RW FAC_CR0 RDI1RO0 BD RW DAC_CR0# RDI1RO1 BE RW CPU_SCR1 RDI1DSM BF RW CPU_SCR0 # Access is bit specific. * has a different meaning. Document Number: 001-43084 Rev. *H Page 12 of 27 [+] Feedback CY8C21345, CY8C22345, CY8C22545 Electrical Specifications This section presents the DC and AC electrical specifications of this PSoC device family. For the latest electrical specifications, check the most recent data sheet by visiting the web at http://www.cypress.com/psoc. Specifications are valid for -40°C ≤ TA ≤ 85°C and TJ ≤ 100°C, except where noted. Specifications for devices running at greater than 12 MHz are valid for -40°C ≤ TA ≤ 70°C and TJ ≤ 82°C. Figure 5. Voltage versus Operating Frequency 5.25 4.75 Vdd Voltage 3.00 93 kHz The following table lists the units of measure that are used in this section. Table 8. Units of Measure Symbol °C dB fF Hz KB Kbit kHz kΩ MHz MΩ μA μF μH μs μV μVrms decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm micro ampere micro farad micro henry microsecond micro volts micro volts root-mean-square Unit of Measure degree Celsius μW mA ms mV nA ns nV W pA pF pp ppm ps sps s V Symbol Unit of Measure micro watts milli-ampere milli-second milli-volts nano ampere nanosecond nanovolts ohm pico ampere pico farad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts lid n g Va rati n e io Op Reg 12 MHz CPU Frequency 24 MHz Document Number: 001-43084 Rev. *H Page 13 of 27 [+] Feedback CY8C21345, CY8C22345, CY8C22545 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 9. Absolute Maximum Ratings Symbol Description TSTG Storage Temperature TA Vdd VIO VIOz IMIO ESD LU Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tristate Maximum Current into any Port Pin Electro Static Discharge Voltage Latch up Current Min -55 -40 -0.5 Vss - 0.5 Vss - 0.5 -25 2000 – Typ – – – – – – – – Max +100 +85 +6.0 Vdd + 0.5 Vdd + 0.5 +50 – 200 Units °C °C V V V mA V mA Human Body Model ESD Notes Higher storage temperatures reduce data retention time Operating Temperature Table 10. Operating Temperature Symbol Description TA Ambient Temperature TJ Junction Temperature Min -40 -40 Typ – – Max +85 +100 Units Notes °C °C The temperature rise from ambient to junction is package specific. See Table 31 on page 25. The user must limit the power consumption to comply with this requirement. Document Number: 001-43084 Rev. *H Page 14 of 27 [+] Feedback CY8C21345, CY8C22345, CY8C22545 DC Electrical Characteristics DC Chip Level Specifications Table 11 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C, and are for design guidance only, unless specified otherwise. Table 11. DC Chip Level Specifications Symbol Vdd IDD Description Supply Voltage Supply Current Min 3.0 – Typ – 7 Max 5.25 12 Units Notes V See Table 18 on page 17 mA Conditions are Vdd = 5.0V, 25°C, CPU = 3 MHz, 48 MHz disabled. VC1 = 1.5 MHz VC2 = 93.75 kHz VC3 = 93.75 kHz Conditions are Vdd = 3.3V TA = 25°C, CPU = 3 MHz 48 MHz = Disabled VC1 = 1.5 MHz, VC2 = 93.75 kHz VC3 = 93.75 kHz Conditions are with internal slow speed oscillator, Vdd = 3.3V -40°C