CY8C22X45

PSoC Programmable System-on-Chip™ Features ■ ■ CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B ® Powerful Harvard-architecture processor ❐ M8C processor speeds up to 24 MHz ❐ Low power at high speed ❐ Operating voltage: 2.4 V to 5.25 V ❐ Operating voltages down to 1.0 V using on-chip switch mode pump (SMP) ❐ Industrial temperature range: –40 °C to +85 °C Advanced peripherals (PSoC® blocks) ❐ Four analog Type E PSoC blocks provide: • Two comparators with digital-to-analog converter (DAC) references • Single or dual 10-bit 28 channel analog-to-digital converters (ADC) ❐ Four digital PSoC blocks provide: • 8- to 32-bit timers, counters, and pulse width modulators (PWMs) • Cyclical redundancy check (CRC) and pseudo random sequence (PRS) modules • Full-duplex universal asynchronous receiver transmitter (UART), serial peripheral interface (SPI) master or slave • Connectable to all general purpose I/O (GPIO) pins ❐ Complex peripherals by combining blocks Flexible on-chip memory ❐ 8 KB flash program storage 50,000 erase/write cycles ❐ 512 bytes static random access memory (SRAM) data storage ❐ In-system serial programming (ISSP) ❐ Partial flash updates ❐ Flexible protection modes ❐ EEPROM emulation in flash Complete development tools ❐ Free development software (PSoC Designer™) ❐ Full-featured, in-circuit emulator (ICE) and programmer ❐ Full-speed emulation ❐ Complex breakpoint structure ❐ 128-KB trace memory Precision, programmable clocking ❐ Internal ±2.5% 24- / 48-MHz main oscillator ❐ Internal oscillator for watchdog and sleep Programmable pin configurations ❐ 25-mA sink, 10-mA source on all GPIOs ❐ Pull-up, pull-down, high Z, strong, or open-drain drive modes on all GPIOs ❐ Up to eight analog inputs on GPIOs ❐ Configurable interrupt on all GPIOs ■ SmartSense™ Auto-Tuning user module: ❐ SmartSense Auto-Tuning is easy to use and provides robust noise immunity. ❐ SmartSense tunes your CapSense system automatically at power up and monitors the system in real time to maintain optimum performance. ❐ SmartSense significantly reduces design cycle time by eliminating the tuning process from prototype to mass production. ❐ SmartSense allows maximum production flexibility by compensating for variations caused by using multiple manufacturing sites and vendors. Versatile analog mux ❐ Common internal analog bus ❐ Simultaneous connection of I/O combinations ❐ Capacitive sensing application capability Additional system resources 2 ❐ I C master, slave, and multi-master to 400 kHz ❐ Watchdog and sleep timers ❐ User-configurable low-voltage detection (LVD) ❐ Integrated supervisory circuit ❐ On-chip precision voltage reference ■ ■ Logic Block Diagram ■ ■ ■ ■ Cypress Semiconductor Corporation Document Number: 001-67345 Rev. *A • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 13, 2011 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Contents Features............................................................................. 1 Logic Block Diagram........................................................ 1 Contents ............................................................................ 2 PSoC Functional Overview.............................................. 3 The PSoC Core ........................................................... 3 The Digital System ...................................................... 3 The Analog System ..................................................... 4 Additional System Resources ..................................... 4 PSoC Device Characteristics ...................................... 5 Getting Started.................................................................. 5 Application Notes ........................................................ 5 Development Kits ........................................................ 5 Training ....................................................................... 5 CYPros Consultants .................................................... 5 Solutions Library.......................................................... 5 Technical Support ....................................................... 5 Development Tools .......................................................... 6 PSoC Designer Software Subsystems........................ 6 Designing with PSoC Designer ....................................... 7 Select User Modules ................................................... 7 Configure User Modules.............................................. 7 Organize and Connect ................................................ 7 Generate, Verify, and Debug....................................... 7 SmartSense................................................................. 7 Pin Information ................................................................. 8 16-Pin Part Pinout ....................................................... 8 20-Pin Part Pinout ....................................................... 9 28-Pin Part Pinout ..................................................... 10 32-Pin Part Pinout ..................................................... 11 56-Pin Part Pinout ..................................................... 13 Register Reference......................................................... 15 Register Conventions ................................................ Register Mapping Tables .......................................... Electrical Specifications ................................................ Absolute Maximum Ratings....................................... Operating Temperature ............................................. DC Electrical Characteristics..................................... AC Electrical Characteristics ..................................... Packaging Information................................................... Thermal Impedances................................................. Solder Reflow Peak Temperature ............................. Development Tool Selection ......................................... Software .................................................................... Development Kits ...................................................... Evaluation Tools........................................................ Device Programmers................................................. Accessories (Emulation and Programming) .............. Ordering Information...................................................... Ordering Code Definitions ......................................... Acronyms ........................................................................ Reference Documents.................................................... Document Conventions ................................................. Units of Measure ....................................................... Numeric Conventions ................................................ Glossary .......................................................................... Document History Page ................................................. .......................................................................................... Sales, Solutions, and Legal Information ...................... Worldwide Sales and Design Support....................... Products .................................................................... PSoC Solutions ......................................................... 15 15 18 18 19 19 25 33 36 36 37 37 37 37 38 38 39 40 41 41 42 42 42 42 47 47 47 47 47 47 Document Number: 001-67345 Rev. *A Page 2 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B PSoC Functional Overview The PSoC family consists of many devices with on-chip controllers. These devices are designed to replace multiple traditional MCU-based system components with one low-cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture makes it possible for you to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast central processing unit (CPU), flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. The PSoC architecture, shown in Figure 1, consists of four main areas: the core, the system resources, the digital system, and the analog system. Configurable global bus resources allow combining all of the device resources into a complete custom system. Each CY8C21x34B PSoC device includes four digital blocks and four analog blocks. Depending on the PSoC package, up to 28 GPIOs are also included. The GPIOs provide access to the global digital and analog interconnects. The Digital System The digital system consists of four digital PSoC blocks. Each block is an 8-bit resource that is used alone or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are called user modules. Digital peripheral configurations include: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ PWMs (8- to 32-bit) PWMs with dead band (8- to 32-bit) Counters (8- to 32-bit) Timers (8- to 32-bit) UART 8- with selectable parity Serial peripheral interface (SPI) master and slave I2C slave and multi-master CRC/generator (8-bit) IrDA PRS generators (8-bit to 32-bit) The PSoC Core The PSoC core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and internal main oscillator (IMO) and internal low speed oscillator (ILO). The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a four-million instructions per second (MIPS) 8-bit Harvard-architecture microprocessor. System resources provide these additional capabilities: ■ ■ ■ ■ ■ The digital blocks are connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows the optimum choice of system resources for your application. Family resources are shown in Table 1 on page 5. Figure 1. Digital System Block Diagram Port 3 Port 2 Port 1 Port 0 Digital clocks for increased flexibility I2C functionality to implement an I2C master and slave An internal voltage reference, multi-master, that provides an absolute value of 1.3 V to a number of PSoC subsystems A SMP that generates normal operating voltages from a single battery cell Various system resets supported by the M8C Digital Clocks To System Bus From Core To Analog System Row Input Configuration The analog system consists of four analog PSoC blocks, supporting comparators, and analog-to-digital conversion up to 10 bits of precision. 8 8 DBB00 DBB01 DCB02 DCB03 4 Row Output Configuration The digital system consists of an array of digital PSoC blocks that may be configured into any number of digital peripherals. The digital blocks are connected to the GPIOs through a series of global buses. These buses can route any signal to any pin, freeing designs from the constraints of a fixed peripheral controller. DIGITAL SYSTEM Digital PSoC Block Array Row 0 4 8 8 GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] Document Number: 001-67345 Rev. *A Page 3 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B The Analog System The analog system consists of four configurable blocks that allow for the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the common PSoC analog functions for this device (most available as user modules) are: ■ ■ ■ ■ The Analog Multiplexer System The analog mux bus can connect to every GPIO pin. Pins may be connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with comparators and analog-to-digital converters. An additional 8:1 analog input multiplexer provides a second path to bring Port 0 pins to the analog array. Switch-control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include: ■ ■ ■ ADCs (single or dual, with 8-bit or 10-bit resolution) Pin-to-pin comparator Single-ended comparators (up to two) with absolute (1.3 V) reference or 8-bit DAC reference 1.3-V reference (as a system resource) Track pad, finger sensing Chip-wide mux that allows analog input from any I/O pin Crosspoint connection between any I/O pin combinations In most PSoC devices, analog blocks are provided in columns of three, which includes one continuous time (CT) and two switched capacitor (SC) blocks. The CY8C21x34B devices provide limited functionality Type E analog blocks. Each column contains one CT Type E block and one SC Type E block. Refer to the PSoC Technical Reference Manual for detailed information on the CY8C21x34B’s Type E analog blocks. Figure 2. Analog System Block Diagram Additional System Resources System resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. Additional resources include a switch-mode pump, low-voltage detection, and power-on-reset (POR). ■ Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks may be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. The I2C module provides 100- and 400-kHz communication over two wires. Slave, master, and multi-master modes are all supported. LVD interrupts can signal the application of falling voltage levels, while the advanced POR circuit eliminates the need for a system supervisor. An internal 1.3-V reference provides an absolute reference for the analog system, including ADCs and DACs. An integrated switch-mode pump generates normal operating voltages from a single 1.2-V battery cell, providing a low cost boost converter. Versatile analog multiplexer system. Array Input Configuration ■ ■ ACI0[1:0] All I/O X X X X ACI1[1:0] ■ ■ ACOL1MUX Analog Mux Bus ■ X Array ACE00 ASE10 ACE01 ASE11 Document Number: 001-67345 Rev. *A Page 4 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B PSoC Device Characteristics Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. Table 1 lists the resources available for specific PSoC device groups. The PSoC device covered by this datasheet is highlighted in Table 1. Table 1. PSoC Device Characteristics PSoC Part Number CY8C29x66 CY8C28xxx CY8C27x43 CY8C24x94 CY8C24x23A CY8C23x33 CY8C22x45 CY8C21x45 CY8C21x34 CY8C21x34B CY8C21x23 CY8C20x34 CY8C20xx6A Digital I/O up to 64 up to 44 up to 44 up to 56 up to 24 up to 26 up to 38 up to 24 up to 28 up to 28 up to 16 up to 28 up to 36 Digital Rows 4 up to 3 2 1 1 1 2 1 1 1 1 0 0 Digital Blocks 16 up to 12 8 4 4 4 8 4 4 4 4 0 0 Analog Inputs up to 12 up to 44 up to 12 up to 48 up to 12 up to 12 up to 38 up to 24 up to 28 up to 28 up to 8 up to 28 up to 36 Analog Outputs 4 up to 4 4 2 2 2 0 0 0 0 0 0 0 Analog Columns 4 up to 6 4 2 2 2 4 4 2 2 2 0 0 Analog Blocks 12 up to 12 + 4[1] 12 6 6 4 6[1] 6[1] 4[1] 4[1] 4 [1] SRAM Size 2K 1K 256 1K 256 256 1K 512 512 512 256 512 up to 2K Flash Size 32 K 16 K 16 K 16 K 4K 8K 16 K 8K 8K 8K 4K 8K up to 32 K SmartSense Enabled – – – – – – – – – Y – – Y 3[1,2] 3[1,2] Getting Started For in-depth information, along with detailed programming details, see the PSoC® Technical Reference Manual. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device datasheets on the web. CYPros Consultants Certified PSoC consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC consultant go to the CYPros Consultants web site. Application Notes Cypress application notes are an excellent introduction to the wide variety of possible PSoC designs. Solutions Library Visit our growing library of solution focused designs. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Development Kits PSoC Development Kits are available online from and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Technical Support Technical support – including a searchable Knowledge Base articles and technical forums – is also available online. If you cannot find an answer to your question, call our Technical Support hotline at 1-800-541-4736. Training Free PSoC technical training (on demand, webinars, and workshops), which is available online via www.cypress.com, covers a wide variety of topics and skill levels to assist you in your designs. Notes 1. Limited analog functionality. 2. Two analog blocks and one CapSense®. Document Number: 001-67345 Rev. *A Page 5 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Development Tools PSoC Designer™ is the revolutionary integrated design environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes: ■ ■ ■ ■ ■ ■ ■ Code Generation Tools The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. You can develop your design in C, assembly, or a combination of the two. Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and are linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows you to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an online support Forum to aid the designer. In-Circuit Emulator A low-cost, high-functionality in-circuit emulator (ICE) is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24 MHz) operation. Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration Extensive user module catalog Integrated source-code editor (C and assembly) Free C compiler with no size restrictions or time limits Built-in debugger In-circuit emulation Built-in support for communication interfaces: 2 ❐ Hardware and software I C slaves and masters ❐ Full-speed USB 2.0 ❐ Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7. PSoC Designer Software Subsystems Design Entry In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use the PSoC blocks, which are called user modules. Examples of user modules are ADCs, DACs, amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this allows you to use more than 100 percent of PSoC's resources for an application. Document Number: 001-67345 Rev. *A Page 6 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is summarized in four steps: 1. Select User Modules. 2. Configure User Modules. 3. Organize and Connect. 4. Generate, Verify, and Debug. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, you perform the “Generate Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides application programming interfaces (APIs) with high-level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed. A complete code development environment allows you to develop and customize your applications in either C, assembly language, or both. The last step in the development process takes place inside PSoC Designer’s debugger (access by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events. These include monitoring address and data bus values, memory locations, and external signals. Select User Modules PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called “user modules.” User modules make selecting and implementing peripheral devices, both analog and digital, simple. Configure User Modules Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a PWM User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the internal operation of the user module and provide performance specifications. Each datasheet describes the use of each user module parameter, and other information you may need to successfully implement your design. SmartSense A key differentiation between the current offering of CY8C21x34 and CY8C21x34B, is the addition of the SmartSense user module in the ‘B’ version. SmartSense is an innovative solution from Cypress that eliminates the manual tuning process from CapSense applications. This solution is easy to use and provides robust noise immunity. It is the only auto-tuning solution that establishes, monitors and maintains all required tuning parameters. SmartSense allows engineers to go from prototyping to mass production without re-tuning for manufacturing variations in PCB and/or overlay material properties. Organize and Connect You build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. You perform the selection, configuration, and routing so that you have complete control over all on-chip resources. Document Number: 001-67345 Rev. *A Page 7 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Pin Information The CY8C21x34B PSoC device is available in a variety of packages which are listed in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O and connection to the common analog bus. However, VSS, VDD, SMP, and XRES are not capable of Digital I/O. 16-Pin Part Pinout Figure 3. CY8C21234B 16-Pin PSoC Device A, I, M, P0[7] A, I, M, P0[5] A, I, M, P0[3] A, I, M, P0[1] SMP VSS M, I2C SCL, P1[1] VSS 1 2 3 4 5 6 7 8 SOIC 16 15 14 13 12 11 10 9 VDD P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M P0[0], A, I, M P1[4], EXTCLK, M P1[2], M P1[0], I2C SDA, M Table 2. Pin Definitions – CY8C21234B 16-Pin (SOIC) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type Digital I/O I/O I/O I/O Power Power I/O Power I/O I/O I/O I/O I/O I/O I/O Power M M M I, M I, M I, M I, M M Analog I, M I, M I, M I, M Name P0[7] P0[5] P0[3] P0[1] SMP VSS P1[1] VSS P1[0] P1[2] P1[4] P0[0] P0[2] P0[4] P0[6] VDD Optional external clock input (EXTCLK) Analog column mux input Analog column mux input Analog column mux input Analog column mux input Supply voltage Analog column mux input Analog column mux input Analog column mux input, integrating input Analog column mux input, integrating input Switch-mode pump (SMP) connection to required external components Ground connection I2C serial clock (SCL), ISSP-SCLK[3] Ground connection I2C serial data (SDA), ISSP-SDATA[3] Description LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. Note 3. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details. Document Number: 001-67345 Rev. *A Page 8 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B 20-Pin Part Pinout Figure 4. CY8C21334B 20-Pin PSoC Device A, I, M, P0[7] A, I, M, P0[5] A, I, M, P0[3] A, I, M, P0[1] VSS M, I2C SCL, P1[7] M, I2C SDA, P1[5] M, P1[3] M, I2C SCL, P1[1] VSS 1 2 3 4 5 6 7 8 9 10 SSOP 20 19 18 17 16 15 14 13 12 11 VDD P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M P0[0], A, I, M XRES P1[6], M P1[4], EXTCLK, M P1[2], M P1[0], I2C SDA, M Table 3. Pin Definitions – CY8C21334B 20-Pin (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Type Digital I/O I/O I/O I/O Power I/O I/O I/O I/O Power I/O I/O I/O I/O Input I/O I/O I/O I/O Power I, M I, M I, M I, M M M M M M M M M Analog I, M I, M I, M I, M Name P0[7] P0[5] P0[3] P0[1] VSS P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] P1[6] XRES P0[0] P0[2] P0[4] P0[6] VDD Active high external reset with internal pull-down Analog column mux input Analog column mux input Analog column mux input Analog column mux input Supply voltage Optional external clock input (EXTCLK) I2C SCL, ISSP-SCLK[4] Ground connection. I2C SDA, ISSP-SDATA[4] Analog column mux input Analog column mux input Analog column mux input, integrating input Analog column mux input, integrating input Ground connection I2C SCL I2C SDA Description LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. Note 4. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details. Document Number: 001-67345 Rev. *A Page 9 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B 28-Pin Part Pinout Figure 5. CY8C21534B 28-Pin PSoC Device A, I, M, P0[7] A, I, M, P0[5] A, I, M, P0[3] A, I, M, P0[1] M, P2[7] M, P2[5] M, P2[3] M, P2[1] VSS M, I2C SCL, P1[7] M, I2C SDA, P1[5] M, P1[3] M, I2C SCL, P1[1] VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M P0[0], A, I, M P2[6], M P2[4], M P2[2], M P2[0], M XRES P1[6], M P1[4], EXTCLK, M P1[2], M P1[0], I2C SDA, M Table 4. Pin Definitions – CY8C21534B 28-Pin (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Type Digital I/O I/O I/O I/O I/O I/O I/O I/O Power I/O I/O I/O I/O Power I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O Power Analog I, M I, M I, M I, M M M I, M I, M M M M M M M M M I, M I, M M M I, M I, M I, M I, M Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] VSS P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD Description Analog column mux input Analog column mux input and column output Analog column mux input and column output, integrating input Analog column mux input, integrating input Direct switched capacitor block input Direct switched capacitor block input Ground connection I2C SCL I2C SDA I2C SCL, ISSP-SCLK[5] Ground connection I2C SDA, ISSP-SDATA[5] Optional external clock input (EXTCLK) Active high external reset with internal pull-down Direct switched capacitor block input Direct switched capacitor block input Analog column mux input Analog column mux input Analog column mux input Analog column mux input Supply voltage LEGEND A: Analog, I: Input, O = Output, and M = Analog Mux Input. Note 5. These are the ISSP pins, which are not high Z at POR. See the PSoC Technical Reference Manual for details. Document Number: 001-67345 Rev. *A Page 10 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B 32-Pin Part Pinout Figure 6. CY8C21434B 32-Pin PSoC Device Figure 7. CY8C21634B 32-Pin PSoC Device Figure 8. CY8C21434B 32-Pin Sawn PSoC Device Sawn Vss P0[3], A, I, M P0[5], A, I, M P0[7], A, I, M Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M Figure 9. CY8C21634B 32-Pin Sawn PSoC Device Vss P0[3], A, I, M P0[5], A, I, M P0[7], A, I, M Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M 32 31 30 29 28 27 26 25 A, I, M, P0[1] M, P2[7] M, P2[5] M, P2[3] M, P2[1] M, P3[3] M, P3[1] M, I2C SCL, P1[7] 1 2 3 4 5 6 7 8 QFN (Top View) 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 P0[0], A, I, M P2[6], M P2[4], M P2[2], M P2[0], M P3[2], M P3[0], M XRES A, I, M, P0[1] M, P2[7] M, P2[5] M, P2[3] M, P2[1] SMP Vss M, I2C SCL, P1[7] 1 2 3 4 5 6 7 8 32 31 30 29 28 27 26 25 QFN (Top View) M, I2C SDA, P1[5] M, P1[3] M, I2C SCL, P1[1] Vss M, I2C SDA, P1[0] M, P1[2] M, EXTCLK, P1[4] M, P1[6] Document Number: 001-67345 Rev. *A M, I2C SDA, P1[5] M, P1[3] M, I2C SCL, P1[1] Vss M, I2C SDA, P1[0] M, P1[2] M, EXTCLK, P1[4] M, P1[6] 9 10 11 12 13 14 15 16 24 23 22 21 20 19 18 17 P0[0], A, I, M P2[6], M P2[4], M P2[2], M P2[0], M P3[2], M P3[0], M XRES Page 11 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Table 5. Pin Definitions - CY8C21434B/CY8C21634B 32-Pin (QFN)[6] Pin No. 1 2 3 4 5 6 6 7 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Digital I/O I/O I/O I/O I/O I/O Power I/O Power I/O I/O I/O I/O Power I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power I/O I/O I/O Power Type Analog I, M M M M M M M M M M M M M M M M M M M M M I, M I, M I, M I, M I, M I, M I, M Name P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] SMP P3[1] VSS P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD P0[7] P0[5] P0[3] VSS Description Analog column mux input, integrating input In CY8C21434B part SMP connection to required external components in CY8C21634B part In CY8C21434B part Ground connection in CY8C21634B part I2C SCL I2C SDA I2C SCL, ISSP-SCLK[7] Ground connection I2C SDA, ISSP-SDATA[7] Optional external clock input (EXTCLK) Active high external reset with internal pull-down Analog column mux input Analog column mux input Analog column mux input Analog column mux input Supply voltage Analog column mux input Analog column mux input Analog column mux input, integrating input Ground connection LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input. Notes 6. The center pad on the QFN package must be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it must be electrically floated and not connected to any other signal. 7. These are the ISSP pins, which are not high Z at POR. See the PSoC Technical Reference Manual for details. Document Number: 001-67345 Rev. *A Page 12 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B 56-Pin Part Pinout The 56-Pin SSOP part is for the CY8C21001 on-chip debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. Figure 10. CY8C21001 56-Pin PSoC Device V ss P 0[7] P 0[5] P 0[3] P 0[1] P 2[7] P 2[5] P 2[3] P 2[1] NC NC NC NC OCDE OCDO SMP V ss V ss P 3[3] P 3[1] NC NC I2C S C L, P 1[7] I2C S D A , P 1[5] NC P 1[3] S C LK , I2C S C L, P 1[1] V ss A I, A I, A I, A I, 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 V dd P 0[6], P 0[4], P 0[2], P 0[0], P 2[6] AI AI AI AI S SO P P 2[4] P 2[2] P 2[0] NC NC P 3[2] P 3[0] C C LK H C LK XR E S NC NC NC NC NC NC P 1[6] P 1[4], E XTC LK P 1[2] P 1[0], I2C S D A , S D A TA NC NC Table 6. Pin Definitions – CY8C21001 56-Pin (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 Type Digital Power I/O I/O I/O I/O I/O I/O I/O I/O Analog I I I I Pin Name VSS P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] NC NC NC NC OCDE OCDO SMP VSS VSS P3[3] Description Ground connection Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input I I OCD OCD Power Power Power I/O Direct switched capacitor block input Direct switched capacitor block input No connection No connection No connection No connection OCD even data I/O OCD odd data output SMP connection to required external components Ground connection Ground connection Document Number: 001-67345 Rev. *A Page 13 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Table 6. Pin Definitions – CY8C21001 56-Pin (SSOP) (continued) Pin No. 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 I/O Type Digital Analog Pin Name P3[1] NC NC P1[7] P1[5] NC P1[3] P1[1] VSS NC NC P1[0] P1[2] P1[4] P1[6] NC NC NC NC NC NC XRES HCLK CCLK P3[0] P3[2] NC NC P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD Description I/O I/O I/O I/O Power I/O I/O I/O I/O No connection No connection I2C SCL I2C SDA No connection IFMTEST I2C SCL, ISSP-SCLK[8] Ground connection No connection No connection I2C SDA, ISSP-SDATA[8] VFMTEST Optional external clock input (EXTCLK) No connection No connection No connection No connection No connection No connection Active high external reset with internal pull-down OCD high-speed clock output OCD CPU clock output Input OCD OCD I/O I/O No connection No connection I/O I/O I/O I/O I/O I/O I/O I/O Power I I I I I I Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Supply voltage LEGEND: A = Analog, I = Input, O = Output, and OCD = On-Chip Debug. Note 8. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details. Document Number: 001-67345 Rev. *A Page 14 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Register Reference This chapter lists the registers of the CY8C21x34B PSoC device. For detailed register information, see the PSoC Technical Reference Manual. Register Conventions The register conventions specific to this section are listed in Table 7. Table 7. Register Conventions Convention R W L C # Description Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific Register Mapping Tables The PSoC device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks, Bank 0 and Bank 1. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set to 1, the user is in Bank 1. Note In the following register mapping tables, blank fields are reserved and must not be accessed. Document Number: 001-67345 Rev. *A Page 15 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Table 8. Register Map 0 Table: User Space Addr (0,Hex) Access Name 00 RW 01 RW 02 RW 03 RW 04 RW 05 RW 06 RW 07 RW 08 RW 09 RW 0A RW 0B RW 0C RW 0D RW 0E RW 0F RW 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBB00DR0 20 # AMX_IN DBB00DR1 21 W AMUXCFG DBB00DR2 22 RW PWM_CR DBB00CR0 23 # DBB01DR0 24 # CMP_CR0 DBB01DR1 25 W DBB01DR2 26 RW CMP_CR1 DBB01CR0 27 # DCB02DR0 28 # ADC0_CR DCB02DR1 29 W ADC1_CR DCB02DR2 2A RW DCB02CR0 2B # DCB03DR0 2C # TMP_DR0 DCB03DR1 2D W TMP_DR1 DCB03DR2 2E RW TMP_DR2 DCB03CR0 2F # TMP_DR3 30 31 32 ACE00CR1 33 ACE00CR2 34 35 36 ACE01CR1 37 ACE01CR2 38 39 3A 3B 3C 3D 3E 3F Blank fields are reserved and must not be accessed. Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Access Name ASE10CR0 Addr (0,Hex) 80 81 82 83 ASE11CR0 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. Access RW Name Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access RW CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 INT_MSK0 INT_MSK1 INT_VC RES_WDT RW RW RW RW RW RW # RW # RW RW RW RW RW RW RC W RW RW RW # RW # # DEC_CR0 DEC_CR1 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW CPU_F RL DAC_D CPU_SCR1 CPU_SCR0 RW # # Document Number: 001-67345 Rev. *A Page 16 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Table 9. Register Map 1 Table: Configuration Space Addr (1,Hex) Access Name 00 RW 01 RW 02 RW 03 RW 04 RW 05 RW 06 RW 07 RW 08 RW 09 RW 0A RW 0B RW 0C RW 0D RW 0E RW 0F RW 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBB00FN 20 RW CLK_CR0 DBB00IN 21 RW CLK_CR1 DBB00OU 22 RW ABF_CR0 23 AMD_CR0 DBB01FN 24 RW CMP_GO_EN DBB01IN 25 RW DBB01OU 26 RW AMD_CR1 27 ALT_CR0 DCB02FN 28 RW DCB02IN 29 RW DCB02OU 2A RW 2B CLK_CR3 DCB03FN 2C RW TMP_DR0 DCB03IN 2D RW TMP_DR1 DCB03OU 2E RW TMP_DR2 2F TMP_DR3 30 31 32 ACE00CR1 33 ACE00CR2 34 35 36 ACE01CR1 37 ACE01CR2 38 39 3A 3B 3C 3D 3E 3F Blank fields are reserved and must not be accessed. Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Access Name ASE10CR0 Addr (1,Hex) 80 81 82 83 ASE11CR0 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. Access RW Name Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access RW GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU RW RW RW RW MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR IMO_TR ILO_TR BDG_TR ECO_TR RW RW RW RW RW RW RW RW RW RW RW R RW RW W W RW W RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW CPU_F RL FLS_PR1 RW DAC_CR CPU_SCR1 CPU_SCR0 RW # # Document Number: 001-67345 Rev. *A Page 17 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C21x34B PSoC device. For up-to-date electrical specifications, visit the Cypress web site at http://www.cypress.com. Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C as specified, except where noted. Refer to Table 21 on page 25 for the electrical specifications for the IMO using SLIMO mode. Figure 11. Voltage versus CPU Frequency Figure 14. IMO Frequency Trim Options SLIMO Mode = 0 5.25 5.25 SLIMO Mode=1 SLIMO Mode=0 Vdd Voltage Vdd Voltage 4.75 4.75 lid ng Va ati er ion Op eg R 3.60 SLIMO Mode=1 SLIMO Mode=1 SLIMO Mode=1 SLIMO Mode=0 3.00 2.40 93 kHz 3 MHz 12 MHz CPU Frequency 24 MHz 3.00 2.40 93 kHz 6 MHz 12 MHz 24 MHz IMO Frequency Absolute Maximum Ratings Symbol TSTG Description Storage temperature Min –55 Typ 25 Max +100 Units °C Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is +25 °C ± 25 °C. Extended duration storage temperatures above 65 °C degrade reliability. TBAKETEMP tBAKETIME TA VDD VIO VIOZ IMIO ESD LU Bake temperature – 125 Bake time Ambient temperature with power applied Supply voltage on VDD relative to VSS DC input voltage DC voltage applied to tri-state Maximum current into any port pin Electrostatic discharge voltage Latch-up current See package label –40 –0.5 VSS – 0.5 VSS – 0.5 –25 2000 – – See package label 72 °C Hours – – – – – – – +85 +6.0 VDD + 0.5 VDD + 0.5 +50 – 200 °C V V V mA V mA Human body model ESD. Document Number: 001-67345 Rev. *A Page 18 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Operating Temperature Symbol Description TA Ambient temperature TJ Junction temperature Min –40 –40 Typ – – Max +85 +100 Units °C °C Notes The temperature rise from ambient to junction is package specific. See Table 34 on page 36. You must limit the power consumption to comply with this requirement. DC Electrical Characteristics DC Chip-Level Specifications Table 10 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 10. DC Chip-level Specifications Symbol Description VDD Supply voltage IDD Supply current, IMO = 24 MHz Min 2.40 – Typ – 3 Max 5.25 4 Units V mA Notes See Table 18 on page 23 Conditions are VDD = 5.0 V, TA = 25 °C, CPU = 3 MHz, 48 MHz disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz Conditions are VDD = 3.3 V, TA = 25 °C, CPU = 3 MHz, clock doubler disabled. VC1 = 375 kHz, VC2 = 23.4 kHz, VC3 = 0.091 kHz Conditions are VDD = 2.55 V, TA = 25 °C, CPU = 3 MHz, clock doubler disabled. VC1 = 375 kHz, VC2 = 23.4 kHz, VC3 = 0.091 kHz VDD = 2.55 V, 0 °C ≤ TA ≤ 40 °C VDD = 3.3 V, –40 °C ≤ TA ≤ 85 °C Trimmed for appropriate VDD VDD = 3.0 V to 5.25 V Trimmed for appropriate VDD VDD = 2.4 V to 3.0 V IDD3 Supply current, IMO = 6 MHz using SLIMO mode. – 1.2 2 mA IDD27 Supply current, IMO = 6 MHz using SLIMO mode. – 1.1 1.5 mA ISB27 ISB VREF VREF27 AGND Sleep (mode) current with POR, LVD, sleep timer, WDT, and internal slow oscillator active. Mid temperature range. Sleep (mode) current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Reference voltage (Bandgap) Reference voltage (Bandgap) Analog ground – 2.6 4 µA – 2.8 5 µA 1.28 1.16 VREF – 0.003 1.30 1.30 VREF 1.32 1.33 VREF + 0.003 V V V Document Number: 001-67345 Rev. *A Page 19 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B DC General-Purpose I/O Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, and 2.7 V at 25 °C and are for design guidance only. Table 11. 5-V and 3.3-V DC GPIO Specifications Symbol Description Pull-up resistor RPU Pull-down resistor RPD High output level VOH Min 4 4 VDD – 1.0 Typ 5.6 5.6 – Max 8 8 – Units kΩ kΩ V Notes VOL Low output level – – 0.75 V IOH IOL VIL VIH VH IIL CIN COUT High level source current Low level sink current Input low level Input high level Input hysteresis Input leakage (absolute value) Capacitive load on pins as input Capacitive load on pins as output 10 25 – 2.1 – – – – – – – – 60 1 3.5 3.5 – – 0.8 – – 10 10 mA mA V V mV nA pF pF IOH = 10 mA, VDD = 4.75 to 5.25 V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5]) IOL = 25 mA, VDD = 4.75 to 5.25 V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])) VOH = VDD – 1.0 V, see the limitations of the total current in the note for VOH VOL = 0.75 V, see the limitations of the total current in the note for VOL VDD = 3.0 to 5.25 VDD = 3.0 to 5.25 Gross tested to 1 µA Package and pin dependent Temp = 25 °C Package and pin dependent Temp = 25 °C Table 12. 2.7-V DC GPIO Specifications Symbol Description RPU Pull-up resistor RPD Pull-down resistor VOH High output level VOL IOH IOL VIL VIH VH IIL CIN COUT Low output level High level source current Low level sink current Input low level Input high level Input hysteresis Input leakage (absolute value) Capacitive load on pins as input Capacitive load on pins as output Min 4 4 VDD – 0.4 – 2.5 10 – 2.0 – – – – Typ 5.6 5.6 – Max 8 8 – Units kΩ kΩ V Notes – – – – – 90 1 3.5 3.5 0.75 – – 0.75 – – – 10 10 V mA mA V V mV nA pF pF IOH = 2.5 mA (6.25 Typ), VDD = 2.4 to 3.0 V (16 mA maximum, 50 mA Typ combined IOH budget) IOL = 10 mA, VDD = 2.4 to 3.0 V (90 mA maximum combined IOL budget) VOH = VDD – 0.4 V, see the limitations of the total current in the note for VOH VOL = 0.75 V, see the limitations of the total current in the note for VOL VDD = 2.4 to 3.0 VDD = 2.4 to 3.0 Gross tested to 1 µA Package and pin dependent Temp = 25 °C Package and pin dependent Temp = 25 °C Document Number: 001-67345 Rev. *A Page 20 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B DC Operational Amplifier Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 13. 5-V DC Operational Amplifier Specifications Symbol VOSOA TCVOSOA IEBOA IEBOA00 CINOA VCMOA GOLOA ISOA Description Input offset voltage (absolute value) Average input offset voltage drift Input leakage current (Port 0 analog pins 7-to-1) Input leakage current (Port 0, Pin 0 analog pin) Input capacitance (Port 0 analog pins) Common mode voltage range Open loop gain Amplifier supply current Min – – – – – 0.0 – – Typ 2.5 10 200 50 4.5 – 80 10 Max 15 – – – 9.5 VDD – 1.0 – 30 Units mV µV/°C pA nA pF V dB µA Notes Gross tested to 1 µA Gross tested to 1 µA Package and pin dependent. Temp = 25 °C Table 14. 3.3-V DC Operational Amplifier Specifications Symbol VOSOA IEBOA IEBOA00 CINOA VCMOA GOLOA ISOA Description Input offset voltage (absolute value) Input leakage current (Port 0 analog pins) Input leakage current (Port 0, Pin 0 analog pin) Input capacitance (Port 0 analog pins) Common mode voltage range Open loop gain Amplifier supply current Min – – – – – 0 – – Typ 2.5 10 200 50 4.5 – 80 10 Max 15 – – – 9.5 VDD – 1.0 – 30 Units mV µV/°C pA nA pF V dB µA Gross tested to 1 µA Gross tested to 1 µA Package and pin dependent. Temp = 25 °C Notes TCVOSOA Average input offset voltage drift Table 15. 2.7-V DC Operational Amplifier Specifications Symbol VOSOA IEBOA IEBOA00 CINOA VCMOA GOLOA ISOA Description Input offset voltage (absolute value) Input leakage current (Port 0 analog pins) Input leakage current (Port 0, Pin 0 analog pin) Input capacitance (Port 0 analog pins) Common mode voltage range Open loop gain Amplifier supply current Min – – – – – 0 – – Typ 2.5 10 200 50 4.5 – 80 10 Max 15 – – – 9.5 VDD – 1.0 – 30 Units mV µV/°C pA nA pF V dB µA Gross tested to 1 µA Gross tested to 1 µA Package and pin dependent. Temp = 25 °C Notes TCVOSOA Average input offset voltage drift Document Number: 001-67345 Rev. *A Page 21 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B DC Switch Mode Pump Specifications Table 16 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Figure 12. Basic Switch Mode Pump Circuit D1 Vdd V PUMP L1 V BAT + SMP Battery PSoC Vss C1 Table 16. DC Switch Mode Pump (SMP) Specifications Symbol VPUMP5V VPUMP3V VPUMP2V IPUMP Description 5 V output voltage from pump Min 4.75 Typ 5.0 Max 5.25 Units V Notes Configured as in Note 9 Average, neglecting ripple SMP trip voltage is set to 5.0 V Configured as in Note 9 Average, neglecting ripple. SMP trip voltage is set to 3.25 V Configured as in Note 9 Average, neglecting ripple. SMP trip voltage is set to 2.55 V Configured as in Note 9 SMP trip voltage is set to 5.0 V SMP trip voltage is set to 3.25 V SMP trip voltage is set to 2.55 V Configured as in Note 9 SMP trip voltage is set to 5.0 V Configured as in Note 9 SMP trip voltage is set to 3.25 V Configured as in Note 9 SMP trip voltage is set to 2.55 V Configured as in Note 9 0 °C ≤ TA ≤ 100. 1.25 V at TA = –40 °C Configured as in Note 9 VO is the “VDD Value for PUMP Trip” specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 18 on page 23 Configured as in Note 9 VO is the “VDD Value for PUMP Trip” specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 18 on page 23 3.3 V output voltage from pump 3.00 3.25 3.60 V 2.6 V output voltage from pump 2.45 2.55 2.80 V Available output current VBAT = 1.8 V, VPUMP = 5.0 V VBAT = 1.5 V, VPUMP = 3.25 V VBAT = 1.3 V, VPUMP = 2.55 V Input voltage range from battery Input voltage range from battery Input voltage range from battery Minimum input voltage from battery to start pump 5 8 8 1.8 1.0 1.0 1.2 – – – – – – – – – – 5.0 3.3 2.8 – mA mA mA V V V V VBAT5V VBAT3V VBAT2V VBATSTART ΔVPUMP_Line Line regulation (over Vi range) – 5 – %VO ΔVPUMP_Load Load regulation – 5 – %VO Note 9. L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. See Figure 12. Document Number: 001-67345 Rev. *A Page 22 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Table 16. DC Switch Mode Pump (SMP) Specifications (continued) Symbol Description Min – 35 Typ 100 50 Max – – Units mVpp % Notes Configured as in Note 9 Load is 5 mA Configured as in Note 9 Load is 5 mA. SMP trip voltage is set to 3.25 V For I load = 1mA, VPUMP = 2.55 V, VBAT = 1.3 V, 10 µH inductor, 1 µF capacitor, and Schottky diode ΔVPUMP_Ripple Output voltage ripple (depends on cap/load) E3 E2 Efficiency Efficiency 35 80 – % FPUMP DCPUMP Switching frequency Switching duty cycle – – 1.3 50 – – MHz % DC Analog Mux Bus Specifications Table 17 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 17. DC Analog Mux Bus Specifications Symbol RSW RVDD Description Switch resistance to common analog bus Resistance of initialization switch to VDD Min – – Typ – – Max 400 800 800 Units Ω Ω Notes VDD ≥ 2.7 V 2.4 V ≤ VDD ≤ 2.7 V DC POR and LVD Specifications Table 18 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 18. DC POR and LVD Specifications Symbol VPPOR0 VPPOR1 VPPOR2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 Description VDD value for PPOR trip PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b VDD value for LVD trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b VDD value for pump trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min – – – 2.40 2.85 2.95 3.06 4.37 4.50 4.62 4.71 2.45 2.96 3.03 3.18 4.54 4.62 4.71 4.89 Typ 2.36 2.82 4.55 2.45 2.92 3.02 3.13 4.48 4.64 4.73 4.81 2.55 3.02 3.10 3.25 4.64 4.73 4.82 5.00 Max 2.40 2.95 4.70 2.51[10] 2.99[11] 3.09 3.20 4.55 4.75 4.83 4.95 2.62[12] 3.09 3.16 3.32[13] 4.74 4.83 4.92 5.12 Units V V V V V V V V V V V V V V V V V V V Notes VDD must be greater than or equal to 2.5 V during startup, the reset from the XRES pin, or reset from watchdog Notes 10. Always greater than 50 mV above VPPOR (PORLEV = 00) for falling supply. 11. Always greater than 50 mV above VPPOR (PORLEV = 01) for falling supply. 12. Always greater than 50 mV above VLVD0. 13. Always greater than 50 mV above VLVD3. Document Number: 001-67345 Rev. *A Page 23 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B DC Programming Specifications Table 19 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 19. DC Programming Specifications Symbol VDDP VDDLV VDDHV VDDIWRITE IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR Description VDD for programming and erase Low VDD for verify High VDD for verify Supply voltage for flash write operation Min 4.5 Typ 5 Max 5.5 Units V Notes This specification applies to the functional requirements of external programmer tools This specification applies to the functional requirements of external programmer tools This specification applies to the functional requirements of external programmer tools This specification applies to this device when it is executing internal flash writes 2.4 2.5 2.6 V 5.1 5.2 5.3 V 2.7 5.25 V Supply current during programming or verify Input low voltage during programming or verify Input high voltage during programming or verify Input current when applying VILP to P1[0] or P1[1] during programming or verify Input current when applying VIHP to P1[0] or P1[1] during programming or verify Output low voltage during programming or verify Output high voltage during programming or verify Flash endurance (per block) Flash endurance (total)[15] Flash data retention – – 2.2 – – – VDD – 1.0 50,000[14] 1,800,000 10 5 – – – – – – – – – 25 0.8 – 0.2 1.5 VSS + 0.75 VDD – – – mA V V mA mA V V – – Years Erase/write cycles per block Erase/write cycles Driving internal pull-down resistor Driving internal pull-down resistor DC I2C Specifications Table 20 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 20. DC I2C Specifications[16] Symbol VILI2C VIHI2C Description Input low level Input high level Min – – 0.7 × VDD Typ – – – Max 0.3 × VDD 0.25 × VDD – Units V V V Notes 2.4 V ≤ VDD ≤ 3.6 V 4.75 V ≤ VDD ≤ 5.25 V 2.4 V ≤ VDD ≤ 5.25 V Notes 14. The 50,000 cycle flash endurance per block is only guaranteed if the flash is operating within one voltage range. Voltage ranges are 2.4 V to 3.0 V, 3.0 V to 3.6 V, and 4.75 V to 5.25 V. 15. A maximum of 36 × 50,000 block endurance cycles is allowed. This may be balanced between operations on 36 × 1 blocks of 50,000 maximum cycles each, 36×2 blocks of 25,000 maximum cycles each, or 36 × 4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36 × 50,000 and ensure that no single block ever sees more than 50,000 cycles). For the full industrial range, you must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs application note AN2015 (Design Aids - Reading and Writing PSoC® Flash) for more information. 16. All GPIO meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I2C GPIO pins also meet the above specs. Document Number: 001-67345 Rev. *A Page 24 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B AC Electrical Characteristics AC Chip-Level Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 21. 5-V and 3.3-V AC Chip-Level Specifications Symbol FIMO24 Description IMO frequency for 24 MHz Min 23.4 Typ 24 Max 24.6[17,18] Units MHz Notes Trimmed for 5 V or 3.3 V operation using factory trim values. See Figure 14 on page 18. SLIMO mode = 0 Trimmed for 5 V or 3.3 V operation using factory trim values. See Figure 14 on page 18. SLIMO mode = 1 24 MHz only for SLIMO mode = 0 SLIMO mode = 0 Refer to AC Digital Block Specifications on page 28 FIMO6 IMO frequency for 6 MHz 5.5 6 6.5[17,18] MHz FCPU1 FCPU2 FBLK5 FBLK33 F32K1 F32K_U CPU frequency (5 V nominal) CPU frequency (3.3 V nominal) Digital PSoC block frequency0(5 V nominal) Digital PSoC block frequency (3.3 V nominal) ILO frequency ILO untrimmed frequency 0.091 0.091 0 0 15 5 24 12 48 24 32 – 24.6[17] 12.3[18] 49.2[17,19] 24.6[19] 64 100 MHz MHz MHz MHz kHz kHz After a reset and before the M8C starts to run, the ILO is not trimmed. See the system resets section of the PSoC Technical Reference Manual for details on this timing tXRST DC24M DCILO Step24M Fout48M FMAX SRPOWER_UP tPOWERUP External reset pulse width 24 MHz duty cycle ILO duty cycle 24 MHz trim step size 48 MHz output frequency Maximum frequency of signal on row input or row output. Power supply slew rate Time from end of POR to CPU executing code 10 40 20 – 46.8 – – – – 50 50 50 48.0 – – 16 – 60 80 – 49.2[17,18] 12.3 250 100 μs % % kHz MHz MHz V/ms ms Trimmed. Using factory trim values VDD slew rate during power-up Power-up from 0 V. See the System Resets section of the PSoC Technical Reference Manual N = 32 tjit_IMO 24-MHz IMO cycle-to-cycle jitter (RMS)[20] 24-MHz IMO long term N cycle-to-cycle jitter (RMS)[20] 24-MHz IMO period jitter (RMS)[20] – – – 200 300 100 700 900 400 ps ps ps Notes 17. 4.75 V < VDD < 5.25 V. 18. 3.0 V < VDD < 3.6 V. See application note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3 V. 19. See the individual user module datasheets for information on maximum frequencies for user modules. 20. Refer to Cypress Jitter Specifications Application Note AN5054 “Understanding Datasheet Jitter Specifications for Cypress Timing Products” at www.cypress.com under Application Notes for more information. Document Number: 001-67345 Rev. *A Page 25 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Table 22. 2.7-V AC Chip-Level Specifications Symbol FIMO12 Description IMO frequency for 12 MHz Min 11.5 Typ 120 Max 12.7[21,22] Units MHz Notes Trimmed for 2.7 V operation using factory trim values. See Figure 14 on page 18. SLIMO mode = 1 Trimmed for 2.7 V operation using factory trim values. See Figure 14 on page 18. SLIMO mode = 1 12 MHz only for SLIMO mode = 0 Refer to AC Digital Block Specifications on page 28 After a reset and before the M8C starts to run, the ILO is not trimmed. See the System Resets section of the PSoC Technical Reference Manual for details on this timing FIMO6 IMO frequency for 6 MHz 5.5 6 6.5[21,22] MHz FCPU1 FBLK27 F32K1 F32K_U CPU frequency (2.7 V nominal) Digital PSoC block frequency (2.7 V nominal) ILO frequency ILO untrimmed frequency 0.093 0 8 5 3 12 32 – 3.15[21] 12.5[21,22] 96 100 MHz MHz kHz kHz tXRST DCILO FMAX SRPOWER_UP tPOWERUP External reset pulse width IILO duty cycle Maximum frequency of signal on row input or row output. Power supply slew rate Time from end of POR to CPU executing code 10 20 – – – – 50 – – 16 – 80 12.3 250 100 µs % MHz V/ms ms VDD slew rate during power-up Power-up from 0 V. See the System Resets section of the PSoC Technical Reference Manual. N = 32 tjit_IMO 12 MHz IMO cycle-to-cycle jitter (RMS)[23] 12 MHz IMO long term N cycle-to-cycle jitter (RMS)[23] 12 MHz IMO period jitter (RMS)[23] – – – 400 600 100 1000 1300 500 ps ps ps Note 21. 2.4 V < VDD < 3.0 V. 22. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” available at http://www.cypress.com for information on maximum frequency for user modules. 23. Refer to Cypress Jitter Specifications Application Note AN5054 “Understanding Datasheet Jitter Specifications for Cypress Timing Products” at www.cypress.com under Application Notes for more information. Document Number: 001-67345 Rev. *A Page 26 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B AC General Purpose I/O Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 23. 5-V and 3.3-V AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO operating frequency Rise time, normal strong mode, Cload = 50 pF Fall time, normal strong mode, Cload = 50 pF Rise time, slow strong mode, Cload = 50 pF Fall time, slow strong mode, Cload = 50 pF Min 0 3 2 7 7 Typ – – – 27 22 Max 12 18 18 – – Units MHz ns ns ns ns Notes Normal strong mode VDD = 4.5 to 5.25 V, 10% to 90% VDD = 4.5 to 5.25 V, 10% to 90% VDD = 3 to 5.25 V, 10% to 90% VDD = 3 to 5.25 V, 10% to 90% Table 24. 2.7 V AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO operating frequency Rise time, normal strong mode, Cload = 50 pF Fall time, normal strong mode, Cload = 50 pF Rise time, slow strong mode, Cload = 50 pF Fall time, slow strong mode, Cload = 50 pF Min 0 6 6 18 18 Typ – – – 40 40 Max 3 50 50 120 120 Units MHz ns ns ns ns Notes Normal strong mode VDD = 2.4 to 3.0 V, 10% to 90% VDD = 2.4 to 3.0 V, 10% to 90% VDD = 2.4 to 3.0 V, 10% to 90% VDD = 2.4 to 3.0 V, 10% to 90% Figure 13. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS AC Operational Amplifier Specifications Table 25 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 25. AC Operational Amplifier Specifications Symbol TCOMP Description Comparator mode response time, 50 mV overdrive Min – Typ – Max 100 200 Units ns ns Notes VDD ≥ 3.0 V 2.4 V < VCC < 3.0 V Document Number: 001-67345 Rev. *A Page 27 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B AC Digital Block Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 26. 5-V and 3.3-V AC Digital Block Specifications Function All functions Description Block input clock frequency VDD ≥ 4.75 V VDD < 4.75 V Timer Input clock frequency No capture, VDD ≥ 4.75 V No capture, VDD < 4.75 V With capture Capture pulse width Counter Input clock frequency No enable input, VDD ≥ 4.75 V No enable input, VDD < 4.75 V With enable input Enable input pulse width Dead Band Kill pulse width Asynchronous restart mode Synchronous restart mode Disable mode Input clock frequency VDD ≥ 4.75 V VDD < 4.75 V CRCPRS (PRS Mode) CRCPRS (CRC Mode) SPIM SPIS Input clock frequency VDD ≥ 4.75 V VDD < 4.75 V Input clock frequency – – – – – – 49.2 24.6 24.6 MHz MHz MHz – – – – 49.2 24.6 MHz MHz 20 50 [24] Min – – – – – 50[24] – – – 50[24] Typ – – – – – – – – – – – – – Max 49.2 24.6 49.2 24.6 24.6 – 49.2 24.6 24.6 – – – – Unit MHz MHz MHz MHz MHz ns MHz MHz MHz ns ns ns ns Notes 50[24] Input clock frequency Input clock (SCLK) frequency Width of SS_negated between transmissions – – 50[24] – – – 8.2 4.1 – MHz MHz ns The SPI serial clock (SCLK) frequency is equal to the input clock frequency divided by 2. The input clock is the SPI SCLK in SPIS mode. Transmitter Input clock frequency VDD ≥ 4.75 V, 2 stop bits VDD ≥ 4.75 V, 1 stop bit VDD < 4.75 V – – – – – – 49.2 24.6 24.6 MHz MHz MHz The baud rate is equal to the input clock frequency divided by 8. Receiver Input clock frequency VDD ≥ 4.75 V, 2 stop bits VDD ≥ 4.75 V, 1 stop bit VDD < 4.75 V – – – – – – 49.2 24.6 24.6 MHz MHz MHz The baud rate is equal to the input clock frequency divided by 8. Note 24. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). Document Number: 001-67345 Rev. *A Page 28 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Table 27. 2.7-V AC Digital Block Specifications Function All functions Timer Counter Description Block input clock frequency Capture pulse width Input clock frequency, with or without capture Enable input pulse width Input clock frequency, no enable input Input clock frequency, enable input Dead Band Kill pulse width: Asynchronous restart mode Synchronous restart mode Disable mode Input clock frequency CRCPRS (PRS Mode) CRCPRS (CRC Mode) SPIM Input clock frequency Input clock frequency Input clock frequency 20 100 100 – – – – – – – – – – – – – – 12.7 12.7 12.7 6.35 ns ns ns MHz MHz MHz MHz The SPI serial clock (SCLK) frequency is equal to the input clock frequency divided by 2. Min – 100[25] – 100 – – Typ – – – – – – Max 12.7 – 12.7 – 12.7 12.7 Units MHz ns MHz ns MHz MHz Notes 2.4 V < VDD < 3.0 V SPIS Transmitter Receiver Input clock (SCLK) frequency Width of SS_ Negated between transmissions Input clock frequency Input clock frequency – 100 – – – – – – 4.1 – 12.7 12.7 MHz ns MHz MHz The baud rate is equal to the input clock frequency divided by 8. The baud rate is equal to the input clock frequency divided by 8. AC External Clock Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 28. 5-V AC External Clock Specifications Symbol FOSCEXT – – – Frequency High period Low period Power-up IMO to switch Description Min 0.093 20.6 20.6 150 Typ – – – – Max 24.6 5300 – – Units MHz ns ns µs Notes Note 25. 100 ns minimum input pulse width is based on the input synchronizers running at 12 MHz (84 ns nominal period). Document Number: 001-67345 Rev. *A Page 29 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Table 29. 3.3-V AC External Clock Specifications Symbol FOSCEXT Description Frequency with CPU clock divide by 1 Min 0.093 Typ – Max 12.3 Units MHz Notes Maximum CPU frequency is 12 MHz at 3.3 V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met FOSCEXT Frequency with CPU clock divide by 2 or greater 0.186 – 24.6 MHz – – – High period with CPU clock divide by 1 Low period with CPU clock divide by 1 Power-up IMO to switch 41.7 41.7 150 – – – 5300 – – ns ns µs Table 30. 2.7-V AC External Clock Specifications Symbol FOSCEXT Description Frequency with CPU clock divide by 1 Min 0.093 Typ – Max 3.08 0 Units MHz Notes Maximum CPU frequency is 3 MHz at 2.7 V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements If the frequency of the external clock is greater than 3 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the fifty percent duty cycle requirement is met FOSCEXT Frequency with CPU clock divide by 2 or greater 0.186 – 6.35 MHz – – – High period with CPU clock divide by 1 Low period with CPU clock divide by 1 Power-up IMO to switch 160 160 150 – – – 5300 – – ns ns µs Document Number: 001-67345 Rev. *A Page 30 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B AC Programming Specifications Table 31 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 31. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 TDSCLK2 TERASEALL TPROGRAM_HOT TPROGRAM_COLD Description Rise time of SCLK Fall time of SCLK Data setup time to falling edge of SCLK Data hold time from falling edge of SCLK Frequency of SCLK Flash erase time (block) Flash block write time Data out delay from falling edge of SCLK Data out delay from falling edge of SCLK Data out delay from falling edge of SCLK Flash erase time (Bulk) Flash block erase + flash block write time Flash block erase + flash block write time Min 1 1 40 40 0 – – – – – – – – Typ – – – – – 10 40 – – – 20 – – Max 20 20 – – 8 – – 45 50 70 – 100[26] 200[26] Units ns ns ns ns MHz ms ms ns ns ns ms ms ms Notes 3.6 < VDD 3.0 ≤ VDD ≤ 3.6 2.4 ≤ VDD ≤ 3.0 Erase all blocks and protection fields at once 0 °C ≤ Tj ≤ 100 °C –40 °C ≤ Tj ≤ 0 °C AC I2C Specifications The following tables list the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V, 3.3 V, or 2.7 V at 25 °C and are for design guidance only. Table 32. AC Characteristics of the I2C SDA and SCL Pins for VDD ≥ 3.0 V Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Description SCL clock frequency Hold time (repeated) start condition. After this period, the first clock pulse is generated Low period of the SCL clock High period of the SCL clock Setup time for a repeated start condition Data hold time Data setup time Setup time for stop condition Bus free time between a stop and start condition Pulse width of spikes suppressed by the input filter. Standard Mode Min Max 0 100 4.0 – 4.7 4.0 4.7 0 250 4.0 4.7 – – – – – – – – – Fast Mode Min Max 0 400 0.6 – 1.3 0.6 0.6 0 100[27] 0.6 1.3 0 – – – – – – – 50 Units kHz µs µs µs µs µs ns µs µs ns Notes 26. For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs application note AN2015 (Design Aids - Reading and Writing PSoC® Flash) for more information. 27. A Fast-Mode I2C-bus device may be used in a Standard-Mode I2C-bus system, but it must meet the requirement TSU;DAT ≥ 250 ns. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If the device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line Trmax + TSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 001-67345 Rev. *A Page 31 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Table 33. 2.7-V AC Characteristics of the I2C SDA and SCL Pins (Fast Mode not Supported) Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Description SCL clock frequency Hold time (repeated) start condition. After this period, the first clock pulse is generated. Low period of the SCL clock High period of the SCL clock Setup time for a repeated start condition Data hold time Data setup time Setup time for stop condition Bus free time between a stop and start condition Pulse width of spikes are suppressed by the input filter. Standard Mode Min Max 0 100 4.0 – 4.7 4.0 4.7 0 250 4.0 4.7 – – – – – – – – – Fast Mode Min – – – – – – – – – – Max – – – – – – – – – – Units kHz µs µs µs µs µs ns µs µs ns Figure 14. Definition for Timing for Fast/Standard Mode on the I2C Bus I2C_SDA TSUDATI2C THDSTAI2C I2C_SCL TSPI2C THDDATI2CTSUSTAI2C TBUFI2C THIGHI2C TLOWI2C S START Condition Sr Repeated START Condition TSUSTOI2C P STOP Condition S Document Number: 001-67345 Rev. *A Page 32 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Packaging Information This section shows the packaging specifications for the CY8C21x34B PSoC device with the thermal impedances for each package. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com. Figure 15. 16-Pin (150-Mil) SOIC 51-85068 *C Figure 16. 20-Pin (210-Mil) SSOP 51-85077 *E Document Number: 001-67345 Rev. *A Page 33 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Figure 17. 28-Pin (210-Mil) SSOP 51-85079 *E Figure 18. 32-Pin QFN ( 5 X 5 X 1.0 MM) LT32B (3.5 X 3.5) EPAD (SAWN) 001-30999 *C Document Number: 001-67345 Rev. *A Page 34 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Figure 19. 32-Pin (5 × 5 × 0.4 mm) QFN (Sawn 1.85 × 2.85) EPAD 0.064 -0.090 PIN#1 (LASER MARKED) 0.400±0.100 0.500 0.25±0.040 32 PIN 1 I.D 0.10 MIN 24 25 2.85±0.10 17 16 9 8 1 TOP VIEW 0.15max BARE COOPER NOTES : 1. HATCH AREA IS SOLDERABLE EXPOSED PAD. 2. ALL DIMENSIONS ARE IN MILLIMETERS. 3. REFERENCE JEDEC #: MO-220 4. MAXIMUM ALLOWABLE METAL IS 0.0508mm 5. PACKAGE WEIGHT: 0.029 grams 0.127 0.064 Figure 20. 32-Pin Thin Sawn QFN Package Important Note For information on the preferred dimensions for mounting QFN packages, see the Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages available at http://www.amkor.com. Document Number: 001-67345 Rev. *A Page 35 of 47 SOLDERABLE 1.85±0.10 BOTTOM VIEW EXPOSED PAD 0.400 0.300 MIN 001-44368 *B 001-48913 *B [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Figure 21. 56-Pin (300-Mil) SSOP 51-85062 *D Thermal Impedances Table 34. Thermal Impedances per Package Package 16-Pin SOIC 20-Pin SSOP 28-Pin SSOP 32-Pin QFN[29] 5 × 5 mm 0.60 Max 32-Pin QFN[29] 5 × 5 mm 0.93 Max 56-Pin SSOP Typical θJA [28] 123 °C/W 117 °C/W 96 °C/W 27 °C/W 22 °C/W 48 °C/W Typical θJC 55 °C/W 41 °C/W 39 °C/W 15 °C/W 12 °C/W 24 °C/W Solder Reflow Peak Temperature Table 35 lists the maximum solder reflow peak temperatures to achieve good solderability. Thermal ramp rate during preheat should be 3 °C/s or lower. Table 35. Solder Reflow Peak Temperature Package 16-Pin SOIC 20-Pin SSOP 28-Pin SSOP 32-Pin QFN 56-Pin SSOP Maximum Peak Temperature 260 °C 260 °C 260 °C 260 °C 260 °C Time at Maximum Temperature 20 s 20 s 20 s 20 s 20 s Notes 28. TJ = TA + Power × θJA 29. To achieve the thermal impedance specified for the QFN package, refer to Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages available at http://www.amkor.com. 30. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 °C with Sn-Pb or 245 ± 5 °C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. Document Number: 001-67345 Rev. *A Page 36 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Development Tool Selection This section presents the development tools available for all current PSoC device families including the CY8C21x34B family. Evaluation Tools All evaluation tools can be purchased from the Cypress Online Store. CY3210-MiniProg1 The CY3210-MiniProg1 kit allows you to program PSoC devices through the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC through a provided USB 2.0 cable. The kit includes: ■ ■ ■ ■ ■ ■ ■ Software PSoC Designer™ At the core of the PSoC development software suite is PSoC Designer, used to generate PSoC firmware applications. PSoC Designer is available free of charge at http://www.cypress.com and includes a free C compiler. PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or operates directly from PSoC Designer. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free of charge at http://www.cypress.com. MiniProg programming unit MiniEval socket programming and evaluation board 28-Pin CY8C29466-24PXI PDIP PSoC device sample 28-Pin CY8C27443-24PXI PDIP PSoC device sample PSoC Designer software CD Getting Started guide USB 2.0 cable Development Kits All development kits can be purchased from the Cypress Online Store. CY3215-DK Basic Development Kit The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation, and the software interface allows you to run, halt, and single step the processor, and view the content of specific memory locations. Advance emulation features also supported through PSoC Designer. The kit includes: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ CY3210-PSoCEval1 The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: ■ ■ ■ ■ ■ ■ Evaluation board with LCD module MiniProg programming unit Two 28-Pin CY8C29466-24PXI PDIP PSoC device samples PSoC Designer software CD Getting Started guide USB 2.0 cable PSoC Designer software CD ICE-Cube in-circuit emulator ICE Flex-Pod for CY8C29x66 family Cat-5 adapter Mini-Eval programming board 110 ~ 240 V power supply, Euro-Plug adapter iMAGEcraft C compiler ISSP cable USB 2.0 cable and Blue Cat-5 cable Two CY8C29466-24PXI 28-PDIP chip samples CY3214-PSoCEvalUSB The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. The board includes both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: ■ ■ ■ ■ ■ ■ ■ PSoCEvalUSB board LCD module MIniProg programming unit Mini USB cable PSoC Designer and example projects CD Getting Started guide Wire pack Document Number: 001-67345 Rev. *A Page 37 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Device Programmers All device programmers can be purchased from the Cypress Online Store. CY3216 Modular Programmer The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes: ■ ■ ■ ■ ■ ■ CY3207ISSP In-System Serial Programmer (ISSP) The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. Note CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes: ■ ■ ■ ■ Modular programmer base Three programming module cards MiniProg programming unit PSoC Designer software CD Getting Started guide USB 2.0 cable CY3207 programmer unit PSoC ISSP software CD 110 ~ 240 V power supply, Euro-Plug adapter USB 2.0 cable Accessories (Emulation and Programming) Table 36. Emulation and Programming Accessories Part Number CY8C21234B-24SXI CY8C21334B-24PVXI CY8C21534B-24PVXI Pin Package 16-Pin SOIC 20-Pin SSOP 28-Pin SSOP Flex-Pod Kit[31] CY3250-21X34 CY3250-21X34 CY3250-21X34 Foot Kit[32] CY3250-16SOIC-FK CY3250-20SSOP-FK CY3250-28SSOP-FK Adapter Adapters can be found at http://www.emulation.com. Notes 31. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. 32. Foot kit includes surface mount feet that can be soldered to the target PCB. Document Number: 001-67345 Rev. *A Page 38 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Ordering Information Switch Mode Pump Temperature Range Digital I/O Pins XRES Pin No No Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes [+] Feedback Ordering Code Package 16-Pin (150-Mil) SOIC 16-Pin (150-Mil) SOIC (Tape and Reel) 20-Pin (210-Mil) SSOP 20-Pin (210-Mil) SSOP (Tape and Reel) 28-Pin (210-Mil) SSOP 28-Pin (210-Mil) SSOP (Tape and Reel) 32-Pin (5 × 5 mm 1.00 max) Sawn QFN CY8C21x34B-24SXI CY8C21x34B-24SXIT CY8C21x34B-24PVXI CY8C21x34B-24PVXIT CY8C21x34B-24PVXI CY8C21x34B-24PVXIT CY8C21x34B-24LTXI 8K 8K 8K 8K 8K 8K 8K 8K 8K 8K 512 512 512 512 512 512 512 512 512 512 Yes Yes No No No No No No No No –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 12 12 16 16 24 24 28 28 28 28 12[33] 12[33] 16[33] 16 [33] 24[33] 24 [33] 28[33] 28[33] 28[33] 28[33] 32-Pin (5 × 5 mm 1.00 max) CY8C21x34B-24LTXIT Sawn QFN [34] (Tape and Reel) 32-Pin (5 × 5 mm 0.40 max) Sawn QFN[34] 32-Pin (5 × 5 mm 0.40 max) Sawn QFN[34] (Tape and Reel) 32-Pin (5 × 5 mm 0.60 max) Thin Sawn QFN 32-Pin (5 × 5 mm 0.60 max) Thin Sawn QFN (Tape and Reel) 56-Pin OCD SSOP CY8C21x34B-24LCXI CY8C21x34B-24LCXIT CY8C21x34B-24LQXI CY8C21x34B-24LQXIT 8K 8K 512 512 No No –40 °C to +85 °C –40 °C to +85 °C 4 4 4 4 28 28 28[33] 28[33] CY8C21001-24PVXI 8K 512 Yes –40 °C to +85 °C 4 4 26 26[33] Note For Die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE). Notes 33. All Digital I/O Pins also connect to the common analog mux. 34. Refer to the section 32-Pin Part Pinout on page 11 for pin differences. Document Number: 001-67345 Rev. *A Page 39 of 47 Analog Outputs 0 0 0 0 0 0 0 0 0 0 0 0 0 Flash (Bytes) SRAM (Bytes) Analog Blocks Analog Inputs Digital Blocks CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Ordering Code Definitions CY 8 C 21 xxxx-24 xx Package Type: Thermal Rating: PX = PDIP Pb-free C = Commercial SX = SOIC Pb-free I = Industrial PVX = SSOP Pb-free E = Extended LFX/LKX/LTX/LCX/LQX = QFN Pb-free Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress Document Number: 001-67345 Rev. *A Page 40 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Acronyms Table 37 lists the acronyms that are used in this document. Table 37. Acronyms Used in this Datasheet Acronym AC ADC API CMOS CPU CRC CT DAC DC DTMF ECO EEPROM GPIO ICE IDE ILO IMO I/O IrDA ISSP LCD LED LPC LVD MAC MCU Description alternating current analog-to-digital converter application programming interface complementary metal oxide semiconductor central processing unit cyclic redundancy check continuous time digital-to-analog converter direct current dual-tone multi-frequency external crystal oscillator electrically erasable programmable read-only memory general purpose I/O in-circuit emulator integrated development environment internal low speed oscillator internal main oscillator input/output infrared data association in-system serial programming liquid crystal display light-emitting diode low power comparator low voltage detect multiply-accumulate microcontroller unit Acronym MIPS OCD PCB PDIP PGA PLL POR PPOR PRS PSoC® PWM QFN RTC SAR SC SLIMO SMP SOIC SPITM SRAM SROM SSOP UART USB WDT XRES on-chip debug printed circuit board plastic dual-in-line package programmable gain amplifier phase-locked loop power on reset precision power on reset pseudo-random sequence Programmable System-on-Chip pulse width modulator quad flat no leads real time clock successive approximation switched capacitor slow IMO switch-mode pump small-outline integrated circuit serial peripheral interface static random access memory supervisory read only memory shrink small-outline package universal asynchronous receiver / transmitter universal serial bus watchdog timer external reset Description million instructions per second Reference Documents CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34B, CY8C21x23, CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip Technical Reference Manual (TRM) (001-14463) Design Aids – Reading and Writing PSoC® Flash - AN2015 (001-40459) Adjusting PSoC® Trims for 3.3 V and 2.7 V Operation – AN2012 (001-17397) Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 (001-14503) Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com. Document Number: 001-67345 Rev. *A Page 41 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Document Conventions Units of Measure Table 38 lists the units of measures. Table 38. Units of Measure Symbol kB dB °C µF fF pF kHz MHz rt-Hz kΩ Ω Unit of Measure 1024 bytes decibels degree Celsius microfarad femto farad picofarad kilohertz megahertz root hertz kilohm ohm microampere milliampere nanoampere pikoampere millihenry Symbol µH µs ms ns ps µV mV mVpp nV V µW W mm ppm % microhenry Unit of Measure microsecond millisecond nanosecond picosecond microvolts millivolts millivolts peak-to-peak nanovolts volts microwatts watt millimeter parts per million percent µA mA nA pA mH Numeric Conventions Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals. Glossary active high 1. A logic signal having its asserted state as the logic 1 state. 2. A logic signal having the logic 1 state as the higher voltage of the two states. The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more. A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation. A series of software routines that comprise an interface between a computer application and lower level services and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create software applications. A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. A stable voltage reference design that matches the positive temperature coefficient of VT with the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference. analog blocks analog-to-digital (ADC) Application programming interface (API) asynchronous bandgap reference Document Number: 001-67345 Rev. *A Page 42 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Glossary (continued) bandwidth 1. The frequency range of a message or information processing system measured in hertz. 2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. 1. A systematic deviation of a value from a reference value. 2. The amount by which the average of a set of values departs from a reference value. 3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. 1. A functional unit that performs a single function, such as an oscillator. 2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or an analog PSoC block. 1. A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which data is written. 2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. An amplifier used to lower the output impedance of a system. 1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0]. 3. One or more conductors that serve as a common connection for a group of related devices. The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks. An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. A program that translates a high level language, such as C, into machine language. In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’. An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. bias block buffer bus clock comparator compiler configuration space crystal oscillator cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear check (CRC) feedback shift register. Similar calculations may be used for a variety of other purposes such as data compression. data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions. A hardware and software system that allows you to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. A period of time when neither of two or more signals are in their active state or in transition. debugger dead band Document Number: 001-67345 Rev. *A Page 43 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Glossary (continued) digital blocks The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator, pseudo-random number generator, or SPI. A device that changes a digital signal to an analog signal of corresponding magnitude. The analogto-digital (ADC) converter performs the reverse operation. The relationship of a clock period high time to its low time, expressed as a percent. Duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop and return to a pre-defined state. An electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is OFF. The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash space that may be protected. A Flash block holds 64 bytes. The number of cycles or events per unit of time, for a periodic function. The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually expressed in dB. A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5V and pulled high with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (PSoC Designer). digital-to-analog (DAC) duty cycle emulator External Reset (XRES) Flash Flash block frequency gain I2C ICE input/output (I/O) A device that introduces data into or extracts data from a system. interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends with the RETI instruction, returning the device to the point in the program where it left normal program execution. 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on serial data streams. 2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles. interrupt service routine (ISR) jitter low-voltage detect A circuit that senses Vdd and provides an interrupt to the system when Vdd falls below a (LVD) selected threshold. Document Number: 001-67345 Rev. *A Page 44 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Glossary (continued) M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the Flash, SRAM, and register space. A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device. An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor. The reference to a circuit containing both analog and digital techniques and components. A device that imposes a signal on a carrier. 1. A disturbance that affects a signal and that may distort the information carried by the signal. 2. The random variations of one or more characteristics of any entity such as voltage, current, or data. A circuit that may be crystal controlled and is used to generate a clock frequency. A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names. A group of pins, usually eight. A circuit that forces the PSoC device to reset when the voltage is below a pre-set level. This is one type of hardware reset. Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-onChip™ is a trademark of Cypress. master device microcontroller mixed-signal modulator noise oscillator parity Phase-locked loop (PLL) pinouts port Power on reset (POR) PSoC® PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology. pulse width An output in the form of duty cycle which varies as a function of the applied measurement modulator (PWM) RAM An acronym for random access memory. A data-storage device from which data can be read out and new data can be written in. A storage device with a specific capacity, such as a bit or byte. A means of bringing a system back to a know state. See hardware reset and software reset. register reset Document Number: 001-67345 Rev. *A Page 45 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Glossary (continued) ROM An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in. 1. Pertaining to a process in which all events occur one after the other. 2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. The time it takes for an output signal or value to stabilize after the input has changed from one value to another. A memory storage device that sequentially shifts a word either left or right to output a stream of serial data. A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. The controlling device is called the master device. An acronym for static random access memory. A memory device where you can store and retrieve data at a high rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is removed from the device. An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code, operating from Flash. A signal following a character or block that prepares the receiving device to receive the next character or block. 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. A system whose operation is synchronized by a clock signal. A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming Interface) for the peripheral function. The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program. A name for a power net meaning ‘voltage drain’. The most positive power supply signal. Usually 5 V or 3.3 V. A name for a power net meaning ‘voltage source’. The most negative power supply signal. A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time. serial settling time shift register slave device SRAM SROM stop bit synchronous tri-state UART user modules user space VDD VSS watchdog timer Document Number: 001-67345 Rev. *A Page 46 of 47 [+] Feedback CY8C21634B, CY8C21534B, CY8C21434B CY8C21334B, CY8C21234B Document History Page Document Title: CY8C21234B, CY8C21334B, CY8C21434B, CY8C21534B, CY8C21634B PSoC® Programmable System-on-Chip™ Document Number: 001-67345 Revision ** *A ECN 3169205 3247292 Orig. of Change YVA YVA Submission Date 02/16/2011 05/11/2011 New datasheet Updated package diagrams. Post to Web. Description of Change Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. 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Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback