Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY8C23433, CY8C23533
PSoC® Programmable System-on-Chip™
Features
■
■
■
■
■
Powerful Harvard-architecture processor
❐ M8C processor speeds to 24 MHz
❐ 8x8 multiply, 32-bit accumulate
❐ Low power at high speed
❐ 3.0 V to 5.25 V operating voltage
❐ Industrial temperature range: –40 °C to +85 °C
■
Additional system resources
2
❐ I C slave, master, and multi-master to 400 kHz
❐ Watchdog and sleep timers
❐ User-configurable low voltage detection
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
■
Complete development tools
❐ Free development software (PSoC Designer™)
❐ Full-featured in-circuit emulator and programmer
❐ Full speed emulation
❐ Complex breakpoint structure
❐ 128-KB trace memory
Advanced peripherals (PSoC blocks)
❐ Four Rail-to-Rail analog PSoC blocks provide:
• Up to 14-bit ADCs
• Up to 8-bit DACs
• Programmable gain amplifiers
• Programmable filters and comparators
❐ Four digital PSoC blocks provide:
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width
modulators (PWMs)
• CRC and PRS modules
• Full-duplex UART
• Multiple SPI masters or slaves
• Connectable to all GPIO pins
❐ Complex peripherals by combining blocks
❐ High-Speed 8-bit SAR ADC optimized for motor control
Logic Block Diagram
Port 3
Port 2
Port 1
Port 0
Analog
Drivers
PSoC CORE
System Bus
Global Digital Interconnect
SRAM
256 Bytes
Precision, programmable clocking
[1] 24-/48-MHz oscillator
❐ Internal ±5%
❐ High-accuracy 24 MHz with optional 32-KHz crystal and PLL
❐ Optional external oscillator, up to 24 MHz
❐ Internal oscillator for watchdog and sleep
SROM
Global Analog Interconnect
Flash 8K
CPUCore (M8C)
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
Flexible on-chip memory
❐ 8 KB flash program storage 50,000 erase/write cycles
❐ 256 bytes SRAM data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ EEPROM emulation in flash
DIGITAL SYSTEM
Digital
Block
Array
Analog
Block Array
2 Columns
4 Blocks
1 Row
4 Blocks
Programmable pin configurations
❐ 25-mA Sink, 10-mA source on all GPIO
❐ Pull-up, pull-down, high Z, strong, or open drain drive modes
on all GPIO
❐ Up to eight analog inputs on GPIO plus two additional analog
inputs with restricted routing
❐ Two 30-mA analog outputs on GPIO
❐ Configurable interrupt on all GPIOs
Digital
Clocks
Multiply
Accum.
ANALOG SYSTEM
SAR8 ADC
Decimator
I2C
Analog
Ref
Analog
Input
Muxing
POR and LVD
System Resets
Internal
Voltage
Ref.
SYSTEM RESOURCES
Note
1. Errata: When the device is operated within 0 °C to 70 °C, the frequency tolerance is reduced to ±2.5%, but if operated at extreme temperature (below 0 °C or above
70 °C), frequency tolerance deviates from ±2.5% to ±5%. For more information, see Errata on page 50.
Cypress Semiconductor Corporation
Document Number: 001-44369 Rev. *I
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 29, 2015
CY8C23433, CY8C23533
Contents
PSoC Functional Overview .............................................. 3
PSoC Core .................................................................. 3
Digital System ................................................................... 3
Analog System .................................................................. 4
Additional System Resources ..................................... 5
PSoC Device Characteristics ...................................... 5
Getting Started .................................................................. 6
Application Notes ........................................................ 6
Development Kits ........................................................ 6
Training ....................................................................... 6
CYPros Consultants .................................................... 6
Solutions Library .......................................................... 6
Technical Support ....................................................... 6
Development Tools .......................................................... 7
PSoC Designer Software Subsystems ........................ 7
Designing with PSoC Designer ....................................... 8
Select User Modules ................................................... 8
Configure User Modules .............................................. 8
Organize and Connect ................................................ 8
Generate, Verify, and Debug ....................................... 8
Pinouts .............................................................................. 9
32-Pin Part Pinout ....................................................... 9
28-Pin Part Pinout .................................................... 10
Register Reference ......................................................... 11
Register Conventions ................................................ 11
Register Mapping Tables .......................................... 11
Electrical Specifications ................................................ 14
Absolute Maximum Ratings ....................................... 15
Document Number: 001-44369 Rev. *I
Operating Temperature ............................................ 15
DC Electrical Characteristics ..................................... 16
AC Electrical Characteristics ..................................... 30
Packaging Information ................................................... 40
Thermal Impedances ................................................ 41
Capacitance on Crystal Pins .................................... 41
Solder Reflow Peak Temperature ............................. 41
Ordering Information ...................................................... 42
Acronyms ........................................................................ 43
Acronyms Used ......................................................... 43
Reference Documents .................................................... 43
Document Conventions ................................................. 44
Units of Measure ....................................................... 44
Numeric Conventions .................................................... 44
Glossary .......................................................................... 45
Errata ............................................................................... 50
Part Numbers Affected .............................................. 50
CY8C23433 Qualification Status ............................... 50
CY8C23433 Errata Summary .................................... 50
Document History Page ................................................. 51
Sales, Solutions, and Legal Information ...................... 53
Worldwide Sales and Design Support ....................... 53
Products .................................................................... 53
PSoC® Solutions ...................................................... 53
Cypress Developer Community ................................. 53
Technical Support ..................................................... 53
Page 2 of 53
CY8C23433, CY8C23533
PSoC Functional Overview
Digital System
The PSoC family consists of many programmable
system-on-chips with on-chip controller devices. These devices
are designed to replace multiple traditional MCU-based system
components with a low-cost single-chip programmable device.
PSoC devices include configurable blocks of analog and digital
logic, and programmable interconnects. This architecture make
it possible for you to create customized peripheral configurations
that match the requirements of each individual application.
additionally, a fast central processing unit (CPU), flash memory,
SRAM data memory, and configurable I/O are included in a
range of convenient pinouts and packages.
The Digital system consists of 4 digital PSoC blocks. Each block
is an 8-bit resource that is used alone or combined with other
blocks to form 8, 16, 24, and 32-bit peripherals, which are called
user module references.
Figure 1. Digital System Block Diagram
Port 3
8
Row 0
Row Input
Configuration
8
DBB00
DBB01
DCB02
4
DCB03
4
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
8
Row Output
Configuration
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.
ToAnalog
System
DIGITAL SYSTEM
The PSoC core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
general Purpose I/O (GPIO)
The PSoC device incorporates flexible internal clock generators,
including a 24 MHz internal main oscillator (IMO) accurate to
±5% [2] over temperature and voltage. The 24 MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low power
32 kHz internal low speed oscillator (ILO) is provided for the
sleep timer and WDT. If crystal accuracy is desired, the ECO
(32.768 kHz external crystal oscillator) is available for use as a
real time clock (RTC) and can optionally generate a
crystal-accurate 24 MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a system
resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
Port 0
Digital PSoC Block Array
PSoC Core
Memory encompasses 8 KB of flash for program storage, 256
bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the flash. Program flash uses four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
Port 1
To System Bus
Digital Clocks
FromCore
The PSoC architecture, as shown in the Logic Block Diagram on
page 1, consists of four main areas: PSoC core, digital system,
analog system, and system resources. Configurable global
busing allows combining all of the device resources into a
complete custom system. The PSoC CY8C23x33 family can
have up to three I/O ports that connect to the global digital and
analog interconnects, providing access to four digital blocks and
four analog blocks.
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four million instructions per second MIPS
8-bit Harvard-architecture microprocessor. The CPU uses an
interrupt controller with 11 vectors, to simplify programming of
real time embedded events. program execution is timed and
protected using the included sleep and watch dog timers (WDT).
Port 2
8
GOE[7:0]
GOO[7:0]
Digital peripheral configurations are:
■
PWMs (8-and 16-bit)
■
PWMs with Dead band (8- and 16-bit)
■
Counters (8- to 32- bit)
■
Timers (8- to 32- bit)
■
UART 8 bit with selectable parity (up to 1)
■
Serial peripheral interface (SPI) master and slave (up to 1)
■
I2C slave and multi master (1 available as a system resource)
■
Cyclical redundancy checker (CRC)/Generator (8 to 32 bit)
■
IrDA (up to 1)
■
Pseudo Random Sequence Generators (8- to 32- bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in the table titled PSoC Device Characteristics on page 5.
Note
2. Errata: When the device is operated within 0 °C to 70 °C, the frequency tolerance is reduced to ±2.5%, but if operated at extreme temperature (below 0 °C or above
70 °C), frequency tolerance deviates from ±2.5% to ±5%. For more information, see Errata on page 50.
Document Number: 001-44369 Rev. *I
Page 3 of 53
CY8C23433, CY8C23533
The analog system consists of an 8-bit SAR ADC and four
configurable blocks. The programmable 8-bit SAR ADC is an
optimized ADC that runs up to 300 Ksps, with monotonic
guarantee. It also has the features to support a motor control
application.
Each analog block consists of an opamp circuit allowing the
creation of complex analog signal flows. Analog peripherals are
very flexible and can be customized to support specific
application requirements. Some of the more common PSoC
analog functions (most available as user modules) are:
Figure 2. Analog System Block Diagram
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
AGNDIn RefIn
Analog System
P2[3]
P2[6]
P2[4]
P2[1]
P2[2]
■
Filters (2 band pass, low-pass)
■
Amplifiers (up to 2, with selectable gain to 48x)
■
Instrumentation amplifiers (1 with selectable gain to 93x)
■
Comparators (1, with 16 selectable thresholds)
■
DAC (6 or 9-bit DAC)
■
Multiplying DAC (6 or 9-bit DAC)
■
High current output drivers (two with 30 mA drive)
■
1.3-V reference (as a system resource)
■
DTMF dialer
■
Modulators
■
Correlators
ASD11
■
Peak detectors
ASC21
■
Many other topologies possible
P2[0]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
Block Array
ACB00
Analog blocks are arranged in a column of three, which includes
one continuous time (CT) and two switched capacitor (SC)
blocks. The Analog column 0 contains the SAR8 ADC block
rather than the standard SC blocks.
ACB01
P0[7:0]
ACI2[3:0]
8-Bit SAR ADC
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-44369 Rev. *I
Page 4 of 53
CY8C23433, CY8C23533
Additional System Resources
■
System resources, some of which are listed in the previous
sections, provide additional capability useful to complete
systems. Additional resources include a multiplier, decimator,
low voltage detection, and power-on-reset. Brief statements
describing the merits of each system resource follow:
■
■
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks may be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■
A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math and
digital filters.
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of delta
sigma ADCs.
The I2C module provides 100- and 400-kHz communication
over two wires. Slave, master, and multi-master modes are all
supported.
■
Low-Voltage detection interrupts can signal the application of
falling voltage levels, while the advanced POR circuit
eliminates the need for a system supervisor.
■
An internal 1.3-V reference provides an absolute reference for
the analog system, including ADCs and DACs.
PSoC Device Characteristics
Depending on the PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3
analog blocks. Table 1 lists the resources available for specific PSoC device groups.
Table 1. PSoC Device Characteristics
PSoC Part
Number
Digital
I/O
CY8C29x66
up to 64
CY8C28xxx
up to 44
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
4
16
up to 12
4
up to 3
up to 12
up to 44
up to 4
Analog
Columns
Analog
Blocks
SRAM
Size
Flash
Size
SAR
ADC
4
12
2K
32 K
No
up to 6
up to
12 + 4[3]
1K
16 K
Yes
CY8C27x43
up to 44
2
8
up to 12
4
4
12
256
16 K
No
CY8C24x94
up to 56
1
4
up to 48
2
2
6
1K
16 K
No
CY8C24x23A
up to 24
1
4
up to 12
2
2
6
256
4K
No
CY8C23x33
up to 26
1
4
up to 12
2
2
4
256
8K
Yes
CY8C24x33
up to 26
1
4
up to 12
2
2
4
256
8K
Yes
[3]
CY8C22x45
up to 38
2
8
up to 38
0
4
6
1K
16 K
No
CY8C21x45
up to 24
1
4
up to 24
0
4
6[3]
512
8K
Yes
CY8C21x34
up to 28
1
4
up to 28
0
2
4[3]
512
8K
No
CY8C21x23
up to 16
1
4
up to 8
0
2
4[3]
256
4K
No
CY8C20x34
up to 28
0
0
up to 28
0
0
3[3,4]
512
8K
No
0
3[3,4]
up to
2K
up to
32 K
No
CY8C20xx6
up to 36
0
0
up to 36
0
Notes
3. Limited analog functionality.
4. Two analog blocks and one CapSense®.
Document Number: 001-44369 Rev. *I
Page 5 of 53
CY8C23433, CY8C23533
Getting Started
The quickest way to understand PSoC silicon is to read this data
sheet and then use the PSoC Designer integrated development
environment (IDE). This data sheet is an overview of the PSoC
integrated circuit and presents specific pin, register, and
electrical specifications.
For in-depth information, along with detailed programming
details, see the PSoC® Technical Reference Manual.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device data sheets on the web
at http://www.cypress.com.
Application Notes
Cypress application notes are an excellent introduction to the
wide variety of possible PSoC designs and can be found at
http://www.cypress.com
Development Kits
PSoC Development Kits are available online from cypress at
http://www.cypress.com and through a growing number of
regional and global distributors, which include Arrow, Avnet,
Digi-Key, Farnell, Future Electronics, and Newark.
Document Number: 001-44369 Rev. *I
Training
Free PSoC technical training (on demand, webinars, and
workshops), which is available online at http://
www.cypress.com, covers a wide variety of topics and skill levels
to assist you in your designs.
CYPros Consultants
Certified PSoC consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC
consultant go to http://www.cypress.com and look for CYPros.
Solutions Library
Visit our growing library of solution-focused designs. Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
Technical Support
For assistance with technical issues, search KnowledgeBase
articles and forums at http://www.cypress.com. If you cannot
find an answer to your question, call technical support at
1-800-541-4736.
Page 6 of 53
CY8C23433, CY8C23533
Development Tools
PSoC Designer™ is the revolutionary integrated design
environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
■
Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■
Extensive user module catalog
■
Integrated source-code editor (C and assembly)
■
Free C compiler with no size restrictions or time limits
■
Built-in debugger
■
In-circuit emulation
Built-in support for communication interfaces:
2
❐ Hardware and software I C slaves and masters
❐ Full-speed USB 2.0
❐ Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
■
PSoC Designer Software Subsystems
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), amplifiers, and filters.
Configure the user modules for your chosen application and
connect them to each other and to the proper pins. Then
generate your project. This prepopulates your project with APIs
and libraries that you can use to program your application.
The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration
makes it possible to change configurations at run time. In
essence, this lets you to use more than 100 percent of PSoC's
resources for an application.
Document Number: 001-44369 Rev. *I
Code Generation Tools
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and are
linked with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices.
The optimizing C compilers provide all of the features of C,
tailored to the PSoC architecture. They come complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, and read and write I/O
registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
Online Help System
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an online support forum
to aid the designer in getting started.
In-Circuit Emulator
A low cost, high functionality ICE is available for development
support. This hardware can program single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24-MHz) operation.
Page 7 of 53
CY8C23433, CY8C23533
Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed-function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and lowering inventory costs. These
configurable resources, called PSoC blocks, have the ability to
implement a wide variety of user-selectable functions. The PSoC
development process is:
1. Select user modules.
2. Configure user modules.
3. Organize and connect.
4. Generate, verify, and debug.
Select User Modules
PSoC Designer provides a library of prebuilt, pretested hardware
peripheral components called “user modules.” User modules
make selecting and implementing peripheral devices, both
analog and digital, simple.
Configure User Modules
Each user module that you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a PWM
User Module configures one or more digital PSoC blocks, one
for each eight bits of resolution. Using these parameters, you can
establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application.
Enter values directly or by selecting values from drop-down
menus. All of the user modules are documented in datasheets
that may be viewed directly in PSoC Designer or on the Cypress
website. These user module datasheets explain the internal
operation of the user module and provide performance specifications. Each datasheet describes the use of each user module
parameter, and other information that you may need to successfully implement your design.
Document Number: 001-44369 Rev. *I
Organize and Connect
Build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. Perform the selection,
configuration, and routing so that you have complete control over
all on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides APIs with high-level functions to control
and respond to hardware events at run time, and interrupt
service routines that you can adapt as needed.
A complete code development environment lets you to develop
and customize your applications in C, assembly language, or
both.
The last step in the development process takes place inside
PSoC Designer's Debugger (accessed by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full-speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition
to traditional single-step, run-to-breakpoint, and watch-variable
features, the debug interface provides a large trace buffer. It lets
you to define complex breakpoint events that include monitoring
address and data bus values, memory locations, and external
signals.
Page 8 of 53
CY8C23433, CY8C23533
Pinouts
The CY8C23X33 PSoC is available in 32-pin QFN and 28-pin SSOP packages. Every port pin (labeled with a “P”), except for Vss and
Vdd in the following table and figure, is capable of Digital I/O.
32-Pin Part Pinout
Table 2. Pin Definitions - 32-Pin (QFN)
I/O
2
I/O
3
I/O
I
4
I/O
I
5
I/O
AVref
6
P2[7]
GPIO
P2[5]
GPIO
P2[3]
Direct switched capacitor block input
P2[1]
Direct switched capacitor block input
P3[0][4] GPIO/ADC Vref (optional)
NC
No connection
7
I/O
P1[7]
I2C serial clock (SCL)
8
I/O
P1[5]
I2C serial data (SDA)
9
NC
No connection
10
I/O
P1[3]
GPIO
11
I/O
P1[1]
GPIO, crystal Input (XTAL in), I2C serial clock
(SCL), ISSP-SCLK*
12
Power
Vss
Ground connection
13
I/O
P1[0]
GPIO, crystal output (XTAL out), I2C serial data
(SDA), ISSP-SDATA*
14
I/O
P1[2]
GPIO
15
I/O
P1[4]
GPIO, external clock IP
I/O
P1[6]
16
17
NC
18
Input
GPIO, P2[7]
GPIO, P2[5]
A, I, P2[3]
A, I, P2[1]
AVref, P3[0]
NC
I2C SCL, P1[7]
I2C SDA, P1[5]
1
2
3
4
5
6
7
8
QFN
(Top View)
24
23
22
21
20
19
18
17
P0[2], A, I
P0[0], A, I
P2[6], Vref
P2[4], AGnd
P2[2], A, I
P2[0], A, I
XRES
P1[6], GPIO
No connection
GPIO
XRES Active high external reset with internal pull down
19
I/O
I
20
I/O
I
21
I/O
22
I/O
23
I/O
I
24
I/O
I
25
P2[0]
Direct switched capacitor block input
P2[2]
Direct switched capacitor block input
P2[4]
External analog ground (AGnd)
P2[6]
External voltage reference (VRef)
P0[0]
Analog column mux input and ADC input
P0[2]
Analog column mux input and ADC input
NC
No connection
26
I/O
I
P0[4]
Analog column mux input and ADC input
27
I/O
I
P0[6]
Analog column mux input and ADC input
28
Figure 3. CY8C23533 32-Pin PSoC Device
P0[1], A, I
P0[3], A, IO
P0[5], A, IO
P0[7], A, I
Vdd
P0[6], A, I
P0[4], A, I
NC
1
Description
32
31
30
29
28
27
26
25
Pin
Digital Analog Name
9
10
11
12
13
14
15
16
Type
NC
GPIO P1[3]
I2C SCL, XTALin, P1[1]
Vss
I2C SDA, XTALout, P1[0]
GPIO P1[2]
GPIO, EXTCLK, P1[4]
NC
Pin
No.
VDD
Supply voltage
29
I/O
Power
I
P0[7]
Analog column mux input and ADC input
30
I/O
I/O
P0[5]
Analog column mux input, column output and ADC
input
31
I/O
I/O
P0[3]
Analog column mux input, column output and ADC
input
32
I/O
I
P0[1]
Analog column mux input.and ADC input
LEGEND: A = Analog, I = Input, and O = Output.
Note
4. Even though P3[0] is an odd port, it resides on the left side of the pinout.
Document Number: 001-44369 Rev. *I
Page 9 of 53
CY8C23433, CY8C23533
28-Pin Part Pinout
Table 3. Pin Definitions - 28-Pin (SSOP)
Figure 4. CY8C23433 28-Pin PSoC Device
Type
Pin
No.
Digital
Analog
1
I/O
I
P0[7]
Analog column mux IP and ADC IP
2
I/O
I/O
P0[5]
Analog column mux IP and column O/P
and ADC IP
Pin
Name
Description
3
I/O
I/O
P0[3]
Analog column mux IP and column O/P
and ADC IP
4
I/O
I
P0[1]
Analog column mux IP and ADC IP
5
I/O
P2[7]
GPIO
6
I/O
P2[5]
GPIO
7
I/O
I
P2[3]
Direct switched capacitor input
8
I/O
I
P2[1]
Direct switched capacitor input
9
I/O
AVref
P3[0][5]
GPIO/ADC Vref (optional)
10
I/O
P1[7]
I2C SCL
11
I/O
P1[5]
I2C SDA
12
I/O
P1[3]
13
I/O
P1[1]
14
Power
Vss
15
I/O
P1[0]
16
I/O
P1[2]
17
I/O
P1[4]
GPIO, External clock IP
18
I/O
P1[6]
GPIO
19
I/O
P3[1][7]
GPIO
20
I/O
I
P2[0]
Direct switched capacitor input
21
I/O
I
22
I/O
23
I/O
24
I/O
I
25
I/O
26
I/O
27
I/O
28
Power
AIO, P0[7]
1
28
Vdd
IO, P0[5]
2
27
P0[6], AIO, AnColMux and ADC IP
IO, P0[3]
3
26
P0[4], AIO, AnColMux and ADC IP
AIO, P0[1]
4
25
P0[2], AIO, AnColMux and ADC IP
IO, P2[7]
5
24
P0[0], AIO, AnColMux and ADC IP
IO, P2[5]
6
23
P2[6], VREF
AIO, P2[3]
7
22
P2[4], AGND
AIO, P2[1]
8
21
P2[2], AIO
AVref, IO, P3[0]
9
20
P2[0], AIO
I2C SCL, IO, P1[7]
10
19
P3[1], IO
I2C SDA, IO, P1[5]
11
18
P1[6], IO
IO, P1[3]
12
17
P1[4], IO, EXTCLK
I2C SCL,ISSP SCL,XTALin,IO, P1[1]
13
16
P1[2], IO
Vss
14
15
P1[0],IO,XTALout,ISSP SDA,I2C SDA
SSOP
GPIO
[6]
GPIO, Xtal input, I2C SCL, ISSP SCL
Ground Pin
[6]
GPIO, Xtal output, I2C SDA, ISSP SDA
GPIO
P2[2]
Direct switched capacitor input
P2[4]
External analog ground (AGnd)
P2[6]
Analog voltage reference (VRef)
P0[0]
Analog column mux IP and ADC IP
I
P0[2]
Analog column mux IP and ADC IP
I
P0[4]
Analog column mux IP and ADC IP
I
P0[6]
Analog column mux IP and ADC IP
Vdd
Supply Voltage
LEGEND: A = Analog, I = Input, and O = Output.
Notes
5. Even though P3[0] is an odd port, it resides on the left side of the pinout.
6. ISSP pin, which is not High Z at POR.
7. Even though P3[1] is an even port, it resides on the right side of the pinout.
Document Number: 001-44369 Rev. *I
Page 10 of 53
CY8C23433, CY8C23533
Register Reference
Register Mapping Tables
This section lists the registers of the CY8C23433 PSoC device
by using mapping tables, in offset order.
Register Conventions
The register conventions specific to this section are listed in
Table 4.
The PSoC device has a total register address space of 512
bytes. The register space is referred to as I/O space and is
divided into two banks Bank 0 and Bank 1. The XIO bit in the Flag
register (CPU_F) determines which bank the user is currently in.
When the XIO bit is set to 1 the user is in Bank 1.
Note In the following register mapping tables, blank fields are
reserved and must not be accessed.
Table 4. Register Conventions
Convention
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Document Number: 001-44369 Rev. *I
Page 11 of 53
CY8C23433, CY8C23533
Table 5. Register Map Bank 0 Table: User Space
Name
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
DCB03DR2
DCB03CR0
Addr (0,Hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
Gray fields are reserved.
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
Name
AMX_IN
ARF_CR
CMP_CR0
ASY_CR
CMP_CR1
SARADC_DL
SARADC_CR0
SARADC_CR1
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1 *
ACB01CR2 *
Addr (0,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
Name
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
RW
RW
#
#
RW
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
Addr (0,Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
Access
Name
RW
RW
RW
RW
RW
RW
RW
RW
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR3
INT_MSK3
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL0_X
MUL0_Y
MUL0_DH
MUL0_DL
ACC0_DR1
ACC0_DR0
ACC0_DR3
ACC0_DR2
RW
RW
RW
RW
RW
RW
RW
CPU_F
CPU_SCR1
CPU_SCR0
Addr (0,Hex) Access
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
RW
D7
#
D8
RW
D9
#
DA
RW
DB
RW
DC
DD
RW
DE
RW
DF
E0
RW
E1
RW
E2
RC
E3
W
E4
RC
E5
RC
E6
RW
E7
RW
E8
W
E9
W
EA
R
EB
R
EC
RW
ED
RW
EE
RW
EF
RW
F0
F1
F2
F3
F4
F5
F6
F7
RL
F8
F9
FA
FB
FC
FD
FE
#
FF
#
# Access is bit specific.
Document Number: 001-44369 Rev. *I
Page 12 of 53
CY8C23433, CY8C23533
Table 6. Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
DBB00FN
DBB00IN
DBB00OU
DBB01FN
DBB01IN
DBB01OU
DCB02FN
DCB02IN
DCB02OU
DCB03FN
DCB03IN
DCB03OU
Addr (1,Hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
Gray fields are reserved.
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
CLK_CR0
CLK_CR1
ABF_CR0
AMD_CR0
AMD_CR1
ALT_CR0
RW
RW
RW
RW
RW
RW
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2 *
Addr (1,Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
Name
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
SARADC_TRS
SARADC_TRCL
SARADC_TRCH
SARADC_CR2
SARADC_LCR
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
Addr (1,Hex) Access
Name
Addr (1,Hex) Access
80
C0
81
C1
82
C2
83
C3
84
RW
C4
85
RW
C5
86
RW
C6
87
RW
C7
88
C8
89
C9
8A
CA
8B
CB
8C
CC
8D
CD
8E
CE
8F
CF
90
GDI_O_IN
D0
RW
91
GDI_E_IN
D1
RW
92
GDI_O_OU
D2
RW
93
GDI_E_OU
D3
RW
94
RW
D4
95
RW
D5
96
RW
D6
97
RW
D7
98
D8
99
D9
9A
DA
9B
DB
9C
DC
9D
OSC_GO_EN
DD
RW
9E
OSC_CR4
DE
RW
9F
OSC_CR3
DF
RW
A0
OSC_CR0
E0
RW
A1
OSC_CR1
E1
RW
A2
OSC_CR2
E2
RW
A3
VLT_CR
E3
RW
A4
VLT_CMP
E4
R
A5
E5
A6
E6
A7
E7
A8
RW
IMO_TR
E8
W
A9
RW
ILO_TR
E9
W
AA
RW
BDG_TR
EA
RW
AB
#
ECO_TR
EB
W
AC
RW
EC
AD
ED
AE
EE
AF
EF
B0
RW
F0
B1
RW
F1
B2
RW
F2
B3
RW
F3
B4
RW
F4
B5
RW
F5
B6
RW
F6
B7
CPU_F
F7
RL
B8
F8
B9
F9
BA
FLS_PR1
FA
RW
BB
FB
BC
FC
BD
FD
BE
CPU_SCR1
FE
#
BF
CPU_SCR0
FF
#
# Access is bit specific.
Document Number: 001-44369 Rev. *I
Page 13 of 53
CY8C23433, CY8C23533
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C23433 PSoC device. For up-to-date latest electrical specifications, visit http://www.cypress.com.
Specifications are valid for –40°C TA 85°C and TJ 100°C, except where noted.
Refer to Table 23 on page 30 for the electrical specifications for the IMO using SLIMO mode.
Figure 5. Voltage versus CPU Frequency
Figure 8. IMO Frequency Trim Options
5.25
4.75
Vdd Voltage
Vdd Voltage
lid g
Va ratin n
pe io
O Reg
4.75
SLIMO Mode = 0
5.25
3.60
3.00
3.00
93 kHz
3 MHz
CPU Frequency
Document Number: 001-44369 Rev. *I
12 MHz
24 MHz
93 kHz
SLIMO
Mode=1
SLIMO
Mode=0
SLIMO
Mode=1
SLIMO
Mode=0
6 MHz
12 MHz
24 MHz
IMO Frequency
Page 14 of 53
CY8C23433, CY8C23533
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 7. Absolute Maximum Ratings
Symbol
TSTG
Description
Storage temperature
TBAKETEMP Bake temperature
TBAKETIME Bake time
Min
Typ
Max
Units
Notes
–55
25
+100
°C
Higher storage temperatures
reduce data retention time.
Recommended storage
temperature is +25°C ± 25°C.
Extended duration storage
temperatures above 65°C
degrade reliability.
–
125
See
package
label
See
package
label
–
72
Hour
s
–40
–
+85
°C
o
C
TA
Ambient temperature with power applied
Vdd
Supply voltage on VDD relative to VSS
–0.5
–
+6.0
V
VIO
DC input voltage
VSS – 0.5
–
VDD + 0.5
V
VIOZ
DC voltage applied to tri-state
VSS – 0.5
–
VDD + 0.5
V
IMIO
Maximum current into any port pin
–25
–
+50
mA
ESD
Electrostatic discharge voltage
2000
–
–
V
LU
Latch-up current
–
–
200
mA
Human Body Model ESD.
Operating Temperature
Table 8. Operating Temperature
Min
Typ
Max
Units
TA
Symbol
Ambient temperature
Description
–40
–
+85
°C
TJ
Junction temperature
–40
–
+100
°C
Document Number: 001-44369 Rev. *I
Notes
The temperature rise from
ambient to junction is package
specific. See Table 37 on page
41. You must limit the power
consumption to comply with this
requirement.
Page 15 of 53
CY8C23433, CY8C23533
DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and –40°C TA 85°C or 3.0 V to 3.6 V and –40°C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C
and are for design guidance only.
Table 9. DC Chip-Level Specifications
Symbol
Description
VDD
Supply voltage
IDD
Supply current
Min
3.0
–
Typ
–
5
Max
5.25
8
IDD3
Supply current
–
3.3
6.0
ISB
Sleep (mode) current with POR, LVD, Sleep
Timer, and WDT.[8]
–
3
6.5
ISBH
Sleep (mode) current with POR, LVD, sleep
timer, and WDT at high temperature.[8]
–
4
25
ISBXTL
Sleep (mode) current with POR, LVD, sleep
timer, WDT, and external crystal.[8]
–
4
7.5
ISBXTLH
Sleep (mode) current with POR, LVD, sleep
timer, WDT, and external crystal at high
temperature.[8]
–
5
26
VREF
Reference voltage (Bandgap)
1.28
1.30
1.32
Units
Notes
V
See Table 19 on page 27.
mA Conditions are VDD = 5.0V,
TA = 25°C, CPU = 3 MHz, SYSCLK
doubler disabled,
VC1 = 1.5 MHz, VC2 = 93.75 kHz,
VC3 = 93.75 kHz,
analog power = off.
SLIMO mode = 0. IMO = 24 MHz.
mA Conditions are VDD = 3.3V,
TA = 25°C, CPU = 3 MHz, SYSCLK
doubler disabled,
VC1 = 1.5 MHz, VC2 = 93.75 kHz,
VC3 = 93.75 kHz, analog power =
off. SLIMO mode = 0.
IMO = 24 MHz.
A Conditions are with internal slow
speed oscillator, VDD = 3.3V,
–40°C TA 55°C,
analog power = off.
A Conditions are with internal slow
speed oscillator, Vdd = 3.3V, 55°C
< TA 85°C, analog power = off.
A Conditions are with properly
loaded, 1 W max, 32.768 kHz
crystal. VDD = 3.3V, –40°C TA
55°C, analog power = off.
A Conditions are with properly
loaded, 1W max, 32.768 kHz
crystal. VDD = 3.3 V, 55°C < TA
85°C, analog power = off.
V
Trimmed for appropriate VDD.
VDD > 3.0V
Note
8. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This must be compared with devices that have similar
functions enabled.
Document Number: 001-44369 Rev. *I
Page 16 of 53
CY8C23433, CY8C23533
DC GPIO Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and –40°C TA 85°C, or 3.0 V to 3.6 V and –40°C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3V at 25°C
and are for design guidance only.
Table 10. 5-V and 3.3-V DC GPIO Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
RPU
Pull-up resistor
4
5.6
8
k
RPD
Pull-down resistor
4
5.6
8
k
VOH
High output level
VDD - 1.0
–
–
V
IOH = 10 mA, VDD = 4.75 to 5.25
V (maximum 40 mA on even port
pins (for example, P0[2], P1[4]),
maximum 40 mA on odd port
pins (for example, P0[3], P1[5])).
80 mA maximum combined IOH
budget.
VOL
Low output level
–
–
0.75
V
IOL = 25 mA, VDD = 4.75 to 5.25
V (maximum 100 mA on even
port pins (for example, P0[2],
P1[4]), maximum 100 mA on
odd port pins (for example,
P0[3], P1[5])). 100 mA maximum
combined IOH budget.
IOH
High level source current
10
–
–
mA
VOH = VDD-1.0 V, see the limitations of the total current in the
note for VOH
IOL
Low level sink current
25
–
–
mA
VOL = 0.75 V, see the limitations
of the total current in the note for
VOL
VIL
Input low level
–
–
0.8
V
VDD = 3.0 to 5.25
VIH
Input high level
2.1
–
V
VDD = 3.0 to 5.25
VH
Input hysterisis
–
60
–
mV
IIL
Input leakage (absolute value)
–
1
–
nA
Gross tested to 1 A
CIN
Capacitive load on pins as input
–
3.5
10
pF
Package and pin dependent.
Temp = 25°C
COUT
Capacitive load on pins as output
–
3.5
10
pF
Package and pin dependent.
Temp = 25°C
Document Number: 001-44369 Rev. *I
Page 17 of 53
CY8C23433, CY8C23533
DC Operational Amplifier Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and –40°C TA 85°C, or 3.0 V to 3.6 V and –40°C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C
and are for design guidance only.
The Operational amplifier is a component of both the analog continuous time PSoC blocks and the analog switched cap PSoC blocks.
The guaranteed specifications are measured in the analog continuous time PSoC block. Typical parameters apply to 5 V at 25°C and
are for design guidance only.
Table 11. 5-V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input offset voltage (absolute value)
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
TCVOSOA Average input offset voltage drift
Min
Typ
Max
Units
–
–
–
1.6
1.3
1.2
10
8
7.5
mV
mV
mV
–
7.0
35.0
V/°C
Notes
IEBOA
Input leakage current (Port 0 analog pins)
–
20
–
pA
Gross tested to 1 A
CINOA
Input capacitance (Port 0 analog pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25°C
VCMOA
Common mode voltage range
Common mode voltage range (high power or high
opamp bias)
0.0
0.5
–
–
VDD
VDD – 0.5
V
V
The common-mode input
voltage range is measured
through an analog output
buffer. The specification
includes the limitations
imposed by the characteristics of the analog output
buffer.
GOLOA
Open loop gain
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
60
60
80
–
–
–
–
–
–
dB
–
–
VOHIGHOA High output voltage swing (internal signals)
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
VDD – 0.2
VDD – 0.2
VDD – 0.5
–
–
–
–
–
–
V
V
V
VOLOWOA Low output voltage swing (internal signals)
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
–
–
–
–
–
–
0.2
0.2
0.5
V
V
V
–
–
–
–
–
300
600
1200
2400
4600
400
800
1600
3200
6400
A
A
A
A
A
52
80
–
dB
ISOA
Supply current (including associated AGND buffer)
Power = low, Opamp bias = high
Power = medium, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = low
Power = high, Opamp bias = high
PSRROA Supply voltage rejection ratio
Document Number: 001-44369 Rev. *I
Specification is applicable at
high power. For all other bias
modes (except high power,
high opamp bias), minimum is
60 dB.
Vss VIN (VDD - 2.25) or
(VDD - 1.25V) VIN VDD
Page 18 of 53
CY8C23433, CY8C23533
Table 12. 3.3-V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Min
Input offset voltage (absolute value)
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
TCVOSOA Average input offset voltage drift
Typ
Max
Units
–
–
–
1.65
1.32
–
10
8
–
mV
mV
mV
–
7.0
35.0
µV/°C
Notes
Power = high, Opamp bias = high
setting is not allowed for 3.3 V VDD
operation.
IEBOA
Input leakage current (port 0 analog pins)
–
20
–
pA
Gross tested to 1 A
CINOA
Input capacitance (port 0 analog pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25 °C
VCMOA
Common mode voltage range
0.2
–
VDD – 0.2
V
The common-mode input voltage
range is measured through an
analog output buffer. The
specification includes the
limitations imposed by the
characteristics of the analog
output buffer.
GOLOA
Open loop gain
Power = low, ppamp Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
60
60
80
–
–
–
–
–
–
dB
dB
dB
VOHIGHOA High output voltage swing (internal signals)
Power = low, Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
VDD – 0.2
VDD – 0.2
VDD – 0.2
–
–
–
–
–
–
V
V
V
VOLOWOA Low output voltage swing (internal signals)
Power = low, ppamp Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
ISOA
PSRROA
Supply current (including associated AGND
buffer)
Power = low, Opamp bias = low
Power = low, Opamp bias = high
Power = medium, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = low
Power = high, Opamp bias = high
–
–
–
–
–
–
150
300
600
1200
2400
–
200
400
800
1600
3200
–
mA
mA
mA
mA
mA
mA
Supply voltage rejection ratio
64
80
–
dB
Specification is applicable at low
Opamp bias. For high Opamp bias
mode (except high power, high
Opamp bias), minimum is 60 dB.
Power = high, Opamp bias = high
setting is not allowed for 3.3 V VDD
operation.
Power = high, Opamp bias = high
setting is not allowed for 3.3 V VDD
operation.
Power = high, Opamp bias = high
setting is not allowed for 3.3 V VDD
operation.
VSS £ VIN £ (VDD – 2.25) or
(VDD – 1.25 V) £ VIN £ VDD
DC Low-Power Comparator Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25
°C and are for design guidance only.
Table 13. DC Low-Power Comparator Specifications
Symbol
Description
Min
Typ
Max
Units
0.2
–
VDD – 1.0
V
VREFLPC
Low power comparator (LPC) reference voltage range
ISLPC
LPC supply current
–
10
40
A
VOSLPC
LPC voltage offset
–
2.5
30
mV
Document Number: 001-44369 Rev. *I
Page 19 of 53
CY8C23433, CY8C23533
DC Analog Output buffer specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and –40°C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25
°C and are for design guidance only.
Table 14. 5-V DC Analog Output Buffer Specifications
Symbol
CL
Description
Load capacitance
Min
Typ
Max
Units
Notes
–
–
200
pF
This specification
applies to the
external circuit that
is being driven by
the analog output
buffer.
3
+6
–
12
–
VDD – 1.0
mV
V/°C
V
1
1
–
–
–
–
–
–
V
V
–
–
0.5 x VDD - 1.3
0.5 x VDD - 1.3
V
V
1.1
2.6
64
5.1
8.8
–
mA
mA
dB
VOSOB
TCVOSOB
VCMOB
ROUTOB
Input offset voltage (absolute value)
–
Average input offset voltage drift
–
Common-mode input voltage range
0.5
Output resistance
Power = low
–
Power = high
–
VOHIGHOB High output voltage swing (Load = 32 ohms to VDD/2)
Power = low
0.5 x VDD + 1.1
Power = high
0.5 x VDD + 1.1
VOLOWOB Low output voltage swing (Load = 32 ohms to VDD/2)
Power = low
–
Power = high
–
ISOB
Supply current including bias cell (no load)
Power = low
–
Power = high
–
PSRROB Supply voltage rejection ratio
52
VOUT >(VDD - 1.25)
Table 15. 3.3-V DC Analog Output Buffer Specifications
Min
Typ
Max
Units
Notes
CL
Symbol
Load capacitance
Description
–
–
200
pF
This specification
applies to the
external circuit that
is being driven by
the analog output
buffer.
VOSOB
Input offset voltage (absolute value)
–
3
12
mV
TCVOSOB Average input offset voltage drift
VCMOB
Common-mode input voltage range
ROUTOB
Output resistance
Power = low
Power = high
–
+6
–
V/°C
0.5
–
VDD – 1.0
V
–
–
1
1
–
–
–
–
–
–
V
V
–
–
0.5 x VDD - 1.0
0.5 x VDD - 1.0
V
V
VOHIGHOB High output voltage swing (Load = 1k ohms to VDD/2)
0.5 x VDD + 1.0
Power = low
0.5 x VDD + 1.0
Power = high
VOLOWOB Low output voltage swing (Load = 1k ohms to VDD/2)
Power = low
–
Power = high
–
ISOB
PSRROB
Supply current including bias cell (no load)
Power = low
Power = high
–
0.8
2.0
2.0
4.3
mA
mA
Supply voltage rejection ratio
52
64
–
dB
Document Number: 001-44369 Rev. *I
VOUT > (VDD - 1.25)
Page 20 of 53
CY8C23433, CY8C23533
DC Analog Reference Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and –40°C TA 85°C, or 3.0 V to 3.6 V and –40°C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C
and are for design guidance only.
The guaranteed specifications are measured through the analog continuous time PSoC blocks. The power levels for AGND refer to
the power of the analog continuous time PSoC block. The power levels for RefHi and RefLo refer to the analog reference control
register. The limits stated for AGND include the offset error of the AGND buffer local to the analog continuous time PSoC block.
reference control power is high.
Table 16. 5-V DC Analog Reference Specifications
Reference
ARF_CR
[5:3]
0b000
Reference Power
Settings
Symbol
Reference
RefPower = high
Opamp bias = high
VREFHI
Ref High
VAGND
AGND
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b001
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
Description
Min
Typ
Max
Units
VDD/2 + Bandgap
VDD/2 + 1.136 VDD/2 + 1.288 VDD/2 + 1.409
V
VDD/2
VDD/2 – 0.138 VDD/2 + 0.003 VDD/2 + 0.132
VDD/2 – 1.417 VDD/2 – 1.289 VDD/2 – 1.154
V
VREFLO
Ref Low
VDD/2 – Bandgap
VREFHI
Ref High
VDD/2 + Bandgap
VAGND
AGND
V
V
VDD/2
VDD/2 + 1.202 VDD/2 + 1.290 VDD/2 + 1.358
VDD/2 – 0.055 VDD/2 + 0.001 VDD/2 + 0.055
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.369 VDD/2 – 1.295 VDD/2 – 1.218
V
VREFHI
Ref High
VDD/2 + Bandgap
V
VAGND
AGND
VDD/2
VDD/2 + 1.211 VDD/2 + 1.292 VDD/2 + 1.357
VDD/2 – 0.055
VDD/2
VDD/2 + 0.052
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.368 VDD/2 – 1.298 VDD/2 – 1.224
V
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 + 1.215 VDD/2 + 1.292 VDD/2 + 1.353
VDD/2 – 0.040 VDD/2 – 0.001 VDD/2 + 0.033
V
VDD/2 – 1.368 VDD/2 – 1.299 VDD/2 – 1.225
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.076
0.021
0.041
V
V
VAGND
AGND
VREFLO
Ref Low
VDD/2 – Bandgap
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
VAGND
AGND
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.025
0.011
0.085
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.069
0.014
0.043
V
VAGND
AGND
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.029
0.005
0.052
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.072
0.011
0.048
V
VDD/2
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
V
V
–
–
VAGND
AGND
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.031
0.002
0.057
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.070
0.009
0.047
V
VAGND
AGND
VREFLO
Ref Low
Document Number: 001-44369 Rev. *I
P2[4]
P2[4]
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.033
0.001
0.039
–
–
V
Page 21 of 53
CY8C23433, CY8C23533
Table 16. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
0b010
Reference Power
Settings
Symbol
Reference
RefPower = high
Opamp bias = high
VREFHI
Ref High
VAGND
AGND
RefPower = high
Opamp bias = low
RefPower =
medium
Opamp bias = high
RefPower =
medium
Opamp bias = low
0b011
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower =
medium
Opamp bias = high
RefPower =
medium
Opamp bias = low
Description
VDD
VDD/2
Min
Typ
Max
Units
VDD – 0.121
VDD – 0.003
VDD
V
VDD/2 –
0.040
VDD/2
VDD/2 +
0.034
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.006
VSS + 0.019
V
VREFHI
Ref High
VDD
VDD – 0.083
VDD – 0.002
VDD
V
VAGND
AGND
VDD/2 –
0.040
VDD/2 –
0.001
VDD/2 +
0.033
V
VDD/2
VREFLO
Ref Low
VSS
VSS
VSS + 0.004
VSS + 0.016
V
VREFHI
Ref High
VDD
VDD – 0.075
VDD – 0.002
VDD
V
VAGND
AGND
VDD/2 –
0.040
VDD/2 –
0.001
VDD/2 +
0.032
V
VDD/2
VREFLO
Ref Low
VSS
VSS
VSS + 0.003
VSS + 0.015
V
VREFHI
Ref High
VDD
VDD – 0.074
VDD – 0.002
VDD
V
VAGND
AGND
VDD/2 –
0.040
VDD/2 –
0.001
VDD/2 +
0.032
V
VDD/2
VREFLO
Ref Low
VSS
VREFHI
Ref High
3 × Bandgap
VSS
VSS + 0.002
VSS + 0.014
V
3.753
3.874
3.979
V
VAGND
AGND
2 × Bandgap
2.511
2.590
2.657
V
VREFLO
Ref Low
Bandgap
1.243
1.297
1.333
V
VREFHI
Ref High
3 × Bandgap
3.767
3.881
3.974
V
VAGND
AGND
2 × Bandgap
2.518
2.592
2.652
V
VREFLO
Ref Low
Bandgap
1.241
1.295
1.330
V
VREFHI
Ref High
3 × Bandgap
2.771
3.885
3.979
V
VAGND
AGND
2 × Bandgap
2.521
2.593
2.649
V
VREFLO
Ref Low
Bandgap
1.240
1.295
1.331
V
VREFHI
Ref High
3 × Bandgap
3.771
3.887
3.977
V
VAGND
AGND
2 × Bandgap
2.522
2.594
2.648
V
VREFLO
Ref Low
Bandgap
1.239
1.295
1.332
V
Document Number: 001-44369 Rev. *I
Page 22 of 53
CY8C23433, CY8C23533
Table 16. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
0b100
Reference Power
Settings
Symbol
Reference
RefPower = high
Opamp bias = high
VREFHI
Ref High
VAGND
AGND
VREFLO
Ref Low
2 × Bandgap – P2[6] 2.515 – P2[6] 2.602 – P2[6] 2.654 – P2[6]
(P2[6] = 1.3 V)
V
VREFHI
Ref High
2 × Bandgap + P2[6] 2.498 + P2[6] 2.579 + P2[6] 2.642 + P2[6]
(P2[6] = 1.3 V)
V
RefPower = high
Opamp bias = low
RefPower =
medium
Opamp bias = high
RefPower =
medium
Opamp bias = low
0b101
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower =
medium
Opamp bias = high
RefPower =
medium
Opamp bias = low
Description
Min
Typ
Max
Units
2 × Bandgap + P2[6] 2.481 + P2[6] 2.569 + P2[6] 2.639 + P2[6]
(P2[6] = 1.3 V)
V
2 × Bandgap
V
2 × Bandgap
2.511
VAGND
AGND
Ref Low
2 × Bandgap – P2[6] 2.513 – P2[6] 2.598 – P2[6] 2.650 – P2[6]
(P2[6] = 1.3 V)
V
VREFHI
Ref High
2 × Bandgap + P2[6] 2.504 + P2[6] 2.583 + P2[6] 2.646 + P2[6]
(P2[6] = 1.3 V)
V
VAGND
AGND
2 × Bandgap
V
VREFLO
Ref Low
2 × Bandgap – P2[6] 2.513 – P2[6] 2.596 – P2[6] 2.649 – P2[6]
(P2[6] = 1.3 V)
V
VREFHI
Ref High
2 × Bandgap + P2[6] 2.505 + P2[6] 2.586 + P2[6] 2.648 + P2[6]
(P2[6] = 1.3 V)
V
2.521
2.592
2.650
AGND
Ref Low
2 × Bandgap – P2[6] 2.513 – P2[6] 2.595 – P2[6] 2.648 – P2[6]
(P2[6] = 1.3 V)
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.228 P2[4] + 1.284 P2[4] + 1.332
V
VAGND
AGND
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.358 P2[4] – 1.293 P2[4] – 1.226
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.236 P2[4] + 1.289 P2[4] + 1.332
V
AGND
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.357 P2[4] – 1.297 P2[4] – 1.229
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.237 P2[4] + 1.291 P2[4] + 1.337
V
VAGND
AGND
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.356 P2[4] – 1.299 P2[4] – 1.232
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.237 P2[4] + 1.292 P2[4] + 1.337
V
VAGND
AGND
Ref Low
Document Number: 001-44369 Rev. *I
P2[4]
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
–
VAGND
P2[4]
P2[4]
P2[4]
V
VREFLO
VREFLO
P2[4]
P2[4]
2.648
V
VAGND
P2[4]
2.594
2.652
VREFLO
P2[4]
2.521
2.592
2.658
VREFLO
2 × Bandgap
2.518
2.590
P2[4]
P2[4]
P2[4] – 1.357 P2[4] – 1.300 P2[4] – 1.233
–
–
–
V
Page 23 of 53
CY8C23433, CY8C23533
Table 16. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
0b110
Reference Power
Settings
Symbol
Reference
RefPower = high
Opamp bias = high
VREFHI
Ref High
RefPower = high
Opamp bias = low
RefPower =
medium
Opamp bias = high
RefPower =
medium
Opamp bias = low
0b111
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower =
medium
Opamp bias = high
RefPower =
medium
Opamp bias = low
Description
Min
Typ
Max
Units
2 × Bandgap
2.512
2.594
2.654
V
Bandgap
1.250
1.303
1.346
V
VSS
VSS + 0.011
VSS + 0.027
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
2 × Bandgap
2.515
2.592
2.654
V
VAGND
AGND
Bandgap
1.253
1.301
1.340
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.006
VSS + 0.02
V
VREFHI
Ref High
2 × Bandgap
2.518
2.593
2.651
V
Bandgap
1.254
1.301
1.338
V
VSS
VSS + 0.004
VSS + 0.017
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
2 × Bandgap
2.517
2.594
2.650
V
VAGND
AGND
Bandgap
1.255
1.300
1.337
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.003
VSS + 0.015
V
VREFHI
Ref High
3.2 × Bandgap
4.011
4.143
4.203
V
1.6 × Bandgap
2.020
2.075
2.118
V
VSS
VSS + 0.011
VSS + 0.026
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
3.2 × Bandgap
4.022
4.138
4.203
V
VAGND
AGND
1.6 × Bandgap
2.023
2.075
2.114
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.006
VSS + 0.017
V
VREFHI
Ref High
3.2 × Bandgap
4.026
4.141
4.207
V
1.6 × Bandgap
2.024
2.075
2.114
V
VSS
VSS + 0.004
VSS + 0.015
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
3.2 × Bandgap
4.030
4.143
4.206
V
VAGND
AGND
1.6 × Bandgap
2.024
2.076
2.112
V
VREFLO
Ref Low
VSS
VSS + 0.003
VSS + 0.013
V
Document Number: 001-44369 Rev. *I
VSS
Page 24 of 53
CY8C23433, CY8C23533
Table 17. 3.3-V DC Analog Reference Specifications
Reference
ARF_CR
[5:3]
0b000
Reference Power
Settings
Symbol
Reference
RefPower = high
Opamp bias = high
VREFHI
Ref High
VAGND
AGND
VREFLO
RefPower = high
Opamp bias = low
RefPower =
medium
Opamp bias = high
RefPower =
medium
Opamp bias = low
0b001
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower =
medium
Opamp bias = high
RefPower =
medium
Opamp bias = low
Min
Typ
Max
Units
VDD/2 + Bandgap
VDD/2 +
1.170
VDD/2 +
1.288
VDD/2 +
1.376
V
VDD/2
VDD/2 –
0.098
VDD/2 +
0.003
VDD/2 +
0.097
V
Ref Low
VDD/2 – Bandgap
VDD/2 –
1.386
VDD/2 –
1.287
VDD/2 –
1.169
V
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 +
1.210
VDD/2 +
1.290
VDD/2 +
1.355
V
VAGND
AGND
VDD/2
VDD/2 –
0.055
VDD/2 +
0.001
VDD/2 +
0.054
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 –
1.359
VDD/2 –
1.292
VDD/2 –
1.214
V
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 +
1.198
VDD/2 +
1.292
VDD/2 +
1.368
V
VAGND
AGND
VDD/2
VDD/2 –
0.041
VDD/2
VDD/2 + 0.04
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 –
1.362
VDD/2 –
1.295
VDD/2 –
1.220
V
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 +
1.202
VDD/2 +
1.292
VDD/2 +
1.364
V
VAGND
AGND
VDD/2
VDD/2 –
0.033
VDD/2
VDD/2 +
0.030
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 –
1.364
VDD/2 –
1.297
VDD/2 –
1.222
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] = P2[4] + P2[6] P2[4] + P2[6]
VDD/2, P2[6] = 0.5 V)
– 0.072
– 0.017
P2[4] + P2[6]
+ 0.041
V
VAGND
AGND
P2[4]
–
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] = P2[4] – P2[6] P2[4] – P2[6]
VDD/2, P2[6] = 0.5 V)
– 0.029
+ 0.010
P2[4] – P2[6]
+ 0.048
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] = P2[4] + P2[6] P2[4] + P2[6]
VDD/2, P2[6] = 0.5 V)
– 0.066
– 0.010
P2[4] + P2[6]
+ 0.043
V
VAGND
AGND
P2[4]
–
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] = P2[4] – P2[6] P2[4] – P2[6]
VDD/2, P2[6] = 0.5 V)
– 0.024
+ 0.004
P2[4] – P2[6]
+ 0.034
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] = P2[4] + P2[6] P2[4] + P2[6]
VDD/2, P2[6] = 0.5 V)
– 0.073
– 0.007
P2[4] + P2[6]
+ 0.053
V
VAGND
AGND
P2[4]
–
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] = P2[4] – P2[6] P2[4] – P2[6]
VDD/2, P2[6] = 0.5 V)
– 0.028
+ 0.002
P2[4] – P2[6]
+ 0.033
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] = P2[4] + P2[6] P2[4] + P2[6]
VDD/2, P2[6] = 0.5 V)
– 0.073
– 0.006
P2[4] + P2[6]
+ 0.056
V
VAGND
AGND
P2[4]
–
VREFLO
Ref Low
Document Number: 001-44369 Rev. *I
Description
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]–P2[6] (P2[4] = P2[4] – P2[6] P2[4] – P2[6] P2[4] – P2[6]
VDD/2, P2[6] = 0.5 V)
– 0.030
+ 0.032
V
Page 25 of 53
CY8C23433, CY8C23533
Table 17. 3.3-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
0b010
Reference Power
Settings
Symbol
Reference
RefPower = high
Opamp bias = high
VREFHI
Ref High
VAGND
AGND
VREFLO
Ref Low
VREFHI
Ref High
VAGND
AGND
VREFLO
Ref Low
VREFHI
Ref High
VAGND
AGND
RefPower = high
Opamp bias = low
RefPower =
medium
Opamp bias = high
RefPower =
medium
Opamp bias = low
Description
Min
Typ
Max
Units
VDD – 0.102
VDD – 0.003
VDD
V
VDD/2 –
0.040
VDD/2 +
0.001
VDD/2 +
0.039
V
VSS
VSS
VSS + 0.005
VSS + 0.020
V
VDD
VDD – 0.082
VDD – 0.002
VDD
V
VDD/2 –
0.031
VDD/2
VDD/2 +
0.028
V
VSS
VSS
VSS + 0.003
VSS + 0.015
V
VDD
VDD – 0.083
VDD – 0.002
VDD
V
VDD/2 –
0.032
VDD/2 –
0.001
VDD/2 +
0.029
V
VDD
VDD/2
VDD/2
VDD/2
VREFLO
Ref Low
VSS
VSS
VSS + 0.002
VSS + 0.014
V
VREFHI
Ref High
VDD
VDD – 0.081
VDD – 0.002
VDD
V
VAGND
AGND
VDD/2 –
0.033
VDD/2 –
0.001
VDD/2 +
0.029
V
VDD/2
VREFLO
Ref Low
VSS
VSS + 0.002
VSS + 0.013
V
0b011
All power settings
Not allowed at 3.3
V
–
–
–
–
–
–
–
0b100
All power settings
Not allowed at 3.3
V
–
–
–
–
–
–
–
0b101
RefPower = high
Opamp bias = high
VREFHI
Ref High
RefPower = high
Opamp bias = low
RefPower =
medium
Opamp bias = high
RefPower =
medium
Opamp bias = low
VSS
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.211 P2[4] + 1.285 P2[4] + 1.348
V
VAGND
AGND
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.354 P2[4] – 1.290 P2[4] – 1.197
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.209 P2[4] + 1.289 P2[4] + 1.353
V
P2[4]
P2[4]
P2[4]
P2[4]
–
VAGND
AGND
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.352 P2[4] – 1.294 P2[4] – 1.222
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.218 P2[4] + 1.291 P2[4] + 1.351
V
P2[4]
P2[4]
P2[4]
P2[4]
–
VAGND
AGND
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.351 P2[4] – 1.296 P2[4] – 1.224
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.215 P2[4] + 1.292 P2[4] + 1.354
V
VAGND
AGND
VREFLO
Ref Low
Document Number: 001-44369 Rev. *I
P2[4]
P2[4]
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4] – 1.352 P2[4] – 1.297 P2[4] – 1.227
–
–
V
Page 26 of 53
CY8C23433, CY8C23533
Table 17. 3.3-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
0b110
Reference Power
Settings
Symbol
Reference
RefPower = high
Opamp bias = high
VREFHI
Ref High
RefPower = high
Opamp bias = low
RefPower =
medium
Opamp bias = high
RefPower =
medium
Opamp bias = low
0b111
Description
Min
Typ
Max
Units
2 × Bandgap
2.460
2.594
2.695
V
Bandgap
1.257
1.302
1.335
V
VSS
VSS + 0.01
VSS + 0.029
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
2 × Bandgap
2.462
2.592
2.692
V
VAGND
AGND
Bandgap
1.256
1.301
1.332
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.005
VSS + 0.017
V
VREFHI
Ref High
2 × Bandgap
2.473
2.593
2.682
V
Bandgap
1.257
1.301
1.330
V
VSS
VSS + 0.003
VSS + 0.014
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
2 × Bandgap
2.470
2.594
2.685
V
VAGND
AGND
Bandgap
1.256
1.300
1.332
V
VREFLO
Ref Low
VSS
VSS + 0.002
VSS + 0.012
V
–
–
–
–
–
–
All power settings
Not allowed at 3.3
V
VSS
–
DC Analog PSoC Block Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and–40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25
°C and are for design guidance only.
Table 18. DC Analog PSoC Block Specifications
Symbol
Description
Min
Typ
Max
Units
RCT
Resistor unit value (continuous time)
–
12.2
–
k
CSC
Capacitor unit value (switch cap)
–
80[9]
–
fF
DC POR and LVD Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at
25 °C and are for design guidance only.
Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Mixed-Signal Array Technical
Reference Manual for more information on the VLT_CR register.
Table 19. DC POR and LVD Specifications
Symbol
Description
VPPOR1
VPPOR2
VDD value for PPOR trip
PORLEV[1:0] = 01b
PORLEV[1:0] = 10b
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Vdd value for LVD trip
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
Min
Typ
Max
Units
Notes
VDD must be greater than or equal
to 2.5 V during startup or reset from
watchdog.
–
2.82
4.55
2.95
4.70
V
V
2.850
2.95
3.06
4.37
4.50
4.62
4.71
2.920
3.02
3.13
4.48
4.64
4.73
4.81
2.99[10]
3.09
3.20
4.55
4.75
4.83
4.95
V0
V0
V0
V0
V0
V
V
Notes
9. CSC is a design guarantee parameter, not tested value
10. Always greater than 50 mV above VPPOR (PORLEV=01) for falling supply.
Document Number: 001-44369 Rev. *I
Page 27 of 53
CY8C23433, CY8C23533
DC Programming Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and –40°C TA 85°C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C
and are for design guidance only.
Table 20. DC Programming Specifications
Min
Typ
Max
Units
Notes
VDDP
Symbol
VDD for programming and erase
Description
4.5
5
5.5
V
This specification applies to
the functional requirements
of external programmer tools
VDDLV
Low VDD for verify
3.0
3.1
3.2
V
This specification applies to
the functional requirements
of external programmer tools
VDDHV
High VDD for verify
5.1
5.2
5.3
V
This specification applies to
the functional requirements
of external programmer tools
3.0
–
5.25
V
This specification applies to
this device when it is
executing internal flash
writes
VDDIWRITE Supply voltage for flash write operation
IDDP
Supply current during programming or verify
–
5
25
mA
VILP
Input low voltage during programming or verify
–
–
0.8
V
VIHP
Input high voltage during programming or verify
2.1
–
–
V
IILP
Input current when applying vilp to P1[0] or
P1[1] during programming or verify
–
–
0.2
mA
Driving internal pull down
resistor
IIHP
Input current when applying vihp to P1[0] or
P1[1] during programming or verify
–
–
1.5
mA
Driving internal pull down
resistor
VOLV
Output low voltage during programming or
verify
–
–
VSS + 0.75
V
VOHV
Output high voltage during programming or
verify
VDD - 1.0
–
VDD
V
50,000
–
–
–
Erase/write cycles per block
1,800,000
–
–
–
Erase/write cycles
10
–
–
Years
FlashENPB Flash endurance (per block)
FlashENT
Flash endurance
FlashDR
Flash data retention
(total)[11]
DC I2C Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85°C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at
25°C and are for design guidance only.
Table 21. DC I2C Specifications[12]
Symbol
VILI2C
Input low level
Description
VIHI2C
Input high level
Min
–
–
0.7 × VDD
Typ
–
–
–
Max
0.3 × VDD
0.25 × VDD
–
Units
V
V
V
Notes
3.0 V VDD 3.6 V
4.75 V VDD 5.25 V
3.0 V VDD 5.25 V
Notes
11. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks
of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees
more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature
argument before writing. Refer to 0xthe Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
12. All GPIOs meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I2C GPIO pins also meet the above specs.
Document Number: 001-44369 Rev. *I
Page 28 of 53
CY8C23433, CY8C23533
SAR8 ADC DC Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and –40°C TA 85°C, or 3.0 V to 3.6 V and –40°C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C
and are for design guidance only.
Table 22. SAR8 ADC DC Specifications
Symbol
Description
VADCVREF Reference voltage at pin P3[0] when configured
as ADC reference voltage
IADCVREF
Current when P3[0] is configured as ADC VREF
INL
Integral non-linearity
INL
(limited
range)
Integral non-linearity accommodating a shift in
the offset at 0x80
DNL
Differential non-linearity
DNL
(limited
range)
Differential non-linearity excluding 0x7F-0x80
transition
Min
Typ
Max
Units
Notes
3.0
–
5.25
V
The voltage level at P3[0]
(when configured as ADC
reference voltage) must
always be maintained to be
less than chip supply voltage
level on VDD pin.
VADCVREF < VDD.
3
–
–
mA
–1.5
–
+1.5
LSB
–1.2[12]
–
+1.2
LSB
The maximum LSB is over a
sub-range not exceeding
1/16 of the full-scale range.
0x7F and 0x80 points specs
are excluded here
–2.3
–
+2.3
LSB
ADC conversion is
monotonic over full range
–1
–
+1
LSB
ADC conversion is
monotonic over full range.
0x7F to 0x80 transition specs
are excluded here.
Note
12. SAR converters require a stable input voltage during the sampling period. If the voltage into the SAR8 changes by more than 1 LSB during the sampling period then
the accuracy specifications may not be met
Document Number: 001-44369 Rev. *I
Page 29 of 53
CY8C23433, CY8C23533
AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and –40°C TA 85°C, or 3.0 V to 3.6 V and –40°C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C
and are for design guidance only.
Table 23. 5-V and 3.3-V AC Chip-Level Specifications
Description
Min
Typ
FIMO24 [13]
Symbol
Internal main oscillator frequency
for 24 MHz
22.8
24
FIMO6
Internal main oscillator frequency
for 6 MHz
5.5
6
FCPU1
CPU frequency (5-V nominal)
0.093
24
FCPU2
CPU Frequency (3.3-V nominal)
0.093
12
F48M
Digital PSoC block frequency
0
48
F24M
Digital PSoC block frequency
0
24
F32K1
Internal low speed oscillator
frequency
External crystal oscillator
15
32
25.2 [15, 17]
75
–
32.768
–
F32K_U
Internal low speed oscillator (ILO)
untrimmed frequency
5
–
100
FPLL
TPLLSLEW
TPLLSLEWSLOW
TOS
PLL frequency
PLL lock time
PLL lock time for low gain setting
External crystal oscillator startup
to 1%
External crystal oscillator startup
to 100 ppm
–
0.5
0.5
–
23.986
–
–
1700
–
10
50
2620
–
2800
3800
ms
External reset pulse width
24 MHz duty cycle
Internal low speed oscillator duty
cycle
24 MHz trim step size
48 MHz output frequency
10
40
20
–
50
50
–
60
80
ms
%
%
–
45.6
50
48.0
–
–
–
F32K2
TOSACC
TXRST
DC24M
DCILO
Step24M
Fout48M
FMAX
Maximum frequency of signal on row
input or row output.
Max
Units
Notes
25.2 [14, 15, 16] MHz Trimmed for 5V or 3.3V operation using
factory trim values. See Figure 8 on
page 14. SLIMO mode = 0.
[14, 15, 16] MHz Trimmed for 5V or 3.3V operation using
6.5
factory trim values. See Figure 8 on
page 14. SLIMO mode = 1.
[14, 15]
MHz
SLIMO
mode = 0.
25.2
12.6 [14, 15]
50.4
[14, 15,17]
50.4
[14, 16]
12.3
MHz SLIMO mode = 0.
MHz Refer to the AC digital block
Specifications.
MHz
kHz
kHz Accuracy is capacitor and crystal
dependent. 50% duty cycle.
kHz After a reset and before the m8c starts
to run, the ILO is not trimmed. See the
system resets section of the PSoC
technical reference manual for details
on timing this
MHz Is a multiple (x732) of crystal frequency.
ms
ms
ms
The crystal oscillator frequency is within
100 ppm of its final value by the end of
the Tosacc period. Correct operation
assumes a properly loaded 1 uW
maximum drive level 32.768 kHz
crystal. 3.0V £ VDD £ 5.5V, –40 °C £ TA
£ 85°C.
kHz
MHz Trimmed. Using factory trim values.
MHz
Notes
13. Errata: When the device is operated within 0 °C to 70 °C, the frequency tolerance is reduced to ±2.5%, but if operated at extreme temperature (below 0 °C or above
70 °C), frequency tolerance deviates from ±2.5% to ±5%. For more information, see “Errata” on page 51.
14. 4.75V < Vdd < 5.25V.
15. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range.
16. 3.0V < Vdd < 3.6V.
17. See the individual user module data sheets for information on maximum frequencies for user modules.
18. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
Document Number: 001-44369 Rev. *I
Page 30 of 53
CY8C23433, CY8C23533
Table 23. 5-V and 3.3-V AC Chip-Level Specifications (continued)
Min
Typ
Max
Units
SRPOWER_UP
Symbol
Power supply slew rate
–
–
250
V/ms VDD slew rate during power up.
TPOWERUP
Time from end of POR to CPU
executing code
–
16
100
ms
tjit_IMO [18]
24 MHz IMO cycle-to-cycle jitter
(RMS)
–
200
700
ps
24 MHz IMO long term N
cycle-to-cycle jitter (RMS)
–
300
900
ps
24 MHz IMO period jitter (RMS)
–
100
400
ps
24 MHz IMO cycle-to-cycle jitter
(RMS)
–
200
800
ps
24 MHz IMO long term N
cycle-to-cycle jitter (RMS)
–
300
1200
ps
24 MHz IMO period jitter (RMS)
–
100
700
ps
tjit_PLL [18]
Description
Notes
Power up from 0V. See the System Resets
section of the PSoC technical reference
manual.
N = 32
N = 32
Figure 9. PLL Lock Timing Diagram
PLL
Enable
TPLLSLEW
24 MHz
FPLL
PLL
Gain
0
Figure 10. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
TPLLSLEWLOW
24 MHz
FPLL
PLL
Gain
1
Figure 11. External Crystal Oscillator Startup Timing Diagram
32K
Select
32 kHz
TOS
F32K2
Document Number: 001-44369 Rev. *I
Page 31 of 53
CY8C23433, CY8C23533
AC GPIO Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and –40°C TA 85°C, or 3.0 V to 3.6 V and –40°C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C
and are for design guidance only.
Table 24. 5-V and 3.3-V AC GPIO Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
FGPIO
GPIO operating frequency
0
–
12.3
MHz
TRiseF
Rise time, normal strong mode, cload = 50 pF
3
–
18
ns
VDD = 4.5 V to 5.25 V, 10% - 90%
Normal strong mode
TFallF
Fall time, normal strong mode, cload = 50 pF
2
–
18
ns
VDD = 4.5 V to 5.25 V, 10% - 90%
TRiseS
Rise time, slow strong mode, cload = 50 pF
10
27
–
ns
VDD = 3 V to 5.25 V, 10% - 90%
TFallS
Fall time, slow strong mode, cload = 50 pF
10
22
–
ns
VDD = 3 V to 5.25 V, 10% - 90%
Figure 12. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
Document Number: 001-44369 Rev. *I
TFallF
TFallS
Page 32 of 53
CY8C23433, CY8C23533
AC Operational Amplifier Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and –40°C TA 85°C, or 3.0 V to 3.6 V and –40°C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C
and are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the analog continuous time PSoC block.
Power = high and Opamp bias = high is not supported at 3.3 V.
Table 25. 5-V AC Operational Amplifier Specifications
Symbol
Description
Min
Typ
Max
Units
TROA
Rising settling time from 80% of V to 0.1% of V (10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
–
–
–
–
–
–
3.9
0.72
0.62
s
s
s
TSOA
Falling settling time from 20% of V to 0.1% of V (10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
–
–
–
–
–
–
5.9
0.92
0.72
s
s
s
SRROA
Rising slew rate (20% to 80%)(10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
0.15
1.7
6.5
–
–
–
–
–
–
V/s
V/s
V/s
SRFOA
Falling slew rate (20% to 80%)(10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
0.01
0.5
4.0
–
–
–
–
–
–
V/s
V/s
V/s
BWOA
Gain bandwidth product
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
0.75
3.1
5.4
–
–
–
–
–
–
MHz
MHz
MHz
Min
Typ
Max
Units
–
–
–
–
3.92
0.72
s
s
–
–
–
–
5.41
0.72
s
s
0.31
2.7
–
–
–
–
V/s
V/s
0.24
1.8
–
–
–
–
V/s
V/s
0.67
2.8
–
–
–
–
MHz
MHz
Table 26. 3.3-V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
Description
Rising settling time from 80% of V to 0.1% of V (10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Falling settling time from 20% of V to 0.1% of V (10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Rising slew rate (20% to 80%)(10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Falling slew rate (20% to 80%)(10 pF load, unity gain)
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Gain bandwidth product
Power = low, Opamp bias = low
Power = medium, Opamp bias = high
Document Number: 001-44369 Rev. *I
Page 33 of 53
CY8C23433, CY8C23533
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor.
Figure 13. Typical AGND Noise with P2[4] Bypass
nV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 14. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
Document Number: 001-44369 Rev. *I
0.01
0.1
Freq (kHz)
1
10
100
Page 34 of 53
CY8C23433, CY8C23533
AC Low-Power Comparator Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and –40°C TA 85°C, or 3.0 V to 3.6 V and –40°C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C
and are for design guidance only.
Table 27. AC Low-Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Min
–
Typ
–
Max
50
Units
ms
Notes
³ 50 mV overdrive comparator
reference set within VREFLPC
AC Digital Block Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and –40°C TA 85°C, or 3.0 V to 3.6 V and –40°C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C
and are for design guidance only.
Table 28. 5-V and 3.3-V AC Digital Block Specifications
Function
All functions
Timer
Description
Max
Unit
–
–
50.4
MHz
VDD < 4.75 V
–
–
25.2
MHz
Notes
No capture, VDD 4.75 V
–
–
50.4
MHz
No capture, VDD < 4.75 V
–
–
25.2
MHz
With capture
–
–
25.2
MHz
50[19]
–
–
ns
Input clock frequency
Input clock frequency
No enable input, VDD 4.75 V
–
–
50.4
MHz
No enable input, VDD < 4.75 V
–
–
25.2
MHz
With enable input
–
–
25.2
MHz
50[19]
–
–
ns
Enable input pulse width
Dead Band
Typ
VDD 4.75 V
Capture pulse width
Counter
Min
Block input clock frequency
Kill pulse width
Asynchronous restart mode
20
–
–
ns
Synchronous restart mode
50[19]
–
–
ns
Disable mode
50[19]
–
–
ns
–
–
50.4
MHz
–
–
25.2
MHz
VDD 4.75 V
–
–
50.4
MHz
VDD < 4.75 V
–
–
25.2
MHz
Input clock frequency
VDD 4.75 V
VDD < 4.75 V
CRCPRS
(PRS Mode)
Input clock frequency
CRCPRS
(CRC Mode)
Input clock frequency
–
–
25.2
MHz
SPIM
Input clock frequency
–
–
8.2
MHz
The SPI serial clock (SCLK) frequency is equal to the input clock
frequency divided by 2.
The input clock is the SPI SCLK in SPIS mode.
SPIS
Input clock (SCLK) frequency
Width of SS_negated between transmissions
Transmitter
–
4.1
MHz
–
–
ns
–
–
50.4
MHz
Input clock frequency
VDD 4.75 V, 2 stop bits
Receiver
–
50[19]
The baud rate is equal to the input clock frequency divided by 8.
VDD 4.75 V, 1 stop bit
–
–
25.2
MHz
VDD < 4.75 V
–
–
25.2
MHz
–
–
50.4
MHz
Input clock frequency
VDD 4.75 V, 2 stop bits
The baud rate is equal to the input clock frequency divided by 8.
VDD 4.75 V, 1 stop bit
–
–
25.2
MHz
VDD < 4.75 V
–
–
25.2
MHz
Note
19. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
Document Number: 001-44369 Rev. *I
Page 35 of 53
CY8C23433, CY8C23533
AC Analog Output Buffer Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and –40°C TA 85°C, or 3.0 V to 3.6 V and –40°C TA 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C
and are for design guidance only.
Table 29. 5-V AC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
TROB
Rising settling time to 0.1%, 1 V step, 100 pF load
Power = low
Power = high
–
–
–
–
2.5
2.5
s
s
TSOB
Falling settling time to 0.1%, 1 V step, 100 pF load
Power = low
Power = high
–
–
–
–
2.2
2.2
s
s
SRROB
Rising slew rate (20% to 80%), 1 V step, 100 pF load
Power = low
Power = high
0.65
0.65
–
–
–
–
V/s
V/s
SRFOB
Falling slew rate (80% to 20%), 1 V step, 100 pF load
Power = low
Power = high
0.65
0.65
–
–
–
–
V/s
V/s
BWOB
Small signal bandwidth, 20 mVpp, 3 dB BW, 100 pF load
Power = low
Power = high
0.8
0.8
–
–
–
–
MHz
MHz
BWOB
Large signal bandwidth, 1 Vpp, 3 dB BW, 100 pF load
Power = low
Power = high
300
300
–
–
–
–
kHz
kHz
Min
Typ
Max
Units
Table 30. 3.3-V AC Analog Output Buffer Specifications
Symbol
Description
TROB
Rising settling time to 0.1%, 1 V step, 100 pF load
Power = low
Power = high
–
–
–
–
3.8
3.8
s
s
TSOB
Falling settling time to 0.1%, 1 V step, 100 pF load
Power = low
Power = high
–
–
–
–
2.6
2.6
s
s
SRROB
Rising slew rate (20% to 80%), 1 V step, 100 pF load
Power = low
Power = high
0.5
0.5
–
–
–
–
V/s
V/s
SRFOB
Falling slew rate (80% to 20%), 1 V step, 100 pF load
Power = low
Power = high
0.5
0.5
–
–
–
–
V/s
V/s
BWOB
Small signal bandwidth, 20 mVpp, 3 dB BW, 100 pF load
Power = low
Power = high
0.7
0.7
–
–
–
–
MHz
MHz
BWOB
Large signal bandwidth, 1 Vpp, 3 dB BW, 100 pF load
Power = low
Power = high
200
200
–
–
–
–
kHz
kHz
Document Number: 001-44369 Rev. *I
Page 36 of 53
CY8C23433, CY8C23533
AC External Clock Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C
and are for design guidance only.
Table 31. 5-V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT
Frequency
0.093
–
24.6
MHz
–
High period
20.6
–
5300
ns
–
Low period
20.6
–
–
ns
–
Power up IMO to switch
150
–
–
s
Table 32. 3.3-V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
0.093
–
12.3
MHz
Frequency with CPU clock divide by 2 or greater[21]
0.186
–
24.6
MHz
–
High period with CPU clock divide by 1
41.7
–
5300
ns
–
Low period with CPU clock divide by 1
41.7
–
–
ns
–
Power up IMO to switch
150
–
–
s
FOSCEXT
Frequency with CPU clock divide by
FOSCEXT
1[20]
AC Programming Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25
V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25
°C and are for design guidance only.
Table 33. AC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
TRSCLK
Rise time of SCLK
1
–
20
ns
TFSCLK
Fall time of SCLK
1
–
20
ns
TSSCLK
Data set up time to falling edge of SCLK
40
–
–
ns
THSCLK
Data hold time from falling edge of SCLK
40
–
–
ns
FSCLK
Frequency of SCLK
0
–
8
MHz
TERASEB
Flash erase time (block)
–
20
–
ms
TWRITE
Flash block write time
–
20
–
ms
TDSCLK
Data out delay from falling edge of SCLK
–
–
45
ns
VDD 3.6
TDSCLK3
Data out delay from falling edge of SCLK
–
–
50
ns
3.0 VDD 3.6
TERASEALL
Flash erase time (bulk)
–
80
–
ms
Erase all Blocks
and protection
fields at once
TPROGRAM_HOT Flash block erase + Flash block write time
–
–
100[23]
ms
0 °C
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