Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
CY8C24094/CY8C24794
CY8C24894/CY8C24994
PSoC® Programmable System-on-Chip™
PSoC® Programmable System-on-Chip™
Features
XRES pin to support in-system serial programming (ISSP) and
external reset control in CY8C24894
■
Powerful Harvard-architecture processor
❐ M8C processor speeds up to 24 MHz
❐ Two 8 × 8 multiply, 32-bit accumulate
❐ Low power at high speed
❐ Operating voltage: 3 V to 5.25 V
❐ Industrial temperature range: –40 °C to +85 °C
❐ USB temperature range: –10 °C to +85 °C
■
■
■
❐
■
■
Advanced peripherals (PSoC® Blocks)
❐ Six rail-to-rail analog PSoC blocks provide:
• Up to 14-bit analog-to-digital converters (ADCs)
• Up to 9-bit digital-to-analog converters (DACs)
• Programmable gain amplifiers (PGAs)
• Programmable filters and comparators
❐ Four digital PSoC blocks provide:
• 8- to 32-bit timers, counters, and pulse width modulators
(PWMs)
• Cyclical redundancy check (CRC) and pseudo random
sequence (PRS) modules
• Full-duplex universal asynchronous receiver transmitter
(UART)
• Multiple serial peripheral interface (SPI) masters or slaves
• Connectable to all general-purpose I/O (GPIO) pins
❐ Complex peripherals by combining blocks
❐ Capacitive sensing application (CSA) capability
Precision, programmable clocking
❐ Internal ±4% 24- / 48-MHz main oscillator
❐ Internal oscillator for watchdog and sleep
❐ 0.25% accuracy for USB with no external components
Additional system resources
2
❐ I C slave, master, and multi-master to 400 kHz
❐ Watchdog and sleep timers
❐ User-configurable low-voltage detection (LVD)
Logic Block Diagram
Port 5 Port 4 Port 3
Port 7
System Bus
■
■
Up to 48 analog inputs on GPIOs
Two 33 mA analog outputs on GPIOs
❐ Configurable interrupt on all GPIOs
❐
Global Digital Interconnect
Port 2 Port 1 Port 0 Analog
Drivers
Global Analog Interconnect
PSoC CORE
SRAM
1K
SROM
Flash16 KB
CPU Core (M8C)
Interrupt
Controller
Sleep and
Watchdog
Clock Sources
(Includes IMO and ILO)
Full speed USB (12 Mbps)
❐ Four unidirectional endpoints
❐ One bidirectional control endpoint
❐ USB 2.0 compliant
❐ Dedicated 256 byte buffer
❐ No external crystal required
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref.
Flexible on-chip memory
❐ 16 KB flash program storage 50,000 erase and write cycles
❐ 1 KB static random access memory (SRAM) data storage
❐ ISSP
❐ Partial flash updates
❐ Flexible protection modes
❐ Electrically erasable programmable read-only memory
(EEPROM) emulation in flash
Digital
Block
Array
Analog
Block
Array
Digital
2
Decimator
Clocks MACs Type 2
I2C
POR and LVD Internal
Voltage
System Resets
Ref.
USB
Analog
Input
Muxing
SYSTEM RESOURCES
Programmable pin configurations
❐ 25-mA sink, 10-mA source on all GPIOs
❐ Pull-up, pull-down, high Z, strong, or open-drain drive modes
on all GPIOs
Errata: For information on silicon errata, see “Errata” on page 64. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation
Document Number: 38-12018 Rev. AN
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 23, 2019
CY8C24094/CY8C24794
CY8C24894/CY8C24994
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
KBA92181, Resources Available for CapSense® Controllers. Following is an abbreviated list for CapSense devices:
■
■
■
■
Overview: CapSense Portfolio, CapSense Roadmap
Product Selectors: CapSense, CapSense Plus, CapSense
Express, PSoC3 with CapSense, PSoC5 with CapSense,
PSoC4. In addition, PSoC Designer offers a device selection
tool at the time of creating a new project.
Application notes: Cypress offers CapSense application notes
covering a broad range of topics, from basic to advanced level.
Recommended application notes for getting started with
CapSense are:
❐ AN64846: Getting Started With CapSense
❐ AN2397: CapSense® Data Viewing Tools
Technical Reference Manual (TRM):
❐ CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43,
CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13,
CY8C21x34, CY8C21x34B, CY8C21x23, CY7C64215,
CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip TRM
Development Kits:
❐ CY3280-24x94 Universal CapSense Controller Board
features a predefined control circuitry and plug-in hardware
to make prototyping and debugging easy. Programming and
I2C-to-USB Bridge hardware are included for tuning and data
acquisition.
❐ CY3280-BMM Matrix Button Module Kit consists of eight
CapSense sensors organized in a 4x4 matrix format to form
16 physical buttons and eight LEDs. This module connects
to any CY3280 Universal CapSense Controller Board,
including CY3280-20x66 Universal CapSense Controller.
❐ CY3280-BSM Simple Button Module Kit consists of ten CapSense buttons and ten LEDs. This module connects to any
CY3280 Universal CapSense Controller Board, including
CY3280-20x66 Universal CapSense Controller.
The CY3217-MiniProg1 and CY8CKIT-002 PSoC® MiniProg3
device provides an interface for flash programming.
■
PSoC Designer
PSoC Designer is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of systems based on CapSense (see Figure 1). With PSoC Designer, you can:
1. Drag and drop User Modules to build your hardware system
3. Configure User Module
design in the main design workspace
4. Explore the library of user modules
2. Codesign your application firmware with the PSoC hardware,
5. Review user module datasheets
using the PSoC Designer IDE C compiler
Figure 1. PSoC Designer Features
1
2
3
5
Document Number: 38-12018 Rev. AN
4
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Contents
PSoC Functional Overview .............................................. 4
The PSoC Core ........................................................... 4
The Digital System ...................................................... 4
The Analog System ..................................................... 5
Additional System Resources ..................................... 6
PSoC Device Characteristics ...................................... 6
Getting Started .................................................................. 7
Application Notes ........................................................ 7
Development Kits ........................................................ 7
Training ....................................................................... 7
CYPros Consultants .................................................... 7
Solutions Library .......................................................... 7
Technical Support ....................................................... 7
Development Tools .......................................................... 7
PSoC Designer Software Subsystems ........................ 7
Designing with PSoC Designer ....................................... 8
Select User Modules ................................................... 8
Configure User Modules .............................................. 8
Organize and Connect ................................................ 8
Generate, Verify, and Debug ....................................... 8
Pin Information ................................................................. 9
56-Pin Part Pinout ....................................................... 9
56-Pin Part Pinout (with XRES) ................................. 10
68-Pin Part Pinout ..................................................... 11
68-Pin Part Pinout (On-Chip Debug) ......................... 12
100-Ball VFBGA Part Pinout ..................................... 13
100-Ball VFBGA Part Pinout (On-Chip Debug) ......... 15
100-Pin Part Pinout (On-Chip Debug) ....................... 17
Register Reference ......................................................... 19
Register Conventions ................................................ 19
Register Mapping Tables .......................................... 19
Register Map Bank 0 Table: User Space .................. 20
Register Map Bank 1 Table: Configuration Space .... 21
Document Number: 38-12018 Rev. AN
Electrical Specifications ................................................ 22
Absolute Maximum Ratings ....................................... 22
Operating Temperature ............................................. 23
DC Electrical Characteristics ..................................... 23
AC Electrical Characteristics ..................................... 40
Thermal Impedance .................................................. 49
Solder Reflow Peak Specifications ............................ 49
Development Tool Selection ......................................... 50
Software .................................................................... 50
Development Kits ...................................................... 50
Evaluation Tools ........................................................ 50
Device Programmers ................................................. 51
Accessories (Emulation and Programming) .............. 51
Ordering Information ...................................................... 52
Ordering Code Definitions ......................................... 52
Packaging Dimensions .................................................. 53
Acronyms ........................................................................ 58
Acronyms Used ......................................................... 58
Document Conventions ................................................. 59
Units of Measure ....................................................... 59
Numeric Conventions ................................................ 59
Glossary .......................................................................... 59
Errata ............................................................................... 64
Part Numbers Affected .............................................. 64
CY8C24x94 Errata Summary .................................... 64
Document History Page ................................................. 68
Sales, Solutions, and Legal Information ...................... 72
Worldwide Sales and Design Support ....................... 72
Products .................................................................... 72
PSoC® Solutions ...................................................... 72
Cypress Developer Community ................................. 72
Technical Support ..................................................... 72
Page 3 of 72
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The PSoC family consists of many devices with on-chip
controllers. These devices are designed to replace multiple
traditional MCU-based system components with one low-cost
single-chip programmable component. A PSoC device includes
configurable blocks of analog and digital logic, and
programmable interconnect. This architecture makes it possible
for you to create customized peripheral configurations, to match
the requirements of each individual application. Additionally, a
fast central processing unit (CPU), flash program memory,
SRAM data memory, and configurable I/O are included in a
range of convenient pinouts.
The PSoC architecture, shown in the Logic Block Diagram on
page 1, consists of four main areas: the core, the system
resources, the digital system, and the analog system.
Configurable global bus resources allow combining all of the
device resources into a complete custom system. Each
CY8C24x94 PSoC device includes four digital blocks and six
analog blocks. Depending on the PSoC package, up to 56
GPIOs are also included. The GPIOs provide access to the
global digital and analog interconnects.
The PSoC Core
The PSoC core is a powerful engine that supports a rich
instruction set. It encompasses SRAM for data storage, an
interrupt controller, sleep and watchdog timers, and internal main
oscillator (IMO) and internal low-speed oscillator (ILO). The CPU
core, called the M8C, is a powerful processor with speeds up to
24 MHz. The M8C is a four-million instructions per second
(MIPS) 8-bit Harvard-architecture microprocessor.
System resources provide these additional capabilities:
■
Digital clocks for increased flexibility
■
I2C functionality to implement an I2C master and slave
■
An internal voltage reference, multi-master, that provides an
absolute value of 1.3 V to a number of PSoC subsystems
■
A switch-mode pump (SMP) that generates normal operating
voltages from a single battery cell
■
Various system resets supported by the M8C
The analog system consists of six analog PSoC blocks,
supporting comparators, and analog-to-digital conversion up to
10-bits of precision.
Document Number: 38-12018 Rev. AN
The digital system consists of four digital PSoC blocks. Each
block is an 8-bit resource that is used alone or combined with
other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which
are called user modules. Digital peripheral configurations
include:
■
PWMs (8- to 32-bit)
■
PWMs with dead band (8- to 32-bit)
■
Counters (8- to 32-bit)
■
Timers (8- to 32-bit)
■
UART 8-bit with selectable parity
■
SPI master and slave
■
I2C slave and multi-master
■
CRC/generator (8-bit)
■
IrDA
■
PRS generators (8- to 32-bit)
The digital blocks are connected to any GPIO through a series
of global buses that can route any signal to any pin. The buses
also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows the optimum
choice of system resources for your application. Family
resources are shown in Table 1 on page 6.
Figure 2. Digital System Block Diagram
Port 7
Port 5
Port 3
Port 4
Port 1
Port 2
To System Bus
Digital Clocks
From Core
Port 0
To Analog
System
DIGITAL SYSTEM
Digital PSoC Block Array
8
8
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
Row Output
Configuration
The digital system consists of an array of digital PSoC blocks that
may be configured into any number of digital peripherals. The
digital blocks are connected to the GPIOs through a series of
global buses. These buses can route any signal to any pin,
freeing designs from the constraints of a fixed peripheral
controller.
The Digital System
Row Input
Configuration
PSoC Functional Overview
8
8
GOE[7:0]
GOO[7:0]
Page 4 of 72
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Figure 3. Analog System Block Diagram
The analog system is composed of six configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are as follows.
■
Filters (2 and 4 pole band-pass, low-pass, and notch)
■
Amplifiers (up to two, with selectable gain to 48x)
■
Instrumentation amplifiers (one with selectable gain to 93x)
■
Comparators (up to two, with 16 selectable thresholds)
■
DACs (up to two, with 6- to 9-bit resolution)
■
Multiplying DACs (up to two, with 6- to 9-bit resolution)
■
High current output drivers (two with 30 mA drive as a PSoC
core resource)
■
1.3-V reference (as a system resource)
■
DTMF dialer
■
Modulators
■
Correlators
■
Peak detectors
■
Many other topologies possible
P 0 [6 ]
P 0 [5 ]
P 0 [4 ]
P 0 [3 ]
P 0 [2 ]
P 0 [1 ]
P 0 [0 ]
P 2 [3 ]
AGNDIn RefIn
ADCs (up to two, with 6- to 14-bit resolution, selectable as
incremental, delta sigma, and successive approximation
register (SAR))
P 0 [7 ]
Analog
■
A ll IO
(E x c e p t P o r t 7 )
Mux Bus
The Analog System
P 2 [6 ]
P 2 [4 ]
P 2 [1 ]
P 2 [2 ]
P 2 [0 ]
A C I 0 [1 :0 ]
A C I 1 [1 :0 ]
A r r a y In p u t
C o n f ig u r a t io n
B lo c k
A rray
AC B00
A C B 01
A SC 10
A SD 11
ASD20
A SC 21
A n a lo g R e f e r e n c e
In t e r f a c e t o
D ig it a l S y s t e m
Analog blocks are arranged in a column of three, which includes
one continuous time (CT) and two switched capacitor (SC)
blocks, as shown in Figure 3.
R e fH i
R e fL o
AGND
R e fe r e n c e
G e n e ra to rs
A G N D In
R e fIn
B andgap
M 8 C In t e r f a c e ( A d d r e s s B u s , D a t a B u s , E t c .)
The Analog Multiplexer System
The analog mux bus can connect to every GPIO pin in ports 0–
5. Pins are connected to the bus individually or in any combination. The bus also connects to the analog system for analysis
with comparators and analog-to-digital converters. It is split into
two sections for simultaneous dual-channel processing. An
additional 8:1 analog input multiplexer provides a second path to
bring Port 0 pins to the analog array.
Switch-control logic enables selected pins to precharge continuously under hardware control. This enables capacitive
measurement for applications such as touch sensing. Other
multiplexer applications include:
Document Number: 38-12018 Rev. AN
■
Track pad, finger sensing
■
Chip-wide mux that enables analog input from up to 48 I/O pins
■
Crosspoint connection between any I/O pin combinations
Page 5 of 72
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Additional System Resources
System resources provide additional capability useful to
complete systems. Additional resources include a multiplier,
decimator, low-voltage detection, and power-on reset (POR).
Brief statements describing the merits of each resource follow.
■
■
Full speed USB (12 Mbps) with five configurable endpoints and
256 bytes of RAM. No external components required except
for two series resistors. Wider than commercial temperature
USB operation (–10 °C to +85 °C).
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks are
generated using digital PSoC blocks as clock dividers.
■
Two multiply accumulates (MACs) provide fast 8-bit multipliers
with 32-bit accumulate, to assist in both general math and
digital filters.
■
Decimator provides a custom hardware filter for digital signal
processing applications including creation of Delta Sigma
ADCs.
■
The I2C module provides 100- and 400-kHz communication
over two wires. Slave, master, multi-master are supported.
■
Low-voltage detection interrupts signal the application of falling
voltage levels, while the advanced POR circuit eliminates the
need for a system supervisor.
■
An internal 1.3-V reference provides an absolute reference for
the analog system, including ADCs and DACs.
■
Versatile analog multiplexer system.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4
analog blocks. The following table lists the resources available for specific PSoC device groups. The device covered by this datasheet
is shown in the highlighted row of the table.
Table 1. PSoC Device Characteristics
PSoC Part Number Digital I/O
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Analog
Outputs Columns
Analog
Blocks
SRAM Size
Flash Size
CY8C29x66
up to 64
4
16
up to 12
4
4
12
2K
32 K
CY8C28xxx
up to 44
up to 3
up to 12
up to 44
up to 4
up to 6
up to
12 + 4[1]
1K
16 K
CY8C27x43
up to 44
2
8
up to 12
4
4
12
256
16 K
CY8C24x94
up to 56
1
4
up to 48
2
2
6
1K
16 K
CY8C24x23A
up to 24
1
4
up to 12
2
2
6
256
4K
CY8C23x33
up to 26
1
4
up to 12
2
2
4
256
8K
CY8C22x45
up to 38
2
8
up to 38
0
4
6[1]
1K
16 K
CY8C21x45
up to 24
1
4
up to 24
0
4
6[1]
512
8K
CY8C21x34
up to 28
1
4
up to 28
0
2
4[1]
512
8K
CY8C21x23
up to 16
1
4
up to 8
0
2
4[1]
256
4K
CY8C20x34
up to 28
0
0
up to 28
0
0
3[1,2]
512
8K
0
3[1,2]
up to 2 K
up to 32 K
CY8C20xx6
up to 36
0
0
up to 36
0
Notes
1. Limited analog functionality.
2. Two analog blocks and one CapSense®.
Document Number: 38-12018 Rev. AN
Page 6 of 72
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Getting Started
For in-depth information, along with detailed programming information, see the Technical Reference Manual for this PSoC
device.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web
at http://www.cypress.com.
Application Notes
Cypress application notes are an excellent introduction to the
wide variety of possible PSoC designs.
Development Kits
PSoC Development Kits are available online from and through a
growing number of regional and global distributors, which
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and
Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops), which is available online via www.cypress.com,
covers a wide variety of topics and skill levels to assist you in
your designs.
CYPros Consultants
Certified PSoC consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC
consultant go to the CYPros Consultants web site.
Solutions Library
Visit our growing library of solution-focused designs. Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
■
Integrated source-code editor (C and assembly)
■
Free C compiler with no size restrictions or time limits
■
Built-in debugger
■
In-circuit emulation
Built-in support for communication interfaces:
2
❐ Hardware and software I C slaves and masters
❐ Full speed USB 2.0
❐ Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
■
PSoC Designer Software Subsystems
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), amplifiers, and filters.
Configure the user modules for your chosen application and
connect them to each other and to the proper pins. Then
generate your project. This prepopulates your project with APIs
and libraries that you can use to program your application.
The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration
makes it possible to change configurations at run time. In
essence, this allows you to use more than 100 percent of PSoC’s
resources for an application.
Code Generation Tools
Technical Support
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
Technical support – including a searchable Knowledge Base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and are
linked with other software modules to get absolute addressing.
Development Tools
PSoC Designer™ is the revolutionary Integrated Design
Environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
■
Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■
Extensive user module catalog
Document Number: 38-12018 Rev. AN
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
You can read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also allows you to create a trace buffer of registers and memory
locations of interest.
Page 7 of 72
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Online Help System
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an online support forum
to aid the designer.
In-Circuit Emulator
A low-cost, high-functionality In-Circuit Emulator (ICE) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full speed
(24-MHz) operation.
User Module configures one or more digital PSoC blocks, one
for each 8 bits of resolution. The user module parameters permit
you to establish the pulse width and duty cycle. Configure the
parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from
drop-down menus. All the user modules are documented in
datasheets that may be viewed directly in PSoC Designer or on
the Cypress website. These user module datasheets explain the
internal operation of the user module and provide performance
specifications. Each datasheet describes the use of each user
module parameter, and other information you may need to
successfully implement your design.
Organize and Connect
You build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. You perform the
selection, configuration, and routing so that you have complete
control over all on-chip resources.
Designing with PSoC Designer
Generate, Verify, and Debug
The development process for the PSoC® device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
The PSoC development process is summarized in four steps:
When you are ready to test the hardware configuration or move
on to developing code for the project, you perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides application programming interfaces
(APIs) with high-level functions to control and respond to
hardware events at run time and interrupt service routines that
you can adapt as needed.
1. Select User Modules
2. Configure User Modules
3. Organize and Connect
4. Generate, Verify, and Debug
Select User Modules
PSoC Designer provides a library of prebuilt, pretested hardware
peripheral components called “user modules.” User modules
make selecting and implementing peripheral devices, both
analog and digital, simple.
Configure User Modules
Each user module that you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a PWM
Document Number: 38-12018 Rev. AN
A complete code development environment allows you to
develop and customize your applications in either C, assembly
language, or both.
The last step in the development process takes place inside
PSoC Designer’s debugger (access by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition
to traditional single-step, run-to-breakpoint, and watch-variable
features, the debug interface provides a large trace buffer and
allows you to define complex breakpoint events. These include
monitoring address and data bus values, memory locations and
external signals.
Page 8 of 72
CY8C24094/CY8C24794
CY8C24894/CY8C24994
Pin Information
This section describes, lists, and illustrates the CY8C24x94 PSoC device family pins and pinout configuration.
The CY8C24x94 PSoC devices are available in the following packages, all of which are shown on the following pages. Every port pin
(labeled with a “P”) is capable of Digital I/O. However, VSS, VDD, and XRES are not capable of Digital I/O.
56-Pin Part Pinout
See LEGEND details and footnotes in Table 3 on page 10.
Table 2. 56-Pin Part Pinout (QFN[6])
P2[4],M
44
43
25
26
27
28
M, I2C SDA, P1[0]
M,P1[2]
EXTCLK, M,P1[4]
M, P1[6]
P7[0]
46
45
Vdd
P0[6], A, I, M
P0[4], A, I, M
P0[2], A, I, M
P0[0], A, I, M
P2[6],M
P0[5], A, IO, M
P0[7], A, I, M
Vss
21
22
23
24
51
50
49
48
47
M,P1[3]
M, I2C SCL, P1[1]
Vss
D+
DVdd
P7[7]
M, I2C SCL, P1[7]
M, I2C SDA, P1[5]
15
16
17
18
19
20
56
55
54
53
52
P2[5],M
P2[7],M
P0[1], A, I, M
P0[3], A, IO, M
Pin
Type
Pin
Type
Name
Description
Name
Description
No. Digital Analog
No. Digital Analog
1
I/O
I, M
P2[3] Direct switched capacitor block input
Figure 4. CY8C24794 56-Pin PSoC Device [3]
2
I/O
I, M
P2[1] Direct switched capacitor block input
3
I/O
M
P4[7]
4
I/O
M
P4[5]
5
I/O
M
P4[3]
6
I/O
M
P4[1]
7
I/O
M
P3[7]
A, I, M , P2[3]
1
P2[2], A, I, M
42
8
I/O
M
P3[5]
A, I, M , P2[1]
2
P2[0], A, I, M
41
M , P4[7]
9
I/O
M
P3[3]
3
P4[6], M
40
M
,
P4[5]
4
P4[4], M
39
10
I/O
M
P3[1]
M , P4[3]
5
P4[2], M
38
11
I/O
M
P5[7]
M , P4[1]
6
P4[0], M
37
12
I/O
M
P5[5]
M , P3[7]
7
P3[6], M
36
QFN
M , P3[5]
8
35
P3[4], M
13
I/O
M
P5[3]
(Top V ie w )
M , P3[3]
9
34
P3[2], M
14
I/O
M
P5[1]
M
,
P3[1]
10
P3[0], M
33
15
I/O
M
P1[7] I2C serial clock (SCL)
M , P5[7]
11
P5[6], M
32
16
I/O
M
P1[5] I2C serial data (SDA)
M , P5[5]
12
P5[4], M
31
M
,
P5[3]
13
P5[2], M
30
17
I/O
M
P1[3]
M
,
P5[1]
P5[0], M
14
29
18
I/O
M
P1[1] I2C SCL, ISSP SCLK [4]
19
Power
VSS Ground connection [5]
20
USB
D+
21
USB
D–
22
Power
VDD Supply voltage
23
I/O
P7[7]
24
I/O
P7[0]
25
I/O
M
P1[0] I2C SDA, ISSP SDATA[4]
26
I/O
M
P1[2]
27
I/O
M
P1[4] Optional external clock input (EXTCLK)
28
I/O
M
P1[6]
29
I/O
M
P5[0]
30
I/O
M
P5[2]
31
I/O
M
P5[4]
44
I/O
M
P2[6] External voltage reference (VREF) input
32
I/O
M
P5[6]
45
I/O
I, M
P0[0] Analog column mux input
33
I/O
M
P3[0]
46
I/O
I, M
P0[2] Analog column mux input
34
I/O
M
P3[2]
47
I/O
I, M
P0[4] Analog column mux input VREF
35
I/O
M
P3[4]
48
I/O
I, M
P0[6] Analog column mux input
36
I/O
M
P3[6]
49
Power
VDD Supply voltage
37
I/O
M
P4[0]
50
Power
VSS Ground connection [5]
38
I/O
M
P4[2]
51
I/O
I, M
P0[7] Analog column mux input
39
I/O
M
P4[4]
52
I/O
I/O, M P0[5] Analog column mux input and column output
40
I/O
M
P4[6]
53
I/O
I/O, M P0[3] Analog column mux input and column output
41
I/O
I, M
P2[0] Direct switched capacitor block input
54
I/O
I, M
P0[1] Analog column mux input
42
I/O
I, M
P2[2] Direct switched capacitor block input
55
I/O
M
P2[7]
43
I/O
M
P2[4] External analog ground (AGND) input
56
I/O
M
P2[5]
Notes
3. This part cannot be programmed with Reset mode; use Power Cycle mode when programming.
4. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.
5. All VSS pins should be brought out to one common GND plane.
Document Number: 38-12018 Rev. AN
Page 9 of 72
CY8C24094/CY8C24794
CY8C24894/CY8C24994
56-Pin Part Pinout (with XRES)
Table 3. 56-Pin Part Pinout (QFN[6])
pull-down
37
I/O
M
P4[0]
38
I/O
M
P4[2]
39
I/O
M
P4[4]
40
I/O
M
P4[6]
41
I/O
I, M
P2[0] Direct switched capacitor block input
42
I/O
I, M
P2[2] Direct switched capacitor block input
43
I/O
M
P2[4] External AGND input
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Pin
Type
Name
No. Digital Analog
Description
M
M
M
M
I,
I,
I,
I,
A,
A,
A,
A,
M
M
48
47
46
45
44
43
1
2
3
4
5
6
7
8
9
10
11
12
13
14
QFN
(Top Vie w)
15
16
17
18
19
20
21
22
23
24
25
26
27
28
P2[3]
P2[1]
P4[7]
P4[5]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
42
41
40
39
38
37
36
35
34
33
32
31
30
29
P2[2],
P2[0],
P4[6],
P4[4],
P4[2],
P4[0],
XRES
P3[4],
P3[2],
P3[0],
P5[6],
P5[4],
P5[2],
P5[0],
A, I, M
A, I, M
M
M
M
M
M
M
M
M
M
M
M
P1[7]
P1[5]
P1[3]
P1[1]
Vss
D+
DVdd
P7[7]
P7[0]
M, I2C SDA, P1[0]
M, P1[2]
EXTCLK, M, P1[4]
M, P1[6]
A, I, M,
A, I, M,
M,
M,
M,
M,
M,
M,
M,
M,
M,
M,
M,
M,
56
55
54
53
52
51
50
49
P2[5],
P2[7],
P0[1],
P0[3],
P0[5],
P0[7],
Vss
Vdd
P0[6],
P0[4],
P0[2],
P0[0],
P2[6],
P2[4],
M
M
A,
A,
A,
A,
I, M
IO, M
IO, M
I, M
Figure 5. CY8C24894 56-Pin PSoC Device
M, I2C SCL,
M, I2C SDA,
M,
M, I2C SCL,
Pin
Type
Name
Description
No. Digital Analog
1
I/O
I, M
P2[3] Direct switched capacitor block input
2
I/O
I, M
P2[1] Direct switched capacitor block input
3
I/O
M
P4[7]
4
I/O
M
P4[5]
5
I/O
M
P4[3]
6
I/O
M
P4[1]
7
I/O
M
P3[7]
8
I/O
M
P3[5]
9
I/O
M
P3[3]
10
I/O
M
P3[1]
11
I/O
M
P5[7]
12
I/O
M
P5[5]
13
I/O
M
P5[3]
14
I/O
M
P5[1]
15
I/O
M
P1[7] I2C SCL
16
I/O
M
P1[5] I2C SDA
17
I/O
M
P1[3]
18
I/O
M
P1[1] I2C SCL, ISSP SCLK [7]
19
Power
VSS Ground connection [8]
20
USB
D+
21
USB
D–
22
Power
VDD Supply voltage
23
I/O
P7[7]
24
I/O
P7[0]
25
I/O
M
P1[0] I2C SDA, ISSP SDATA[7]
26
I/O
M
P1[2]
27
I/O
M
P1[4] Optional EXTCLK
28
I/O
M
P1[6]
29
I/O
M
P5[0]
30
I/O
M
P5[2]
31
I/O
M
P5[4]
32
I/O
M
P5[6]
33
I/O
M
P3[0]
34
I/O
M
P3[2]
35
I/O
M
P3[4]
36
Input
XRES Active high external reset with internal
44
45
46
47
48
49
I/O
M
I/O
I, M
I/O
I, M
I/O
I, M
I/O
I, M
Power
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
VDD
External VREF input
Analog column mux input
Analog column mux input
Analog column mux input VREF
Analog column mux input
Supply voltage
50
51
52
53
54
55
56
Power
I/O
I, M
I/O
I/O, M
I/O
I/O, M
I/O
I, M
I/O
M
I/O
M
VSS
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
Ground connection [8]
Analog column mux input
Analog column mux input and column output
Analog column mux input and column output
Analog column mux input
Notes
6. The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it
should be electrically floated and not connected to any other signal.
7. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.
8. All VSS pins should be brought out to one common GND plane.
Document Number: 38-12018 Rev. AN
Page 10 of 72
CY8C24094/CY8C24794
CY8C24894/CY8C24994
68-Pin Part Pinout
The following 68-pin QFN part table and drawing is for the CY8C24994 PSoC device.
Table 4. 68-Pin Part Pinout (QFN[9])
44
45
46
Input
M
M
M
M
M
M
M
M
M
M
M
M
NC
NC
XRES
Pin
No.
Type
Digital Analog
Name
Description
I2C SDA, ISSP SDATA[11]
Optional EXTCLK
No connection. Pin must be left floating.
No connection. Pin must be left floating.
Active high pin reset with internal
50
51
52
53
54
55
56
57
58
59
60
61
62
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
Power
I/O
I/O
M
I, M
I, M
M
M
I, M
I, M
I, M
I, M
I, M
I/O, M
P4[6]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
VDD
VSS
P0[7]
P0[5]
63
64
65
I/O
I/O
I/O
I/O, M
I, M
M
P0[3]
P0[1]
P2[7]
P2[6], M, Ext. VREF
P2[4], M, Ext. AGND
P2[2], M, AI
53
52
P0[2], M, AI
P0[0], M, AI
58
57
56
P0[7], M, AI
Vss
Vdd
P0[6], M, AI
P0[4], M, AI
P0[1], M, AI
P0[3], M, AIO
P0[5], M, AIO
63
62
61
60
59
55
54
38
37
36
35
P2[0], M, AI
P4[6], M
P4[4], M
P4[2], M
P4[0], M
XRES
NC
NC
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
P1[6], M
EXTCLK, M, P1[4]
31
32
33
34
I2C SDA, M, P1[0]
M, P1[2]
Supply voltage
28
29
30
I2C SCL ISSP SCLK[11]
Ground connection [10]
QFN
(Top View)
P7[3]
P7[2]
P7[1]
P7[0]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]
I2C SCL, M, P1[7]
I2C SDA, M, P1[5]
49
48
47
46
45
44
43
42
41
40
39
24
25
26
27
I2C SCL
I2C SDA
51
50
P7[7]
P7[6]
P7[5]
P7[4]
M, P4[1]
NC
NC
Vss
M, P3[7]
M, P3[5]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
20
21
22
23
M, P4[7]
M, P4[5]
M, P4[3]
64
P2[3], M, AI
P2[5], M
P2[7], M
No connection. Pin must be left floating
No connection. Pin must be left floating
Ground connection [10]
66
65
P2[1], M, AI
Figure 6. CY8C24994 68-Pin PSoC Device
68
67
M
M
M
M
M
M
M
M
M
M
M
M
P4[7]
P4[5]
P4[3]
P4[1]
NC
NC
VSS
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
VSS
D+
D–
VDD
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
P1[0]
P1[2]
P1[4]
P1[6]
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
P3[6]
Description
18
19
Power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
USB
USB
Power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Name
M, P1[3]
Type
Digital Analog
I/O
M
I/O
M
I/O
M
I/O
M
I2C SCL, M, P1[1]
Vss
D+
DVdd
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
Direct switched capacitor block input
Direct switched capacitor block input
External AGND input
External VREF input
Analog column mux input
Analog column mux input and column output
Analog column mux input and column output
Analog column mux input
Supply voltage
Ground connection [10]
Analog column mux input, integration input #1
Analog column mux input and column output, integration
input #2
Analog column mux input and column output
Analog column mux input
pull-down.
47 I/O
M
P4[0]
66 I/O
M
P2[5]
48 I/O
M
P4[2]
67 I/O
I, M
P2[3] Direct switched capacitor block input
M
P4[4]
68 I/O
I, M
P2[1] Direct switched capacitor block input
49 I/O
LEGEND A = Analog, I = Input, O = Output, NC = No connection. Pin must be left floating, M = Analog Mux Input.
Notes
9. The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it
should be electrically floated and not connected to any other signal.
10. All VSS pins should be brought out to one common GND plane.
11. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.
Document Number: 38-12018 Rev. AN
Page 11 of 72
CY8C24094/CY8C24794
CY8C24894/CY8C24994
68-Pin Part Pinout (On-Chip Debug)
The following 68-pin QFN part table and drawing is for the CY8C24094 OCD PSoC device.
Note: This part is only used for in-circuit debugging. It is NOT available for production.
Table 5. 68-Pin Part Pinout (QFN[12])
M
M
M
M
M
M
M
M
M
M
M
M
Pin
Type
Name
No. Digital Analog
Description
I2C SDA, ISSP SDATA[14]
Optional EXTCLK
50
51
52
53
54
55
56
57
58
59
60
61
62
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
Power
I/O
I/O
M
I, M
I, M
M
M
I, M
I, M
I, M
I, M
I, M
I/O, M
44
HCLK OCD high speed clock output
63 I/O
I/O, M
45
CCLK OCD CPU clock output
64 I/O
I, M
46
Input
XRES Active high pin reset with internal pull-down 65 I/O
M
47
I/O
M
P4[0]
66 I/O
M
48
I/O
M
P4[2]
67 I/O
I, M
49
I/O
M
P4[4]
68 I/O
I, M
LEGEND A = Analog, I = Input, O = Output, M = Analog Mux Input, OCD = On-Chip Debugger.
P4[6]
P2[0]
P2[2]
P2[4]
P2[6]
P0[0]
P0[2]
P0[4]
P0[6]
VDD
VSS
P0[7]
P0[5]
P0[3]
P0[1]
P2[7]
P2[5]
P2[3]
P2[1]
P2[6], M, Ext. VREF
P2[4], M, Ext. AGND
P2[2], M, AI
28
29
30
31
32
33
34
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
P2[0], M, AI
P4[6], M
P4[4], M
P4[2], M
P4[0], M
XRES
CCLK
HCLK
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
P1[6], M
,
55
54
53
52
58
57
56
64
63
62
61
60
59
P0[7], M, AI
Vss
Vdd
P0[6], M, AI
P0[4], M, AI
P0[2], M, AI
P0[0], M, AI
I2C SDA, M, P1[0]
M, P1[2]
EXTCLK M, P1[4]
Supply voltage
P7[3]
P7[2]
P7[1]
P7[0]
I2C SCL, ISSP SCLK [14]
Ground connection [13]
QFN
(Top View)
P7[7]
P7[6]
P7[5]
P7[4]
I2C SCL
I2C SDA
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
23
24
25
26
27
M, P4[7]
M, P4[5]
M, P4[3]
M, P4[1]
OCDE
OCDO
Vss
M, P3[7]
M, P3[5]
M, P3[3]
M, P3[1]
M, P5[7]
M, P5[5]
M, P5[3]
M, P5[1]
I2C SCL, M, P1[7]
I2C SDA, M, P1[5]
P2[3], M, AI
P2[5], M
P2[7], M
P0[1], M, AI
P0[3], M, AIO
P0[5], M, AIO
OCD even data I/O
OCD odd data output
Ground connection [13]
66
65
P2[1], M, AI
Figure 7. CY8C24094 68-Pin OCD PSoC Device
20
21
22
M
M
M
M
M
M
M
M
M
M
M
M
P4[7]
P4[5]
P4[3]
P4[1]
OCDE
OCDO
VSS
P3[7]
P3[5]
P3[3]
P3[1]
P5[7]
P5[5]
P5[3]
P5[1]
P1[7]
P1[5]
P1[3]
P1[1]
VSS
D+
D–
VDD
P7[7]
P7[6]
P7[5]
P7[4]
P7[3]
P7[2]
P7[1]
P7[0]
P1[0]
P1[2]
P1[4]
P1[6]
P5[0]
P5[2]
P5[4]
P5[6]
P3[0]
P3[2]
P3[4]
P3[6]
Description
68
67
Power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Power
USB
USB
Power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Name
18
19
Type
Digital Analog
I/O
M
I/O
M
I/O
M
I/O
M
M, P1[3]
I2C SCL, M, P1[1]
Vss
D+
DVdd
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
Direct switched capacitor block input
Direct switched capacitor block input
External AGND input
External VREF input
Analog column mux input
Analog column mux input and column output
Analog column mux input and column output
Analog column mux input
Supply voltage
Ground connection [13]
Analog column mux input, integration input #1
Analog column mux input and column output, integration
input #2
Analog column mux input and column output
Analog column mux input
Direct switched capacitor block input
Direct switched capacitor block input
Notes
12. The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it
should be electrically floated and not connected to any other signal.
13. All VSS pins should be brought out to one common GND plane.
14. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.
Document Number: 38-12018 Rev. AN
Page 12 of 72
CY8C24094/CY8C24794
CY8C24894/CY8C24994
100-Ball VFBGA Part Pinout
The 100-ball VFBGA part is for the CY8C24994 PSoC device.
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
B1
B2
B3
B4
B5
B6
B7
B8
B9
B10
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
E1
E2
E3
E4
E5
E6
E7
E8
E9
E10
Power
Power
Power
Power
Power
Power
Power
I/O
I, M
I/O
I, M
I/O
I, M
Power
I/O
I, M
I/O
I, M
Power
Power
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
I/O, M
I, M
I, M
I, M
M
M
M
M
I/O, M
I,M
M
M
M
I/O
M
I/O
I, M
Power
Power
I/O
M
I/O
M
I/O
M
VSS
VSS
NC
NC
NC
VDD
NC
NC
VSS
VSS
VSS
VSS
P2[1]
P0[1]
P0[7]
VDD
P0[2]
P2[2]
VSS
VSS
NC
P4[1]
P4[7]
P2[7]
P0[5]
P0[6]
P0[0]
P2[0]
P4[2]
NC
NC
P3[7]
P4[5]
P2[5]
P0[3]
P0[4]
P2[6]
P4[6]
P4[0]
NC
NC
NC
P4[3]
P2[3]
VSS
VSS
P2[4]
P4[4]
P3[6]
NC
Description
Ground connection
Ground connection
No connection. Pin must be left floating
No connection. Pin must be left floating
No connection. Pin must be left floating
Supply voltage
No connection. Pin must be left floating
No connection. Pin must be left floating
Ground connection
Ground connection
Ground connection
Ground connection
Direct switched capacitor block input
Analog column mux input
Analog column mux input
Supply voltage
Analog column mux input
Direct switched capacitor block input
Ground connection
Ground connection
No connection. Pin must be left floating
Analog column mux input and column output
Analog column mux input
Analog column mux input
Direct switched capacitor block input
No connection. Pin must be left floating
No connection. Pin must be left floating
Analog column mux input and column output
Analog column mux input
External VREF input
No connection. Pin must be left floating
No connection. Pin must be left floating
No connection. Pin must be left floating
Direct switched capacitor block input
Ground connection
Ground connection
External AGND input
No connection. Pin must be left floating
Pin
No.
F1
F2
F3
F4
F5
F6
F7
F8
F9
F10
G1
G2
G3
G4
G5
G6
G7
G8
G9
G10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
J1
J2
J3
J4
J5
J6
J7
J8
J9
J10
K1
K2
K3
K4
K5
K6
K7
K8
K9
K10
Analog
Name
Digital
Analog
Pin
No.
Digital
Table 6. 100-Ball Part Pinout (VFBGA[15])
I/O
M
I/O
M
I/O
M
Power
Power
I/O
M
I/O
M
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
M
M
M
M
M
M
M
M
I/O
M
I/O
M
I/O
M
I/O
M
I/O
M
I/O
M
I/O
M
I/O
M
I/O
Power
Power
USB
USB
Power
I/O
I/O
I/O
M
Power
Power
Power
Power
Power
I/O
I/O
I/O
Power
Power
Name
NC
P5[7]
P3[5]
P5[1]
VSS
VSS
P5[0]
P3[0]
XRES
P7[1]
NC
P5[5]
P3[3]
P1[7]
P1[1]
P1[0]
P1[6]
P3[4]
P5[6]
P7[2]
NC
P5[3]
P3[1]
P1[5]
P1[3]
P1[2]
P1[4]
P3[2]
P5[4]
P7[3]
VSS
VSS
D+
D–
VDD
P7[7]
P7[0]
P5[2]
VSS
VSS
VSS
VSS
NC
NC
VDD
P7[6]
P7[5]
P7[4]
VSS
VSS
Description
No connection. Pin must be left floating
Ground connection
Ground connection
Active high pin reset with internal pull-down
No connection. Pin must be left floating
I2C SCL
I2C SCL, ISSP SCLK[16]
I2C SDA, ISSP SDATA[16]
No connection. Pin must be left floating
I2C SDA
Optional EXTCLK
Ground connection
Ground connection
Supply voltage
Ground connection
Ground connection
Ground connection
Ground connection
No connection. Pin must be left floating
No connection. Pin must be left floating
Supply voltage
Ground connection
Ground connection
LEGEND A = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No connection. Pin must be left floating.
Notes
15. All VSS pins should be brought out to one common GND plane.
16. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.
Document Number: 38-12018 Rev. AN
Page 13 of 72
CY8C24094/CY8C24794
CY8C24894/CY8C24994
Figure 8. CY8C24094 OCD (Not for Production)
1
2
3
4
5
6
7
8
9
10
A
Vss
Vss
NC
NC
NC
Vdd
NC
NC
Vss
Vss
B
Vss
Vss
P2[1]
P0[1]
P0[7]
Vdd
P0[2]
P2[2]
Vss
Vss
C
NC
P4[1]
P4[7]
P2[7]
P0[5]
P0[6]
P0[0]
P2[0]
P4[2]
NC
D
NC
P3[7]
P4[5]
P2[5]
P0[3]
P0[4]
P2[6]
P4[6]
P4[0]
NC
E
NC
NC
P4[3]
P2[3]
Vss
Vss
P2[4]
P4[4]
P3[6]
NC
F
NC
P5[7]
P3[5]
P5[1]
Vss
Vss
P5[0]
P3[0]
XRES
P7[1]
G
NC
P5[5]
P3[3]
P1[7]
P1[1]
P1[0]
P1[6]
P3[4]
P5[6]
P7[2]
H
NC
P5[3]
P3[1]
P1[5]
P1[3]
P1[2]
P1[4]
P3[2]
P5[4]
P7[3]
J
Vss
Vss
D+
D-
Vdd
P7[7]
P7[0]
P5[2]
Vss
Vss
K
Vss
Vss
NC
NC
Vdd
P7[6]
P7[5]
P7[4]
Vss
Vss
BGA (Top View)
Document Number: 38-12018 Rev. AN
Page 14 of 72
CY8C24094/CY8C24794
CY8C24894/CY8C24994
100-Ball VFBGA Part Pinout (On-Chip Debug)
The following 100-pin VFBGA part table and drawing is for the CY8C24094 OCD PSoC device.
Note This part is only used for in-circuit debugging. It is NOT available for production.
Description
Pin
No.
Analog
Name
Digital
Analog
Pin
No.
Digital
Table 7. 100-Ball Part Pinout (VFBGA[17])
Name
Description
A1
Power
VSS
Ground connection
F1
OCDE OCD even data I/O
A2
Power
VSS
Ground connection
F2
I/O
M
P5[7]
A3
NC
No connection. Pin must be left floating
F3
I/O
M
P3[5]
A4
NC
No connection. Pin must be left floating
F4
I/O
M
P5[1]
A5
NC
No connection. Pin must be left floating.
F5
Power
VSS
Ground connection
A6
Power
VDD
Supply voltage.
F6
Power
VSS
Ground connection
A7
NC
No connection. Pin must be left floating.
F7
I/O
M
P5[0]
A8
NC
No connection. Pin must be left floating.
F8
I/O
M
P3[0]
A9
Power
VSS
Ground connection
F9
XRES
Active high pin reset with internal pull-down
A10 Power
VSS
Ground connection
F10 I/O
P7[1]
B1
Power
VSS
Ground connection
G1
OCDO OCD odd data output
B2
Power
VSS
Ground connection
G2
I/O
M
P5[5]
B3
I/O
I, M
P2[1]
Direct switched capacitor block input
G3
I/O
M
P3[3]
B4
I/O
I, M
P0[1]
Analog column mux input
G4
I/O
M
P1[7]
I2C SCL
B5
I/O
I, M
P0[7]
Analog column mux input
G5
I/O
M
P1[1]
I2C SCL, ISSP SCLK[18]
B6
Power
VDD
Supply voltage
G6
I/O
M
P1[0]
I2C SDA, ISSP SDATA[18]
B7
I/O
I, M
P0[2]
Analog column mux input
G7
I/O
M
P1[6]
B8
I/O
I, M
P2[2]
Direct switched capacitor block input
G8
I/O
M
P3[4]
B9
Power
VSS
Ground connection
G9
I/O
M
P5[6]
B10 Power
VSS
Ground connection
G10 I/O
P7[2]
C1
NC
No connection. Pin must be left floating
H1
NC
No connection. Pin must be left floating
C2
I/O
M
P4[1]
H2
I/O
M
P5[3]
C3
I/O
M
P4[7]
H3
I/O
M
P3[1]
C4
I/O
M
P2[7]
H4
I/O
M
P1[5]
I2C SDA
C5
I/O
I/O,M P0[5]
Analog column mux input and column output
H5
I/O
M
P1[3]
C6
I/O
I, M
P0[6]
Analog column mux input
H6
I/O
M
P1[2]
C7
I/O
I, M
P0[0]
Analog column mux input
H7
I/O
M
P1[4]
Optional EXTCLK
C8
I/O
I, M
P2[0]
Direct switched capacitor block input
H8
I/O
M
P3[2]
C9
I/O
M
P4[2]
H9
I/O
M
P5[4]
C10
NC
No connection. Pin must be left floating
H10 I/O
P7[3]
D1
NC
No connection. Pin must be left floating
J1
Power
VSS
Ground connection
D2
I/O
M
P3[7]
J2
Power
VSS
Ground connection
D3
I/O
M
P4[5]
J3
USB
D+
D4
I/O
M
P2[5]
J4
USB
DD5
I/O
I/O, M P0[3]
Analog column mux input and column output
J5
Power
VDD
Supply voltage
D6
I/O
I, M
P0[4]
Analog column mux input
J6
I/O
P7[7]
D7
I/O
M
P2[6]
External VREF input
J7
I/O
P7[0]
D8
I/O
M
P4[6]
J8
I/O
M
P5[2]
D9
I/O
M
P4[0]
J9
Power
VSS
Ground connection
D10
CCLK
OCD CPU clock output
J10 Power
VSS
Ground connection
E1
NC
No connection. Pin must be left floating
K1
Power
VSS
Ground connection
E2
NC
No connection. Pin must be left floating
K2
Power
VSS
Ground connection
E3
I/O
M
P4[3]
K3
NC
No connection. Pin must be left floating
E4
I/O
I, M
P2[3]
Direct switched capacitor block input
K4
NC
No connection. Pin must be left floating
E5
Power
VSS
Ground connection
K5
Power
VDD
Supply voltage
E6
Power
VSS
Ground connection
K6
I/O
P7[6]
E7
I/O
M
P2[4]
External AGND input
K7
I/O
P7[5]
E8
I/O
M
P4[4]
K8
I/O
P7[4]
E9
I/O
M
P3[6]
K9
Power
VSS
Ground connection
E10
HCLK
OCD high speed clock output
K10 Power
VSS
Ground connection
LEGEND A = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No connection. Pin must be left floating, OCD = On-Chip Debugger.
Notes
17. All VSS pins should be brought out to one common GND plane.
18. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.
Document Number: 38-12018 Rev. AN
Page 15 of 72
CY8C24094/CY8C24794
CY8C24894/CY8C24994
Figure 9. CY8C24094 OCD (Not for Production)
1
2
3
4
5
6
7
8
9
10
A
Vss
Vss
NC
NC
NC
Vdd
NC
NC
Vss
Vss
B
Vss
Vss
P2[1]
P0[1]
P0[7]
Vdd
P0[2]
P2[2]
Vss
Vss
C
NC
P4[1]
P4[7]
P2[7]
P0[5]
P0[6]
P0[0]
P2[0]
P4[2]
NC
D
NC
P3[7]
P4[5]
P2[5]
P0[3]
P0[4]
P2[6]
P4[6]
P4[0]
CClk
E
NC
NC
P4[3]
P2[3]
Vss
Vss
P2[4]
P4[4]
P3[6]
HClk
F
ocde
P5[7]
P3[5]
P5[1]
Vss
Vss
P5[0]
P3[0]
XRES
P7[1]
G
ocdo
P5[5]
P3[3]
P1[7]
P1[1]
P1[0]
P1[6]
P3[4]
P5[6]
P7[2]
H
NC
P5[3]
P3[1]
P1[5]
P1[3]
P1[2]
P1[4]
P3[2]
P5[4]
P7[3]
J
Vss
Vss
D+
D-
Vdd
P7[7]
P7[0]
P5[2]
Vss
Vss
K
Vss
Vss
NC
NC
Vdd
P7[6]
P7[5]
P7[4]
Vss
Vss
BGA (Top View)
Document Number: 38-12018 Rev. AN
Page 16 of 72
CY8C24094/CY8C24794
CY8C24894/CY8C24994
100-Pin Part Pinout (On-Chip Debug)
The 100-pin TQFP part is for the CY8C24094 OCD PSoC device.
Note: This part is only used for in-circuit debugging. It is NOT available for production.
Description
Pin
No.
Analog
Name
Digital
Analog
Pin
No.
Digital
Table 8. 100-Pin Part Pinout (TQFP[19])
Name
Description
1
NC
No connection. Pin must be left floating
51
I/O
M
P1[6]
2
NC
No connection. Pin must be left floating
52
I/O
M
P5[0]
3
I/O
I, M P0[1]
Analog column mux input
53
I/O
M
P5[2]
4
I/O
M
P2[7]
54
I/O
M
P5[4]
5
I/O
M
P2[5]
55
I/O
M
P5[6]
6
I/O
I, M P2[3]
Direct switched capacitor block input
56
I/O
M
P3[0]
7
I/O
I, M P2[1]
Direct switched capacitor block input
57
I/O
M
P3[2]
8
I/O
M
P4[7]
58
I/O
M
P3[4]
9
I/O
M
P4[5]
59
I/O
M
P3[6]
10
I/O
M
P4[3]
60
HCLK
OCD high speed clock output
11
I/O
M
P4[1]
61
CCLK
OCD CPU clock output
12
OCDE OCD even data I/O
62
Input
XRES
Active high pin reset with internal pull-down
13
OCDO OCD odd data output
63
I/O
M
P4[0]
14
NC
No connection. Pin must be left floating
64
I/O
M
P4[2]
15
Power
VSS
Ground connection
65
Power
VSS
Ground connection
16
I/O
M
P3[7]
66
I/O
M
P4[4]
17
I/O
M
P3[5]
67
I/O
M
P4[6]
18
I/O
M
P3[3]
68
I/O
I, M
P2[0]
Direct switched capacitor block input
19
I/O
M
P3[1]
69
I/O
I, M
P2[2]
Direct switched capacitor block input
20
I/O
M
P5[7]
70
I/O
P2[4]
External AGND input
21
I/O
M
P5[5]
71
NC
No connection. Pin must be left floating
22
I/O
M
P5[3]
72
I/O
P2[6]
External VREF input
23
I/O
M
P5[1]
73
NC
No connection. Pin must be left floating
24
I/O
M
P1[7]
I2C SCL
74
I/O
I
P0[0]
Analog column mux input
25
NC
No connection. Pin must be left floating
75
NC
No connection. Pin must be left floating
26
NC
No connection. Pin must be left floating
76
NC
No connection. Pin must be left floating
27
NC
No connection. Pin must be left floating
77
I/O
I, M
P0[2]
Analog column mux input and column output
28
I/O
P1[5]
I2C SDA
78
NC
No connection. Pin must be left floating
29
I/O
P1[3]
79
I/O
I, M
P0[4]
Analog column mux input and column output
30
I/O
P1[1]
Crystal (XTALin), I2C SCL, ISSP SCLK[20]
80
NC
No connection. Pin must be left floating
31
NC
No connection. Pin must be left floating
81
I/O
I, M
P0[6]
Analog column mux input
32
Power
VSS
Ground connection
82
Power
VDD
Supply voltage
33
USB
D+
83
NC
No connection. Pin must be left floating
34
USB
D84
Power
VSS
Ground connection
35
Power
VDD
Supply voltage
85
NC
No connection. Pin must be left floating
36
I/O
P7[7]
86
NC
No connection. Pin must be left floating
37
I/O
P7[6]
87
NC
No connection. Pin must be left floating
38
I/O
P7[5]
88
NC
No connection. Pin must be left floating
39
I/O
P7[4]
89
NC
No connection. Pin must be left floating
40
I/O
P7[3]
90
NC
No connection. Pin must be left floating
41
I/O
P7[2]
91
NC
No connection. Pin must be left floating
42
I/O
P7[1]
92
NC
No connection. Pin must be left floating
43
I/O
P7[0]
93
NC
No connection. Pin must be left floating
44
NC
No connection. Pin must be left floating
94
NC
No connection. Pin must be left floating
45
NC
No connection. Pin must be left floating
95
I/O
I, M
P0[7]
Analog column mux input
46
NC
No connection. Pin must be left floating
96
NC
No connection. Pin must be left floating
47
NC
No connection. Pin must be left floating
97
I/O
I/O, M P0[5]
Analog column mux input and column output
48
I/O
P1[0]
Crystal (XTALout), I2C SDA, ISSP SDATA[20]
98
NC
No connection. Pin must be left floating
49
I/O
P1[2]
99
I/O
I/O, M P0[3]
Analog column mux input and column output
50
I/O
P1[4]
Optional EXTCLK
100
NC
No connection. Pin must be left floating
LEGEND A = Analog, I = Input, O = Output, NC = No connection. Pin must be left floating, M = Analog Mux Input, OCD = On-Chip Debugger.
Notes
19. All VSS pins should be brought out to one common GND plane.
20. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.
Document Number: 38-12018 Rev. AN
Page 17 of 72
CY8C24094/CY8C24794
CY8C24894/CY8C24994
Document Number: 38-12018 Rev. AN
NC
P0[2], M, AI
NC
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
P0[0], M , AI
NC
P2[6], M , External VREF
NC
P2[4], M , External AGND
P2[2], M , AI
P2[0], M , AI
P4[6], M
P4[4], M
Vss
P4[2], M
P4[0], M
XRES
CCLK
HCLK
P3[6], M
P3[4], M
P3[2], M
P3[0], M
P5[6], M
P5[4], M
P5[2], M
P5[0], M
P1[6], M
M, P1[2]
EXTCLK, M, P1[4]
46
47
48
49
50
P7[1]
P7[0]
NC
NC
NC
NC
I2C SDA, M, P1[0]
P7[3]
P7[2]
36
37
38
39
40
41
42
43
44
45
P7[7]
P7[6]
P7[5]
P7[4]
31
32
33
34
35
77
76
80
79
78
NC
Vdd
P0[6], M, AI
NC
P0[4], M, AI
NC
NC
Vss
87
86
85
84
83
82
81
90
89
88
NC
NC
NC
NC
NC
NC
NC
NC
P0[7], M, AI
NC
95
94
93
92
91
P0[3], M, AI
NC
P0[5], M, AI
98
97
96
28
29
30
26
27
TQFP
NC
I2C SDA, M, P1[5]
M, P1[3]
I2C SCL, M, P1[1]
NC
Vss
D+
DVdd
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
NC
NC
NC
AI, M , P0[1]
M , P2[7]
M , P2[5]
AI, M , P2[3]
AI, M , P2[1]
M , P4[7]
M , P4[5]
M , P4[3]
M , P4[1]
OCDE
OCDO
NC
Vss
M , P3[7]
M , P3[5]
M , P3[3]
M , P3[1]
M , P5[7]
M , P5[5]
M , P5[3]
M , P5[1]
I2C SCL, P1[7]
NC
100
99
NC
Figure 10. CY8C24094 OCD (Not for Production)
Page 18 of 72
CY8C24094/CY8C24794
CY8C24894/CY8C24994
Register Reference
This section lists the registers of the CY8C24x94 PSoC device family. For detailed register information, see the
PSoC Technical Reference Manual.
Register Conventions
Register Mapping Tables
The register conventions specific to this section are listed in the
following table.
The PSoC device has a total register address space of
512 bytes. The register space is referred to as I/O space and is
divided into two banks, Bank 0 and Bank 1. The XOI bit in the
Flag register (CPU_F) determines which bank the user is
currently in. When the XOI bit is set to 1, the user is in Bank 1.
Convention
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Document Number: 38-12018 Rev. AN
Note: In the following register mapping tables, blank fields are
Reserved and should not be accessed.
Page 19 of 72
CY8C24094/CY8C24794
CY8C24894/CY8C24994
Register Map Bank 0 Table: User Space
Name
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
PRT4DR
PRT4IE
PRT4GS
PRT4DM2
PRT5DR
PRT5IE
PRT5GS
PRT5DM2
Addr (0, Hex) Access
Name
00
RW
PMA0_DR
01
RW
PMA1_DR
02
RW
PMA2_DR
03
RW
PMA3_DR
04
RW
PMA4_DR
05
RW
PMA5_DR
06
RW
PMA6_DR
07
RW
PMA7_DR
08
RW
USB_SOF0
09
RW
USB_SOF1
0A
RW
USB_CR0
0B
RW
USBI/O_CR0
0C
RW
USBI/O_CR1
0D
RW
0E
RW
EP1_CNT1
0F
RW
EP1_CNT
10
RW
EP2_CNT1
11
RW
EP2_CNT
12
RW
EP3_CNT1
13
RW
EP3_CNT
14
RW
EP4_CNT1
15
RW
EP4_CNT
16
RW
EP0_CR
17
RW
EP0_CNT
18
EP0_DR0
19
EP0_DR1
1A
EP0_DR2
1B
EP0_DR3
PRT7DR
1C
RW
EP0_DR4
PRT7IE
1D
RW
EP0_DR5
PRT7GS
1E
RW
EP0_DR6
PRT7DM2
1F
RW
EP0_DR7
DBB00DR0
20
#
AMX_IN
DBB00DR1
21
W
AMUXCFG
DBB00DR2
22
RW
DBB00CR0
23
#
ARF_CR
DBB01DR0
24
#
CMP_CR0
DBB01DR1
25
W
ASY_CR
DBB01DR2
26
RW
CMP_CR1
DBB01CR0
27
#
DCB02DR0
28
#
DCB02DR1
29
W
DCB02DR2
2A
RW
DCB02CR0
2B
#
DCB03DR0
2C
#
TMP_DR0
DCB03DR1
2D
W
TMP_DR1
DCB03DR2
2E
RW
TMP_DR2
DCB03CR0
2F
#
TMP_DR3
30
ACB00CR3
31
ACB00CR0
32
ACB00CR1
33
ACB00CR2
34
ACB01CR3
35
ACB01CR0
36
ACB01CR1
37
ACB01CR2
38
39
3A
3B
3C
3D
3E
3F
Blank fields are reserved and should not be accessed.
Document Number: 38-12018 Rev. AN
Addr (0, Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
RW
RW
RW
RW
RW
RW
RW
RW
R
R
RW
#
RW
#
RW
#
RW
#
RW
#
RW
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
Addr (0, Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
ASD20CR0
90
ASD20CR1
91
ASD20CR2
92
ASD20CR3
93
ASC21CR0
94
ASC21CR1
95
ASC21CR2
96
ASC21CR3
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
MUL1_X
A8
MUL1_Y
A9
MUL1_DH
AA
MUL1_DL
AB
ACC1_DR1
AC
ACC1_DR0
AD
ACC1_DR3
AE
ACC1_DR2
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
# Access is bit specific.
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
W
W
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
CUR_PP
STK_PP
IDX_PP
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR2
INT_CLR3
INT_MSK3
INT_MSK2
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL0_X
MUL0_Y
MUL0_DH
MUL0_DL
ACC0_DR1
ACC0_DR0
ACC0_DR3
ACC0_DR2
CPU_F
DAC_D
CPU_SCR1
CPU_SCR0
Addr (0, Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
RW
RW
RW
RW
RW
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
RL
RW
#
#
Page 20 of 72
CY8C24094/CY8C24794
CY8C24894/CY8C24994
Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
PRT3DM0
PRT3DM1
PRT3IC0
PRT3IC1
PRT4DM0
PRT4DM1
PRT4IC0
PRT4IC1
PRT5DM0
PRT5DM1
PRT5IC0
PRT5IC1
Addr (1, Hex) Access
Name
00
RW
PMA0_WA
01
RW
PMA1_WA
02
RW
PMA2_WA
03
RW
PMA3_WA
04
RW
PMA4_WA
05
RW
PMA5_WA
06
RW
PMA6_WA
07
RW
PMA7_WA
08
RW
09
RW
0A
RW
0B
RW
0C
RW
0D
RW
0E
RW
0F
RW
10
RW
PMA0_RA
11
RW
PMA1_RA
12
RW
PMA2_RA
13
RW
PMA3_RA
14
RW
PMA4_RA
15
RW
PMA5_RA
16
RW
PMA6_RA
17
RW
PMA7_RA
18
19
1A
1B
PRT7DM0
1C
RW
PRT7DM1
1D
RW
PRT7IC0
1E
RW
PRT7IC1
1F
RW
DBB00FN
20
RW
CLK_CR0
DBB00IN
21
RW
CLK_CR1
DBB00OU
22
RW
ABF_CR0
23
AMD_CR0
DBB01FN
24
RW
CMP_GO_EN
DBB01IN
25
RW
DBB01OU
26
RW
AMD_CR1
27
ALT_CR0
DCB02FN
28
RW
DCB02IN
29
RW
DCB02OU
2A
RW
2B
DCB03FN
2C
RW
TMP_DR0
DCB03IN
2D
RW
TMP_DR1
DCB03OU
2E
RW
TMP_DR2
2F
TMP_DR3
30
ACB00CR3
31
ACB00CR0
32
ACB00CR1
33
ACB00CR2
34
ACB01CR3
35
ACB01CR0
36
ACB01CR1
37
ACB01CR2
38
39
3A
3B
3C
3D
3E
3F
Blank fields are reserved and should not be accessed.
Document Number: 38-12018 Rev. AN
Addr (1, Hex)
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
Addr (1, Hex)
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
ASD20CR1
91
ASD20CR2
92
ASD20CR3
93
ASC21CR0
94
ASC21CR1
95
ASC21CR2
96
ASC21CR3
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
RDI0RI
B0
RDI0SYN
B1
RDI0IS
B2
RDI0LT0
B3
RDI0LT1
B4
RDI0RO0
B5
RDI0RO1
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
# Access is bit specific.
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Name
USBI/O_CR2
USB_CR1
Addr (1, Hex) Access
C0
RW
C1
#
EP1_CR0
EP2_CR0
EP3_CR0
EP4_CR0
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
GDI_O_IN
GDI_E_IN
GDI_O_OU
GDI_E_OU
MUX_CR0
MUX_CR1
MUX_CR2
MUX_CR3
OSC_GO_EN
OSC_CR4
OSC_CR3
OSC_CR0
OSC_CR1
OSC_CR2
VLT_CR
VLT_CMP
IMO_TR
ILO_TR
BDG_TR
ECO_TR
MUX_CR4
MUX_CR5
RW
RW
RW
RW
RW
RW
RW
CPU_F
DAC_CR
CPU_SCR1
CPU_SCR0
#
#
#
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
R
W
W
RW
W
RW
RW
RL
RW
#
#
Page 21 of 72
CY8C24094/CY8C24794
CY8C24894/CY8C24994
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C24x94 PSoC device family. For the most up-to-date electrical
specifications, confirm that you have the most recent datasheet by visiting http://www.cypress.com.
Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications for devices when used in USB
applications with IMO > 12 MHz and VDD = 3.3 V are valid for –40 °C
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