CY8C24423-24PVI

CY8C24123 CY8C24223, CY8C24423 PSoC® Programmable System-on-Chip™ Features ■ ■ Powerful Harvard Architecture Processor ❐ M8C Processor Speeds to 24 MHz ❐ 8x8 Multiply, 32-Bit Accumulate ❐ Low Power at High Speed ❐ 3.0 to 5.25 V Operating Voltage ❐ Operating Voltages Down to 1.0V Using On-Chip Switch Mode Pump (SMP) ❐ Industrial Temperature Range: -40°C to +85°C Advanced Peripherals (PSoC Blocks) ❐ Six Rail-to-Rail Analog PSoC Blocks Provide: • Up to 14-Bit ADCs • Up to 8-Bit DACs • Programmable Gain Amplifiers • Programmable Filters and Comparators ❐ Four Digital PSoC Blocks Provide: • 8 to 32-Bit Timers, Counters, and PWMs • CRC and PRS Modules • Full-Duplex UART • Multiple SPI™ Masters or Slaves • Connectable to all GPIO Pins ❐ Complex Peripherals by Combining Blocks Precision, Programmable Clocking ❐ Internal ± 2.5% 24/48 MHz Oscillator ❐ High-Accuracy 24 MHz with Optional 32 kHz Crystal and PLL ❐ Optional External Oscillator, up to 24 MHz ❐ Internal Oscillator for Watchdog and Sleep Flexible On-Chip Memory ❐ 4K Bytes Flash Program Storage 50,000 Erase/Write Cycles ❐ 256 Bytes SRAM Data Storage ❐ In-System Serial Programming (ISSP™) ❐ Partial Flash Updates ❐ Flexible Protection Modes ❐ EEPROM Emulation in Flash Programmable Pin Configurations ❐ 25 mA Sink on all GPIO ❐ Pull up, Pull down, High Z, Strong, or Open Drain Drive Modes on all GPIO ❐ Up to 10 Analog Inputs on GPIO ❐ Two 30 mA Analog Outputs on GPIO ❐ Configurable Interrupt on all GPIO Additional System Resources 2 ❐ I C™ Slave, Master, and Multi-Master to 400 kHz ❐ Watchdog and Sleep Timers ❐ User-Configurable Low Voltage Detection ❐ Integrated Supervisory Circuit ❐ On-Chip Precision Voltage Reference Complete Development Tools ❐ Free Development Software (PSoC Designer™) ❐ Full-Featured, In-Circuit Emulator and Programmer ❐ Full Speed Emulation ❐ Complex Breakpoint Structure ❐ 128K Bytes Trace Memory ■ ■ Logic Block Diagram Port 2 Port 1 Port 0 Analog Drivers PSoC CORE System Bus Global Digital Interconnect SRAM 256 Bytes Interrupt Controller Global Analog Interconnect Flash 4K Sleep and Watchdog ■ SROM CPU Core (M8C) Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) ■ DIGITAL SYSTEM Digital Block Array (1 Rows, 4 Blocks) ANALOG SYSTEM Analog Block Array (2 Columns, 6 Blocks) Analog Ref ■ Analog Input Muxing Digital Clocks Multiply Accum. POR and LVD Decimator I2C System Resets Internal Voltage Ref. Switch Mode Pump SYSTEM RESOURCES Cypress Semiconductor Corporation Document Number: 38-12011 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised December 11, 2008 [+] Feedback CY8C24123 CY8C24223, CY8C24423 PSoC® Functional Overview The PSoC® family consists of many Mixed Signal Array with On-Chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, and programmable interconnects. This architecture allows the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable IO are included in a range of convenient pinouts and packages. The PSoC architecture, as shown in the Logic Block Diagram on page 1, is comprised of four main areas: PSoC Core, Digital System, Analog System, and System Resources. Configurable global busing allows all the device resources to be combined into a complete custom system. The PSoC CY8C24x23 family can have up to three IO ports that connect to the global digital and analog interconnects, providing access to four digital blocks and 6 analog blocks. Digital System The Digital System is composed of four digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Figure 1. Digital System Block Diagram Port 2 Port 1 Port 0 Digital Clocks From Core To System Bus To Analog System DIGITAL SYSTEM Digital PSoC Block Array Row Input Configuration 8 8 Row 0 DBB00 DBB01 DCB02 4 DCB03 4 8 8 Row Output Configuration PSoC Core The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO). The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with 11 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT). Memory encompasses 4 KB of Flash for program storage, 256 bytes of SRAM for data storage, and up to 2 KB of EEPROM emulated using the Flash. Program Flash uses four protection levels on blocks of 64 bytes, allowing customized software IP protection. The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to 2.5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. PSoC GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] Digital peripheral configurations include: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ PWMs (8 to 32 bit) PWMs with Dead band (8 to 32 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) UART 8-bit with selectable parity (up to one) SPI master and slave (up to one) I2C slave and master (one available as a System Resource) Cyclical Redundancy Checker/Generator (8 to 32 bit) IrDA (up to one) Pseudo Random Sequence Generators (8 to 32 bit) The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows the optimum choice of system resources for your application. Family resources are listed in the table PSoC Device Characteristics on page 4. Document Number: 38-12011 Rev. *G Page 2 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Analog System The Analog System is composed of six configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Figure 2. Analog System Block Diagram P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6] P0[4] P0[2] P0[0] P2[6] Analog-to-digital converters (up to two, with 6 to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR) Filters (two and four pole band-pass, low-pass, and notch) Amplifiers (up to two, with selectable gain to 48x) Instrumentation amplifiers (one with selectable gain to 93x) Comparators (up to two, with 16 selectable thresholds) DACs (up to two, with 6 to 9-bit resolution) Multiplying DACs (up to two, with 6- to 9-bit resolution) High current output drivers (two with 30 mA drive as a Core Resource) 1.3V reference (as a System Resource) DTMF dialer Modulators Correlators Peak detectors Many other topologies possible P2[3] P2[4] P2[2] P2[0] P2[1] Array Input Configuration ACI0[1:0] ACI1[1:0] Block Array ACB00 ASC10 ASD20 ACB01 ASD11 ASC21 Analog blocks are provided in columns of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks. The number of blocks is dependant on the device family which is detailed in the table PSoC Device Characteristics on page 4. Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 38-12011 Rev. *G Page 3 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Additional System Resources System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, switch mode pump, low voltage detection, and power on reset. Brief statements describing the merits of each system resource follow: ■ Getting Started The quickest path to understanding the PSoC silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in-depth information, along with detailed programming information, refer the PSoC Programmable Sytem-on-Chip Technical Reference Manual. For up-to-date Ordering, Packaging, and Electrical Specification information, refer the latest PSoC device data sheets on the web at http://www.cypress.com/psoc. Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. A multiply accumulate (MAC) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in both general math and digital filters. The decimator provides a custom hardware filter for digital signal processing applications including the creation of Delta Sigma ADCs. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3V reference provides an absolute reference for the analog system, including ADCs and DACs. An integrated switch mode pump (SMP) generates normal operating voltages from a single 1.2V battery cell, providing a low cost boost converter. ■ Development Kits Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items. ■ ■ ■ Technical Training Free PSoC technical training is available for beginners and is taught by a marketing or application engineer over the phone. PSoC training classes cover designing, debugging, advanced analog, and application-specific classes covering topics, such as PSoC and the LIN bus. Go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select Technical Training for more details. ■ ■ PSoC Device Characteristics Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3 analog blocks. The following table lists the resources available for specific PSoC device groups. Table 1. PSoC Device Characteristics Analog Columns Analog Outputs Analog Inputs Analog Blocks PSoC Part Number Digital Blocks Digital IO Digital Rows Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select CYPros Consultants. Technical Support PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support. CY8C29x66 up to 4 64 CY8C27x66 up to 2 44 CY8C27x43 up to 2 44 CY8C24x23 up to 1 24 CY8C22x13 up to 1 16 16 8 8 4 4 12 12 12 12 8 4 4 4 2 1 4 4 4 2 1 12 12 12 6 3 Application Notes A long list of application notes can assist you in every aspect of your design effort. To view the PSoC application notes, go to the http://www.cypress.com web site and select Application Notes under the Design Resources list located in the center of the web page. Application notes are listed by date as default. Document Number: 38-12011 Rev. *G Page 4 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Development Tools The Cypress MicroSystems PSoC Designer is a Microsoft® Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE and application runs on Windows 98, Windows NT 4.0, Windows 2000, Windows Millennium (Me), or Windows XP (refer Figure 3). PSoC Designer helps the customer to select an operating configuration for the PSoC, write application code that uses the PSoC, and debug the application. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and the CYASM macro assembler for the CPUs. PSoC Designer also supports a high-level C language compiler developed specifically for the devices in the family. Figure 3. PSoC Designer Subsystems PSoC Designer Software Subsystems Device Editor The Device Editor subsystem allows the user to select different onboard analog and digital components called user modules using the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time. PSoC Designer sets up power on initialization tables for selected PSoC block configurations and creates source code for an application framework. The framework contains software to operate the selected components and, if the project uses more than one operating configuration, contains routines to switch between different sets of PSoC block configurations at run time. PSoC Designer can print out a configuration sheet for a given project configuration for use during application programming in conjunction with the Device Data Sheet. After the framework is generated, the user can add application-specific code to flesh out the framework. It is also possible to change the selected components and regenerate the framework. Design Browser The Design Browser allows users to select and import preconfigured designs into the user’s project. Users can easily browse a catalog of preconfigured designs to facilitate time-to-design. Examples provided in the tools include a 300-baud modem, LIN Bus master and slave, fan controller, and magnetic card reader. Application Editor PSoC TM D esigner Graphical Designer Interface Context Sensitive Help Commands Results Importable Design Database Device Database Application Database Project Database User Modules Library PSoC Configuration Sheet PSoCTM Designer Core Engine In the Application Editor you can edit your C language and Assembly language source code. You can also assemble, compile, link, and build. Assembler. The macro assembler allows the assembly code to be merged seamlessly with C code. The link libraries automatically use absolute addressing or can be compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compiler. A C language compiler is available that supports Cypress MicroSystems’ PSoC family devices. Even if you have never worked in the C language before, the product quickly allows you to create complete C programs for the PSoC family devices. The embedded, optimizing C compiler provides all the features of C tailored to the PSoC architecture. It comes complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Manufacturing Information File Emulation Pod In-Circuit Emulator Device Programmer Document Number: 38-12011 Rev. *G Page 5 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing the designer to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write IO registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. User Modules and the PSoC Development Process The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. Each block has several registers that determine its function and connectivity to other blocks, multiplexers, buses and to the IO pins. Iterative development cycles permit you to adapt the hardware as well as the software. This substantially lowers the risk of having to select a different part to meet the final design requirements. To speed the development process, the PSoC Designer Integrated Development Environment (IDE) provides a library of pre-built, pre-tested hardware peripheral functions, called “User Modules.” User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. The standard User Module library contains over 50 common peripherals such as ADCs, DACs Timers, Counters, UARTs, and other not-so common peripherals such as DTMF Generators and Bi-Quad analog filter sections. Each user module establishes the basic register settings that implement the selected function. It also provides parameters that allow you to tailor its precise configuration to your particular application. For example, a Pulse Width Modulator User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. User modules also provide tested software to cut your development time. The user module application programming interface (API) provides high-level functions to control and respond to hardware events at run-time. The API also provides optional interrupt service routines that you can adapt as needed. The API functions are documented in user module data sheets that are viewed directly in the PSoC Designer IDE. These data sheets explain the internal operation of the user module and provide performance specifications. Each data sheet describes the use of each user module parameter and documents the setting of each register controlled by the user module. The development process starts when you open a new project and bring up the Device Editor, a pictorial environment (GUI) for configuring the hardware. You pick the user modules you need for your project and map them onto the PSoC blocks with point-and-click simplicity. Next, you build signal chains by interconnecting user modules to each other and the IO pins. At this stage, you also configure the clock source connections and enter parameter values directly or by selecting values from drop-down menus. When you are ready to test the hardware configuration or move on to developing code for the project, you perform the “Generate Application” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high-level user module API functions. Hardware Tools In-Circuit Emulator A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of the parallel or USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. Figure 4. PSoC Development Tool Kit Document Number: 38-12011 Rev. *G Page 6 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Figure 5. User Module and Source Code Development Flows Document Conventions Acronyms Used The following table lists the acronyms that are used in this document. Table 2. Acronyms Acronym AC alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current ADC API CPU CT DAC DC Description Device Editor User Module Selection Placement and Parameter -ization Source Code Generator Generate Application Application Editor Project Manager Source Code Editor Build Manager EEPROM electrically erasable programmable read-only memory FSR Build All full scale range general purpose IO input/output imprecise power on reset least-significant bit low voltage detect most-significant bit program counter power on reset precision power on reset Programmable System-on-Chip pulse width modulator random access memory read only memory switched capacitor switch mode pump GPIO IO IPOR LSb Debugger Interface to ICE Storage Inspector Event & Breakpoint Manager LVD MSb PC POR PPOR The next step is to write your main program, and any sub-routines using PSoC Designer’s Application Editor subsystem. The Application Editor includes a Project Manager that allows you to open the project source code files (including all generated code files) from a hierarchal view. The source code editor provides syntax coloring and advanced edit features for both C and assembly language. File search capabilities include simple string searches and recursive “grep-style” patterns. A single mouse click invokes the Build Manager. It employs a professional-strength “makefile” system to automatically analyze all file dependencies and run the compiler and assembler as necessary. Project-level options control optimization strategies used by the compiler and linker. Syntax errors are displayed in a console window. Double clicking the error message takes you directly to the offending line of source code. When all is correct, the linker builds a ROM file image suitable for programming. The last step in the development process takes place inside the PSoC Designer’s Debugger subsystem. The Debugger downloads the ROM image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. PSoC® PWM RAM ROM SC SMP Units of Measure A units of measure table is located in the Electrical Specifications section. Table 7 on page 11 lists all the abbreviations used to measure the PSoC devices. Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal. Document Number: 38-12011 Rev. *G Page 7 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Pinouts The CY8C24x23 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, SMP, and XRES are not capable of Digital IO. 8-Pin Part Pinout Table 3. 8-Pin Part Pinout (PDIP, SOIC) Type Pin Pin No. Digital Analog Name 1 2 3 4 5 6 7 8 IO IO IO Power I I IO IO IO Power IO IO P0[5] P0[3] P1[1] Vss P1[0] P0[2] P0[4] Vdd Description Analog column mux input and column output Analog column mux input and column output Crystal Input (XTALin), I2C Serial Clock (SCL) Ground connection Crystal Output (XTALout), I2C Serial Data (SDA) Analog column mux input Analog column mux input Supply voltage Figure 6. CY8C24123 8-Pin PSoC Device AIO, P0[5] AIO, P0[3] I2C SCL, XTALin, P1[1] Vss 8 1 2 PDIP 7 3SOIC6 5 4 Vdd P0[4], AI P0[2], AI P1[0], XTALout, I2C SDA LEGEND: A = Analog, I = Input, and O = Output. 20-Pin Part Pinout Table 4. 20-Pin Part Pinout (PDIP, SSOP, SOIC) Type Pin Pin No. Digital Analog Name 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 IO IO IO IO Power IO IO IO IO Input I I I I IO IO IO IO Power IO IO IO IO Power I IO IO I P0[7] P0[5] P0[3] P0[1] SMP P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES Active high external reset with internal pull down P0[0] P0[2] P0[4] P0[6] Vdd Analog column mux input Analog column mux input Analog column mux input Analog column mux input Supply voltage Optional External Clock Input (EXTCLK) Crystal Input (XTALin), I2C Serial Clock (SCL) Ground connection Crystal Output (XTALout), I2C Serial Data (SDA) Description Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Switch Mode Pump (SMP) connection to external components required I2C Serial Clock (SCL I2C Serial Data (SDA) Figure 7. CY8C24223 20-Pin PSoC Device AI, P0[7] AIO, P0[5] AIO, P0[3] AI, P0[1] SMP I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 PDIP SSOP SOIC 20 19 18 17 16 15 14 13 12 11 Vdd P0[6], AI P0[4], AI P0[2], AI P0[0], AI XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA LEGEND: A = Analog, I = Input, and O = Output. Document Number: 38-12011 Rev. *G Page 8 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 28-Pin Part Pinout Table 5. 28-Pin Part Pinout (PDIP, SSOP, SOIC) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Type Pin Description Digital Analog Name IO I P0[7] Analog column mux input IO IO P0[5] Analog column mux input and column output IO IO P0[3] Analog column mux input and column output IO I P0[1] Analog column mux input. IO P2[7] IO P2[5] IO I P2[3] Direct switched capacitor block input IO I P2[1] Direct switched capacitor block input Power SMP Switch Mode Pump (SMP) connection to external components required IO P1[7] I2C Serial Clock (SCL) IO P1[5] I2C Serial Data (SDA) IO P1[3] IO P1[1] Crystal Input (XTALin), I2C Serial Clock (SCL) Power Vss Ground connection IO P1[0] Crystal Output (XTALout), I2C Serial Data (SDA) IO P1[2] IO P1[4] Optional External Clock Input (EXTCLK) IO P1[6] Input XRES Active high external reset with internal pull down IO I P2[0] Direct switched capacitor block input IO I P2[2] Direct switched capacitor block input IO P2[4] External Analog Ground (AGND) IO P2[6] External Voltage Reference (VRef) IO I P0[0] Analog column mux input IO I P0[2] Analog column mux input IO I P0[4] Analog column mux input IO I P0[6] Analog column mux input Power Vdd Supply voltage Figure 8. CY8C24423 28-Pin PSoC Device AI, P0[7] AIO, P0[5] AIO, P0[3] AI, P0[1] P2[7] P2[5] AI, P2[3] AI, P2[1] SMP I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PDIP SSOP SOIC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd P0[6], AI P0[4], AI P0[2], AI P0[0], AI P2[6], External VRef P2[4], External AGND P2[2], AI P2[0], AI XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA LEGEND: A = Analog, I = Input, and O = Output. Document Number: 38-12011 Rev. *G Page 9 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 32-Pin Part Pinout Table 6. 32-Pin Part Pinout (MLF*) Type Pin No. Digital Analog 1 IO 2 IO 3 IO I 4 IO I 5 Power 6 Power Pin Name P2[7] P2[5] P2[3] P2[1] Vss SMP Description Figure 9. CY8C24423 32-Pin PSoC Device P0[1], AI P0[3], AIO P0[5], AIO P0[7], AI Vdd P0[6], AI P2[7] P2[5] AI, P2[3] AI, P2[1] Vss SMP I2C SCL, P1[7] I2C SDA, P1[5] 1 2 3 4 5 6 7 8 P0[4], AI NC 24 23 22 21 20 19 18 17 P0[2], AI P0[0], AI P2[6], External VRef P2[4], External AGND P2[2], AI P2[0], AI XRES P1[6] 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Power IO IO IO Vss P1[0] P1[2] P1[4] Crystal Input (XTALin), I2C Serial Clock (SCL) Ground connection Crystal Output (XTALout), I2C Serial Data (SDA) Optional External Clock Input (EXTCLK) No connection. Do not use. IO Input IO IO IO IO IO IO IO IO Power IO IO IO IO I IO IO I I I I I I I NC P1[6] XRES Active high external reset with internal pull down P2[0] Direct switched capacitor block input P2[2] Direct switched capacitor block input P2[4] External Analog Ground (AGND) P2[6] External Voltage Reference (VRef) P0[0] Analog column mux input P0[2] Analog column mux input NC No connection. Do not use. P0[4] Analog column mux input P0[6] Analog column mux input Vdd Supply voltage P0[7] Analog column mux input P0[5] Analog column mux input and column output P0[3] Analog column mux input and column output P0[1] Analog column mux input LEGEND: A = Analog, I = Input, and O = Output. * The MLF package has a center pad that must be connected to the same ground as the Vss pin. Document Number: 38-12011 Rev. *G NC P1[3] I2C SCL, XTALin, P1[1] Vss I2C SDA, XTALout, P1[0] P1[2] EXTCLK, P1[4] NC 7 8 9 10 11 IO IO IO IO P1[7] P1[5] NC P1[3] P1[1] Direct switched capacitor block input Direct switched capacitor block input Ground connection Switch Mode Pump (SMP) connection to external components required I2C Serial Clock (SCL) I2C Serial Data (SDA) No connection. Do not use. 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 MLF (Top View) Page 10 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Register Reference This section lists the registers of the CY8C27xxx PSoC device by way of mapping tables, in offset order. For detailed register information, reference the PSoC Programmable System-on-Chip Technical Reference Manual. Register Mapping Tables The PSoC device has a total register address space of 512 bytes. The register space is also referred to as IO space and is broken into two parts. The XOI bit in the Flag register determines which bank the user is currently in. When the XOI bit is set, the user is said to be in the “extended” address space or the “configuration” registers. Note In the following register mapping tables, blank fields are Reserved and must not be accessed. Register Conventions Abbreviations Used The register conventions specific to this section are listed in the following table. Table 7. Abbreviations Convention RW R W L C # Description Read and write register or bit(s) Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific Document Number: 38-12011 Rev. *G Page 11 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Table 8. Register Map Bank 0 Table: User Space Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name Name Name Name Access PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F RW RW RW RW RW RW RW RW RW RW RW RW 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F RW RW RW RW RW RW RW RW C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F RW RW RW RW RW RW RW RW I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC INT_CLR3 INT_MSK3 DD DE DF INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL_X MUL_Y MUL_DH MUL_DL ACC_DR1 ACC_DR0 E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED RW RW RC W RC RC RW RW W W R R RW RW RW RW RW # RW # RW RW DBB00DR0 DBB00DR1 DBB00DR2 DBB00CR0 DBB01DR0 DBB01DR1 DBB01DR2 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 DCB03DR1 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D # W RW # # W RW # # W RW # # W AMX_IN 60 61 62 RW A0 A1 A2 ARF_CR CMP_CR0 ASY_CR CMP_CR1 63 64 65 66 67 68 69 6A 6B 6C 6D RW # # RW A3 A4 A5 A6 A7 A8 A9 AA AB AC AD # Access is bit specific. Blank fields are Reserved and must not be accessed. Document Number: 38-12011 Rev. *G Page 12 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Table 8. Register Map Bank 0 Table: User Space (continued) Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name Name Name Name Access DCB03DR2 DCB03CR0 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F RW # ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RDI0RI RDI0SYN RDI0IS RDI0LT0 RDIOLT1 RDI0RO0 RDI0RO1 AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. RW RW RW RW RW RW RW ACC_DR3 ACC_DR2 EE EF F0 F1 F2 F3 F4 F5 F6 RW RW CPU_F F7 F8 F9 FA FB FC FD RL CPU_SCR1 CPU_SCR0 FE FF # # Blank fields are Reserved and must not be accessed. Table 9. Register Map Bank 1 Table: Configuration Space Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 RW RW RW RW RW RW RW RW RW RW RW RW 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F RW RW RW RW RW RW RW RW C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 90 91 92 93 94 95 96 RW RW RW RW RW RW RW GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU D0 D1 D2 D3 D4 D5 D6 RW RW RW RW Blank fields are Reserved and must not be accessed. # Access is bit specific. Document Number: 38-12011 Rev. *G Page 13 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Table 9. Register Map Bank 1 Table: Configuration Space (continued) Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name Name 17 18 19 1A 1B 1C 1D 1E 1F DBB00FN DBB00IN DBB00OU 20 21 22 23 DBB01FN DBB01IN DBB01OU 24 25 26 27 DCB02FN DCB02IN DCB02OU 28 29 2A 2B DCB03FN DCB03IN DCB03OU 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Blank fields are Reserved and must not be accessed. 57 58 59 5A 5B 5C 5D 5E 5F RW RW RW CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 RW RW RW AMD_CR1 ALT_CR0 RW RW RW 60 61 62 63 64 65 66 67 68 69 6A 6B RW RW RW 6C 6D 6E 6F ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RW RW RW RW RW RW ASC21CR3 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RW D7 D8 D9 DA DB DC OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 IMO_TR ILO_TR BDG_TR ECO_TR E8 E9 EA EB EC ED EE EF W W RW W RW RW RW RW RW RW RW R RDI0RI RDI0SYN RDI0IS RDI0LT0 RDIOLT1 RDI0RO0 RDI0RO1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF RW RW RW RW RW RW RW CPU_F F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD CPU_SCR1 CPU_SCR0 FE FF # # RL # Access is bit specific. Document Number: 38-12011 Rev. *G Page 14 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C24x23 PSoC device. For latest electrical specifications, http://www.cypress.com. Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted. Specifications for devices running at greater than 12 MHz are valid for -40oC ≤ TA ≤ 70oC and TJ ≤ 82oC. Figure 10. Voltage versus Operating Frequency 5.25 4.75 Vdd Voltage 3.00 93 kHz CPU Frequency The following table lists the units of measure that are used in this section. Table 10. Units of Measure Symbol °C dB fF Hz KB Kbit kHz kΩ MHz MΩ μA μF μH μs μV μVrms Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm micro ampere micro farad micro henry microsecond micro volts micro volts root-mean-square Symbol μW mA ms mV nA ns nV W pA pF pp ppm ps sps s V Unit of Measure micro watts milli-ampere milli-second milli-volts nano ampere nanosecond nanovolts ohm pico ampere pico farad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts lid ng Va rati n pe io O Reg 12 MHz 24 MHz Document Number: 38-12011 Rev. *G Page 15 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 11. Absolute Maximum Ratings Symbol Description TSTG Storage Temperature TA Vdd VIO – IMIO IMAIO – – Min -55 Typ – – – – – – – – – Units Notes o C Higher storage temperatures reduce data retention time. o +85 C +6.0 V Vdd + 0.5 V Vdd + 0.5 V +50 mA +50 mA – 200 V mA Max +100 Ambient Temperature with Power Applied -40 Supply Voltage on Vdd Relative to Vss -0.5 DC Input Voltage Vss - 0.5 DC Voltage Applied to Tri-state Vss - 0.5 Maximum Current into any Port Pin -25 Maximum Current into any Port Pin Configured -50 as Analog Driver Static Discharge Voltage 2000 Latch-up Current – Operating Temperature Table 12. Operating Temperature Symbol Description TA Ambient Temperature TJ Junction Temperature Min -40 -40 Typ – – Max +85 +100 Units Notes oC oC The temperature rise from ambient to junction is package specific. See Thermal Impedances per Package on page 41. The user must limit the power consumption to comply with this requirement. Document Number: 38-12011 Rev. *G Page 16 of 43 [+] Feedback CY8C24123 CY8C24223, CY8C24423 DC Electrical Characteristics DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only or unless otherwise specified. Table 13. DC Chip-Level Specifications Symbol Description Vdd Supply Voltage IDD Supply Current Min 3.00 – Typ – 5 Max 5.25 8 Units Notes V mA Conditions are Vdd = 5.0V, 25 oC, CPU = 3 MHz, 48 MHz disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. mA Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3 MHz, 48 MHz = Disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. μA Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40 oC