Please note that Cypress is an Infineon Technologies Company.
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to offer the product to new and existing customers as part of the Infineon product
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Continuity of document content
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Infineon continues to support existing part numbers. Please continue to use the
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www.infineon.com
CY8C24533
PSoC® Programmable System-on-Chip™
Features
■
Powerful Harvard-architecture processor
❐ M8C processor speeds to 24 MHz
❐ 8 × 8 multiply, 32-bit accumulate
❐ Low power at high speed
❐ 3.0-V to 5.25-V operating voltage
❐ Industrial temperature range: –40 °C to +85 °C
■
Advanced peripherals (PSoC blocks)
❐ Four rail-to-rail analog PSoC blocks provide:
• Up to 14-bit ADCs
• Up to 8-bit DACs
• Programmable gain amplifiers
• Programmable filters and comparators
❐ Four digital PSoC blocks provide:
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width
modulators (PWMs)
• CRC and PRS modules
• Full-duplex UART
• Multiple SPI masters or slaves
• Connectable to all GPIO pins
❐ Complex peripherals by combining blocks
❐ High-speed 8-bit SAR ADC optimized for motor control
■
■
■
Complete development tools
❐ Free development software (PSoC Designer™)
❐ Full-featured in-circuit emulator (ICE) and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128-KB trace memory
Logic Block Diagram
Port 3
Global Digital Interconnect
SRAM
256 Bytes
■
Additional system resources
2
❐ I C slave, master, and multi-master to 400 kHz
❐ Watchdog and sleep timers
❐ User-configurable low-voltage detection
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
Cypress Semiconductor Corporation
Document Number: 001-14643 Rev. *L
•
198 Champion Court
SROM
Analog
Drivers
Global Analog Interconnect
Flash 8K
CPUCore (M8C)
Interrupt
Controller
Sleep and
Watchdog
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
DIGITAL SYSTEM
Digital
Block
Array
Flexible on-chip memory
❐ 8-KB flash program storage 50,000 erase/write cycles
❐ 256 bytes SRAM data storage
❐ In-system serial programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ EEPROM emulation in flash
Programmable pin configurations
❐ 25-mA sink on All GPIO
❐ Pull-up, pull-down, high Z, strong, or open drain drive modes
on all GPIO
❐ Up to eight analog inputs on GPIO plus two additional analog
inputs with restricted routing
❐ Two 30-mA analog outputs on GPIO
❐ Configurable interrupt on all GPIOs
Port 1 Port 0
System Bus
Precision, programmable clocking
❐ Internal ±5% 24-/48-MHz oscillator
❐ High accuracy 24 MHz with optional 32-kHz crystal and PLL
❐ Optional external oscillator, up to 24 MHz
❐ Internal oscillator for watchdog and sleep
■
Port 2
PSoC CORE
Analog
Block Array
2 Columns
4 Blocks
1 Row
4 Blocks
Digital
Clocks
Multiply
Accum.
ANALOG SYSTEM
SAR8 ADC
Decimator
I2C
Analog
Ref
Analog
Input
Muxing
POR and LVD
System Resets
Internal
Voltage
Ref.
SYSTEM RESOURCES
•
San Jose, CA 95134-1709
• 408-943-2600
Revised January 29, 2015
CY8C24533
Contents
Features ............................................................................ 1
Logic Block Diagram ........................................................ 1
Contents ............................................................................ 2
PSoC Functional Overview .............................................. 3
PSoC Core .................................................................. 3
Digital System ................................................................... 3
Analog System ................................................................. 4
Additional System Resources ..................................... 5
PSoC Device Characteristics ...................................... 5
Getting Started ................................................................. 6
Application Notes ........................................................ 6
Development Kits ........................................................ 6
Training ....................................................................... 6
CYPros Consultants .................................................... 6
Solutions Library ......................................................... 6
Technical Support ....................................................... 6
Development Tools .......................................................... 7
PSoC Designer Software Subsystems ........................ 7
Designing with PSoC Designer ....................................... 8
Select User Modules ................................................... 8
Configure User Modules ............................................. 8
Organize and Connect ................................................ 8
Generate, Verify, and Debug ...................................... 8
Pinouts .............................................................................. 9
28-Pin Part Pinout ....................................................... 9
Register Reference ......................................................... 10
Register Conventions .................................................... 10
Document Number: 001-14643 Rev. *L
Abbreviations Used ................................................... 10
Register Mapping Tables ............................................... 10
Electrical Specifications ................................................ 13
Absolute Maximum Ratings ...................................... 14
Operating Temperature ............................................. 14
DC Electrical Characteristics .................................... 15
AC Electrical Characteristics ..................................... 28
Packaging Information .................................................. 38
Thermal Impedances ................................................ 38
Solder Reflow Peak Temperature ............................. 38
Ordering Information ..................................................... 39
Ordering Code Definitions ......................................... 39
Acronyms ........................................................................ 40
Acronyms Used ......................................................... 40
Reference Documents ................................................... 40
Document Conventions ................................................. 41
Units of Measure ....................................................... 41
Numeric Conventions ................................................ 41
Glossary .......................................................................... 42
Document History Page. ................................................ 47
Sales, Solutions, and Legal Information ...................... 48
Worldwide Sales and Design Support ...................... 48
Products .................................................................... 48
PSoC® Solutions ...................................................... 48
Page 2 of 48
CY8C24533
PSoC Functional Overview
Digital System
The PSoC family consists of many programmable systemon-chips with on-chip controller devices. These devices are
designed to replace multiple traditional MCU-based system
components with one, low-cost single-chip programmable
device. PSoC devices include configurable blocks of analog and
digital logic, and programmable interconnects. This architecture
allows the user to create customized peripheral configurations
that match the requirements of each individual application.
Additionally, a fast central processing unit (CPU), flash program
memory, SRAM data memory, and configurable I/O are included
in a range of convenient pinouts and packages.
The digital system is composed of 4 digital PSoC blocks. Each
block is an 8-bit resource that can be used alone or combined
with other blocks to form 8-, 16-, 24-, and 32-bit peripherals,
which are called user module references.
Figure 1. Digital System Block Diagram
Port 3
8
Document Number: 001-14643 Rev. *L
Row Input
Configuration
8
Row 0
DBB00
DBB01
DCB02
4
DCB03
4
GIE[7:0]
GIO[7:0]
Global Digital
Interconnect
Row Output
Configuration
PSoC GPIOs provide connection to the CPU, digital and analog
resources of the device. Each pin’s drive mode may be selected
from eight options, allowing great flexibility in external
interfacing. Every pin also has the capability to generate a
system interrupt on high level, low level, and change from last
read.
ToAnalog
System
DIGITAL SYSTEM
The PSoC core is a powerful engine that supports a rich feature
set. The core includes a CPU, memory, clocks, and configurable
general purpose I/O (GPIO).
The PSoC device incorporates flexible internal clock generators,
including a 24-MHz internal main oscillator (IMO), accurate to
±5% over temperature and voltage. The 24-MHz IMO can also
be doubled to 48 MHz for use by the digital system. A low-power
32-kHz internal low-speed oscillator (ILO) is provided for the
sleep timer and WDT. If crystal accuracy is desired, the ECO
(32.768-kHz external crystal oscillator) is available for use as a
real time clock (RTC) and can optionally generate a
crystal-accurate 24-MHz system clock using a PLL. The clocks,
together with programmable clock dividers (as a system
resource), provide the flexibility to integrate almost any timing
requirement into the PSoC device.
Port 0
Digital PSoC Block Array
PSoC Core
Memory encompasses 8 KB of flash for program storage,
256 bytes of SRAM for data storage, and up to 2 KB of EEPROM
emulated using the flash. Program flash utilizes four protection
levels on blocks of 64 bytes, allowing customized software IP
protection.
Port 1
To System Bus
Digital Clocks
FromCore
The PSoC architecture, as shown in the Logic Block Diagram on
page 1, is comprised of four main areas: PSoC core, digital
system, analog system, and system resources. Configurable
global busing allows all the device resources to be combined into
a complete custom system. The PSoC CY8C24x33 family can
have up to three I/O ports that connect to the global digital and
analog interconnects, providing access to four digital blocks and
four analog blocks.
The M8C CPU core is a powerful processor with speeds up to
24 MHz, providing a four MIPS 8-bit Harvard-architecture
microprocessor. The CPU uses an interrupt controller with 11
vectors, to simplify programming of real-time embedded events.
Program execution is timed and protected using the included
sleep and watch dog timers (WDT).
Port 2
8
8
GOE[7:0]
GOO[7:0]
The digital peripheral configurations include:
■
PWMs (8- and 16-bit)
■
PWMs with dead band (8- and 16-bit)
■
Counters (8- to 32-bit)
■
Timers (8- to 32-bit)
■
UART 8 bit with selectable parity (up to 1)
■
SPI master and slave (up to 1)
■
I2C slave and master (one available as a system resource)
■
Cyclical redundancy checker/generator (8- to 32-bit)
■
IrDA (up to one)
■
Pseudo random sequence generators (8- to 32-bit)
The digital blocks can be connected to any GPIO through a
series of global buses that can route any signal to any pin. The
buses also allow for signal multiplexing and for performing logic
operations. This configurability frees your designs from the
constraints of a fixed peripheral controller.
Digital blocks are provided in rows of four, where the number of
blocks varies by PSoC device family. This allows you the
optimum choice of system resources for your application. Family
resources are shown in the table titled PSoC Device
Characteristics on page 5.
Page 3 of 48
CY8C24533
Analog System
Figure 2. Analog System Block Diagram
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
Each analog block is comprised of an opamp circuit allowing the
creation of complex analog signal flows. Analog peripherals are
very flexible and can be customized to support specific
application requirements. Some of the more common PSoC
analog functions (most available as user modules) are:
P0[1]
P0[0]
■
Filters (2 and 4 pole band pass, low-pass, and notch)
■
Amplifiers (up to two, with selectable gain to 48x)
■
Instrumentation amplifiers (1 with selectable gain to 93x)
■
Comparators (up to two, with 16 selectable thresholds)
■
DACs (up to two, with 6- to 9-bit resolution)
■
Multiplying DACs (up to two, with 6- to 9-bit resolution)
■
High current output drivers (two with 30 mA drive as a core
resource)
■
1.3-V reference (as a system resource)
■
DTMF dialer
■
Modulators
■
Correlators
■
Peak detectors
■
Many other topologies possible
AGNDIn RefIn
The analog system is composed of an 8-bit SAR ADC and four
configurable blocks. The programmable 8-bit SAR ADC is an
optimized ADC that runs up to 300 Ksps, with monotonic
guarantee. It also has the features to support a motor control
application.
P2[3]
P2[6]
P2[4]
P2[1]
P2[2]
P2[0]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
Block Array
ACB00
ACB01
ASD11
ASC21
P0[7:0]
Analog blocks are arranged in a column of three, which includes
one continuous time (CT) and two switched capacitor (SC)
blocks. The analog column 0 contains the SAR8 ADC block
rather than the standard SC blocks.
ACI2[3:0]
8-Bit SAR ADC
Analog Reference
Interface to
Digital System
RefHi
RefLo
AGND
Reference
Generators
AGNDIn
RefIn
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 001-14643 Rev. *L
Page 4 of 48
CY8C24533
Additional System Resources
System resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Additional resources include a multiplier, decimator, low voltage
detection, and power on reset. Brief statements describing the
merits of each system resource follow:
■
■
■
■
The decimator provides a custom hardware filter for digital
signal processing applications including the creation of delta
sigma ADCs.
The I2C module provides 100- and 400- kHz communication
over two wires. Slave, master, and multi-master modes are all
supported.
Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
■
A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math as well
as digital filters.
Low-voltage detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
circuit eliminates the need for a system supervisor.
■
An internal 1.3-V voltage reference provides an absolute
reference for the analog system, including ADCs and DACs.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 3
analog blocks. The following table lists the resources available for specific PSoC device groups.
Table 1. PSoC Device Characteristics
PSoC Part
Number
Digital
I/O
CY8C29x66
up to 64
CY8C28xxx
up to 44
Digital
Rows
Digital
Blocks
Analog
Inputs
Analog
Outputs
4
16
up to 12
4
up to 3
up to 12
up to 44
up to 4
Analog
Columns
Analog
Blocks
SRAM
Size
Flash
Size
SAR
ADC
4
12
2K
32 K
No
up to 6
up to
12 + 4[1]
1K
16 K
Yes
CY8C27x43
up to 44
2
8
up to 12
4
4
12
256
16 K
No
CY8C24x94
up to 56
1
4
up to 48
2
2
6
1K
16 K
No
CY8C24x23A
up to 24
1
4
up to 12
2
2
6
256
4K
No
CY8C23x33
up to 26
1
4
up to 12
2
2
4
256
8K
Yes
CY8C22x45
up to 38
2
8
up to 38
0
4
6[1]
1K
16 K
No
[1]
CY8C21x45
up to 24
1
4
up to 24
0
4
6
512
8K
Yes
CY8C21x34
up to 28
1
4
up to 28
0
2
4[1]
512
8K
No
[1]
CY8C21x23
up to 16
1
4
up to 8
0
2
256
4K
No
CY8C20x34
up to 28
0
0
up to 28
0
0
3[1,2]
4
512
8K
No
CY8C20xx6
up to 36
0
0
up to 36
0
0
3[1,2]
up to
2K
up to
32 K
No
Notes
1. Limited analog functionality.
2. Two analog blocks and one CapSense®.
Document Number: 001-14643 Rev. *L
Page 5 of 48
CY8C24533
Getting Started
For in-depth information, along with detailed programming
details, see the PSoC® Technical Reference Manual.
covers a wide variety of topics and skill levels to assist you in
your designs.
For up-to-date ordering, packaging, and electrical specification
information, see the latest PSoC device datasheets on the web.
CYPros Consultants
Application Notes
Cypress application notes are an excellent introduction to the
wide variety of possible PSoC designs.
Development Kits
PSoC Development Kits are available online from and through a
growing number of regional and global distributors, which
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and
Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops), which is available online via www.cypress.com,
Document Number: 001-14643 Rev. *L
Certified PSoC consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC
consultant go to the CYPros Consultants web site.
Solutions Library
Visit our growing library of solution focused designs. Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
Technical Support
Technical support – including a searchable Knowledge Base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
Page 6 of 48
CY8C24533
Development Tools
PSoC Designer™ is the revolutionary integrated design
environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
■
Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■
Extensive user module catalog
■
Integrated source-code editor (C and assembly)
■
Free C compiler with no size restrictions or time limits
■
Built-in debugger
■
In-circuit emulation
Built-in support for communication interfaces:
2
❐ Hardware and software I C slaves and masters
❐ Full-speed USB 2.0
❐ Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
■
PSoC Designer Software Subsystems
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), amplifiers, and filters.
Configure the user modules for your chosen application and
connect them to each other and to the proper pins. Then
generate your project. This prepopulates your project with APIs
and libraries that you can use to program your application.
The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration
makes it possible to change configurations at run time. In
essence, this lets you to use more than 100 percent of PSoC's
resources for an application.
Document Number: 001-14643 Rev. *L
Code Generation Tools
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
You can read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also lets you to create a trace buffer of registers and memory
locations of interest.
Online Help System
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an Online Support
Forum to aid the designer.
In-Circuit Emulator
A low-cost, high-functionality in-circuit emulator (ICE) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24 MHz) operation.
Page 7 of 48
CY8C24533
Designing with PSoC Designer
The development process for the PSoC device differs from that
of a traditional fixed-function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and lowering inventory costs. These
configurable resources, called PSoC blocks, have the ability to
implement a wide variety of user-selectable functions. The PSoC
development process is:
1. Select user modules.
2. Configure user modules.
3. Organize and connect.
4. Generate, verify, and debug.
Select User Modules
PSoC Designer provides a library of prebuilt, pretested hardware
peripheral components called “user modules.” User modules
make selecting and implementing peripheral devices, both
analog and digital, simple.
Configure User Modules
Each user module that you select establishes the basic register
settings that implement the selected function. They also provide
parameters and properties that allow you to tailor their precise
configuration to your particular application. For example, a PWM
User Module configures one or more digital PSoC blocks, one
for each eight bits of resolution. Using these parameters, you can
establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application.
Enter values directly or by selecting values from drop-down
menus. All of the user modules are documented in datasheets
that may be viewed directly in PSoC Designer or on the Cypress
website. These user module datasheets explain the internal
operation of the user module and provide performance specifi-
Document Number: 001-14643 Rev. *L
cations. Each datasheet describes the use of each user module
parameter, and other information that you may need to successfully implement your design.
Organize and Connect
Build signal chains at the chip level by interconnecting user
modules to each other and the I/O pins. Perform the selection,
configuration, and routing so that you have complete control over
all on-chip resources.
Generate, Verify, and Debug
When you are ready to test the hardware configuration or move
on to developing code for the project, perform the “Generate
Configuration Files” step. This causes PSoC Designer to
generate source code that automatically configures the device to
your specification and provides the software for the system. The
generated code provides APIs with high-level functions to control
and respond to hardware events at run time, and interrupt
service routines that you can adapt as needed.
A complete code development environment lets you to develop
and customize your applications in C, assembly language, or
both.
The last step in the development process takes place inside
PSoC Designer's Debugger (accessed by clicking the Connect
icon). PSoC Designer downloads the HEX image to the ICE
where it runs at full-speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition
to traditional single-step, run-to-breakpoint, and watch-variable
features, the debug interface provides a large trace buffer. It lets
you to define complex breakpoint events that include monitoring
address and data bus values, memory locations, and external
signals.
Page 8 of 48
CY8C24533
Pinouts
The PSoC CY8C24533 is available in a 28-pin SSOP package. Every port pin (labeled with a “P”), except for Vss and Vdd in the
following table and figure, is capable of Digital I/O.
28-Pin Part Pinout
Figure 3. CY8C24533 PSoC Device
Pin Name
Analog
Digital
Pin Number
CY8C24533
Table 2. 28-Pin Part Pinout (SSOP)
Description
1
I/O
I
P0[7]
Analog col mux IP and ADC IP
2
I/O
I/O
P0[5]
Analog col mux IP and column O/P and ADC
IP
3
4
I/O
I/O
I/O
I
P0[3]
Analog col mux IP and column O/P and ADC
IP
P0[1]
Analog col mux IP and ADC IP
5
I/O
P2[7]
GPIO
6
I/O
P2[5]
GPIO
7
I/O
P2[3]
Direct switched capacitor input
I
8
I/O
9
I/O
AVref P3[0]
10
I/O
P1[7]
I2C SCL
11
I/O
P1[5]
I2C SDA
12
I/O
P1[3]
GPIO
13
I/O
P1[1][4]
GPIO, Xtal input, I2C SCL, ISSP SCL
Vss
Ground pin
P1[0][4]
GPIO, Xtal output, I2C SDA, ISSP SDA
14
15
I
P2[1]
[3]
Power
I/O
Direct switched capacitor input
I/O
P1[2]
GPIO
17
I/O
P1[4]
GPIO, external clock IP
18
I/O
P1[6]
GPIO
19
I/O
P3[1][5]
GPIO
20
I/O
I
P2[0]
Direct switched capacitor input
21
I/O
I
P2[2]
Direct switched capacitor input
22
I/O
P2[4]
GPIO
23
I/O
P2[6]
GPIO
24
I/O
I
P0[0]
Analog col mux IP and ADC IP
25
I/O
I
P0[2]
Analog col mux IP and ADC IP
26
I/O
I
P0[4]
Analog col mux IP and ADC IP
27
I/O
I
P0[6]
Analog col mux IP and ADC IP
Vdd
Supply voltage
Power
1
28
Vdd
IO, P0[5]
2
27
P0[6], AIO, AnColMux and ADC IP
IO, P0[3]
3
26
P0[4], AIO, AnColMux and ADC IP
AIO, P0[1]
4
25
P0[2], AIO, AnColMux and ADC IP
IO, P2[7]
5
24
P0[0], AIO, AnColMux and ADC IP
IO, P2[5]
6
23
P2[6], IO
AIO, P2[3]
7
22
P2[4], IO
AIO, P2[1]
8
21
P2[2], AIO
AVref, IO, P3[0]
9
20
P2[0], AIO
I2C SCL, IO, P1[7]
10
19
P3[1], IO
I2C SDA, IO, P1[5]
11
18
P1[6], IO
IO, P1[3]
12
17
P1[4], IO, EXTCLK
I2C SCL, ISSP SCL, XTALin, IO, P1[1]
13
16
P1[2], IO
14
15
P1[0], IO, XTALout, ISSP SDA, I2CSDA
Vss
SSOP
GPIO/ADC Vref (optional)
16
28
AIO, P0[7]
LEGEND: A = Analog, I = Input, and O = Output.
Notes
3. Even though P3[0] is an odd port, it resides on the left side of the pinout.
4. ISSP pin, which is not High Z at POR.
5. Even though P3[1] is an even port, it resides on the right side of the pinout.
Document Number: 001-14643 Rev. *L
Page 9 of 48
CY8C24533
Register Reference
This chapter lists the registers of the CY8C24533 PSoC device by using mapping tables, in offset order.
Register Conventions
Register Mapping Tables
Abbreviations Used
The PSoC device has a total register address space of 512
bytes. The register space is referred to as I/O space and is
divided into two banks, Bank 0 and Bank 1. The XOI bit in the
flag register (CPU_F) determines which bank the user is
currently in. When the XOI bit is set, the user is in Bank 1.
The register conventions specific to this section are listed in the
following table.
Convention
Description
R
Read register or bit(s)
W
Write register or bit(s)
L
Logical register or bit(s)
C
Clearable register or bit(s)
#
Access is bit specific
Document Number: 001-14643 Rev. *L
Note In the following register mapping tables, blank fields are
reserved and must not be accessed.
Page 10 of 48
CY8C24533
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
DCB03DR2
DCB03CR0
Gray fields are reserved.
#
W
RW
#
#
W
RW
#
#
W
RW
#
#
W
RW
#
AMX_IN
ARF_CR
CMP_CR0
ASY_CR
CMP_CR1
SARADC_DL
SARADC_CR0
SARADC_CR1
TMP_DR0
TMP_DR1
TMP_DR2
TMP_DR3
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1 *
ACB01CR2 *
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
RW
RW
#
#
RW
RW
#
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
RW
RW
RW
RW
RW
RW
RW
RW
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
INT_CLR3
INT_MSK3
INT_MSK0
INT_MSK1
INT_VC
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL0_X
MUL0_Y
MUL0_DH
MUL0_DL
ACC0_DR1
ACC0_DR0
ACC0_DR3
ACC0_DR2
RW
RW
RW
RW
RW
RW
RW
CPU_F
CPU_SCR1
CPU_SCR0
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Access
Addr
(0,Hex)
Name
Access
Addr
(0,Hex)
Name
Access
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Addr
(0,Hex)
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
Name
Access
PRT0DR
PRT0IE
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
PRT3DR
PRT3IE
PRT3GS
PRT3DM2
Addr
(0,Hex)
Name
Table 3. Register Map Bank 0 Table: User Space
RW
#
RW
#
RW
RW
RW
RW
RW
RW
RC
W
RC
RC
RW
RW
W
W
R
R
RW
RW
RW
RW
RL
#
#
# Access is bit specific.
Document Number: 001-14643 Rev. *L
Page 11 of 48
CY8C24533
Table 4. Register Map Bank 1 Table: Configuration Space
Name
PRT0DM0
Addr (1,Hex)
Access
00
RW
Name
Addr (1,Hex)
40
Access
Name
Addr (1,Hex)
80
Access
Name
Addr (1,Hex)
C0
PRT0DM1
01
RW
41
81
C1
PRT0IC0
02
RW
42
82
C2
PRT0IC1
03
RW
43
83
PRT1DM0
04
RW
44
ASD11CR0
84
RW
C4
PRT1DM1
05
RW
45
ASD11CR1
85
RW
C5
PRT1IC0
06
RW
46
ASD11CR2
86
RW
C6
PRT1IC1
07
RW
47
ASD11CR3
87
RW
C7
PRT2DM0
08
RW
48
88
PRT2DM1
09
RW
49
89
C9
PRT2IC0
0A
RW
4A
8A
CA
Access
C3
C8
PRT2IC1
0B
RW
4B
8B
CB
PRT3DM0
0C
RW
4C
8C
CC
PRT3DM1
0D
RW
4D
8D
CD
PRT3IC0
0E
RW
4E
8E
CE
PRT3IC1
0F
RW
4F
8F
10
50
90
GDI_O_IN
D0
RW
11
51
91
GDI_E_IN
D1
RW
12
52
92
GDI_O_OU
D2
RW
13
53
93
GDI_E_OU
D3
RW
14
54
ASC21CR0
94
RW
D4
15
55
ASC21CR1
95
RW
D5
16
56
ASC21CR2
96
RW
D6
17
57
ASC21CR3
97
RW
D7
18
58
98
19
59
99
D9
1A
5A
9A
DA
CF
D8
1B
5B
9B
DB
1C
5C
9C
DC
1D
5D
9D
OSC_GO_EN
DD
RW
1E
5E
9E
OSC_CR4
DE
RW
1F
5F
9F
OSC_CR3
DF
RW
DBB00FN
20
RW
CLK_CR0
60
RW
A0
OSC_CR0
E0
RW
DBB00IN
21
RW
CLK_CR1
61
RW
A1
OSC_CR1
E1
RW
DBB00OU
22
RW
ABF_CR0
62
RW
A2
OSC_CR2
E2
RW
AMD_CR0
63
RW
A3
VLT_CR
E3
RW
VLT_CMP
E4
R
23
DBB01FN
24
RW
64
A4
DBB01IN
25
RW
65
A5
E5
DBB01OU
26
RW
E6
27
AMD_CR1
66
RW
A6
ALT_CR0
67
RW
A7
E7
DCB02FN
28
RW
68
SARADC_TRS
A8
RW
IMO_TR
E8
W
DCB02IN
29
RW
69
SARADC_TRCL
A9
RW
ILO_TR
E9
W
DCB02OU
2A
RW
6A
SARADC_TRCH
AA
RW
BDG_TR
EA
RW
6B
SARADC_CR2
AB
#
ECO_TR
EB
W
SARADC_LCR
AC
RW
2B
DCB03FN
2C
RW
TMP_DR0
6C
RW
DCB03IN
2D
RW
TMP_DR1
6D
RW
AD
ED
DCB03OU
2E
RW
TMP_DR2
6E
RW
AE
EE
2F
TMP_DR3
6F
RW
AF
30
ACB00CR3
70
RW
RDI0RI
B0
RW
F0
31
ACB00CR0
71
RW
RDI0SYN
B1
RW
F1
32
ACB00CR1
72
RW
RDI0IS
B2
RW
F2
33
ACB00CR2
73
RW
RDI0LT0
B3
RW
F3
34
ACB01CR3
74
RW
RDI0LT1
B4
RW
F4
35
ACB01CR0
75
RW
RDI0RO0
B5
RW
F5
36
ACB01CR1
76
RW
RDI0RO1
B6
RW
37
ACB01CR2 *
77
RW
38
78
B7
EC
EF
F6
CPU_F
B8
F7
RL
F8
39
79
B9
3A
7A
BA
3B
7B
BB
FB
3C
7C
BC
FC
3D
7D
BD
3E
7E
BE
CPU_SCR1
FE
#
3F
7F
BF
CPU_SCR0
FF
#
Gray fields are reserved.
F9
FLS_PR1
FA
RW
FD
# Access is bit specific.
Document Number: 001-14643 Rev. *L
Page 12 of 48
CY8C24533
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C24533 PSoC device. For the latest electrical specifications,
visit http://www.cypress.com.
Specifications are valid for –40 oC TA 85 °C and TJ 100 °C, except where noted.
Refer to Table 20 on page 27 for the electrical specifications for the IMO using SLIMO mode.
Figure 4. Voltage versus CPU Frequency
Figure 4. IMO Frequency Trim Options
5.25
4.75
Vdd Voltage
Vdd Voltage
lid g
Va ratin n
pe io
O Reg
4.75
SLIMO Mode = 0
5.25
3.60
3.00
3.00
93 kHz
3 MHz
CPU Frequency
Document Number: 001-14643 Rev. *L
12 MHz
24 MHz
93 kHz
SLIMO
Mode=1
SLIMO
Mode=0
SLIMO
Mode=1
SLIMO
Mode=0
6 MHz
12 MHz
24 MHz
IMO Frequency
Page 13 of 48
CY8C24533
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested.
Table 5. Absolute Maximum Ratings
Symbol
TSTG
Description
Storage temperature
TBAKETEMP Bake temperature
TBAKETIME Bake Time
Min
Typ
Max
Units
Notes
–55
25
+100
°C
Higher storage temperatures
reduces data retention time.
Recommended storage
temperature is +25 °C ± 25 °C.
Extended duration storage
temperatures above 65 °C degrades
reliability.
-
125
See
package
label
See
package
label
-
72
Hours
–40
–
+85
°C
o
C
TA
Ambient temperature with power applied
Vdd
Supply voltage on Vdd relative to Vss
–0.5
–
+6.0
V
VIO
DC input voltage
Vss - 0.5
–
Vdd + 0.5
V
VIOZ
DC voltage applied to Tri-state
Vss - 0.5
–
Vdd + 0.5
V
IMIO
Maximum current into any port pin
–25
–
+50
mA
ESD
Electro static discharge voltage
2000
–
–
V
LU
Latch up current
–
–
200
mA
Min
Typ
Max
Units
Human Body Model ESD
Operating Temperature
Table 6. Operating Temperature
Symbol
Description
TA
Ambient temperature
–40
–
+85
°C
TJ
Junction temperature
–40
–
+100
°C
Document Number: 001-14643 Rev. *L
Notes
The temperature rise from ambient to
junction is package specific. See
Thermal Impedances by Package on
page 38. The user must limit the
power consumption to comply with
this requirement.
Page 14 of 48
CY8C24533
DC Electrical Characteristics
DC Chip-Level Specifications
The following table lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to
5.25 V and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V
at 25 °C and are for design guidance only.
Table 7. DC Chip-Level Specifications
Symbol
Description
VDD
Supply voltage
IDD
Supply current
Min
3.0
–
Typ
–
5
Max
5.25
8
Units
V
mA
IDD3
Supply current
–
3.3
6.0
mA
ISB
Sleep (Mode) current with POR, LVD, sleep
timer, and WDT.[6]
–
3
6.5
A
ISBH
Sleep (Mode) current with POR, LVD, sleep
timer, and WDT at high temperature.[6]
–
4
25
A
ISBXTL
Sleep (Mode) current with POR, LVD, sleep
timer, WDT, and external crystal.[6]
–
4
7.5
A
ISBXTLH Sleep (Mode) current with POR, LVD, sleep
timer, WDT, and external crystal at high
temperature.[6]
–
5
26
A
1.28
1.30
1.32
V
VREF
Reference voltage (Bandgap)
Notes
See Table 17 on page 25.
Conditions are VDD = 5.0 V,
TA = 25 °C, CPU = 3 MHz, SYSCLK
doubler disabled, VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 93.75 kHz,
analog power = off. SLIMO mode = 0.
IMO = 24 MHz.
Conditions are VDD = 3.3V,
TA = 25 °C, CPU = 3 MHz, SYSCLK
doubler disabled, VC1 = 1.5 MHz,
VC2 = 93.75 kHz, VC3 = 93.75 kHz,
analog power = off. SLIMO mode = 0.
IMO = 24 MHz.
Conditions are with internal slow
speed oscillator, VDD = 3.3 V,
–40 °C TA 55 °C,
analog power = off.
Conditions are with internal slow
speed oscillator,
VDD = 3.3 V, 55 °C < TA 85 °C,
analog power = off.
Conditions are with properly loaded,
1 W max, 32.768 kHz crystal.
VDD = 3.3 V, -40 °C TA 55 °C,
analog power = off.
Conditions are with properly loaded,
1W max, 32.768 kHz crystal.
VDD = 3.3 V, 55 °C < TA 85 °C,
analog power = off.
Trimmed for appropriate VDD.
VDD > 3.0 V
Note
6. Standby current includes all functions (POR, LVD, WDT, sleep time) needed for reliable system operation. This must be compared with devices that have similar
functions enabled.
Document Number: 001-14643 Rev. *L
Page 15 of 48
CY8C24533
DC GPIO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 8. 5-V and 3.3-V DC GPIO Specifications
Symbol
Description
Pull-up resistor
RPU
Pull-down resistor
RPD
High output level
VOH
VOL
Low output level
IOH
IOL
VIL
VIH
VH
IIL
CIN
High-level source current
Low-level sink current
Input low-level
Input high-level
Input hysterisis
Input leakage (Absolute Value)
Capacitive load on pins as input
COUT
Capacitive load on pins as output
Document Number: 001-14643 Rev. *L
Min
4
4
VDD 1.0
Typ
5.6
5.6
–
Max
8
8
–
Units
k
k
V
–
–
0.75
V
10
25
–
2.1
–
–
–
–
–
–
–
60
1
3.5
–
–
0.8
–
–
10
mA
mA
V
V
mV
nA
pF
–
3.5
10
pF
Notes
IOH = 10 mA, VDD = 4.75 to 5.25 V
(maximum 40 mA on even port pins
(for example, P0[2], P1[4]),
maximum 40 mA on odd port pins
(for example, P0[3], P1[5])). 80 mA
maximum combined IOH budget.
IOL = 25 mA, VDD = 4.75 to 5.25 V
(maximum 100 mA on even port
pins (for example, P0[2], P1[4]),
maximum 100 mA on odd port pins
(for example, P0[3], P1[5])). 100 mA
maximum combined IOH budget.
VDD = 3.0 to 5.25
VDD = 3.0 to 5.25
Gross tested to 1 A
Package and pin dependent.
Temp = 25 °C
Package and pin dependent.
Temp = 25 °C
Page 16 of 48
CY8C24533
DC Operational Amplifier Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
The Operational Amplifier is a component of both the analog continuous time PSoC blocks and the analog switched cap PSoC blocks.
The guaranteed specifications are measured in the analog continuous time PSoC block. Typical parameters apply to 5 V at 25 °C and
are for design guidance only.
Table 9. 5-V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input offset voltage (absolute value)
Power = Low, opamp Bias = High
Power = Medium, opamp Bias = High
Power = High, opamp Bias = High
TCVOSOA Average input offset voltage drift
IEBOA
Input leakage current (Port 0 Analog Pins)
Input capacitance (Port 0 Analog Pins)
CINOA
Min
Typ
Max
–
–
–
–
–
–
1.6
1.3
1.2
7.0
20
4.5
10
8
7.5
35.0
–
9.5
VCMOA
Common mode voltage range
Common mode voltage range (high power or high
opamp bias)
0.0
0.5
–
–
GOLOA
Open loop gain
Power = Low, opamp Bias = High
Power = Medium, opamp Bias = High
Power = High, opamp Bias = High
60
60
80
–
–
–
VOHIGHOA High output voltage swing (internal signals)
Power = Low, Opamp Bias = High
VDD - 0.2
–
Power = Medium, Opamp Bias = High
–
VDD - 0.2
Power = High, Opamp Bias = High
VDD - 0.5
–
VOLOWOA Low output voltage swing (internal signals)
–
–
Power = Low, Opamp Bias = High
–
–
Power = Medium, Opamp Bias = High
–
–
Power = High, Opamp Bias = High
ISOA
Supply current (including associated AGND buffer)
300
–
Power = Low, Opamp Bias = High
600
–
Power = Medium, Opamp Bias = Low
1200
–
Power = Medium, Opamp Bias = High
2400
–
Power = High, Opamp Bias = Low
4600
–
Power = High, Opamp Bias = High
PSRROA Supply voltage rejection ratio
52
80
Document Number: 001-14643 Rev. *L
Units
Notes
mV
mV
mV
V/°C
pA Gross tested to 1 A
pF Package and pin dependent.
Temp = 25 °C
VDD
V
The common-mode input
VDD - 0.5
voltage range is measured
through an analog output
buffer. The specification
includes the limitations
imposed by the
characteristics of the analog
output buffer.
Specification is applicable at
dB high power. For all other bias
–
dB modes (except high power,
–
dB high opamp bias), minimum
–
is 60 dB.
–
–
–
V
V
V
0.2
0.2
0.5
V
V
V
400
800
1600
3200
6400
–
A
A
A
A
A
dB
VSS VIN (VDD - 2.25) or
(VDD - 1.25 V) VIN VDD
Page 17 of 48
CY8C24533
Table 10. 3.3-V DC Operational Amplifier Specifications
Symbol
VOSOA
Description
Input offset voltage (absolute value)
Power = low, Opamp bias = high
Power = medium, Opamp bias = high
Power = high, Opamp bias = high
Min
Typ
Max
Units
Notes
Power = high, Opamp bias = high
setting is not allowed for 3.3-V VDD
operation.
–
–
–
1.65
1.32
–
10
8
–
mV
mV
mV
TCVOSOA Average input offset voltage drift
–
7.0
35.0
µV/°C
IEBOA
Input leakage current (port 0 analog pins)
–
20
–
pA
Gross tested to 1 A
CINOA
Input capacitance (port 0 analog pins)
–
4.5
9.5
pF
Package and pin dependent.
Temp = 25 °C
VCMOA
Common mode voltage range
0.2
–
VDD – 0.2
V
The common-mode input voltage
range is measured through an
analog output buffer. The
specification includes the
limitations imposed by the
characteristics of the analog
output buffer.
GOLOA
Open loop gain
Power = low, ppamp, Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
60
60
80
–
–
–
–
–
–
dB
dB
dB
VOHIGHOA High output voltage swing (internal signals)
Power = low, Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
VDD – 0.2
VDD – 0.2
VDD – 0.2
–
–
–
–
–
–
V
V
V
VOLOWOA Low output voltage swing (internal signals)
Power = low, ppamp, Opamp bias = low
Power = medium, Opamp bias = low
Power = high, Opamp bias = low
–
–
–
–
–
–
0.2
0.2
0.2
V
V
V
ISOA
PSRROA
Supply current (including associated AGND
buffer)
Power = low, Opamp bias = low
Power = low, Opamp bias = high
Power = medium, Opamp bias = low
Power = medium, Opamp bias = high
Power = high, Opamp bias = low
Power = high, Opamp bias = high
–
–
–
–
–
–
150
300
600
1200
2400
–
200
400
800
1600
3200
–
A
A
A
A
A
A
Supply voltage rejection ratio
64
80
–
dB
Specification is applicable at low
Opamp bias. For high Opamp bias
mode (except high power, high
Opamp bias), minimum is 60 dB.
Power = high, Opamp bias = high
setting is not allowed for 3.3-V VDD
operation.
Power = high, Opamp bias = high
setting is not allowed for 3.3-V VDD
operation.
Power = high, Opamp bias = high
setting is not allowed for 3.3-V VDD
operation.
VSS VIN (VDD – 2.25) or
(VDD – 1.25 V) VIN VDD
DC Low-Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 11. DC Low-Power Comparator Specifications
Symbol
Description
Min
Typ
Max
Units
0.2
–
Vdd - 1
V
LPC supply current
–
10
40
A
LPC voltage offset
–
2.5
30
mV
VREFLPC
Low power comparator (LPC) reference voltage
range
ISLPC
VOSLPC
Document Number: 001-14643 Rev. *L
Notes
Page 18 of 48
CY8C24533
DC Analog Output Buffer Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 12. 5-V DC Analog Output Buffer Specifications
Symbol
Description
Min
Typ
Max
Units
–
200
pF
CL
Load capacitance
–
VOSOB
Input offset voltage (Absolute value)
–
3
12
mV
–
+6
–
V/°C
0.5
–
VDD – 1.0
V
–
–
1
1
–
–
VOHIGHOB High output voltage swing (Load = 32 ohms to Vdd/2)
Power = Low
0.5 x VDD + 1.1
Power = High
0.5 x VDD + 1.1
–
–
–
–
V
V
VOLOWOB Low output voltage swing (Load = 32 ohms to Vdd/2)
Power = Low
Power = High
–
–
–
–
0.5 x VDD - 1.3
0.5 x VDD- 1.3
V
V
TCVOSOB Average input offset voltage drift
VCMOB
Common-mode input voltage range
ROUTOB
Output resistance
Power = Low
Power = High
ISOB
Supply current including bias cell (No load)
Power = Low
Power = High
–
–
1.1
2.6
5.1
8.8
mA
mA
PSRROB
Supply Voltage rejection ratio
52
64
–
dB
Notes
This specification
applies to the
external circuit that
is being driven by
the analog output
buffer.
VOUT > (VDD - 1.25)
Table 13. 3.3-V DC Analog Output Buffer Specifications
Min
Typ
Max
Units
CL
Symbol
Load capacitance
Description
–
–
200
pF
VOSOB
Input offset voltage (Absolute value)
–
3
12
mV
TCVOSOB Average input offset voltage drift
VCMOB
Common-mode input voltage range
ROUTOB
Output resistance
Power = Low
Power = High
–
+6
–
V/°C
0.5
–
Vdd – 1.0
V
–
–
1
1
–
–
–
–
–
–
V
V
–
–
0.5 x VDD - 1.0
0.5 x VDD - 1.0
V
V
VOHIGHOB High output voltage swing (Load = 1 k ohms to VDD/2)
0.5 x VDD + 1.0
Power = Low
0.5 x VDD + 1.0
Power = High
VOLOWOB Low output voltage swing (Load = 1k ohms to VDD/2)
Power = Low
–
Power = High
–
ISOB
PSRROB
Supply current including bias cell (No load)
Power = Low
Power = High
–
0.8
2.0
2.0
4.3
mA
mA
Supply voltage rejection ratio
52
64
–
dB
Document Number: 001-14643 Rev. *L
Notes
This specification
applies to the
external circuit that
is being driven by
the analog output
buffer.
VOUT > (VDD - 1.25)
Page 19 of 48
CY8C24533
DC Analog Reference Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
The guaranteed specifications are measured through the analog continuous time PSoC blocks. The power levels for AGND refer to
the power of the analog continuous time PSoC block. The power levels for RefHi and RefLo refer to the analog reference control
register. The limits stated for AGND include the offset error of the AGND buffer local to the analog continuous time PSoC block.
Reference control power is high.
Table 14. 5-V DC Analog Reference Specifications
Reference
ARF_CR
[5:3]
0b000
Reference Power
Settings
Symbol
Reference
RefPower = high
Opamp bias = high
VREFHI
Ref High
VAGND
AGND
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b001
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
Description
Min
Typ
Max
Units
VDD/2 + Bandgap
VDD/2 + 1.136 VDD/2 + 1.288 VDD/2 + 1.409
V
VDD/2
VDD/2 – 0.138 VDD/2 + 0.003 VDD/2 + 0.132
VDD/2 – 1.417 VDD/2 – 1.289 VDD/2 – 1.154
V
VREFLO
Ref Low
VDD/2 – Bandgap
VREFHI
Ref High
VDD/2 + Bandgap
VAGND
AGND
V
V
VDD/2
VDD/2 + 1.202 VDD/2 + 1.290 VDD/2 + 1.358
VDD/2 – 0.055 VDD/2 + 0.001 VDD/2 + 0.055
V
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.369 VDD/2 – 1.295 VDD/2 – 1.218
V
VREFHI
Ref High
VDD/2 + Bandgap
V
VAGND
AGND
VDD/2
VDD/2 + 1.211 VDD/2 + 1.292 VDD/2 + 1.357
VDD/2 – 0.055
VDD/2
VDD/2 + 0.052
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.368 VDD/2 – 1.298 VDD/2 – 1.224
V
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 + 1.215 VDD/2 + 1.292 VDD/2 + 1.353
VDD/2 – 0.040 VDD/2 – 0.001 VDD/2 + 0.033
V
VDD/2 – 1.368 VDD/2 – 1.299 VDD/2 – 1.225
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.076
0.021
0.041
V
V
VAGND
AGND
VREFLO
Ref Low
VDD/2 – Bandgap
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
VAGND
AGND
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.025
0.011
0.085
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.069
0.014
0.043
V
VAGND
AGND
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.029
0.005
0.052
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.072
0.011
0.048
V
VDD/2
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
V
V
–
–
VAGND
AGND
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.031
0.002
0.057
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.070
0.009
0.047
V
VAGND
AGND
VREFLO
Ref Low
Document Number: 001-14643 Rev. *L
P2[4]
P2[4]
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 1.3 V)
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.033
0.001
0.039
Page 20 of 48
–
–
V
CY8C24533
Table 14. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
0b010
Reference Power
Settings
Symbol
Reference
RefPower = high
Opamp bias = high
VREFHI
Ref High
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b011
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b100
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
Description
VDD
Min
Typ
Max
Units
VDD – 0.121
VDD – 0.003
VDD
V
VAGND
AGND
VDD/2 – 0.040
VDD/2
VDD/2 + 0.034
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.006
VSS + 0.019
V
VREFHI
Ref High
VDD
VDD – 0.083
VDD – 0.002
VDD
V
VDD/2
VAGND
AGND
VREFLO
Ref Low
VSS
VSS
VSS + 0.004
VSS + 0.016
V
VREFHI
Ref High
VDD
VDD – 0.075
VDD – 0.002
VDD
V
VDD/2
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
VDD
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
VAGND
AGND
VREFLO
VDD/2
VDD/2
VDD/2 – 0.040 VDD/2 – 0.001 VDD/2 + 0.033
VDD/2 – 0.040 VDD/2 – 0.001 VDD/2 + 0.032
V
V
VSS
VSS + 0.003
VSS + 0.015
V
VDD – 0.074
VDD – 0.002
VDD
V
VDD/2 – 0.040 VDD/2 – 0.001 VDD/2 + 0.032
V
VSS
VSS + 0.002
VSS + 0.014
V
3 × Bandgap
3.753
3.874
3.979
V
2 × Bandgap
2.511
2.590
2.657
V
Ref Low
Bandgap
1.243
1.297
1.333
V
VREFHI
Ref High
3 × Bandgap
3.767
3.881
3.974
V
VAGND
AGND
2 × Bandgap
2.518
2.592
2.652
V
VREFLO
Ref Low
Bandgap
1.241
1.295
1.330
V
VREFHI
Ref High
3 × Bandgap
2.771
3.885
3.979
V
VAGND
AGND
2 × Bandgap
2.521
2.593
2.649
V
VREFLO
Ref Low
Bandgap
1.240
1.295
1.331
V
VREFHI
Ref High
3 × Bandgap
3.771
3.887
3.977
V
VAGND
AGND
2 × Bandgap
2.522
2.594
2.648
V
VREFLO
Ref Low
Bandgap
VREFHI
Ref High
2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
1.239
1.295
1.332
V
2.481 + P2[6]
2.569 + P2[6]
2.639 + P2[6]
V
VAGND
AGND
2.511
2.590
2.658
V
VREFLO
Ref Low
2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
2.515 – P2[6]
2.602 – P2[6]
2.654 – P2[6]
V
VREFHI
Ref High
2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
2.498 + P2[6]
2.579 + P2[6]
2.642 + P2[6]
V
VAGND
AGND
2.518
2.592
2.652
V
VREFLO
Ref Low
2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
2.513 – P2[6]
2.598 – P2[6]
2.650 – P2[6]
V
VREFHI
Ref High
2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
2.504 + P2[6]
2.583 + P2[6]
2.646 + P2[6]
V
VAGND
AGND
2.521
2.592
2.650
V
VREFLO
Ref Low
2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
2.513 – P2[6]
2.596 – P2[6]
2.649 – P2[6]
V
VREFHI
Ref High
2 × Bandgap + P2[6]
(P2[6] = 1.3 V)
2.505 + P2[6]
2.586 + P2[6]
2.648 + P2[6]
V
VAGND
AGND
2.521
2.594
2.648
V
VREFLO
Ref Low
2.513 – P2[6]
2.595 – P2[6]
2.648 – P2[6]
V
Document Number: 001-14643 Rev. *L
2 × Bandgap
2 × Bandgap
2 × Bandgap
2 × Bandgap
2 × Bandgap – P2[6]
(P2[6] = 1.3 V)
Page 21 of 48
CY8C24533
Table 14. 5-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
0b101
Reference Power
Settings
Symbol
Reference
RefPower = high
Opamp bias = high
VREFHI
Ref High
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b110
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b111
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
Description
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4]
Min
Typ
Max
Units
P2[4] + 1.228
P2[4] + 1.284
P2[4] + 1.332
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.358
P2[4] – 1.293
P2[4] – 1.226
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.236
P2[4] + 1.289
P2[4] + 1.332
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.357
P2[4] – 1.297
P2[4] – 1.229
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.237
P2[4] + 1.291
P2[4] + 1.337
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.356
P2[4] – 1.299
P2[4] – 1.232
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.237
P2[4] + 1.292
P2[4] + 1.337
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.357
P2[4] – 1.300
P2[4] – 1.233
V
VREFHI
Ref High
2 × Bandgap
2.512
2.594
2.654
V
VAGND
AGND
Bandgap
1.250
1.303
1.346
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.011
VSS + 0.027
V
VREFHI
Ref High
2 × Bandgap
2.515
2.592
2.654
V
VAGND
AGND
Bandgap
1.253
1.301
1.340
V
P2[4]
P2[4]
P2[4]
VREFLO
Ref Low
VSS
VSS
VSS + 0.006
VSS + 0.02
V
VREFHI
Ref High
2 × Bandgap
2.518
2.593
2.651
V
VAGND
AGND
Bandgap
1.254
1.301
1.338
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.004
VSS + 0.017
V
VREFHI
Ref High
2 × Bandgap
2.517
2.594
2.650
V
VAGND
AGND
Bandgap
1.255
1.300
1.337
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.003
VSS + 0.015
V
VREFHI
Ref High
3.2 × Bandgap
4.011
4.143
4.203
V
1.6 × Bandgap
2.020
2.075
2.118
V
VSS
VSS + 0.011
VSS + 0.026
V
4.138
4.203
V
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
3.2 × Bandgap
4.022
1.6 × Bandgap
2.023
2.075
2.114
VSS
VSS + 0.006
VSS + 0.017
V
4.141
4.207
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
3.2 × Bandgap
4.026
1.6 × Bandgap
2.024
2.075
2.114
V
VSS
VSS + 0.004
VSS + 0.015
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
3.2 × Bandgap
4.030
4.143
4.206
V
VAGND
AGND
1.6 × Bandgap
2.024
2.076
2.112
V
VREFLO
Ref Low
VSS
VSS + 0.003
VSS + 0.013
V
Document Number: 001-14643 Rev. *L
VSS
Page 22 of 48
CY8C24533
Table 15. 3.3-V DC Analog Reference Specifications
Reference
ARF_CR
[5:3]
0b000
Reference Power
Settings
Symbol
Reference
RefPower = high
Opamp bias = high
VREFHI
Ref High
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b001
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b010
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b011
All power settings
Not allowed at 3.3 V
Description
VDD/2 + Bandgap
Min
Typ
Max
Units
VAGND
AGND
VDD/2
VDD/2 + 1.170 VDD/2 + 1.288 VDD/2 + 1.376
VDD/2 – 0.098 VDD/2 + 0.003 VDD/2 + 0.097
VREFLO
Ref Low
VDD/2 – Bandgap
VDD/2 – 1.386 VDD/2 – 1.287 VDD/2 – 1.169
V
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 + 1.210 VDD/2 + 1.290 VDD/2 + 1.355
VDD/2 – 0.055 VDD/2 + 0.001 VDD/2 + 0.054
V
VDD/2 – 1.359 VDD/2 – 1.292 VDD/2 – 1.214
VDD/2 + 1.198 VDD/2 + 1.292 VDD/2 + 1.368
V
VAGND
AGND
VREFLO
Ref Low
VDD/2 – Bandgap
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2
V
V
V
V
VAGND
AGND
VDD/2
VDD/2 – 0.041
VDD/2 + 0.04
V
VREFLO
Ref Low
VDD/2 – Bandgap
V
VREFHI
Ref High
VDD/2 + Bandgap
VDD/2 – 1.362 VDD/2 – 1.295 VDD/2 – 1.220
VDD/2 + 1.202 VDD/2 + 1.292 VDD/2 + 1.364
VAGND
AGND
VDD/2
VDD/2 – 0.033
VDD/2 + 0.030
V
VREFLO
Ref Low
VDD/2 – Bandgap
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
VDD/2 – 1.364 VDD/2 – 1.297 VDD/2 – 1.222
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.072
0.017
0.041
VAGND
AGND
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.029
0.010
0.048
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.066
0.010
0.043
V
P2[4]
P2[4]
VDD/2
VDD/2
P2[4]
P2[4]
V
V
–
VAGND
AGND
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.024
0.004
0.034
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.073
0.007
0.053
V
P2[4]
P2[4]
P2[4]
P2[4]
–
VAGND
AGND
VREFLO
Ref Low
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6] P2[4] – P2[6] + P2[4] – P2[6] +
– 0.028
0.002
0.033
V
VREFHI
Ref High
P2[4]+P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] + P2[6] P2[4] + P2[6] – P2[4] + P2[6] +
– 0.073
0.006
0.056
V
VAGND
AGND
VREFLO
Ref Low
VREFHI
Ref High
P2[4]
P2[4]
P2[4]
P2[4]
P2[4]
–
P2[4]
P2[4]
P2[4]
–
P2[4]–P2[6] (P2[4] =
VDD/2, P2[6] = 0.5 V)
P2[4] – P2[6]
– 0.030
P2[4] – P2[6]
P2[4] – P2[6] +
0.032
V
VDD
VDD – 0.102
VDD – 0.003
VDD
V
VAGND
AGND
VREFLO
Ref Low
VSS
VSS
VSS + 0.005
VSS + 0.020
V
VREFHI
Ref High
VDD
VDD – 0.082
VDD – 0.002
VDD
V
VDD/2
VDD/2 – 0.040 VDD/2 + 0.001 VDD/2 + 0.039
V
VAGND
AGND
VDD/2 – 0.031
VDD/2
VDD/2 + 0.028
V
VREFLO
Ref Low
VSS
VSS
VSS + 0.003
VSS + 0.015
V
VREFHI
Ref High
VDD
VDD – 0.083
VDD – 0.002
VDD
V
VDD/2
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
VDD
VAGND
AGND
VREFLO
Ref Low
–
–
Document Number: 001-14643 Rev. *L
VDD/2
VDD/2
VSS
–
VDD/2 – 0.032 VDD/2 – 0.001 VDD/2 + 0.029
V
VSS
VSS + 0.002
VSS + 0.014
V
VDD – 0.081
VDD – 0.002
VDD
V
VDD/2 – 0.033 VDD/2 – 0.001 VDD/2 + 0.029
V
VSS
VSS + 0.002
VSS + 0.013
V
–
–
–
–
Page 23 of 48
CY8C24533
Table 15. 3.3-V DC Analog Reference Specifications (continued)
Reference
ARF_CR
[5:3]
Reference Power
Settings
Symbol
Reference
Description
Typ
Max
Units
–
–
–
–
P2[4] + 1.211
P2[4] + 1.285
P2[4] + 1.348
V
P2[4]
P2[4]
P2[4]
–
0b100
All power settings
Not allowed at 3.3 V
–
–
0b101
RefPower = high
Opamp bias = high
VREFHI
Ref High
VAGND
AGND
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.354
P2[4] – 1.290
P2[4] – 1.197
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.209
P2[4] + 1.289
P2[4] + 1.353
V
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b110
RefPower = high
Opamp bias = high
RefPower = high
Opamp bias = low
RefPower = medium
Opamp bias = high
RefPower = medium
Opamp bias = low
0b111
All power settings
Not allowed at 3.3 V
–
Min
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4]
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.352
P2[4] – 1.294
P2[4] – 1.222
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.218
P2[4] + 1.291
P2[4] + 1.351
V
P2[4]
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.351
P2[4] – 1.296
P2[4] – 1.224
V
VREFHI
Ref High
P2[4] + Bandgap
(P2[4] = VDD/2)
P2[4] + 1.215
P2[4] + 1.292
P2[4] + 1.354
V
VAGND
AGND
P2[4]
P2[4]
P2[4]
–
VREFLO
Ref Low
P2[4] – Bandgap
(P2[4] = VDD/2)
P2[4] – 1.352
P2[4] – 1.297
P2[4] – 1.227
V
VREFHI
Ref High
2 × Bandgap
2.460
2.594
2.695
V
Bandgap
1.257
1.302
1.335
V
VSS
VSS + 0.01
VSS + 0.029
V
2.592
2.692
V
V
P2[4]
P2[4]
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
2 × Bandgap
2.462
Bandgap
1.256
1.301
1.332
VSS
VSS + 0.005
VSS + 0.017
V
2.593
2.682
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
2 × Bandgap
2.473
Bandgap
1.257
1.301
1.330
V
VSS
VSS + 0.003
VSS + 0.014
V
VAGND
AGND
VREFLO
Ref Low
VSS
VREFHI
Ref High
2 × Bandgap
2.470
2.594
2.685
V
VAGND
AGND
Bandgap
1.256
1.300
1.332
V
VREFLO
Ref Low
VSS
VSS + 0.002
VSS + 0.012
V
–
–
–
–
–
–
Document Number: 001-14643 Rev. *L
VSS
–
Page 24 of 48
CY8C24533
DC Analog PSoC Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 16. DC Analog PSoC Block Specifications
Symbol
Description
RCT
Resistor unit value (continuous time)
Min
–
Typ
12.2
Max
–
Units
k
DC POR and LVD Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register.
Table 17. DC POR and LVD Specifications
Symbol
Description
Min
Vdd value for PPOR trip
VPPOR0 PORLEV[1:0] = 00b
VPPOR1 PORLEV[1:0] = 01b
VPPOR2 PORLEV[1:0] = 10b
VLVD0
VLVD1
VLVD2
VLVD3
VLVD4
VLVD5
VLVD6
VLVD7
Vdd value for LVD trip
VM[2:0] = 000b
VM[2:0] = 001b
VM[2:0] = 010b
VM[2:0] = 011b
VM[2:0] = 100b
VM[2:0] = 101b
VM[2:0] = 110b
VM[2:0] = 111b
Typ
Max
Units
–
2.36
2.82
4.55
2.40
2.95
4.70
V
V
V
2.400
2.850
2.95
3.06
4.37
4.50
4.62
4.71
2.450
2.920
3.02
3.13
4.48
4.64
4.73
4.81
2.51[7]
2.99[8]
3.09
3.20
4.55
4.75
4.83
4.95
V0
V0
V0
V0
V0
V
V
V
Notes
Vdd must be greater than or
equal to 2.5 V during startup or
reset from watchdog.
Notes
7. Always greater than 50 mV above VPPOR (PORLEV=00) for falling supply.
8. Always greater than 50 mV above VPPOR (PORLEV=01) for falling supply.
Document Number: 001-14643 Rev. *L
Page 25 of 48
CY8C24533
DC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40° C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 18. DC Programming Specifications
Symbol
VDDP
Description
VDD for programming and erase
Min
4.5
Typ
5
Max
5.5
VDDLV
Low VDD for verify
3.0
3.1
3.2
VDDHV
High VDD for verify
5.1
5.2
5.3
VDDIWRITE
Supply voltage for flash write operation
3.0
–
5.25
IDDP
VILP
Supply current during programming or verify
Input low voltage during programming or
verify
Input high voltage during programming or
Verify
Input current when applying Vilp to P1[0] or
P1[1] during programming or verify
Input current when applying Vihp to P1[0] or
P1[1] during programming or verify
Output low voltage during programming or
verify
Output high voltage during programming or
verify
Flash endurance (per block)
Flash endurance (total)[10]
Flash data retention
–
–
5
–
25
0.8
2.1
–
–
V
–
–
0.2
mA
–
–
1.5
mA
–
–
Vss + 0.75
V
Vdd - 1.0
–
Vdd
V
50,000[9]
1,800,000
10
–
–
–
–
–
–
VIHP
IILP
IIHP
VOLV
VOHV
FlashENPB
FlashENT
FlashDR
Units
Notes
V
This specification applies to the
functional requirements of
external programmer tools
V
This specification applies to the
functional requirements of
external programmer tools
V
This specification applies to the
functional requirements of
external programmer tools
V
This specification applies to
this device when it is executing
internal flash writes
mA
V
Driving internal pull-down
resistor.
Driving internal pull-down
resistor.
–
Erase/write cycles per block.
–
Erase/write cycles.
Years
DC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 19. DC I2C Specifications[11]
Symbol
VILI2C
Input low level
Description
VIHI2C
Input high level
Min
–
–
0.7 × VDD
Typ
–
–
–
Max
0.3 × VDD
0.25 × VDD
–
Units
V
V
V
Notes
3.0 V VDD 3.6 V
4.75 V VDD 5.25 V
3.0 V VDD 5.25 V
Notes
9. The 50,000 cycle flash endurance per block will only be guaranteed if the flash is operating within one voltage range. Voltage ranges are 2.4 V TO 3.0 V, 3.0 V to
3.6 V and 4.75 V to 5.25 V.
10. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2
blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever
sees more than 50,000 cycles).
For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing.
Refer to the flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information.
11. All GPIOs meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I2C GPIO pins also meet the above specs.
Document Number: 001-14643 Rev. *L
Page 26 of 48
CY8C24533
SAR8 ADC DC Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 20. SAR8 ADC DC Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
VADCVREF
Reference voltage at Pin P3[0]
when configured as ADC reference
voltage
3.0
–
5.25
V
The voltage level at P3[0] (when configured as ADC
reference voltage) must always be maintained to be
less than chip supply voltage level on VDD pin.
VADCVREF < VDD.
IADCVREF
Current when P3[0] is configured as
ADC VREF
3
–
–
mA
INL
R-2R integral non-linearity[12]
–1.2
–
+1.2
LSB
The maximum LSB is over a sub-range not
exceeding 1/16 of the full scale range.
DNL
R-2R differential non-linearity[13]
–1
–
+1
LSB
Output is monotonic.
Notes
12. At the 7F and 80 points, the maximum INL is 1.5 LSB.
13. For the 7F to 80 transition, the DNL specification is waived.
Document Number: 001-14643 Rev. *L
Page 27 of 48
CY8C24533
AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 21. 5V and 3.3V AC Chip-Level Specifications
Symbol
FIMO24
Description
Internal main oscillator frequency
for 24 MHz
Min
22.8
Typ
24
25.2[14],[15],[16]
FIMO6
Internal main oscillator frequency
for 6 MHz
5.5
6
6.5[14],[15],[16]
FCPU1
CPU frequency (5-V nominal)
0.0937
24
24.6[14],[15]
Units
Notes
MHz Trimmed for 5 V or 3.3 V operation using factory
trim values. See Figure 4 on page 13. SLIMO
mode = 0.
MHz Trimmed for 5 V or 3.3 V operation using factory
trim values. See Figure 4 on page 13. SLIMO
mode = 1.
MHz SLIMO mode = 0.
FCPU2
CPU frequency (3.3-V nominal)
0.0937
12
12.3[15],[16]
MHz SLIMO mode = 0.
F48M
Digital PSoC block frequency
0
48
49.2[14],[15],[17]
F24M
Digital PSoC block frequency
0
24
MHz
F32K1
Internal low speed oscillator
frequency
External crystal oscillator
15
32
24.6[15],[17]
75
–
32.768
–
kHz
Internal low speed oscillator
untrimmed frequency
Internal low speed oscillator duty
cycle
PLL frequency
PLL lock time
PLL lock time for low gain setting
External crystal oscillator startup to
1%
External crystal oscillator startup to
100 ppm
5
–
100
kHz
20
50
80
%
–
0.5
0.5
–
23.986
–
–
1700
–
10
50
2620
–
2800
3800
10
40
–
46.8
–
50
50
48.0
–
60
–
–
–
49.2[14],[16]
12.3
–
–
–
16
250
100
V/ms
ms
–
200
700
ps
–
300
900
ps
–
–
100
200
400
800
ps
ps
–
300
1200
ps
–
100
700
ps
F32K2
F32K_U
DCILO
FPLL
TPLLSLEW
TPLLSLEWSLOW
TOS
TOSACC
TXRST
DC24M
Step24M
Fout48M
External reset pulse width
24-MHz duty cycle
24-MHz trim step size
48-MHz output frequency
FMAX
Maximum frequency of signal on
row input or row output.
Power supply slew rate
Time from end of POR to CPU
executing Code
24-MHz IMO cycle-to-cycle jitter
(RMS)
24-MHz IMO long term N
cycle-to-cycle jitter (RMS)
24-MHz IMO period jitter (RMS)
24-MHz IMO cycle-to-cycle jitter
(RMS)
24-MHz IMO long term N
cycle-to-cycle jitter (RMS)
24-MHz IMO period jitter (RMS)
SRPOWER_UP
TPOWERUP
tjit_IMO [18]
tjit_PLL [18]
Max
MHz Refer to the AC digital block specifications.
kHz
Accuracy is capacitor and crystal dependent.
50% duty cycle.
MHz Is a multiple (x732) of crystal frequency.
ms
ms
ms
ms
The crystal oscillator frequency is within 100 ppm
of its final value by the end of the Tosacc period.
Correct operation assumes a properly loaded 1
uW maximum drive level 32.768-kHz crystal.
3.0 V Vdd5.5 V, –40 °C TA 85 °C
s
%
kHz
MHz Trimmed. Using factory trim values.
MHz
N = 32
N = 32
Notes
14. 4.75 V < Vdd < 5.25 V.
15. Accuracy derived from internal main oscillator with appropriate trim for Vdd range.
16. 3.0 V < Vdd < 3.6 V.
17. See the individual user module data sheets for information on maximum frequencies for user modules.
18. Refer to Cypress jitter specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
Document Number: 001-14643 Rev. *L
Page 28 of 48
CY8C24533
Figure 8. PLL Lock Timing Diagram
PLL
Enable
TPLLSLEW
24 MHz
FPLL
PLL
Gain
0
Figure 9. PLL Lock for Low Gain Setting Timing Diagram
PLL
Enable
TPLLSLEWLOW
24 MHz
FPLL
PLL
Gain
1
Figure 10. External Crystal Oscillator Startup Timing Diagram
32K
Select
32 kHz
TOS
F32K2
Document Number: 001-14643 Rev. *L
Page 29 of 48
CY8C24533
AC GPIO Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 22. 5-V and 3.3-V AC GPIO Specifications
Symbol
FGPIO
TRiseF
TFallF
TRiseS
TFallS
Description
GPIO operating frequency
Rise time, Normal strong mode, Cload = 50 pF
Fall time, Normal strong mode, Cload = 50 pF
Rise time, Slow strong mode, Cload = 50 pF
Fall Time, Slow strong mode, Cload = 50 pF
Min
0
3
2
10
10
Typ
–
–
–
27
22
Max
12
18
18
–
–
Units
MHz
ns
ns
ns
ns
Notes
Normal strong mode
VDD = 4.5 to 5.25 V, 10% - 90%
VDD = 4.5 to 5.25 V, 10% - 90%
VDD = 3 to 5.25 V, 10% - 90%
VDD = 3 to 5.25 V, 10% - 90%
Figure 11. GPIO Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
Document Number: 001-14643 Rev. *L
TFallF
TFallS
Page 30 of 48
CY8C24533
AC Operational Amplifier Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Settling times, slew rates, and gain bandwidth are based on the analog continuous time PSoC block.
Power = High and opamp Bias = High is not supported at 3.3 V.
Table 23. 5-V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
Description
Rising settling time from 80% of V to 0.1% of V (10 pF load, Unity gain)
Power = Low, opamp bias = Low
Power = Medium, opamp bias = High
Power = High, opamp bias = High
Falling settling time from 20% of V to 0.1% of V (10 pF load, Unity gain)
Power = Low, opamp bias = Low
Power = Medium, opamp bias = High
Power = High, opamp bias = High
Rising slew rate (20% to 80%)(10 pF load, Unity gain)
Power = Low, opamp bias = Low
Power = Medium, opamp bias = High
Power = High, opamp bias = High
Falling slew rate (20% to 80%)(10 pF load, Unity gain)
Power = Low, opamp bias = Low
Power = Medium, opamp bias = High
Power = High, opamp bias = High
Gain bandwidth product
Power = Low, opamp bias = Low
Power = Medium, opamp bias = High
Power = High, opamp bias = High
Min
Typ
Max
Units
–
–
–
–
–
–
3.9
0.72
0.62
s
s
s
–
–
–
–
–
–
5.9
0.92
0.72
s
s
s
0.15
1.7
6.5
–
–
–
–
–
–
V/s
V/s
V/s
0.01
0.5
4.0
–
–
–
–
–
–
V/s
V/s
V/s
0.75
3.1
5.4
–
–
–
–
–
–
MHz
MHz
MHz
Min
Typ
Max
Units
–
–
–
–
3.92
0.72
s
s
–
–
–
–
5.41
0.72
s
s
0.31
2.7
–
–
–
–
V/s
V/s
0.24
1.8
–
–
–
–
V/s
V/s
0.67
2.8
–
–
–
–
MHz
MHz
Table 24. 3.3-V AC Operational Amplifier Specifications
Symbol
TROA
TSOA
SRROA
SRFOA
BWOA
Description
Rising settling time from 80% of V to 0.1% of V (10-pF load, Unity gain)
Power = Low, opamp bias = Low
Power = Medium, opamp bias = High
Falling settling time from 20% of V to 0.1% of V
(10-pF load, Unity gain)
Power = Low, Opamp bias = Low
Power = Medium, Opamp bias = High
Rising slew rate (20% to 80%) (10-pF load, Unity Gain)
Power = Low, opamp bias = Low
Power = Medium, opamp bias = High
Falling slew rate (20% to 80%) (10-pF load, Unity Gain)
Power = Low, opamp bias = Low
Power = Medium, Opamp bias = High
Gain bandwidth product
Power = Low, Opamp bias = Low
Power = Medium, Opamp bias = High
Document Number: 001-14643 Rev. *L
Page 31 of 48
CY8C24533
When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up
to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1 k resistance and the external capacitor.
Figure 12. Typical AGND Noise with P2[4] Bypass
nV/rtHz
10000
0
0.01
0.1
1.0
10
1000
100
0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high
frequencies, increased power level reduces the noise spectrum level.
Figure 13. Typical Opamp Noise
nV/rtHz
10000
PH_BH
PH_BL
PM_BL
PL_BL
1000
100
10
0.001
Document Number: 001-14643 Rev. *L
0.01
0.1
Freq (kHz)
1
10
100
Page 32 of 48
CY8C24533
AC Low Power Comparator Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 25. AC Low Power Comparator Specifications
Symbol
TRLPC
Description
LPC response time
Min
–
Typ
–
Max
50
Units
s
Notes
50 mV overdrive comparator
reference set within VREFLPC.
AC Digital Block Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 26. 5-V and 3.3-V AC Digital Block Specifications
Function
All functions
Timer
Counter
Dead Band
CRCPRS
(PRS
Mode)
CRCPRS
(CRC
Mode)
SPIM
SPIS
Description
Block input clock frequency
VDD 4.75 V
VDD < 4.75 V
Input clock frequency
No capture, VDD 4.75 V
No capture, VDD < 4.75 V
With capture
Capture pulse width
Input clock frequency
No enable input, VDD 4.75 V
No enable input, VDD < 4.75 V
With enable input
Enable input pulse width
Kill pulse width
Asynchronous restart mode
Synchronous restart mode
Disable mode
Input clock frequency
VDD 4.75 V
VDD < 4.75 V
Input clock frequency
VDD 4.75 V
VDD < 4.75 V
Input clock frequency
Input clock frequency
Input clock (SCLK) frequency
Width of SS_negated between
transmissions
Min
Typ
Max
Unit
–
–
–
–
49.2
24.6
MHz
MHz
–
–
–
50[19]
–
–
–
–
49.2
24.6
24.6
–
MHz
MHz
MHz
ns
–
–
–
50[19]
–
–
–
–
49.2
24.6
24.6
–
MHz
MHz
MHz
ns
20
50[19]
50[19]
–
–
–
–
–
–
ns
ns
ns
–
–
–
–
49.2
24.6
MHz
MHz
–
–
–
–
–
–
49.2
24.6
24.6
MHz
MHz
MHz
–
–
8.2
MHz
–
50[19]
–
–
4.1
–
MHz
ns
Notes
The SPI serial clock (SCLK) frequency is equal to
the input clock frequency divided by 2.
The input clock is the SPI SCLK in SPIS mode.
Note
19. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42-ns nominal period).
Document Number: 001-14643 Rev. *L
Page 33 of 48
CY8C24533
Table 26. 5-V and 3.3-V AC Digital Block Specifications (continued)
Function
Transmitter
Receiver
Description
Input clock frequency
VDD 4.75 V, 2 stop bits
VDD 4.75 V, 1 stop bit
VDD < 4.75 V
Input clock frequency
VDD 4.75 V, 2 stop bits
VDD 4.75 V, 1 stop bit
VDD < 4.75 V
Min
Typ
Max
Unit
–
–
–
–
–
–
49.2
24.6
24.6
MHz
MHz
MHz
Notes
The baud rate is equal to the input clock frequency
divided by 8.
The baud rate is equal to the input clock frequency
divided by 8.
–
–
–
–
–
–
49.2
24.6
24.6
MHz
MHz
MHz
AC Analog Output Buffer Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 27. 5-V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOB
BWOB
Description
Rising settling time to 0.1%, 1 V Step, 100 pF load
Power = Low
Power = High
Falling settling time to 0.1%, 1 V Step, 100 pF load
Power = Low
Power = High
Rising slew rate (20% to 80%), 1 V Step, 100 pF load
Power = Low
Power = High
Falling slew rate (80% to 20%), 1 V Step, 100 pF load
Power = Low
Power = High
Small signal bandwidth, 20mVpp, 3dB BW, 100 pF load
Power = Low
Power = High
Large signal bandwidth, 1Vpp, 3dB BW, 100 pF load
Power = Low
Power = High
Min
Typ
Max
Units
–
–
–
–
2.5
2.5
s
s
–
–
–
–
2.2
2.2
s
s
0.65
0.65
–
–
–
–
V/s
V/s
0.65
0.65
–
–
–
–
V/s
V/s
0.8
0.8
–
–
–
–
MHz
MHz
300
300
–
–
–
–
kHz
kHz
Min
Typ
Max
Units
–
–
–
–
3.8
3.8
s
s
–
–
–
–
2.6
2.6
s
s
0.5
0.5
–
–
–
–
V/s
V/s
0.5
0.5
–
–
–
–
V/s
V/s
0.7
0.7
–
–
–
–
MHz
MHz
200
200
–
–
–
–
kHz
kHz
Table 28. 3.3-V AC Analog Output Buffer Specifications
Symbol
TROB
TSOB
SRROB
SRFOB
BWOB
BWOB
Description
Rising settling time to 0.1%, 1-V Step, 100-pF Load
Power = Low
Power = High
Falling Settling Time to 0.1%, 1-V Step, 100-pF load
Power = Low
Power = High
Rising slew rate (20% to 80%), 1-V Step, 100-pF load
Power = Low
Power = High
Falling slew rate (80% to 20%), 1-V Step, 100-pF load
Power = Low
Power = High
Small signal bandwidth, 20mVpp, 3dB BW, 100-pF load
Power = Low
Power = High
Large signal bandwidth, 1Vpp, 3dB BW, 100-pF load
Power = Low
Power = High
Document Number: 001-14643 Rev. *L
Page 34 of 48
CY8C24533
AC External Clock Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 29. 5-V AC External Clock Specifications
Symbol
Description
Min
Typ
Max
Units
FOSCEXT
Frequency
0.093
–
24.6
MHz
–
High period
20.6
–
5300
ns
–
Low period
20.6
–
–
ns
–
Power up IMO to switch
150
–
–
s
Min
Typ
Max
Units
0.093
–
12.3
MHz
Table 30. 3.3-V AC External Clock Specifications
Symbol
FOSCEXT
Description
Frequency with CPU clock divide by
1[20]
greater[21]
FOSCEXT
Frequency with CPU clock divide by 2 or
0.186
–
24.6
MHz
–
High period with CPU clock divide by 1
41.7
–
5300
ns
–
Low period with CPU clock divide by 1
41.7
–
–
ns
–
Power up iMO to switch
150
–
–
s
AC Programming Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 31. AC Programming Specifications
Symbol
Description
Min
Typ
Max
Units
Notes
TRSCLK
Rise time of SCLK
1
–
20
ns
TFSCLK
fall time of sclk
1
–
20
ns
TSSCLK
Data set up time to falling edge of SCLK
40
–
–
ns
THSCLK
Data hold time from falling edge of SCLK
40
–
–
ns
FSCLK
Frequency of SCLK
0
–
8
MHz
TERASEB
Flash erase time (Block)
–
20
–
ms
TWRITE
Flash block write time
–
80
–
ms
TDSCLK
Data out delay from falling edge of SCLK
–
–
45
ns
VDD 3.6
TDSCLK3
Data out delay from falling edge of SCLK
–
–
50
ns
3.0 VDD 3.6
TERASEALL
Flash erase time (Bulk)
–
20
–
ms
Erase all blocks and
protection fields at
once.
TPROGRAM_HOT
Flash block erase + Flash block write time
–
–
200
ms
0 °C TJ 100 °C
TPROGRAM_COLD Flash block erase + Flash block write time
–
–
400
ms
–40 °C TJ 0 °C
Notes
20. Maximum CPU frequency is 12 MHz at 3.3 V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements.
21. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider ensures that the
fifty percent duty cycle requirement is met.
Document Number: 001-14643 Rev. *L
Page 35 of 48
CY8C24533
SAR8 ADC AC Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 32. SAR8 ADC AC Specifications
Symbol
Description
Min
Typ
Max
Units
Freq3
Input clock frequency 3 V
–
–
3.0
MHz
Freq5
Input clock frequency 5 V
–
–
3.0
MHz
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V
and –40 °C TA 85 °C, or 3.0 V to 3.6 V and –40 °C TA 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C
and are for design guidance only.
Table 33. AC Characteristics of the I2C SDA and SCL Pins for VDD > 3.0 V
Symbol
Description
Standard-Mode
Min
Max
Fast-Mode
Min
Max
Units
FSCLI2C
SCL clock frequency
0
100
0
400
kHz
THDSTAI2C
Hold time (repeated) START condition. After this period,
the first clock pulse is generated.
4.0
–
0.6
–
s
TLOWI2C
LOW period of the SCL Clock
4.7
–
1.3
–
s
THIGHI2C
HIGH period of the SCL Clock
4.0
–
0.6
–
s
TSUSTAI2C
Setup time for a repeated START condition
4.7
–
0.6
–
s
THDDATI2C
Data hold time
0
–
0
–
s
TSUDATI2C
Data setup time
250
–
–
ns
TSUSTOI2C
Setup time for STOP condition
4.0
–
0.6
–
s
TBUFI2C
Bus free time between a STOP and START Condition
4.7
–
1.3
–
s
TSPI2C
Pulse width of spikes are suppressed by the input filter.
–
–
0
50
ns
[22]
100
Table 34. AC Characteristics of the I2C SDA and SCL Pins for VDD 3.0 V (Fast-Mode Not Supported)
Symbol
Description
Standard-Mode
Fast-Mode
Min
Max
Min
Max
Units
FSCLI2C
SCL clock frequency
0
100
–
–
kHz
THDSTAI2C
Hold time (repeated) START condition. After this period,
the first clock pulse is generated.
4.0
–
–
–
s
TLOWI2C
LOW period of the SCL Clock
4.7
–
–
–
s
THIGHI2C
HIGH period of the SCL Clock
4.0
–
–
–
s
TSUSTAI2C
Setup time for a repeated START condition
4.7
–
–
–
s
THDDATI2C
Data hold time
0
–
–
–
s
TSUDATI2C
Data setup time
250
–
–
–
ns
TSUSTOI2C
Setup time for STOP condition
4.0
–
–
–
s
TBUFI2C
Bus free time between a STOP and START condition
4.7
–
–
–
s
TSPI2C
Pulse width of spikes are suppressed by the input filter.
–
–
–
–
ns
Document Number: 001-14643 Rev. *L
Page 36 of 48
CY8C24533
Figure 14. Definition for Timing for Fast-/Standard-Mode on the I2C Bus
I2C_SDA
TSUDATI2C
THDSTAI2C
TSPI2C
THDDATI2CTSUSTAI2C
TBUFI2C
I2C_SCL
THIGHI2C TLOWI2C
S
START Condition
TSUSTOI2C
Sr
Repeated START Condition
P
S
STOP Condition
Note
22. A Fast-Mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This is automatically the case
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 001-14643 Rev. *L
Page 37 of 48
CY8C24533
Packaging Information
This section illustrates the packaging specifications for the CY8C24533 PSoC device, along with the thermal impedances for each
package, solder reflow peak temperature, and the typical package capacitance on crystal pins.
Figure 15. 28-Pin (210-Mil) SSOP
51-85079 *F
Thermal Impedances
Table 35. Thermal Impedances by Package
Package
Typical JA [23]
28-pin SSOP
95°C/W
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 36. Solder Reflow Peak Temperature
Package
Maximum Peak Temperature
Time at Maximum Peak Temperature
28-pin SSOP
260 °C
30 s
Notes
23. TJ = TA + POWER x JA .
Document Number: 001-14643 Rev. *L
Page 38 of 48
CY8C24533
Ordering Information
The following table lists the CY8C24533 PSoC device family key package features and ordering codes.
Temperature
Range
Digital Blocks
(Rows of 4)
Analog Blocks
(Columns of 3)
Digital I/O Pins
Analog Inputs
Analog Outputs
XRES Pin
CY8C24533-24PVXI
CY8C24533-24PVXIT
RAM
(Bytes)
28-pin (210 Mil) SSOP
28-pin (210 Mil) SSOP
(Tape and Reel)
Flash
(Kbytes)
Package
Ordering
Code
Table 37. CY8C24533 PSoC Device Family Key Features and Ordering Information
8
8
256
256
–40 °C to +85 °C
–40 °C to +85 °C
4
4
4
4
26
26
12
12
2
2
No
No
Ordering Code Definitions
CY 8 C 24 XXX- SP XX
Package Type:
PX = PDIP Pb-free
SX = SOIC Pb-free
PVX = SSOP Pb-free
LFX/LKX/LQX/LTX = QFN Pb-free
AX = TQFP Pb-free
BVX = VFBGA Pb-free
Speed: 24 MHz
Thermal Rating:
C = Commercial
I = Industrial
E = Extended
Part Number
Family Code
Technology Code: C = CMOS
Marketing Code: 8 = PSoC
Company ID: CY = Cypress
Document Number: 001-14643 Rev. *L
Page 39 of 48
CY8C24533
Acronyms
Acronyms Used
Table 38 lists the acronyms that are used in this document.
Table 38. Acronyms Used in this Datasheet
Acronym
AC
ADC
Description
Acronym
Description
alternating current
MCU
microcontroller unit
analog-to-digital converter
MIPS
million instructions per second
printed circuit board
API
application programming interface
PCB
CPU
central processing unit
PGA
programmable gain amplifier
CRC
cyclic redundancy check
PLL
phase-locked loop
POR
power-0on reset
CT
DAC
continuous time
digital-to-analog converter
PPOR
precision power on reset
DC
direct current
PRS
pseudo-random sequence
DNL
differential nonlinearity
PSoC
Programmable System-on-Chip
DTMF
dual-tone multi-frequency
PWM
pulse width modulator
ECO
external crystal oscillator
RTC
real time clock
electrically erasable programmable read-only
memory
SAR
successive approximation
EEPROM
GPIO
general purpose I/O
SC
SLIMO
switched capacitor
ICE
in-circuit emulator
slow IMO
IDE
integrated development environment
SMP
switch-mode pump
SOIC
small-outline integrated circuit
ILO
internal low speed oscillator
IMO
internal main oscillator
INL
integral nonlinearity
SRAM
static random access memory
I/O
SPI
serial peripheral interface
input/output
SROM
supervisory read only memory
IrDA
infrared data association
SSOP
shrink small-outline package
ISSP
in-system serial programming
UART
universal asynchronous reciever / transmitter
LPC
low power comparator
USB
universal serial bus
LVD
low-voltage detect
WDT
watchdog timer
MAC
multiply-accumulate
XRES
external reset
Reference Documents
PSoC® 1 - Getting Started with Flash & E2PROM – AN2015 (001-40459)
Document Number: 001-14643 Rev. *L
Page 40 of 48
CY8C24533
Document Conventions
Units of Measure
Table 39 lists the units of measures.
Table 39. Units of Measure
Symbol
Unit of Measure
Symbol
Unit of Measure
kB
1024 bytes
ms
millisecond
dB
decibels
ns
nanosecond
picosecond
°C
degree Celsius
ps
pF
picofarads
µV
microvolts
kHz
kilohertz
mV
millivolts
MHz
megahertz
nV
nanovolts
LSB
least significant bit
V
volts
k
kilo-ohm
µW
µA
microamperes
W
microwatts
mA
milliamperes
mm
millimeter
nA
nanoamperes
ppm
parts per million
pA
pikoamperes
%
µs
microsecond
watt
percent
Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’).
Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended
lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimals.
Document Number: 001-14643 Rev. *L
Page 41 of 48
CY8C24533
Glossary
active high
1. A logic signal having its asserted state as the logic 1 state.
2. A logic signal having the logic 1 state as the higher voltage of the two states.
analog blocks
The basic programmable opamp circuits. These are switched capacitor (SC) and continuous
time (CT) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain
stages, and much more.
analog-to-digital
(ADC)
A device that changes an analog signal to a digital signal of corresponding magnitude. Typically,
an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs
the reverse operation.
API (Application
Programming
Interface)
A series of software routines that comprise an interface between a computer application and
lower level services and functions (for example, user modules and libraries). APIs serve as
building blocks for programmers that create software applications.
asynchronous
A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal.
Bandgap
reference
A stable voltage reference design that matches the positive temperature coefficient of VT with
the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally)
reference.
bandwidth
1. The frequency range of a message or information processing system measured in hertz.
2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or
loss); it is sometimes represented more specifically as, for example, full width at half maximum.
bias
1. A systematic deviation of a value from a reference value.
2. The amount by which the average of a set of values departs from a reference value.
3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a
reference level to operate the device.
block
1. A functional unit that performs a single function, such as an oscillator.
2. A functional unit that may be configured to perform one of several functions, such as a digital
PSoC block or an analog PSoC block.
buffer
1. A storage area for data that is used to compensate for a speed difference, when transferring
data from one device to another. Usually refers to an area reserved for IO operations, into
which data is read, or from which data is written.
2. A portion of memory set aside to store data, often before it is sent to an external device or as
it is received from an external device.
3. An amplifier used to lower the output impedance of a system.
bus
1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets
with similar routing patterns.
2. A set of signals performing a common function and carrying similar data. Typically represented
using vector notation; for example, address[7:0].
3. One or more conductors that serve as a common connection for a group of related devices.
clock
The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is
sometimes used to synchronize different logic blocks.
comparator
An electronic circuit that produces an output voltage or current whenever two input levels simultaneously
satisfy predetermined amplitude requirements.
Document Number: 001-14643 Rev. *L
Page 42 of 48
CY8C24533
Glossary
(continued)
compiler
A program that translates a high level language, such as C, into machine language.
configuration
space
In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register,
is set to ‘1’.
crystal oscillator
An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric
crystal is less sensitive to ambient temperature than other circuit components.
cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear
check (CRC)
feedback shift register. Similar calculations may be used for a variety of other purposes such as
data compression.
data bus
A bi-directional set of signals used by a computer to convey information from a memory location
to the central processing unit and vice versa. More generally, a set of signals used to convey
data between digital functions.
debugger
A hardware and software system that allows the user to analyze the operation of the system
under development. A debugger usually allows the developer to step through the firmware one
step at a time, set break points, and analyze memory.
dead band
A period of time when neither of two or more signals are in their active state or in transition.
digital blocks
The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC
generator, pseudo-random number generator, or SPI.
digital-to-analog
(DAC)
A device that changes a digital signal to an analog signal of corresponding magnitude. The analogto-digital (ADC) converter performs the reverse operation.
duty cycle
The relationship of a clock period high time to its low time, expressed as a percent.
emulator
Duplicates (provides an emulation of) the functions of one system with a different system, so that
the second system appears to behave like the first system.
external reset
(XRES)
An active high signal that is driven into the PSoC device. It causes all operation of the CPU and
blocks to stop and return to a pre-defined state.
flash
An electrically programmable and erasable, non-volatile technology that provides users with the
programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means
that the data is retained when power is off.
Flash block
The smallest amount of flash ROM space that may be programmed at one time and the smallest
amount of flash space that may be protected. A flash block holds 64 bytes.
frequency
The number of cycles or events per unit of time, for a periodic function.
gain
The ratio of output current, voltage, or power to input current, voltage, or power, respectively.
Gain is usually expressed in dB.
I2C
A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an
Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The
original system was created in the early 1980s as a battery control interface, but it was later used
as a simple internal bus system for building control electronics. I2C uses only two bi-directional
pins, clock and data, both running at +5 V and pulled high with resistors. The bus operates at 100
kbits/second in standard mode and 400 kbits/second in fast mode.
Document Number: 001-14643 Rev. *L
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CY8C24533
Glossary
(continued)
ICE
The in-circuit emulator that allows users to test the project in a hardware environment, while
viewing the debugging device activity in a software environment (PSoC Designer).
input/output (I/O) A device that introduces data into or extracts data from a system.
interrupt
A suspension of a process, such as the execution of a computer program, caused by an event
external to that process, and performed in such a way that the process can be resumed.
interrupt service
routine (ISR)
A block of code that normal code execution is diverted to when the M8C receives a hardware
interrupt. Many interrupt sources may each exist with its own priority and individual ISR code
block. Each ISR code block ends with the RETI instruction, returning the device to the point in
the program where it left normal program execution.
jitter
1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on
serial data streams.
2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between
successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
low-voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a
(LVD)
selected threshold.
M8C
An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside
a PSoC by interfacing to the flash, SRAM, and register space.
master device
A device that controls the timing for data exchanges between two devices. Or when devices are
cascaded in width, the master device is the one that controls the timing for data exchanges
between the cascaded devices and an external interface. The controlled device is called the slave device.
microcontroller
An integrated circuit chip that is designed primarily for control systems and products. In addition
to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason
for this is to permit the realization of a controller with a minimal quantity of chips, thus
achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of
the controller. The microcontroller is normally not used for general-purpose computation as is a
microprocessor.
mixed-signal
The reference to a circuit containing both analog and digital techniques and components.
modulator
A device that imposes a signal on a carrier.
noise
1. A disturbance that affects a signal and that may distort the information carried by the signal.
2. The random variations of one or more characteristics of any entity such as voltage, current, or data.
oscillator
A circuit that may be crystal controlled and is used to generate a clock frequency.
parity
A technique for testing transmitting data. Typically, a binary digit is added to the data to make the
sum of all the digits of the binary data either always even (even parity) or always odd (odd parity).
phase-locked
loop (PLL)
An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative
to a reference signal.
pinouts
The pin number assignment: the relation between the logical inputs and outputs of the PSoC
device and their physical counterparts in the printed circuit board (PCB) package. Pinouts
involve pin numbers as a link between schematic and PCB design (both being computer generated
files) and may also involve pin names.
Document Number: 001-14643 Rev. *L
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CY8C24533
Glossary
(continued)
port
A group of pins, usually eight.
power on reset
(POR)
A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is
one type of hardware reset.
PSoC®
Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-onChip™ is a trademark of Cypress.
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology.
pulse width
An output in the form of duty cycle which varies as a function of the applied measurand
modulator (PWM)
RAM
An acronym for random access memory. A data-storage device from which data can be read out
and new data can be written in.
register
A storage device with a specific capacity, such as a bit or byte.
reset
A means of bringing a system back to a know state. See hardware reset and software reset.
ROM
An acronym for read only memory. A data-storage device from which data can be read out, but
new data cannot be written in.
serial
1. Pertaining to a process in which all events occur one after the other.
2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or
channel.
settling time
The time it takes for an output signal or value to stabilize after the input has changed from one
value to another.
shift register
A memory storage device that sequentially shifts a word either left or right to output a stream of
serial data.
slave device
A device that allows another device to control the timing for data exchanges between two
devices. Or when devices are cascaded in width, the slave device is the one that allows another
device to control the timing of data exchanges between the cascaded devices and an external
interface. The controlling device is called the master device.
SRAM
An acronym for static random access memory. A memory device allowing users to store and
retrieve data at a high rate of speed. The term static is used because, after a value has been
loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is
removed from the device.
SROM
An acronym for supervisory read only memory. The SROM holds code that is used to boot the
device, calibrate circuitry, and perform flash operations. The functions of the SROM may be
accessed in normal user code, operating from flash.
stop bit
A signal following a character or block that prepares the receiving device to receive the next
character or block.
synchronous
1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal.
2. A system whose operation is synchronized by a clock signal.
Document Number: 001-14643 Rev. *L
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CY8C24533
Glossary
(continued)
tri-state
A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does
not drive any value in the Z state and, in many respects, may be considered to be disconnected
from the rest of the circuit, allowing another output to drive the same net.
UART
A UART or universal asynchronous receiver-transmitter translates between parallel bits of data
and serial bits.
user modules
Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and
configuring the lower level analog and Digital PSoC Blocks. User modules also provide high
level API (Application Programming Interface) for the peripheral function.
user space
The bank 0 space of the register map. The registers in this bank are more likely to be modified
during normal program execution and not just during initialization. Registers in bank 1 are most
likely to be modified only during the initialization phase of the program.
VDD
A name for a power net meaning "voltage drain." The most positive power supply signal.
Usually 5 V or 3.3 V.
VSS
A name for a power net meaning "voltage source." The most negative power supply signal.
watchdog timer
A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.
Document Number: 001-14643 Rev. *L
Page 46 of 48
CY8C24533
Document History Page .
Document Title: CY8C24533 PSoC® Programmable System-on-Chip™
Document Number: 001-14643
Rev
ECN
Orig. of
Change
Submission
Date
**
998721
VED
See ECN
New spec.
*A
1149184
HMT
See ECN
Update Advance to Preliminary. Update features, pinouts, registers, specs.,
packages, package data, and order information. Convert to new Cypress template.
*B
1411003
HMT
See ECN
Update formatting edits. Split out device. Update registers and electrical specs.
Convert Table Notes to Cypress template style.
*C
1648723
HMT
See ECN
Update SAR ADC electrical specs. Update INL, DNL, and VOL specs. Finetune
specs. Make data sheet Final.
*D
2616862 OGNE/AESA
12/05/2008
Changed title to: “CY8C24533 PSoC® Programmable System-on-Chip™”
Changed names of registers on page 10.
"SARADC_C0" to "SARADC_CR0"
"SARADC_C1" to "SARADC_CR1"
*E
2861699
JHU/HMT
01/20/2010
Add Table of Contents.
Update DC GPIO, AC Chip-Level, and AC Programming Specifications as
follows:
Replace TRAMP (time) with SRPOWER_UP (slew rate) specification.
Added IOH, IOL, DCILO, F32K_U, TPOWERUP, TERASEALL, TPROGRAM_HOT,
and TPROGRAM_COLD specifications.
Update copyright and Sales, Solutions, and Legal Information URLs.
Update 28-Pin SSOP package diagram.
*F
2902396
NJF
03/30/2010
Updated Cypress website links.
Updated Features.
Added TBAKETEMP and TBAKETIME parameters in Absolute Maximum Ratings.
Updated 5V and 3.3V AC Chip-Level Specifications.
Updated links in Sales, Solutions, and Legal Information.
*G
3135262
NJF
01/12/11
Updated PSoC Device Characteristics table .
Added DC I2C Specifications table.
Added Tjit_IMO specification, removed existing jitter specifications.
Updated DC Analog Reference Specifications and 3.3 V DC operational amplifier
specifications tables.
Updated Units of Measure, Acronyms, Glossary, and References sections.
Updated solder reflow specifications.
No specific changes were made to AC Digital Block Specifications table and I2C
Timing Diagram. They were updated for clearer understanding.
Updated Figure 12 since the labelling for y-axis was incorrect.
Added ordering code definitions.
*H
3331742
SHOB
07/29/11
Updated Getting Started, Development Tools, and Designing with PSoC Designer.
Updated Solder Reflow Peak Temperature table
Removed reference to obsolete Application Note AN2012.
SHOB
08/09/11
Description of Change
*I
3340625
*J
3598339 LURE/XZNG
04/24/2012
*K
3747663
PMAD
09/18/2012
Removed reference to obsolete spec (001-14503).
*L
4644206
SEG
01/29/2015
Corrected the units for ROUTOB parameter.
Updated 28-Pin (210-Mil) SSOP package diagram.
Updated Sales, Solutions, and Legal Information based on the template.
Document Number: 001-14643 Rev. *L
Correction in ECN number for *H.
Changed the PWM description string from “8- to 32-bit” to “8- and 16-bit”.
Page 47 of 48
CY8C24533
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Automotive
Clocks & Buffers
Interface
Lighting & Power Control
Memory
cypress.com/go/automotive
cypress.com/go/clocks
cypress.com/go/interface
cypress.com/go/powerpsoc
cypress.com/go/memory
PSoC
Touch Sensing
cypress.com/go/psoc
cypress.com/go/touch
USB Controllers
Wireless/RF
psoc.cypress.com/solutions
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
Cypress Developer Community
Community | Forums | Blogs | Video | Training
Technical Support
cypress.com/go/support
cypress.com/go/USB
cypress.com/go/wireless
© Cypress Semiconductor Corporation, 2007-2015. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-14643 Rev. *L
Revised January 29, 2015
Page 48 of 48
PSoC Designer™ is a trademark and PSoC® is a registered trademark of Cypress Semiconductor Corporation.
Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors.
All products and company names mentioned in this document may be the trademarks of their respective holders.
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