CY8C26233-24SIT

end m m o c Not Re Des w e N r ed f o xxx 7 2 C 8 e CY s U : s i gn Configurable Mixed-Signal Array with On-board Controller CY8C25122, CY8C26233, CY8C26443, CY8C26643 Device Data Sheet for Silicon Revision D Programmable System-on-Chip (PSoC™) May 17, 2005 Document #: 38-12010 CY Rev. *C 1 CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet Getting Started in the PSoC World! The award winning PSoC Designer software and PSoC silicon are an integrated unit. The quickest path to understanding the PSoC silicon is through the PSoC Designer software GUI. This data sheet is useful for understanding the details of the PSOC integrated circuit, but is not a good starting point for a new PSoC developer seeking to get a general overview of this new technology. PSoC developers are NOT required to build their own ADCs, DACs, and other peripherals. Embedded in the PSoC Designer software are the individual data sheets, performance graphs, and PSoC User Modules (graphically selected code packets) for the peripherals, such as the incremental ADCs, DACs, LCD controllers, op amps, low-pass filters, etc. With simple GUI-based selection, placement, and connection, the basic architecture of a design may be developed within PSoC Designer software without ever writing a single line of code. Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store also contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items. Free PSoC technical training is available for beginners and is taught by a marketing or application engineer over the phone. PSoC training classes cover designing, debugging, advanced analog, as well as application-specific classes covering topics such as PSoC and the LIN bus. Go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select Technical Training for more details. Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select CYPros Consultants. PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm. Cypress Semiconductor 2700 162nd Street SW, Building D Lynnwood, WA 98037 Phone: 425.787.4400 Fax: 425.787.4641 Application Support Hotline: 425.787.4814 © Cypress Semiconductor Corporation. 2000-2005. All rights reserved. PSoC™, PSoC Designer™, and Programmable System-on-Chip™ are PSoCrelated trademarks of Cypress Semiconductor Corporation. All other trademarks or registered trademarks referenced herein are property of the respective corporations. The information contained herein is subject to change without notice. Cypress Semiconductor assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress Semiconductor products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress Semiconductor. Note the following details of the Flash code protection features on Cypress Semiconductor PSoC devices. Cypress Semiconductor products meet the specifications contained in their particular Cypress Semiconductor Data Sheets. Cypress Semiconductor believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress Semiconductor, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress Semiconductor nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Cypress Semiconductor is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress Semiconductor are committed to continuously improving the code protection features of our products. 2 Document #: 38-12010 CY Rev. *C May 17, 2005 The PSoC™ CY8C25122/CY8C26233/CY8C26443/CY8C26643 family of programmable system-on-chip devices replace multiple MCU-based system components with one single-chip, configurable device. A PSoC device includes configurable analog and digital peripheral blocks, a fast CPU, Flash program memory, and SRAM data memory in a range of convenient pin-outs and memory sizes. The driving force behind this innovative programmable system-on-chip comes from user configurability of the analog and digital arrays: the PSoC blocks. end m m o c Not Re Des w e N r ed f o xxx 7 2 C 8 e CY s U : s i gn Programmable System-on-Chip (PSoC™) Blocks ƒ Partial Flash updates ƒ On-chip, user configurable analog and digital peripheral blocks ƒ Flexible protection modes ƒ PSoC blocks can be used individually or in combination ƒ EEPROM emulation in Flash, up to 2,304 bytes ƒ 12 Analog PSoC blocks provide: ƒUp to 11-bit Delta-Sigma ADC ƒUp to 8-bit Successive Approximation ADC ƒUp to 12-bit Incremental ADC ƒUp to 9-bit DAC ƒProgrammable gain amplifier ƒProgrammable filters ƒDifferential comparators ƒ 8 Digital PSoC blocks provide: ƒMultipurpose timers: event timing, real-time clock, pulse width modulation (PWM) and PWM with deadband ƒCRC modules ƒFull-duplex UARTs ƒSPI™ master or slave configuration ƒFlexible clocking sources for analog PSoC blocks Powerful Harvard Architecture Processor with Fast Multiply/Accumulate ƒ ƒ ƒ ƒ ƒ ƒ M8C processor instruction set Programmable Pin Configurations ƒ Schmitt trigger TTL I/O pins ƒ Logic output drive to 25 mA with internal pull-up or pull-down resistors, High Z, or strong driver ƒ Interrupt on pin change ƒ Analog output drive to 40 mA Precision, Programmable Clocking ƒ Internal 24/48 MHz Oscillator (+/- 2.5%, no external components) ƒ External 32.768 kHz Crystal Oscillator (optional precision source for PLL) ƒ Internal Low Speed Oscillator for Watchdog and Sleep Dedicated Peripherals ƒ Watchdog and Sleep Timers ƒ Low Voltage Detection with user-configurable threshold voltages ƒ On-chip voltage reference Fully Static CMOS Devices using advanced Flash technology Processor speeds to 24 MHz Register speed memory transfers ƒ Low power at high speed Flexible addressing modes ƒ Operating voltage from 3.0 to 5.25 V ƒ Operating voltage down to 1.0 V using on-chip switch mode voltage pump ƒ Wide temperature range: -40 oC to + 85 oC Bit manipulation on I/O and memory 8x8 multiply, 32-bit accumulate Flexible On-Chip Memory ƒ Flash program storage, 4K to 16K bytes, depending on device Complete Development Tools ƒ ƒ ƒ 50,000 erase/write cycles ƒ Powerful integrated development environment (PSoC™ Designer) ƒ Low-cost, in-circuit emulator and programmer 256 bytes SRAM data storage In-System Serial Programming (ISSP™) May 17, 2005 Document #: 38-12010 CY Rev. *C 3 CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet This page has intentionally been left blank. 4 Document #: 38-12010 CY Rev. *C May 17, 2005 Table of Contents 1.0 Functional Overview ......................................................................................................................14 1.1 Key Features ..............................................................................................................................14 1.2 Pin-out Descriptions ...................................................................................................................15 2.0 CPU Architecture ............................................................................................................................19 2.1 Introduction ................................................................................................................................19 2.2 CPU Registers ...........................................................................................................................20 2.3 Addressing Modes .....................................................................................................................21 2.4 Instruction Set Summary ...........................................................................................................25 3.0 Memory Organization .....................................................................................................................26 3.1 Flash Program Memory Organization ........................................................................................26 3.2 RAM Data Memory Organization ...............................................................................................26 4.0 Register Organization ....................................................................................................................26 4.1 Introduction ................................................................................................................................26 4.2 Register Bank 0 Map .................................................................................................................27 4.3 Register Bank 1 Map ................................................................................................................28 5.0 I/O Ports ...........................................................................................................................................29 5.1 Introduction ................................................................................................................................29 6.0 I/O Registers ...................................................................................................................................31 6.1 Port Data Registers ...................................................................................................................31 6.2 Port Interrupt Enable Registers .................................................................................................31 6.3 Port Global Select Registers .....................................................................................................32 7.0 Clocking ..........................................................................................................................................35 7.1 Oscillator Options .......................................................................................................................35 7.2 System Clocking Signals ............................................................................................................38 8.0 Interrupts .........................................................................................................................................42 8.1 Overview ....................................................................................................................................42 8.2 Interrupt Control Architecture .....................................................................................................44 8.3 Interrupt Vectors .........................................................................................................................44 8.4 Interrupt Masks ..........................................................................................................................45 8.5 Interrupt Vector Register ...........................................................................................................46 8.6 GPIO Interrupt ............................................................................................................................47 9.0 Digital PSoC Blocks .......................................................................................................................48 9.1 Introduction ................................................................................................................................48 9.2 Digital PSoC Block Bank 1 Registers .........................................................................................49 9.3 Digital PSoC Block Bank 0 Registers .........................................................................................54 9.4 Global Inputs and Outputs .........................................................................................................60 9.5 Available Programmed Digital Functionality ...............................................................................60 10.0 Analog PSoC Blocks ....................................................................................................................71 10.1 Introduction ..............................................................................................................................71 10.2 Analog System Clocking Signals .............................................................................................72 10.3 Array of Analog PSoC Blocks .................................................................................................72 10.4 Analog Reference Control ........................................................................................................73 10.5 Analog PSoC Block Clocking Options ......................................................................................76 10.6 Analog Clock Select Register ..................................................................................................77 10.7 Analog Continuous Time PSoC Blocks ....................................................................................80 May 17, 2005 Document #: 38-12010 CY Rev. *C 5 CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet 10.8 Analog Switch Cap Type A PSoC Blocks ................................................................................85 10.9 Analog Switch Cap Type B PSoC Blocks ................................................................................94 10.10 Analog Comparator Bus .......................................................................................................101 10.11 Analog Synchronization .......................................................................................................101 10.12 Analog I/O ............................................................................................................................103 10.13 Analog Modulator .................................................................................................................106 10.14 Analog PSoC Block Functionality .........................................................................................107 10.15 Temperature Sensing Capability ..........................................................................................108 11.0 Special Features of the CPU ......................................................................................................109 11.1 Multiplier/Accumulator ............................................................................................................109 11.2 Decimator ...............................................................................................................................112 11.3 Reset ......................................................................................................................................114 11.4 Sleep States ...........................................................................................................................116 11.5 Supply Voltage Monitor ..........................................................................................................118 11.6 Switch Mode Pump ................................................................................................................119 11.7 Internal Voltage Reference ....................................................................................................120 11.8 Supervisor ROM/System Supervisor Call Instruction .............................................................120 11.9 Flash Program Memory Protection ........................................................................................122 11.10 Programming Requirements and Step Descriptions ............................................................122 11.11 Programming Wave Forms .................................................................................................124 11.12 Programming File Format ....................................................................................................124 12.0 Development Tools ...................................................................................................................125 12.1 Overview ................................................................................................................................125 12.2 Integrated Development Environment Subsystems ...............................................................126 12.3 Hardware Tools ......................................................................................................................126 13.0 DC and AC Characteristics ........................................................................................................127 13.1 Absolute Maximum Ratings ..................................................................................................127 13.2 DC Characteristics .................................................................................................................129 13.3 AC Characteristics .................................................................................................................138 14.0 Packaging Information ..............................................................................................................143 14.1 Thermal Impedances per Package .......................................................................................148 15.0 Ordering Guide ..........................................................................................................................149 16.0 Document Revision History .......................................................................................................150 6 Document #: 38-12010 CY Rev. *C May 17, 2005 List of Tables Table 1: Device Family Key Features.........................................................................................................14 Table 2: Pin-out 8 Pin .................................................................................................................................15 Table 3: Pin-out 20 Pin ...............................................................................................................................15 Table 4: Pin-out 28 Pin ...............................................................................................................................16 Table 5: Pin-out 44 Pin ...............................................................................................................................16 Table 6: Pin-out 48 Pin ...............................................................................................................................17 Table 7: CPU Registers and Mnemonics ...................................................................................................19 Table 8: Flags Register ..............................................................................................................................20 Table 9: Accumulator Register (CPU_A)....................................................................................................20 Table 10: Index Register (CPU_X) .............................................................................................................21 Table 11: Stack Pointer Register (CPU_SP) ..............................................................................................21 Table 12: Program Counter Register (CPU_PC)........................................................................................21 Table 13: Source Immediate ......................................................................................................................21 Table 14: Source Direct..............................................................................................................................22 Table 15: Source Indexed ..........................................................................................................................22 Table 16: Destination Direct .......................................................................................................................22 Table 17: Destination Indexed....................................................................................................................23 Table 18: Destination Direct Immediate .....................................................................................................23 Table 19: Destination Indexed Immediate ..................................................................................................23 Table 20: Destination Direct Direct.............................................................................................................24 Table 21: Source Indirect Post Increment ..................................................................................................24 Table 22: Destination Indirect Post Increment............................................................................................24 Table 23: Instruction Set Summary (Sorted by Mnemonic)........................................................................25 Table 24: Flash Program Memory Map ......................................................................................................26 Table 25: RAM Data Memory Map .............................................................................................................26 Table 26: Bank 0 ........................................................................................................................................27 Table 27: Bank 1 ........................................................................................................................................28 Table 28: Port Data Registers ....................................................................................................................31 Table 29: Port Interrupt Enable Registers ..................................................................................................31 Table 30: Port Global Select Registers ......................................................................................................32 Table 31: Port Drive Mode 0 Registers ......................................................................................................32 Table 32: Port Drive Mode 1 Registers ......................................................................................................33 Table 33: Port Interrupt Control 0 Registers...............................................................................................33 Table 34: Port Interrupt Control 1 Registers...............................................................................................34 Table 35: Internal Main Oscillator Trim Register ........................................................................................35 Table 36: Internal Low Speed Oscillator Trim Register ..............................................................................36 Table 37: External Crystal Oscillator Trim Register....................................................................................37 Table 38: Typical Package Capacitances ..................................................................................................37 Table 39: System Clocking Signals and Definitions ...................................................................................38 Table 40: Oscillator Control 0 Register.......................................................................................................40 Table 41: Oscillator Control 1 Register.......................................................................................................40 Table 42: 24V1/24V2 Frequency Selection ................................................................................................41 Table 43: Interrupt Vector Table.................................................................................................................44 Table 44: General Interrupt Mask Register ................................................................................................45 Table 45: Digital PSoC Block Interrupt Mask Register ...............................................................................46 May 17, 2005 Document #: 38-12010 CY Rev. *C 7 CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet Table 46: Interrupt Vector Register ............................................................................................................46 Table 47: Digital Basic Type A/ Communications Type A Block xx Function Register...............................50 Table 48: Digital Basic Type A / Communications Type A Block xx Input Register ...................................51 Table 49: Digital Function Data Input Definitions .......................................................................................52 Table 50: Digital Basic Type A / Communications Type A Block xx Output Register.................................53 Table 51: Digital Function Outputs .............................................................................................................54 Table 52: Digital Basic Type A / Communications Type A Block xx Data Register 0,1,2...........................54 Table 53: R/W Variations per User Module Selection ................................................................................55 Table 54: Digital Basic Type A / Communications Type A Block xx Control Register 0 .............................55 Table 55: Digital Basic Type A/Communications Type A Block xx Control Register 0...............................56 Table 56: Digital Communications Type A Block xx Control Register 0... ..................................................57 Table 57: Digital Communications Type A Block xx Control Register 0... ..................................................58 Table 58: Digital Communications Type A Block xx Control Register 0... ..................................................59 Table 59: Global Input Assignments...........................................................................................................60 Table 60: Global Output Assignments........................................................................................................60 Table 61: Analog System Clocking Signals................................................................................................72 Table 62: AGND, RefHI, RefLO Operating Parameters .............................................................................74 Table 63: Analog Reference Control Register............................................................................................75 Table 64: Analog Column Clock Select Register........................................................................................76 Table 65: Analog Clock Select Register .....................................................................................................77 Table 66: Analog Continuous Time Block xx Control 0 Register................................................................82 Table 67: Analog Continuous Time Block xx Control 1 Register................................................................83 Table 68: Analog Continuous Time Type A Block xx Control 2 Register ...................................................84 Table 69: Analog Switch Cap Type A Block xx Control 0 Register ............................................................88 Table 70: Analog Switch Cap Type A Block xx Control 1 Register ............................................................90 Table 71: Analog Switch Cap Type A Block xx Control 2 Register ............................................................92 Table 72: Analog Switch Cap Type A Block xx Control 3 Register ............................................................93 Table 73: Analog Switch Cap Type B Block xx Control 0 Register ............................................................95 Table 74: Analog Switch Cap Type B Block xx Control 1 Register ............................................................97 Table 75: Analog Switch Cap Type B Block xx Control 2 Register ............................................................99 Table 76: Analog Switch Cap Type B Block xx Control 3 Register ..........................................................100 Table 77: Analog Comparator Control Register .......................................................................................101 Table 78: Analog Frequency Relationships..............................................................................................102 Table 79: Analog Synchronization Control Register.................................................................................102 Table 80: Analog Input Select Register ....................................................................................................104 Table 81: Analog Output Buffer Control Register .....................................................................................106 Table 82: Analog Modulator Control Register ..........................................................................................107 Table 83: Multiply Input X Register...........................................................................................................110 Table 84: Multiply Input Y Register...........................................................................................................110 Table 85: Multiply Result High Register ...................................................................................................111 Table 86: Multiply Result Low Register ....................................................................................................111 Table 87: Accumulator Result 1 / Multiply/Accumulator Input X Register ................................................111 Table 88: Accumulator Result 0 / Multiply/Accumulator Input Y Register ................................................111 Table 89: Accumulator Result 3 / Multiply/Accumulator Clear 0 Register ................................................112 Table 90: Accumulator Result 2 / Multiply/Accumulator Clear 1 Register ................................................112 Table 91: Decimator/Incremental Control Register ..................................................................................113 Table 92: Decimator Data High Register..................................................................................................113 Table 93: Decimator Data Low Register...................................................................................................113 Table 94: Processor Status and Control Register ....................................................................................114 Table 95: Reset WDT Register.................................................................................................................116 Table 96: Voltage Monitor Control Register .............................................................................................118 Table 97: Bandgap Trim Register.............................................................................................................120 Table 98: CY8C25122, CY8C26233, CY8C26443, CY8C26643 (256 Bytes of SRAM) ..........................121 Table 99: Table Read for Supervisory Call Functions ..............................................................................122 8 Document #: 38-12010 CY Rev. *C May 17, 2005 Table 100: Flash Program Memory Protection.........................................................................................122 Table 101: Programmer Requirements ....................................................................................................122 Table 102: Absolute Maximum Ratings....................................................................................................127 Table 103: Temperature Specifications....................................................................................................128 Table 104: DC Operating Specifications ..................................................................................................129 Table 105: 5V DC Operational Amplifier Specifications ...........................................................................130 Table 106: 3.3V DC Operational Amplifier Specifications ........................................................................ 131 Table 107: DC Analog Input Pin with Multiplexer Specifications ..............................................................132 Table 108: DC Analog Input Pin to SC Block Specifications ....................................................................132 Table 109: 5V DC Analog Output Buffer Specifications ........................................................................... 132 Table 110: 3.3V DC Analog Output Buffer Specifications ........................................................................133 Table 111: DC Switch Mode Pump Specifications ...................................................................................134 Table 112: 5V DC Analog Reference Specifications ................................................................................135 Table 113: 3.3V DC Analog Reference Specifications ............................................................................. 136 Table 114: DC Analog PSoC Block Specifications...................................................................................136 Table 115: DC Programming Specifications.............................................................................................137 Table 116: AC Operating Specifications...................................................................................................138 Table 117: 5V AC Operational Amplifier Specifications ...........................................................................139 Table 118: 3.3V AC Operational Amplifier Specifications ........................................................................ 140 Table 119: 5V AC Analog Output Buffer Specifications ...........................................................................141 Table 120: 3.3V AC Analog Output Buffer Specifications ........................................................................142 Table 121: AC Programming Specifications.............................................................................................142 Table 122: Thermal Impedances..............................................................................................................148 Table 123: Ordering Guide (Leaded)........................................................................................................149 Table 124: Ordering Guide (Pb-Free Denoted with an “X” in Ordering Code) .........................................149 Table 125: Document Revision History ....................................................................................................150 May 17, 2005 Document #: 38-12010 CY Rev. *C 9 CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet 10 Document #: 38-12010 CY Rev. *C May 17, 2005 List of Figures Figure 1: Block Diagram ............................................................................................................................13 Figure 2: CY8C25122 ................................................................................................................................15 Figure 3: CY8C26233 ................................................................................................................................15 Figure 4: 26443 PDIP/SOIC/SSOP ...........................................................................................................16 Figure 5: 26643 TQFP ...............................................................................................................................17 Figure 6: 26643 PDIP/SSOP .....................................................................................................................18 Figure 7: General Purpose I/O Pins ..........................................................................................................30 Figure 8: External Crystal Oscillator Connections .....................................................................................37 Figure 9: PSoC MCU Clock Tree of Signals ..............................................................................................39 Figure 10: Interrupts Overview ..................................................................................................................43 Figure 11: GPIO Interrupt Enable Diagram ...............................................................................................47 Figure 12: Digital Basic and Digital Communications PSoC Blocks ..........................................................49 Figure 13: Polynomial LFSR ......................................................................................................................65 Figure 14: Polynomial PRS .......................................................................................................................65 Figure 15: SPI Waveforms ........................................................................................................................68 Figure 16: Array of Analog PSoC Blocks ...................................................................................................72 Figure 17: Analog Reference Control Schematic ......................................................................................73 Figure 18: NMux Connections ...................................................................................................................78 Figure 19: PMux Connections ...................................................................................................................79 Figure 20: RBotMux Connections ..............................................................................................................79 Figure 21: Analog Continuous Time PSoC Blocks ....................................................................................81 Figure 22: Analog Switch Cap Type A PSoC Blocks .................................................................................86 Figure 23: AMux Connections ...................................................................................................................87 Figure 24: CMux Connections ...................................................................................................................87 Figure 25: BMuxSCA/SCB Connections ...................................................................................................88 Figure 26: Analog Switch Cap Type B PSoC Blocks .................................................................................95 Figure 27: Analog Input Muxing ...............................................................................................................103 Figure 28: Analog Output Buffers ............................................................................................................105 Figure 29: Multiply/Accumulate Block Diagram .......................................................................................110 Figure 30: Decimator Coefficients ...........................................................................................................112 Figure 31: Execution Reset .....................................................................................................................115 Figure 32: Three Sleep States .................................................................................................................117 Figure 33: Switch Mode Pump ................................................................................................................119 Figure 34: Programming Wave Forms ....................................................................................................124 Figure 35: PSoC Designer Functional Flow ............................................................................................125 Figure 36: CY8C25xxx/CY8C26xxx Voltage Frequency Graph ..............................................................127 Figure 37: 44-Lead Thin Plastic Quad Flat Pack A44 .............................................................................143 Figure 38: 20-Pin Shrunk Small Outline Package O20 ...........................................................................144 Figure 39: 28-Lead (210-Mil) Shrunk Small Outline Package O28 .........................................................145 Figure 40: 48-Lead Shrunk Small Outline Package O48 .........................................................................145 Figure 41: 20-Lead (300-Mil) Molded DIP P5 ..........................................................................................146 Figure 42: 28-Lead (300-Mil) Molded DIP P21 ........................................................................................146 Figure 43: 48-Lead (600-Mil) Molded DIP P25 ........................................................................................147 Figure 44: 20-Lead (300-Mil) Molded SOIC S5 .......................................................................................147 Figure 45: 28-Lead (300-Mil) Molded SOIC S21 .....................................................................................148 May 17, 2005 Document #: 38-12010 CY Rev. *C 11 CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet Figure 46: 8-Lead (300-Mil) Molded DIP .................................................................................................148 12 Document #: 38-12010 CY Rev. *C May 17, 2005 P5 P4 P3 P2 P1 P0 I/O Ports Analog Input Muxing Analog Output Drivers A C A 0 0 A C A 0 1 A C A 0 2 A C A 0 3 A S A 1 0 A S B 1 1 A S A 1 2 A S B 1 3 A S B 2 0 A S A 2 1 A S B 2 2 A S A 2 3 Global I/O Programmable Interconnect Clocks to Analog Comparator Outputs D B A 0 0 Array of Analog PSoC Blocks D B A 0 1 D B A 0 2 D B A 0 3 D C A 0 4 D C A 0 5 D C A 0 6 D C A 0 7 Array of Digital PSoC Blocks Flash Program Memory Oscillator and PLL MAC Multiply Accumulate SRAM Memory M8C CPU Core Internal System Bus Decimator Watchdog/ Sleep Timer LVD/POR Interrupt Controller Figure 1: Block Diagram May 17, 2005 Document #: 38-12010 CY Rev. *C 13 CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet 1.0 Functional Overview The CPU heart of this next generation family of microcontrollers is a high performance, 8-bit, M8C Harvard architecture microprocessor. Separate program and memory busses allow for faster overall throughput. Processor clock speeds to 24 MHz are available. The processor may also be run at lower clock speeds for powersensitive applications. A rich instruction set allows for efficient low-level language support. All devices in this family include both analog and digital configurable peripherals (PSoC blocks). These blocks enable the user to define unique functions during configuration of the device. Included are twelve analog PSoC blocks and eight digital PSoC blocks. Potential applications for the digital PSoC blocks are timers, counters, UARTs, CRC generators, PWMs, and other functions. The analog PSoC blocks can be used for SAR ADCs, Multi-slope ADCs, programmable gain amplifiers, programmable filters, DACs, and other functions. Higher order User Modules such as modems, complex motor controllers, and complete sensor signal chains can be created from these building blocks. This allows for an unprecedented level of flexibility and integration in microcontroller-based systems. A Multiplier/Accumulator (MAC) is available on all devices in this family. The MAC is implemented on this device as a peripheral that is mapped into the register space. When an instruction writes to the MAC input registers, the result of an 8x8 multiply and a 32-bit accumulate are available to be read from the output registers on the next instruction cycle. The number of general purpose I/Os available in this family of parts range from 6 to 44. Each of these I/O pins has a variety of programmable options. In the output 1.1 Table 1: Multiple oscillator options are available for use in clocking the CPU, analog PSoC blocks and digital PSoC blocks. These options include an internal main oscillator running at 48/24 MHz, an external crystal oscillator for use with a 32.768 kHz watch crystal, and an internal lowspeed oscillator for use in clocking the PSoC blocks and the Watchdog/Sleep timer. User selectable clock divisors allow for optimizing code execution speed and power trade-offs. The different device types in this family provide various amounts of code and data memory. The code space ranges in size from 4K to 16K bytes of user programmable Flash memory. This memory can be programmed serially in either a programming Pod or on the user board. The endurance on the Flash memory is 50,000 erase/write cycles. The data space is 256 bytes of user SRAM. A powerful and flexible protection model secures the user’s sensitive information. This model allows the user to selectively lock blocks of memory for read and write protection. This allows partial code updates without exposing proprietary information. Devices in this family range from 8 pins through 48 pins in PDIP, SOIC and SSOP packages. Key Features Device Family Key Features Operating Frequency Operating Voltage Program Memory (KBytes) Data Memory (Bytes) Digital PSoC Blocks Analog PSoC Blocks I/O Pins External Switch Mode Pump Available Packages 14 mode, the user can select the drive strength desired. Any pin can serve as an interrupt source, and can be selected to trigger on positive edges, negative edges, or any change. Digital signal sources can be routed directly from a pin to the digital PSoC blocks. Some pins have additional capability to route analog signals to the analog PSoC blocks. CY8C25122 93.7kHz - 24MHz 3.0 - 5.25V 4 256 8 12 6 No 8 PDIP CY8C26233 93.7kHz - 24MHz 3.0 - 5.25V 8 256 8 12 16 Yes 20 PDIP 20 SOIC 20 SSOP Document #: 38-12010 CY Rev. *C CY8C26443 93.7kHz - 24MHz 3.0 - 5.25V 16 256 8 12 24 Yes 28 PDIP 28 SOIC 28 SSOP CY8C26643 93.7kHz - 24MHz 3.0 - 5.25V 16 256 8 12 40/44 Yes 48 PDIP 48 SSOP 44 TQFP May 17, 2005 Functional Overview 1.2 Pin-out Descriptions Table 2: Name Pin-out 8 Pin I/O Pin Pin-out 20 Pin Table 3: Description Name I/O Pin Description I/O 1 Port 0[7] (Analog Input) P0[7] I/O 1 Port 0[7] (Analog Input) P0[5] I/O 2 Port 0[5] (Analog Input/Output) P0[5] I/O 2 Port 0[5] (Analog Input/Output) P1[1] I/O 3 Port 1[1] / XtalIn / SCLK P0[3] I/O 3 Port 0[3] (Analog Input/Output) Vss Power 4 Ground P0[1] I/O 4 Port 0[1] (Analog Input) P1[0] I/O 5 Port 1[0] / XtalOut / SDATA SMP O 5 Switch Mode Pump P0[2] I/O 6 Port 0[2] (Analog Input/Output) P1[7] I/O 6 Port 1[7] P0[4] I/O 7 Port 0[4] (Analog Input/Output) P1[5] I/O 7 Port 1[5] Vcc Power 8 Supply Voltage P1[3] I/O 8 Port 1[3] P1[1] I/O 9 Port 1[1] / XtalIn / SCLK Vss Power 10 Ground P1[0] I/O 11 Port 1[0] / XtalOut / SDATA P1[2] I/O 12 Port 1[2] P1[4] I/O 13 Port 1[4] P1[6] I/O 14 Port 1[6] P0[7] P0[5] XtalIn/SCLK/P1[1] Vss 1 2 3 4 CY8C25122 P0[7] 8 7 6 5 Vcc P0[4] P0[2] P1[0]/XtalOut/SDATA Figure 2: CY8C25122 XRES I 15 External Reset P0[0] I/O 16 Port 0[0] (Analog Input) P0[2] I/O 17 Port 0[2] (Analog Input/Output) P0[4] I/O 18 Port 0[4] (Analog Input/Output) P0[6] I/O 19 Port 0[6] (Analog Input) Vcc Power 20 Supply Voltage XtalIn/SCLK/P1[1] Vss CY8C26233 PDIP/SOIC/SSOP 1 2 3 4 5 6 7 8 9 10 P0[7] P0[5] P0[3] P0[1] SMP P1[7] P1[5] P1[3] 20 19 18 17 16 15 14 13 12 11 Vcc P0[6] P0[4] P0[2] P0[0] XRES P1[6] P1[4] P1[2] P1[0]/XtalOut/SDATA Figure 3: CY8C26233 May 17, 2005 Document #: 38-12010 CY Rev. *C 15 CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet Table 4: Pin-out 28 Pin Name P0[7] I/O Pin Description 1 Port 0[7] (Analog Input) P0[5] I/O Port 0[5] (Analog Input/ Out2 put) P0[3] I/O 3 P0[1] I/O 4 Port 0[1] (Analog Input) P2[7] I/O 5 Port 2[7] P2[5] I/O 6 Port 2[5] P2[3] I/O 7 Port 2[3] (Non-Multiplexed Analog Input) P2[1] I/O 8 Port 2[1] (Non-Multiplexed Analog Input) SMP O P1[7] I/O 10 Port 1[7] P1[5] I/O 11 Port 1[5] P1[3] I/O 12 Port 1[3] P1[1] I/O 13 Port 1[1] / XtalIn / SCLK Vss Power 14 Ground P1[0] I/O 15 Port 1[0] / XtalOut / SDATA P1[2] I/O 16 Port 1[2] P1[4] I/O P1[6] P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] SMP P1[7] P1[5] P1[3] Port 0[3] (Analog Input/ Output) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 XtalIn/SCLK/P1[1] Vss 26443 PDIP/SOIC/SSOP I/O 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vcc P0[6] P0[4] P0[2] P0[0] P2[6]/External V ref P2[4]/External AGND P2[2] P2[0] Xres P1[6] P1[4] P1[2] P1[0]/XtalOut/SDATA Figure 4: 26443 PDIP/SOIC/SSOP 9 Switch Mode Pump Pin-out 44 Pin Table 5: Name I/O Pin Description P2[5] I/O 1 Port 2[5] P2[3] I/O 2 Port 2[3] (Non-Multiplexed Analog Input) P2[1] I/O 3 Port 2[1] (Non-Multiplexed Analog Input) 17 Port 1[4] P3[7] I/O 4 Port 3[7] I/O 18 Port 1[6] P3[5] I/O 5 Port 3[5] XRES I 19 External Reset P3[3] I/O 6 Port 3[3] P2[0] I/O 20 Port 2[0] (Non-Multiplexed Analog Input) P3[1] I/O 7 Port 3[1] SMP O 8 Switch Mode Pump P4[7] I/O 9 Port 4[7] P4[5] I/O 10 Port 4[5] P4[3] I/O 11 Port 4[3] P4[1] I/O 12 Port 4[1] P1[7] I/O 13 Port 1[7] P1[5] I/O 14 Port 1[5] P1[3] I/O 15 Port 1[3] P1[1] I/O 16 Port 1[1] / XtalIn / SCLK P2[2] I/O Port 2[2] (Non-Multiplexed 21 Analog Input) P2[4] I/O 22 Port 2[4] / External AGNDIn P2[6] I/O 23 Port 2[6] / External VREFIn P0[0] I/O 24 Port 0[0] (Analog Input) P0[2] I/O 25 Port 0[2] (Analog Input/Output) P0[4] I/O 26 Port 0[4] (Analog Input/Output) P0[6] I/O 27 Port 0[6] (Analog Input) Vss Power 17 Ground Vcc Power 28 Supply Voltage P1[0] I/O 18 Port 1[0] / XtalOut / SDATA P1[2] I/O 19 Port 1[2] P1[4] I/O 20 Port 1[4] P1[6] I/O 21 Port 1[6] P4[0] I/O 22 Port 4[0] P4[2] I/O 23 Port 4[2] P4[4] I/O 24 Port 4[4] 16 Document #: 38-12010 CY Rev. *C May 17, 2005 Functional Overview Pin-out 44 Pin, continued Table 5: Pin-out 48 Pin Table 6: P4[6] I/O 25 Port 4[6] XRES I 26 External Reset P3[0] I/O 27 Port 3[0] P3[2] I/O 28 Port 3[2] P3[4] I/O 29 Port 3[4] P3[6] I/O 30 Port 3[6] P2[0] I/O 31 Name I/O Pin Description P0[7] I/O 1 Port 0[7] (Analog Input) P0[5] I/O 2 Port 0[5] (Analog Input/Output) P0[3] I/O 3 Port 0[3] (Analog Input/Output) Port 2[0] (Non-Multiplexed Analog Input) P0[1] I/O 4 Port 0[1] (Analog Input) P2[7] I/O 5 Port 2[7] P2[5] I/O 6 Port 2[5] P2[3] I/O 7 Port 2[3] (Non-Multiplexed Analog Input) P2[1] I/O 8 Port 2[1] (Non-Multiplexed Analog Input) P2[4] I/O 33 Port 2[4] / External AGNDIn P2[6] I/O 34 Port 2[6] / External VREFIn P0[0] I/O 35 Port 0[0] (Analog Input) P0[2] I/O 36 Port 0[2] (Analog Input/Output) P3[7] I/O 9 Port 3[7] P0[4] I/O 37 Port 0[4] (Analog Input/Output) P3[5] I/O 10 Port 3[5] P0[6] I/O 38 Port 0[6] (Analog Input) P3[3] I/O 11 Port 3[3] Vcc Power 39 Supply Voltage P3[1] I/O 12 Port 3[1] P0[7] I/O 40 Port 0[7] (Analog Input) SMP O 13 Switch Mode Pump P0[5] I/O 41 Port 0[5] (Analog Input/Output) P4[7] I/O 14 Port 4[7] P0[3] I/O 42 Port 0[3] (Analog Input/Output) P4[5] I/O 15 Port 4[5] P0[1] I/O 43 Port 0[1] (Analog Input) P4[3] I/O 16 Port 4[3] P2[7] I/O 44 Port 2[7] P4[1] I/O 17 Port 4[1] P5[3] I/O 18 Port 5[3] P5[1] I/O 19 Port 5[1] P1[7] I/O 20 Port 1[7] P1[5] I/O 21 Port 1[5] P1[3] I/O 22 Port 1[3] P1[1] I/O 23 Port 1[1] / XtalIn / SCLK Vss Power 24 Ground P1[0] I/O 25 Port 1[0] / XtalOut / SDATA P1[2] I/O 26 Port 1[2] P1[4] I/O 27 Port 1[4] P1[6] I/O 28 Port 1[6] 1 44 43 42 41 40 39 38 37 36 35 34 2 3 4 5 6 7 8 9 10 11 26643 TQFP P2[5] P2[3] P2[1] P3[7] P3[5] P3[3] P3[1] SMP P4[7] P4[5] P4[3] P2[6]/ExVrefIn I/O P2[7] P0[1] P0[3] P0[5] P0[7] Vcc P0[6] P0[4] P0[2] P0[0] P2[2] Port 2[2] (Non-Multiplexed 32 Analog Input) 33 32 31 30 29 28 27 26 25 24 23 P2[4]/Ex AGNDIn P2[2] P2[0] P3[6] P3[4] P3[2] P3[0] Xres P4[6] P4[4] P4[2] P4[1] P1[7] P1[5] P1[3] XtalIn/SCLK/P1[1] Vss XtalOut/SDATA/P1[0] P1[2] P1[4] P1[6] P4[0] 12 13 14 15 16 17 18 19 20 21 22 Figure 5: 26643 TQFP May 17, 2005 Document #: 38-12010 CY Rev. *C 17 CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet Pin-out 48 Pin, continued Table 6: P5[0] I/O 29 Port 5[0] P5[2] I/O 30 Port 5[2] P4[0] I/O 31 Port 4[0] P4[2] I/O 32 Port 4[2] P4[4] I/O 33 Port 4[4] P4[6] I/O 34 Port 4[6] XRES I 35 External Reset P3[0] I/O 36 Port 3[0] P3[2] I/O 37 Port 3[2] P3[4] I/O 38 Port 3[4] P3[6] I/O 39 Port 3[6] P2[0] I/O 40 Port 2[0] (Non-Multiplexed Analog Input) P2[2] I/O 41 Port 2[2] (Non-Multiplexed Analog Input) P2[4] I/O 42 Port 2[4] / External AGNDIn P2[6] I/O 43 Port 2[6] / External VREFIn P0[0] I/O 44 Port 0[0] (Analog Input) P0[2] I/O 45 Port 0[2] (Analog Input/Output) P0[4] I/O 46 Port 0[4] (Analog Input/Output) P0[6] I/O 47 Port 0[6] (Analog Input) Vcc Power 48 Supply Voltage XtalIn/SCLK/P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 26643 PDIP/SSOP P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P3[7] P3[5] P3[3] P3[1] SMP P4[7] P4[5] P4[3] P4[1] P5[3] P5[1] P1[7] P1[5] P1[3] 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Vcc P0[6] P0[4] P0[2] P0[0] P2[6]/External V ref IN P2[4] /External AGNDIN P2[2] P2[0] P3[6] P3[4] P3[2] P3[0] Xres P4[6] P4[4] P4[2] P4[0] P5[2] P5[0] P1[6] P1[4] P1[2] P1[0]/XtalOut/SDATA Figure 6: 26643 PDIP/SSOP 18 Document #: 38-12010 CY Rev. *C May 17, 2005 CPU Architecture 2.0 CPU Architecture 2.1 Introduction This family of microcontrollers is based on a high perfor- RET instructions, which manage the software stack. It mance, 8-bit, Harvard architecture microprocessor. Five can also be affected by the SWAP and ADD instructions. registers control the primary operation of the CPU core. These registers are affected by various instructions, but are not directly accessible through the register space by the user. For more details on addressing with the register The Flag Register (CPU_F) has three status bits: Zero Flag bit [1]; Carry Flag bit [2]; Supervisory State bit [3]. The Global Interrupt Enable bit [0] is used to globally enable or disable interrupts. An extended I/O space space, see section 4.0. address, bit [4], is used to determine which bank of the Table 7: CPU Registers and Mnemonics Register Mnemonic register space is in use. The user cannot manipulate the Supervisory State status bit [3]. The flags are affected by Flags CPU_F arithmetic, logic, and shift operations. The manner in Program Counter CPU_PC which each flag is changed is dependent upon the Accumulator CPU_A instruction being executed (i.e., AND, OR, XOR... See Stack Pointer CPU_SP Table 23 on page 25). Index CPU_X The 16 bit Program Counter Register (CPU_PC) allows for direct addressing of the full 16 Kbytes of program memory space available in the largest members of this family. This forms one contiguous program space, and no paging is required. The Accumulator Register (CPU_A) is the general-purpose register that holds the results of instructions that specify any of the source addressing modes. The Index Register (CPU_X) holds an offset value that is used in the indexed addressing modes. Typically, this is used to address a block of data within the data memory space. The Stack Pointer Register (CPU_SP) holds the address of the current top-of-stack in the data memory space. It is affected by the PUSH, POP, LCALL, CALL, RETI, and May 17, 2005 Document #: 38-12010 CY Rev. *C 19 CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet 2.2 CPU Registers 2.2.1 Flags Register The Flags Register can only be set or reset with logical instruction. Table 8: Flags Register Bit # 7 6 5 4 3 2 1 0 POR 0 0 0 0 0 0 1 0 Read/ Write -- -- -- RW R RW RW RW Bit Name Reserved Reserved Reserved XIO Super Carry Zero Global IE Bit 7: Reserved Bit 6: Reserved Bit 5: Reserved Bit 4: XIO Set by the user to select between the register banks 0 = Bank 0 1 = Bank 1 Bit 3: Super Indicates whether the CPU is executing user code or Supervisor Code. (This code cannot be accessed directly by the user and is not displayed in the ICE debugger.) 0 = User Code 1 = Supervisor Code Bit 2: Carry Set by CPU to indicate whether there has been a carry in the previous logical/arithmetic operation 0 = No Carry 1 = Carry Bit 1: Zero Set by CPU to indicate whether there has been a zero result in the previous logical/arithmetic operation 0 = Not Equal to Zero 1 = Equal to Zero Bit 0: Global IE Determines whether all interrupts are enabled or disabled 0 = Disabled 1 = Enabled 2.2.2 Accumulator Register Table 9: Accumulator Register (CPU_A) Bit # POR Read/Write Bit Name 7 0 System1 Data [7] 6 0 System1 Data [6] 5 0 System1 Data [5] 4 0 System1 Data [4] 3 0 System1 Data [3] 2 0 System1 Data [2] 1 0 0 0 System1 Data [1] System1 Data [0] Bit [7:0]: Data [7:0] 8-bit data value holds the result of any logical/arithmetic instruction that uses a source addressing mode 1. 20 System - not directly accessible by the user Document #: 38-12010 CY Rev. *C May 17, 2005 CPU Architecture 2.2.3 Index Register Table 10: Index Register (CPU_X) Bit # POR Read/ Write Bit Name 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 System1 System1 System1 System1 System1 System1 System1 System1 Data [7] Data [6] Data [5] Data [4] Data [3] Data [2] Data [1] Data [0] Bit [7:0]: Data [7:0] 8-bit data value holds an index for any instruction that uses an indexed addressing mode 1. System - not directly accessible by the user 2.2.4 Stack Pointer Register Table 11: Stack Pointer Register (CPU_SP) Bit # POR Read/ Write Bit Name 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 System1 System1 System1 System1 System1 System1 System1 System1 Data [7] Data [6] Data [5] Data [4] Data [3] Data [2] Data [1] Data [0] Bit [7:0]: Data [7:0] 8-bit data value holds a pointer to the current top-of-stack 1. System - not directly accessible by the user 2.2.5 Program Counter Register Table 12: Bit # POR Read/ Write Bit Name Program Counter Register (CPU_PC) 15 0 14 0 13 0 12 0 11 0 10 0 9 0 8 0 7 0 6 0 5 0 4 0 3 0 2 0 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Data Data Data Data Data Data Data Data Data Data Data Data Data Data Data [15] [14] [13] [12] [11] [10] [9] [8] [7] [6] [5] [4] [3] [2] [1] Data [0] Bit [15:0]: Data [15:0] 16-bit data value is the low-order/high-order byte of the Program Counter 1. System - not directly accessible by the user 2.3 Addressing Modes 2.3.1 Source Immediate require two sources. Instructions using this addressing The result of an instruction using this addressing mode is placed in the A register, the F register, the SP register, or the X register, which is specified as part of the instruction opcode. Operand 1 is an immediate value that serves as mode are two bytes in length. Table 13: Opcode Instruction Source Immediate Operand 1 Immediate Value a source for the instruction. Arithmetic instructions May 17, 2005 Document #: 38-12010 CY Rev. *C 21 CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet Examples: added to the X register forming an address that points to a location in either the RAM memory space or the regis- ADD MOV AND 2.3.2 A, X, F, 7 ;In this case, the immediate ;value of 7 is added with the ;Accumulator, and the result ;is placed in the ;Accumulator. 8 ;In this case, the immediate ;value of 8 is moved to the X ;register. 9 ;In this case, the immediate ;value of 9 is logically ;ANDed with the F register ;and the result is placed in ;the F register. ter space that is the source for the instruction. Arithmetic instructions require two sources, the second source is the A register or X register specified in the opcode. Instructions using this addressing mode are two bytes. Table 15: Source Indexed Opcode Instruction Operand 1 Source Index Examples: [X+7] ;In this case, the ;value in the memory ;location at address ;X + 7 is added with ;the Accumulator, and ;the result is placed ;in the Accumulator. REG[X+8] ;In this case, the ;value in the ;register space at ;address X + 8 is ;moved to the X ;register. Source Direct The result of an instruction using this addressing mode is ADD A, placed in either the A register or the X register, which is specified as part of the instruction opcode. Operand 1 is an address that points to a location in either the RAM memory space or the register space that is the source for the instruction. Arithmetic instructions require two MOV X, sources, the second source is the A register or X register specified in the opcode. Instructions using this addressing mode are two bytes in length. Table 14: Destination Direct Operand 1 The result of an instruction using this addressing mode is Source Address placed within either the RAM memory space or the regis- Opcode Instruction 2.3.4 Source Direct ter space. Operand 1 is an address that points to the location of the result. The source for the instruction is Examples: either the A register or the X register, which is specified ADD MOV 2.3.3 A, X, [7] ;In this case, the ;value in the RAM ;memory location at ;address 7 is added ;with the Accumulator, ;and the result is ;placed in the ;Accumulator. ;In this case, the ;value in the register REG[8] ;space at address 8 is ;moved to the X ;register. as part of the instruction opcode. Arithmetic instructions require two sources, the second source is the location specified by Operand 1. Instructions using this addressing mode are two bytes in length. Table 16: Opcode Instruction Destination Direct Operand 1 Destination Address Source Indexed The result of an instruction using this addressing mode is placed in either the A register or the X register, which is specified as part of the instruction opcode. Operand 1 is 22 Document #: 38-12010 CY Rev. *C May 17, 2005 CPU Architecture source for the instruction is Operand 2, which is an Examples: immediate value. Arithmetic instructions require two ADD MOV 2.3.5 [7], A REG[8], A ;In this case, the ;value in the memory ;location at address ;7 is added with the ;Accumulator, and the ;result is placed in ;the memory location ;at address 7. The ;Accumulator is ;unchanged. sources, the second source is the location specified by ;In this case, the ;Accumulator is moved ;to the register ;space location at ;address 8. The ;Accumulator is ;unchanged. Examples: Operand 1. Instructions using this addressing mode are three bytes in length. Table 18: Destination Direct Immediate Opcode Instruction ADD [7], Operand 1 Destination Address Immediate Value ;In this case, value in ;the memory location at ;address 7 is added to ;the immediate value of ;5, and the result is ;placed in the memory ;location at address 7. 5 Destination Indexed ;In this case, the ;immediate value of 6 is ;moved into the register ;space location at ;address 8. The result of an instruction using this addressing mode is placed within either the RAM memory space or the regis- Operand 2 MOV REG[8], 6 ter space. Operand 1 is added to the X register forming the address that points to the location of the result. The source for the instruction is the A register. Arithmetic 2.3.7 Destination Indexed Immediate instructions require two sources, the second source is the location specified by Operand 1 added with the X The result of an instruction using this addressing mode is register. Instructions using this addressing mode are two placed within either the RAM memory space or the regis- bytes in length. ter space. Operand 1 is added to the X register to form Table 17: the address of the result. The source for the instruction is Destination Indexed Opcode Instruction Operand 2, which is an immediate value. Arithmetic Operand 1 instructions require two sources, the second source is Destination Index the location specified by Operand 1 added with the X register. Instructions using this addressing mode are three bytes in length. Example: ADD [X+7], 2.3.6 A ;In this case, the value ;in the memory location ;at address X+7 is added ;with the Accumulator, ;and the result is placed ;in the memory location ;at address x+7. The ;Accumulator is ;unchanged. Table 19: Opcode Instruction Destination Indexed Immediate Operand 1 Destination Index Operand 2 Immediate Value Destination Direct Immediate The result of an instruction using this addressing mode is placed within either the RAM memory space or the register space. Operand 1 is the address of the result. The May 17, 2005 Document #: 38-12010 CY Rev. *C 23 CY8C25122/CY8C26233/CY8C26443/CY8C26643 Device Family Data Sheet Examples: Language User Guide for further details on MVI instruc- tion. ADD MOV 2.3.8 [X+7], 5 REG[X+8], 6 ;In this case, the ;value in the memory ;location at address ;X+7 is added with ;the immediate value ;of 5, and the result ;is placed in the ;memory location at ;address X+7. ;In this case, the ;immediate value of 6 ;is moved into the ;location in the ;register space at ;address X+8. Table 21: Source Indirect Post Increment Opcode Instruction Operand 1 Source Address Address Example: MVI A, [8] Destination Direct Direct ;In this case, the value ;in the memory location at ;address 8 is an indirect ;address. The memory ;location pointed to by ;the indirect address is ;moved into the ;Accumulator. The ;indirect address is then ;incremented. The result of an instruction using this addressing mode is placed within the RAM memory. Operand 1 is the address of the result. Operand 2 is an address that points to a location in the RAM memory that is the source for the instruction. This addressing mode is only valid on 2.3.10 Destination Indirect Post Increment The result of an instruction using this addressing mode is placed within the memory space. Operand 1 is an the MOV instruction. The instruction using this address- address pointing to a location within the memory space, ing mode is three bytes in length. which contains an address (the indirect address) for the Table 20: destination of the instruction. The indirect address is Destination Direct Direct incremented as part of the instruction execution. The Opcode Instruction Operand 1 Operand 2 Destination Address Source Address source for the instruction is the Accumulator. This addressing mode is only valid on the MVI instruction. The instruction using this addressing mode is two bytes Example: MOV in length. ;In this case, the value ;in the memory location at [7], [8] ;address 8 is moved to the ;memory location at ;address 7. Table 22: Destination Indirect Post Increment Opcode Instruction Operand 1 Destination Address Address Example: 2.3.9 Source Indirect Post Increment The result of an instruction using this addressing mode is placed in the Accumulator. Operand 1 is an address pointing to a location within the memory space, which contains an address (the indirect address) for the source MVI [8], A of the instruction. The indirect address is incremented as part of the instruction execution. This addressing mode is only valid on the MVI instruction. The instruction using this addressing mode is two bytes in length. See Sec- ;In this case, the ;value in the memory ;location at address 8 ;is an indirect ;address. The ;Accumulator is moved ;into the memory ;location pointed to by ;the indirect address. ;The indirect address ;is then incremented. tion 7. Instruction Set in PSoC Designer: Assembly 24 Document #: 38-12010 CY Rev. *C May 17, 2005 CPU Architecture 2.4 Instruction Set Summary Table 23: Instruction Set Summary (Sorted by Mnemonic) INC [expr] INC [X+expr] INDEX JACC JC JMP JNC JNZ JZ LCALL LJMP MOV X, SP MOV A, expr MOV A, [expr] MOV A, [X+expr] MOV [expr], A MOV [X+expr], A MOV [expr], expr MOV [X+expr], expr MOV X, expr MOV X, [expr] MOV X, [X+expr] MOV [expr], X MOV A, X MOV X, A MOV A, reg[expr] MOV A, reg[X+expr] MOV [expr], [expr] MOV reg[expr], A MOV reg[X+expr], A MOV reg[expr], expr MOV reg[X+expr], expr MVI A, [ [expr]++ ] MVI [ [expr]++ ], A NOP OR A, expr OR A, [expr] OR A, [X+expr] OR [expr], A OR [X+expr], A OR [expr], expr OR [X+expr], expr OR reg[expr], expr OR reg[X+expr], expr OR F, expr C, Z C, Z Z 20 18 10 08 7E 7F 6A 6B 6C 28 6D 6E 6F 19 1A 1B 1C 1D 1E 1F 00 11 12 13 14 15 16 17 4B 4C 4D 4E 47 48 49 4A 72 31 32 33 34 35 36 37 45 46 Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z Z C, Z Document #: 38-12010 CY Rev. *C Instruction Format Flags Bytes Cycles Flags Bytes Cycles 09 4 2 ADC A, expr C, Z 76 7 2 0A 6 2 ADC A, [expr] C, Z 77 8 2 0B 7 2 ADC A, [X+expr] C, Z Fx 13 2 0C 7 2 ADC [expr], A C, Z Ex 7 2 0D 8 2 ADC [X+expr], A C, Z Cx 5 2 0E 9 3 ADC [expr], expr C, Z 8x 5 2 0F 10 3 ADC [X+expr], expr C, Z Dx 5 2 01 4 2 ADD A, expr C, Z Bx 5 2 02 6 2 ADD A, [expr] C, Z Ax 5 2 03 7 2 ADD A, [X+expr] C, Z 7C 13 3 04 7 2 ADD [expr], A C, Z 7D 7 3 05 8 2 ADD [X+expr], A C, Z 4F 4 1 06 9 3 ADD [expr], expr C, Z 50 4 2 07 10 3 ADD [X+expr], expr C, Z 51 5 2 38 5 2 ADD SP, expr 52 6 2 21 4 2 AND A, expr Z 53 5 2 22 6 2 AND A, [expr] Z 54 6 2 23 7 2 AND A, [X+expr] Z 55 8 3 24 7 2 AND [expr], A Z 56 9 3 25 8 2 AND [X+expr], A Z 57 4 2 26 9 3 AND [expr], expr Z 58 6 2 27 10 3 AND [X+expr], expr Z 59 7 2 70 4 2 AND F, expr C, Z 5A 5 2 41 9 3 AND reg[expr], expr Z 5B 4 1 42 10 3 AND reg[X+expr], expr Z 5C 4 1 64 4 1 ASL A C, Z 5D 6 2 65 7 2 ASL [expr] C, Z 5E 7 2 66 8 2 ASL [X+expr] C, Z 5F 10 3 67 4 1 ASR A C, Z 60 5 2 68 7 2 ASR [expr] C, Z 61 6 2 69 8 2 ASR [X+expr] C, Z 62 8 3 9x 11 2 CALL 63 9 3 39 5 2 CMP A, expr if (A=B) Z=1 3E 10 2 3A 7 2 CMP A, [expr] if (A