CY8C28243

CY8C28243, CY8C28403, CY8C28413 PRELIMINARY CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 ® PSoC Programmable System-on-Chip ❐ Features ■ ■ Varied Resource Options Within One PSoC Device Group Powerful Harvard Architecture Processor ❐ M8C Processor Speeds up to 24 MHz ❐ 8x8 Multiply, 32-Bit Accumulate ❐ Low Power at High Speed ❐ 3.0V to 5.25V Operating Voltage ❐ Operating Voltages Down to 1.5V Using On-Chip Switched Mode Pump (SMP) ❐ Industrial Temperature Range: -40°C to +85°C Advanced Reconfigurable Peripherals (PSoC Blocks) ❐ Up to 12 Rail-to-Rail Analog PSoC Blocks Provide: • Up to 14-Bit ADCs • Up to 9-Bit DACs • Programmable Gain Amplifiers • Programmable Filters and Comparators • Multiple ADC configurations • Dedicated SAR ADC, up to 192 ksps with Sample and Hold • Up to 4 Synchronized or Independent Delta-Sigma ADCs for Advanced Applications ❐ Up to 4 Limited Type E Analog Blocks Provide: • Dual Channel Capacitive Sensing Capability • Comparators with Programmable DAC Reference • Up to 10-bit Single-Slope ADCs ❐ Up to 12 Digital PSoC Blocks Provide: • 8 to 32-Bit Timers, Counters, and PWMs • Shift Register, CRC, and PRS Modules • Up to 3 Full-Duplex UARTs • Up to 6 Half-Duplex UARTs • Multiple Variable Data Length SPI™ Masters or Slaves • Connectable to All GPIO ❐ Complex Peripherals by Combining Blocks Precision, Programmable Clocking ❐ Internal ±2.5% 24/48 MHz Main Oscillator ❐ Optional 32.768 kHz Crystal for Precise On-Chip Clocks ❐ Optional External Oscillator, up to 24 MHz ❐ Internal Low Speed, Low Power Oscillator for Watchdog and Sleep Functionality Flexible On-Chip Memory ❐ 16K Bytes Flash Program Storage 50,000 Erase/Write Cycles ❐ 1K Bytes SRAM Data Storage ❐ In-System Serial Programming (ISSP™) ❐ Partial Flash Updates ❐ Flexible Protection Modes ❐ EEPROM Emulation in Flash Programmable Pin Configurations ❐ 25 mA Sink, 10 mA Drive on All GPIO Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on All GPIO ❐ Analog Input on All GPIO ❐ 30 mA Analog Outputs on GPIO ❐ Configurable Interrupt on all GPIO ■ ■ Additional System Resources 2 ❐ Up to 2 Hardware I C Resources • Each Resource Implements Slave, Master, or Multi-Master Modes • Operation Between 0 and 400 kHz ❐ Watchdog and Sleep Timers ❐ User-Configurable Low Voltage Detection ❐ Flexible Internal Voltage References ❐ Integrated Supervisory Circuit ❐ On-Chip Precision Voltage Reference Complete Development Tools ❐ Free Development Software (PSoC Designer™) ❐ Full Featured In-Circuit Emulator, and Programmer ❐ Full Speed Emulation ❐ Flexible and Functional Breakpoint Structure ❐ 128K Trace Memory ■ System Block Diagram Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Analog Drivers PSoC CORE System Bus Global Digital Interconnect SRAM 1K Interrupt Controller Global Analog Interconnect Flash 16K Sleep and Watchdog SROM CPU Core (M8C) ■ Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) DIGITAL SYSTEM Digital Block Array ANALOG SYSTEM Analog Block Array Analog Ref. ■ Analog Input Muxing Digital Clocks 2 MACs 4 Type 2 2 I2C Decimators Blocks POR and LVD System Resets ■ Internal Voltage Ref. Switch Mode Pump SYSTEM RESOURCES Cypress Semiconductor Corporation Document Number: 001-48111 Rev. *D • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised August 10, 2009 [+] [+] Feedback PRELIMINARY CY8C28xxx PSoC Functional Overview The PSoC family consists of many devices with On-Chip Controllers. These devices are designed to replace multiple traditional MCU based system components with one low cost single chip programmable component. A PSoC device includes configurable analog blocks, digital blocks, and interconnections. This architecture enables the user to create customized peripheral configurations to match the requirements of each individual application. In addition, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts and packages. The CY8C28xxx group of PSoC devices described in this data sheet have multiple resource configuration options available. Therefore, not every resource mentioned in this data sheet is available for each CY8C28xxx subgroup. The CY8C28x45 subgroup has a full feature set of all resources described. There are six more segmented subgroups that allow designers to use a device with only the resources and functionality necessary for a specific application. See Table 2 on page 6 to determine the resources available for each CY8C28xxx subgroup. The same information is also presented in more detail in the Ordering Information section. The architecture for this specific PSoC device family, as shown in the System Block Diagram on page 1, consists of four main areas: PSoC Core, Digital System, Analog System, and System Resources. The configurable global bus system allows all the device resources to be combined into a complete custom system. PSoC CY8C28xxx family devices have up to six I/O ports that connect to the global digital and analog interconnects, providing access to up to 12 digital blocks and up to 16 analog blocks. alone or combined with other blocks to create 8, 16, 24, and 32-bit peripherals, which are called user modules. The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. Figure 1. Digital System Block Diagram[1] Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Digital Clocks From Core To System Bus To Analog System DIGITAL SYSTEM Digital PSoC Block Array Row Input Configuration Row 0 DBC00 DBC01 DCC02 4 DCC03 4 Row Output Configuration 8 8 Row Input Configuration 8 Row 1 DBC10 DBC11 DCC12 4 DCC13 4 8 Row Output Configuration Row Input Configuration Row 2 DBC20 DBC21 DCC22 4 DCC23 4 Row Output Configuration The PSoC Core The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable general Purpose I/O (GPIO). The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microcontroller. Memory encompasses 16K bytes of Flash for program storage, 1K bytes of SRAM for data storage. The PSoC device incorporates flexible internal clock generators, including a 24 MHz internal main oscillator (IMO) accurate to 2.5% over temperature and voltage. A low power 32 kHz internal low speed oscillator (ILO) is provided for the sleep timer and watch dog timer (WDT). The 32.768 kHz external crystal oscillator (ECO) is available for use as a real time clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. PSoC GPIOs provide connections to the CPU, and digital and analog resources. Each pin’s drive mode may be selected from 8 options, which allows great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] Digital peripheral configurations include: ■ ■ ■ ■ ■ ■ ■ PWMs (8 to 16 bit, One-shot and Multi-shot capability) PWMs with Dead band/Kill (8 to 16 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) Full-duplex 8-bit UARTs (up to 3) with selectable parity Half-duplex 8-bit UARTs (up to 6) with selectable parity Variable length SPI slave and master ❐ Up to 6 total slaves and masters (8-bit) ❐ Supports 8 to 16 bit operation I2C slave, master, or multi-master (up to 2 available as System Resources) IrDA (up to 3) Pseudo Random Sequence Generators (8 to 32 bit) Cyclical Redundancy Checker/Generator (16 bit) Shift Register (2 to 32 bit) ■ ■ ■ ■ ■ The Digital System The Digital System is composed of up to 12 configurable digital PSoC blocks. Each block is an 8-bit resource that can be used Note 1. CY8C28x52 devices do not have digital block row 2. They have two digital rows with eight total digital blocks. Document Number: 001-48111 Rev. *D Page 2 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx The Analog System The Analog System is composed of up to 16 configurable analog blocks, each containing an opamp circuit that allows the creation of complex analog signal flows. Some devices in this PSoC family have an analog multiplex bus that can connect to every GPIO pin. This bus can also connect to the analog system for analysis with comparators and analog-to-digital converters. It can be split into two sections for simultaneous dual-channel processing. Some of the more common PSoC analog functions (most available as user modules) are: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Figure 2. Analog System Block Diagram for CY8C28x45 and CY8C28x52 Devices All GPIO P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6] P0[4] P0[2] P0[0] P2[6] P2[3] P2[1] Analog Mux Bus Analog-to-digital converters (6 to 14-bit resolution, up to 4, selectable as Incremental or Delta Sigma) Dedicated 10-bit SAR ADC with sample rates up to 192 ksps Synchronized, simultaneous Delta Sigma ADCs (up to 4) Filters (2 to 8 pole band-pass, low-pass, and notch) Amplifiers (up to 4, with selectable gain to 48x) Instrumentation amplifiers (up to 2, with selectable gain to 93x) Comparators (up to 6, with 16 selectable thresholds) DACs (up to 4, with 6 to 9-bit resolution) Multiplying DACs (up to 4, with 6 to 9-bit resolution) High current output drivers (up to 4 with 30 mA drive) 1.3V reference (as a System Resource) DTMF Dialer Modulators Correlators Peak detectors Many other topologies possible P2[4] P2[2] P2[0] Array Input Configuration ACI0[1:0] ACI1[1:0] ACI2[1:0] ACI3[1:0] ACI4[1:0] ACI5[1:0] Block Array ACC00 ASC10 ASD20 ACC01 ASD11 ASC21 ACC02 ASC12 ASD22 ACC03 ACE00 ACE01 ASD13 ASE10 ASE11 ASC23 Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 001-48111 Rev. *D Page 3 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx Figure 3. Analog System Block Diagram for CY8C28x43 Devices All GPIO P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6] Figure 4. Analog System Block Diagram for CY8C28x33 Devices All GPIO P0[7] P0[4] P0[5] P0[2] P0[0] P2[6] P0[3] P0[6] P0[4] P0[1] P2[3] Analog Mux Bus P0[2] P0[0] AGNDIn RefIn P2[6] P2[3] P2[4] P2[2] P2[0] P2[1] P2[1] Analog Mux Bus P2[4] Array Input Configuration Array Input Configuration ACI0[1:0] ACI1[1:0] ACI4[1:0] ACI5[1:0] ACI0[1:0] ACI1[1:0] ACI2[1:0] ACI3[1:0] Block Array Block Array ACC00 ASC10 ASD20 ACC01 ASD11 ASC21 ACC02 ASC12 ASD22 ACC03 ASD13 ASC23 ACC00 ASC10 ASD20 ACC01 ACE00 ACE01 ASD11 ASE10 ASE11 ASC21 Analog Reference Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap M8C Interface (Address Bus, Data Bus, Etc.) M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 001-48111 Rev. *D Page 4 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx Figure 5. Analog System Block Diagram for CY8C28x23 Devices P0[7] P0[5] Figure 6. Analog System Block Diagram for CY8C28x13 Devices All GPIO P0[7] P0[3] P0[4] P0[1] P2[3] P2[1] AGNDIn RefIn P0[2] P0[0] P2[6] Analog Mux Bus P0[6] P0[6] P0[4] P0[2] P0[0] P0[5] P0[3] P0[1] P2[4] ACI0[1:0] Array Input Configuration ACI1[1:0] Array Input Configuration ACI0[1:0] ACI1[1:0] Block Array ACE00 ACE01 Block Array ACC00 ASC10 ASD20 ACC01 ASD11 ASC21 ASE10 ASE11 Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap Analog Reference M8C Interface (Address Bus, Data Bus, Etc.) Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 001-48111 Rev. *D Page 5 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx System Resources System Resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. Additional resources include a multiplier, multiple decimators, switch mode pump, low voltage detection, and power on reset. Statements describing the merits of each system resource follow: ■ Table 1. PSoC Device Characteristics Analog Columns Analog Outputs Analog Inputs Analog Blocks Digital Blocks Digital I/O Digital Rows SRAM Size 2K 256 Bytes 1K 256 Bytes 256 Bytes 512 Bytes 256 Bytes 512 Bytes PSoC Part Number CY8C29x66 CY8C28xxx CY8C27x43 CY8C24x94 Flash Size 32K 16K 16K 16K 4K 8K 8K 4K 8K up to 64 up to 44 up to 44 64 4 16 12 4 up to 4 4 2 2 2 0 0 0 4 up to 6 4 2 2 2 2 2 0 12 Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. Multiply accumulate (MAC) provides fast 8-bit multiplier with 32-bit accumulate, to assist in general math and digital filters. Up to four decimators provide custom hardware filters for digital signal processing applications such as Delta-Sigma ADCs and CapSense capacitive sensor measurement. Up to two I2C resources provide 0 to 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. I2C resources have hardware address detection capability. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3V reference provides an absolute reference for the analog system, including ADCs and DACs. An integrated switch mode pump (SMP) generates normal operating voltages from a single 1.5V battery cell, providing a low cost boost converter. up to up to up to 3 12 44 2 1 1 1 1 1 0 8 4 4 4 4 4 0 12 48 12 12 28 8 28 up to 1K 12/4[2] 12 6 6 4 4[3] 4[3] 3[4] ■ ■ CY8C24x23A up to 24 CY8C23x33 CY8C21x34 CY8C21x23 CY8C20x34 up to up to 28 16 up to 28 ■ ■ ■ ■ The devices covered by this data sheet all have the same architecture, specifications, and ratings. However, the amount of some hardware resources varies from device to device within the group. The following table lists resources available for the specific device subgroups covered by this data sheet. Table 2. CY8C28xxx Device Characteristics Digital Blocks Regular Analog Blocks Limited Analog Blocks Decimators CapSense Analog Outputs 0 0 2 2 4 4 4 HW I2C Analog Inputs PSoC Device Characteristics There are other PSoC device groups in addition to the one described in this data sheet. These other PSoC device groups offer even more resource options. The following table lists the resources available for specific PSoC device groups. The PSoC device group covered by this data sheet is highlighted. PSoC Part Number CY8C28x03 CY8C28x13 CY8C28x23 CY8C28x33 CY8C28x43 CY8C28x45 CY8C28x52 N Y N Y N Y Y 12 12 12 12 12 12 8 0 0 6 6 12 12 12 0 4 0 4 0 4 4 2 1 2 1 2 2 1 0 2 2 4 4 4 4 up to up to 24 8 up to up to 40 40 up to up to 44 10 up to up to 40 40 up to up to 44 44 up to up to 44 44 up to up to 24 24 Notes 2. Has 12 regular analog blocks and four limited Type-E analog blocks 3. Limited analog functionality. 4. Two analog blocks and one CapSense. Document Number: 001-48111 Rev. *D Digital I/O Page 6 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx Getting Started The quickest way to understand PSoC silicon is to read this data sheet and then use the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the PSoC integrated circuit and presents specific pin, register, and electrical specifications. For in depth information, along with detailed programming details, see the PSoC® Programmable System-on-Chip Technical Reference Manual for CY8C28xxx PSoC devices. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device data sheets on the web at www.cypress.com/psoc. PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family. PSoC Designer Software Subsystems System-Level View A drag-and-drop visual embedded system design environment based on PSoC Express. In the system level view you create a model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state based upon any or all other system devices. Based upon the design, PSoC Designer automatically selects one or more PSoC On-Chip Controllers that match your system requirements. PSoC Designer generates all embedded code, then compiles and links it into a programming file for a specific PSoC device. Chip-Level View The chip-level view is a more traditional integrated development environment (IDE) based on PSoC Designer 4.4. Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time. Hybrid Designs You can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. All views of the project share a common code editor, builder, and common debug, emulation, and programming tools. Code Generation Tools PSoC Designer supports multiple third party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours. Assemblers. The assemblers allow assembly code to merge seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Page 7 of 65 Application Notes Application notes are an excellent introduction to the wide variety of possible PSoC designs. They are located here: www.cypress.com/psoc. Select Application Notes under the Documentation tab. Development Kits PSoC Development Kits are available online from Cypress at www.cypress.com/shop and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Training Free PSoC technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training. The training covers a wide variety of topics and skill levels to assist you in your designs. CYPros Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to www.cypress.com/cypros. Solutions Library Visit our growing library of solution focused designs at www.cypress.com/solutions. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Technical Support For assistance with technical issues, search KnowledgeBase articles and forums at www.cypress.com/support. If you cannot find an answer to your question, call technical support at 1-800-541-4736. Development Tools PSoC Designer is a Microsoft® Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE runs on Windows XP or Windows Vista. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built-in support for third-party assemblers and C compilers. Document Number: 001-48111 Rev. *D [+] [+] Feedback PRELIMINARY CY8C28xxx Debugger commands allow the designer to read and program and read and write data memory, read and write I/O registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. Width Modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. Both the system-level drivers and chip-level user modules are documented in data sheets that are viewed directly in the PSoC Designer. These data sheets explain the internal operation of the component and provide performance specifications. Each data sheet describes the use of each user module parameter or driver property, and other information you may need to successfully implement your design. In-Circuit Emulator A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. Organize and Connect You can build signal chains at the chip level by interconnecting user modules to each other and the I/O pins, or connect system level inputs, outputs, and communication interfaces to each other with valuator functions. In the system-level view, selecting a potentiometer driver to control a variable speed fan driver and setting up the valuators to control the fan speed based on input from the pot selects, places, routes, and configures a programmable gain amplifier (PGA) to buffer the input from the potentiometer, an analog to digital converter (ADC) to convert the potentiometer’s output to a digital signal, and a PWM to control the fan. In the chip-level view, perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources. Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process can be summarized in the following four steps: 1. Select components 2. Configure components 3. Organize and Connect 4. Generate, Verify, and Debug Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, perform the “Generate Application” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. Both system-level and chip-level designs generate software based on your design. The chip-level design provides application programming interfaces (APIs) with high level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed. The system-level design also generates a C main() program that completely controls the chosen application and contains placeholders for custom code at strategic positions allowing you to further refine the software without disrupting the generated code. A complete code development environment allows you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside the PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the In-Circuit Emulator (ICE) where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. Select Components Both the system-level and chip-level views provide a library of prebuilt, pretested hardware peripheral components. In the system-level view, these components are called “drivers” and correspond to inputs (a thermistor, for example), outputs (a brushless DC fan, for example), communication interfaces (I2C-bus, for example), and the logic to control how they interact with one another (called valuators). In the chip-level view, the components are called “user modules”. User modules make selecting and implementing peripheral devices simple, and come in analog, digital, and mixed signal varieties. Configure Components Each of the components you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a Pulse Document Number: 001-48111 Rev. *D Page 8 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx Document Conventions Acronyms Used The following table lists the acronyms that are used in this document. Acronym AC ADC API CPU CT DAC DC ECO EEPROM FSR GPIO GUI HBM ICE ILO IMO I/O IPOR LSb LVD MSb PC PLL POR PPOR PSoC PWM SAR SC SLIMO SMP SRAM Description alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current external crystal oscillator electrically erasable programmable read-only memory full scale range general purpose I/O graphical user interface human body model in-circuit emulator internal low speed oscillator internal main oscillator input/output imprecise power on reset least-significant bit low voltage detect most-significant bit program counter phase-locked loop power on reset precision power on reset Programmable System-on-Chip pulse width modulator successive approximation register switched capacitor slow IMO switch mode pump static random access memory Units of Measure A units of measure table is located in the Electrical Specifications section. Table 8 on page 31 lists all the abbreviations used to measure the PSoC devices. Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal. Document Number: 001-48111 Rev. *D Page 9 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx Pinouts This section describes, lists, and illustrates the CY8C28xxx PSoC device pins and pinout configurations. The CY8C28xxx PSoC devices are available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, SMP, and XRES are not capable of Digital I/O. 20-Pin Part Pinout Table 3. 20-Pin Part Pinout (SSOP) Type Pin No. Digital Analog 1 I/O I, M, S Pin Name Description CY8C28243 20-Pin PSoC Device 20 19 18 17 16 15 14 13 12 11 Vdd P0[6], M, AI, S P0[4], M, AIO, S P0[2], M, AIO, S P0[0], M, AI, S XRES P1[6], M, I2C1 SCL P1[4], M, EXTCLK P1[2], M, I2C1 SDA P1[0], M, XTALout, I2C0 SDA S, AI, M, P0[7] 1 P0[7] Analog column mux and SAR ADC input.[6] 2 S, AIO, M, P0[5] S, AIO, M, P0[3] 3 2 I/O I/O, M, S P0[5] Analog column mux and SAR ADC S, AI, M, P0[1] 4 input. Analog column output.[6, 7] SMP 5 SSOP 3 I/O I/O, M, S P0[3] Analog column mux and SAR ADC I2C0 SCL, M, P1[7] 6 input. Analog column output.[6, 7] I2C0 SDA, M, P1[5] 7 4 I/O I, M, S P0[1] Analog column mux and SAR ADC M, P1[3] 8 [6] input. I2C0 SCL, XTALin, M, P1[1] 9 Vss 5 Output SMP Switch Mode Pump (SMP) 10 connection to external components. 6 I/O M P1[7] I2C0 Serial Clock (SCL). 7 I/O M P1[5] I2C0 Serial Data (SDA). 8 I/O M P1[3] 9 I/O M P1[1] Crystal Input (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK[5]. 10 Power Vss Ground connection. 11 I/O M P1[0] Crystal Output (XTALout), I2C0 Serial Data (SDA), ISSP-SDATA[5]. 12 I/O M P1[2] I2C1 Serial Data (SDA).[8] 13 I/O M P1[4] Optional External Clock Input (EXTCLK). 14 I/O M P1[6] I2C1 Serial Clock (SCL).[8] 15 Input XRES Active high external reset with internal pull down. 16 I/O I, M, S P0[0] Analog column mux and SAR ADC input.[6] 17 I/O I/O, M, S P0[2] Analog column mux and SAR ADC input. Analog column output.[6, 9] 18 I/O I/O, M, S P0[4] Analog column mux and SAR ADC input. Analog column output.[6, 9] 19 I/O I, M, S P0[6] Analog column mux and SAR ADC input.[6] 20 Power Vdd Supply voltage. LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input. Notes 5. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Programmable System-on-Chip Technical Reference Manual for CY8C28xxx PSoC devices for details. 6. CY8C28x52 and CY8C28x23 devices do not have a SAR ADC. Therefore, this pin does not function as a SAR ADC input for these devices. 7. CY8C28x13 and CY8C28x03 devices do not have any analog output buffers. Therefore, this pin does not function as an analog column output for these devices. 8. CY8C28x52, CY8C28x13, and CY8C28x33 devices only have one I2C block. Therefore, this GPIO does not function as an I2C pin for these devices. 9. CY8C28x33, CY8C28x23, CY8C28x13, and CY8C28x03 devices do not have an analog output buffer for this pin. Therefore, this pin does not function as an analog column output for these devices. Document Number: 001-48111 Rev. *D Page 10 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx 28-Pin Part Pinout Table 4. 28-Pin Part Pinout (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input I, M I, M M M I, M, S I/O, M, S I/O, M, S I, M, S Power I/O I/O I/O I/O Power M M M M Type Digital I/O I/O I/O I/O I/O I/O I/O I/O Analog I, M, S I/O, M, S I/O, M, S I, M, S M M I, M I, M Output M M M M Pin Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] SMP P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] Crystal Input (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK[5]. Ground connection. Crystal Output (XTALout), I2C0 Serial Data (SDA), ISSP-SDATA[5]. I2C1 Serial Data (SDA).[8] Optional External Clock Input (EXTCLK). I2C1 Serial Clock (SCL).[8] Direct switched capacitor block input.[10] Direct switched capacitor block input.[10] Switch Mode Pump (SMP) connection to external components. I2C0 Serial Clock (SCL). I2C0 Serial Data (SDA). Description CY8C28403, CY8C28413, CY8C28433, CY8C28445, and CY8C28452 28-Pin PSoC Devices S, AI, M, P0[7] S, AIO, M, P0[5] S, AIO, M, P0[3] S, AI, M, P0[1] M, P2[7] M, P2[5] AI, M, P2[3] AI, M, P2[1] SMP I2C0 SCL, M, P1[7] I2C0 SDA, M, P1[5] M, P1[3] I2C0 SCL, XTALin, M, P1[1] Vss Analog column mux and SAR ADC input.[6] Analog column mux and SAR ADC input. Analog column output.[6, 7] Analog column mux and SAR ADC input. Analog column output.[6, 7] Analog column mux and SAR ADC input.[6] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd P0[6], M, AI, S P0[4], M, AIO, S P0[2], M, AIO, S P0[0], M, AI, S P2[6], M, External VRef P2[4], M, External AGND P2[2], M, AI P2[0], M, AI XRES P1[6], M, I2C1 SCL P1[4], M, EXTCLK P1[2], M, I2C1 SDA P1[0], M, XTALout, I2C0 SDA XRES Active high external reset with internal pull down. P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Direct switched capacitor block input.[11] Direct switched capacitor block input.[11] External Analog Ground (AGND). External Voltage Reference (VRef). Analog column mux and SAR ADC input.[6] Analog column mux and SAR ADC input. Analog column output.[6, 9] Analog column mux and SAR ADC input. Analog column output.[6, 9] Analog column mux and SAR ADC input.[6] Supply voltage. LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input Notes 10. This pin is not a direct switched capacitor block analog input for CY8C28x03 and CY8C28x13 devices. 11. This pin is not a direct switched capacitor block analog input for CY8C28x03, CY8C28x13, CY8C28x23, and CY8C28x33 devices. Document Number: 001-48111 Rev. *D Page 11 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx 44-Pin Part Pinout Table 5. 44-Pin Part Pinout (TQFP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Type Digital Analog I/O M I/O I, M I/O I, M I/O M I/O M I/O M I/O M Output I/O I/O I/O I/O I/O I/O I/O I/O Output I/O I/O I/O I/O I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O M M M M I, M I, M M M I, M, S I/O, M S I/O, M, S M M M M M M M M M M M M M M M M Pin Name P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd P0[7] P0[5] P0[3] Description Direct switched capacitor block input.[10] Direct switched capacitor block input.[10] CY8C28513, CY8C28533, and CY8C28545 44-Pin PSoC Devices P2[7], M P0[1], M, AI, S P0[3], M, AIO, S P0[5], M, AIO, S P0[7], M, AI, S Vdd P0[6], M, AI, S P0[4], M, AIO, S P0[2], M, AIO, S P0[0], M, AI, S P2[6], M, External VRef M, P2[5] AI, M, P2[3] AI, M, P2[1] M, P4[7] M, P4[5] M, P4[3] M, P4[1] SMP M, P3[7] M, P3[5] M, P3[3] M, P3[1] I2C0 SCL, M, P1[7] I2C0 SDA, M, P1[5] M, P1[3] I2C0 SCL, XTALin, M, P1[1] Vss I2C0 SDA, XTALout, M, P1[0] I2C1 SDA, M, P1[2] EXTCLK, M, P1[4] I2C1 SCL, M, P1[6] I2C1 SDA, M, P3[0] 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 Switch Mode Pump (SMP) connection to external components. I2C0 Serial Clock (SCL). I2C0 Serial Data (SDA). Crystal Input (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK[5]. Ground connection. Crystal Output (XTALout), I2C0 Serial Data (SDA), ISSP-SDATA[5]. I2C1 Serial Data (SDA).[8] Optional External Clock Input (EXTCLK). I2C1 Serial Clock (SCL).[8] I2C1 Serial Data (SDA).[8] I2C1 Serial Clock (SCL).[8] TQFP 33 32 31 30 29 28 27 26 25 24 23 P2[4], M, External AGND P2[2], M, AI P2[0], M, AI P4[6], M P4[4], M P4[2], M P4[0], M XRES P3[6], M P3[4], M P3[2], M, I2C1 SCL Active high external reset with internal pull down. I, M, S Power I/O I, M, S I/O I/O, M, S I/O I/O, M, S 43 I/O I, M, S P0[1] 44 I/O P2[7] LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input. Direct switched capacitor block input.[11] Direct switched capacitor block input.[11] External Analog Ground (AGND). External Voltage Reference (VRef). Analog column mux and SAR ADC input.[6] Analog column mux and SAR ADC input. Analog column output.[6, 9] Analog column mux and SAR ADC input. Analog column output.[6, 9] Analog column mux and SAR ADC input.[6] Supply voltage. Analog column mux and SAR ADC input.[6] Analog column mux and SAR ADC input. Analog column output.[6, 7] Analog column mux and SAR ADC input. Analog column output.[6, 7] Analog column mux and SAR ADC input.[6] Document Number: 001-48111 Rev. *D Page 12 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx 48-Pin Part Pinout Table 6. 48-Pin Part Pinout (QFN[12]) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Type Digital Analog I/O I, M I/O I, M I/O M I/O M I/O M I/O M Output I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O M M M M I, M I, M M M I, M, S M M M M M M M M M M M M M M M M M M M M Pin Name P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] Description Direct switched capacitor block input.[10] Direct switched capacitor block input.[10] CY8C28623, CY8C28643, and CY8C28645 48-Pin PSoC Devices P2[5], M P2[7], M P0[1], M, AI, S P0[3], M, AIO, S P0[5], M, AIO, S P0[7], M, AI, S Vdd P0[6], M, AI, S P0[4], M, AIO, S P0[2], M, AIO, S P0[0], M, AI, S P2[6], M, External VRef Switch Mode Pump (SMP) connection to external components. I2C0 Serial Clock (SCL). I2C0 Serial Data (SDA). Crystal Input (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK[5]. Ground connection. Crystal Output (XTALout), I2C0 Serial Data (SDA), ISSP-SDATA[5]. I2C1 Serial Data (SDA).[8] Optional External Clock Input (EXTCLK). I2C1 Serial Clock (SCL).[8] P1[6] P5[0] P5[2] P3[0] I2C1 Serial Data (SDA).[8] P3[2] I2C1 Serial Clock (SCL).[8] P3[4] P3[6] XRES Active high external reset with internal pull down. P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] Pin No. 41 42 43 44 45 Type Digital Analog I/O I, M, S Power I, M, S I/O, M, S I/O, M, S I, M, S M, P5[1] I2C0 SCL, M, P1[7] I2C0 SDA, M, P1[5] M, P1[3] I2C0 SCL, XTALin, M, P1[1] Vss I2C0 SDA, XTALout, M, P1[0] I2C1 SDA, M, P1[2] EXTCLK, M, P1[4] I2C1 SCL, M, P1[6] M, P5[0] M, P5[2] 13 14 15 16 17 18 19 20 21 22 23 24 AI, M, P2[3] AI, M, P2[1] M, P4[7] M, P4[5] M, P4[3] M, P4[1] SMP M, P3[7] M, P3[5] M, P3[3] M, P3[1] M, P5[3] 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 QFN (Top View) 36 35 34 33 32 31 30 29 28 27 26 25 P2[4], M, External AGND P2[2], M, AI P2[0], M, AI P4[6], M P4[4], M P4[2], M P4[0], M XRES P3[6], M P3[4], M P3[2], M, I2C1 SCL P3[0], M, I2C1 SDA Pin Name P0[6] Vdd P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] Description Analog column mux and SAR ADC input.[6] Supply voltage. Analog column mux and SAR ADC input.[6] Analog column mux and SAR ADC input. Analog column output.[6, 7] Analog column mux and SAR ADC input. Analog column output.[6, 7] Analog column mux and SAR ADC input.[6] Direct switched capacitor block input.[11] Direct switched capacitor block input.[11] External Analog Ground (AGND). External Voltage Reference (VRef). I/O I/O I/O Analog column mux and SAR ADC 46 I/O input.[6] 39 I/O I/O, M, S P0[2] Analog column mux and SAR ADC input. 47 I/O M Analog column output.[6, 9] 40 I/O I/O, M, S P0[4] Analog column mux and SAR ADC input. 48 I/O M Analog column output.[6, 9] LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input. Note 12. The QFN package has a center pad that must be connected to ground (Vss) Document Number: 001-48111 Rev. *D Page 13 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx 56-Pin Part Pinout The 56-pin SSOP part is for the CY8C28000 On-Chip Debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. Table 7. 56-Pin Part Pinout (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O M M M M M M M M M M I/O I/O Power M M I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O OCD OCD Output M M M M M M M M I, M, S I/O, M, S I/O, M, S I, M, S M M I I M M I, M I, M M M Type Digital Analog Pin Name NC P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] OCDE OCD even data I/O. OCDO OCD odd data output. SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] NC P1[3] P1[1] Vdd NC NC P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] I2C1 Serial Data (SDA). I2C1 Serial Clock (SCL). Crystal Input (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK[5]. Ground connection. No connection. No connection. Crystal Output (XTALout), I2C0 Serial Data (SDA), ISSP-SDATA[5]. I2C1 Serial Data (SDA). Optional External Clock Input (EXTCLK). I2C1 Serial Clock (SCL). I2C0 Serial Clock (SCL). I2C0 Serial Data (SDA). No connection. Switch Mode Pump (SMP) connection to required external components. Direct switched capacitor block input. Direct switched capacitor block input. Description No connection. Analog column mux and SAR ADC input. Analog column mux and SAR ADC input. Analog column output. Analog column mux and SAR ADC input. Analog column output. Analog column mux and SAR ADC input. CY8C28000 56-Pin PSoC Device NC S, AI, M, P0[7] S, AIO, M, P0[5] S, AIO, M, P0[3] S, AI, M, P0[1] M, P2[7] M, P2[5] AI, M, P2[3] AI, M, P2[1] M, P4[7] M, P4[5] M, P4[3] M, P4[1] OCDE OCDO SMP M, P3[7] M, P3[5] M, P3[3] M, P3[1] M, P5[3] M, P5[1] I2C0 SCL, M, P1[7] I2C0 SDA, M, P1[5] NC M, P1[3] SCLK, I2C0 SCL, XTALIn, M, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 Vdd P0[6], M, AI, S P0[4], M, AIO, S P0[2], M, AIO, S P0[0], M, AI, S P2[6], M, External VRef P2[4], M, External AGND P2[2], M, AI P2[0], M, AI P4[6], M P4[4], M P4[2], M P4[0], M CCLK HCLK XRES P3[6], M P3[4], M P3[2], M, I2C1 SCL P3[0], M, I2C1 SDA P5[2], M P5[0], M P1[6], M, I2C1 SCL P1[4], M, EXTCLK P1[2], M, I2C1 SDA P1[0], M, XTALOut, I2C0 SDA, SDATA NC NC SSOP Not for Production Document Number: 001-48111 Rev. *D Page 14 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx Table 7. 56-Pin Part Pinout (SSOP) (continued) Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 OCD OCD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Type Digital Analog Input M M M M M M I, M I, M M M I, M, S I/O, M, S I/O, M, S I, M, S Power Pin Name Description XRES Active high external reset with internal pull down. HCLK OCD high-speed clock output. CCLK OCD CPU clock output. P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VRef). Analog column mux and SAR ADC input. Analog column mux and SAR ADC input. Analog column output. Analog column mux and SAR ADC input. Analog column output. Analog column mux and SAR ADC input. Supply voltage. LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, M = Analog Mux Bus Input, and OCD = On-Chip Debug. Document Number: 001-48111 Rev. *D Page 15 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx Register Reference This section lists the registers of the CY8C28xxx PSoC devices. For detailed register information, reference the PSoC Programmable System-on-Chip Technical Reference Manual for CY8C28xxx PSoC devices. Register Conventions The register conventions specific to this section are listed in the following table. Convention R W L C # Description Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific Register Mapping Tables CY8C28xxx PSoC devices have a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks. The XIO bit in the Flag register (CPU_F) determines which bank of registers CPU instructions access. When the XIO bit is set the registers in Bank 1 are accessed by CPU instructions. When the XIO bit is cleared the registers in Bank 0 are accessed by CPU instructions. Note In the following register mapping tables, blank fields are reserved and should not be accessed. Document Number: 001-48111 Rev. *D Page 16 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx CY8C28x03 Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW SADC_DH SADC_DL TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 I2C1_DR Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBC20DR0 DBC20DR1 DBC20DR2 DBC20CR0 DBC21DR0 DBC21DR1 DBC21DR2 DBC21CR0 DCC22DR0 DCC22DR1 DCC22DR2 DCC22CR0 DCC23DR0 DCC23DR1 DCC23DR2 DCC23CR0 Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F # Access is bit specific. RW RW RW RW RW RW RW MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 Access # W RW # # W RW # # W RW # # W RW # Name Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW CPU_SCR1 CPU_F MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT I2C1_SCR I2C1_MSCR CUR_PP STK_PP Access Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF # # RL W W R R RW RW RW RW RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W # # RW RW Access RW RW RW RW RW RW RW RW DCC13CR0 3F # Blank fields are Reserved and should not be accessed. RDI1DSM BF RW CPU_SCR0 *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *D Page 17 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx CY8C28x03 Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW SADC_TSCR0 SADC_TSCR1 I2C1_CFG TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F # Access is bit specific. RW RW RW RW RW RW RW GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR SADC_CR0 SADC_CR1 SADC_CR2 SADC_CR3 SADC_CR4 I2C0_ADDR I2C1_ADDR AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDIODSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name SADC_TSCMPL SADC_TSCMPH Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW CPU_SCR1 CPU_SCR0 FLS_PR1 CPU_F IMO_TR ILO_TR BDG_TR ECO_TR OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU Access RW RW Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF # # RW RL RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Access RW RW RW RW RW RW RW RW Blank fields are Reserved and should not be accessed. *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *D Page 18 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx CY8C28x13 Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW SADC_DH SADC_DL TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 AMUX_CFG Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBC20DR0 DBC20DR1 DBC20DR2 DBC20CR0 DBC21DR0 DBC21DR1 DBC21DR2 DBC21CR0 DCC22DR0 DCC22DR1 DCC22DR2 DCC22CR0 DCC23DR0 DCC23DR1 DCC23DR2 DCC23CR0 Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F # Access is bit specific. RW RW RW RW RW RW MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RW DEC0_DH DEC0_DL DEC1_DH DEC1_DL Access # W RW # # W RW # # W RW # # W RW # Name Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW DAC1_D DAC0_D CPU_SCR1 CPU_F DEC_CR0* DEC_CR1* MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 RC RC RC RC IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT CUR_PP STK_PP Access Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW RW # # RL RW RW W W R R RW RW RW RW RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W RW RW Access RW RW RW RW RW RW RW RW DCC13CR0 3F # Blank fields are Reserved and should not be accessed. RDI1DSM BF RW CPU_SCR0 *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *D Page 19 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx CY8C28x13 Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ACE0_CR1 ACE0_CR2 ACE0_CR3 ACE_CMP_GI_EN ACE_ALT_CR0 ACE_ABF_CR0 ACE_AMX_IN ACE_CMP_CR0 ACE_CMP_CR1 SADC_TSCR0 SADC_TSCR1 ACE_AMD_CR0 TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 AMUX_CFG1 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDIODSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM RW GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR SADC_CR0 SADC_CR1 SADC_CR2 SADC_CR3 SADC_CR4 I2C0_ADDR DEC_CR5 DEC1_CR0 DEC0_CR0 DEC_CR3 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ACE01CR1 ACE01CR2 ASE11CR0 ACE_CLK_CR0 ACE_CLK_CR1 ACE_CLK_CR3 ACE_PWM_CR ACE_ADC0_CR ACE_ADC1_CR Name SADC_TSCMPL SADC_TSCMPH ACE_AMD_CR1 Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW IDAC_CR0 CPU_SCR1 CPU_SCR0 FLS_PR1 CPU_F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 IDAC_CR1 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR IDAC_CR2 IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5 RW RW RW RW RW RW RW RW RW RW GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU DEC0_CR DEC1_CR RW RW RW Access RW RW RW Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW # # RW RL RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Access RW RW RW RW RW RW RW RW Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *D Page 20 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx CY8C28x23 Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 AMX_IN AMUX_CFG CLK_CR3 ARF_CR CMP_CR0 ASY_CR CMP_CR1 I2C1_DR Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBC20DR0 DBC20DR1 DBC20DR2 DBC20CR0 DBC21DR0 DBC21DR1 DBC21DR2 DBC21CR0 DCC22DR0 DCC22DR1 DCC22DR2 DCC22CR0 DCC23DR0 DCC23DR1 DCC23DR2 DCC23CR0 Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F # Access is bit specific. RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # # RW RW MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 DEC0_DH DEC0_DL DEC1_DH DEC1_DL Access # W RW # # W RW # # W RW # # W RW # ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW CPU_SCR1 CPU_F RC RC RC RC RW RW RW RW RW RW RW RW IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT I2C1_SCR I2C1_MSCR DEC_CR0* DEC_CR1* MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 CUR_PP STK_PP Access RW RW RW RW RW RW RW RW Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF # # RL RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W # # RW RW W W R R RW RW RW RW RW RW Access RW RW RW RW RW RW RW RW DCC13CR0 3F # Blank fields are Reserved and should not be accessed. RDI1DSM BF RW CPU_SCR0 *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *D Page 21 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx CY8C28x23 Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW I2C1_CFG TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 CLK_CR2 AMD_CR1 ALT_CR0 CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F # Access is bit specific. RW RW RW RW RW I2C0_ADDR I2C1_ADDR AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDIODSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM RW RW RW RW RW RW RW RW GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR DEC_CR5 DEC1_CR0 DEC0_CR0 DEC_CR3 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW CPU_SCR1 CPU_SCR0 FLS_PR1 CPU_F RW RW RW RW RW RW RW RW IMO_TR ILO_TR BDG_TR ECO_TR OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP RW RW RW RW RW RW GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU DEC0_CR DEC1_CR Access Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF # # RW RL RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Access RW RW RW RW RW RW RW RW Blank fields are Reserved and should not be accessed. *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *D Page 22 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx CY8C28x33 Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW SADC_DH SADC_DL TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 AMX_IN AMUX_CFG CLK_CR3 ARF_CR CMP_CR0 ASY_CR CMP_CR1 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBC20DR0 DBC20DR1 DBC20DR2 DBC20CR0 DBC21DR0 DBC21DR1 DBC21DR2 DBC21CR0 DCC22DR0 DCC22DR1 DCC22DR2 DCC22CR0 DCC23DR0 DCC23DR1 DCC23DR2 DCC23CR0 Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F # Access is bit specific. RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # # RW DEC0_DH DEC0_DL DEC1_DH DEC1_DL DEC2_DH DEC2_DL DEC3_DH DEC3_DL MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 Access # W RW # # W RW # # W RW # # W RW # ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE RC RC RC RC RC RC RC RC W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW DAC1_D DAC0_D CPU_SCR1 CPU_F DEC_CR0* DEC_CR1* MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 RW RW RW RW RW RW RW RW IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT CUR_PP STK_PP Access RW RW RW RW RW RW RW RW Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW RW # # RL RW RW W W R R RW RW RW RW RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W RW RW Access RW RW RW RW RW RW RW RW DCC13CR0 3F # Blank fields are Reserved and should not be accessed. RDI1DSM BF RW CPU_SCR0 *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *D Page 23 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx CY8C28x33 Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ACE0_CR1 ACE0_CR2 ACE0_CR3 ACE_CMP_GI_EN ACE_ALT_CR0 ACE_ABF_CR0 ACE_AMX_IN ACE_CMP_CR0 ACE_CMP_CR1 SADC_TSCR0 SADC_TSCR1 ACE_AMD_CR0 TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 CLK_CR2 AMUX_CFG1 AMD_CR1 ALT_CR0 CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDIODSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM RW RW RW RW RW RW RW RW RW GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR SADC_CR0 SADC_CR1 SADC_CR2 SADC_CR3 SADC_CR4 I2C0_ADDR DEC3_CR0 DEC2_CR0 DEC_CR5 DEC1_CR0 DEC_CR4 DEC0_CR0 DEC_CR3 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ACE01CR1 ACE01CR2 ASE11CR0 ACE_CLK_CR0 ACE_CLK_CR1 ACE_CLK_CR3 ACE_PWM_CR ACE_ADC0_CR ACE_ADC1_CR Name SADC_TSCMPL SADC_TSCMPH ACE_AMD_CR1 Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW IDAC_CR0 CPU_SCR1 CPU_SCR0 FLS_PR1 CPU_F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU DEC0_CR DEC1_CR DEC2_CR DEC3_CR MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 IDAC_CR1 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR IDAC_CR2 IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5 RW RW RW RW RW RW RW Access RW RW RW Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW # # RW RL RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Access RW RW RW RW RW RW RW RW Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *D Page 24 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx CY8C28x43 Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW SADC_DH SADC_DL TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 ACB02CR3 ACB02CR0 ACB02CR1 ACB02CR2 ACB03CR3 ACB03CR0 ACB03CR1 AMX_IN AMUX_CFG CLK_CR3 ARF_CR CMP_CR0 ASY_CR CMP_CR1 I2C1_DR Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBC20DR0 DBC20DR1 DBC20DR2 DBC20CR0 DBC21DR0 DBC21DR1 DBC21DR2 DBC21CR0 DCC22DR0 DCC22DR1 DCC22DR2 DCC22CR0 DCC23DR0 DCC23DR1 DCC23DR2 DCC23CR0 Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # # RW RW Access # W RW # # W RW # # W RW # # W RW # Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 DEC0_DH DEC0_DL DEC1_DH DEC1_DL DEC2_DH DEC2_DL DEC3_DH DEC3_DL MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RC RC RC RC RC RC RC RC W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW CPU_SCR1 CPU_F IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT I2C1_SCR I2C1_MSCR DEC_CR0* DEC_CR1* MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 CUR_PP STK_PP Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF # # RL RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W # # RW RW W W R R RW RW RW RW RW RW Access RW RW RW RW RW RW RW RW DCC13CR0 3F # ACB03CR2 Blank fields are Reserved and should not be accessed. 7F RW # Access is bit specific. RDI1DSM BF RW CPU_SCR0 *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *D Page 25 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx CY8C28x43 Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW SADC_TSCR0 SADC_TSCR1 CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN CMP_GO_EN1 AMD_CR1 ALT_CR0 ALT_CR1 CLK_CR2 AMUX_CFG1 I2C1_CFG TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F # Access is bit specific. RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR SADC_CR0 SADC_CR1 SADC_CR2 SADC_CR3 SADC_CR4 I2C0_ADDR I2C1_ADDR AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDIODSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM DEC3_CR0 DEC2_CR0 DEC_CR5 DEC1_CR0 DEC_CR4 DEC0_CR0 DEC_CR3 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name SADC_TSCMPL SADC_TSCMPH Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW CPU_SCR1 CPU_SCR0 FLS_PR1 CPU_F IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5 RW OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP RW RW RW RW RW RW GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU DEC0_CR DEC1_CR DEC2_CR DEC3_CR MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 Access RW RW Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF # # RW RL RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Access RW RW RW RW RW RW RW RW Blank fields are Reserved and should not be accessed. *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *D Page 26 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx CY8C28x45 Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW SADC_DH SADC_DL TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 ACB02CR3 ACB02CR0 ACB02CR1 ACB02CR2 ACB03CR3 ACB03CR0 ACB03CR1 AMX_IN AMUX_CFG CLK_CR3 ARF_CR CMP_CR0 ASY_CR CMP_CR1 I2C1_DR Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBC20DR0 DBC20DR1 DBC20DR2 DBC20CR0 DBC21DR0 DBC21DR1 DBC21DR2 DBC21CR0 DCC22DR0 DCC22DR1 DCC22DR2 DCC22CR0 DCC23DR0 DCC23DR1 DCC23DR2 DCC23CR0 Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # # RW RW Access # W RW # # W RW # # W RW # # W RW # Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 DEC0_DH DEC0_DL DEC1_DH DEC1_DL DEC2_DH DEC2_DL DEC3_DH DEC3_DL MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RC RC RC RC RC RC RC RC W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW DAC1_D DAC0_D CPU_SCR1 CPU_F IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT I2C1_SCR I2C1_MSCR DEC_CR0* DEC_CR1* MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 CUR_PP STK_PP Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW RW # # RL RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W # # RW RW W W R R RW RW RW RW RW RW Access RW RW RW RW RW RW RW RW DCC13CR0 3F # ACB03CR2 Blank fields are Reserved and should not be accessed. 7F RW # Access is bit specific. RDI1DSM BF RW CPU_SCR0 *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *D Page 27 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx CY8C28x45 Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ACE0_CR1 ACE0_CR2 ACE0_CR3 ACE_CMP_GI_EN ACE_ALT_CR0 ACE_ABF_CR0 ACE_AMX_IN ACE_CMP_CR0 ACE_CMP_CR1 SADC_TSCR0 SADC_TSCR1 ACE_AMD_CR0 CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN CMP_GO_EN1 AMD_CR1 ALT_CR0 ALT_CR1 CLK_CR2 AMUX_CFG1 I2C1_CFG TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR SADC_CR0 SADC_CR1 SADC_CR2 SADC_CR3 SADC_CR4 I2C0_ADDR I2C1_ADDR AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDIODSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM DEC3_CR0 DEC2_CR0 DEC_CR5 DEC1_CR0 DEC_CR4 DEC0_CR0 DEC_CR3 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ACE01CR1 ACE01CR2 ASE11CR0 ACE_CLK_CR0 ACE_CLK_CR1 ACE_CLK_CR3 ACE_PWM_CR ACE_ADC0_CR ACE_ADC1_CR Name SADC_TSCMPL SADC_TSCMPH ACE_AMD_CR1 Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW IDAC_CR0 CPU_SCR1 CPU_SCR0 FLS_PR1 CPU_F RW RW RW RW RW RW RW Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU DEC0_CR DEC1_CR DEC2_CR DEC3_CR MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 IDAC_CR1 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR IDAC_CR2 IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5 Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW # # RW RL RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Access RW RW RW RW RW RW RW RW Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *D Page 28 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx CY8C28x52 Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 ACB02CR3 ACB02CR0 ACB02CR1 ACB02CR2 ACB03CR3 ACB03CR0 ACB03CR1 AMX_IN AMUX_CFG CLK_CR3 ARF_CR CMP_CR0 ASY_CR CMP_CR1 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # # RW Access Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 DEC0_DH DEC0_DL DEC1_DH DEC1_DL DEC2_DH DEC2_DL DEC3_DH DEC3_DL MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RC RC RC RC RC RC RC RC W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW DAC1_D DAC0_D CPU_SCR1 CPU_F DEC_CR0* DEC_CR1* MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT CUR_PP STK_PP Name Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW RW # # RL RW RW W W R R RW RW RW RW RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W RW RW Access DCC13CR0 3F # ACB03CR2 Blank fields are Reserved and should not be accessed. 7F RW # Access is bit specific. RDI1DSM BF RW CPU_SCR0 *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *D Page 29 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx CY8C28x52 Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ACE0_CR1 ACE0_CR2 ACE0_CR3 ACE_CMP_GI_EN ACE_ALT_CR0 ACE_ABF_CR0 ACE_AMX_IN ACE_CMP_CR0 ACE_CMP_CR1 ACE_AMD_CR0 TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN CMP_GO_EN1 AMD_CR1 ALT_CR0 ALT_CR1 CLK_CR2 AMUX_CFG1 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RW RW RW RW RW RW AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDIODSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM I2C0_ADDR RW RW RW RW RW RW RW RW RW RW RW GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR DEC3_CR0 DEC2_CR0 DEC_CR5 DEC1_CR0 DEC_CR4 DEC0_CR0 DEC_CR3 ACE01CR1 ACE01CR2 ASE11CR0 ACE_CLK_CR0 ACE_CLK_CR1 ACE_CLK_CR3 ACE_PWM_CR ACE_ADC0_CR ACE_ADC1_CR ACE_AMD_CR1 Access Name Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW IDAC_CR0 CPU_SCR1 CPU_SCR0 FLS_PR1 CPU_F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU DEC0_CR DEC1_CR DEC2_CR DEC3_CR MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 IDAC_CR1 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR IDAC_CR2 IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5 RW RW RW RW RW RW RW Access Name Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW # # RW RL RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Access Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *D Page 30 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C28xxx PSoC devices. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc. Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted. Specifications for devices running at greater than 12 MHz are valid for -40oC ≤ TA ≤ 70oC and TJ ≤ 82oC. Figure 7. Voltage versus CPU Frequency 5.25 lid ing Va rat on pe i O R eg 4.75 The following table lists the units of measure that are used in this section. Table 8. Units of Measure Symbol C dB fF Hz KB Kbit kHz kΩ MHz MΩ μA μF μH μs μV μVrms o Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square Document Number: 001-48111 Rev. *D Vdd Voltage 3.00 93 kHz 12 MHz CPU Frequency 24 MHz Symbol μW mA ms mV nA ns nV Ω pA pF pp ppm ps ksps ∑ V Unit of Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond kilo-samples per second sigma: one standard deviation volts Page 31 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx Absolute Maximum Ratings Table 9. Absolute Maximum Ratings Symbol Description TSTG Storage Temperature Min -55 Typ 25 Max +100 Units o C Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is +25oC ± 25oC. Extended duration storage temperatures above 65oC degrade reliability. TA Vdd VIO VIOZ IMIO IMAIO ESD LU Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Maximum Current into any Port Pin Configured as Analog Driver Electro Static Discharge Voltage Latch-up Current -40 -0.5 Vss0.5 Vss 0.5 -25 -50 2000 – – – – – – – – – +85 +6.0 Vdd + 0.5 Vdd + 0.5 +50 +50 – 200 o C V V V mA mA V mA Human Body Model ESD. Operating Temperature Table 10. Operating Temperature Symbol Description TA Ambient Temperature TJ Junction Temperature Min -40 -40 Typ – – Max +85 +100 Units oC oC Notes The temperature rise from ambient to junction is package specific. See Thermal Impedances on page 60. The user must limit the power consumption to comply with this requirement. Document Number: 001-48111 Rev. *D Page 32 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx DC Electrical Characteristics DC Chip Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 11. DC Chip Level Specifications Symbol Description Vdd Supply Voltage IDD Supply Current Min 3.00 – Typ – 8 Max 5.25 14 Units V mA Notes Conditions are Vdd = 5.0V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40 oC ≤ TA ≤ 55 oC. Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55 oC < TA ≤ 85 oC. Conditions are with properly loaded, 1 μW max, 32.768 kHz crystal. Vdd = 3.3V, -40 oC ≤ TA ≤ 55 oC. Conditions are with properly loaded, 1 μW max, 32.768 kHz crystal. Vdd = 3.3V, 55 oC < TA ≤ 85 oC. Trimmed for appropriate Vdd. IDD3 Supply Current – 5 9 mA ISB Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT.[13] Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT at high temperature.[13] Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal.[13] Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal at high temperature.[13] Reference Voltage (Bandgap) – 3 10 μA μA μA μA ISBH – 4 25 ISBXTL – 4 11 ISBXTLH – 5 26 VREF IXRES 1.280 1.00 1.300 – 1.320 1.058 V mA Note 13. Standby (sleep) current includes all functions (POR, LVD, WDT, Sleep Timer) needed for reliable system operation. This should be compared with devices that have similar functions enabled. Document Number: 001-48111 Rev. *D Page 33 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx DC General Purpose I/O Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 12. DC GPIO Specifications Symbol Description Pull Up Resistor RPU Pull Down Resistor RPD VOH High Output Level Min 4 4 Vdd 1.0 Typ 5.6 5.6 – Max 8 8 – Units kΩ kΩ V Notes VOL Low Output Level – – 0.75 V IOH IOL VIL VIH VH IIL CIN COUT High Level Source Current Low Level Sink Current Input Low Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output 10 25 – 2.1 – – – – – – – – 60 1 3.5 3.5 – – 0.8 – – 10 10 mA mA V V mV nA pF pF IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). VOH = Vdd-1.0V, see the limitations of the total current in the note for VOH. VOL = 0.75V, see the limitations of the total current in the note for VOL. Vdd = 3.0 to 5.25. Vdd = 3.0 to 5.25. Gross tested to 1 μA. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC. DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. The Operational Amplifiers covered by these specifications are components of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Table 13. 5V DC Operational Amplifier Specifications Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High TCVOSOA Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) IEBOA Input Capacitance (Port 0 Analog Pins) CINOA VCMOA Common Mode Voltage Range Common Mode Voltage Range (high power or high opamp bias) Symbol VOSOA Min – – – – – – 0.0 0.5 Typ 1.6 1.3 1.2 7.0 200 4.5 – – Max 10 10 10 35.0 – 9.5 Vdd Vdd 0.5 Units mV mV mV μV/oC pA pF V Notes Gross tested to 1 μA. Package and pin dependent. Temp = 25oC. The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Document Number: 001-48111 Rev. *D Page 34 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx Table 13. 5V DC Operational Amplifier Specifications (continued) Symbol Description CMRROA Common Mode Rejection Ratio Power = Low Power = Medium Power = High GOLOA Open Loop Gain Power = Low Power = Medium Power = High VOHIGHOA High Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High Min 60 60 60 – 60 60 80 Vdd 0.2 Vdd 0.2 Vdd 0.5 – – – – – – – – – V V V – dB Typ – Max – Units dB Notes Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. VOLOWOA Low Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High ISOA Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High PSRROA Supply Voltage Rejection Ratio Table 14. 3.3V DC Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High High Power is 5 Volts Only TCVOSOA Average Input Offset Voltage Drift IEBOA Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) CINOA Common Mode Voltage Range – – – 0.2 0.2 0.5 V V V μA μA μA μA μA μA dB – – – – – – 60 150 300 600 1200 2400 4600 – 200 400 800 1600 3200 6400 – Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd 1.25V) ≤ VIN ≤ Vdd. Min – – – – – 0.2 Typ 1.65 1.32 7.0 200 4.5 – Max 10 8 35.0 – 9.5 Units mV mV Notes VCMOA CMRROA Common Mode Rejection Ratio Power = Low Power = Medium Power = High GOLOA Open Loop Gain Power = Low Power = Medium Power = High – 50 50 50 – 60 60 80 μV/oC pA Gross tested to 1 μA. pF Package and pin dependent. Temp = 25oC. Vdd - 0.2 V The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. – dB Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 50 dB. – dB Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. Document Number: 001-48111 Rev. *D Page 35 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx Table 14. 3.3V DC Operational Amplifier Specifications (continued) Symbol Description VOHIGHOA High Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High is 5V only Min Vdd 0.2 Vdd 0.2 Vdd 0.2 – – – – – – – – – 50 Typ – – – Max – – – Units V V V Notes VOLOWOA Low Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High ISOA Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High PSRROA Supply Voltage Rejection Ratio – – – 150 300 600 1200 2400 4600 80 0.2 0.2 0.2 200 400 800 1600 3200 6400 – V V V μA μA μA μA μA μA dB Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd 1.25V) ≤ VIN ≤ Vdd. DC Type-E Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C £ TA £ 85°C, or 3.0V to 3.6V and -40°C £ TA £ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. The Operational Amplifiers covered by these specifications are components of the Limited Type E Analog PSoC blocks. Table 15. 5V DC Type-E Operational Amplifier Specifications Symbol Description VOSOA Input Offset Voltage (absolute value) Min – – – – – 0.0 – Typ 2.5 2.5 10 200 4.5 – 10 Max 15 20 – – 9.5 Vdd - 1 30 Units mV mV Notes For 0.2V < Vin < Vdd - 1.2V. For Vin = 0 to 0.2V and Vin > Vdd 1.2V. TCVOSOA Average Input Offset Voltage Drift IEBOA[14] Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) CINOA VCMOA ISOA Common Mode Voltage Range Amplifier Supply Current μV/oC pA Gross tested to 1 μA. pF Package and pin dependent. Temp = 25oC. V μA Table 16. 3.3V DC Type-E Operational Amplifier Specifications Symbol Description Input Offset Voltage (absolute value) VOSOA Min – – – – – 0 – Typ 2.5 2.5 10 200 4.5 – 10 Max 15 20 – – 9.5 Vdd - 1 30 Units Notes mV For 0.2V < Vin < Vdd - 1.2V. mV For Vin = 0 to 0.2V and Vin > Vdd 1.2V. μV/oC pA Gross tested to 1 μA. pF Package and pin dependent. Temp = 25oC. V μA TCVOSOA Average Input Offset Voltage Drift IEBOA[14] Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) CINOA VCMOA ISOA Common Mode Voltage Range Amplifier Supply Current Note 14. Atypical behavior: IEBOA of Port 0 Pin 0 is below 1 nA at 25°C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA. Document Number: 001-48111 Rev. *D Page 36 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx DC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 17. DC Low Power Comparator Specifications Symbol VREFLPC VOSLPC ISLPC Description Low power comparator (LPC) reference voltage range LPC voltage offset LPC supply current Min 0.2 – – Typ – 2.5 10 Max Vdd - 1 30 40 Units V mV μA Notes DC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 18. 5V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High High Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High VOLOWOB Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High ISOB Supply Current Including Bias Cell (No Load) Power = Low Power = High Supply Voltage Rejection Ratio Min – – 0.5 – – Typ 3 +6 – 1 1 Max 12 TBD Vdd - 1.0 – – Units mV μV/°C V Ω Ω Notes VOHIGHOB 0.5 x Vdd + 1.3 0.5 x Vdd + 1.3 – – – – V V – – – – 0.5 x Vdd - 1.3 0.5 x Vdd - 1.3 V V PSRROB – – 60 1.1 2.6 64 5.1 8.8 – mA mA dB Document Number: 001-48111 Rev. *D Page 37 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx Table 19. 3.3V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High VOHIGHOB High Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High VOLOWOB Low Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High ISOB Supply Current Including Bias Cell (No Load) Power = Low Power = High Supply Voltage Rejection Ratio Min – – 0.5 – – Typ 3 +6 1 1 Max 12 TBD Vdd - 1.0 – – Units mV μV/°C V Ω Ω Notes 0.5 x Vdd + 1.0 0.5 x Vdd + 1.0 – – – – V V – – – – 0.5 x Vdd - 1.0 0.5 x Vdd - 1.0 2.0 4.3 – V V PSRROB – 60 0.8 2.0 64 mA mA dB Document Number: 001-48111 Rev. *D Page 38 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx DC Switch Mode Pump Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 20. DC Switch Mode Pump (SMP) Specifications Symbol VPUMP 5V Description 5V Output Voltage Min 4.75 Typ 5.0 Max 5.25 Units V Notes Configuration of footnote.[15] Average, neglecting ripple. SMP trip voltage is set to 5.0V. Configuration of footnote.[15] Average, neglecting ripple. SMP trip voltage is set to 3.25V. Configuration of footnote.[15] SMP trip voltage is set to 3.25V. SMP trip voltage is set to 5.0V. To get better performance, refer to Cypress application note, AN2349. Configuration of footnote.[15] SMP trip voltage is set to 5.0V. Configuration of footnote.[15] SMP trip voltage is set to 3.25V. Configuration of footnote.[15] Configuration of footnote.[15] VO is the “Vdd Value for PUMP Trip” specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 30 on page 45. Configuration of footnote.[15] VO is the “Vdd Value for PUMP Trip” specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 30 on page 45. Configuration of footnote.[15] Load is 5mA. Configuration of footnote.[15] Load is 5 mA. SMP trip voltage is set to 3.25V. VPUMP 3V 3V Output Voltage 3.00 3.25 3.60 V IPUMP Available Output Current VBAT = 1.5V, VPUMP = 3.25V VBAT = 1.8V, VPUMP = 5.0V 8 5 – – – – mA mA VBAT5V VBAT3V VBATSTART ΔVPUMP_Line Input Voltage Range from Battery Input Voltage Range from Battery Minimum Input Voltage from Battery to Start Pump Line Regulation (over VBAT range) 1.8 1.5 1.1 – – – – 5 5.0 3.3 – – V V V %VO ΔVPUMP_Load Load Regulation – 5 – %VO ΔVPUMP_Ripple E3 FPUMP DCPUMP Output Voltage Ripple (depends on capacitor/load) Efficiency Switching Frequency Switching Duty Cycle – 35 – – 100 50 1.3 50 – – – – mVpp % MHz % Note 15. L1 = 2 uH inductor, C1 = 10 uF capacitor, D1 = Schottky diode. See Figure 8. Document Number: 001-48111 Rev. *D Page 39 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx Figure 8. Basic Switch Mode Pump Circuit D1 Vdd V PUMP L1 V BAT C1 SMP + Battery PSoC TM Vss DC Analog Reference Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high. Table 21. 5V DC Analog Reference Specifications for High Power Symbol VBG5 – – – – – – – – – – – – – – – – – – Description Bandgap Voltage Reference 5V AGND = Vdd/2[16] AGND = 2 x BandGap[16] AGND = P2[4] (P2[4] = Vdd/2)[16] AGND = BandGap[16] AGND = 1.6 x BandGap[16] AGND Block to Block Variation (AGND = Vdd/2)[16] RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) RefHi = 2 x BandGap RefHi = 3.2 x BandGap RefLo = Vdd/2 – BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) RefLo = P2[4] – BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) Min 1.28 Vdd/2 - 0.02 2.52 P2[4] - 0.013 1.27 2.03 -0.034 Vdd/2 + 1.21 3.75 P2[6] + 2.478 P2[4] + 1.218 P2[4] + P2[6] 0.058 2.50 4.02 Vdd/2 - 1.369 1.20 2.489 - P2[6] P2[4] - 1.368 P2[4] - P2[6] 0.042 Typ 1.30 Vdd/2 2.60 P2[4] 1.3 2.08 0.000 Vdd/2 + 1.3 3.9 P2[6] + 2.6 P2[4] + 1.3 P2[4] + P2[6] 2.60 4.16 Vdd/2 - 1.30 1.30 2.6 - P2[6] P2[4] - 1.30 P2[4] - P2[6] Max 1.32 Vdd/2 + 0.02 2.72 P2[4] + 0.013 1.34 2.13 0.034 Vdd/2 + 1.382 4.05 P2[6] + 2.722 P2[4] + 1.382 P2[4] + P2[6] + 0.058 2.70 4.29 Vdd/2 - 1.231 1.40 2.711 - P2[6] P2[4] - 1.232 P2[4] - P2[6] + 0.042 Units V V V V V V V V V V V V V V V V V V V Note 16. AGND tolerance includes the offsets of the local buffer in the PSoC block. Document Number: 001-48111 Rev. *D Page 40 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx Table 22. 5V DC Analog Reference Specifications for Medium Power Symbol VBG5 – – – – – – – – – – – – – – – – – – Description Bandgap Voltage Reference 5V AGND = Vdd/2[16] AGND = 2 x BandGap[16] AGND = P2[4] (P2[4] = Vdd/2)[16] AGND = BandGap[16] AGND = 1.6 x BandGap[16] AGND Block to Block Variation (AGND = Vdd/2)[16] RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) RefHi = 2 x BandGap RefHi = 3.2 x BandGap RefLo = Vdd/2 – BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) RefLo = P2[4] – BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) Min 1.28 Vdd/2 - 0.02 2.52 P2[4] - 0.013 1.27 2.03 -0.034 Vdd/2 + 1.21 3.75 P2[6] + 2.478 P2[4] + 1.218 P2[4] + P2[6] 0.058 2.50 4.02 Vdd/2 - 1.369 1.20 2.489 - P2[6] P2[4] - 1.368 P2[4] - P2[6] 0.042 Typ 1.30 Vdd/2 2.60 P2[4] 1.3 2.08 0.000 Vdd/2 + 1.3 3.9 P2[6] + 2.6 P2[4] + 1.3 P2[4] + P2[6] 2.60 4.16 Vdd/2 - 1.30 1.30 2.6 - P2[6] P2[4] - 1.30 P2[4] - P2[6] Max 1.32 Vdd/2 + 0.02 2.72 P2[4] + 0.013 1.34 2.13 0.034 Vdd/2 + 1.382 4.05 P2[6] + 2.722 P2[4] + 1.382 P2[4] + P2[6] + 0.058 2.70 4.29 Vdd/2 - 1.231 1.40 2.711 - P2[6] P2[4] - 1.232 P2[4] - P2[6] + 0.042 Units V V V V V V V V V V V V V V V V V V V Table 23. 5V DC Analog Reference Specifications for Low Power Symbol VBG5 – – – – – – – – – – – – – – – – – – Description Bandgap Voltage Reference 5V AGND = Vdd/2[16] AGND = 2 x BandGap[16] AGND = P2[4] (P2[4] = Vdd/2)[16] AGND = BandGap[16] AGND = 1.6 x BandGap[16] AGND Block to Block Variation (AGND = Vdd/2)[16] RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) RefHi = 2 x BandGap RefHi = 3.2 x BandGap RefLo = Vdd/2 – BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) RefLo = P2[4] – BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) Min 1.28 Vdd/2 - 0.02 2.52 P2[4] - 0.013 1.27 2.03 -0.034 Vdd/2 + 1.21 3.75 P2[6] + 2.478 P2[4] + 1.218 P2[4] + P2[6] 0.058 2.50 4.02 Vdd/2 - 1.369 1.20 2.489 - P2[6] P2[4] - 1.368 P2[4] - P2[6] 0.042 Typ 1.30 Vdd/2 2.60 P2[4] 1.3 2.08 0.000 Vdd/2 + 1.3 3.9 P2[6] + 2.6 P2[4] + 1.3 P2[4] + P2[6] 2.60 4.16 Vdd/2 - 1.30 1.30 2.6 - P2[6] P2[4] - 1.30 P2[4] - P2[6] Max 1.32 Vdd/2 + 0.02 2.72 P2[4] + 0.013 1.34 2.13 0.034 Vdd/2 + 1.382 4.05 P2[6] + 2.722 P2[4] + 1.382 P2[4] + P2[6] + 0.058 2.70 4.29 Vdd/2 - 1.231 1.40 2.711 - P2[6] P2[4] - 1.232 P2[4] - P2[6] + 0.042 Units V V V V V V V V V V V V V V V V V V V Document Number: 001-48111 Rev. *D Page 41 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx Table 24. 3.3V DC Analog Reference Specifications for High Power Symbol VBG33 – – – – – – – – – – – – – – – – – – Description Bandgap Voltage Reference 3.3V AGND = Vdd/2[16] AGND = 2 x BandGap[16] AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGap[16] AGND = 1.6 x BandGap[16] AGND Block to Block Variation (AGND = Vdd/2)[16] RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) Min 1.28 Vdd/2 - 0.02 Not Allowed P2[4] - 0.009 1.27 2.03 -0.034 Not Allowed Not Allowed Not Allowed Not Allowed P2[4] + P2[6] 0.042 RefHi = 2 x BandGap 2.50 RefHi = 3.2 x BandGap Not Allowed RefLo = Vdd/2 - BandGap Not Allowed RefLo = BandGap Not Allowed RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) Not Allowed RefLo = P2[4] – BandGap (P2[4] = Vdd/2) Not Allowed RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] 0.036 Typ 1.30 Vdd/2 P2[4] 1.30 2.08 0.000 Max 1.32 Vdd/2 + 0.02 P2[4] + 0.009 1.34 2.13 0.034 Units V V V V V mV P2[4] + P2[6] 2.60 P2[4] + P2[6] + 0.042 2.70 V V P2[4] - P2[6] P2[4] - P2[6] + 0.036 V Table 25. 3.3V DC Analog Reference Specifications for Medium Power Symbol VBG33 – – – – – – – – – – – – – – – – – – Description Bandgap Voltage Reference 3.3V AGND = Vdd/2[16] AGND = 2 x BandGap[16] AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGap[16] AGND = 1.6 x BandGap[16] AGND Block to Block Variation (AGND = Vdd/2)[16] RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) Min 1.28 Vdd/2 - 0.02 Not Allowed P2[4] - 0.009 1.27 2.03 -0.034 Not Allowed Not Allowed Not Allowed Not Allowed P2[4] + P2[6] 0.042 RefHi = 2 x BandGap 2.50 RefHi = 3.2 x BandGap Not Allowed RefLo = Vdd/2 - BandGap Not Allowed RefLo = BandGap Not Allowed RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) Not Allowed RefLo = P2[4] – BandGap (P2[4] = Vdd/2) Not Allowed RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] 0.036 Typ 1.30 Vdd/2 P2[4] 1.30 2.08 0.000 Max 1.32 Vdd/2 + 0.02 P2[4] + 0.009 1.34 2.13 0.034 Units V V V V V mV P2[4] + P2[6] 2.60 P2[4] + P2[6] + 0.042 2.70 V V P2[4] - P2[6] P2[4] - P2[6] + 0.036 V Document Number: 001-48111 Rev. *D Page 42 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx Table 26. 3.3V DC Analog Reference Specifications for Low Power Symbol VBG33 – – – – – – – – – – – – – – – – – – Description Bandgap Voltage Reference 3.3V AGND = Vdd/2[16] AGND = 2 x BandGap[16] AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGap[16] AGND = 1.6 x BandGap[16] AGND Block to Block Variation (AGND = Vdd/2)[16] RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) Min 1.30 Vdd/2 P2[4] 1.30 2.08 0.000 Typ Max 1.32 Vdd/2 + 0.02 P2[4] + 0.009 1.34 2.13 0.034 Units V V V V V mV 1.28 Vdd/2 - 0.02 Not Allowed P2[4] - 0.009 1.27 2.03 -0.034 Not Allowed Not Allowed Not Allowed Not Allowed P2[4] + P2[6] 0.042 RefHi = 2 x BandGap 2.50 RefHi = 3.2 x BandGap Not Allowed RefLo = Vdd/2 - BandGap Not Allowed RefLo = BandGap Not Allowed RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) Not Allowed RefLo = P2[4] – BandGap (P2[4] = Vdd/2) Not Allowed RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] - P2[6] 0.036 P2[4] + P2[6] 2.60 P2[4] + P2[6] + 0.042 2.70 V V P2[4] - P2[6] P2[4] - P2[6] + 0.036 V Note See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V. DC Analog PSoC Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 27. DC Analog PSoC Block Specifications Symbol RCT CSC Description Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switch Cap) Min – – Typ 12.24 80 Max – – Units kΩ fF Notes DC Analog Mux Bus Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 28. DC Analog Mux Bus Specifications Symbol RSW RVSS Description Switch Resistance to Common Analog Bus Resistance of Initialization Switch to VSS Min – – Typ – – Max 400 800 Units Ω Ω Notes Vdd ≥ 3.0V Document Number: 001-48111 Rev. *D Page 43 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx DC SAR10 ADC Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 29. DC SAR10 ADC Specifications Symbol INLSAR10 DNLSAR10 ISAR10 IVREFSAR10 Description Integral nonlinearity Differential nonlinearity Active current consumption Input current into P2[5] when configured as the SAR10 ADC's VREF input. VVREFSAR10 Input reference voltage at P2[5] when configured as the SAR10 ADC's external voltage reference. Min -2.5 -1.5 0.08 3.0 Typ TBD Max Units Notes 2.5 LSB 10-bit resolution 1.5 LSB 10-bit resolution 0.497 mA 0.5 mA The internal voltage reference buffer is disabled in this configuration. 4.95 V When VREF is buffered inside the SAR10 ADC, the voltage level at P2[5] (when configured as the external reference voltage) must always be at least 300 mV less than the chip supply voltage level on the Vdd pin. (VVREFSAR10 < (Vdd - 300 mV) ). 9 mV VOSSAR10 Offset voltage 5 TBD Document Number: 001-48111 Rev. *D Page 44 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Programmable System-on-Chip Technical Reference Manual for CY8C28xxx PSoC devices, for more information on the VLT_CR register. Table 30. DC POR and LVD Specifications Symbol VPPOR0R VPPOR1R VPPOR2R VPPOR0 VPPOR1 VPPOR2 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 Description Vdd Value for PPOR Trip (positive ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for PPOR Trip (negative ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b PPOR Hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Vdd Value for PUMP Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min Typ 2.91 4.39 4.55 2.82 4.39 4.55 92 0 0 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 3.02 3.10 3.25 4.19 4.64 4.73 4.82 5.00 Max Units V V V V V V mV mV mV V V V V V V V V V V V V V V V V Notes Vdd must be greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from Watchdog. – – – – – – – 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.96 3.03 3.18 4.11 4.55 4.63 4.72 4.90 – – – 2.98[17] 3.08 3.20 4.08 4.57 4.74[18] 4.82 4.91 3.08 3.16 3.32 4.28 4.74 4.82 4.91 5.10 Notes 17. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. 18. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply. Document Number: 001-48111 Rev. *D Page 45 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 31. DC Programming Specifications Symbol IDDP VILP Description Supply Current During Programming or Verify Input Low Voltage During Programming or Verify VIHP Input High Voltage During Programming or Verify IILP Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify IIHP Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify VOLV Output Low Voltage During Programming or Verify VOHV Output High Voltage During Programming or Verify FlashENPB Flash Endurance (per block) FlashENT Flash Endurance (total)[19] FlashDR Flash Data Retention Min – – 2.2 – – – Vdd - 1.0 50,000 1,800,000 10 Typ 5 – – – – – – – – – Max 25 0.8 – 0.2 1.5 Vss + 0.75 Vdd – – – Units mA V V mA mA V V – Erase/write cycles per block. – Erase/write cycles. Years Driving internal pull-down resistor. Driving internal pull-down resistor. Notes Note 19. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. Document Number: 001-48111 Rev. *D Page 46 of 65 [+] [+] Feedback PRELIMINARY CY8C28xxx AC Electrical Characteristics AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 32. AC Chip-Level Specifications Symbol FIMO FIMO6 FCPU1 FCPU2 FBLK5 FBLK33 F32K1 F32K2 F32K_U Description Internal Main Oscillator Frequency Internal Main Oscillator Frequency for 6 MHz CPU Frequency (5V Nominal) CPU Frequency (3.3V Nominal) Digital PSoC Block Frequency Digital PSoC Block Frequency Internal Low Speed Oscillator Frequency External Crystal Oscillator Internal Low Speed Oscillator Untrimmed Frequency Min 23.4 5.5 Typ 24 6 Max 24.6[20] 6.5[20] Units MHz MHz Notes Trimmed. Utilizing factory trim values. Trimmed for 5V or 3.3V operation using factory trim values. SLIMO Mode = 1. Trimmed. Utilizing factory trim values. Trimmed. Utilizing factory trim values. 4.75V< Vdd