CY8C28452

CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 PSoC® Programmable System-on-Chip™ Features ■ ■ ❐ Varied resource options within one PSoC® device group Powerful Harvard-architecture processor ❐ M8C processor speeds up to 24 MHz ❐ 8 × 8 Multiply, 32-bit accumulate ❐ Low power at high speed ❐ Operating voltage: 3.0 V to 5.25 V ❐ Operating voltages down to 1.5 V Using on-chip switched mode pump (SMP) ❐ Industrial temperature range: –40 °C to +85 °C Advanced reconfigurable peripherals (PSoC Blocks) ❐ Up to 12 rail-to-rail analog PSoC blocks provide: • Up to 14-bit ADCs • Up to 9-bit DACs • Programmable gain amplifiers • Programmable filters and comparators • Multiple ADC configurations • Dedicated SAR ADC, up to 142 ksps with sample and hold • Up to 4 synchronized or independent delta-sigma ADCs for advanced applications ❐ Up to 4 limited type E analog blocks provide: • Dual channel capacitive sensing capability • Comparators with programmable DAC reference • Up to 10-bit single-slope ADCs ❐ Up to 12 digital PSoC blocks provide: • 8 to 32-bit timers, counters, and PWMs • Shift register, CRC, and PRS modules • Up to 3 full-duplex UARTs • Up to 6 half-duplex UARTs • Multiple variable data length SPI™ masters or slaves • Connectable to all GPIOs ❐ Complex peripherals by combining blocks Precision, programmable clocking ❐ Internal ±2.5% 24/48 MHz main oscillator ❐ Optional 32.768 kHz crystal for precise on-chip clocks ❐ Optional external oscillator, up to 24 MHz ❐ Internal low speed, low power oscillator for watchdog and sleep functionality Flexible on-chip memory ❐ 16 KB flash program storage 50,000 erase/write cycles ❐ 1-KB SRAM data storage ❐ In-system serial programming (ISSP™) ❐ Partial flash updates ❐ Flexible protection modes ❐ EEPROM emulation in flash Programmable Pin configurations ❐ 25 mA sink, 10 mA drive on all GPIOs Pull-up, pull-down, high Z, strong, or open-drain drive modes on all GPIOs ❐ Analog input on all GPIOs ❐ 30 mA analog outputs on GPIOs ❐ Configurable interrupt on all GPIOs ■ ■ Additional system resources 2 ❐ Up to two hardware I C resources • Each resource implements slave, master, or multi-master modes • Operation between 0 and 400 kHz ❐ Watchdog and Sleep timers ❐ User-configurable low voltage detection ❐ Flexible internal voltage references ❐ Integrated supervisory circuit ❐ On-chip precision voltage reference Complete development tools ❐ Free development software (PSoC Designer™) ❐ Full featured in-circuit emulator, and programmer ❐ Full speed emulation ❐ Flexible and functional breakpoint structure ❐ 128 KB trace memory ■ Logic Block Diagram Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Analog Drivers PSoC CORE System Bus Global Digital Interconnect SRAM 1K Interrupt Controller Global Analog Interconnect Flash 16K Sleep and Watchdog SROM CPU Core (M8C) ■ Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) DIGITAL SYSTEM Digital Block Array ANALOG SYSTEM Analog Block Array Analog Ref. ■ Analog Input Muxing ■ Digital Clocks 2 MACs 4 Type 2 2 I2C Decimators Blocks POR and LVD System Resets Internal Voltage Ref. Switch Mode Pump SYSTEM RESOURCES Cypress Semiconductor Corporation Document Number: 001-48111 Rev. *I • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 8, 2011 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Contents PSoC Functional Overview .............................................. 3 The PSoC Core ........................................................... 3 The Digital System ...................................................... 3 The Analog System ..................................................... 4 System Resources ...................................................... 7 PSoC Device Characteristics ...................................... 7 Getting Started .................................................................. 8 Application Notes ........................................................ 8 Development Kits ........................................................ 8 Training ....................................................................... 8 CYPros Consultants .................................................... 8 Solutions Library .......................................................... 8 Technical Support ....................................................... 8 Development Tools .......................................................... 9 PSoC Designer Software Subsystems ........................ 9 Designing with PSoC Designer ..................................... 10 Select User Modules ................................................. 10 Configure User Modules ............................................ 10 Organize and Connect .............................................. 10 Generate, Verify, and Debug ..................................... 10 Pinouts ............................................................................ 11 20-Pin Part Pinout .................................................... 11 28-Pin Part Pinout ..................................................... 12 44-Pin Part Pinout .................................................... 13 48-Pin Part Pinout ..................................................... 14 56-Pin Part Pinout ..................................................... 15 Register Reference ......................................................... 17 Register Conventions ................................................ 17 Register Mapping Tables .......................................... 17 Electrical Specifications ................................................ 32 Absolute Maximum Ratings ...................................... 33 Operating Temperature ............................................ 33 DC Electrical Characteristics ..................................... 34 AC Electrical Characteristics ..................................... 52 Packaging Information ................................................... 62 Packaging Dimensions .............................................. 62 Thermal Impedances ................................................ 66 Capacitance on Crystal Pins .................................... 66 Solder Reflow Peak Temperature ............................. 66 Development Tool Selection ......................................... 67 Software .................................................................... 67 Development Kits ...................................................... 67 Evaluation Tools ........................................................ 67 Device Programmers ................................................. 68 Accessories (Emulation and Programming) .............. 68 Ordering Information ...................................................... 69 Ordering Code Definitions ......................................... 70 Acronyms ........................................................................ 71 Acronyms Used ......................................................... 71 Reference Documents .................................................... 71 Document Conventions ................................................. 72 Units of Measure ....................................................... 72 Numeric Conventions ................................................ 72 Glossary .......................................................................... 72 Document History Page ................................................. 77 Sales, Solutions, and Legal Information ...................... 78 Worldwide Sales and Design Support ....................... 78 Products .................................................................... 78 PSoC Solutions ......................................................... 78 Document Number: 001-48111 Rev. *I Page 2 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 PSoC Functional Overview The PSoC family consists of many devices with On-Chip Controllers. These devices are designed to replace multiple traditional MCU based system components with one low cost single chip programmable component. A PSoC device includes configurable analog blocks, digital blocks, and interconnections. This architecture enables the user to create customized peripheral configurations to match the requirements of each individual application. In addition, a fast CPU, Flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts and packages. The CY8C28xxx group of PSoC devices described in this datasheet have multiple resource configuration options available. Therefore, not every resource mentioned in this datasheet is available for each CY8C28xxx subgroup. The CY8C28x45 subgroup has a full feature set of all resources described. There are six more segmented subgroups that allow designers to use a device with only the resources and functionality necessary for a specific application. See Table 2 on page 8 to determine the resources available for each CY8C28xxx subgroup. The same information is also presented in more detail in the Ordering Information section. The architecture for this specific PSoC device family, as shown in the Logic Block Diagram on page 1, consists of four main areas: PSoC Core, Digital System, Analog System, and System Resources. The configurable global bus system allows all the device resources to be combined into a complete custom system. PSoC CY8C28xxx family devices have up to six I/O ports that connect to the global digital and analog interconnects, providing access to up to 12 digital blocks and up to 16 analog blocks. alone or combined with other blocks to create 8, 16, 24, and 32-bit peripherals, which are called user modules. The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. Figure 1. Digital System Block Diagram[1] Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Digital Clocks From Core To System Bus To Analog System DIGITAL SYSTEM Digital PSoC Block Array Row Input Configuration Row 0 DBC00 DBC01 DCC02 4 DCC03 4 Row Output Configuration 8 8 Row Input Configuration 8 Row 1 DBC10 DBC11 DCC12 4 DCC13 4 8 Row Output Configuration Row Input Configuration Row 2 DBC20 DBC21 DCC22 4 DCC23 4 Row Output Configuration The PSoC Core The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable general Purpose I/O (GPIO). The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microcontroller. Memory encompasses 16K bytes of Flash for program storage, 1K bytes of SRAM for data storage. The PSoC device incorporates flexible internal clock generators, including a 24 MHz internal main oscillator (IMO) accurate to 2.5% over temperature and voltage. A low power 32 kHz internal low speed oscillator (ILO) is provided for the sleep timer and watch dog timer (WDT). The 32.768 kHz external crystal oscillator (ECO) is available for use as a real time clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. PSoC GPIOs provide connections to the CPU, and digital and analog resources. Each pin’s drive mode may be selected from 8 options, which allows great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] Digital peripheral configurations include: ■ ■ ■ ■ ■ ■ ■ PWMs (8 to 16 bit, One-shot and Multi-shot capability) PWMs with Dead band/Kill (8 to 16 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) Full-duplex 8-bit UARTs (up to 3) with selectable parity Half-duplex 8-bit UARTs (up to 6) with selectable parity Variable length SPI slave and master ❐ Up to 6 total slaves and masters (8-bit) ❐ Supports 8 to 16 bit operation I2C slave, master, or multi-master (up to 2 available as System Resources) IrDA (up to 3) Pseudo Random Sequence Generators (8 to 32 bit) Cyclical Redundancy Checker/Generator (16 bit) Shift Register (2 to 32 bit) ■ ■ ■ ■ ■ The Digital System The Digital System is composed of up to 12 configurable digital PSoC blocks. Each block is an 8-bit resource that can be used Note 1. CY8C28x52 devices do not have digital block row 2. They have two digital rows with eight total digital blocks. Document Number: 001-48111 Rev. *I Page 3 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 The Analog System The Analog System is composed of up to 16 configurable analog blocks, each containing an opamp circuit that allows the creation of complex analog signal flows. Some devices in this PSoC family have an analog multiplex bus that can connect to every GPIO pin. This bus can also connect to the analog system for analysis with comparators and analog-to-digital converters. It can be split into two sections for simultaneous dual-channel processing. Some of the more common PSoC analog functions (most available as user modules) are: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Figure 2. Analog System Block Diagram for CY8C28x45 and CY8C28x52 Devices All GPIO P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6] P0[4] P0[2] P0[0] P2[6] P2[3] P2[1] Analog Mux Bus Analog-to-digital converters (6 to 14-bit resolution, up to 4, selectable as Incremental or Delta Sigma) Dedicated 10-bit SAR ADC with sample rates up to 142 ksps Synchronized, simultaneous Delta Sigma ADCs (up to 4) Filters (2 to 8 pole band-pass, low pass, and notch) Amplifiers (up to 4, with selectable gain to 48x) Instrumentation amplifiers (up to 2, with selectable gain to 93x) Comparators (up to 6, with 16 selectable thresholds) DACs (up to 4, with 6 to 9-bit resolution) Multiplying DACs (up to 4, with 6 to 9-bit resolution) High current output drivers (up to 4 with 30 mA drive) 1.3 V reference (as a System Resource) DTMF Dialer Modulators Correlators Peak detectors Many other topologies possible P2[4] P2[2] P2[0] Array Input Configuration ACI0[1:0] ACI1[1:0] ACI2[1:0] ACI3[1:0] ACI4[1:0] ACI5[1:0] Block Array ACC00 ASC10 ASD20 ACC01 ASD11 ASC21 ACC02 ASC12 ASD22 ACC03 ACE00 ACE01 ASD13 ASE10 ASE11 ASC23 Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 001-48111 Rev. *I Page 4 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Figure 3. Analog System Block Diagram for CY8C28x43 Devices All GPIO P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6] P0[7] Figure 4. Analog System Block Diagram for CY8C28x33 Devices All GPIO P0[4] P0[5] P0[2] P0[0] P2[6] P0[3] P0[6] P0[4] P0[1] P2[3] Analog Mux Bus P0[2] P0[0] AGNDIn RefIn P2[6] P2[3] P2[4] P2[2] P2[0] P2[1] P2[1] Analog Mux Bus P2[4] Array Input Configuration Array Input Configuration ACI0[1:0] ACI1[1:0] ACI4[1:0] ACI5[1:0] ACI0[1:0] ACI1[1:0] ACI2[1:0] ACI3[1:0] Block Array Block Array ACC00 ASC10 ASD20 ACC01 ASD11 ASC21 ACC02 ASC12 ASD22 ACC03 ASD13 ASC23 ACC00 ASC10 ASD20 ACC01 ACE00 ACE01 ASD11 ASE10 ASE11 ASC21 Analog Reference Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap M8C Interface (Address Bus, Data Bus, Etc.) M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 001-48111 Rev. *I Page 5 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Figure 5. Analog System Block Diagram for CY8C28x23 Devices P0[7] P0[5] Figure 6. Analog System Block Diagram for CY8C28x13 Devices All GPIO P0[7] P0[3] P0[4] P0[1] P2[3] P2[1] AGNDIn RefIn P0[2] P0[0] P2[6] Analog Mux Bus P0[6] P0[6] P0[4] P0[2] P0[0] P0[5] P0[3] P0[1] P2[4] ACI0[1:0] Array Input Configuration ACI1[1:0] Array Input Configuration ACI0[1:0] ACI1[1:0] Block Array ACE00 ACE01 Block Array ACC00 ASC10 ASD20 ACC01 ASD11 ASC21 ASE10 ASE11 Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap Analog Reference M8C Interface (Address Bus, Data Bus, Etc.) Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 001-48111 Rev. *I Page 6 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 System Resources System Resources, some of which are listed in the previous sections, provide additional capability useful to complete systems. Additional resources include a multiplier, multiple decimators, switch mode pump, low voltage detection, and power on reset. Statements describing the merits of each system resource follow: ■ ■ Up to four decimators provide custom hardware filters for digital signal processing applications such as Delta-Sigma ADCs and CapSense capacitive sensor measurement. Up to two I2C resources provide 0 to 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. I2C resources have hardware address detection capability. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3 V reference provides an absolute reference for the analog system, including ADCs and DACs. An integrated switch mode pump (SMP) generates normal operating voltages from a single 1.5 V battery cell, providing a low cost boost converter. ■ Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. Multiply accumulate (MAC) provides fast 8-bit multiplier with 32-bit accumulate, to assist in general math and digital filters. ■ ■ ■ ■ PSoC Device Characteristics Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks, and 12, 6, or 4 analog blocks. Table 1 on page 7 lists the resources available for specific PSoC device groups. The PSoC device covered by this datasheet is highlighted in this table. Table 1. PSoC Device Characteristics PSoC Part Number CY8C29x66 CY8C28xxx CY8C27x43 CY8C24x94 CY8C24x23A CY8C23x33 CY8C22x45 CY8C21x45 CY8C21x34 CY8C21x23 CY8C20x34 CY8C20xx6 Digital I/O up to 64 up to 44 up to 44 up to 56 up to 24 up to 26 up to 38 up to 24 up to 28 up to 16 up to 28 up to 36 Digital Rows 4 up to 3 2 1 1 1 2 1 1 1 0 0 Digital Blocks 16 up to 12 8 4 4 4 8 4 4 4 0 0 Analog Inputs up to 12 up to 44 up to 12 up to 48 up to 12 up to 12 up to 38 up to 24 up to 28 up to 8 up to 28 up to 36 Analog Outputs 4 up to 4 4 2 2 2 0 0 0 0 0 0 Analog Columns 4 up to 6 4 2 2 2 4 4 2 2 0 0 Analog Blocks 12 up to 12 + 4[2] 12 6 6 4 6[2] 6[2] 4[2] 4 3 [2] SRAM Size 2K 1K 256 1K 256 256 1K 512 512 256 512 up to 2K Flash Size 32 K 16 K 16 K 16 K 4K 8K 16 K 8K 8K 4K 8K up to 32 K 3[2,3] [2,3] Notes 2. Limited analog functionality. 3. Two analog blocks and one CapSense®. Document Number: 001-48111 Rev. *I Page 7 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 The devices covered by this datasheet all have the same architecture, specifications, and ratings. However, the amount of some hardware resources varies from device to device within the group. The following table lists resources available for the specific device subgroups covered by this datasheet. Table 2. CY8C28xxx Device Characteristics PSoC Part Number CY8C28x03 CY8C28x13 CY8C28x23 CY8C28x33 CY8C28x43 CY8C28x45 CY8C28x52 CapSense N Y N Y N Y Y Digital Blocks 12 12 12 12 12 12 8 Regular Analog Blocks 0 0 6 6 12 12 12 Limited Analog Blocks 0 4 0 4 0 4 4 HW I2C 2 1 2 1 2 2 1 Decimators 0 2 2 4 4 4 4 Digital I/O up to 24 up to 40 up to 44 up to 40 up to 44 up to 44 up to 24 Analog Inputs up to 8 up to 40 up to 10 up to 40 up to 44 up to 44 up to 24 Analog Outputs 0 0 2 2 4 4 4 Getting Started For in depth information, along with detailed programming details, see the PSoC® Technical Reference Manual. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device datasheets on the web. CYPros Consultants Certified PSoC consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC consultant go to the CYPros Consultants web site. Application Notes Cypress application notes are an excellent introduction to the wide variety of possible PSoC designs. Solutions Library Visit our growing library of solution focused designs. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Development Kits PSoC Development Kits are available online from and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Technical Support Technical support – including a searchable Knowledge Base articles and technical forums – is also available online. If you cannot find an answer to your question, call our Technical Support hotline at 1-800-541-4736. Training Free PSoC technical training (on demand, webinars, and workshops), which is available online via www.cypress.com, covers a wide variety of topics and skill levels to assist you in your designs. Notes 4. Has 12 regular analog blocks and four limited Type-E analog blocks. 5. Limited analog functionality. 6. Two analog blocks and one CapSense. Document Number: 001-48111 Rev. *I Page 8 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Development Tools PSoC Designer™ is the revolutionary integrated design environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes: ■ ■ ■ ■ ■ ■ ■ Code Generation Tools The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. You can develop your design in C, assembly, or a combination of the two. Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also lets you to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer. In-Circuit Emulator A low-cost, high-functionality in-circuit emulator (ICE) is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24 MHz) operation. Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration Extensive user module catalog Integrated source-code editor (C and assembly) Free C compiler with no size restrictions or time limits Built-in debugger In-circuit emulation Built-in support for communication interfaces: 2 ❐ Hardware and software I C slaves and masters ❐ Full-speed USB 2.0 ❐ Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7. PSoC Designer Software Subsystems Design Entry In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use the PSoC blocks, which are called user modules. Examples of user modules are analog-to-digital converters (ADCs), digital-to-analog converters (DACs), amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this lets you to use more than 100 percent of PSoC's resources for an application. Document Number: 001-48111 Rev. *I Page 9 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed-function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and lowering inventory costs. These configurable resources, called PSoC blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is: 1. Select user modules. 2. Configure user modules. 3. Organize and connect. 4. Generate, verify, and debug. Organize and Connect Build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. Perform the selection, configuration, and routing so that you have complete control over all on-chip resources. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, perform the “Generate Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides APIs with high-level functions to control and respond to hardware events at run time, and interrupt service routines that you can adapt as needed. A complete code development environment lets you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside PSoC Designer's Debugger (accessed by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full-speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer. It lets you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals. Select User Modules PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called “user modules.” User modules make selecting and implementing peripheral devices, both analog and digital, simple. Configure User Modules Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a PWM User Module configures one or more digital PSoC blocks, one for each eight bits of resolution. Using these parameters, you can establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All of the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the internal operation of the user module and provide performance specifications. Each datasheet describes the use of each user module parameter, and other information that you may need to successfully implement your design. Document Number: 001-48111 Rev. *I Page 10 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Pinouts This section describes, lists, and illustrates the CY8C28xxx PSoC device pins and pinout configurations. The CY8C28xxx PSoC devices are available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O. However, VSS, VDD, SMP, and XRES are not capable of Digital I/O. 20-Pin Part Pinout Table 3. 20-Pin Part Pinout (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 I/O I/O I/O I/O I/O I/O I/O I/O Input I, M, S I/O, M, S I/O, M, S I, M, S Power I/O I/O I/O I/O Power M M M M Type Digital I/O I/O I/O I/O Analog I, M, S I/O, M, S I/O, M, S I, M, S Output M M M M Pin Name P0[7] P0[5] P0[3] P0[1] SMP P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] P1[6] Crystal Input (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK[7]. Ground connection. Crystal Output (XTALout), I2C0 Serial Data (SDA), ISSP-SDATA[7]. I2C1 Serial Data (SDA).[10] Optional External Clock Input (EXTCLK). I2C1 Serial Clock (SCL).[10] Description Analog column mux and SAR ADC input.[8] CY8C28243 20-Pin PSoC Device S, AI, M, P0[7] S, AIO, M, P0[5] Analog column mux and SAR ADC input. S, AIO, M, P0[3] Analog column output.[8, 9] S, AI, M, P0[1] Analog column mux and SAR ADC input. SMP [8, 9] Analog column output. I2C0 SCL, M, P1[7] Analog column mux and SAR ADC I2C0 SDA, M, P1[5] input.[8] M, P1[3] Switch Mode Pump (SMP) connection to I2C0 SCL, XTALin, M, P1[1] external components. Vss 1 2 3 4 5 6 7 8 9 10 SSOP 20 19 18 17 16 15 14 13 12 11 Vdd P0[6], M, AI, S P0[4], M, AIO, S P0[2], M, AIO, S P0[0], M, AI, S XRES P1[6], M, I2C1 SCL P1[4], M, EXTCLK P1[2], M, I2C1 SDA P1[0], M, XTALout, I2C0 SDA I2C0 Serial Clock (SCL). I2C0 Serial Data (SDA). XRES Active high external reset with internal pull-down. P0[0] P0[2] P0[4] P0[6] VDD Analog column mux and SAR ADC input.[8] Analog column mux and SAR ADC input. Analog column output.[8, 11] Analog column mux and SAR ADC input. Analog column output.[8, 11] Analog column mux and SAR ADC input.[8] Supply voltage. LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input. Notes 7. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Technical Reference Manual for CY8C28xxx PSoC devices for details. 8. CY8C28x52 and CY8C28x23 devices do not have a SAR ADC. Therefore, this pin does not function as a SAR ADC input for these devices. 9. CY8C28x13 and CY8C28x03 devices do not have any analog output buffers. Therefore, this pin does not function as an analog column output for these devices. 10. CY8C28x52, CY8C28x13, and CY8C28x33 devices only have one I2C block. Therefore, this GPIO does not function as an I2C pin for these devices. 11. CY8C28x33, CY8C28x23, CY8C28x13, and CY8C28x03 devices do not have an analog output buffer for this pin. Therefore, this pin does not function as an analog column output for these devices. Document Number: 001-48111 Rev. *I Page 11 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 28-Pin Part Pinout Table 4. 28-Pin Part Pinout (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input I, M I, M M M I, M, S I/O, M, S I/O, M, S I, M, S Power I/O I/O I/O I/O Power M M M M Type Digital I/O I/O I/O I/O I/O I/O I/O I/O Analog I, M, S I/O, M, S I/O, M, S I, M, S M M I, M I, M Output M M M M Pin Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] SMP P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] P1[6] Crystal Input (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK[7]. Ground connection. Crystal Output (XTALout), I2C0 Serial Data (SDA), ISSP-SDATA[7]. I2C1 Serial Data (SDA).[10] Optional External Clock Input (EXTCLK). I2C1 Serial Clock (SCL).[10] Direct switched capacitor block input.[12] Direct switched capacitor block input.[12] Switch Mode Pump (SMP) connection to external components. I2C0 Serial Clock (SCL). I2C0 Serial Data (SDA). Description CY8C28403, CY8C28413, CY8C28433, CY8C28445, and CY8C28452 28-Pin PSoC Devices S, AI, M, P0[7] S, AIO, M, P0[5] S, AIO, M, P0[3] S, AI, M, P0[1] M, P2[7] M, P2[5] AI, M, P2[3] AI, M, P2[1] SMP I2C0 SCL, M, P1[7] I2C0 SDA, M, P1[5] M, P1[3] I2C0 SCL, XTALin, M, P1[1] Vss Analog column mux and SAR ADC input.[8] Analog column mux and SAR ADC input. Analog column output.[8, 9] Analog column mux and SAR ADC input. Analog column output.[8, 9] Analog column mux and SAR ADC input.[8] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd P0[6], M, AI, S P0[4], M, AIO, S P0[2], M, AIO, S P0[0], M, AI, S P2[6], M, External VRef P2[4], M, External AGND P2[2], M, AI P2[0], M, AI XRES P1[6], M, I2C1 SCL P1[4], M, EXTCLK P1[2], M, I2C1 SDA P1[0], M, XTALout, I2C0 SDA XRES Active high external reset with internal pull-down. P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD Direct switched capacitor block input.[13] Direct switched capacitor block input.[13] External Analog Ground (AGND). External Voltage Reference (VRef). Analog column mux and SAR ADC input.[8] Analog column mux and SAR ADC input. Analog column output.[8, 11] Analog column mux and SAR ADC input. Analog column output.[8, 11] Analog column mux and SAR ADC input.[8] Supply voltage. LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input Notes 12. This pin is not a direct switched capacitor block analog input for CY8C28x03 and CY8C28x13 devices. 13. This pin is not a direct switched capacitor block analog input for CY8C28x03, CY8C28x13, CY8C28x23, and CY8C28x33 devices. Document Number: 001-48111 Rev. *I Page 12 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 44-Pin Part Pinout Table 5. 44-Pin Part Pinout (TQFP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 Type Digital Analog I/O M I/O I, M I/O I, M I/O M I/O M I/O M I/O M Output I/O I/O I/O I/O I/O I/O I/O I/O Power I/O I/O I/O I/O I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O M M M M I, M I, M M M I, M, S I/O, M S I/O, M, S M M M M M M M M M M M M M M M M Pin Name P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] P1[6] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD P0[7] P0[5] P0[3] Description Direct switched capacitor block input.[12] Direct switched capacitor block input.[12] CY8C28513, CY8C28533, and CY8C28545 44-Pin PSoC Devices P2[7], M P0[1], M, AI, S P0[3], M, AIO, S P0[5], M, AIO, S P0[7], M, AI, S Vdd P0[6], M, AI, S P0[4], M, AIO, S P0[2], M, AIO, S P0[0], M, AI, S P2[6], M, External VRef M, P2[5] AI, M, P2[3] AI, M, P2[1] M, P4[7] M, P4[5] M, P4[3] M, P4[1] SMP M, P3[7] M, P3[5] M, P3[3] M, P3[1] I2C0 SCL, M, P1[7] I2C0 SDA, M, P1[5] M, P1[3] I2C0 SCL, XTALin, M, P1[1] Vss I2C0 SDA, XTALout, M, P1[0] I2C1 SDA, M, P1[2] EXTCLK, M, P1[4] I2C1 SCL, M, P1[6] I2C1 SDA, M, P3[0] 12 13 14 15 16 17 18 19 20 21 22 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 Switch Mode Pump (SMP) connection to external components. TQFP I2C0 Serial Clock (SCL). I2C0 Serial Data (SDA). Crystal Input (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK[7]. Ground connection. Crystal Output (XTALout), I2C0 Serial Data (SDA), ISSP-SDATA[7]. I2C1 Serial Data (SDA).[10] Optional External Clock Input (EXTCLK). I2C1 Serial Clock (SCL).[10] I2C1 Serial Data (SDA).[10] I2C1 Serial Clock (SCL).[10] 33 32 31 30 29 28 27 26 25 24 23 P2[4], M, External AGND P2[2], M, AI P2[0], M, AI P4[6], M P4[4], M P4[2], M P4[0], M XRES P3[6], M P3[4], M P3[2], M, I2C1 SCL Active high external reset with internal pull-down. I, M, S Power I/O I, M, S I/O I/O, M, S I/O I/O, M, S 43 I/O I, M, S P0[1] 44 I/O P2[7] LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input. Direct switched capacitor block input.[13] Direct switched capacitor block input.[13] External Analog Ground (AGND). External Voltage Reference (VRef). Analog column mux and SAR ADC input.[8] Analog column mux and SAR ADC input. Analog column output.[8, 11] Analog column mux and SAR ADC input. Analog column output.[8, 11] Analog column mux and SAR ADC input.[8] Supply voltage. Analog column mux and SAR ADC input.[8] Analog column mux and SAR ADC input. Analog column output.[8, 9] Analog column mux and SAR ADC input. Analog column output.[8, 9] Analog column mux and SAR ADC input.[8] Document Number: 001-48111 Rev. *I Page 13 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 48-Pin Part Pinout Table 6. 48-Pin Part Pinout (QFN[14]) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 Type Digital Analog I/O I, M I/O I, M I/O M I/O M I/O M I/O M Output I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O M M M M I, M I, M M M I, M, S M M M M M M M M M M M M M M M M M M M M Pin Name P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] Description Direct switched capacitor block input.[12] Direct switched capacitor block input.[12] CY8C28623, CY8C28643, and CY8C28645 48-Pin PSoC Devices P2[5], M P2[7], M P0[1], M, AI, S P0[3], M, AIO, S P0[5], M, AIO, S P0[7], M, AI, S Vdd P0[6], M, AI, S P0[4], M, AIO, S P0[2], M, AIO, S P0[0], M, AI, S P2[6], M, External VRef Switch Mode Pump (SMP) connection to external components. I2C0 Serial Clock (SCL). I2C0 Serial Data (SDA). Crystal Input (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK[7]. Ground connection. Crystal Output (XTALout), I2C0 Serial Data (SDA), ISSP-SDATA[7]. I2C1 Serial Data (SDA).[10] Optional External Clock Input (EXTCLK). I2C1 Serial Clock (SCL).[10] P1[6] P5[0] P5[2] P3[0] I2C1 Serial Data (SDA).[10] P3[2] I2C1 Serial Clock (SCL).[10] P3[4] P3[6] XRES Active high external reset with internal pull-down. P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] Pin No. 41 Digital Direct switched capacitor block input.[13] Direct switched capacitor block input.[13] External Analog Ground (AGND). External Voltage Reference (VRef). 42 43 44 45 Analog column mux and SAR ADC 46 input.[8] 39 I/O I/O, M, S P0[2] Analog column mux and SAR ADC input. 47 Analog column output.[8, 11] 40 I/O I/O, M, S P0[4] Analog column mux and SAR ADC input. 48 I/O M Analog column output.[8, 11] LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, and M = Analog Mux Bus Input. Note 14. The QFN package has a center pad that must be connected to ground (VSS) Pin Nam Description e I/O I, M, S P0[6] Analog column mux and SAR ADC input.[8] Power VDD Supply voltage. I/O I, M, S P0[7] Analog column mux and SAR ADC input.[8] I/O I/O, M, S P0[5] Analog column mux and SAR ADC input. Analog column output.[8, 9] I/O I/O, M, S P0[3] Analog column mux and SAR ADC input. Analog column output.[8, 9] I/O I, M, S P0[1] Analog column mux and SAR ADC input.[8] I/O M P2[7] Analog P2[5] Document Number: 001-48111 Rev. *I M, P5[1] I2C0 SCL, M, P1[7] I2C0 SDA, M, P1[5] M, P1[3] I2C0 SCL, XTALin, M, P1[1] Vss I2C0 SDA, XTALout, M, P1[0] I2C1 SDA, M, P1[2] EXTCLK, M, P1[4] I2C1 SCL, M, P1[6] M, P5[0] M, P5[2] Type 13 14 15 16 17 18 19 20 21 22 23 24 AI, M, P2[3] AI, M, P2[1] M, P4[7] M, P4[5] M, P4[3] M, P4[1] SMP M, P3[7] M, P3[5] M, P3[3] M, P3[1] M, P5[3] 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 QFN (Top View) 36 35 34 33 32 31 30 29 28 27 26 25 P2[4], M, External AGND P2[2], M, AI P2[0], M, AI P4[6], M P4[4], M P4[2], M P4[0], M XRES P3[6], M P3[4], M P3[2], M, I2C1 SCL P3[0], M, I2C1 SDA Page 14 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 56-Pin Part Pinout The 56-pin SSOP part is for the CY8C28000 On-Chip Debug (OCD) PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. Table 7. 56-Pin Part Pinout (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O M M M M M M M M M M I/O I/O Power M M I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O OCD OCD Output M M M M M M M M I, M, S I/O, M, S I/O, M, S I, M, S M M I I M M I, M I, M M M Type Digital Analog Pin Name NC P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] OCDE OCD even data I/O. OCDO OCD odd data output. SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] NC P1[3] P1[1] Crystal Input (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK[7]. Ground connection. No connection. No connection. Crystal Output (XTALout), I2C0 Serial Data (SDA), ISSP-SDATA[7]. I2C1 Serial Data (SDA). Optional External Clock Input (EXTCLK). I2C1 Serial Clock (SCL). I2C0 Serial Clock (SCL). I2C0 Serial Data (SDA). No connection. Switch Mode Pump (SMP) connection to required external components. Direct switched capacitor block input. Direct switched capacitor block input. Description No connection. Analog column mux and SAR ADC input. Analog column mux and SAR ADC input. Analog column output. Analog column mux and SAR ADC input. Analog column output. Analog column mux and SAR ADC input. CY8C28000 56-Pin PSoC Device NC S, AI, M, P0[7] S, AIO, M, P0[5] S, AIO, M, P0[3] S, AI, M, P0[1] M, P2[7] M, P2[5] AI, M, P2[3] AI, M, P2[1] M, P4[7] M, P4[5] M, P4[3] M, P4[1] OCDE OCDO SMP M, P3[7] M, P3[5] M, P3[3] M, P3[1] M, P5[3] M, P5[1] I2C0 SCL, M, P1[7] I2C0 SDA, M, P1[5] NC M, P1[3] SCLK, I2C0 SCL, XTALIn, M, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 Vdd P0[6], M, AI, S P0[4], M, AIO, S P0[2], M, AIO, S P0[0], M, AI, S P2[6], M, External VRef P2[4], M, External AGND P2[2], M, AI P2[0], M, AI P4[6], M P4[4], M P4[2], M P4[0], M CCLK HCLK XRES P3[6], M P3[4], M P3[2], M, I2C1 SCL P3[0], M, I2C1 SDA P5[2], M P5[0], M P1[6], M, I2C1 SCL P1[4], M, EXTCLK P1[2], M, I2C1 SDA P1[0], M, XTALOut, I2C0 SDA, SDATA NC NC SSOP Not for Production VSS NC NC P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] I2C1 Serial Data (SDA). I2C1 Serial Clock (SCL). Document Number: 001-48111 Rev. *I Page 15 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Table 7. 56-Pin Part Pinout (SSOP) (continued) Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 OCD OCD I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Type Digital Analog Input M M M M M M I, M I, M M M I, M, S I/O, M, S I/O, M, S I, M, S Power Pin Name Description XRES Active high external reset with internal pull-down. HCLK OCD high speed clock output. CCLK OCD CPU clock output. P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VRef). Analog column mux and SAR ADC input. Analog column mux and SAR ADC input. Analog column output. Analog column mux and SAR ADC input. Analog column output. Analog column mux and SAR ADC input. Supply voltage. VDD LEGEND: A = Analog, I = Input, O = Output, S = SAR ADC Input, M = Analog Mux Bus Input, and OCD = On-Chip Debug. Document Number: 001-48111 Rev. *I Page 16 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Register Reference This section lists the registers of the CY8C28xxx PSoC devices. For detailed register information, reference the PSoC Technical Reference Manual for CY8C28xxx PSoC devices. Register Conventions The register conventions specific to this section are listed in the following table. Convention R W L C # Description Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific Register Mapping Tables CY8C28xxx PSoC devices have a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks. The XIO bit in the Flag register (CPU_F) determines which bank of registers CPU instructions access. When the XIO bit is set the registers in Bank 1 are accessed by CPU instructions. When the XIO bit is cleared the registers in Bank 0 are accessed by CPU instructions. Note In the following register mapping tables, blank fields are reserved and should not be accessed. Document Number: 001-48111 Rev. *I Page 17 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Table 8. CY8C28x03 Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW SADC_DH SADC_DL TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 I2C1_DR Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBC20DR0 DBC20DR1 DBC20DR2 DBC20CR0 DBC21DR0 DBC21DR1 DBC21DR2 DBC21CR0 DCC22DR0 DCC22DR1 DCC22DR2 DCC22CR0 DCC23DR0 DCC23DR1 DCC23DR2 DCC23CR0 Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F # Access is bit specific. RW RW RW RW RW RW RW MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 Access # W RW # # W RW # # W RW # # W RW # Name Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW CPU_SCR1 CPU_F MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT I2C1_SCR I2C1_MSCR CUR_PP STK_PP Access Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF # # RL W W R R RW RW RW RW RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W # # RW RW Access RW RW RW RW RW RW RW RW DCC13CR0 3F # Blank fields are Reserved and should not be accessed. RDI1DSM BF RW CPU_SCR0 *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *I Page 18 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Table 9. CY8C28x03 Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW SADC_TSCR0 SADC_TSCR1 I2C1_CFG TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F # Access is bit specific. RW RW RW RW RW RW RW GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR SADC_CR0 SADC_CR1 SADC_CR2 SADC_CR3 SADC_CR4 I2C0_ADDR I2C1_ADDR AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDIODSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name SADC_TSCMPL SADC_TSCMPH Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW CPU_SCR1 CPU_SCR0 FLS_PR1 CPU_F IMO_TR ILO_TR BDG_TR ECO_TR OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU Access RW RW Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF # # RW RL RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Access RW RW RW RW RW RW RW RW Blank fields are Reserved and should not be accessed. *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *I Page 19 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Table 10. CY8C28x13 Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW SADC_DH SADC_DL TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 AMUX_CFG Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBC20DR0 DBC20DR1 DBC20DR2 DBC20CR0 DBC21DR0 DBC21DR1 DBC21DR2 DBC21CR0 DCC22DR0 DCC22DR1 DCC22DR2 DCC22CR0 DCC23DR0 DCC23DR1 DCC23DR2 DCC23CR0 Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F # Access is bit specific. RW RW RW RW RW RW MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RW DEC0_DH DEC0_DL DEC1_DH DEC1_DL Access # W RW # # W RW # # W RW # # W RW # Name Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW DAC1_D DAC0_D CPU_SCR1 CPU_F DEC_CR0* DEC_CR1* MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 RC RC RC RC IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT CUR_PP STK_PP Access Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW RW # # RL RW RW W W R R RW RW RW RW RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W RW RW Access RW RW RW RW RW RW RW RW DCC13CR0 3F # Blank fields are Reserved and should not be accessed. RDI1DSM BF RW CPU_SCR0 *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *I Page 20 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Table 11. CY8C28x13 Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ACE0_CR1 ACE0_CR2 ACE0_CR3 ACE_CMP_GI_EN ACE_ALT_CR0 ACE_ABF_CR0 ACE_AMX_IN ACE_CMP_CR0 ACE_CMP_CR1 SADC_TSCR0 SADC_TSCR1 ACE_AMD_CR0 TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 AMUX_CFG1 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDIODSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM RW GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR SADC_CR0 SADC_CR1 SADC_CR2 SADC_CR3 SADC_CR4 I2C0_ADDR DEC_CR5 DEC1_CR0 DEC0_CR0 DEC_CR3 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ACE01CR1 ACE01CR2 ASE11CR0 ACE_CLK_CR0 ACE_CLK_CR1 ACE_CLK_CR3 ACE_PWM_CR ACE_ADC0_CR ACE_ADC1_CR Name SADC_TSCMPL SADC_TSCMPH ACE_AMD_CR1 Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW IDAC_CR0 CPU_SCR1 CPU_SCR0 FLS_PR1 CPU_F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 IDAC_CR1 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR IDAC_CR2 IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5 RW RW RW RW RW RW RW RW RW RW GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU DEC0_CR DEC1_CR RW RW RW Access RW RW RW Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW # # RW RL RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Access RW RW RW RW RW RW RW RW Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *I Page 21 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Table 12. CY8C28x23 Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 AMX_IN AMUX_CFG CLK_CR3 ARF_CR CMP_CR0 ASY_CR CMP_CR1 I2C1_DR Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBC20DR0 DBC20DR1 DBC20DR2 DBC20CR0 DBC21DR0 DBC21DR1 DBC21DR2 DBC21CR0 DCC22DR0 DCC22DR1 DCC22DR2 DCC22CR0 DCC23DR0 DCC23DR1 DCC23DR2 DCC23CR0 Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F # Access is bit specific. RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # # RW RW MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 DEC0_DH DEC0_DL DEC1_DH DEC1_DL Access # W RW # # W RW # # W RW # # W RW # ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW CPU_SCR1 CPU_F RC RC RC RC RW RW RW RW RW RW RW RW IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT I2C1_SCR I2C1_MSCR DEC_CR0* DEC_CR1* MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 CUR_PP STK_PP Access RW RW RW RW RW RW RW RW Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF # # RL RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W # # RW RW W W R R RW RW RW RW RW RW Access RW RW RW RW RW RW RW RW DCC13CR0 3F # Blank fields are Reserved and should not be accessed. RDI1DSM BF RW CPU_SCR0 *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *I Page 22 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Table 13. CY8C28x23 Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW I2C1_CFG TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 CLK_CR2 AMD_CR1 ALT_CR0 CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F # Access is bit specific. RW RW RW RW RW I2C0_ADDR I2C1_ADDR AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDIODSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM RW RW RW RW RW RW RW RW GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR DEC_CR5 DEC1_CR0 DEC0_CR0 DEC_CR3 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW CPU_SCR1 CPU_SCR0 FLS_PR1 CPU_F RW RW RW RW RW RW RW RW IMO_TR ILO_TR BDG_TR ECO_TR OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP RW RW RW RW RW RW GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU DEC0_CR DEC1_CR Access Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF # # RW RL RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Access RW RW RW RW RW RW RW RW Blank fields are Reserved and should not be accessed. *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *I Page 23 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Table 14. CY8C28x33 Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW SADC_DH SADC_DL TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 AMX_IN AMUX_CFG CLK_CR3 ARF_CR CMP_CR0 ASY_CR CMP_CR1 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBC20DR0 DBC20DR1 DBC20DR2 DBC20CR0 DBC21DR0 DBC21DR1 DBC21DR2 DBC21CR0 DCC22DR0 DCC22DR1 DCC22DR2 DCC22CR0 DCC23DR0 DCC23DR1 DCC23DR2 DCC23CR0 Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F # Access is bit specific. RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # # RW DEC0_DH DEC0_DL DEC1_DH DEC1_DL DEC2_DH DEC2_DL DEC3_DH DEC3_DL MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 Access # W RW # # W RW # # W RW # # W RW # ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE RC RC RC RC RC RC RC RC W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW DAC1_D DAC0_D CPU_SCR1 CPU_F DEC_CR0* DEC_CR1* MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 RW RW RW RW RW RW RW RW IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT CUR_PP STK_PP Access RW RW RW RW RW RW RW RW Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW RW # # RL RW RW W W R R RW RW RW RW RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W RW RW Access RW RW RW RW RW RW RW RW DCC13CR0 3F # Blank fields are Reserved and should not be accessed. RDI1DSM BF RW CPU_SCR0 *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *I Page 24 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Table 15. CY8C28x33 Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ACE0_CR1 ACE0_CR2 ACE0_CR3 ACE_CMP_GI_EN ACE_ALT_CR0 ACE_ABF_CR0 ACE_AMX_IN ACE_CMP_CR0 ACE_CMP_CR1 SADC_TSCR0 SADC_TSCR1 ACE_AMD_CR0 TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 CLK_CR2 AMUX_CFG1 AMD_CR1 ALT_CR0 CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDIODSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM RW RW RW RW RW RW RW RW RW GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR SADC_CR0 SADC_CR1 SADC_CR2 SADC_CR3 SADC_CR4 I2C0_ADDR DEC3_CR0 DEC2_CR0 DEC_CR5 DEC1_CR0 DEC_CR4 DEC0_CR0 DEC_CR3 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ACE01CR1 ACE01CR2 ASE11CR0 ACE_CLK_CR0 ACE_CLK_CR1 ACE_CLK_CR3 ACE_PWM_CR ACE_ADC0_CR ACE_ADC1_CR Name SADC_TSCMPL SADC_TSCMPH ACE_AMD_CR1 Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW IDAC_CR0 CPU_SCR1 CPU_SCR0 FLS_PR1 CPU_F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU DEC0_CR DEC1_CR DEC2_CR DEC3_CR MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 IDAC_CR1 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR IDAC_CR2 IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5 RW RW RW RW RW RW RW Access RW RW RW Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW # # RW RL RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Access RW RW RW RW RW RW RW RW Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *I Page 25 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Table 16. CY8C28x43 Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW SADC_DH SADC_DL TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 ACB02CR3 ACB02CR0 ACB02CR1 ACB02CR2 ACB03CR3 ACB03CR0 ACB03CR1 AMX_IN AMUX_CFG CLK_CR3 ARF_CR CMP_CR0 ASY_CR CMP_CR1 I2C1_DR Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBC20DR0 DBC20DR1 DBC20DR2 DBC20CR0 DBC21DR0 DBC21DR1 DBC21DR2 DBC21CR0 DCC22DR0 DCC22DR1 DCC22DR2 DCC22CR0 DCC23DR0 DCC23DR1 DCC23DR2 DCC23CR0 Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # # RW RW Access # W RW # # W RW # # W RW # # W RW # Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 DEC0_DH DEC0_DL DEC1_DH DEC1_DL DEC2_DH DEC2_DL DEC3_DH DEC3_DL MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RC RC RC RC RC RC RC RC W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW CPU_SCR1 CPU_F IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT I2C1_SCR I2C1_MSCR DEC_CR0* DEC_CR1* MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 CUR_PP STK_PP Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF # # RL RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W # # RW RW W W R R RW RW RW RW RW RW Access RW RW RW RW RW RW RW RW DCC13CR0 3F # ACB03CR2 Blank fields are Reserved and should not be accessed. 7F RW # Access is bit specific. RDI1DSM BF RW CPU_SCR0 *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *I Page 26 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Table 17. CY8C28x43 Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW SADC_TSCR0 SADC_TSCR1 CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN CMP_GO_EN1 AMD_CR1 ALT_CR0 ALT_CR1 CLK_CR2 AMUX_CFG1 I2C1_CFG TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F # Access is bit specific. RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR SADC_CR0 SADC_CR1 SADC_CR2 SADC_CR3 SADC_CR4 I2C0_ADDR I2C1_ADDR AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDIODSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM DEC3_CR0 DEC2_CR0 DEC_CR5 DEC1_CR0 DEC_CR4 DEC0_CR0 DEC_CR3 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name SADC_TSCMPL SADC_TSCMPH Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW CPU_SCR1 CPU_SCR0 FLS_PR1 CPU_F IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5 RW OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP RW RW RW RW RW RW GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU DEC0_CR DEC1_CR DEC2_CR DEC3_CR MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 Access RW RW Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF # # RW RL RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Access RW RW RW RW RW RW RW RW Blank fields are Reserved and should not be accessed. *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *I Page 27 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Table 18. CY8C28x45 Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW SADC_DH SADC_DL TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 ACB02CR3 ACB02CR0 ACB02CR1 ACB02CR2 ACB03CR3 ACB03CR0 ACB03CR1 AMX_IN AMUX_CFG CLK_CR3 ARF_CR CMP_CR0 ASY_CR CMP_CR1 I2C1_DR Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBC20DR0 DBC20DR1 DBC20DR2 DBC20CR0 DBC21DR0 DBC21DR1 DBC21DR2 DBC21CR0 DCC22DR0 DCC22DR1 DCC22DR2 DCC22CR0 DCC23DR0 DCC23DR1 DCC23DR2 DCC23CR0 Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # # RW RW Access # W RW # # W RW # # W RW # # W RW # Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 DEC0_DH DEC0_DL DEC1_DH DEC1_DL DEC2_DH DEC2_DL DEC3_DH DEC3_DL MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RC RC RC RC RC RC RC RC W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW DAC1_D DAC0_D CPU_SCR1 CPU_F IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT I2C1_SCR I2C1_MSCR DEC_CR0* DEC_CR1* MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 CUR_PP STK_PP Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW RW # # RL RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W # # RW RW W W R R RW RW RW RW RW RW Access RW RW RW RW RW RW RW RW DCC13CR0 3F # ACB03CR2 Blank fields are Reserved and should not be accessed. 7F RW # Access is bit specific. RDI1DSM BF RW CPU_SCR0 *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *I Page 28 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Table 19. CY8C28x45 Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ACE0_CR1 ACE0_CR2 ACE0_CR3 ACE_CMP_GI_EN ACE_ALT_CR0 ACE_ABF_CR0 ACE_AMX_IN ACE_CMP_CR0 ACE_CMP_CR1 SADC_TSCR0 SADC_TSCR1 ACE_AMD_CR0 CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN CMP_GO_EN1 AMD_CR1 ALT_CR0 ALT_CR1 CLK_CR2 AMUX_CFG1 I2C1_CFG TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR SADC_CR0 SADC_CR1 SADC_CR2 SADC_CR3 SADC_CR4 I2C0_ADDR I2C1_ADDR AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDIODSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM DEC3_CR0 DEC2_CR0 DEC_CR5 DEC1_CR0 DEC_CR4 DEC0_CR0 DEC_CR3 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ACE01CR1 ACE01CR2 ASE11CR0 ACE_CLK_CR0 ACE_CLK_CR1 ACE_CLK_CR3 ACE_PWM_CR ACE_ADC0_CR ACE_ADC1_CR Name SADC_TSCMPL SADC_TSCMPH ACE_AMD_CR1 Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW IDAC_CR0 CPU_SCR1 CPU_SCR0 FLS_PR1 CPU_F RW RW RW RW RW RW RW Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU DEC0_CR DEC1_CR DEC2_CR DEC3_CR MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 IDAC_CR1 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR IDAC_CR2 IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5 Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW # # RW RL RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Access RW RW RW RW RW RW RW RW Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *I Page 29 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Table 20. CY8C28x52 Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 ACB02CR3 ACB02CR0 ACB02CR1 ACB02CR2 ACB03CR3 ACB03CR0 ACB03CR1 AMX_IN AMUX_CFG CLK_CR3 ARF_CR CMP_CR0 ASY_CR CMP_CR1 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # # RW Access Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 DEC0_DH DEC0_DL DEC1_DH DEC1_DL DEC2_DH DEC2_DL DEC3_DH DEC3_DL MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RC RC RC RC RC RC RC RC W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW DAC1_D DAC0_D CPU_SCR1 CPU_F DEC_CR0* DEC_CR1* MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT CUR_PP STK_PP Name Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW RW # # RL RW RW W W R R RW RW RW RW RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W RW RW Access DCC13CR0 3F # ACB03CR2 Blank fields are Reserved and should not be accessed. 7F RW # Access is bit specific. RDI1DSM BF RW CPU_SCR0 *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *I Page 30 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Table 21. CY8C28x52 Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW ACE0_CR1 ACE0_CR2 ACE0_CR3 ACE_CMP_GI_EN ACE_ALT_CR0 ACE_ABF_CR0 ACE_AMX_IN ACE_CMP_CR0 ACE_CMP_CR1 ACE_AMD_CR0 TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN CMP_GO_EN1 AMD_CR1 ALT_CR0 ALT_CR1 CLK_CR2 AMUX_CFG1 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RW RW RW RW RW RW AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDIODSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM I2C0_ADDR RW RW RW RW RW RW RW RW RW RW RW GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR DEC3_CR0 DEC2_CR0 DEC_CR5 DEC1_CR0 DEC_CR4 DEC0_CR0 DEC_CR3 ACE01CR1 ACE01CR2 ASE11CR0 ACE_CLK_CR0 ACE_CLK_CR1 ACE_CLK_CR3 ACE_PWM_CR ACE_ADC0_CR ACE_ADC1_CR ACE_AMD_CR1 Access Name Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW IDAC_CR0 CPU_SCR1 CPU_SCR0 FLS_PR1 CPU_F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU DEC0_CR DEC1_CR DEC2_CR DEC3_CR MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 IDAC_CR1 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR IDAC_CR2 IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5 RW RW RW RW RW RW RW Access Name Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF RW # # RW RL RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Access Blank fields are Reserved and should not be accessed. # Access is bit specific. *Address has a dual purpose, see “Mapping Exceptions” on page 251 Document Number: 001-48111 Rev. *I Page 31 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C28xxx PSoC devices. For the most up to date electrical specifications, confirm that you have the most recent datasheet by going to the web at http//www.cypress.com. Specifications are valid for -40oC ≤ TA ≤ 85°C and TJ ≤ 100°C, except where noted. Specifications for devices running at greater than 12 MHz are valid for -40°C ≤ TA ≤ 70°C and TJ ≤ 82°C. Figure 7. Voltage versus CPU Frequency 5.25 lid ing Va rat on pe i O R eg 4.75 Document Number: 001-48111 Rev. *I Vdd Voltage 3.00 93 kHz 12 MHz CPU Frequency 24 MHz Page 32 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Absolute Maximum Ratings Table 22. Absolute Maximum Ratings Symbol TSTG Description Storage temperature Min -55 Typ 25 Max +100 Units °C Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is +25°C ± 25°C. Extended duration storage temperatures above 65°C degrade reliability. TBAKETEMP Bake temperature - 125 tBAKETIME Bake time TA VDD VIO VIOZ IMIO IMAIO ESD LU Ambient temperature with power applied Supply voltage on VDD relative to VSS DC input voltage DC voltage applied to tri-state Maximum current into any port pin Maximum current into any port pin configured as analog driver Electro static discharge voltage Latch up current See package label -40 -0.5 VSS- 0.5 VSS – 0.5 -25 -50 2000 – - See Package label 72 o C Hours – – – – – – – – +85 +6.0 VDD + 0.5 VDD + 0.5 +50 +50 – 200 °C V V V mA mA V mA Human Body Model ESD. Operating Temperature Table 23. Operating Temperature Symbol TA TJ Description Ambient temperature Junction temperature Min -40 -40 Typ – – Max +85 +100 Units °C °C Notes The temperature rise from ambient to junction is package specific. See Thermal Impedances on page 66. The user must limit the power consumption to comply with this requirement. Document Number: 001-48111 Rev. *I Page 33 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 DC Electrical Characteristics DC Chip Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40°C ≤ TA ≤ 85°C, or 3.0 V to 3.6 V and –40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5 V and 3.3 V at 25°C and are for design guidance only. Table 24. DC Chip Level Specifications Symbol Description VDD Supply voltage IDD Supply current Min 3.00 – Typ – 8 Max 5.25 14 Units V mA Notes Conditions are VDD = 5.0 V, TA = 25 °C, CPU = 3 MHz, SYSCLK doubler disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. Conditions are VDD = 3.3 V, TA = 25 °C, CPU = 3 MHz, SYSCLK doubler disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. Conditions are VDD = 3.3 V, TA = 25 °C, CPU = 0.75 MHz, SYSCLK doubler disabled, VC1 = 0.375 MHz, VC2 = 23.44 kHz, VC3 = 0.09 kHz. Conditions are with internal slow speed oscillator, VDD = 3.3 V, –40 °C ≤ TA ≤ 55 °C. Conditions are with internal slow speed oscillator, VDD = 3.3 V, 55 °C < TA ≤ 85 °C. Conditions are with properly loaded, 1 μW max, 32.768 kHz crystal. VDD = 3.3 V, –40 °C ≤ TA ≤ 55 °C. Conditions are with properly loaded, 1 μW max, 32.768 kHz crystal. VDD = 3.3 V, 55 °C < TA ≤ 85 °C. Extra current consumed by the RTC during sleep. This number is typical at 25 °C and 5 V. Trimmed for appropriate VDD. Max is peak current after XRES; Typical value is the steady state current value. TA = 25 °C. IDD3 Supply current – 5 9 mA IDDP Supply current when IMO = 6 MHz using SLIMO mode=1 – 2 3 mA ISB Sleep (Mode) current with POR, LVD, sleep timer, and WDT.[15] Sleep (Mode) current with POR, LVD, sleep timer, and WDT at high temperature.[15] Sleep (Mode) Current with POR, LVD, sleep timer, WDT, and external crystal.[15] Sleep (Mode) current with POR, LVD, sleep timer, WDT, and external crystal at high temperature.[15] Current consumed by RTC during sleep – 3 10 μA μA μA μA ISBH – 4 25 ISBXTL – 4 13 ISBXTLH – 5 26 ISBRTC – 0.5 1 µA VREF ISXRES Reference voltage (Bandgap) Supply current with XRES asserted 5 V Supply current with XRES asserted 3.3 V 1.280 – - 1.300 0.65 0.4 1.320 3 1.5 V mA mA Note 15. Standby (sleep) current includes all functions (POR, LVD, WDT, Sleep Timer) needed for reliable system operation. This should be compared with devices that have similar functions enabled. Document Number: 001-48111 Rev. *I Page 34 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 DC GPIO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 25. DC GPIO Specifications Symbol RPU RPD VOH Description Pull-up resistor Pull-down resistor High output level Min 4 4 VDD – 1.0 Typ 5.6 5.6 – Max 8 8 – Units Notes kΩ kΩ V IOH = 10 mA, VDD = 4.75 to 5.25 V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget. V IOL = 25 mA, VDD = 4.75 to 5.25 V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 150 mA maximum combined IOL budget. mA VOH = VDD – 1.0 V, see the limitations of the total current in the note for VOH. mA VOL = 0.75 V, see the limitations of the total current in the note for VOL. V VDD = 3.0 to 5.25. V VDD = 3.0 to 5.25. mV nA Gross tested to 1 μA. pF Package and pin dependent. Temp = 25 °C. pF Package and pin dependent. Temp = 25 °C. VOL Low output level – – 0.75 IOH High level source current 10 – – IOL VIL VIH VH IIL CIN COUT Low level sink current Input low level Input high level Input hysteresis Input leakage (absolute value) Capacitive load on pins as input Capacitive load on pins as output 25 – 2.1 – – – – – – – 60 1 3.5 3.5 – 0.8 – – – 10 10 Document Number: 001-48111 Rev. *I Page 35 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. The Operational Amplifiers covered by these specifications are components of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Table 26. 5 V DC Operational Amplifier Specifications Description Input Offset Voltage CT Block (absolute value) Power = Low, Opamp bias = High Power = Medium, Opamp bias = High Power = High, Opamp bias = High VOSOA Input Offset Voltage SC and AGND Opamps (absolute value) TCVOSOA Average Input Offset Voltage Drift IEBOA Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) CINOA VCMOA Common Mode Voltage Range Common Mode Voltage Range (high power or high Opamp bias) Symbol VOSOACT Min – – – – – – – 0.0 0.5 Typ 1.6 1.3 1.2 1 7.0 200 4.5 – – Max 8 8 8 6 35.0 – 9.5 VDD VDD – 0.5 Units mV mV mV mV Notes Applies to High and Low Opamp bias. μV/°C pA Gross tested to 1 μA. pF Package and pin dependent. Temp = 25 °C. V The common-mode input V voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. dB dB dB dB dB dB CMRROA Common Mode Rejection Ratio Power = Low Power = Medium Power = High GOLOA Open Loop Gain Power = Low Power = Medium Power = High VOHIGHOA High Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High 60 60 60 60 60 80 – – – – – – – – – – – – VDD – 0.2 VDD – 0.2 VDD – 0.5 – – – – – – – – – V V V VOLOWOA Low Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High ISOA Supply Current (including associated AGND buffer) Power = Low, Opamp bias = Low Power = Low, Opamp bias = High Power = Medium, Opamp bias = Low Power = Medium, Opamp bias = High Power = High, Opamp bias = Low Power = High, Opamp bias = High Supply Voltage Rejection Ratio – – – 0.2 0.2 0.5 V V V μA μA μA μA μA μA dB PSRROA – – – – – – 60 200 400 700 1400 2400 4600 – 300 600 1100 2000 3600 7700 – VSS ≤ VIN ≤ (VDD – 2.25) or (VDD – 1.25 V) ≤ VIN ≤ VDD. Document Number: 001-48111 Rev. *I Page 36 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Table 27. 3.3 V DC Operational Amplifier Specifications Description Input Offset Voltage CT Blocks (absolute value) Power = Low, Opamp bias = High Power = Medium, Opamp bias = High Power = High, Opamp bias = High VOSOA Input Offset Voltage SC and AGND (absolute value) TCVOSOA Average Input Offset Voltage Drift IEBOA Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) CINOA VCMOA Common Mode Voltage Range Symbol VOSOACT Min – – – – – – – 0.2 Typ 1.65 1.32 – 1 7.0 200 4.5 – Max 8 8 – 6 35.0 – 9.5 VDD – 0.2 Units mV mV mV mV Notes Applies to High and Low Opamp bias. μV/°C pA Gross tested to 1 μA. pF Package and pin dependent. Temp = 25 °C. V The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. dB dB dB dB dB dB V V V CMRROA Common Mode Rejection Ratio Power = Low Power = Medium Power = High GOLOA Open Loop Gain Power = Low Power = Medium Power = High VOHIGHOA High Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High is 5 V only 50 50 50 60 60 80 VDD – 0.2 VDD – 0.2 VDD – 0.2 – – – – – – – – – – – – – – – – – – – – – VOLOWOA Low Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High ISOA Supply Current (including associated AGND buffer) Power = Low, Opamp bias = Low Power = Low, Opamp bias = High Power = Medium, Opamp bias = Low Power = Medium, Opamp bias = High Power = High, Opamp bias = Low Power = High, Opamp bias = High PSRROA Supply Voltage Rejection Ratio – – – 0.2 0.2 0.2 V V V μA μA μA μA μA μA dB – – – – – – 50 200 400 700 1400 2400 4600 80 300 600 1000 2000 3600 7500 – VSS ≤ VIN ≤ (VDD – 2.25 V) or (VDD – 1.25 V) ≤ VIN ≤ VDD. Document Number: 001-48111 Rev. *I Page 37 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 DC Type-E Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. The Operational Amplifiers covered by these specifications are components of the Limited Type E Analog PSoC blocks. Table 28. 5 V DC Type-E Operational Amplifier Specifications Symbol Description Input offset voltage (absolute value) VOSOA Min – – – – – 0.0 – Typ 2.5 2.5 10 200 4.5 – 10 Max 15 20 – – 9.5 VDD 30 Units mV mV Notes For 0.2 V < VIN < VDD – 1.2 V. For VIN = 0 to 0.2 V and VIN > VDD – 1.2 V. TCVOSOA Average input offset voltage drift IEBOA[16] Input leakage current (Port 0 Analog Pins) Input capacitance (Port 0 Analog Pins) CINOA VCMOA ISOA Common mode voltage range Amplifier supply current μV/°C nA Gross tested to 1 μA. pF Package and pin dependent. Temp = 25 °C. V μA Table 29. 3.3 V DC Type-E Operational Amplifier Specifications Symbol Description Input offset voltage (absolute value) VOSOA Min – – – – – 0 – Typ 2.5 2.5 10 200 4.5 – 10 Max 15 20 – – 9.5 VDD 30 Units Notes mV For 0.2 V < VIN < VDD – 1.2 V. mV For VIN = 0 to 0.2 V and VIN > VDD – 1.2 V. μV/°C nA Gross tested to 1 μA. pF Package and pin dependent. Temp = 25 °C. V μA TCVOSOA Average input offset voltage drift IEBOA[16] Input leakage current (Port 0 Analog Pins) Input capacitance (Port 0 Analog Pins) CINOA VCMOA ISOA Common mode voltage range Amplifier supply current DC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V at 25 °C and are for design guidance only. Table 30. DC Low Power Comparator Specifications Symbol VREFLPC VOSLPC ISLPC Description Low power comparator (LPC) reference voltage range LPC voltage offset LPC supply current Min 0.2 – – Typ – 2.5 10 Max VDD – 1 30 40 Units V mV μA Notes Note 16. Atypical behavior: IEBOA of Port 0 Pin 0 is below 1 nA at 25 °C; 50 nA over temperature. Use Port 0 Pins 1-7 for the lowest leakage of 200 nA. Document Number: 001-48111 Rev. *I Page 38 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 DC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 31. 5 V DC Analog Output Buffer Specifications Symbol CL Description Load capacitance Min – Typ – Max 200 Units pF Notes This specification applies to the external circuit that is being driven by the analog output buffer. VOSOB TCVOSOB VCMOB ROUTOB VOHIGHOB VOLOWOB ISOB PSRROB Input offset voltage (Absolute Value) – Average input offset voltage drift – Common-mode input voltage range 0.5 Output resistance – Power = Low – Power = High High output voltage swing (Load = 32 Ω to VDD/2) Power = Low 0.5 × VDD + 1.3 Power = High 0.5 × VDD + 1.3 Low output voltage swing (Load = 32 Ω to VDD/2) Power = Low – Power = High – Supply current including bias cell (No Load) Power = Low – Power = High – Supply voltage rejection ratio 53 3 +6 – 1 1 12 20 VDD – 1.0 – – mV μV/°C V Ω Ω – – – – V V – – 0.5 × VDD – 1.3 0.5 × VDD – 1.3 5.1 8.8 – V V 1.1 2.6 64 mA mA dB (0.5 × VDD – 1.0) ≤ VOUT ≤ (0.5 × VDD + 0.9). Document Number: 001-48111 Rev. *I Page 39 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Table 32. 3.3 V DC Analog Output Buffer Specifications Symbol CL Description Load Capacitance Min – Typ – Max 200 Units pF Notes This specification applies to the external circuit that is being driven by the analog output buffer. VOSOB TCVOSOB VCMOB ROUTOB Input Offset Voltage (Absolute Value) – Average Input Offset Voltage Drift – Common-Mode Input Voltage Range 0.5 Output Resistance Power = Low – Power = High – VOHIGHOB High Output Voltage Swing (Load = 1 kΩ to VDD/2) Power = Low 0.5 × VDD + 1.0 Power = High 0.5 × VDD + 1.0 VOLOWOB Low Output Voltage Swing (Load = 1 kΩ to VDD/2) – Power = Low – Power = High ISOB Supply current including bias cell (No – Load) – Power = Low Power = High PSRROB Supply voltage rejection ratio 47 3 +6 – 1 1 12 20 VDD – 1.0 – – mV μV/°C V Ω Ω – – – – V V – – 0.8 2.0 64 0.5 × VDD – 1.0 0.5 × VDD – 1.0 2.0 4.3 – V V mA mA dB (0.5 × VDD – 1.0) ≤ VOUT ≤ (0.5 × VDD + 0.9). Document Number: 001-48111 Rev. *I Page 40 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 DC Switch Mode Pump Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 33. DC Switch Mode Pump (SMP) Specifications Symbol VPUMP 5 V Description 5 V output voltage Min 4.75 Typ 5.0 Max 5.25 Units Notes V Configuration of footnote.[17] Average, neglecting ripple. SMP trip voltage is set to 5.0 V. V Configuration of footnote.[17] Average, neglecting ripple. SMP trip voltage is set to 3.25 V. Configuration of footnote.[17] SMP trip voltage is set to 3.25 V. mA SMP trip voltage is set to 5.0 V. mA V Configuration of footnote.[17] SMP trip voltage is set to 5.0 V. V Configuration of footnote.[17] SMP trip voltage is set to 3.25 V. V Configuration of footnote.[17] %VO Configuration of footnote.[17] VO is the “VDD Value for PUMP Trip” specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 40 on page 50. %VO Configuration of footnote.[17] VO is the “VDD Value for PUMP Trip” specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 40 on page 50. mVpp Configuration of footnote.[17] Load is 5mA. % MHz % Configuration of footnote.[17] Load is 5 mA. SMP trip voltage is set to 3.25 V. VPUMP 3 V 3 V output voltage 3.00 3.25 3.60 IPUMP VBAT5 V VBAT3 V VBATSTART ΔVPUMP_Line Available output current VBAT = 1.5 V, VPUMP = 3.25 V VBAT = 1.8 V, VPUMP = 5.0 V Input voltage range from battery Input voltage range from battery Minimum input voltage from battery to start pump Line regulation (over VBAT range) 8 5 1.8 1.5 2.6 – – – – – – 5 – – 5.0 3.3 – – ΔVPUMP_Load Load regulation – 5 – ΔVPUMP_Ripple E3 FPUMP DCPUMP Output voltage ripple (depends on capacitor/load) Efficiency Switching frequency Switching duty cycle – 35 – – 100 50 1.3 50 – – – – Figure 8. Basic Switch Mode Pump Circuit D1 Vdd V PUMP L1 V BAT C1 SMP + Battery PSoC TM Vss Note 17. L1 = 2 uH inductor, C1 = 10 uF capacitor, D1 = Schottky diode. See Figure 8. Document Number: 001-48111 Rev. *I Page 41 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 DC Analog Reference Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. The guaranteed specifications for RefHI and RefLo are measured through the Analog Continuous Time PSoC blocks. The power levels for RefHi and RefLo refer to the Analog Reference Control register. AGND is measured at P2[4] in AGND bypass mode. Each Analog Continuous Time PSoC block adds a maximum of 10mV additional offset error to guaranteed AGND specifications from the local AGND buffer. Reference control power can be set to medium or high unless otherwise noted. Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling of the digital signal may appear on the AGND. Table 34. 5-V DC Analog Reference Specifications Reference ARF_CR [5:3] Reference Power Settings Symbol Reference Description Min Typ Max Units 0b000 RefPower = High VREFHI Opamp bias = High VAGND VREFLO RefPower = High VREFHI Opamp bias = Low VAGND VREFLO RefPower = VREFHI Medium Opamp bias = High V AGND VREFLO RefPower = VREFHI Medium Opamp bias = Low V AGND VREFLO Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low VDD/2 + Bandgap VDD/2 VDD/2 – Bandgap VDD/2 + Bandgap VDD/2 VDD/2 – Bandgap VDD/2 + Bandgap VDD/2 VDD/2 – Bandgap VDD/2 + Bandgap VDD/2 VDD/2 – Bandgap VDD/2 + 1.214 VDD/2 – 0.018 VDD/2 – 1.328 VDD/2 + 0.228 VDD/2 – 0.015 VDD/2 – 1.329 VDD/2 + 1.224 VDD/2 – 0.014 VDD/2 – 1.328 VDD/2 + 1.226 VDD/2 – 0.014 VDD/2 – 1.328 VDD/2 + 1.279 VDD/2 – 0.004 VDD/2 – 1.301 VDD/2 + 1.284 VDD/2 – 0.002 VDD/2 – 1.303 VDD/2 + 1.287 VDD/2 – 0.001 VDD/2 – 1.304 VDD/2 + 1.288 VDD/2 – 0.001 VDD/2 – 1.304 VDD/2 + 1.341 VDD/2 + 0.01 VDD/2 – 1.273 VDD/2 + 1.344 VDD/2 + 0.011 VDD/2 – 1.275 VDD/2 + 1.345 VDD/2 + 0.012 VDD/2 – 1.275 VDD/2 + 1.346 VDD/2 + 0.012 VDD/2 – 1.276 V V V V V V V V V V V V Note 18. AGND tolerance includes the offsets of the local buffer in the PSoC block. Document Number: 001-48111 Rev. *I Page 42 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Table 34. 5-V DC Analog Reference Specifications (continued) Reference ARF_CR [5:3] Reference Power Settings Symbol Reference Description Min Typ Max Units 0b001 RefPower = High VREFHI Opamp bias = High VAGND VREFLO RefPower = High VREFHI Opamp bias = Low VAGND VREFLO RefPower = VREFHI Medium Opamp bias = High V AGND VREFLO VREFHI RefPower = Medium Opamp bias = Low V AGND VREFLO Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low P2[4]+P2[6] (P2[4] = P2[4] + P2[6] P2[4] + P2[6] P2[4] + P2[6] VDD/2, P2[6] = 1.3 V) – 0.055 – 0.019 + 0.019 P2[4] P2[4] P2[4] P2[4] P2[4]–P2[6] (P2[4] = P2[4] – P2[6] P2[4] – P2[6] P2[4] – P2[6] + 0.005 + 0.035 VDD/2, P2[6] = 1.3 V) – 0.030 P2[4]+P2[6] (P2[4] = P2[4] + P2[6] P2[4] + P2[6] P2[4] + P2[6] – 0.015 + 0.021 VDD/2, P2[6] = 1.3 V) – 0.05 P2[4] P2[4] P2[4] P2[4] P2[4]–P2[6] (P2[4] = P2[4] – P2[6] P2[4] – P2[6] P2[4] – P2[6] VDD/2, P2[6] = 1.3 V) – 0.033 + 0.001 + 0.031 P2[4]+P2[6] (P2[4] = P2[4] + P2[6] P2[4] + P2[6] P2[4] + P2[6] VDD/2, P2[6] = 1.3 V) – 0.048 – 0.013 + 0.022 P2[4] P2[4] P2[4] P2[4] P2[4]–P2[6] (P2[4] = P2[4] – P2[6] P2[4] – P2[6] P2[4] – P2[6] VDD/2, P2[6] = 1.3 V) – 0.034 – 0.001 + 0.031 P2[4]+P2[6] (P2[4] = P2[4] + P2[6] P2[4] + P2[6] P2[4] + P2[6] VDD/2, P2[6] = 1.3 V) – 0.047 – 0.012 + 0.023 P2[4] P2[4] P2[4] P2[4] P2[4]–P2[6] (P2[4] = P2[4] – P2[6] P2[4] – P2[6] P2[4] – P2[6] – 0.002 + 0.030 VDD/2, P2[6] = 1.3 V) – 0.036 VDD VDD/2 VSS VDD VDD/2 VSS VDD VDD/2 VSS VDD VDD/2 VSS VDD – 0.028 VDD – 0.010 VDD/2 – VDD/2 – 0.014 0.002 VSS VSS + 0.004 VDD – 0.021 VDD – 0.007 VDD/2 – VDD/2 – 0.014 0.001 VSS VSS + 0.002 VDD – 0.019 VDD – 0.006 VDD/2 – VDD/2 – 0.014 0.001 VSS VSS + 0.002 VDD – 0.017 VDD – 0.005 VDD/2 – VDD/2 – 0.014 0.001 VSS VSS + 0.001 VDD VDD/2 + 0.012 VSS + 0.008 VDD VDD/2 + 0.012 VSS + 0.005 VDD VDD/2 + 0.012 VSS + 0.004 VDD VDD/2 + 0.013 VSS + 0.003 V – V V – V V – V V – V V V V V V V V V V V V V 0b010 RefPower = High VREFHI Opamp bias = High V AGND VREFLO RefPower = High VREFHI Opamp bias = Low V AGND VREFLO RefPower = VREFHI Medium V Opamp bias = High AGND VREFLO RefPower = VREFHI Medium V Opamp bias = Low AGND VREFLO Document Number: 001-48111 Rev. *I Page 43 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Table 34. 5-V DC Analog Reference Specifications (continued) Reference ARF_CR [5:3] Reference Power Settings Symbol Reference Description Min Typ Max Units 0b011 RefPower = High VREFHI Opamp bias = High V AGND VREFLO RefPower = High VREFHI Opamp bias = Low V AGND VREFLO VREFHI RefPower = Medium V Opamp bias = High AGND VREFLO VREFHI RefPower = Medium V Opamp bias = Low AGND VREFLO Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low 3 × Bandgap 2 × Bandgap Bandgap 3 × Bandgap 2 × Bandgap Bandgap 3 × Bandgap 2 × Bandgap Bandgap 3 × Bandgap 2 × Bandgap Bandgap 3.736 2.525 1.265 3.747 2.528 1.264 3.749 2.529 1.264 3.751 2.530 1.264 3.887 2.598 1.302 3.894 2.601 1.302 3.897 2.602 1.302 3.899 2.603 1.302 4.030 2.667 1.335 4.034 2.668 1.335 4.035 2.668 1.335 4.037 2.669 1.335 V V V V V V V V V V V V V V V V V V V V V V V V 0b100 RefPower = High VREFHI Opamp bias = High VAGND VREFLO RefPower = High VREFHI Opamp bias = Low VAGND VREFLO RefPower = VREFHI Medium Opamp bias = High V AGND VREFLO VREFHI RefPower = Medium Opamp bias = Low V AGND VREFLO 2 × Bandgap + P2[6] 2.483 – P2[6] 2.578 – P2[6] 2.669 – P2[6] (P2[6] = 1.3 V) 2 × Bandgap 2.525 2.598 2.666 2 × Bandgap – P2[6] 2.512 – P2[6] 2.602 – P2[6] 2.684 – P2[6] (P2[6] = 1.3 V) 2 × Bandgap + P2[6] 2.495 – P2[6] 2.586 – P2[6] 2.673 – P2[6] (P2[6] = 1.3 V) 2 × Bandgap 2.528 2.601 2.668 2 × Bandgap – P2[6] 2.510 – P2[6] 2.602 – P2[6] 2.685 – P2[6] (P2[6] = 1.3 V) 2 × Bandgap + P2[6] 2.498 – P2[6] 2.589 – P2[6] 2.674 – P2[6] (P2[6] = 1.3 V) 2 × Bandgap 2.529 2.601 2.668 2 × Bandgap – P2[6] 2.509 – P2[6] 2.601 – P2[6] 2.685 – P2[6] (P2[6] = 1.3 V) 2 × Bandgap + P2[6] 2.500 – P2[6] 2.591 – P2[6] 2.675 – P2[6] (P2[6] = 1.3 V) 2 × Bandgap 2.530 2.603 2.669 2 × Bandgap – P2[6] 2.508 – P2[6] 2.601 – P2[6] 2.686 – P2[6] (P2[6] = 1.3 V) Document Number: 001-48111 Rev. *I Page 44 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Table 34. 5-V DC Analog Reference Specifications (continued) Reference ARF_CR [5:3] Reference Power Settings Symbol Reference Description Min Typ Max Units 0b101 RefPower = High VREFHI Opamp bias = High VAGND VREFLO RefPower = High VREFHI Opamp bias = Low VAGND VREFLO RefPower = VREFHI Medium Opamp bias = High V AGND VREFLO VREFHI RefPower = Medium Opamp bias = Low V AGND VREFLO Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] – Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] – Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] – Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] – Bandgap (P2[4] = VDD/2) 2 × Bandgap Bandgap VSS 2 × Bandgap Bandgap VSS 2 × Bandgap Bandgap VSS 2 × Bandgap Bandgap VSS P2[4] + 1.218 P2[4] + 1.283 P2[4] + 1.344 P2[4] P2[4] P2[4] V – V V – V V – V V – V V V V V V V V V V V V V P2[4] – 1.329 P2[4] – 1.297 P2[4] – 1.265 P2[4] + 1.225 P2[4] + 1.287 P2[4] + 1.346 P2[4] P2[4] P2[4] P2[4] – 1.330 P2[4] – 1.301 P2[4] – 1.271 P2[4] + 1.226 P2[4] + 1.288 P2[4] + 1.346 P2[4] P2[4] P2[4] P2[4] – 1.330 P2[4] – 1.302 P2[4] – 1.272 P2[4] + 1.227 P2[4] + 1.289 P2[4] + 1.347 P2[4] P2[4] P2[4] P2[4] – 1.331 P2[4] – 1.303 P2[4] – 1.273 2.506 1.263 VSS 2.508 1.263 VSS 2.508 1.263 VSS 2.508 1.263 VSS 2.597 1.302 VSS + 0.006 2.595 1.302 VSS + 0.003 2.595 1.302 VSS + 0.002 2.596 1.302 VSS + 0.001 2.674 1.336 VSS + 0.014 2.675 1.336 VSS + 0.008 2.676 1.336 VSS + 0.005 2.677 1.336 VSS + 0.003 0b110 RefPower = High VREFHI Opamp bias = High V AGND VREFLO RefPower = High VREFHI Opamp bias = Low V AGND VREFLO RefPower = VREFHI Medium V Opamp bias = High AGND VREFLO RefPower = VREFHI Medium V Opamp bias = Low AGND VREFLO Document Number: 001-48111 Rev. *I Page 45 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Table 34. 5-V DC Analog Reference Specifications (continued) Reference ARF_CR [5:3] Reference Power Settings Symbol Reference Description Min Typ Max Units 0b111 RefPower = High VREFHI Opamp bias = High V AGND VREFLO RefPower = High VREFHI Opamp bias = Low V AGND VREFLO VREFHI RefPower = Medium V Opamp bias = High AGND VREFLO VREFHI RefPower = Medium V Opamp bias = Low AGND VREFLO Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low 3.2 × Bandgap 1.6 × Bandgap VSS 3.2 × Bandgap 1.6 × Bandgap VSS 3.2 × Bandgap 1.6 × Bandgap VSS 3.2 × Bandgap 1.6 × Bandgap VSS 4.056 2.012 VSS 4.061 2.023 VSS 4.063 2.020 VSS 4.061 2.026 VSS 4.155 2.083 VSS + 0.01 4.153 2.082 VSS + 0.006 4.154 2.083 VSS + 0.006 4.154 2.081 VSS + 0.004 4.222 2.168 VSS + 0.035 4.223 2.145 VSS + 0.022 4.224 2.152 VSS + 0.024 4.225 2.140 VSS + 0.017 V V V V V V V V V V V V Table 35. 3.3-V DC Analog Reference Specifications Reference Reference Power ARF_CR Settings [5:3] 0b000 Symbol Reference Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Description VDD/2 + Bandgap VDD/2 VDD/2 – Bandgap VDD/2 + Bandgap VDD/2 VDD/2 – Bandgap VDD/2 + Bandgap VDD/2 VDD/2 – Bandgap VDD/2 + Bandgap VDD/2 VDD/2 – Bandgap Min VDD/2 + 1.223 VDD/2 – 0.013 VDD/2 – 1.322 VDD/2 + 1.228 VDD/2 – 0.008 VDD/2 – 1.322 VDD/2 + 1.232 VDD/2 – 0.008 VDD/2 – 1.322 VDD/2 + 1.233 VDD/2 – 0.006 VDD/2 – 1.322 Typ VDD/2 + 1.283 VDD/2 – 0.003 VDD/2 – 1.297 VDD/2 + 1.288 VDD/2 – 0.002 VDD/2 – 1.298 VDD/2 + 1.290 VDD/2 – 0.001 VDD/2 – 1.299 VDD/2 + 1.291 VDD/2 VDD/2 – 1.299 Max Units RefPower = High VREFHI Opamp bias = High VAGND VREFLO RefPower = High VREFHI Opamp bias = Low VAGND VREFLO RefPower = VREFHI Medium VAGND Opamp bias = High VREFLO RefPower = VREFHI Medium VAGND Opamp bias = Low VREFLO VDD/2 + 1.343 V VDD/2 + 0.005 V VDD/2 – 1.270 V VDD/2 + 1.345 V VDD/2 + 0.005 V VDD/2 – 1.271 V VDD/2 + 1.346 V VDD/2 + 0.006 V VDD/2 – 1.272 V VDD/2 + 1.347 V VDD/2 + 0.006 V VDD/2 – 1.272 V Document Number: 001-48111 Rev. *I Page 46 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Table 35. 3.3-V DC Analog Reference Specifications (continued) Reference Reference Power ARF_CR Settings [5:3] 0b001 Symbol Reference Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low – Description P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) VDD VDD/2 VSS VDD VDD/2 VSS VDD VDD/2 VSS VDD VDD/2 VSS – Min Typ Max Units RefPower = High VREFHI Opamp bias = High VAGND VREFLO RefPower = High VREFHI Opamp bias = Low VAGND VREFLO RefPower = VREFHI Medium Opamp bias = High VAGND VREFLO RefPower = VREFHI Medium Opamp bias = Low VAGND VREFLO P2[4] + P2[6] – P2[4] + P2[6] – 0.045 0.017 P2[4] P2[4] – P2[6] – 0.019 P2[4] P2[4] – P2[6] + 0.004 P2[4] + P2[6] + V 0.016 P2[4] – P2[4] – P2[6] + V 0.023 P2[4] + P2[6] + V 0.013 P2[4] – P2[4] – P2[6] + V 0.021 P2[4] + P2[6] + V 0.013 P2[4] – P2[4] – P2[6] + V 0.016 P2[4] + P2[6] + V 0.014 P2[4] – P2[4] – P2[6] + V 0.020 VDD V VDD/2 + 0.031 V VSS + 0.0165 V V VDD VSS + 0.012 VDD VSS + 0.014 VDD VSS + 0.012 – V V V V V V – VDD/2 + 0.028 V P2[4] + P2[6] – P2[4] + P2[6] – 0.036 0.012 P2[4] P2[4] – P2[6] – 0.021 P2[4] P2[4] – P2[6] – 0.001 P2[4] + P2[6] – P2[4] + P2[6] – 0.034 0.011 P2[4] P2[4] – P2[6] – 0.023 P2[4] P2[4] – P2[6] – 0.002 P2[4] + P2[6] – P2[4] + P2[6] – 0.033 0.009 P2[4] P2[4] – P2[6] – 0.024 VDD – 0.042 VDD/2 – 0.035 VSS VDD – 0.035 VDD/2 – 0.031 VSS VDD – 0.044 VDD/2 – 0.052 VSS VDD – 0.036 VDD/2 – 0.032 VSS – P2[4] P2[4] – P2[6] – 0.003 VDD – 0.008 VDD/2 – 0.001 VSS + 0.003 VDD – 0.005 VDD/2 – 0.001 VSS + 0.002 VDD – 0.005 VDD/2 VSS + 0.002 VDD – 0.004 VDD/2 VSS + 0.001 – 0b010 RefPower = High VREFHI Opamp bias = High VAGND VREFLO RefPower = High VREFHI Opamp bias = Low VAGND VREFLO RefPower = VREFHI Medium VAGND Opamp bias = High VREFLO RefPower = VREFHI Medium Opamp bias = Low VAGND VREFLO VDD/2 + 0.046 V VDD/2 + 0.029 V 0b011 All power settings. Not allowed for 3.3 V. All power settings. Not allowed for 3.3 V. – 0b100 – – – – – – – Document Number: 001-48111 Rev. *I Page 47 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 Table 35. 3.3-V DC Analog Reference Specifications (continued) Reference Reference Power ARF_CR Settings [5:3] 0b101 Symbol Reference Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low Ref high AGND Ref low – Description P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] – Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] – Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] – Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] – Bandgap (P2[4] = VDD/2) 2 × Bandgap Bandgap VSS 2 × Bandgap Bandgap VSS 2 × Bandgap Bandgap VSS 2 × Bandgap Bandgap VSS – Min P2[4] + 1.226 P2[4] P2[4] – 1.323 P2[4] + 1.232 P2[4] P2[4] – 1.324 P2[4] + 1.233 P2[4] P2[4] – 1.324 P2[4] + 1.234 P2[4] P2[4] – 1.324 2.504 1.262 VSS 2.506 1.262 VSS 2.506 1.262 VSS 2.507 1.262 VSS – Typ P2[4] + 1.286 P2[4] P2[4] – 1.293 P2[4] + 1.29 P2[4] P2[4] – 1.296 P2[4] + 1.291 P2[4] P2[4] – 1.298 P2[4] + 1.292 P2[4] P2[4] – 1.299 2.595 1.301 VSS + 0.006 2.593 1.301 VSS + 0.003 2.594 1.301 VSS + 0.002 2.595 1.301 VSS + 0.001 – Max Units RefPower = High VREFHI Opamp bias = High VAGND VREFLO RefPower = High VREFHI Opamp bias = Low VAGND VREFLO RefPower = VREFHI Medium Opamp bias = High VAGND VREFLO RefPower = VREFHI Medium Opamp bias = Low VAGND VREFLO P2[4] + 1.343 V P2[4] P2[4] –1.262 – V P2[4] + 1.344 V P2[4] – P2[4] – 1.267 V P2[4] + 1.345 V P2[4] – P2[4] – 1.269 V P2[4] +1.345 P2[4] V – P2[4] – 1.270 V 2.672 1.336 VSS + 0.013 2.674 1.336 VSS + 0.008 2.675 1.335 VSS + 0.007 2.675 1.335 VSS + 0.005 – V V V V V V V V V V V V – 0b110 RefPower = High VREFHI Opamp bias = High VAGND VREFLO RefPower = High VREFHI Opamp bias = Low VAGND VREFLO RefPower = VREFHI Medium Opamp bias = High VAGND VREFLO RefPower = VREFHI Medium Opamp bias = Low VAGND VREFLO 0b111 All power settings. Not allowed for 3.3 V. – DC Analog PSoC Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 36. DC Analog PSoC Block Specifications Symbol RCT CSC Description Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switch Cap) Min – – Typ 12.24 80 Max – – Units kΩ fF Notes Document Number: 001-48111 Rev. *I Page 48 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 DC Analog Mux Bus Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 37. DC Analog Mux Bus Specifications Symbol RSW RVSS Description Switch Resistance to Common Analog Bus Resistance of Initialization Switch to VSS Min – – Typ – – Max 400 800 Units Ω Ω Notes VDD ≥ 3.0 V DC SAR10 ADC Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 38. DC SAR10 ADC Specifications Symbol INLSAR10 DNLSAR10 ISAR10 IVREFSAR10 VVREFSAR10 Description Integral nonlinearity for VREF ≥ 3 V Integral nonlinearity for VREF < 3 V Differential nonlinearity for VREF ≥ 3 V Differential nonlinearity for VREF > 3 V Active current consumption Input current into P2[5] when configured as the SAR10 ADC's VREF input. Input reference voltage at P2[5] when configured as the SAR10 ADC's external voltage reference. Min –2.5 –5 –1.5 –4 0.08 – 2.7 Typ – – – – 0.5 – – Max 2.5 5 1.5 4 0.497 0.5 VDD – 0.3 V Units LSB LSB LSB LSB mA mA V Notes 10-bit resolution 10-bit resolution 10-bit resolution 10-bit resolution The internal voltage reference buffer is disabled in this configuration. When VREF is buffered inside the SAR10 ADC, the voltage level at P2[5] (when configured as the external reference voltage) must always be at least 300 mV less than the chip supply voltage level on the VDD pin. (VVREFSAR10 < (VDD – 300 mV)). Frequency dependant = 1/ Fs °C. 142.9 kHz (maximum) and Cin = 4.28 pF (typical) VOSSAR10 SARIMP Offset voltage SAR input impedence 5 – 7.7 1.64 10 – mV MΩ Table 39. DC IDAC Specifications Symbol IDAC_DNL IDAC_INL IDAC_Gain Description Differential nonlinearity Integral nonlinearity Gain per bit – Range 1 (91 µA) Gain per bit – Range 2 (318 µA) Gain per bit – Range 3 (637 µA) IDACOffset Offset at Code 0 vs LSB Ideal – Range 1 (91 µA) Offset at Code 0 vs LSB Ideal – Range 2 (318 µA) Offset at Code 0 vs LSB Ideal – Range 3 (637 µA) Min –5.0 –5.0 283 985 1959 Typ 2.0 2.0 357 1250 2500 2.0% 1.0% 1.0% Max 5.0 5.0 447 1532 3056 20% 10% 10% Units LSB LSB nA nA nA % % % Measured as a % of LSB (Current @ Code 0)/(LSB Ideal Current) Notes Valid for all 3 current ranges Valid for all 3 current ranges Measured at full scale Document Number: 001-48111 Rev. *I Page 49 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. See the PSoC Technical Reference Manual for CY8C28xxx PSoC devices, for more information on the VLT_CR register. Table 40. DC POR and LVD Specifications Symbol VPPOR0R VPPOR1R VPPOR2R VPPOR0 VPPOR1 VPPOR2 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 Description VDD Value for PPOR Trip (positive ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b VDD Value for PPOR Trip (negative ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b PPOR Hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b VDD Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b VDD Value for PUMP Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min – – – – – – – – – 2.83 2.93 3.04 3.90 4.38 4.54 4.62 4.71 2.93 3.00 3.16 4.09 4.53 4.61 4.70 4.88 Typ 2.91 4.39 4.55 2.82 4.39 4.55 92 0 0 2.91 3.01 3.12 3.99 4.47 4.63 4.71 4.80 3.01 3.08 3.24 4.17 4.62 4.71 4.80 4.98 Max 2.985 4.49 4.65 2.90 4.49 4.64 – – – 3.00[19] 3.10 3.21 4.09 4.58 4.74[20] 4.83 4.92 3.10 3.17 3.33 4.28 4.74 4.82 4.91 5.10 Units V V V V V V mV mV mV V V V V V V V V V V V V V V V V Notes VDD must be greater than or equal to 2.5 V during startup, reset from the XRES pin, or reset from Watchdog. VDD must be greater than or equal to 2.5 V during startup, reset from the XRES pin, or reset from Watchdog. Notes 19. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. 20. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply. Document Number: 001-48111 Rev. *I Page 50 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 41. DC Programming Specifications Symbol VDDP Description VDD for programming and erase Min 4.5 Typ 5 Max 5.5 Units Notes V This specification applies to the functional requirements of external programmer tools. V This specification applies to the functional requirements of external programmer tools. V This specification applies to the functional requirements of external programmer tools. V This specification applies to this device when it is executing internal flash writes. mA V V mA mA V V – – Erase/write cycles per block. Erase/write cycles. Must be programmed and read at the same voltage to meet this. Driving internal pull-down resistor. Driving internal pull-down resistor. VDDLV Low VDD for verify 3 3.1 3.2 VDDHV High VDD for verify 5.1 5.2 5.3 VDDIWRITE Supply Voltage for Flash write operation 3 – 5.25 IDDP VILP Supply Current During Programming or Verify Input Low Voltage During Programming or Verify VIHP Input High Voltage During Programming or Verify IILP Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify IIHP Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify VOLV Output Low Voltage During Programming or Verify VOHV Output High Voltage During Programming or Verify FlashENPB Flash Endurance (per block) FlashENT Flash Endurance (total)[22] – – 2.2 – – – VDD – 1.0 50,000[21] 1,800,000 5 – – – – – – – – 25 0.8 – 0.21 1.5 0.75 VDD – – FlashDR Flash Data Retention 10 – – Years Notes 21. The 50,000 cycle Flash endurance per block will only be guaranteed if the Flash is operating within one voltage range. Voltage ranges are 3.0 V to 3.6 V and 4.75 V to 5.25 V. 22. A maximum of 36 × 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. Document Number: 001-48111 Rev. *I Page 51 of 78 CY8C28243, CY8C28403, CY8C28413 CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645 DC I2C Specifications Table 42 lists the guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 42. DC I2C Specifications[23] Symbol VILI2C VIHI2C Description Input low level Input high level Min – – 0.7 × VDD Typ Max – 0.3 × VDD – 0.25 × VDD – – Units V V V Notes 3.0 V ≤ VDD ≤ 3.6 V 4.75 V ≤ VDD ≤ 5.25 V 3.0 V ≤ VDD ≤ 5.25 V AC Electrical Characteristics AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 43. AC Chip-Level Specifications Symbol FIMO FIMO6 FCPU1 FCPU2 FBLK5 FBLK33 F32K1 F32K2 F32K_U Description Internal Main Oscillator Frequency Internal Main Oscillator Frequency for 6 MHz CPU Frequency (5 V Nominal) CPU Frequency (3.3 V Nominal) Digital PSoC Block Frequency Digital PSoC Block Frequency Internal Low Speed Oscillator Frequency External Crystal Oscillator Internal Low Speed Oscillator Untrimmed Frequency Min 23.4 Typ 24 Max 24.6[24] Units MHz Notes Trimmed. Utilizing factory trim values. SLIMO Mode = 0. Trimmed for 5 V or 3.3 V operation using factory trim values. SLIMO Mode = 1. Trimmed. Utilizing factory trim values. SLIMO mode = 0. Trimmed. Utilizing factory trim values. SLIMO mode = 0. 4.75 V< VDD