CY8C29466_11

CY8C29466, CY8C29566 CY8C29666, CY8C29866 PSoC® Programmable System-on-Chip™ PSoC® Programmable System-on-Chip Features ■ Powerful Harvard-architecture processor ❐ M8C processor speeds to 24 MHz ❐ Two 8 × 8 multiply, 32-bit accumulate ❐ Low power at high speed ❐ Operating voltage: 3.0 V to 5.25 V ❐ Operating voltages down to 1.0 V using on-chip switch mode pump (SMP) ❐ Industrial temperature range: –40 °C to +85 °C Advanced peripherals (PSoC® blocks) ❐ 12 rail-to-rail analog PSoC blocks provide: • Up to 14-bit analog-to-digital converters (ADCs) • Up to 9-bit digital-to-analog converters (DACs) • Programmable gain amplifiers (PGAs) • Programmable filters and comparators ❐ 16 digital PSoC blocks provide: • 8- to 32-bit timers, counters, and pulse-width modulators (PWMs) • Cyclical redundancy check (CRC) and pseudo random sequence (PRS) modules • Up to four full-duplex universal asynchronous receiver transmitters (UARTs) • Multiple serial peripheral interface (SPI) masters or slaves • Can connect to all general-purpose I/O (GPIO) pins ❐ Create complex peripherals by combining blocks Precision, programmable clocking ❐ Internal ±2.5% 24- / 48-MHz main oscillator ❐ 24- / 48-MHz with optional 32.768 kHz crystal ❐ Optional external oscillator, up to 24 MHz ❐ Internal oscillator for watchdog and sleep Flexible on-chip memory ❐ 32 KB flash program storage 50,000 erase/write cycles ❐ 2 KB static random access memory (SRAM) data storage ❐ In-system serial programming (ISSP) ❐ Partial flash updates ❐ Flexible protection modes ❐ Electrically erasable programmable read-only memory (EEPROM) emulation in flash Programmable pin configurations ❐ 25-mA sink, 10-mA source on all GPIOs ❐ Pull-up, pull-down, high Z, strong, or open-drain drive modes on all GPIOs ❐ Eight standard analog inputs on GPIOs, plus four additional analog inputs with restricted routing ❐ Four 40 mA analog outputs on GPIOs ❐ Configurable interrupt on all GPIOs ■ Additional system resources 2 ❐ I C slave, master, and multi-master to 400 kHz ❐ Watchdog and sleep timers ❐ User-configurable low-voltage detection (LVD) ❐ Integrated supervisory circuit ❐ On-chip precision voltage reference Complete development tools ❐ Free development software (PSoC Designer™) ❐ Full-featured in-circuit emulator (ICE) and programmer ❐ Full-speed emulation ❐ Complex breakpoint structure ❐ 128 KB trace memory ❐ Complex events ❐ C compilers, assembler, and linker ■ ■ Logic Block Diagram Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 with Analog Drivers PSoC CORE System Bus ■ Global Digital Interconnect SRAM 2 KB Interrupt Controller Global Analog Interconnect Flash 32KB Sleep and Watchdog SROM CPU Core (M8C) ■ Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) DIGITAL SYSTEM Digital Block Array ANALOG SYSTEM Analog Ref. Analog Block Array ■ Analog Input Muxing Digital Clocks Multiply Accum. POR and LVD Decimator I2 C System Resets Internal Voltage Ref. Switch Mode Pump SYSTEM RESOURCES Cypress Semiconductor Corporation Document Number: 38-12013 Rev. *S • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised July 7, 2011 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Contents PSoC Programmable System-on-Chip ........................... 1 Features ............................................................................. 1 Logic Block Diagram ........................................................ 1 PSoC Functional Overview .............................................. 3 PSoC Core .................................................................. 3 Digital System ............................................................. 3 Analog System ............................................................ 4 Additional System Resources ..................................... 5 PSoC Device Characteristics ...................................... 5 Getting Started .................................................................. 6 Application Notes ........................................................ 6 Development Kits ........................................................ 6 Training ....................................................................... 6 CYPros Consultants .................................................... 6 Solutions Library .......................................................... 6 Technical Support ....................................................... 6 Development Tools .......................................................... 6 PSoC Designer Software Subsystems ........................ 6 Designing with PSoC Designer ....................................... 7 Select User Modules ................................................... 7 Configure User Modules .............................................. 7 Organize and Connect ................................................ 7 Generate, Verify, and Debug ....................................... 7 Pinouts .............................................................................. 8 28-Pin Part Pinout ....................................................... 8 44-Pin Part Pinout ....................................................... 9 48-Pin Part Pinout ..................................................... 10 100-Pin Part Pinout ................................................... 12 100-Pin Part Pinout (On-Chip Debug) ....................... 14 Register Reference ......................................................... 16 Register Conventions ................................................ 16 Register Mapping Tables .......................................... 16 Electrical Specifications ................................................ 19 Absolute Maximum Ratings ....................................... 19 Operating Temperature ............................................ 20 DC Electrical Characteristics ..................................... 20 AC Electrical Characteristics ..................................... 35 Packaging Information ................................................... 44 Packaging Dimensions .............................................. 44 Thermal Impedances ................................................ 49 Capacitance on Crystal Pins .................................... 49 Solder Reflow Specifications ..................................... 49 Development Tool Selection ......................................... 50 Software .................................................................... 50 Development Kits ...................................................... 50 Evaluation Tools ........................................................ 50 Device Programmers ................................................. 51 Accessories (Emulation and Programming) ................ 51 Ordering Information ...................................................... 52 Ordering Code Definitions ......................................... 52 Acronyms ........................................................................ 53 Acronyms Used ......................................................... 53 Reference Documents .................................................... 53 Document Conventions ............................................. 54 Units of Measure ....................................................... 54 Numeric Conventions ................................................ 54 Glossary .......................................................................... 54 Document History Page ................................................ 59 Sales, Solutions, and Legal Information ...................... 61 Worldwide Sales and Design Support ....................... 61 Products .................................................................... 61 PSoC Solutions ......................................................... 61 Document Number: 38-12013 Rev. *S Page 2 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 PSoC Functional Overview The PSoC family consists of many Programmable System-on-Chip controller devices. These devices are designed to replace multiple traditional microcontroller unit (MCU)-based system components with one, low-cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, as well as programmable interconnects. This architecture allows you to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast central processing unit (CPU), flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts and packages. The PSoC architecture, as illustrated in the Logic Block Diagram on page 1, consists of four main areas: PSoC core, digital system, analog system, and system resources. Configurable global busing allows all of the device resources to be combined into a complete custom system. The PSoC CY8C29x66 family can have up to five I/O ports that connect to the global digital and analog interconnects, providing access to 8 digital blocks and 12 analog blocks. selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. Digital System The digital system is composed of 16 digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are called user modules. Figure 1. Digital System Block Diagram Port7 Port6 Port5 Port4 Port3 Port2 Port1 Port0 Digital Clocks From Core To System Bus To Analog System PSoC Core The PSoC core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIOs. The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a 4 million instructions per second (MIPS) 8-bit Harvard-architecture microprocessor. The CPU uses an interrupt controller with 17 vectors, to simplify programming of real-time embedded events. Program execution is timed and protected using the included sleep and watchdog timers (WDT). Memory uses 16 KB of flash for program storage, 256 bytes of SRAM for data storage, and up to 2 KB of EEPROM emulated using the flash. Program flash uses four protection levels on blocks of 64 bytes, allowing customized software information protection (IP). The PSoC device incorporates flexible internal clock generators, including a 24 MHz internal main oscillator (IMO) accurate to 2.5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low-power 32 kHz internal low speed oscillator (ILO) is provided for the sleep timer and WDT. If crystal accuracy is desired, the 32.768 kHz external crystal oscillator (ECO) is available for use as a real-time clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a system resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. PSoC GPIOs provide connection to the CPU, and digital and analog resources of the device. Each pin’s drive mode may be DIGITAL SYSTEM Digital PSoC Block Array Row Input Configuration Row0 DBB00 DBB01 DCB02 4 DCB03 4 Row Output Configuration 8 8 Row Input Configuration 8 Row1 DBB10 DBB11 DCB12 4 DCB13 4 8 Row Output Configuration Row Input Configuration Row2 DBB20 DBB21 DCB22 4 DCB23 4 Row Output Configuration Row Input Configuration Row3 DBB30 DBB31 DCB32 4 DCB33 4 Row Output Configuration GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] Document Number: 38-12013 Rev. *S Page 3 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Digital peripheral configurations include: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ DTMF Dialer Modulators Correlators Peak detectors Many other topologies possible PWMs (8- to 32-bit) PWMs with dead band (8- to 32-bit) Counters (8- to 32-bit) Timers (8- to 32-bit) UART 8-bit with selectable parity (up to 2) SPI slave and master (up to 2) I2C slave and multi-master (one available as a system resource) CRC generator (8- to 32-bit) IrDA (up to 2) PRS generators (8- to 32-bit) Analog blocks are provided in columns of three, which includes one continuous time (CT) and two switched capacitor (SC) blocks, as shown in Figure 2. Figure 2. Analog System Block Diagram P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6] P0[4] P0[2] P0[0] P2[6] The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows you the optimum choice of system resources for your application. Family resources are shown in the table titled “PSoC Device Characteristics” on page 5. P2[3] P2[4] P2[2] P2[0] P2[1] Analog System The analog system is composed of 12 configurable blocks, each containing an opamp circuit that allows the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are: ■ ■ ■ ■ ■ ■ ■ ■ ■ ACI0[1:0] Array Input Configuration ACI1[1:0] ACI2[1:0] ACI3[1:0] Block Array A CB00 ASC10 ASD20 ACB01 ASD11 ASC21 ACB02 ASC12 ASD22 ACB03 ASD13 ASC23 ADCs (up to 4, with 6- to 14-bit resolution; selectable as incremental, delta sigma, and SAR) Filters (2-, 4-, 6-, and 8-pole band pass, low pass, and notch) Amplifiers (up to 4, with selectable gain to 48x) Instrumentation amplifiers (up to 2, with selectable gain to 93x) Comparators (up to 4, with 16 selectable thresholds) DACs (up to 4, with 6-bit to 9-bit resolution) Multiplying DACs (up to 4, with 6-bit to 9-bit resolution) High current output drivers (four with 30-mA drive as a core resource) 1.3-V reference (as a system resource) Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 38-12013 Rev. *S Page 4 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Additional System Resources System resources, some of which were previously listed, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, switch mode pump, low-voltage detection, and power-on-reset (POR). ■ ■ ■ Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. Multiply accumulate (MAC) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in general math and digital filters. The decimator provides a custom hardware filter for digital signal processing applications including the creation of delta sigma ADCs. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. ■ LVD interrupts can signal the application of falling voltage levels, while the advanced POR circuit eliminates the need for a system supervisor. ■ An internal 1.3 V reference provides an absolute reference for the analog system, including ADCs and DACs. ■ An integrated switch-mode pump (SMP) generates normal operating voltages from a single 1.2 V battery cell, providing a low cost boost converter. ■ PSoC Device Characteristics Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. The following table lists the resources available for specific PSoC device groups.The PSoC device covered by this datasheet is highlighted. Table 1. PSoC Device Characteristics PSoC Part Number CY8C29x66 CY8C28xxx CY8C27x43 CY8C24x94 CY8C24x23A CY8C23x33 CY8C22x45 CY8C21x45 CY8C21x34 CY8C21x23 CY8C20x34 CY8C20xx6 Digital I/O up to 64 up to 44 up to 44 up to 56 up to 24 up to 26 up to 38 up to 24 up to 28 up to 16 up to 28 up to 36 Digital Rows 4 up to 3 2 1 1 1 2 1 1 1 0 0 Digital Blocks 16 up to 12 8 4 4 4 8 4 4 4 0 0 Analog Inputs up to 12 up to 44 up to 12 up to 48 up to 12 up to 12 up to 38 up to 24 up to 28 up to 8 up to 28 up to 36 Analog Outputs 4 up to 4 4 2 2 2 0 0 0 0 0 0 Analog Columns 4 up to 6 4 2 2 2 4 4 2 2 0 0 Analog Blocks 12 up to 12 + 4[1] 12 6 6 4 6[1] 6[1] 4 [1] SRAM Size 2K 1K 256 1K 256 256 1K 512 512 256 512 up to 2 K Flash Size 32 K 16 K 16 K 16 K 4K 8K 16 K 8K 8K 4K 8K up to 32 K 4[1] 3[1,2] 3[1,2] Notes 1. Limited analog functionality. 2. Two analog blocks and one CapSense®. Document Number: 38-12013 Rev. *S Page 5 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Getting Started For in depth information, along with detailed programming details, see the PSoC® Technical Reference Manual. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device datasheets on the web. CYPros Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to the CYPros Consultants web site. Application Notes Cypress application notes are an excellent introduction to the wide variety of possible PSoC designs. Solutions Library Visit our growing library of solution focused designs. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Development Kits PSoC Development Kits are available online from and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Technical Support Technical support – including a searchable Knowledge Base articles and technical forums – is also available online. If you cannot find an answer to your question, call our Technical Support hotline at 1-800-541-4736. Training Free PSoC technical training (on demand, webinars, and workshops), which is available online via www.cypress.com, covers a wide variety of topics and skill levels to assist you in your designs. Development Tools PSoC Designer™ is the revolutionary Integrated Design Environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes: ■ ■ ■ ■ ■ ■ ■ PSoC Designer Software Subsystems Design Entry In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use the PSoC blocks, which are called user modules. Examples of user modules are analog-to-digital converters (ADCs), digital-to-analog converters (DACs), amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this allows you to use more than 100 percent of PSoC's resources for an application. Code Generation Tools The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. You can develop your design in C, assembly, or a combination of the two. Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration Extensive user module catalog Integrated source-code editor (C and assembly) Free C compiler with no size restrictions or time limits Built-in debugger In-circuit emulation Built-in support for communication interfaces: 2 ❐ Hardware and software I C slaves and masters ❐ Full-speed USB 2.0 ❐ Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7. Document Number: 38-12013 Rev. *S Page 6 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Debugger PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows you to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer. In-Circuit Emulator A low-cost, high-functionality In-Circuit Emulator (ICE) is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24 MHz) operation. Designing with PSoC Designer The development process for the PSoC® device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is summarized in four steps: 1. Select User Modules. 2. Configure user modules. 3. Organize and connect. 4. Generate, verify, and debug. Organize and Connect You build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. You perform the selection, configuration, and routing so that you have complete control over all on-chip resources. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, you perform the “Generate Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides application programming interfaces (APIs) with high-level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. A complete code development environment allows you to develop and customize your applications in either C, assembly language, or both. The last step in the development process takes place inside PSoC Designer’s debugger (access by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations and external signals. Select User Modules PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called “user modules.” User modules make selecting and implementing peripheral devices, both analog and digital, simple. Configure User Modules Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a pulse width modulator (PWM) User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the internal operation of the user module and provide performance specifications. Each datasheet describes the use of each user module parameter, and other information you may need to successfully implement your design. Document Number: 38-12013 Rev. *S Page 7 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Pinouts The CY8C29x66 PSoC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O. However, VSS, VDD, SMP, and XRES are not capable of Digital I/O. 28-Pin Part Pinout Table 2. 28-Pin Part Pinout (PDIP, SSOP, SOIC) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 I/O I/O I/O I/O I/O I/O I/O I/O Power I I/O I/O I I/O I/O I/O I/O Input I I I/O I/O I/O I/O Power Type Digital I/O I/O I/O I/O I/O I/O I/O I/O Power I I Analog I I/O I/O I Pin Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] SMP P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD Active high external reset with internal pull-down Direct switched capacitor block input Direct switched capacitor block input External analog ground (AGND) External voltage reference (VREF) Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Supply voltage Optional external clock input (EXTCLK) Crystal (XTALin), I2C Serial Clock (SCL), ISSP-SCLK[3] Ground connection Crystal (XTALout), I2C Serial Data (SDA), ISSP-SDATA[3] Direct switched capacitor block input Direct switched capacitor block input Switch mode pump (SMP) connection to external components required I2C serial clock (SCL) I2C serial data (SDA) Description Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Figure 3. CY8C29466 28-Pin PSoC Device A, I, P0[7] A, IO, P0[5] A, IO, P0[3] A, I, P0[1] P2[7] P2[5] A, I, P2[3] A, I, P2[1] SMP I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 PDIP SSOP SOIC 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6], External VREF P2[4], External AGND P2[2], A, I P2[0], A, I XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2CSDA LEGEND: A = Analog, I = Input, and O = Output. Note 3. These are the ISSP pins, which are not High Z at Power On Reset (POR). See the PSoC Programmable System-on-Chip Technical Reference Manual for details. Document Number: 38-12013 Rev. *S Page 8 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 44-Pin Part Pinout Table 3. 44-Pin Part Pinout (TQFP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power I I/O I/O I I I/O I/O I I I I/O I/O I/O I/O I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O Power Type Digital I/O I/O I/O I/O I/O I/O I/O Power I I Analog Pin Name P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] P1[6] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD P0[7] P0[5] P0[3] P0[1] P2[7] Direct switched capacitor block input Direct switched capacitor block input External analog ground (AGND) External voltage reference (VREF) Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Supply voltage Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Active high external reset with internal pull-down Optional EXTCLK Crystal (XTALin), I2C SCL, ISSP-SCLK[4] Ground connection Crystal (XTALout), I2C SDA, ISSP-SDATA[4] I2C SCL I2C SDA Switch mode pump (SMP) connection to external components required Direct switched capacitor block input Direct switched capacitor block input Description Figure 4. CY8C29566 44-Pin PSoC Device P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6], External VREF 33 P2[4], External AGND 32 P2[2], A, I 31 P2[0], A, I 30 P4[6] 29 P4[4] 28 P4[2] 27 P4[0] 26 XRES 25 P3[6] 24 P3[4] 23 P3[2] LEGEND: A = Analog, I = Input, and O = Output. Note 4. These are the ISSP pins, which are not High Z at POR. See the PSoC Programmable System-on-Chip Technical Reference Manual for details. Document Number: 38-12013 Rev. *S P3[1] I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] VSS I2CSDA, XTALout, P1[0] P1[2] EXTCLK, P1[4] P1[6] P3[0] 12 13 14 15 16 17 18 19 20 21 22 P2[5] A, I, P2[3] A, I, P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] 1 2 3 4 5 6 7 8 9 10 11 44 43 42 41 40 39 38 37 36 35 34 P2[7] P0[1], A, I P0[3], A, IO P0[5], A, IO P0[7], A, I VDD TQFP Page 9 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 48-Pin Part Pinout Table 4. 48-Pin Part Pinout (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power I I/O I/O I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Type Digital I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power I I Analog I I/O I/O I Pin Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD Direct switched capacitor block input Direct switched capacitor block input External Analog Ground (AGND) External Voltage Reference (VREF) Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Supply voltage Active high external reset with internal pull-down Optional EXTCLK Crystal (XTALin), I2C SCL, ISSP-SCLK[5] Ground connection Crystal (XTALout), I2C SDA, ISSP-SDATA[5] I2C SCL I2C SDA Switch mode pump (SMP) connection to external components required Direct switched capacitor block input Direct switched capacitor block input Description Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Figure 5. CY8C29666 48-Pin PSoC Device A, I, P0[7] A, IO, P0[5] A, IO, P0[3] A, I, P0[1] P2[7] P2[5] A, I, P2[3] A, I, P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDD P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6], External VREF P2[4], External AGND P2[2], A, I P2[0], A, I P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] P5[2] P5[0] P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA LEGEND: A = Analog, I = Input, and O = Output. Note 5. These are the ISSP pins, which are not High Z at POR. See the PSoC Programmable System-on-Chip Technical Reference Manual for details. Document Number: 38-12013 Rev. *S Page 10 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Table 5. 48-Pin Part Pinout (QFN)[7] Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power I I/O I/O I I I/O I/O I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Type Digital I/O I/O I/O I/O I/O I/O Power Analog I I Pin Name P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] VSS P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] Direct switched capacitor block input Direct switched capacitor block input External analog ground (AGND) External voltage reference (VREF) Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Supply voltage Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Active high external reset with internal pull-down Optional EXTCLK Crystal (XTALin), I2C SCL, ISSP-SCLK[6] Ground connection Crystal (XTALout), I2C SDA, ISSP-SDATA[6] I2C SCL I2C SDA Switch mode pump (SMP) connection to external components required Description Direct switched capacitor block input Direct switched capacitor block input Figure 6. CY8C29666 48-Pin PSoC Device P2[5] P2[7] P0[1], A, I P0[3], A, IO P0[5], A, IO P0[7], A, I VDD P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6], External VREF 48 47 46 45 44 43 42 41 40 39 38 37 13 14 I2C SDA, P1[5] 15 P1[3] 16 I2C SCL, XTALin, P1[1] 17 VSS 18 I2C SDA, XTALout, P1[0] 19 P1[2] 20 EXTCLK, P1[4] 21 P1[6] 22 P5[0] 23 P5[2] 24 A, I, P2[3] A, I, P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] 1 2 3 4 5 6 7 8 9 10 11 12 QFN (Top View) 36 35 34 33 32 31 30 29 28 27 26 25 P2[4], External AGND P2[2], A, I P2[0], A, I P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] LEGEND: A = Analog, I = Input, and O = Output. Notes 6. These are the ISSP pins, which are not High Z at POR. See the PSoC Programmable System-on-Chip Technical Reference Manual for details. 7. The QFN package has a center pad that must be connected to ground (VSS). Document Number: 38-12013 Rev. *S P5[1] I2C SCL, P1[7] Page 11 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 100-Pin Part Pinout Table 6. 100-Pin Part Pinout (TQFP) Pin No. Type Digital Analog Name Description Pin No. Type Digital Analog Name Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I NC NC P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] NC NC SMP VSS P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] NC NC NC P1[5] P1[3] P1[1] NC VDD NC VSS NC P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] P1[0] P1[2] P1[4] P1[6] NC NC NC No connection No connection Analog column mux input Direct switched capacitor block input Direct switched capacitor block input No connection No connection Switch mode pump (SMP) connection to external components required Ground connection 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 I/O I/O I/O I/O I/O I/O I/O I/O Input I/O I/O Power I/O I/O I/O I/O I/O I/O I/O I NC P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] NC NC XRES P4[0] P4[2] VSS P4[4] P4[6] P2[0] P2[2] P2[4] NC P2[6] NC P0[0] NC NC P0[2] NC P0[4] NC P0[6] VDD VDD VSS VSS P6[0] P6[1] P6[2] P6[3] P6[4] P6[5] P6[6] P6[7] NC P0[7] NC P0[5] NC P0[3] NC No connection No connection No connection Active high external reset with internal pull-down Power Power I/O I/O I/O I/O I/O I/O I/O I/O I/O Ground connection I I I/O I/O I/O I2C SCL No connection No connection No connection I2C SDA Crystal (XTALin), I2C Serial Clock (SCL), ISSP-SCLK[8] No connection Supply voltage No connection Ground connection No connection I/O I/O I/O I/O Direct switched capacitor block input Direct switched capacitor block input External Analog Ground (AGND) No connection External Voltage Reference (VREF) No connection Analog column mux input No connection No connection Analog column mux input and column output No connection Analog column mux input and column output No connection Analog column mux input Supply voltage Supply voltage Ground connection Ground connection I/O Power Power Power Power I/O I/O I/O I/O I/O I/O I/O I/O I Power Power I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Crystal (XTALout), I2C Serial Data (SDA), ISSP-SDATA[8] Optional EXTCLK No connection No connection No connection No connection Analog column mux input No connection Analog column mux input and column output No connection Analog column mux input and column output No connection I/O I/O I/O I I/O I/O LEGEND: A = Analog, I = Input, and O = Output. Note 8. These are the ISSP pins, which are not High Z at POR. See the PSoC Programmable System-on-Chip Technical Reference Manual for details. Document Number: 38-12013 Rev. *S Page 12 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Figure 7. CY8C29866 100-Pin PSoC Device NC P0[3], A, IO NC P0[5], A, IO NC P0[7], A, I NC VDD VDD P0[6], A, I NC P0[4], A, IO NC P0[2], A, IO NC 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC P0[0], A, I NC P2[6], External VREF NC P2[4], External AGND P2[2], A, I P2[0], A, I P4[6] P4[4] VSS P4[2] P4[0] XRES NC NC P3[6] P3[4] P3[2] P3[0] P5[6] P5[4] P5[2] P5[0] NC NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 NC NC A, I, P0[1] P2[7] P2[5] A, I, P2[3] A, I, P2[1] P4[7] P4[5] P4[3] P4[1] NC NC SMP VSS P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] I2C SCL, P1[7] NC NC NC I2C SDA, P1[5] P1[3] XTALin, I2C SCL, P1[1] NC VDD NC VSS NC Document Number: 38-12013 Rev. *S P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] XTALout, I2C SDA, P1[0] P1[2] EXTCLK, P1[4] P1[6] NC 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 TQFP 87 86 85 84 83 82 81 80 79 78 77 76 P6[7] P6[6] P6[5] P6[4] P6[3] P6[2] P6[1] P6[0] VSS VSS Page 13 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 100-Pin Part Pinout (On-Chip Debug) The 100-pin TQFP part is for the CY8C29000 On-Chip Debug (OCD) PSoC device. Note OCD parts are only used for in-circuit debugging. OCD parts are NOT available for production Table 7. 100-Pin OCD Part Pinout (TQFP) Analog Pin No. Name Description Pin No. Analog Digital Digital Name Description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 I/O I/O I/O I/O I/O I/O I/O I/O I/O I I I Power NC NC P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] OCDE OCDO SMP No internal connection No internal connection Analog column mux input Direct switched capacitor block input Direct switched capacitor block input 15 Power VSS 16 I/O P3[7] 17 I/O P3[5] 18 I/O P3[3] 19 I/O P3[1] 20 I/O P5[7] 21 I/O P5[5] 22 I/O P5[3] 23 I/O P5[1] 24 I/O P1[7] I2C SCL 25 NC No internal connection 26 NC No internal connection 27 NC No internal connection 28 I/O P1[5] I2C SDA 29 I/O P1[3] IFMTEST 30 I/O P1[1][9] Crystal (XTALin), I2C SCL, TC SCLK. 31 NC No internal connection 32 Power VDD Supply voltage 33 NC No internal connection 34 Power VSS Ground connection 35 NC No internal connection 36 I/O P7[7] 37 I/O P7[6] 38 I/O P7[5] 39 I/O P7[4] 40 I/O P7[3] 41 I/O P7[2] 42 I/O P7[1] 43 I/O P7[0] 44 I/O P1[0]* Crystal (XTALout), I2C SDA, TC SDATA 45 I/O P1[2] VFMTEST 46 I/O P1[4] Optional External Clock Input (EXTCLK) 47 I/O P1[6] 48 NC No internal connection 49 NC No internal connection 50 NC No internal connection LEGEND A = Analog, I = Input, O = Output, NC = No Connection, TC/TM: Test. Note 9. ISSP pin which is not High-Z at POR. OCD even data I/O OCD odd data output Switch Mode Pump (SMP) connection to required external components Ground connection 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 I/O I/O I/O I/O I/O I/O I/O I/O Input I/O I/O Power I/O I/O I/O I I/O I I/O I/O I/O I NC P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] HCLK CCLK XRES P4[0] P4[2] VSS P4[4] P4[6] P2[0] P2[2] P2[4] NC P2[6] NC P0[0] NC NC P0[2] NC P0[4] NC P0[6] VDD VDD VSS VSS P6[0] P6[1] P6[2] P6[3] P6[4] P6[5] P6[6] P6[7] NC P0[7] NC P0[5] NC P0[3] NC No internal connection OCD high speed clock output OCD CPU clock output Active high pin reset with internal pull-down Ground connection I/O I/O I/O I/O I/O I Power Power Power Power I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I I/O I/O Direct switched capacitor block input Direct switched capacitor block input External Analog Ground (AGND) input No internal connection External Voltage Reference (VREF) input No internal connection Analog column mux input No internal connection No internal connection Analog column mux input and column output No internal connection Analog column mux input and column output, VREF No internal connection Analog column mux input Supply voltage Supply voltage Ground connection Ground connection No internal connection Analog column mux input No internal connection Analog column mux input and column output No internal connection Analog column mux input and column output No internal connection Document Number: 38-12013 Rev. *S Page 14 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Figure 8. CY8C29000 OCD (Not for Production) NC P0[3], AIO NC P0[5], AIO NC P0[7], AI NC P6[0] VSS VSS VDD VDD P0[6], AI NC P0[4], AIO NC P0[2], AIO NC 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC P0[0] , AI NC P2[6] , External VREF NC P2[4] , External AGND P2[2] , AI P2[0] , AI P4[6] P4[4] VSS P4[2] P4[0] XRES CCLK HCLK P3[6] P3[4] P3[2] P3[0] P5[6] P5[4] P5[2] P5[0] NC NC NC XTALout, I2C SDA, P1[0] P1[2] EXTCLK, P1[4] P1[6] NC 100 99 98 97 96 95 94 93 92 91 90 89 88 26 27 28 29 30 31 32 33 34 35 NC NC I2C SDA, P1[5] P1[3] XTALin, I2C SCL, P1[1] NC VDD NC VSS NC Document Number: 38-12013 Rev. *S P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC AI , P0[1] P2[7] P2[5] AI , P2[3] AI , P2[1] P4[7] P4[5] P4[3] P4[1] OCDE OCDO SMP Vss P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] I2 C SCL, P1[7] NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 OCD TQFP 87 86 85 84 83 82 81 80 79 78 P6[7] P6[6] P6[5] P6[4] P6[3] P6[2] P6[1] Page 15 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Register Reference This section lists the registers of the CY8C29x66 PSoC device. For detailed register information, refer to the PSoC Programmable System-on-Chip Technical Reference Manual. Register Conventions The register conventions specific to this section are listed in Table 8. Table 8. Register Conventions Convention R W L C # Description Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific Register Mapping Tables The PSoC device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks. The XOI bit in the flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1. Note In the register mapping tables, blank fields are reserved and should not be accessed. Document Number: 38-12013 Rev. *S Page 16 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Table 9. Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 PRT6DR PRT6IE PRT6GS PRT6DM2 PRT7DR PRT7IE PRT7GS PRT7DM2 DBB00DR0 DBB00DR1 DBB00DR2 DBB00CR0 DBB01DR0 DBB01DR1 DBB01DR2 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 DCB03DR1 DCB03DR2 DCB03CR0 DBB10DR0 DBB10DR1 DBB10DR2 DBB10CR0 DBB11DR0 DBB11DR1 DBB11DR2 DBB11CR0 DCB12DR0 DCB12DR1 DCB12DR2 DCB12CR0 DCB13DR0 DCB13DR1 DCB13DR2 DCB13CR0 Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # Name DBB20DR0 DBB20DR1 DBB20DR2 DBB20CR0 DBB21DR0 DBB21DR1 DBB21DR2 DBB21CR0 DCB22DR0 DCB22DR1 DCB22DR2 DCB22CR0 DCB23DR0 DCB23DR1 DCB23DR2 DCB23CR0 DBB30DR0 DBB30DR1 DBB30DR2 DBB30CR0 DBB31DR0 DBB31DR1 DBB31DR2 DBB31CR0 DCB32DR0 DCB32DR1 DCB32DR2 DCB32CR0 DCB33DR0 DCB33DR1 DCB33DR2 DCB33CR0 AMX_IN Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Access # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # RW Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI3RI RDI3SYN RDI3IS RDI3LT0 RDI3LT1 RDI3RO0 RDI3RO1 CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W RC RC RW RW W W R R RW RW RW RW ARF_CR CMP_CR0 ASY_CR CMP_CR1 RW # # RW MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 ACB02CR3 ACB02CR0 ACB02CR1 ACB02CR2 ACB03CR3 ACB03CR0 ACB03CR1 ACB03CR2 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW CPU_F RL CPU_SCR1 CPU_SCR0 # # Blank fields are Reserved and should not be accessed. # Access is bit specific. Document Number: 38-12013 Rev. *S Page 17 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Table 10. Register Map Bank 1 Table: Configuration Space Addr (1,Hex) Access Name 00 RW DBB20FN 01 RW DBB20IN 02 RW DBB20OU 03 RW 04 RW DBB21FN 05 RW DBB21IN 06 RW DBB21OU 07 RW 08 RW DCB22FN 09 RW DCB22IN 0A RW DCB22OU 0B RW 0C RW DCB23FN 0D RW DCB23IN 0E RW DCB23OU 0F RW 10 RW DBB30FN 11 RW DBB30IN 12 RW DBB30OU 13 RW 14 RW DBB31FN 15 RW DBB31IN 16 RW DBB31OU 17 RW 18 RW DCB32FN 19 RW DCB32IN 1A RW DCB32OU 1B RW 1C RW DCB33FN 1D RW DCB33IN 1E RW DCB33OU 1F RW 20 RW CLK_CR0 21 RW CLK_CR1 22 RW ABF_CR0 23 AMD_CR0 DBB01FN 24 RW DBB01IN 25 RW DBB01OU 26 RW AMD_CR1 27 ALT_CR0 DCB02FN 28 RW ALT_CR1 DCB02IN 29 RW CLK_CR2 DCB02OU 2A RW 2B DCB03FN 2C RW TMP_DR0 DCB03IN 2D RW TMP_DR1 DCB03OU 2E RW TMP_DR2 2F TMP_DR3 DBB10FN 30 RW ACB00CR3 DBB10IN 31 RW ACB00CR0 DBB10OU 32 RW ACB00CR1 33 ACB00CR2 DBB11FN 34 RW ACB01CR3 DBB11IN 35 RW ACB01CR0 DBB11OU 36 RW ACB01CR1 37 ACB01CR2 DCB12FN 38 RW ACB02CR3 DCB12IN 39 RW ACB02CR0 DCB12OU 3A RW ACB02CR1 3B ACB02CR2 DCB13FN 3C RW ACB03CR3 DCB13IN 3D RW ACB03CR0 DCB13OU 3E RW ACB03CR1 3F ACB03CR2 Blank fields are Reserved and should not be accessed. Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 PRT6DM0 PRT6DM1 PRT6IC0 PRT6IC1 PRT7DM0 PRT7DM1 PRT7IC0 PRT7IC1 DBB00FN DBB00IN DBB00OU Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 RDI1RI B8 RDI1SYN B9 RDI1IS BA RDI1LT0 BB RDI1LT1 BC RDI1RO0 BD RDI1RO1 BE BF # Access is bit specific. Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI3RI RDI3SYN RDI3IS RDI3LT0 RDI3LT1 RDI3RO0 RDI3RO1 GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP RW RW RW RW RW RW RW R RW RW RW RW DEC_CR2 IMO_TR ILO_TR BDG_TR ECO_TR RW W W RW W RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW CPU_F RW RW RW RW RW RW RW RL FLS_PR1 RW CPU_SCR1 CPU_SCR0 # # Document Number: 38-12013 Rev. *S Page 18 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Electrical Specifications This section presents the DC and AC electrical specifications of the CY8C29x66 PSoC device. For the most up-to-date electrical specifications, confirm that you have the most recent datasheet by going to the web at http://www.cypress.com. Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Refer to Table 27 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode. Figure 9. Voltage versus CPU Frequency Figure 10. IMO Frequency Options S L IM O M o d e =1 4.75 Vdd Voltage 3.00 9 3 kHz C PU F r e q u e n c y 4.75 Vdd Voltage SLIMO Mode = 0 5.25 5.25 S L IM O M o d e =0 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 11. Absolute Maximum Ratings Symbol TSTG Description Storage temperature Min –55 Typ 25 Max +100 Unit °C Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is +25 °C ± 25 °C. Extended duration storage temperatures higher than 65 °C degrade reliability. O l id g V a a tin n r pe g io Re 12 MHz 2 4 MHz 3.60 S L IM O M o d e =1 S L IM O M o d e =0 3.00 9 3 kHz 6 MHz IM O F r e q u e n cy 1 2 MHz 2 4 MHz TBAKETEMP TBAKETIME TA VDD VIO VIOZ IMIO IMAIO ESD LU Bake temperature – 125 See package label 72 °C Bake time See package label –40 –0.5 VSS – 0.5 VSS – 0.5 –25 –50 2000 – – Hours Ambient temperature with power applied Supply voltage on VDD relative to VSS DC input voltage DC voltage applied to tristate Maximum current into any port pin Maximum current into any port pin configured as analog driver Electrostatic discharge voltage Latch-up current – – – – – – – – +85 +6.0 VDD + 0.5 VDD + 0.5 +50 +50 – 200 °C V V V mA mA V mA Human body model ESD. Document Number: 38-12013 Rev. *S Page 19 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Operating Temperature Table 12. Operating Temperature Symbol TA TJ Description Ambient temperature Junction temperature Min –40 –40 Typ – – Max +85 +100 Unit °C °C Notes The temperature rise from ambient to junction is package specific. See “Thermal Impedances” on page 49. You must limit the power consumption to comply with this requirement. DC Electrical Characteristics DC Chip-Level Specifications Table 13 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 13. DC Chip-Level Specifications Symbol VDD IDD IDD3 IDDP ISB ISBH ISBXTL ISBXTLH VREF Supply voltage Supply current Description Min 3.00 – Typ – 8 Max 5.25 14 Unit Notes s V See DC POR, SMP, and LVD Specifications on page 33. mA Conditions are 5.0 V, TA = 25 °C, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz. mA Conditions are VDD = 3.3 V, TA = 25 °C, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz. mA Conditions are VDD = 3.3 V, TA = 25 °C, CPU = 0.75 MHz, SYSCLK doubler disabled, VC1 = 0.375 MHz, VC2 = 23.44 kHz, VC3 = 0.09 kHz. µA Conditions are with internal slow speed oscillator, VDD = 3.3 V, –40 °C ≤ TA ≤ 55 °C. µA Conditions are with internal slow speed oscillator, VDD = 3.3 V, 55 °C < TA ≤ 85 °C. µA Conditions are with properly loaded, 1 µW max, 32.768 kHz crystal. VDD = 3.3 V, –40 °C ≤ TA ≤ 55 °C. µA V Conditions are with properly loaded, 1 µW max, 32.768 kHz crystal. VDD = 3.3 V, 55 °C < TA ≤ 85 °C. Trimmed for appropriate VDD. Supply current – 5 9 Supply current when IMO = 6 MHz using SLIMO mode. – 2 3 Sleep (Mode) current with POR, LVD, sleep – timer, WDT, and internal slow oscillator active. Sleep (Mode) current with POR, LVD, sleep – timer, WDT, and internal slow oscillator active. Sleep (Mode) current with POR, LVD, sleep – timer, WDT, internal slow oscillator, and 32 kHz crystal oscillator active. Sleep (Mode) current with POR, LVD, sleep – timer, WDT, and 32 kHz crystal oscillator active. Reference voltage (Bandgap) 1.28 3 4 4 10 25 12 5 1.3 27 1.32 Document Number: 38-12013 Rev. *S Page 20 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 DC GPIO Specifications Table 14 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 14. DC GPIO Specifications Symbol RPU RPD VOH Pull-up resistor Pull-down resistor High output level Description Min 4 4 VDD – 1.0 Typ 5.6 5.6 – Max 8 8 – Unit kΩ kΩ V IOH = 10 mA, VDD = 4.75 to 5.25 V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget. IOL = 25 mA, VDD = 4.75 to 5.25 V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 150 mA maximum combined IOL budget. VOH = VDD – 1.0 V, see the limitations of the total current in the note for VOH VOL = 0.75 V, see the limitations of the total current in the note for VOL VDD = 3.0 to 5.25 VDD = 3.0 to 5.25 Gross tested to 1 µA. Package and pin dependent. Temp = 25 °C. Package and pin dependent. Temp = 25 °C. Notes VOL Low output level – – 0.75 V IOH IOL VIL VIH VH IIL CIN COUT High level source current Low level sink current Input low level Input high level Input hysteresis Input leakage (absolute value) Capacitive load on pins as input Capacitive load on pins as output 10 25 – 2.1 – – – – – – – – 60 1 3.5 3.5 – – 0.8 – – – 10 10 mA mA V V mV nA pF pF DC Operational Amplifier Specifications Table 15 and Table 16 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5 V at 25 °C and are for design guidance only. Table 15. 5-V DC Operational Amplifier Specifications Symbol VOSOA Description Input offset voltage (absolute value) Power = Low, Opamp bias = Low Power = Low, Opamp bias = High Power = Medium, Opamp bias = Low Power = Medium, Opamp bias = High Power = High, Opamp bias = Low Power = High, Opamp bias = High Average input offset voltage drift Input leakage current (port 0 analog pins) Input capacitance (port 0 analog pins) Min – – – – – – – – – Typ 1.6 1.6 1.6 1.6 1.6 1.6 4 200 4.5 Max 10 10 10 10 10 10 23 – 9.5 Unit mV mV mV mV mV mV µV/°C pA pF Gross tested to 1 µA Package and pin dependent. Temp = 25 °C Notes TCVOSOA I EBOA CINOA Document Number: 38-12013 Rev. *S Page 21 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Table 15. 5-V DC Operational Amplifier Specifications (continued) Symbol V CMOA Description Common mode voltage range (All cases, except Power = High, Opamp bias = High) Common mode voltage range (Power = High, Opamp bias = High) Min 0 Typ – Max VDD VDD – 0.5 Unit V Notes The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. 0.5 – V CMRROA GOLOA Common mode rejection ratio Open loop gain 60 80 VDD – 0.01 – – – – – – – – 0.1 dB dB V V VOHIGHOA High output voltage swing (internal signals) VOLOWOA ISOA Low output voltage swing (internal signals) Supply current (including associated AGND buffer) Power = Low, Opamp bias = Low Power = Low, Opamp bias = High Power = Medium, Opamp bias = Low Power = Medium, Opamp bias = High Power = High, Opamp bias = Low Power = High, Opamp bias = High Supply voltage rejection ratio – – – – – – 67 150 300 600 1200 2400 4600 80 200 400 800 1600 3200 6400 – µA µA µA µA µA µA dB VSS ≤ VIN ≤ (VDD – 2.25) or (VDD – 1.25 V) ≤ VIN ≤ VDD. PSRROA Table 16. 3.3-V DC Operational Amplifier Specifications Symbol VOSOA Description Input offset voltage (absolute value) Power = Low, Opamp bias = Low Power = Low, Opamp bias = High Power = Medium, Opamp bias = Low Power = Medium, Opamp bias = High Power = High, Opamp bias = Low Power = High, Opamp bias = High Average input offset voltage drift Input leakage current (port 0 analog pins) Input capacitance (port 0 analog pins) Common mode voltage range Min – – – – – – – – – 0 Typ 1.4 1.4 1.4 1.4 1.4 – 7 200 4.5 – Max 10 10 10 10 10 – 40 – 9.5 VDD Unit mV mV mV mV mV mV µV/°C pA pF V Gross tested to 1 µA. Package and pin dependent. Temp = 25 °C The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Notes Power = High, Opamp bias = High setting is not allowed for 3.3 V VDD operation. TCVOSOA I EBOA CINOA V CMOA CMRROA GOLOA VOHIGHOA Common mode rejection ratio Open loop gain High output voltage swing (internal signals) 60 80 VDD – 0.01 – – – – – – dB dB V Document Number: 38-12013 Rev. *S Page 22 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Table 16. 3.3-V DC Operational Amplifier Specifications (continued) Symbol VOLOWOA ISOA Description Low output voltage swing (internal signals) Supply current (including associated AGND buffer) Power = Low, Opamp bias = Low Power = Low, Opamp bias = High Power = Medium, Opamp bias = Low Power = Medium, Opamp bias = High Power = High, Opamp bias = Low Power = High, Opamp bias = High Supply voltage rejection ratio Min – Typ – Max 0.01 Unit V Power = High, Opamp bias = High setting is not allowed for 3.3 V VDD operation. Notes – – – – – – 54 150 300 600 1200 2400 – 80 200 400 800 1600 3200 – – µA µA µA µA µA µA dB PSRROA VSS ≤ VIN ≤ (VDD – 2.25) or (VDD – 1.25 V) ≤ VIN ≤ VDD DC Low-Power Comparator Specifications Table 17 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V at 25 °C and are for design guidance only. Table 17. DC Low-Power Comparator Specifications Symbol VREFLPC ISLPC VOSLPC LPC supply current LPC voltage offset Description Low-power comparator (LPC) reference voltage range Min 0.2 – – Typ – 10 2.5 Max VDD – 1 40 30 Unit V µA mV DC Analog Output Buffer Specifications Table 18 and Table 19 list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 18. 5-V DC Analog Output Buffer Specifications Symbol VOSOB Description Input offset voltage (absolute value) Power = Low, Opamp bias = Low Power = Low, Opamp bias = High Power = High, Opamp bias = Low Power = High, Opamp bias = High Average input offset voltage drift Common-mode input voltage range Output resistance Power = Low Power = High High output voltage swing (Load = 32 ohms to VDD/2) Power = Low Power = High Low output voltage swing (Load = 32 ohms to VDD/2) Power = Low Power = High Min – – – – – 0.5 – – Typ 3.2 3.2 3.2 3.2 5.5 – – – Max 18 18 18 18 26 VDD – 1.0 1 1 Unit mV mV mV mV µV/°C V Ω Ω Notes TCVOSOB VCMOB ROUTOB VOHIGHOB 0.5 × VDD + 1.3 0.5 × VDD + 1.3 – – – – – – V V VOLOWOB – – 0.5 × VDD – 1.3 0.5 × VDD – 1.3 V V Document Number: 38-12013 Rev. *S Page 23 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Table 18. 5-V DC Analog Output Buffer Specifications (continued) Symbol ISOB PSRROB CL Description Supply current including bias cell (no load) Power = Low Power = High Supply voltage rejection ratio Load capacitance Min – – 40 – Typ 1.1 2.6 64 – 200 Max 2 5 Unit mA mA dB pF This specification applies to the external circuit driven by the analog output buffer. Notes Table 19. 3.3-V DC Analog Output Buffer Specifications Symbol VOSOB Description Input offset voltage (absolute value) Power = Low, Opamp bias = Low Power = Low, Opamp bias = High Power = High, Opamp bias = Low Power = High, Opamp bias = High Average input offset voltage drift Power = Low, Opamp bias = Low Power = Low, Opamp bias = High Power = High, Opamp bias = Low Power = High, Opamp bias = High Common-mode input voltage range Output resistance Power = Low Power = High High output voltage swing (Load = 32 ohms to VDD/2) Power = Low Power = High Low output voltage swing (Load = 32 ohms to VDD/2) Power = Low Power = High Supply current including bias cell (no load) Power = Low Power = High Supply voltage rejection ratio Load capacitance Min – – – – – – – – 0.5 – – Typ 3.2 3.2 6 6 8 8 12 12 – – – Max 20 20 25 25 32 32 41 41 VDD – 1.0 10 10 Unit mV mV mV mV µV/°C µV/°C µV/°C µV/°C V W W Notes High power setting is not recommended. TCVOSOB High power setting is not recommended. VCMOB ROUTOB VOHIGHOB 0.5 × VDD + 1.0 0.5 × VDD + 1.0 – – – – 60 – – – – – V V VOLOWOB – – 0.8 2.0 64 – 0.5 × VDD – 1.0 0.5 × VDD – 1.0 1 5 – 200 V V mA mA dB pF This specification applies to the external circuit driven by the analog output buffer. ISOB PSRROB CL Document Number: 38-12013 Rev. *S Page 24 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 DC Switch Mode Pump Specifications Table 20 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 20. DC Switch Mode Pump (SMP) Specifications Symbol VPUMP 5 V VPUMP 3 V IPUMP VBAT5 V VBAT3 V VBATSTART ΔVPUMP_Line Description 5 V output voltage at VDD from pump 3 V output voltage at VDD from pump Available output current VBAT = 1.5 V, VPUMP = 3.25 V VBAT = 1.8 V, VPUMP = 5.0 V Input voltage range from battery Input voltage range from battery Minimum input voltage from battery to start pump Line regulation (over VBAT range) Min 4.75 Typ 5.0 Max 5.25 Unit V Notes Configured as in Note 10. Average, neglecting ripple. SMP trip voltage is set to 5.0 V Configured as in Note 10. Average, neglecting ripple. SMP trip voltage is set to 3.25 V Configured as in Note 10 SMP trip voltage is set to 3.25 V SMP trip voltage is set to 5.0 V Configured as in Note 10. SMP trip voltage is set to 5.0 V Configured as in Note 10. SMP trip voltage is set to 3.25 V Configured as in Note 10.0 °C ≤ TA ≤ 100. 1.25 V at TA = –40 °C Configured as in Note 10. VO is the “VDD Value for PUMP Trip” specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 24, “DC POR, SMP, and LVD Specifications,” on page 33 Configured as in Note 10. VO is the “VDD Value for PUMP Trip” specified by the VM[2:0] setting in Table 24, “DC POR, SMP, and LVD Specifications,” on page 33 Configured as in Note 10. Load is 5 mA Configured as in Note 10. Load is 5 mA. SMP trip voltage is set to 3.25 V 3.00 3.25 3.60 V 8 5 1.8 1.0 1.2 – – – – – – 5 – – 5.0 3.3 – – mA mA V V V %VO ΔVPUMP_Load Load regulation – 5 – %VO ΔVPUMP_Ripple Output voltage ripple (depends on capacitor/load) E3 FPUMP DCPUMP Efficiency – 35 100 50 – – mVpp % Switching frequency Switching duty cycle – – 1.4 50 – – MHz % Note 10. L1 = 2 µH inductor, C1 = 10 µF capacitor, D1 = Schottky diode. See Figure 11. Document Number: 38-12013 Rev. *S Page 25 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Figure 11. Basic Switch Mode Pump Circuit D1 Vdd V PUMP L1 V BAT C1 SMP + Battery PSoC Vss DC Analog Reference Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. The guaranteed specifications for RefHI and RefLO are measured through the analog continuous time PSoC blocks. The power levels for RefHI and RefLO refer to the analog reference control register. AGND is measured at P2[4] in AGND bypass mode. Each analog continuous time PSoC block adds a maximum of 10 mV additional offset error to guaranteed AGND specifications from the local AGND buffer. Reference control power can be set to medium or high unless otherwise noted. Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the analog reference. Some coupling of the digital signal may appear on the AGND. Table 21. 5-V DC Analog Reference Specifications Reference ARF_CR[5:3] Reference Power Settings RefPower = High Opamp bias = High Symbol VREFHI VAGND VREFLO RefPower = High Opamp bias = Low 0b000 VREFHI VAGND VREFLO RefPower = Med Opamp bias = High VREFHI VAGND VREFLO RefPower = Med Opamp bias = Low VREFHI VAGND VREFLO Reference Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Description VDD/2 + Bandgap VDD/2 VDD/2 – Bandgap VDD/2 + Bandgap VDD/2 VDD/2 – Bandgap VDD/2 + Bandgap VDD/2 VDD/2 – Bandgap VDD/2 + Bandgap VDD/2 VDD/2 – Bandgap Min VDD/2 + 1.228 VDD/2 – 0.078 VDD/2 – 1.336 VDD/2 + 1.224 VDD/2 – 0.056 VDD/2 – 1.338 VDD/2 + 1.226 VDD/2 – 0.057 VDD/2 – 1.337 VDD/2 + 1.226 VDD/2 – 0.047 VDD/2 – 1.338 Typ Max Unit V V V V V V V V V V V V VDD/2 + 1.290 VDD/2 + 1.352 VDD/2 – 0.007 VDD/2 – 1.295 VDD/2 – 0.005 VDD/2 – 1.298 VDD/2 – 0.006 VDD/2 – 1.298 VDD/2 – 0.004 VDD/2 – 1.299 VDD/2 + 0.063 VDD/2 – 1.250 VDD/2 + 0.043 VDD/2 – 1.255 VDD/2 + 0.044 VDD/2 – 1.256 VDD/2 + 0.035 VDD/2 – 1.258 VDD/2 + 1.293 VDD/2 + 1.356 VDD/2 + 1.293 VDD/2 + 1.356 VDD/2 + 1.294 VDD/2 + 1.359 Document Number: 38-12013 Rev. *S Page 26 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Table 21. 5-V DC Analog Reference Specifications (continued) Reference ARF_CR[5:3] Reference Power Settings RefPower = High Opamp bias = High Symbol VREFHI Reference Ref High Description P2[4] + P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] P2[4] – P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] + P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] P2[4] – P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] + P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] P2[4] – P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] + P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] P2[4] – P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) VDD VDD/2 VSS VDD VDD/2 VSS VDD VDD/2 VSS VDD VDD/2 VSS Min P2[4] + P2[6] – 0.085 P2[4] P2[4] – P2[6] – 0.022 P2[4] + P2[6] – 0.077 P2[4] P2[4] – P2[6] – 0.022 P2[4] + P2[6] – 0.070 P2[4] P2[4] – P2[6] – 0.022 P2[4] + P2[6] – 0.070 P2[4] P2[4] – P2[6] – 0.022 VDD – 0.037 VDD/2 – 0.061 VSS VDD – 0.039 VDD/2 – 0.049 VSS VDD – 0.037 VDD/2 – 0.054 VSS VDD – 0.042 VDD/2 – 0.046 VSS Typ P2[4] + P2[6] – 0.016 P2[4] Max P2[4] + P2[6] + 0.044 P2[4] Unit V VAGND VREFLO AGND Ref Low – V P2[4] – P2[6] + P2[4] – P2[6] + 0.010 0.055 P2[4] + P2[6] – 0.010 P2[4] P2[4] + P2[6] + 0.051 P2[4] RefPower = High Opamp bias = Low VREFHI Ref High V VAGND VREFLO 0b001 AGND Ref Low – V P2[4] – P2[6] + P2[4] – P2[6] + 0.005 0.039 P2[4] + P2[6] – 0.010 P2[4] P2[4] + P2[6] + 0.050 P2[4] RefPower = Med Opamp bias = High VREFHI Ref High V VAGND VREFLO AGND Ref Low – V P2[4] – P2[6] + P2[4] – P2[6] + 0.005 0.039 P2[4] + P2[6] – 0.007 P2[4] P2[4] + P2[6] + 0.054 P2[4] RefPower = Med Opamp bias = Low VREFHI Ref High V VAGND VREFLO AGND Ref Low – V P2[4] – P2[6] + P2[4] – P2[6] + 0.002 0.032 VDD – 0.009 VDD/2 – 0.006 VSS + 0.007 VDD – 0.006 VDD/2 – 0.005 VSS + 0.005 VDD – 0.007 VDD/2 – 0.005 VSS + 0.006 VDD – 0.005 VDD/2 – 0.004 VSS + 0.004 VDD VDD/2 + 0.047 VSS + 0.028 VDD VDD/2 + 0.036 VSS + 0.019 VDD VDD/2 + 0.041 VSS + 0.024 VDD VDD/2 + 0.034 VSS + 0.017 RefPower = High Opamp bias = High VREFHI VAGND VREFLO VREFHI VAGND VREFLO VREFHI VAGND VREFLO VREFHI VAGND VREFLO Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low V V V V V V V V V V V V RefPower = High Opamp bias = Low 0b010 RefPower = Med Opamp bias = High RefPower = Med Opamp bias = Low Document Number: 38-12013 Rev. *S Page 27 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Table 21. 5-V DC Analog Reference Specifications (continued) Reference ARF_CR[5:3] Reference Power Settings RefPower = High Opamp bias = High Symbol VREFHI VAGND VREFLO RefPower = High Opamp bias = Low 0b011 VREFHI VAGND VREFLO RefPower = Med Opamp bias = High VREFHI VAGND VREFLO RefPower = Med Opamp bias = Low VREFHI VAGND VREFLO RefPower = High Opamp bias = High VREFHI Reference Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High Description 3 × Bandgap 2 × Bandgap Bandgap 3 × Bandgap 2 × Bandgap Bandgap 3 × Bandgap 2 × Bandgap Bandgap 3 × Bandgap 2 × Bandgap Bandgap 2 × Bandgap + P2[6] (P2[6] = 1.3 V) 2 × Bandgap 2 × Bandgap – P2[6] (P2[6] = 1.3 V) 2 × Bandgap + P2[6] (P2[6] = 1.3 V) 2 × Bandgap 2 × Bandgap – P2[6] (P2[6] = 1.3 V) 2 × Bandgap + P2[6] (P2[6] = 1.3 V) 2 × Bandgap 2 × Bandgap – P2[6] (P2[6] = 1.3 V) 2 × Bandgap + P2[6] (P2[6] = 1.3 V) 2 × Bandgap 2 × Bandgap – P2[6] (P2[6] = 1.3 V) Min 3.788 2.500 1.257 3.792 2.518 1.256 3.795 2.516 1.256 3.792 2.522 1.255 2.495 – P2[6] Typ 3.891 2.604 1.306 3.893 2.602 1.302 3.894 2.603 1.303 3.895 2.602 1.301 2.586 – P2[6] Max 3.986 3.699 1.359 3.982 2.692 1.354 3.993 2.698 1.353 3.986 2.685 1.350 2.657 – P2[6] Unit V V V V V V V V V V V V V VAGND VREFLO AGND Ref Low 2.502 2.531 – P2[6] 2.604 2.611 – P2[6] 2.719 2.681 – P2[6] V V RefPower = High Opamp bias = Low VREFHI Ref High 2.500 – P2[6] 2.591 – P2[6] 2.662 – P2[6] V VAGND VREFLO 0b100 AGND Ref Low 2.519 2.530 – P2[6] 2.602 2.605 – P2[6] 2.693 2.666 – P2[6] V V RefPower = Med Opamp bias = High VREFHI Ref High 2.503 – P2[6] 2.592 – P2[6] 2.662 – P2[6] V VAGND VREFLO AGND Ref Low 2.517 2.529 – P2[6] 2.603 2.606 – P2[6] 2.698 2.665 – P2[6] V V RefPower = Med Opamp bias = Low VREFHI Ref High 2.505 – P2[6] 2.594 – P2[6] 2.665 – P2[6] V VAGND VREFLO AGND Ref Low 2.525 2.528 – P2[6] 2.602 2.603 – P2[6] 2.685 2.661 – P2[6] V V Document Number: 38-12013 Rev. *S Page 28 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Table 21. 5-V DC Analog Reference Specifications (continued) Reference ARF_CR[5:3] Reference Power Settings RefPower = High Opamp bias = High Symbol VREFHI VAGND VREFLO RefPower = High Opamp bias = Low VREFHI VAGND VREFLO 0b101 RefPower = Med Opamp bias = High VREFHI VAGND VREFLO RefPower = Med Opamp bias = Low VREFHI VAGND VREFLO RefPower = High Opamp bias = High VREFHI VAGND VREFLO RefPower = High Opamp bias = Low 0b110 VREFHI VAGND VREFLO RefPower = Med Opamp bias = High VREFHI VAGND VREFLO RefPower = Med Opamp bias = Low VREFHI VAGND VREFLO RefPower = High Opamp bias = High VREFHI VAGND VREFLO RefPower = High Opamp bias = Low 0b111 VREFHI VAGND VREFLO RefPower = Med Opamp bias = High VREFHI VAGND VREFLO RefPower = Med Opamp bias = Low VREFHI VAGND VREFLO Reference Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Description P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] – Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] – Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] – Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] – Bandgap (P2[4] = VDD/2) 2 × Bandgap Bandgap VSS 2 × Bandgap Bandgap VSS 2 × Bandgap Bandgap VSS 2 × Bandgap Bandgap VSS 3.2 × Bandgap 1.6 × Bandgap VSS 3.2 × Bandgap 1.6 × Bandgap VSS 3.2 × Bandgap 1.6 × Bandgap VSS 3.2 × Bandgap 1.6 × Bandgap VSS Min P2[4] + 1.222 P2[4] P2[4] – 1.331 P2[4] + 1.226 P2[4] P2[4] – 1.331 P2[4] + 1.227 P2[4] P2[4] – 1.331 P2[4] + 1.228 P2[4] P2[4] – 1.332 2.535 1.227 VSS 2.530 1.244 VSS 2.532 1.239 VSS 2.528 1.249 VSS 4.041 1.998 VSS 4.047 2.012 VSS 4.049 2.008 VSS 4.047 2.016 VSS Typ P2[4] + 1.290 P2[4] P2[4] – 1.295 P2[4] + 1.293 P2[4] P2[4] – 1.298 P2[4] + 1.294 P2[4] P2[4] – 1.298 P2[4] + 1.295 P2[4] P2[4] – 1.299 2.598 1.305 VSS + 0.009 2.598 1.303 VSS + 0.005 2.598 1.304 VSS + 0.006 2.598 1.302 VSS + 0.004 4.155 2.083 VSS + 0.010 4.153 2.082 VSS + 0.006 4.154 2.083 VSS + 0.006 4.154 2.081 VSS + 0.004 Max P2[4] + 1.343 P2[4] P2[4] – 1.254 P2[4] + 1.347 P2[4] P2[4] – 1.259 P2[4] + 1.347 P2[4] P2[4] – 1.259 P2[4] + 1.349 P2[4] P2[4] – 1.260 2.644 1.398 VSS + 0.038 2.643 1.370 VSS + 0.024 2.644 1.380 VSS + 0.026 2.645 1.362 VSS + 0.018 4.234 2.183 VSS + 0.038 4.236 2.157 VSS + 0.024 4.238 2.165 VSS + 0.026 4.238 2.150 VSS + 0.018 Unit V – V V – V V – V V – V V V V V V V V V V V V V V V V V V V V V V V V V Document Number: 38-12013 Rev. *S Page 29 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Table 22. 3.3-V DC Analog Reference Specifications Reference ARF_CR[5:3] Reference Power Settings RefPower = High Opamp bias = High Symbol Reference VREFHI VAGND VREFLO VREFHI RefPower = High Opamp bias = Low 0b000 RefPower = Med Opamp bias = High VAGND VREFLO VREFHI VAGND VREFLO VREFHI RefPower = Med Opamp bias = Low VAGND VREFLO VREFHI Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High Description VDD/2 + BandGap VDD/2 VDD/2 – BandGap VDD/2 + BandGap VDD/2 VDD/2 – BandGap VDD/2 + BandGap VDD/2 VDD/2 – BandGap VDD/2 + BandGap VDD/2 VDD/2 – BandGap P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) RefPower = High Opamp bias = High VAGND VREFLO AGND Ref Low P2[4] P2[4] P2[4] P2[4] – V Min VDD/2 + 1.225 VDD/2 – 0.067 VDD/2 – 1.35 VDD/2 + 1.218 VDD/2 – 0.038 VDD/2 – 1.329 VDD/2 + 1.221 VDD/2 – 0.050 VDD/2 – 1.331 VDD/2 + 1.226 VDD/2 – 0.028 VDD/2 – 1.329 Typ VDD/2 + 1.292 VDD/2 – 0.002 VDD/2 – 1.293 VDD/2 + 1.294 VDD/2 – 0.001 VDD/2 – 1.296 VDD/2 + 1.294 VDD/2 – 0.002 VDD/2 – 1.296 VDD/2 + 1.295 VDD/2 – 0.001 VDD/2 – 1.297 Max VDD/2 + 1.361 VDD/2 + 0.063 VDD/2 – 1.210 VDD/2 + 1.370 VDD/2 + 0.035 VDD/2 – 1.259 VDD/2 + 1.366 VDD/2 + 0.046 VDD/2 – 1.260 VDD/2 + 1.365 VDD/2 + 0.025 VDD/2 – 1.262 Unit V V V V V V V V V V V V V P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + 0.098 0.018 0.055 P2[4] – P2[6] (P2[4] P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + = VDD/2, P2[6] = 0.055 0.013 0.086 0.5 V) P2[4] + P2[6] (P2[4] P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + = VDD/2, P2[6] = 0.082 0.011 0.050 0.5 V) P2[4] P2[4] P2[4] P2[4] VREFHI Ref High V RefPower = High Opamp bias = Low VAGND VREFLO AGND Ref Low – V P2[4] – P2[6] (P2[4] P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + = VDD/2, P2[6] = 0.037 0.006 0.054 0.5 V) P2[4] + P2[6] (P2[4] P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + = VDD/2, P2[6] = 0.079 0.012 0.047 0.5 V) P2[4] P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] P2[4] P2[4] 0b001 VREFHI Ref High V RefPower = Med Opamp bias = High VAGND VREFLO AGND Ref Low – V P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + 0.038 0.006 0.057 P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + 0.080 0.008 0.055 P2[4] P2[4] P2[4] VREFHI Ref High V RefPower = Med Opamp bias = Low VAGND VREFLO AGND Ref Low – V P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + 0.032 0.003 0.042 Document Number: 38-12013 Rev. *S Page 30 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Table 22. 3.3-V DC Analog Reference Specifications (continued) Reference ARF_CR[5:3] Reference Power Settings RefPower = High Opamp bias = High Symbol Reference VREFHI VAGND VREFLO VREFHI RefPower = High Opamp bias = Low 0b010 RefPower = Med Opamp bias = High VAGND VREFLO VREFHI VAGND VREFLO VREFHI RefPower = Med Opamp bias = Low All power settings. Not allowed for 3.3 V All power settings. Not allowed for 3.3 V VAGND VREFLO 0b011 0b100 – – VREFHI RefPower = High Opamp bias = High VAGND VREFLO VREFHI RefPower = High Opamp bias = Low VAGND VREFLO 0b101 VREFHI RefPower = Med Opamp bias = High VAGND VREFLO VREFHI RefPower = Med Opamp bias = Low VAGND VREFLO Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low – – Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Description VDD VDD/2 Vss VDD VDD/2 Vss VDD VDD/2 Vss VDD VDD/2 Vss – – P2[4] + BandGap (P2[4] = VDD/2) P2[4] P2[4] – BandGap (P2[4] = VDD/2) P2[4] + BandGap (P2[4] = VDD/2) P2[4] P2[4] – BandGap (P2[4] = VDD/2) P2[4] + BandGap (P2[4] = VDD/2) P2[4] P2[4] – BandGap (P2[4] = VDD/2) P2[4] + BandGap (P2[4] = VDD/2) P2[4] P2[4] – BandGap (P2[4] = VDD/2) Min VDD – 0.06 VDD/2 – 0.05 Vss VDD – 0.060 VDD/2 – 0.028 Vss VDD – 0.058 VDD/2 – 0.037 Vss VDD – 0.057 VDD/2 – 0.025 Vss – – P2[4] + 1.213 P2[4] P2[4] – 1.333 P2[4] + 1.217 P2[4] P2[4] – 1.320 P2[4] + 1.217 P2[4] P2[4] – 1.322 P2[4] + 1.219 P2[4] P2[4] – 1.324 Typ VDD – 0.010 VDD/2 – 0.002 Vss + 0.009 VDD – 0.006 VDD/2 – 0.001 Vss + 0.005 VDD – 0.008 VDD/2 – 0.002 Vss + 0.007 VDD – 0.006 VDD/2 – 0.001 Vss + 0.004 – – P2[4] + 1.291 P2[4] P2[4] – 1.294 P2[4] + 1.294 P2[4] P2[4] – 1.296 P2[4] + 1.294 P2[4] P2[4] – 1.297 P2[4] + 1.295 P2[4] P2[4] – 1.297 Max VDD VDD/2 + 0.040 Vss + 0.056 VDD VDD/2 + 0.025 Vss + 0.034 VDD VDD/2 + 0.033 Vss + 0.046 VDD VDD/2 + 0.022 Vss + 0.030 – – P2[4] + 1.367 P2[4] P2[4] – 1.208 P2[4] + 1.368 P2[4] P2[4] – 1.261 P2[4] + 1.369 P2[4] P2[4] – 1.262 P2[4] + 1.37 P2[4] P2[4] – 1.262 Unit V V V V V V V V V V V V – – V V V V V V V V V V V V Document Number: 38-12013 Rev. *S Page 31 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Table 22. 3.3-V DC Analog Reference Specifications (continued) Reference ARF_CR[5:3] Reference Power Settings RefPower = High Opamp bias = High Symbol Reference VREFHI VAGND VREFLO VREFHI RefPower = High Opamp bias = Low 0b110 RefPower = Med Opamp bias = High VAGND VREFLO VREFHI VAGND VREFLO VREFHI RefPower = Med Opamp bias = Low 0b111 All power settings. Not allowed for 3.3 V. VAGND VREFLO – Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low – Description 2 × BandGap BandGap Vss 2 × BandGap BandGap Vss 2 × BandGap BandGap Vss 2 × BandGap BandGap Vss – Min 2.507 1.203 Vss 2.516 1.241 Vss 2.510 1.240 Vss 2.515 1.258 Vss – Typ 2.598 1.307 Vss + 0.012 2.598 1.303 Vss + 0.007 2.599 1.305 Vss + 0.008 2.598 1.302 Vss + 0.005 – Max 2.698 1.424 Vss + 0.067 2.683 1.376 Vss + 0.040 2.693 1.374 Vss + 0.048 2.683 1.355 Vss + 0.03 – Unit V V V V V V V V V V V V – DC Analog PSoC Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 23. DC Analog PSoC Block Specifications Symbol RCT CSC Description Resistor unit value (continuous time) Capacitor unit value (switch cap) Min – – Typ 12.2 80 Max – – Unit kΩ fF Notes Document Number: 38-12013 Rev. *S Page 32 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 DC POR, SMP, and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 24. DC POR, SMP, and LVD Specifications Symbol VPPOR0R VPPOR1R VPPOR2R VPPOR0 VPPOR1 VPPOR2 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 Description VDD value for PPOR trip (positive ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b VDD value for PPOR trip (negative ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b PPOR hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b VDD value for LVD trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b VDD value for SMP trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min Typ 2.91 4.39 4.55 2.82 4.39 4.55 92 0 0 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 3.02 3.10 3.25 4.19 4.64 4.73 4.82 5.00 Max Units V V V V V V mV mV mV V V V V V V V V V V V V V V V V Notes – – – – – – – 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.96 3.03 3.18 4.11 4.55 4.63 4.72 4.90 – – – 2.98[11] 3.08 3.20 4.08 4.57 4.74[12] 4.82 4.91 3.08 3.16 3.32 4.28 4.74 4.82 4.91 5.10 Notes 11. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. 12. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply. Document Number: 38-12013 Rev. *S Page 33 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 25. DC Programming Specifications Symbol VDDP Description VDD for programming and erase 4.5 VDDLV Low VDD for verify 3 VDDHV High VDD for verify 5.1 VDDIWRITE Supply voltage for flash write operation 3.15 IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR Supply current during programming or verify Input low voltage during programming or verify Input high voltage during programming or verify Input current when applying Vilp to P1[0] or P1[1] during programming or verify Input current when applying Vihp to P1[0] or P1[1] during programming or verify Output low voltage during programming or verify Output high voltage during programming or verify Flash endurance (per block) Flash endurance (total)[14] Flash data retention – – 2.2 – – – VDD – 1.0 50,000 [13] Min Typ 5 Max 5.5 Units V Notes This specification applies to the functional requirements of external programmer tools. This specification applies to the functional requirements of external programmer tools. This specification applies to the functional requirements of external programmer tools. This specification applies to this device when it is executing internal flash writes. 3.1 3.2 V 5.2 5.3 V 5.25 10 – – – – – – – – – 30 0.8 – 0.2 1.5 VSS + 0.75 VDD – – – V mA V V mA mA V V – – Years Driving internal pull-down resistor Driving internal pull-down resistor Erase/write cycles per block Erase/write cycles 1,800,000 10 DC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 26. DC I2C Specifications Parameter VILI2C[15] VIHI2C[15] Input low level Input high level Description Min – – 0.7 × VDD Typ – – – Max 0.3 × VDD 0.25 × VDD – Units V V V Notes 3.0 V ≤ VDD ≤ 3.6 V 4.75 V ≤ VDD ≤ 5.25 V 3.0 V ≤ VDD ≤ 5.25 V Notes 13. The 50,000 cycle flash endurance per block is only guaranteed if the flash is operating within one voltage range. Voltage ranges are 3.0 V to 3.6 V and 4.75 V to 5.25 V. 14. A maximum of 36 × 50,000 block endurance cycles is allowed. This may be balanced between operations on 36 × 1 blocks of 50,000 maximum cycles each, 36 × 2 blocks of 25,000 maximum cycles each, or 36 × 4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36 × 50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs application note Design Aids – Reading and Writing PSoC® Flash – AN2015 for more information. 15. All GPIOs meet the DC GPIO VIL and VIH specifications found in the DC GPIO specifications sections.The I2C GPIO pins also meet the mentioned specs. Document Number: 38-12013 Rev. *S Page 34 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 AC Electrical Characteristics AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Note See the individual user module datasheets for information on maximum frequencies for user modules. Table 27. AC Chip-Level Specifications Symbol FIMO24 Description Internal main oscillator (IMO) frequency for 24 MHz Min 23.4 Typ 24 Max 24.6 [16,17] Units MHz Notes Trimmed for 5 V or 3.3 V operation using factory trim values. See Figure 10 on page 19. SLIMO Mode = 0. Trimmed for 5 V or 3.3 V operation using factory trim values. See Figure 10 on page 19. SLIMO Mode = 1. SLIMO Mode = 0. SLIMO Mode = 0. Refer to AC Digital Block Specifications on page 40. FIMO6 IMO frequency for 6 MHz 5.5 6 6.5[16,17] MHz FCPU1 FCPU2 F48M F24M F32K1 F32K2 F32K_U CPU frequency (5 V Nominal) CPU frequency (3.3 V Nominal) Digital PSoC block frequency Digital PSoC block frequency Internal low speed oscillator frequency External crystal oscillator 0.0914 0.0914 0 0 15 – 24 12 48 24 32 32.768 24.6[16] 12.3 [17] MHz MHz MHz MHz kHz kHz 49.2[16,18] 24.6[18] 64 – Accuracy is capacitor and crystal dependent. 50% duty cycle After a reset and before the M8C starts to run, the ILO is not trimmed. See the System Resets section of the PSoC Technical Reference Manual for details on this timing A multiple (x732) of crystal frequency Internal low speed oscillator (ILO) untrimmed frequency 5 – 100 kHz FPLL TPLLSLEW TPLLSLEWLOW TOS TOSACC PLL frequency PLL lock time PLL lock time for low gain setting External crystal oscillator startup to 1% External crystal oscillator startup to 100 ppm – 0.5 0.5 – – 23.986 – – 250 300 – 10 50 500 600 MHz ms ms ms ms The crystal oscillator frequency is within 100 ppm of its final value by the end of the TOSACC period. Correct operation assumes a properly loaded 1 µW maximum drive level 32.768 kHz crystal. 3.0 V ≤ VDD ≤ 5.5 V, –40 °C ≤ TA ≤ 85 °C. TXRST DC24M DCILO Step24M Fout48M External reset pulse width 24 MHz duty cycle Internal low speed oscillator duty cycle 24 MHz trim step size 48 MHz output frequency 10 40 20 – 46.8 – 50 50 50 48.0 – 60 80 – 49.2[16, 17] μs % % kHz MHz Trimmed. Using factory trim values Notes 16. 4.75 V < VDD < 5.25 V. 17. 3.0 V < VDD < 3.6 V. See application note Adjusting PSoC® Trims for 3.3 V and 2.7 V Operation – AN2012 for information on trimming for operation at 3.3 V. 18. See the individual user module datasheets for information on maximum frequencies for user modules Document Number: 38-12013 Rev. *S Page 35 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Table 27. AC Chip-Level Specifications (continued) Symbol FMAX SRPOWER_UP TPOWERUP Description Maximum frequency of signal on row input or row output. Power supply slew rate Time from end of POR to CPU executing code Min – – – Typ – – 16 Max 12.3 250 100 Units MHz V/ms ms VDD slew rate during power-up Power-up from 0 V. See the System Resets section of the PSoC Technical Reference Manual N = 32 Notes tjit_IMO[19] 24 MHz IMO cycle-to-cycle jitter (RMS) 24 MHz IMO long term N cycle-to-cycle jitter (RMS) 24 MHz IMO period jitter (RMS) – – – – – – 200 300 100 200 300 100 700 900 400 800 1200 700 ps tjit_PLL [19] 24 MHz IMO cycle-to-cycle jitter (RMS) 24 MHz IMO long term N cycle-to-cycle jitter (RMS) 24 MHz IMO period jitter (RMS) ps N = 32 Figure 12. PLL Lock Timing Diagram PLL Enable TPLLSLEW 24 MHz FPLL PLL Gain 0 Figure 13. PLL Lock for Low Gain Setting Timing Diagram PLL Enable TPLLSLEWLOW 24 MHz FPLL PLL Gain 1 Figure 14. External Crystal Oscillator Startup Timing Diagram 32K Select TOS 32 kHz F32K2 Note 19. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information. Document Number: 38-12013 Rev. *S Page 36 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 AC General Purpose I/O Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 28. AC GPIO Specifications Symbol FGPIO tRiseF tFallF tRiseS tFallS Description GPIO operating frequency Rise time, normal strong mode, Cload = 50 pF Fall time, normal strong mode, Cload = 50 pF Rise time, slow strong mode, Cload = 50 pF Fall time, slow strong mode, Cload = 50 pF Min 0 3 2 10 10 Typ – – – 27 22 Max 12.3 18 18 – – Unit MHz ns ns ns ns Notes Normal strong mode VDD = 4.75 to 5.25 V, 10% to 90% VDD = 4.75 to 5.25 V, 10% to 90% VDD = 3 to 5.25 V, 10% to 90% VDD = 3 to 5.25 V, 10% to 90% Figure 15. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS AC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the analog continuous time PSoC block. Power = High and Opamp bias = High is not supported at 3.3 V. Table 29. 5-V AC Operational Amplifier Specifications Symbol tROA Description Rising settling time to 0.1% for a 1 V step (10 pF load, unity gain) Power = Low, Opamp bias = Low Power = Medium, Opamp bias = High Power = High, Opamp bias = High Falling settling time to 0.1% for a 1 V step (10 pF load, unity gain) Power = Low, Opamp bias = Low Power = Medium, Opamp bias = High Power = High, Opamp bias = High Rising slew rate (20% to 80%) of a 1 V step (10 pF load, unity gain) Power = Low, Opamp bias = Low Power = Medium, Opamp bias = High Power = High, Opamp bias = High Falling slew rate (20% to 80%) of a 1 V step (10 pF load, unity gain) Power = Low, Opamp bias = Low Power = Medium, Opamp bias = High Power = High, Opamp bias = High Gain bandwidth product Power = Low, Opamp bias = Low Power = Medium, Opamp bias = High Power = High, Opamp bias = High Noise at 1 kHz (Power = Medium, Opamp bias = High) Min – – – – – – 0.15 1.7 6.5 0.01 0.5 4.0 0.75 3.1 5.4 – Typ – – – – – – – – – – – – – – – 100 Max 3.9 0.72 0.62 5.9 0.92 0.72 – – – – – – – – – – Unit µs µs µs µs µs µs V/µs V/µs V/µs V/µs V/µs V/µs MHz MHz MHz nV/rt-Hz tSOA SRROA SRFOA BWOA ENOA Document Number: 38-12013 Rev. *S Page 37 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Table 30. 3.3-V AC Operational Amplifier Specifications Symbol tROA tSOA SRROA SRFOA BWOA ENOA Description Rising settling time to 0.1% of a 1 V Step (10 pF load, unity gain) Power = Low, Opamp bias = Low Power = Medium, Opamp bias = High Falling settling time to 0.1% of a 1 V Step (10 pF load, unity gain) Power = Low, Opamp bias = Low Power = Medium, Opamp bias = High Rising slew rate (20% to 80%) of a 1 V Step (10 pF load, unity gain) Power = Low, Opamp bias = Low Power = Medium, Opamp bias = High Falling slew rate (20% to 80%) of a 1 V Step (10 pF load, unity gain) Power = Low, Opamp bias = Low Power = Medium, Opamp bias = High Gain bandwidth product Power = Low, Opamp bias = Low Power = Medium, Opamp bias = High Noise at 1 kHz (Power = Medium, Opamp bias = High) Min – – – – 0.31 2.7 0.24 1.8 0.67 2.8 – Typ – – – – – – – – – – 100 Max 3.92 0.72 5.41 0.72 – – – – – – – Units µs µs µs µs V/µs V/µs V/µs V/µs MHz MHz nV/rt-Hz When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1 K resistance and the external capacitor. Figure 16. Typical AGND Noise with P2[4] Bypass   nV/rtHz 10000 0 0.01 0.1 1.0 10 1000 100 0.001 0.01 0.1 Freq (kHz) 1 10 100 At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level. Document Number: 38-12013 Rev. *S Page 38 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Figure 17. Typical Opamp Noise nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000 100 10 0.001 0.01 0.1 Freq (kHz) 1 10 100 AC Low-Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, or 2.4 V to 3.0 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V at 25 °C and are for design guidance only. Table 31. AC Low-Power Comparator Specifications Symbol tRLPC Description LPC response time Min Typ Max Unit – – 50 µs Notes ≥ 50 mV overdrive comparator reference set within VREFLPC Document Number: 38-12013 Rev. *S Page 39 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 AC Digital Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 32. AC Digital Block Specifications Function All functions Description Block input clock frequency VDD ≥ 4.75 V VDD < 4.75 V Timer Input clock frequency No capture, VDD ≥ 4.75 V No capture, VDD < 4.75 V With capture Capture pulse width Counter Input clock frequency No enable input, VDD ≥ 4.75 V No enable input, VDD < 4.75 V With enable input Enable input pulse width Dead Band Kill pulse width Asynchronous restart mode Synchronous restart mode Disable mode Input clock frequency VDD ≥ 4.75 V VDD < 4.75 V CRCPRS (PRS Mode) Input clock frequency VDD ≥ 4.75 V VDD < 4.75 V CRCPRS (CRC Mode) SPIM SPIS Input clock frequency Input clock frequency Input clock (SCLK) frequency Width of SS_negated between transmissions Transmitter Input clock frequency VDD ≥ 4.75 V, 2 stop bits VDD ≥ 4.75 V, 1 stop bit VDD < 4.75 V Receiver Input clock frequency VDD ≥ 4.75 V, 2 stop bits VDD ≥ 4.75 V, 1 stop bit VDD < 4.75 V – – – – – – 49.2 24.6 24.6 MHz MHz MHz – – – – – – 49.2 24.6 24.6 MHz MHz MHz The baud rate is equal to the input clock frequency divided by 8 – – – – – 50[20] – – – – – – 49.2 24.6 24.6 8.2 4.1 – MHz MHz MHz MHz MHz ns The baud rate is equal to the input clock frequency divided by 8 The SPI serial clock (SCLK) frequency is equal to the input clock frequency divided by 2 The input clock is the SPI SCLK in SPIS mode – – – – 49.2 24.6 MHz MHz 20 50 [20] Min – – – – – 50[20] – – – 50[20] Typ – – – – – – – – – – – – – Max 49.2 24.6 49.2 24.6 24.6 – 49.2 24.6 24.6 – – – – Unit MHz MHz MHz MHz MHz ns MHz MHz MHz ns ns ns ns Notes 50[20] Note 20. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). Document Number: 38-12013 Rev. *S Page 40 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 AC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 33. 5-V AC Analog Output Buffer Specifications Symbol tROB tSOB SRROB SRFOB BWOB BWOB Description Rising settling time to 0.1%, 1 V Step, 100 pF load Power = Low Power = High Falling settling time to 0.1%, 1 V step, 100 pF load Power = Low Power = High Rising slew rate (20% to 80%), 1 V step, 100 pF load Power = Low Power = High Falling slew rate (80% to 20%), 1 V step, 100 pF load Power = Low Power = High Small signal bandwidth, 20 mVpp, 3 dB BW, 100 pF load Power = Low Power = High Large signal bandwidth, 1 Vpp, 3 dB BW, 100 pF load Power = Low Power = High Min – – – – 0.5 0.5 0.55 0.55 0.8 0.8 300 300 Typ – – – – – – – – – – – – Max 4 4 3.4 3.4 – – – – – – – – Unit µs µs µs µs V/µs V/µs V/µs V/µs MHz MHz kHz kHz Table 34. 3.3-V AC Analog Output Buffer Specifications Symbol tROB tSOB SRROB SRFOB BWOB BWOB Description Rising settling time to 0.1%, 1 V Step, 100 pF load Power = Low Power = High Falling settling time to 0.1%, 1 V Step, 100 pF load Power = Low Power = High Rising slew rate (20% to 80%), 1 V Step, 100 pF load Power = Low Power = High Falling slew rate (80% to 20%), 1 V Step, 100 pF load Power = Low Power = High Small signal bandwidth, 20 mVpp, 3 dB BW, 100 pF load Power = Low Power = High Large signal bandwidth, 1 Vpp, 3 dB BW, 100 pF load Power = Low Power = High Min – – – – 0.36 0.36 0.40 0.40 0.7 0.7 200 200 Typ – – – – – – – – – – – – Max 4.7 4.7 4 4 – – – – – – – – Unit µs µs µs µs V/µs V/µs V/µs V/µs MHz MHz kHz kHz AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 35. 5-V AC External Clock Specifications Symbol FOSCEXT – – – Frequency High period Low period Power-up IMO to switch Description Min 0.093 20.6 20.6 150 Typ – – – – Max 24.6 5300 – – Unit MHz ns ns ms Document Number: 38-12013 Rev. *S Page 41 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Table 36. 3.3-V AC External Clock Specifications Symbol FOSCEXT FOSCEXT – – – Description Frequency with CPU clock divide by 1 Frequency with CPU clock divide by 2 or greater High period with CPU clock divide by 1 Low period with CPU clock divide by 1 Power-up IMO to switch Min 0.093 0.186 41.7 41.7 150 Typ – – – – – Max 12.3 24.6 5300 – – Unit MHz MHz ns ns µs AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 37. AC Programming Specifications Symbol tRSCLK tFSCLK tSSCLK tHSCLK FSCLK tERASEB tWRITE tDSCLK tDSCLK3 tERASEALL tPROGRAM_HOT tPROGRAM_COLD Rise time of SCLK Fall time of SCLK Data setup time to falling edge of SCLK Data hold time from falling edge of SCLK Frequency of SCLK Flash erase time (block) Flash block write time Data out delay from falling edge of SCLK Data out delay from falling edge of SCLK Flash erase time (Bulk) Flash block erase + Flash block write time Flash block erase + Flash block write time Description Min 1 1 40 40 0 – – – – – – – Typ – – – – – 10 40 – – 80 – – Max 20 20 – – 8 – – 45 50 – 100[21] 200[21] Unit ns ns ns ns MHz ms ms ns ns ms ms ms – – – – – – – VDD > 3.6 3.0 ≤ VDD ≤ 3.6 Erase all blocks and protection fields at once 0 °C ≤ Tj ≤ 100 °C –40 °C ≤ Tj ≤ 0 °C Notes Note 21. For the full industrial range, you must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs application note Design Aids – Reading and Writing PSoC® Flash – AN2015 for more information. Document Number: 38-12013 Rev. *S Page 42 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 38. AC Characteristics of the I2C SDA and SCL Pins Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated. LOW period of the SCL clock HIGH period of the SCL clock Setup time for a repeated START condition Data hold time Data setup time Setup time for STOP condition Bus free time between a STOP and START condition Pulse width of spikes are suppressed by the input filter. Description Standard Mode Min 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 – Max 100 – – – – – – – – – Fast Mode Min 0 0.6 1.3 0.6 0.6 0 100[22] 0.6 1.3 0 Max 400 – – – – – – – – 50 Unit kHz µs µs µs µs µs ns µs µs ns Figure 18. Definition for Timing for Fast/Standard Mode on the I2C Bus I2C_SDA TSUDATI2C THDSTAI2C I2C_SCL TSPI2C THDDATI2CTSUSTAI2C TBUFI2C THIGHI2C TLOWI2C S START Condition Sr Repeated START Condition TSUSTOI2C P STOP Condition S Note 22. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT >= 250 ns must then be met. This is the automatic case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the standard-mode I2C-bus specification) before the SCL line is released. Document Number: 38-12013 Rev. *S Page 43 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Packaging Information This section illustrates the packaging specifications for the CY8C29x66 PSoC device, along with the thermal impedances for each package and the typical package capacitance on crystal pins. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the emulator pod drawings at http://www.cypress.com. Packaging Dimensions Figure 19. 28-Pin (300-Mil) Molded DIP SEE LEAD END OPTION 14 1 DIMENSIONS IN INCHES[MM] 0.260[6.60] 0.295[7.49] MIN. MAX. REFERENCE JEDEC MO-095 PACKAGE WEIGHT: 2.15gms PART # STANDARD PKG. LEAD FREE PKG. 15 28 0.030[0.76] 0.080[2.03] P28.3 PZ28.3 SEATING PLANE 1.345[34.16] 1.385[35.18] 0.290[7.36] 0.325[8.25] 0.120[3.05] 0.140[3.55] 0.009[0.23] 0.012[0.30] 0.310[7.87] 0.385[9.78] SEE LEAD END OPTION 3° MIN. 0.140[3.55] 0.190[4.82] 0.115[2.92] 0.160[4.06] 0.055[1.39] 0.065[1.65] 0.015[0.38] 0.020[0.50] 0.015[0.38] 0.060[1.52] 0.090[2.28] 0.110[2.79] LEAD END OPTION (LEAD #1, 14, 15 & 28) 51-85014 *E Document Number: 38-12013 Rev. *S Page 44 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Figure 20. 28-Pin (210-Mil) SSOP 51-85079 *E Figure 21. 28-Pin (300-Mil) SOIC 51-85026 *F Document Number: 38-12013 Rev. *S Page 45 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Figure 22. 44-Pin TQFP 51-85064 *E Figure 23. 48-Pin (7 × 7 mm) QFN SOLDERABLE EXPOSED PAD 001-12919 *C Document Number: 38-12013 Rev. *S Page 46 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Figure 24. 48-Pin (300-Mil) SSOP .020 24 1 0.395 0.420 0.292 0.299 DIMENSIONS IN INCHES MIN. MAX. 25 48 0.620 0.630 0.088 0.092 0.095 0.110 SEATING PLANE GAUGE PLANE .010 0.005 0.010 0.025 BSC 0.004 0.008 0.0135 0.008 0.016 0°-8° 0.024 0.040 51-85061 *D Figure 25. 48-Pin QFN 7 × 7 × 0.90 mm (Sawn Type) 001-13191 *E Document Number: 38-12013 Rev. *S Page 47 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Figure 26. 100-Pin TQFP 51-85048 *E Important Note For information on the preferred dimensions for mounting the QFN packages, see the application note Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages available at http://www.amkor.com. Important Note Pinned vias for thermal conduction are not required for the low-power PSoC device. Document Number: 38-12013 Rev. *S Page 48 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Thermal Impedances Table 39. Thermal Impedances per Package Package 28-pin PDIP 28-pin SSOP 28-pin SOIC 44-pin TQFP 48-pin SSOP 48-pin QFN[24] 100-pin TQFP Typical θJA[ 69 °C/W 94 °C/W 67 °C/W 60 °C/W 69 °C/W 28 °C/W 50 °C/W 23] Capacitance on Crystal Pins Table 40. Typical Package Capacitance on Crystal Pins Package 28-pin PDIP 28-pin SSOP 28-pin SOIC 44-pin TQFP 48-pin SSOP 48-pin QFN 100-pin TQFP Package Capacitance 3.5 pF 2.8 pF 2.7 pF 2.6 pF 3.3 pF 1.8 pF 3.1 pF Solder Reflow Specifications Table 41 shows the solder reflow temperature limits that must not be exceeded. Table 41. Solder Reflow Specifications Package 28-pin PDIP 28-pin SSOP 28-pin SOIC 44-pin TQFP 48-pin SSOP 48-pin QFN 100-pin TQFP Maximum Peak Temperature (TC) Maximum Time above TC – 5 °C 260 °C 260 °C 260 °C 260 °C 260 °C 260 °C 260 °C 30 seconds 30 seconds 30 seconds 30 seconds 30 seconds 30 seconds 30 seconds Notes 23. TJ = TA + POWER × θJA. 24. To achieve the thermal impedance specified for the QFN package, refer to the application notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages available at http://www.amkor.com. Document Number: 38-12013 Rev. *S Page 49 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Development Tool Selection This section presents the development tools available for all current PSoC device families including the CY8C29x66 family. Evaluation Tools All evaluation tools can be purchased from the Cypress online store. CY3210-MiniProg1 Software PSoC Designer™ At the core of the PSoC development software suite is PSoC Designer, used to generate PSoC firmware applications. PSoC Designer is available free of charge at http://www.cypress.com and includes a free C compiler. PSoC Programmer The CY3210-MiniProg1 kit allows a user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes: ■ ■ ■ ■ ■ ■ ■ MiniProg programming unit MiniEval socket programming and evaluation board 28-pin CY8C29466-24PXI PDIP PSoC device sample 28-pin CY8C27443-24PXI PDIP PSoC device sample PSoC Designer software CD Getting Started guide USB 2.0 cable Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free of charge at http://www.cypress.com. Development Kits All development kits can be purchased from the Cypress Online Store. CY3215-DK Basic Development Kit CY3210-PSoCEval1 The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation and the software interface allows users to run, halt, and single step the processor and view the content of specific memory locations. Advance emulation features also supported through PSoC Designer. The kit includes: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: ■ ■ ■ ■ ■ ■ Evaluation board with LCD module MiniProg programming unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2) PSoC Designer software CD Getting Started guide USB 2.0 cable PSoC Designer software CD ICE-Cube In-Circuit Emulator ICE Flex-Pod for CY8C29x66 family Cat-5 adapter Mini-Eval programming board 110 ~ 240 V power supply, Euro-Plug adapter iMAGEcraft C compiler ISSP cable USB 2.0 cable and Blue Cat-5 cable Two CY8C29466-24PXI 28-PDIP chip samples CY3214-PSoCEvalUSB The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special features of the board include both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of bread boarding space to meet all of your evaluation needs. The kit includes: ■ ■ ■ ■ ■ ■ ■ PSoCEvalUSB board LCD module MIniProg programming unit Mini USB cable PSoC Designer and example projects CD Getting Started guide Wire pack Document Number: 38-12013 Rev. *S Page 50 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Device Programmers All device programmers can be purchased from the Cypress Online Store. CY3216 Modular Programmer CY3207ISSP In-System Serial Programmer (ISSP) The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes: ■ ■ ■ ■ ■ ■ The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. Note CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes: ■ ■ ■ ■ CY3207 programmer unit PSoC ISSP software CD 110 ~ 240 V power supply, Euro-Plug adapter USB 2.0 cable Modular programmer base Three programming module cards MiniProg programming unit PSoC Designer software CD Getting Started guide USB 2.0 cable Accessories (Emulation and Programming) Table 42. Emulation and Programming Accessories Part # CY8C29466-24PXI CY8C29466-24PVXI CY8C29466-24SXI CY8C29566-24AXI CY8C29666-24PVXI CY8C29666-24LTXI CY8C29866-24AXI Pin Package 28-pin PDIP 28-pin SSOP 28-pin SOIC 44-pin TQFP 48-pin SSOP 48-pin QFN Flex-Pod Kit[25] CY3250-29XXX CY3250-29XXX CY3250-29XXX CY3250-29XXX CY3250-29XXX CY3250-29XXXQFN Foot Kit[26] CY3250-28PDIP-FK CY3250-28SSOP-FK CY3250-28SOIC-FK CY3250-44TQFP-FK CY3250-48SSOP-FK CY3250-48QFN-FK CY3250-100TQFP-FK Adapter[27] Adapters can be found at http://www.emulation.com. 100-pin TQFP CY3250-29XXX Notes 25. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. 26. Foot kit includes surface mount feet that can be soldered to the target PCB. 27. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com Document Number: 38-12013 Rev. *S Page 51 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Ordering Information The following table lists the CY8C29x66 PSoC device’s key package features and ordering codes. Analog PSoC Blocks Switch Mode Pump Temperature Range Digital PSoC Blocks Digital I/O Pins XRES Pin Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes [+] Feedback Ordering Code Package 28-pin (300-mil) DIP 28-pin (210-mil) SSOP 28-pin (210-mil) SSOP (Tape and Reel) 28-pin (300-mil) SOIC 28-pin (300-mil) SOIC (Tape and Reel) 44-pin TQFP 44-pin TQFP (Tape and Reel) 48-pin (300-mil) SSOP 48-pin (300-mil) SSOP (Tape and Reel) 100-Pin TQFP 100-Pin OCD TQFP[28] 48-Pin (7 × 7 × 1.0 mm) QFN (Sawn) 48-Pin (7 × 7 × 1.0 mm) QFN (Sawn) CY8C29466-24PXI CY8C29466-24PVXI CY8C29466-24PVXIT CY8C29466-24SXI CY8C29466-24SXIT CY8C29566-24AXI CY8C29566-24AXIT CY8C29666-24PVXI CY8C29666-24PVXIT CY8C29866-24AXI CY8C29000-24AXI CY8C29666-24LTXI CY8C29666-24LTXIT 32 32 32 32 32 32 32 32 32 32 32 32 32 2 2 2 2 2 2 2 2 2 2 2 2 2 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C –40 °C to +85 °C 16 16 16 16 16 16 16 16 16 16 16 16 16 12 12 12 12 12 12 12 12 12 12 12 12 12 24 24 24 24 24 40 40 44 44 64 64 44 44 12 12 12 12 12 12 12 12 12 12 12 12 12 Note For Die sales information, contact a local Cypress sales office or field applications engineer (FAE). Ordering Code Definitions CY 8 C 29 xxx-SPxx Package Type: PX = PDIP Pb-free SX = SOIC Pb-free PVX = SSOP Pb-free LFX/LKX/LTX/LQX/LCX = QFN Pb-free AX = TQFP Pb-free Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress Thermal Rating: C = Commercial I = Industrial E = Extended Note 28. This part may be used for in-circuit debugging. It is NOT available for production. Document Number: 38-12013 Rev. *S Page 52 of 61 Analog Outputs 4 4 4 4 4 4 4 4 4 4 4 4 4 Analog Inputs Flash (KB) RAM (KB) CY8C29466, CY8C29566 CY8C29666, CY8C29866 Acronyms Acronyms Used Table 43 lists the acronyms that are used in this document. Table 43. Acronyms Used in this Datasheet Acronym AC ADC API CMOS CPU CRC CT DAC DC DTMF ECO EEPROM GPIO ICE IDE ILO IMO I/O IrDA ISSP LCD LED LPC LVD MAC MCU alternating current analog-to-digital converter application programming interface complementary metal oxide semiconductor central processing unit cyclic redundancy check continuous time digital-to-analog converter direct current dual-tone multi-frequency external crystal oscillator electrically erasable programmable read-only memory general purpose I/O in-circuit emulator integrated development environment internal low speed oscillator internal main oscillator input/output infrared data association in-system serial programming liquid crystal display light-emitting diode low power comparator low voltage detect multiply-accumulate microcontroller unit Description Acronym MIPS OCD PCB PDIP PGA PLL POR PPOR PRS PSoC® PWM QFN RTC SAR SC SMP SOIC SPI SRAM SROM SSOP TQFP UART USB WDT XRES on-chip debug printed circuit board plastic dual-in-line package programmable gain amplifier phase-locked loop power on reset precision power on reset pseudo-random sequence Programmable System-on-Chip pulse width modulator quad flat no leads real time clock successive approximation switched capacitor switch mode pump small-outline integrated circuit serial peripheral interface static random access memory supervisory read only memory shrink small-outline package thin quad flat pack universal asynchronous reciever / transmitter universal serial bus watchdog timer external reset Description million instructions per second Reference Documents CY8CPLC20, CY8CLED16P01, CY8C29x66, CY8C27x43, CY8C24x94, CY8C24x23, CY8C24x23A, CY8C22x13, CY8C21x34, CY8C21x23, CY7C64215, CY7C603xx, CY8CNP1xx, and CYWUSB6953 PSoC® Programmable System-on-Chip Technical Reference Manual (TRM) (001-14463) Design Aids – Reading and Writing PSoC® Flash - AN2015 (001-40459) Adjusting PSoC® Trims for 3.3 V and 2.7 V Operation – AN2012 (001-17397) Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 (001-14503) Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages – available at http://www.amkor.com. Document Number: 38-12013 Rev. *S Page 53 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Document Conventions Units of Measure Table 44 lists the unit sof measures. Table 44. Units of Measure Symbol dB °C fF pF kHz MHz rt-Hz kΩ Ω µA mA nA pA µs Unit of Measure decibels degree Celsius femto farad picofarad kilohertz megahertz root hertz kilohm ohm microampere milliampere nanoampere pikoampere microsecond Symbol ms ns ps µV mV mVpp nV V µW W mm ppm % Unit of Measure millisecond nanosecond picosecond microvolts millivolts millivolts peak-to-peak nanovolts volts microwatts watt millimeter parts per million percent Numeric Conventions Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimals. Glossary active high 1. A logic signal having its asserted state as the logic 1 state. 2. A logic signal having the logic 1 state as the higher voltage of the two states. The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more. A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation. A series of software routines that comprise an interface between a computer application and lower level services and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create software applications. A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. A stable voltage reference design that matches the positive temperature coefficient of VT with the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference. 1. The frequency range of a message or information processing system measured in hertz. 2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. analog blocks analog-to-digital (ADC) Application programming interface (API) asynchronous bandgap reference bandwidth Document Number: 38-12013 Rev. *S Page 54 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Glossary (continued) bias 1. A systematic deviation of a value from a reference value. 2. The amount by which the average of a set of values departs from a reference value. 3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. 1. A functional unit that performs a single function, such as an oscillator. 2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or an analog PSoC block. 1. A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which data is written. 2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. An amplifier used to lower the output impedance of a system. 1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0]. 3. One or more conductors that serve as a common connection for a group of related devices. The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks. An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. A program that translates a high level language, such as C, into machine language. In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’. An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components. block buffer bus clock comparator compiler configuration space crystal oscillator cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear check (CRC) feedback shift register. Similar calculations may be used for a variety of other purposes such as data compression. data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions. A hardware and software system that allows you to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. A period of time when neither of two or more signals are in their active state or in transition. The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator, pseudo-random number generator, or SPI. debugger dead band digital blocks Document Number: 38-12013 Rev. *S Page 55 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Glossary (continued) digital-to-analog (DAC) duty cycle emulator A device that changes a digital signal to an analog signal of corresponding magnitude. The analogto-digital (ADC) converter performs the reverse operation. The relationship of a clock period high time to its low time, expressed as a percent. Duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop and return to a pre-defined state. An electrically programmable and erasable, non-volatile technology that provides you the programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is OFF. The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash space that may be protected. A Flash block holds 64 bytes. The number of cycles or events per unit of time, for a periodic function. The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually expressed in dB. A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5V and pulled high with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. The in-circuit emulator that allows you to test the project in a hardware environment, while viewing the debugging device activity in a software environment (PSoC Designer). External Reset (XRES) Flash Flash block frequency gain I2C ICE input/output (I/O) A device that introduces data into or extracts data from a system. interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends with the RETI instruction, returning the device to the point in the program where it left normal program execution. 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on serial data streams. 2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles. interrupt service routine (ISR) jitter low-voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a selected threshold. (LVD) M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the Flash, SRAM, and register space. Document Number: 38-12013 Rev. *S Page 56 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Glossary (continued) master device A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device. An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor. The reference to a circuit containing both analog and digital techniques and components. A device that imposes a signal on a carrier. 1. A disturbance that affects a signal and that may distort the information carried by the signal. 2. The random variations of one or more characteristics of any entity such as voltage, current, or data. A circuit that may be crystal controlled and is used to generate a clock frequency. A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names. A group of pins, usually eight. A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is a type of hardware reset. Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-onChip™ is a trademark of Cypress. microcontroller mixed-signal modulator noise oscillator parity Phase-locked loop (PLL) pinouts port Power on reset (POR) PSoC® PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology. pulse width An output in the form of duty cycle which varies as a function of the applied measurand modulator (PWM) RAM An acronym for random access memory. A data-storage device from which data can be read out and new data can be written in. A storage device with a specific capacity, such as a bit or byte. A means of bringing a system back to a know state. See hardware reset and software reset. An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in. register reset ROM Document Number: 38-12013 Rev. *S Page 57 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Glossary (continued) serial 1. Pertaining to a process in which all events occur one after the other. 2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel. The time it takes for an output signal or value to stabilize after the input has changed from one value to another. A memory storage device that sequentially shifts a word either left or right to output a stream of serial data. A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. The controlling device is called the master device. An acronym for static random access memory. A memory device where you can store and retrieve data at a high rate of speed. The term static is used because, after a value is loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is removed from the device. An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code, operating from Flash. A signal following a character or block that prepares the receiving device to receive the next character or block. 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. A system whose operation is synchronized by a clock signal. A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming Interface) for the peripheral function. The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program. A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V. A name for a power net meaning "voltage source." The most negative power supply signal. A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time. settling time shift register slave device SRAM SROM stop bit synchronous tri-state UART user modules user space VDD VSS watchdog timer Document Number: 38-12013 Rev. *S Page 58 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Document History Page Document Title: CY8C29466, CY8C29566, CY8C29666, CY8C29866 PSoC® Programmable System-on-Chip™ Document Number: 38-12013 Revision ECN Origin of Change Submission Date Description of Change ** *A *B *C *D *E *F *G *H 131151 132848 133205 133656 227240 240108 247492 288849 722736 New Silicon NWJ NWJ SFV SFV SFV SFV HMT HMT 11/13/2003 01/21/2004 01/27/2004 02/09/2004 06/01/2004 See ECN See ECN See ECN See ECN New document (Revision **). New information. First edition of preliminary datasheet. Changed part numbers, increased SRAM data storage to 2 K bytes. Changed part numbers and removed a 28-pin SOIC. Changes to Overview section, 48-pin MLF pinout, and significant changes to the Electrical Specs. Added a 28-lead (300 mil) SOIC part. New information added to the Electrical Specifications chapter. Add DS standards, update device table, fine-tune pinouts, add Reflow Peak Temp. table. Finalize. Add QFN package clarifications. Add new QFN diagram. Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add CY8C20x34 to PSoC Device Characteristics table. Update emulation pod/feet kit part numbers. Add OCD non-production pinouts and package diagrams. Add ISSP note to pinout tables. Update package diagram revisions. Update typical and recommended Storage Temperature per industrial specs. Update CY branding and QFN convention. Add new Dev. Tool section. Update copyright and trademarks. Pinout for CY8C29000 OCD wrongly included details of CY8C24X94. The correct pinout for CY8C29000 is included in this version. Added note on digital signaling in “DC Analog Reference Specifications” section. Added note to Ordering Information Changed title from “CY8C29466, CY8C29566, CY8C29666, and CY8C29866 PSoC Mixed Signal Array Final datasheet” to “CY8C29466, CY8C29566, CY8C29666, and CY8C29866 PSoC® Programmable System-on-Chip™” Updated to datasheet template Added 48-Pin QFN (Sawn) package diagram and CY8C29666-24LTXI and CY8C29666-24LTXIT part details in the Ordering Information table Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as follows: Modified FIMO6 (page 27), TWRITE specifications (page 34) Added IOH (page 21), IOL (page 21), DCILO (page 28), F32K_U (page 27), TPOWERUP (page 28), TERASEALL (page 34), TPROGRAM_HOT (page 34), and TPROGRAM_COLD (page 34) specifications Added SRPOWER_UP parameter in AC specs table.. Corrected Notes for VDD parameter in Table 13, “DC Chip-Level Specifications,” on page 20. Added “Contents” on page 2. Updated links in Sales, Solutions, and Legal Information. *I 2503350 DFK/PYRS See ECN *J *K 2545030 2708295 YARA JVY 07/29/08 04/22/2009 *L *M 2761941 2842762 DRSW/AESA DRSW 09/10/2009 01/08/2010 Document Number: 38-12013 Rev. *S Page 59 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Document Title: CY8C29466, CY8C29566, CY8C29666, CY8C29866 PSoC® Programmable System-on-Chip™ Document Number: 38-12013 Revision ECN Origin of Change Submission Date Description of Change *N 2902396 NJF 03/30/2010 Updated Digital System Block Diagram and content in Digital System Updated Cypress website links. Removed reference to PSoC Designer 4.4 in PSoC Designer Software Subsystems Added TBAKETEMP and TBAKETIME parameters in Absolute Maximum Ratings Updated AC Chip-Level Specifications Changed unit for SPIS function to ns in AC Digital Block Specifications Updated notes in Packaging Information and package diagrams. Updated Solder Reflow Specifications Updated Emulation and Programming Accessories Removed Third Party Tools and Build a PSoC Emulator into Your Board. Updated Ordering Information and Ordering Code Definitions. Updated content to match current style guide and datasheet template. No technical updates. Added PSoC Device Characteristics table . Added DC I2C Specifications table. Added F32K_U max limit. Added Tjit_IMO specification, removed existing jitter specifications. Updated Analog reference tables. Updated Units of Measure, Acronyms, Glossary, and References sections. Updated solder reflow specifications. No specific changes were made to AC Digital Block Specifications table and I2C Timing Diagram. They were updated for clearer understanding. Updated Figure 13 since the labelling for y-axis was incorrect. Template and styles update. Removed footnote reference for “Solder Reflow Peak Temperature” table. Removed the pruned part “CY8C29666-24LFXI” from the Ordering Information and Accessories (Emulation and Programming). Updated Logic Block Diagram. Updated Solder Reflow Specifications. Fixed page numbering error on footer. *O *P 2940410 3044869 YJI NJF 05/31/2010 10/01/2010 *Q *R *S 3017427 3263978 3301676 GDK NJF NJF 11/08/10 05/23/11 07/04/11 Document Number: 38-12013 Rev. *S Page 60 of 61 [+] Feedback CY8C29466, CY8C29566 CY8C29666, CY8C29866 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2003-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 38-12013 Rev. *S Revised July 7, 2011 Page 61 of 61 PSoC Designer™ and Programmable System-on-Chip™ are trademarks and PSoC® and CapSense® are registered trademarks of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback