CY8C24094, CY8C24794 CY8C24894, CY8C24994
PSoC® Programmable System-on-Chip™
PSoC® Programmable System-on-Chip
1. Features
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XRES pin to support in-system serial programming (ISSP) and external reset control in CY8C24894 Powerful Harvard-architecture processor ❐ M8C processor speeds up to 24 MHz ❐ Two 8 × 8 multiply, 32-bit accumulate ❐ Low power at high speed ❐ Operating voltage: 3 V to 5.25 V ❐ Industrial temperature range: –40 °C to +85 °C ❐ USB temperature range: –10 °C to +85 °C Advanced peripherals (PSoC® Blocks) ❐ Six rail-to-rail analog PSoC blocks provide: • Up to 14-bit analog-to-digital converters (ADCs) • Up to 9-bit digital-to-analog converters (DACs) • Programmable gain amplifiers (PGAs) • Programmable filters and comparators ❐ Four digital PSoC blocks provide: • 8- to 32-bit timers, counters, and pulse width modulators (PWMs) • Cyclical redundancy check (CRC) and pseudo random sequence (PRS) modules • Full-duplex universal asynchronous receiver transmitter (UART) • Multiple serial peripheral interface (SPI) masters or slaves • Connectable to all general-purpose I/O (GPIO) pins ❐ Complex peripherals by combining blocks ❐ Capacitive sensing application (CSA) capability Full speed USB (12 Mbps) ❐ Four unidirectional endpoints ❐ One bidirectional control endpoint ❐ USB 2.0 compliant ❐ Dedicated 256 byte buffer ❐ No external crystal required Flexible on-chip memory ❐ 16 KB flash program storage 50,000 erase and write cycles ❐ 1 KB static random access memory (SRAM) data storage ❐ ISSP ❐ Partial flash updates ❐ Flexible protection modes ❐ Electrically erasable programmable read-only memory (EEPROM) emulation in flash Programmable pin configurations ❐ 25-mA sink, 10-mA source on all GPIOs ❐ Pull-up, pull-down, high Z, strong, or open-drain drive modes on all GPIOs ❐ Up to 48 analog inputs on GPIOs ❐ Two 33 mA analog outputs on GPIOs ❐ Configurable interrupt on all GPIOs
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Precision, programmable clocking ❐ Internal ±4% 24- / 48-MHz main oscillator ❐ Internal oscillator for watchdog and sleep ❐ 0.25% accuracy for USB with no external components Additional system resources 2 ❐ I C slave, master, and multi-master to 400 kHz ❐ Watchdog and sleep timers ❐ User-configurable low voltage detection (LVD)
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2. Logic Block Diagram
Port 7 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Analog Drivers
System Bus
Global Digital Interconnect
Global Analog Interconnect
PSoC CORE
SRAM 1K Interrupt Controller SROM Flash16 KB Sleep and Watchdog
CPU Core (M8C) Clock Sources (Includes IMO and ILO)
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DIGITAL SYSTEM
Digital Block Array
ANALOG SYSTEM
Analog Ref.
Analog Block Array
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Digital 2 Decimator Clocks MACs Type 2
I2C
POR and LVD Internal Voltage System Resets Ref.
USB
Analog Input Muxing
SYSTEM RESOURCES
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Cypress Semiconductor Corporation Document Number: 38-12018 Rev. *Z
•
198 Champion Court
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San Jose, CA 95134-1709 • 408-943-2600 Revised January 3, 2011
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3. Contents
PSoC Functional Overview ................................................3 The PSoC Core .............................................................3 The Digital System ........................................................3 The Analog System .......................................................4 Additional System Resources .......................................5 PSoC Device Characteristics ........................................5 Getting Started ....................................................................6 Application Notes ..........................................................6 Development Kits ..........................................................6 Training .........................................................................6 CYPros Consultants ......................................................6 Solutions Library ............................................................6 Technical Support .........................................................6 Development Tools ............................................................6 PSoC Designer Software Subsystems ..........................6 Designing with PSoC Designer .........................................7 Select User Modules .....................................................7 Configure User Modules ................................................7 Organize and Connect ..................................................7 Generate, Verify, and Debug .........................................7 Pin Information ...................................................................8 56-Pin Part Pinout ........................................................8 56-Pin Part Pinout (with XRES) ....................................9 68-Pin Part Pinout .......................................................10 68-Pin Part Pinout (On-Chip Debug) ...........................11 100-Ball VFBGA Part Pinout .......................................12 100-Ball VFBGA Part Pinout (On-Chip Debug) ...........14 100-Pin Part Pinout (On-Chip Debug) .........................16 Register Reference ...........................................................18 Register Conventions ..................................................18 Register Mapping Tables ............................................18 Register Map Bank 0 Table: User Space ...................19 Register Map Bank 1 Table: Configuration Space .....20 Electrical Specifications ..................................................21 Absolute Maximum Ratings .........................................21 Operating Temperature ...............................................22 DC Electrical Characteristics .......................................22 AC Electrical Characteristics .......................................35 Thermal Impedance ....................................................43 Solder Reflow Peak Temperature ...............................43 Development Tool Selection ...........................................44 Software ......................................................................44 Development Kits ........................................................44 Evaluation Tools ..........................................................44 Device Programmers ...................................................44 Accessories (Emulation and Programming) ................45 Ordering Information ........................................................46 Ordering Code Definitions ...........................................47 Packaging Dimensions ....................................................47 Acronyms ..........................................................................51 Acronyms Used ...........................................................51 Document Conventions ...................................................52 Units of Measure .........................................................52 Numeric Conventions ..................................................52 Glossary ............................................................................52 Document History Page ...................................................57 Sales, Solutions, and Legal Information ........................59 Worldwide Sales and Design Support .........................59 Products ......................................................................59 PSoC Solutions ...........................................................59
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4. PSoC Functional Overview
The PSoC family consists of many devices with on-chip controllers. These devices are designed to replace multiple traditional MCU-based system components with one low-cost single-chip programmable component. A PSoC device includes configurable blocks of analog and digital logic, and programmable interconnect. This architecture makes it possible for you to create customized peripheral configurations, to match the requirements of each individual application. Additionally, a fast central processing unit (CPU), flash program memory, SRAM data memory, and configurable I/O are included in a range of convenient pinouts. The PSoC architecture, shown in “Logic Block Diagram” on page 1, consists of four main areas: the core, the system resources, the digital system, and the analog system. Configurable global bus resources allow combining all of the device resources into a complete custom system. Each CY8C24x94 PSoC device includes four digital blocks and six analog blocks. Depending on the PSoC package, up to 56 GPIOs are also included. The GPIOs provide access to the global digital and analog interconnects.
4.2 The Digital System
The digital system consists of four digital PSoC blocks. Each block is an 8-bit resource that is used alone or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals, which are called user modules. Digital peripheral configurations include:
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PWMs (8- to 32-bit) PWMs with dead band (8- to 32-bit) Counters (8- to 32-bit) Timers (8- to 32-bit) UART 8-bit with selectable parity SPI master and slave I2C slave and multi-master CRC/generator (8-bit) IrDA PRS generators (8- to 32-bit)
4.1 The PSoC Core
The PSoC core is a powerful engine that supports a rich instruction set. It encompasses SRAM for data storage, an interrupt controller, sleep and watchdog timers, and internal main oscillator (IMO) and internal low speed oscillator (ILO). The CPU core, called the M8C, is a powerful processor with speeds up to 24 MHz. The M8C is a four-million instructions per second (MIPS) 8-bit Harvard-architecture microprocessor. System resources provide these additional capabilities:
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The digital blocks are connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by PSoC device family. This allows the optimum choice of system resources for your application. Family resources are shown in Table 1 on page 5. Figure 1. Digital System Block Diagram
Port 7 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
Digital clocks for increased flexibility I2C functionality to implement an I2C master and slave An internal voltage reference, multi-master, that provides an absolute value of 1.3 V to a number of PSoC subsystems A switch mode pump (SMP) that generates normal operating voltages from a single battery cell Various system resets supported by the M8C
Digital Clocks From Core
To System Bus
To Analog System
Row Input Configuration
The digital system consists of an array of digital PSoC blocks that may be configured into any number of digital peripherals. The digital blocks are connected to the GPIOs through a series of global buses. These buses can route any signal to any pin, freeing designs from the constraints of a fixed peripheral controller. The analog system consists of six analog PSoC blocks, supporting comparators, and analog-to-digital conversion up to 10-bits of precision.
DIGITAL SYSTEM
Digital PSoC Block Array
8 8
Row 0
DBB00 DBB01 DCB02
4 DCB03 4
8 8
Row Output Configuration
GIE[7:0] GIO[7:0]
Global Digital Interconnect
GOE[7:0] GOO[7:0]
Document Number: 38-12018 Rev. *Z
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4.3 The Analog System
The analog system is composed of six configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are as follows.
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Figure 2. Analog System Block Diagram
A ll IO (E x c e p t P o r t 7 ) P 0 [7 ] P 0 [5 ] P 0 [3 ] P 0 [1 ] AGNDIn RefIn Mux Bus Analog P 0 [6 ] P 0 [4 ] P 0 [2 ] P 0 [0 ] P 2 [6 ]
ADCs (up to two, with 6- to 14-bit resolution, selectable as incremental, delta sigma, and successive approximation register (SAR)) Filters (2 and 4 pole band-pass, low-pass, and notch) Amplifiers (up to two, with selectable gain to 48x) Instrumentation amplifiers (one with selectable gain to 93x) Comparators (up to two, with 16 selectable thresholds) DACs (up to two, with 6- to 9-bit resolution) Multiplying DACs (up to two, with 6- to 9-bit resolution) High current output drivers (two with 30 mA drive as a PSoC core resource) 1.3-V reference (as a system resource) DTMF dialer Modulators Correlators Peak detectors Many other topologies possible
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P 2 [3 ]
P 2 [4 ] P 2 [2 ] P 2 [0 ]
P 2 [1 ]
A C I 0 [1 :0 ]
A C I 1 [1 :0 ]
A r r a y In p u t C o n f ig u r a t io n
B lo c k A rray
AC B00 A SC 10 ASD20
A C B 01 A SD 11 A SC 21
A n a lo g R e f e r e n c e
In t e r f a c e t o D ig it a l S y s t e m R e fH i R e fL o AGND R e fe r e n c e G e n e ra to rs A G N D In R e fIn B andgap
Analog blocks are arranged in a column of three, which includes one continuous time (CT) and two switched capacitor (SC) blocks, as shown in Figure 2.
M 8 C In t e r f a c e ( A d d r e s s B u s , D a t a B u s , E t c .)
4.3.1 The Analog Multiplexer System The analog mux bus can connect to every GPIO pin in ports 0–5. Pins are connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with comparators and analog-to-digital converters. It is split into two sections for simultaneous dual-channel processing. An additional 8:1 analog input multiplexer provides a second path to bring Port 0 pins to the analog array. Switch-control logic enables selected pins to precharge continuously under hardware control. This enables capacitive measurement for applications such as touch sensing. Other multiplexer applications include:
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Track pad, finger sensing Chip-wide mux that enables analog input from up to 48 I/O pins Crosspoint connection between any I/O pin combinations
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4.4 Additional System Resources
System resources provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, low-voltage detection, and power-on reset (POR). Brief statements describing the merits of each resource follow.
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Decimator provides a custom hardware filter for digital signal processing applications including creation of Delta Sigma ADCs. The I2C module provides 100- and 400-kHz communication over two wires. Slave, master, multi-master are supported. Low-voltage detection interrupts signal the application of falling voltage levels, while the advanced POR circuit eliminates the need for a system supervisor. An internal 1.3-V reference provides an absolute reference for the analog system, including ADCs and DACs. Versatile analog multiplexer system.
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Full speed USB (12 Mbps) with five configurable endpoints and 256 bytes of RAM. No external components required except for two series resistors. Wider than commercial temperature USB operation (–10 °C to +85 °C). Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks are generated using digital PSoC blocks as clock dividers. Two multiply accumulates (MACs) provide fast 8-bit multipliers with 32-bit accumulate, to assist in both general math and digital filters.
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4.5 PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. The following table lists the resources available for specific PSoC device groups. The device covered by this datasheet is shown in the highlighted row of the table. Table 1. PSoC Device Characteristics
PSoC Part Number CY8C29x66 CY8C28xxx CY8C27x43 CY8C24x94 CY8C24x23A CY8C23x33 CY8C22x45 CY8C21x45 CY8C21x34 CY8C21x23 CY8C20x34 CY8C20xx6 Digital I/O up to 64 up to 44 up to 44 up to 56 up to 24 up to 26 up to 38 up to 24 up to 28 up to 16 up to 28 up to 36 Digital Rows 4 up to 3 2 1 1 1 2 1 1 1 0 0 Digital Blocks 16 up to 12 8 4 4 4 8 4 4 4 0 0 Analog Inputs up to 12 up to 44 up to 12 up to 48 up to 12 up to 12 up to 38 up to 24 up to 28 up to 8 up to 28 up to 36 Analog Outputs 4 up to 4 4 2 2 2 0 0 0 0 0 0 Analog Columns 4 up to 6 4 2 2 2 4 4 2 2 0 0 Analog Blocks 12 up to 12 + 4[1] 12 6 6 4 6[1] 6[1] 4
[1]
SRAM Size 2K 1K 256 1K 256 256 1K 512 512 256 512 up to 2K
Flash Size 32 K 16 K 16 K 16 K 4K 8K 16 K 8K 8K 4K 8K up to 32 K
4[1] 3[1,2] 3
[1,2]
Notes 1. Limited analog functionality. 2. Two analog blocks and one CapSense®.
Document Number: 38-12018 Rev. *Z
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5. Getting Started
For in-depth information, along with detailed programming information, see the Technical Reference Manual for this PSoC device. For up-to-date ordering, packaging, and electrical specification information, see the latest PSoC device datasheets on the web at http://www.cypress.com. covers a wide variety of topics and skill levels to assist you in your designs.
5.4 CYPros Consultants
Certified PSoC consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC consultant go to the CYPros Consultants web site.
5.1 Application Notes
Cypress application notes are an excellent introduction to the wide variety of possible PSoC designs.
5.5 Solutions Library
Visit our growing library of solution-focused designs. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly.
5.2 Development Kits
PSoC Development Kits are available online from and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark.
5.6 Technical Support
Technical support – including a searchable Knowledge Base articles and technical forums – is also available online. If you cannot find an answer to your question, call our Technical Support hotline at 1-800-541-4736.
5.3 Training
Free PSoC technical training (on demand, webinars, and workshops), which is available online via www.cypress.com,
6. Development Tools
PSoC Designer™ is the revolutionary Integrated Design Environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes:
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the PSoC blocks, which are called user modules. Examples of user modules are analog-to-digital converters (ADCs), digital-to-analog converters (DACs), amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this allows you to use more than 100 percent of PSoC's resources for an application. 6.1.2 Code Generation Tools The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. You can develop your design in C, assembly, or a combination of the two. Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and are linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. 6.1.3 Debugger PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and Page 6 of 59
Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration Extensive user module catalog Integrated source-code editor (C and assembly) Free C compiler with no size restrictions or time limits Built-in debugger In-circuit emulation
Built-in support for communication interfaces: 2 ❐ Hardware and software I C slaves and masters ❐ Full speed USB 2.0 ❐ Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7.
6.1 PSoC Designer Software Subsystems
6.1.1 Design Entry In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use
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read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows you to create a trace buffer of registers and memory locations of interest. 6.1.4 Online Help System The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an online support forum to aid the designer.
6.1.5 In-Circuit Emulator A low-cost, high-functionality In-Circuit Emulator (ICE) is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24-MHz) operation.
7. Designing with PSoC Designer
The development process for the PSoC® device differs from that of a traditional fixed function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is summarized in four steps: 1. Select User Modules 2. Configure User Modules 3. Organize and Connect 4. Generate, Verify, and Debug
7.3 Organize and Connect
You build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. You perform the selection, configuration, and routing so that you have complete control over all on-chip resources.
7.4 Generate, Verify, and Debug
When you are ready to test the hardware configuration or move on to developing code for the project, you perform the “Generate Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides application programming interfaces (APIs) with high-level functions to control and respond to hardware events at run time and interrupt service routines that you can adapt as needed. A complete code development environment allows you to develop and customize your applications in either C, assembly language, or both. The last step in the development process takes place inside PSoC Designer’s debugger (access by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer and allows you to define complex breakpoint events. These include monitoring address and data bus values, memory locations and external signals.
7.1 Select User Modules
PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called “user modules.” User modules make selecting and implementing peripheral devices, both analog and digital, simple.
7.2 Configure User Modules
Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a PWM User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. The user module parameters permit you to establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the internal operation of the user module and provide performance specifications. Each datasheet describes the use of each user module parameter, and other information you may need to successfully implement your design.
Document Number: 38-12018 Rev. *Z
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8. Pin Information
This section describes, lists, and illustrates the CY8C24x94 PSoC device family pins and pinout configuration. The CY8C24x94 PSoC devices are available in the following packages, all of which are shown on the following pages. Every port pin (labeled with a “P”) is capable of Digital I/O. However, VSS, VDD, and XRES are not capable of Digital I/O.
8.1 56-Pin Part Pinout
Table 2. 56-Pin Part Pinout (QFN[6]) See LEGEND details and footnotes in Table 3 on page 9.
Type Figure 3. CY8C24794 56-Pin PSoC Name Description No. Digital Analog 1 I/O I, M P2[3] Direct switched capacitor block input 2 I/O I, M P2[1] Direct switched capacitor block input 3 I/O M P4[7] 4 I/O M P4[5] 5 I/O M P4[3] A, I, M , P2[3] 1 6 I/O M P4[1] A, I, M , P2[1] 2 7 I/O M P3[7] M , P4[7] 3 M , P4[5] 4 8 I/O M P3[5] M , P4[3] 5 9 I/O M P3[3] M , P4[1] 6 10 I/O M P3[1] M , P3[7] 7 QFN 11 I/O M P5[7] 8 M , P3[5] (Top V ie w ) M , P3[3] 9 12 I/O M P5[5] 10 M , P3[1] 13 I/O M P5[3] 11 M , P5[7] 14 I/O M P5[1] 12 M , P5[5] M , P5[3] 15 I/O M P1[7] I2C serial clock (SCL) 13 M , P5[1] 14 16 I/O M P1[5] I2C serial data (SDA) 17 I/O M P1[3] 18 I/O M P1[1] I2C SCL, ISSP SCLK[4] 19 Power VSS Ground connection 20 USB D+ 21 USB D– 22 Power VDD Supply voltage 23 I/O P7[7] 24 I/O P7[0] 25 I/O M P1[0] I2C SDA, ISSP SDATA[4] 26 I/O M P1[2] 27 I/O M P1[4] Optional external clock input (EXTCLK) 28 I/O M P1[6] 29 I/O M P5[0] Type Pin Name Description 30 I/O M P5[2] No. Digital Analog Pin
P2[5],M P2[7],M P0[1], A, I, M P0[3], A, IO, M P0[5], A, IO, M P0[7], A, I, M Vss 56 55 54 53 52 51 50 49 48 47 46 45 21 22 23 24 15 16 17 18 19 20 M,P1[3] M, I2C SCL, P1[1] Vss D+ DVdd P7[7] M, I2C SCL, P1[7] M, I2C SDA, P1[5] P7[0]
Device[3]
P2[4],M 43
44
Vdd P0[6], A, I, M P0[4], A, I, M P0[2], A, I, M P0[0], A, I, M P2[6],M
31 32 33 34 35 36 37 38 39 40 41 42 43
I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
M M M M M M M M M M I, M I, M M
P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] Direct switched capacitor block input Direct switched capacitor block input External analog ground (AGND) input
44 45 46 47 48 49 50 51 52 53 54 55 56
I/O I/O I/O I/O I/O
M I, M I, M I, M I, M
P2[6] P0[0] P0[2] P0[4] P0[6] VDD VSS P0[7] P0[5] P0[3] P0[1] P2[7] P2[5]
External voltage reference (VREF) input Analog column mux input Analog column mux input Analog column mux input VREF Analog column mux input Supply voltage Ground connection Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input
Power Power I/O I/O I/O I/O I/O I/O I, M I/O, M I/O, M I, M M M
Notes 3. This part cannot be programmed with Reset mode; use Power Cycle mode when programming. 4. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.
Document Number: 38-12018 Rev. *Z
M, I2C SDA, P1[0] M,P1[2] EXTCLK, M,P1[4] M, P1[6]
25 26 27 28
42 41 40 39 38 37 36 35 34 33 32 31 30 29
P2[2], A, I, M P2[0], A, I, M P4[6], M P4[4], M P4[2], M P4[0], M P3[6], M P3[4], M P3[2 ], M P3[0 ], M P5[6 ], M P5[4 ], M P5[2 ], M P5[0 ], M
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8.2 56-Pin Part Pinout (with XRES)
Table 3. 56-Pin Part Pinout (QFN[6])
Pin Type Name Description No. Digital Analog 1 I/O I, M P2[3] Direct switched capacitor block input 2 I/O I, M P2[1] Direct switched capacitor block input 3 I/O M P4[7] 4 I/O M P4[5] 5 I/O M P4[3] 6 I/O M P4[1] 7 I/O M P3[7] 8 I/O M P3[5] 9 I/O M P3[3] 10 I/O M P3[1] 11 I/O M P5[7] 12 I/O M P5[5] 13 I/O M P5[3] 14 I/O M P5[1] 15 I/O M P1[7] I2C SCL 16 I/O M P1[5] I2C SDA 17 I/O M P1[3] 18 I/O M P1[1] I2C SCL, ISSP SCLK[5] 19 Power VSS Ground connection 20 USB D+ 21 USB D– 22 Power VDD Supply voltage 23 I/O P7[7] 24 I/O P7[0] 25 I/O M P1[0] I2C SDA, ISSP SDATA[5] 26 I/O M P1[2] 27 I/O M P1[4] Optional EXTCLK 28 I/O M P1[6] 29 I/O M P5[0] 30 31 32 33 34 35 36 37 38 39 40 41 42 43 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input M M M M I, M I, M M M M M M M M P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] XRES Active high external reset with internal pull-down P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] Direct switched capacitor block input Direct switched capacitor block input External AGND input 50 51 52 53 54 55 56 Power I/O I/O I/O I/O I/O I/O I, M I/O, M I/O, M I, M M M VSS P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] Ground connection Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input
Figure 4. CY8C24894 56-Pin PSoC Device
I, M IO, M IO, M I, M M M M M 48 47 46 45 44 43 A, A, A, A, M M I, I, I, I,
A, I, M, A, I, M, M, M, M, M, M, M, M, M, M, M, M, M,
P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1]
Pin 44 45 46 47 48 49 I/O I/O I/O I/O I/O
Type M I, M I, M I, M I, M
No. Digital Analog
Power
LEGEND A = Analog, I = Input, O = Output, and M = Analog Mux Input.
Notes 5. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details. 6. The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal.
Document Number: 38-12018 Rev. *Z
P1[7] P1[5] P1[3] P1[1] Vss D+ DVdd P7[7] P7[0] M, I2C SDA, P1[0] M, P1[2] EXTCLK, M, P1[4] M, P1[6]
M, I2C SCL, M, I2C SDA, M, M, I2C SCL,
15 16 17 18 19 20 21 22 23 24 25 26 27 28
1 2 3 4 5 6 7 8 9 10 11 12 13 14
56 55 54 53 52 51 50 49
P2[5], P2[7], P0[1], P0[3], P0[5], P0[7], Vss Vdd P0[6], P0[4], P0[2], P0[0], P2[6], P2[4],
M M A, A, A, A,
QFN
(Top Vie w)
42 41 40 39 38 37 36 35 34 33 32 31 30 29
P2[2], P2[0], P4[6], P4[4], P4[2], P4[0], XRES P3[4], P3[2], P3[0], P5[6], P5[4], P5[2], P5[0],
A, I, M A, I, M M M M M M M M M M M M
Name P2[6] P0[0] P0[2] P0[4] P0[6] VDD
Description External VREF input Analog column mux input Analog column mux input Analog column mux input VREF Analog column mux input Supply voltage
Page 9 of 59
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CY8C24094, CY8C24794 CY8C24894, CY8C24994
8.3 68-Pin Part Pinout
The following 68-pin QFN part table and drawing is for the CY8C24994 PSoC device. Table 4. 68-Pin Part Pinout (QFN[7])
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
P2[6], M, Ext. VREF P2[4], M, Ext. AGND P2[2], M, AI 53 52
P2[3], M, AI P2[5], M P2[7], M
P0[1], M, AI P0[3], M, AIO P0[5], M, AIO
P2[1], M, AI
P0[7], M, AI Vss Vdd P0[6], M, AI P0[4], M, AI
Power I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power USB USB Power I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
No connection No connection Ground connection
68 67
66 65
64
63 62 61 60 59
58 57 56
M M M M M M M M M M M M
M, P4[7] M, P4[5] M, P4[3] M, P4[1] NC NC Vss M, P3[7] M, P3[5] M, P3[3] M, P3[1] M, P5[7] M, P5[5] M, P5[3] M, P5[1] I2C SCL, M, P1[7] I2C SDA, M, P1[5]
55 54
P0[2], M, AI P0[0], M, AI
Type Digital Analog I/O M I/O M I/O M I/O M
Name P4[7] P4[5] P4[3] P4[1] NC NC VSS P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] VSS D+ D– VDD P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] NC NC XRES
Description
Figure 5. CY8C24994 68-Pin PSoC Device
I2C SCL I2C SDA I2C SCL ISSP SCLK[8] Ground connection
18 19
20 21 22 23
24 25 26 27
28 29 30
I2C SCL, M, P1[1] Vss D+ DVdd
P7[7] P7[6] P7[5] P7[4]
M, P1[3]
P7[3] P7[2] P7[1] P7[0]
I2C SDA, M, P1[0] M, P1[2]
Supply voltage
Pin No. 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65
M M M M M M M M M M M M
I2C SDA, ISSP SDATA[8] Optional EXTCLK
Type Digital Analog I/O M I/O I, M I/O I, M I/O M I/O M I/O I, M I/O I, M I/O I, M I/O I, M Power Power I/O I, M I/O I/O, M I/O I/O I/O I/O, M I, M M
Name P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD VSS P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1]
Description
Direct switched capacitor block input Direct switched capacitor block input External AGND input External VREF input Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Supply voltage Ground connection Analog column mux input, integration input #1 Analog column mux input and column output, integration input #2 Analog column mux input and column output Analog column mux input
Input
No connection. No connection. Active high pin reset with internal
pull-down. 47 I/O M P4[0] 66 I/O M 48 I/O M P4[2] 67 I/O I, M 49 I/O M P4[4] 68 I/O I, M LEGEND A = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input.
Direct switched capacitor block input Direct switched capacitor block input
Notes 7. The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. 8. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.
Document Number: 38-12018 Rev. *Z
EXTCLK, M, P1[4]
31 32 33 34
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
P2[0], M, AI P4[6], M P4[4], M P4[2], M P4[0], M XRES NC NC P3[6], M P3[4], M P3[2], M P3[0], M P5[6], M P5[4], M P5[2], M P5[0], M P1[6], M
QFN
(Top View)
Page 10 of 59
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CY8C24094, CY8C24794 CY8C24894, CY8C24994
8.4 68-Pin Part Pinout (On-Chip Debug)
The following 68-pin QFN part table and drawing is for the CY8C24094 OCD PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. Table 5. 68-Pin Part Pinout (QFN[9])
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
P2[6], M, Ext. VREF P2[4], M, Ext. AGND P2[2], M, AI
P2[3], M, AI P2[5], M P2[7], M P0[1], M, AI P0[3], M, AIO P0[5], M, AIO
Power I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power USB USB Power I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O
OCD even data I/O OCD odd data output Ground connection
64 63 62 61 60 59
58 57 56
M M M M M M M M M M M M
I2C SCL I2C SDA I2C SCL, ISSP SCLK[10] Ground connection
M, P4[7] M, P4[5] M, P4[3] M, P4[1] OCDE OCDO Vss M, P3[7] M, P3[5] M, P3[3] M, P3[1] M, P5[7] M, P5[5] M, P5[3] M, P5[1] I2C SCL, M, P1[7] I2C SDA, M, P1[5]
55 54 53 52
68 67
66 65
P0[7], M, AI Vss Vdd P0[6], M, AI P0[4], M, AI P0[2], M, AI P0[0], M, AI
P2[1], M, AI
Type Digital Analog I/O M I/O M I/O M I/O M
Name P4[7] P4[5] P4[3] P4[1] OCDE OCDO VSS P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] VSS D+ D– VDD P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6]
Description
Figure 6. CY8C24094 68-Pin OCD PSoC Device
20 21 22
23 24 25 26 27
M, P1[3] I2C SCL, M, P1[1] Vss D+ DVdd
Supply voltage
I2C SDA, M, P1[0] M, P1[2] EXTCLK M, P1[4]
P7[7] P7[6] P7[5] P7[4]
P7[3] P7[2] P7[1] P7[0]
28 29 30 31 32 33 34
18 19
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
QFN
(Top View)
51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35
P2[0], M, AI P4[6], M P4[4], M P4[2], M P4[0], M XRES CCLK HCLK P3[6], M P3[4], M P3[2], M P3[0], M P5[6], M P5[4], M P5[2], M P5[0], M P1[6], M
Pin No. 50 51 52 53 54 55 56 57 58 59 60 61 62
M M M M M M M M M M M M
I2C SDA, ISSP SDATA[10] Optional EXTCLK
Type Digital Analog I/O M I/O I, M I/O I, M I/O M I/O M I/O I, M I/O I, M I/O I, M I/O I, M Power Power I/O I, M I/O I/O, M
Name P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] VDD VSS P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1]
Description
Direct switched capacitor block input Direct switched capacitor block input External AGND input External VREF input Analog column mux input Analog column mux input and column output Analog column mux input and column output Analog column mux input Supply voltage Ground connection Analog column mux input, integration input #1 Analog column mux input and column output, integration input #2 Analog column mux input and column output Analog column mux input
HCLK OCD high speed clock output 63 I/O I/O, M 44 45 CCLK OCD CPU clock output 64 I/O I, M Input XRES Active high pin reset with internal pull-down 65 I/O M 46 47 I/O M P4[0] 66 I/O M 48 I/O M P4[2] 67 I/O I, M 49 I/O M P4[4] 68 I/O I, M LEGEND A = Analog, I = Input, O = Output, M = Analog Mux Input, OCD = On-Chip Debugger.
Direct switched capacitor block input Direct switched capacitor block input
Notes 9. The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. 10. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.
Document Number: 38-12018 Rev. *Z
,
Page 11 of 59
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CY8C24094, CY8C24794 CY8C24894, CY8C24994
8.5 100-Ball VFBGA Part Pinout
The 100-ball VFBGA part is for the CY8C24994 PSoC device. Table 6. 100-Ball Part Pinout (VFBGA)
Analog Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 E1 E2 E3 E4 E5 E6 E7 E8 E9 E10 Name VSS VSS NC NC NC VDD NC NC VSS VSS VSS VSS P2[1] P0[1] P0[7] VDD P0[2] P2[2] VSS VSS NC P4[1] P4[7] P2[7] P0[5] P0[6] P0[0] P2[0] P4[2] NC NC P3[7] P4[5] P2[5] P0[3] P0[4] P2[6] P4[6] P4[0] NC NC NC P4[3] P2[3] VSS VSS P2[4] P4[4] P3[6] NC Description Ground connection Ground connection No connection No connection No connection Supply voltage No connection No connection Ground connection Ground connection Ground connection Ground connection Direct switched capacitor block input Analog column mux input Analog column mux input Supply voltage Analog column mux input Direct switched capacitor block input Ground connection Ground connection No connection Pin No. F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 G1 G2 G3 G4 G5 G6 G7 G8 G9 G10 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 Analog Digital Digital Name NC P5[7] P3[5] P5[1] VSS VSS P5[0] P3[0] XRES P7[1] NC P5[5] P3[3] P1[7] P1[1] P1[0] P1[6] P3[4] P5[6] P7[2] NC P5[3] P3[1] P1[5] P1[3] P1[2] P1[4] P3[2] P5[4] P7[3] VSS VSS D+ D– VDD P7[7] P7[0] P5[2] VSS VSS VSS VSS NC NC VDD P7[6] P7[5] P7[4] VSS VSS No connection Description
Power Power
Power
I/O M I/O M I/O M Power Power I/O M I/O M I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O M M M M M M M M
Ground connection Ground connection
Power Power Power Power I/O I, M I/O I, M I/O I, M Power I/O I, M I/O I, M Power Power I/O I/O I/O I/O I/O I/O I/O I/O M M M I/O, M I, M I, M I, M M
Active high pin reset with internal pull-down No connection
I2C SCL I2C SCL, ISSP SCLK[11] I2C SDA, ISSP SDATA[11]
No connection
Analog column mux input and column output Analog column mux input Analog column mux input Direct switched capacitor block input No connection No connection
I/O I/O I/O I/O I/O I/O I/O I/O
M M M I/O, M I,M M M M
Analog column mux input and column output Analog column mux input External VREF input
No connection No connection No connection Direct switched capacitor block input Ground connection Ground connection External AGND input
I/O M I/O M I/O M I/O M I/O M I/O M I/O M I/O M I/O Power Power USB USB Power I/O I/O I/O M Power Power Power Power
I2C SDA
Optional EXTCLK
Ground connection Ground connection
Supply voltage
I/O M I/O I, M Power Power I/O M I/O M I/O M
No connection
Power I/O I/O I/O Power Power
Ground connection Ground connection Ground connection Ground connection No connection No connection Supply voltage
Ground connection Ground connection
LEGEND A = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No Connection.
Note 11. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.
Document Number: 38-12018 Rev. *Z
Page 12 of 59
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CY8C24094, CY8C24794 CY8C24894, CY8C24994
Figure 7. CY8C24094 OCD (Not for Production)
1 A B C D E F G H J K
Vss
2
Vss
3
NC
4
NC
5
NC
6
Vdd
7
NC
8
NC
9
Vss
10
Vss
Vss
Vss
P2[1]
P0[1]
P0[7]
Vdd
P0[2]
P2[2]
Vss
Vss
NC
P4[1]
P4[7]
P2[7]
P0[5]
P0[6]
P0[0]
P2[0]
P4[2]
NC
NC
P3[7]
P4[5]
P2[5]
P0[3]
P0[4]
P2[6]
P4[6]
P4[0]
NC
NC
NC
P4[3]
P2[3]
Vss
Vss
P2[4]
P4[4]
P3[6]
NC
NC
P5[7]
P3[5]
P5[1]
Vss
Vss
P5[0]
P3[0]
XRES
P7[1]
NC
P5[5]
P3[3]
P1[7]
P1[1]
P1[0]
P1[6]
P3[4]
P5[6]
P7[2]
NC
P5[3]
P3[1]
P1[5]
P1[3]
P1[2]
P1[4]
P3[2]
P5[4]
P7[3]
Vss
Vss
D+
D-
Vdd
P7[7]
P7[0]
P5[2]
Vss
Vss
Vss
Vss
NC
NC
Vdd
P7[6]
P7[5]
P7[4]
Vss
Vss
BGA (Top View)
Document Number: 38-12018 Rev. *Z
Page 13 of 59
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CY8C24094, CY8C24794 CY8C24894, CY8C24994
8.6 100-Ball VFBGA Part Pinout (On-Chip Debug)
The following 100-pin VFBGA part table and drawing is for the CY8C24094 OCD PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. Table 7. 100-Ball Part Pinout (VFBGA)
Analog Pin No. Name Description Pin No. Analog Digital Digital Name Description
A1 Power VSS Ground connection F1 OCDE OCD even data I/O A2 Power VSS Ground connection F2 I/O M P5[7] A3 NC No connection F3 I/O M P3[5] A4 NC No connection F4 I/O M P5[1] A5 NC No connection. F5 Power VSS Ground connection A6 Power VDD Supply voltage. F6 Power VSS Ground connection A7 NC No connection. F7 I/O M P5[0] A8 NC No connection. F8 I/O M P3[0] A9 Power VSS Ground connection F9 XRES Active high pin reset with internal pull-down A10 Power VSS Ground connection F10 I/O P7[1] B1 Power VSS Ground connection G1 OCDO OCD odd data output B2 Power VSS Ground connection G2 I/O M P5[5] B3 I/O I, M P2[1] Direct switched capacitor block input G3 I/O M P3[3] B4 I/O I, M P0[1] Analog column mux input G4 I/O M P1[7] I2C SCL B5 I/O I, M P0[7] Analog column mux input G5 I/O M P1[1] I2C SCL, ISSP SCLK[12] B6 Power VDD Supply voltage G6 I/O M P1[0] I2C SDA, ISSP SDATA[12] B7 I/O I, M P0[2] Analog column mux input G7 I/O M P1[6] B8 I/O I, M P2[2] Direct switched capacitor block input G8 I/O M P3[4] B9 Power VSS Ground connection G9 I/O M P5[6] B10 Power VSS Ground connection G10 I/O P7[2] C1 NC No connection H1 NC No connection C2 I/O M P4[1] H2 I/O M P5[3] C3 I/O M P4[7] H3 I/O M P3[1] C4 I/O M P2[7] H4 I/O M P1[5] I2C SDA C5 I/O I/O,M P0[5] Analog column mux input and column output H5 I/O M P1[3] C6 I/O I, M P0[6] Analog column mux input H6 I/O M P1[2] C7 I/O I, M P0[0] Analog column mux input H7 I/O M P1[4] Optional EXTCLK C8 I/O I, M P2[0] Direct switched capacitor block input H8 I/O M P3[2] C9 I/O M P4[2] H9 I/O M P5[4] C10 NC No connection H10 I/O P7[3] D1 NC No connection J1 Power VSS Ground connection D2 I/O M P3[7] J2 Power VSS Ground connection D3 I/O M P4[5] J3 USB D+ D4 I/O M P2[5] J4 USB DD5 I/O I/O, M P0[3] Analog column mux input and column output J5 Power VDD Supply voltage D6 I/O I, M P0[4] Analog column mux input J6 I/O P7[7] D7 I/O M P2[6] External VREF input J7 I/O P7[0] D8 I/O M P4[6] J8 I/O M P5[2] D9 I/O M P4[0] J9 Power VSS Ground connection D10 CCLK OCD CPU clock output J10 Power VSS Ground connection E1 NC No connection K1 Power VSS Ground connection E2 NC No connection K2 Power VSS Ground connection E3 I/O M P4[3] K3 NC No connection E4 I/O I, M P2[3] Direct switched capacitor block input K4 NC No connection E5 Power VSS Ground connection K5 Power VDD Supply voltage E6 Power VSS Ground connection K6 I/O P7[6] E7 I/O M P2[4] External AGND input K7 I/O P7[5] E8 I/O M P4[4] K8 I/O P7[4] E9 I/O M P3[6] K9 Power VSS Ground connection E10 HCLK OCD high speed clock output K10 Power VSS Ground connection LEGEND A = Analog, I = Input, O = Output, M = Analog Mux Input, NC = No Connection, OCD = On-Chip Debugger. Note 12. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.
Document Number: 38-12018 Rev. *Z
Page 14 of 59
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CY8C24094, CY8C24794 CY8C24894, CY8C24994
Figure 8. CY8C24094 OCD (Not for Production)
1 A B C D E F G H J K
Vss
2
Vss
3
NC
4
NC
5
NC
6
Vdd
7
NC
8
NC
9
Vss
10
Vss
Vss
Vss
P2[1]
P0[1]
P0[7]
Vdd
P0[2]
P2[2]
Vss
Vss
NC
P4[1]
P4[7]
P2[7]
P0[5]
P0[6]
P0[0]
P2[0]
P4[2]
NC
NC
P3[7]
P4[5]
P2[5]
P0[3]
P0[4]
P2[6]
P4[6]
P4[0]
CClk
NC
NC
P4[3]
P2[3]
Vss
Vss
P2[4]
P4[4]
P3[6]
HClk
ocde
P5[7]
P3[5]
P5[1]
Vss
Vss
P5[0]
P3[0]
XRES
P7[1]
ocdo
P5[5]
P3[3]
P1[7]
P1[1]
P1[0]
P1[6]
P3[4]
P5[6]
P7[2]
NC
P5[3]
P3[1]
P1[5]
P1[3]
P1[2]
P1[4]
P3[2]
P5[4]
P7[3]
Vss
Vss
D+
D-
Vdd
P7[7]
P7[0]
P5[2]
Vss
Vss
Vss
Vss
NC
NC
Vdd
P7[6]
P7[5]
P7[4]
Vss
Vss
BGA (Top View)
Document Number: 38-12018 Rev. *Z
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8.7 100-Pin Part Pinout (On-Chip Debug)
The 100-pin TQFP part is for the CY8C24094 OCD PSoC device. Note This part is only used for in-circuit debugging. It is NOT available for production. Table 8. 100-Pin Part Pinout (TQFP)
Analog Pin No. Name Description Pin No. Analog Digital Digital Name Description
1 NC No connection 51 I/O M P1[6] 2 NC No connection 52 I/O M P5[0] 3 I/O I, M P0[1] Analog column mux input 53 I/O M P5[2] 4 I/O M P2[7] 54 I/O M P5[4] 5 I/O M P2[5] 55 I/O M P5[6] 6 I/O I, M P2[3] Direct switched capacitor block input 56 I/O M P3[0] 7 I/O I, M P2[1] Direct switched capacitor block input 57 I/O M P3[2] 8 I/O M P4[7] 58 I/O M P3[4] 9 I/O M P4[5] 59 I/O M P3[6] 10 I/O M P4[3] 60 HCLK OCD high speed clock output 11 I/O M P4[1] 61 CCLK OCD CPU clock output 12 OCDE OCD even data I/O 62 Input XRES Active high pin reset with internal pull-down 13 OCDO OCD odd data output 63 I/O M P4[0] 14 NC No connection 64 I/O M P4[2] 15 Power VSS Ground connection 65 Power VSS Ground connection 16 I/O M P3[7] 66 I/O M P4[4] 17 I/O M P3[5] 67 I/O M P4[6] 18 I/O M P3[3] 68 I/O I, M P2[0] Direct switched capacitor block input 19 I/O M P3[1] 69 I/O I, M P2[2] Direct switched capacitor block input 20 I/O M P5[7] 70 I/O P2[4] External AGND input 21 I/O M P5[5] 71 NC No connection 22 I/O M P5[3] 72 I/O P2[6] External VREF input 23 I/O M P5[1] 73 NC No connection 24 I/O M P1[7] I2C SCL 74 I/O I P0[0] Analog column mux input 25 NC No connection 75 NC No connection 26 NC No connection 76 NC No connection 27 NC No connection 77 I/O I, M P0[2] Analog column mux input and column output 28 I/O P1[5] I2C SDA 78 NC No connection 29 I/O P1[3] 79 I/O I, M P0[4] Analog column mux input and column output 30 I/O P1[1] Crystal (XTALin), I2C SCL, ISSP SCLK[13] 80 NC No connection 31 NC No connection 81 I/O I, M P0[6] Analog column mux input 32 Power VSS Ground connection 82 Power VDD Supply voltage 33 USB D+ 83 NC No connection 34 USB D84 Power VSS Ground connection 35 Power VDD Supply voltage 85 NC No connection 36 I/O P7[7] 86 NC No connection 37 I/O P7[6] 87 NC No connection 38 I/O P7[5] 88 NC No connection 39 I/O P7[4] 89 NC No connection 40 I/O P7[3] 90 NC No connection 41 I/O P7[2] 91 NC No connection 42 I/O P7[1] 92 NC No connection 43 I/O P7[0] 93 NC No connection 44 NC No connection 94 NC No connection 45 NC No connection 95 I/O I, M P0[7] Analog column mux input 46 NC No connection 96 NC No connection 47 NC No connection 97 I/O I/O, M P0[5] Analog column mux input and column output 48 I/O P1[0] Crystal (XTALout), I2C SDA, ISSP SDATA[13] 98 NC No connection 49 I/O P1[2] 99 I/O I/O, M P0[3] Analog column mux input and column output 50 I/O P1[4] Optional EXTCLK 100 NC No connection LEGEND A = Analog, I = Input, O = Output, NC = No Connection, M = Analog Mux Input, OCD = On-Chip Debugger.
5
Note 13. These are the ISSP pins, which are not High Z at POR. See the PSoC Technical Reference Manual for details.
Document Number: 38-12018 Rev. *Z
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Figure 9. CY8C24094 OCD (Not for Production)
P0[3], M, AI NC P0[5], M, AI NC Vdd P0[6], M, AI NC P0[4], M, AI NC P0[2], M, AI NC 77 76 M, P1[2] EXTCLK, M, P1[4] 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC P0[0], M , AI NC P2[6], M , External VREF NC P2[4], M , External AGND P2[2], M , AI P2[0], M , AI P4[6], M P4[4], M Vss P4[2], M P4[0], M XRES CCLK HCLK P3[6], M P3[4], M P3[2], M P3[0], M P5[6], M P5[4], M P5[2], M P5[0], M P1[6], M NC P0[7], M, AI NC
100 99
98 97 96
95 94 93 92 91
90 89 88
87 86 85 84 83 82 81 P7[3] P7[2]
NC NC Vss
NC NC NC NC NC NC NC
NC
26 27
28 29 30
31 32 33 34 35
36 37 38 39 40 41 42 43 44 45 P7[7] P7[6] P7[5] P7[4]
NC I2C SDA, M, P1[5] M, P1[3] I2C SCL, M, P1[1] NC Vss D+ DVdd
Document Number: 38-12018 Rev. *Z
P7[1] P7[0] NC NC NC NC I2C SDA, M, P1[0]
NC
46 47 48 49 50
NC NC AI, M , P0[1] M , P2[7] M , P2[5] AI, M , P2[3] AI, M , P2[1] M , P4[7] M , P4[5] M , P4[3] M , P4[1] OCDE OCDO NC Vss M , P3[7] M , P3[5] M , P3[3] M , P3[1] M , P5[7] M , P5[5] M , P5[3] M , P5[1] I2C SCL, P1[7] NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
TQFP
80 79 78
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9. Register Reference
This section lists the registers of the CY8C24x94 PSoC device family. For detailed register information, see the PSoC Technical Reference Manual.
9.1 Register Conventions
The register conventions specific to this section are listed in the following table. Convention R W L C # Description Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific
9.2 Register Mapping Tables
The PSoC device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks, Bank 0 and Bank 1. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set to 1, the user is in Bank 1. Note In the following register mapping tables, blank fields are Reserved and should not be accessed.
Document Number: 38-12018 Rev. *Z
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9.3 Register Map Bank 0 Table: User Space
Addr (0, Hex) Access Name 00 RW PMA0_DR 01 RW PMA1_DR 02 RW PMA2_DR 03 RW PMA3_DR 04 RW PMA4_DR 05 RW PMA5_DR 06 RW PMA6_DR 07 RW PMA7_DR 08 RW USB_SOF0 09 RW USB_SOF1 0A RW USB_CR0 0B RW USBI/O_CR0 0C RW USBI/O_CR1 0D RW 0E RW EP1_CNT1 0F RW EP1_CNT 10 RW EP2_CNT1 11 RW EP2_CNT 12 RW EP3_CNT1 13 RW EP3_CNT 14 RW EP4_CNT1 15 RW EP4_CNT 16 RW EP0_CR 17 RW EP0_CNT 18 EP0_DR0 19 EP0_DR1 1A EP0_DR2 1B EP0_DR3 PRT7DR 1C RW EP0_DR4 PRT7IE 1D RW EP0_DR5 PRT7GS 1E RW EP0_DR6 PRT7DM2 1F RW EP0_DR7 DBB00DR0 20 # AMX_IN DBB00DR1 21 W AMUXCFG DBB00DR2 22 RW DBB00CR0 23 # ARF_CR DBB01DR0 24 # CMP_CR0 DBB01DR1 25 W ASY_CR DBB01DR2 26 RW CMP_CR1 DBB01CR0 27 # DCB02DR0 28 # DCB02DR1 29 W DCB02DR2 2A RW DCB02CR0 2B # DCB03DR0 2C # TMP_DR0 DCB03DR1 2D W TMP_DR1 DCB03DR2 2E RW TMP_DR2 DCB03CR0 2F # TMP_DR3 30 ACB00CR3 31 ACB00CR0 32 ACB00CR1 33 ACB00CR2 34 ACB01CR3 35 ACB01CR0 36 ACB01CR1 37 ACB01CR2 38 39 3A 3B 3C 3D 3E 3F Blank fields are reserved and should not be accessed. Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0, Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Access RW RW RW RW RW RW RW RW R R RW # RW # RW # RW # RW # RW # # RW RW RW RW RW RW RW RW RW RW RW # # RW Addr (0, Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F ASD20CR0 90 ASD20CR1 91 ASD20CR2 92 ASD20CR3 93 ASC21CR0 94 ASC21CR1 95 ASC21CR2 96 ASC21CR3 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 MUL1_X A8 MUL1_Y A9 MUL1_DH AA MUL1_DL AB ACC1_DR1 AC ACC1_DR0 AD ACC1_DR3 AE ACC1_DR2 AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 Access RW RW RW RW RW RW RW RW Name Addr (0, Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access
RW RW RW RW RW RW RW RW
CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2
RW RW RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W RC RC RW RW W W R R RW RW RW RW
RW RW RW RW RW RW RW RW RW RW RW RW
W W R R RW RW RW RW RW RW RW RW RW RW RW
CPU_F
RL
DAC_D CPU_SCR1 CPU_SCR0
RW # #
Document Number: 38-12018 Rev. *Z
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9.4 Register Map Bank 1 Table: Configuration Space
Addr (1, Hex) Access Name 00 RW PMA0_WA 01 RW PMA1_WA 02 RW PMA2_WA 03 RW PMA3_WA 04 RW PMA4_WA 05 RW PMA5_WA 06 RW PMA6_WA 07 RW PMA7_WA 08 RW 09 RW 0A RW 0B RW 0C RW 0D RW 0E RW 0F RW 10 RW PMA0_RA 11 RW PMA1_RA 12 RW PMA2_RA 13 RW PMA3_RA 14 RW PMA4_RA 15 RW PMA5_RA 16 RW PMA6_RA 17 RW PMA7_RA 18 19 1A 1B PRT7DM0 1C RW PRT7DM1 1D RW PRT7IC0 1E RW PRT7IC1 1F RW DBB00FN 20 RW CLK_CR0 DBB00IN 21 RW CLK_CR1 DBB00OU 22 RW ABF_CR0 23 AMD_CR0 DBB01FN 24 RW CMP_GO_EN DBB01IN 25 RW DBB01OU 26 RW AMD_CR1 27 ALT_CR0 DCB02FN 28 RW DCB02IN 29 RW DCB02OU 2A RW 2B DCB03FN 2C RW TMP_DR0 DCB03IN 2D RW TMP_DR1 DCB03OU 2E RW TMP_DR2 2F TMP_DR3 30 ACB00CR3 31 ACB00CR0 32 ACB00CR1 33 ACB00CR2 34 ACB01CR3 35 ACB01CR0 36 ACB01CR1 37 ACB01CR2 38 39 3A 3B 3C 3D 3E 3F Blank fields are reserved and should not be accessed. Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1, Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Access RW RW RW RW RW RW RW RW Addr (1, Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 ASD20CR1 91 ASD20CR2 92 ASD20CR3 93 ASC21CR0 94 ASC21CR1 95 ASC21CR2 96 ASC21CR3 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 Access RW RW RW RW RW RW RW RW Name USBI/O_CR2 USB_CR1 Addr (1, Hex) Access C0 RW C1 #
EP1_CR0 EP2_CR0 EP3_CR0 EP4_CR0
RW RW RW RW RW RW RW RW
RW RW RW RW RW RW RW
GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU
MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP
RW RW RW RW RW RW RW
RW RW RW RW RW RW RW RW RW RW RW RW
IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5
RW RW RW RW RW RW RW CPU_F
DAC_CR CPU_SCR1 CPU_SCR0
C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF
# # # #
RW RW RW RW
RW RW RW RW RW RW RW RW RW RW RW R
W W RW W RW RW
RL
RW # #
Document Number: 38-12018 Rev. *Z
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10. Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8C24x94 PSoC device family. For the most up-to-date electrical specifications, confirm that you have the most recent datasheet by visiting http://www.cypress.com. Specifications are valid for –40 °C ≤ TA ≤ 85 °C and TJ ≤ 100 °C, except where noted. Specifications for devices running at greater than 12 MHz are valid for –40 °C ≤ TA ≤ 70 °C and TJ ≤ 82 °C. Figure 10. Voltage Versus CPU Frequency
5.25
4.75 Vdd Voltage
lid ng Va rati n e io Op Reg
3.00
93 kHz CPU Frequency
12 MHz
24 MHz
10.1 Absolute Maximum Ratings
Table 9. Absolute Maximum Ratings
Symbol TSTG Description Storage temperature Min –55 Typ 25 Max +100 Units °C Notes Higher storage temperatures reduces data retention time. Recommended storage temperature is +25 °C ± 25 °C. Extended duration storage temperatures higher than 65 °C degrades reliability.
TBAKETEMP
Bake temperature
–
125
tBAKETIME
Bake time
TA VDD VI/O VI/O2 IMI/O IMAI/O ESD LU
Ambient temperature with power applied Supply voltage on VDD relative to VSS DC input voltage DC voltage applied to tri-state Maximum current into any port pin Maximum current into any port pin configured as analog driver Electrostatic discharge voltage Latch-up current
See package label –40 –0.5 VSS – 0.5 VSS – 0.5 –25 –50 2000 –
–
See package label 72
°C
Hours
– – – – – – – –
+85 +6.0 VDD + 0.5 VDD + 0.5 +50 +50 – 200
°C V V V mA mA V mA Human body model ESD.
Document Number: 38-12018 Rev. *Z
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10.2 Operating Temperature
Table 10. Operating Temperature
Symbol TA TAUSB TJ Description Ambient temperature Ambient temperature using USB Junction temperature Min –40 –10 –40 Typ – – – Max +85 +85 +100 Units °C °C °C Notes
The temperature rise from ambient to junction is package specific. See Thermal Impedance on page 43. The user must limit the power consumption to comply with this requirement.
10.3 DC Electrical Characteristics
10.3.1 DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 °C and are for design guidance only. Table 11. DC Chip-Level Specifications
Symbol VDD IDD5 Description Supply voltage Supply current, IMO = 24 MHz (5 V) Min 3.0 – Typ – 14 Max 5.25 27 Units V mA Notes See DC POR and LVD specifications, Table 22 on page 33. Conditions are VDD = 5.0 V, TA = 25 °C, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off. Conditions are VDD = 3.3 V, TA = 25 °C, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.367 kHz, analog power = off. Conditions are with internal slow speed oscillator, VDD = 3.3 V, –40 °C ≤ TA ≤ 55 °C, analog power = off. Conditions are with internal slow speed oscillator, VDD = 3.3 V, 55 °C < TA ≤ 85 °C, analog power = off.
IDD3
Supply current, IMO = 24 MHz (3.3 V)
–
8
14
mA
ISB
Sleep (mode) current with POR, LVD, sleep timer, and WDT.[14] Sleep (mode) current with POR, LVD, Sleep Timer, and WDT at high temperature.[14]
–
3
6.5
µA
ISBH
–
4
25
µA
Note 14. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar functions enabled.
Document Number: 38-12018 Rev. *Z
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10.3.2 DC GPIO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 °C and are for design guidance only. Table 12. DC GPIO Specifications
Symbol Description Pull-up resistor RPU Pull-down resistor RPD High output level VOH Min 4 4 VDD – 1.0 Typ 5.6 5.6 – Max 8 8 – Units kΩ kΩ V Notes
VOL
Low output level
–
–
0.75
V
IOH IOL VIL VIH VH IIL CIN COUT
High level source current Low level sink current Input low level Input high level Input hysterisis Input leakage (absolute value) Capacitive load on pins as input Capacitive load on pins as output
10 25 – 2.1 – – – –
– – – – 60 1 3.5 3.5
– – 0.8 – – 10 10
mA mA V V mV nA pF pF
IOH = 10 mA, VDD = 4.75 V to 5.25 V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget. IOL = 25 mA, VDD = 4.75 V to 5.25 V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 200 mA maximum combined IOL budget. VOH = VDD – 1.0 V, see the limitations of the total current in the note for VOH VOL = 0.75 V, see the limitations of the total current in the note for VOL VDD = 3.0 to 5.25. VDD = 3.0 to 5.25. Gross tested to 1 µA. Package and pin dependent. Temp = 25 °C. Package and pin dependent. Temp = 25 °C.
10.3.3 DC Full Speed USB Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –10 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –10 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 °C and are for design guidance only. Table 13. DC Full Speed (12 Mbps) USB Specifications
Symbol Description USB Interface Differential input sensitivity VDI Differential input common mode range VCM Single ended receiver threshold VSE Transceiver capacitance CIN High Z state data line leakage II/O REXT External USB series resistor Static output high, driven VUOH VUOHI VUOL ZO VCRS Static output high, idle Static output low USB driver output impedance D+/D– crossover voltage Min 0.2 0.8 0.8 – –10 23 2.8 2.7 – 28 1.3 Typ – – – – – – – – – – – Max – 2.5 2.0 20 10 25 3.6 3.6 0.3 44 2.0 Units V V V pF µA Ω V V V Ω V | (D+) – (D–) | Notes
0 V < VIN < 3.3 V. In series with each USB pin. 15 kΩ ± 5% to ground. Internal pull-up enabled. 15 kΩ ± 5% to ground. Internal pull-up enabled. 15 kΩ ± 5% to ground. Internal pull-up enabled. Including REXT resistor.
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10.3.4 DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 °C and are for design guidance only. The operational amplifier is a component of both the analog continuous time PSoC blocks and the analog switched capacitor PSoC blocks. The guaranteed specifications are measured in the analog continuous time PSoC block. Table 14. 5-V DC Operational Amplifier Specifications
Symbol VOSOA Description Input offset voltage (absolute value) Power = low, Opamp bias = high Power = medium, Opamp bias = high Power = high, Opamp bias = high Average input offset voltage drift Input leakage current (Port 0 analog pins) Input capacitance (Port 0 analog pins) Common mode voltage range Common mode voltage range (high power or high Opamp bias) Min – – – – – – 0.0 0.5 Typ 1.6 1.3 1.2 7.0 20 4.5 – – Max 10 8 7.5 35.0 – 9.5 VDD VDD – 0.5 Units mV mV mV µV/°C pA pF V V Notes
TCVOSOA IEBOA CINOA VCMOA
Gross tested to 1 µA. Package and pin dependent. Temp = 25 °C. The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer.
GOLOA
VOHIGHOA
VOLOWOA
ISOA
PSRROA
Open loop gain Power = low, Opamp bias = high Power = medium, Opamp bias = high Power = high, Opamp bias = high High output voltage swing (internal signals) Power = low, Opamp bias = high Power = medium, Opamp bias = high Power = high, Opamp bias = high Low output voltage swing (internal signals) Power = low, Opamp bias = high Power = medium, Opamp bias = high Power = high, Opamp bias = high Supply current (including associated AGND buffer) Power = low, Opamp bias = low Power = low, Opamp bias = high Power = medium, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = low Power = high, Opamp bias = high Supply voltage rejection ratio
60 60 80 VDD – 0.2 VDD – 0.2 VDD – 0.5 – – –
– – – – – – – – –
– – – – – – 0.2 0.2 0.5
dB dB dB V V V V V V
– – – – – – 65
400 500 800 1200 2400 4600 80
800 900 1000 1600 3200 6400 –
µA µA µA µA µA µA dB
VSS ≤ VIN ≤ (VDD – 2.25) or (VDD – 1.25 V) ≤ VIN ≤ VDD.
Document Number: 38-12018 Rev. *Z
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Table 15. 3.3-V DC Operational Amplifier Specifications
Symbol VOSOA Description Input offset voltage (absolute value) Power = low, Opamp bias = high Power = medium, Opamp bias = high Power = high, Opamp bias = high Average input offset voltage drift Input leakage current (port 0 analog pins) Input capacitance (port 0 analog pins) Common mode voltage range Min – – – – – – 0.2 Typ 1.65 1.32 – 7.0 20 4.5 – Max 10 8 – 35.0 – 9.5 VDD – 0.2 Units mV mV mV µV/°C pA pF V Notes Power = high, Opamp bias = high setting is not allowed for 3.3 V VDD operation
TCVOSOA IEBOA CINOA VCMOA
Open loop gain Power = low, Opamp bias = low Power = medium, Opamp bias = low Power = high, Opamp bias = low VOHIGHOA High output voltage swing (internal signals) Power = low, Opamp bias = low Power = medium, Opamp bias = low Power = high, Opamp bias = low VOLOWOA Low output voltage swing (internal signals) Power = low, Opamp bias = low Power = medium, Opamp bias = low Power = high, Opamp bias = low ISOA Supply current (including associated AGND buffer) Power = low, Opamp bias = low Power = low, Opamp bias = high Power = medium, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = low Power = high, Opamp bias = high PSRROA Supply voltage rejection ratio
GOLOA
60 60 80 VDD – 0.2 VDD – 0.2 VDD – 0.2 – – –
– – – – – – – – –
– – – – – – 0.2 0.2 0.2
dB dB dB V V V V V V
Gross tested to 1 µA. Package and pin dependent. Temp = 25 °C. The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Specification is applicable at Low opamp bias. For high opamp bias mode (except high power, High opamp bias), minimum is 60 dB. Power = high, Opamp bias = high setting is not allowed for 3.3 V VDD operation Power = high, Opamp bias = high setting is not allowed for 3.3 V VDD operation Power = high, Opamp bias = high setting is not allowed for 3.3 V VDD operation
– – – – – – 65
400 500 800 1200 2400 – 80
800 900 1000 1600 3200 – –
µA µA µA µA µA µA dB
VSS ≤ VIN ≤ (VDD – 2.25) or (VDD – 1.25 V) ≤ VIN ≤ VDD
10.3.5 DC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V at 25 °C and are for design guidance only. Table 16. DC Low Power Comparator Specifications
Symbol VREFLPC ISLPC VOSLPC Description Low power comparator (LPC) reference voltage range LPC supply current LPC voltage offset Min 0.2 – – Typ – 10 2.5 Max VDD – 1 40 30 Units V µA mV Notes
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10.3.6 DC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 °C and are for design guidance only. Table 17. 5-V DC Analog Output Buffer Specifications
Symbol CL Description Load Capacitance Min – Typ – Max 200 Units Notes pF This specification applies to the external circuit that is being driven by the analog output buffer. mV µV/°C V Ω Ω
VOSOB TCVOSOB VCMOB ROUTOB
VOHIGHOB
VOLOWOB
ISOB
PSRROB
Input offset voltage (absolute value) – Average input offset voltage drift – Common mode input voltage range 0.5 Output resistance Power = low – Power = high – High output voltage swing (Load = 32 ohms to VDD/2) Power = low 0.5 × VDD + 1.1 Power = high 0.5 × VDD + 1.1 Low output voltage swing (Load = 32 ohms to VDD/2) Power = low – Power = high – Supply current including opamp bias cell (No Load) Power = low – Power = high – Supply voltage rejection ratio 53
3 +6 – 0.6 0.6
12 – VDD – 1.0 – –
– –
– –
V V
– –
0.5 × VDD – 1.3 0.5 × VDD – 1.3
V V
1.1 2.6 64
5.1 8.8 –
mA mA dB
(0.5 × VDD – 1.3) ≤ VOUT ≤ (VDD – 2.3).
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Table 18. 3.3-V DC Analog Output Buffer Specifications
Symbol CL Description Load Capacitance Min – Typ – Max 200 Units Notes pF This specification applies to the external circuit that is being driven by the analog output buffer. mV µV/°C V W W
VOSOB TCVOSOB VCMOB ROUTOB
VOHIGHOB
VOLOWOB
ISOB
PSRROB
Input offset voltage (absolute value) Average input offset voltage drift Common mode input voltage range Output resistance Power = low Power = high High output voltage swing (Load = 1 K ohms to VDD/2) Power = low Power = high Low output voltage swing (Load = 1 K ohms to VDD/2) Power = low Power = high Supply current including opamp bias cell (No load) Power = low Power = high Supply voltage rejection ratio
– – 0.5 – –
3 +6 – 1 1
12 – VDD – 1.0 – –
0.5 × VDD + 1.0 0.5 × VDD + 1.0
– –
– –
V V
– –
– –
0.5 × VDD – 1.0 0.5 × VDD – 1.0
V V
– – 34
0.8 2.0 64
2.0 4.3 –
mA mA dB
(0.5 × VDD – 1.0) ≤ VOUT ≤ (0.5 × VDD + 0.9).
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10.3.7 DC Analog Reference Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 °C and are for design guidance only. The guaranteed specifications are measured through the analog continuous time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high. Table 19. 5-V DC Analog Reference Specifications
Reference ARF_CR [5:3] 0b000 Reference Power Settings RefPower = high Opamp bias = high Symbol VREFHI VAGND VREFLO RefPower = high Opamp bias = low VREFHI VAGND VREFLO RefPower = medium VREFHI Opamp bias = high V AGND VREFLO RefPower = medium VREFHI Opamp bias = low VAGND VREFLO 0b001 RefPower = high Opamp bias = high VREFHI VAGND VREFLO RefPower = high Opamp bias = low VREFHI VAGND VREFLO RefPower = medium VREFHI Opamp bias = high VAGND VREFLO RefPower = medium VREFHI Opamp bias = low VAGND VREFLO Reference Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Description VDD/2 + Bandgap VDD/2 VDD/2 – Bandgap VDD/2 + Bandgap VDD/2 VDD/2 – Bandgap VDD/2 + Bandgap VDD/2 VDD/2 – Bandgap VDD/2 + Bandgap VDD/2 VDD/2 – Bandgap P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) Min Typ Max Units V V V V V V V V V V V V V – V V – V V – V V – V
VDD/2 + 1.229 VDD/2 + 1.290 VDD/2 + 1.346 VDD/2 – 0.038 VDD/2 VDD/2 + 0.040 VDD/2 – 1.356 VDD/2 – 1.295 VDD/2 – 1.218 VDD/2 + 1.220 VDD/2 + 1.292 VDD/2 + 1.348 VDD/2 – 0.036 VDD/2 VDD/2 + 0.036 VDD/2 – 1.357 VDD/2 – 1.297 VDD/2 – 1.225 VDD/2 + 1.221 VDD/2 + 1.293 VDD/2 + 1.351 VDD/2 – 0.036 VDD/2 VDD/2 + 0.036 VDD/2 – 1.357 VDD/2 – 1.298 VDD/2 – 1.228 VDD/2 + 1.219 VDD/2 + 1.293 VDD/2 + 1.353 VDD/2 – 0.037 VDD/2 – 0.001 VDD/2 + 0.036 VDD/2 – 1.359 VDD/2 – 1.299 VDD/2 – 1.229 P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + 0.092 0.011 0.064 P2[4] P2[4] P2[4] P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + 0.031 0.007 0.056 P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + 0.078 0.008 0.063 P2[4] P2[4] P2[4] P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + 0.031 0.004 0.043 P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + 0.073 0.006 0.062 P2[4] P2[4] P2[4] P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + 0.032 0.003 0.038 P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + 0.073 0.006 0.062 P2[4] P2[4] P2[4] P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + 0.034 0.002 0.037
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Table 19. 5-V DC Analog Reference Specifications (continued)
Reference ARF_CR [5:3] 0b010 Reference Power Settings RefPower = high Opamp bias = high Symbol VREFHI VAGND VREFLO RefPower = high Opamp bias = low VREFHI VAGND VREFLO RefPower = medium VREFHI Opamp bias = high V AGND VREFLO RefPower = medium VREFHI Opamp bias = low VAGND VREFLO 0b011 RefPower = high Opamp bias = high VREFHI VAGND VREFLO RefPower = high Opamp bias = low VREFHI VAGND VREFLO RefPower = medium VREFHI Opamp bias = high V AGND VREFLO RefPower = medium VREFHI Opamp bias = low VAGND VREFLO 0b100 RefPower = high Opamp bias = high VREFHI VAGND VREFLO RefPower = high Opamp bias = low VREFHI VAGND VREFLO RefPower = medium VREFHI Opamp bias = high VAGND VREFLO RefPower = medium VREFHI Opamp bias = low VAGND VREFLO Reference Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low VDD VDD/2 VSS VDD VDD/2 VSS VDD VDD/2 VSS VDD VDD/2 VSS 3 × Bandgap 2 × Bandgap Bandgap 3 × Bandgap 2 × Bandgap Bandgap 3 × Bandgap 2 × Bandgap Bandgap 3 × Bandgap 2 × Bandgap Bandgap 2 × Bandgap + P2[6] (P2[6] = 1.3 V) 2 × Bandgap 2 × Bandgap – P2[6] (P2[6] = 1.3 V) 2 × Bandgap + P2[6] (P2[6] = 1.3 V) 2 × Bandgap 2 × Bandgap – P2[6] (P2[6] = 1.3 V) 2 × Bandgap + P2[6] (P2[6] = 1.3 V) 2 × Bandgap 2 × Bandgap – P2[6] (P2[6] = 1.3 V) 2 × Bandgap + P2[6] (P2[6] = 1.3 V) 2 × Bandgap 2 × Bandgap – P2[6] (P2[6] = 1.3 V) Description Min VDD – 0.037 VSS VDD – 0.034 VSS VDD – 0.032 VSS VDD – 0.031 VSS 3.760 2.522 1.252 3.766 2.523 1.252 3.769 2.523 1.251 3.769 2.523 1.251 2.483 – P2[6] 2.522 2.524 – P2[6] 2.490 – P2[6] 2.523 2.523 – P2[6] 2.493 – P2[6] 2.523 2.523 – P2[6] 2.494 – P2[6] 2.523 2.522 – P2[6] Typ VDD – 0.007 VSS + 0.005 VDD – 0.006 VSS + 0.004 VDD – 0.005 VSS + 0.003 VDD – 0.005 VSS + 0.003 3.884 2.593 1.299 3.887 2.594 1.297 3.888 2.594 1.296 3.889 2.595 1.296 2.582 – P2[6] 2.593 2.600 – P2[6] 2.586 – P2[6] 2.594 2.598 – P2[6] 2.588 – P2[6] 2.594 2.597 – P2[6] 2.589 – P2[6] 2.595 2.596 – P2[6] Max VDD VSS + 0.029 VDD VSS + 0.024 VDD VSS + 0.022 VDD VSS + 0.020 4.006 2.669 1.342 4.010 2.670 1.342 4.013 2.671 1.343 4.015 2.671 1.344 2.674 – P2[6] 2.669 2.676 – P2[6] 2.679 – P2[6] 2.669 2.675 – P2[6] 2.682 – P2[6] 2.670 2.675 – P2[6] 2.685 – P2[6] 2.671 2.676 – P2[6] Units V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V V
VDD/2 – 0.036 VDD/2 – 0.001 VDD/2 + 0.036
VDD/2 – 0.036 VDD/2 – 0.001 VDD/2 + 0.035
VDD/2 – 0.036 VDD/2 – 0.001 VDD/2 + 0.035
VDD/2 – 0.037 VDD/2 – 0.001 VDD/2 + 0.035
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Table 19. 5-V DC Analog Reference Specifications (continued)
Reference ARF_CR [5:3] 0b101 Reference Power Settings RefPower = high Opamp bias = high Symbol VREFHI VAGND VREFLO RefPower = high Opamp bias = low VREFHI VAGND VREFLO RefPower = medium VREFHI Opamp bias = high VAGND VREFLO RefPower = medium VREFHI Opamp bias = low VAGND VREFLO 0b110 RefPower = high Opamp bias = high VREFHI VAGND VREFLO RefPower = high Opamp bias = low VREFHI VAGND VREFLO RefPower = medium VREFHI Opamp bias = high V AGND VREFLO RefPower = medium VREFHI Opamp bias = low VAGND VREFLO 0b111 RefPower = high Opamp bias = high VREFHI VAGND VREFLO RefPower = high Opamp bias = low VREFHI VAGND VREFLO RefPower = medium VREFHI Opamp bias = high V AGND VREFLO RefPower = medium VREFHI Opamp bias = low VAGND VREFLO Reference Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Description P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] – Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] – Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] – Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] – Bandgap (P2[4] = VDD/2) 2 × Bandgap Bandgap VSS 2 × Bandgap Bandgap VSS 2 × Bandgap Bandgap VSS 2 × Bandgap Bandgap VSS 3.2 × Bandgap 1.6 × Bandgap VSS 3.2 × Bandgap 1.6 × Bandgap VSS 3.2 × Bandgap 1.6 × Bandgap VSS 3.2 × Bandgap 1.6 × Bandgap VSS Min P2[4] + 1.218 P2[4] P2[4] – 1.335 P2[4] + 1.221 P2[4] P2[4] – 1.337 P2[4] + 1.222 P2[4] P2[4] – 1.338 P2[4] + 1.221 P2[4] P2[4] – 1.340 2.513 1.264 VSS 2.514 1.264 VSS 2.514 1.264 VSS 2.514 1.264 VSS 4.028 2.028 VSS 4.032 2.029 VSS 4.034 2.029 VSS 4.036 2.029 VSS Typ P2[4] + 1.291 P2[4] P2[4] – 1.294 P2[4] + 1.293 P2[4] P2[4] – 1.297 P2[4] + 1.294 P2[4] P2[4] – 1.298 P2[4] + 1.294 P2[4] P2[4] – 1.298 2.593 1.302 VSS + 0.008 2.593 1.301 VSS + 0.005 2.593 1.301 VSS + 0.004 2.593 1.300 VSS + 0.003 4.144 2.076 VSS + 0.008 4.142 2.076 VSS + 0.005 4.143 2.076 VSS + 0.004 4.144 2.076 VSS + 0.003 Max P2[4] + 1.354 P2[4] P2[4] – 1.237 P2[4] + 1.358 P2[4] P2[4] – 1.243 P2[4] + 1.360 P2[4] P2[4] – 1.245 P2[4] + 1.362 P2[4] P2[4] – 1.245 2.672 1.340 VSS + 0.038 2.674 1.340 VSS + 0.028 2.676 1.340 VSS + 0.024 2.677 1.340 VSS + 0.021 4.242 2.125 VSS + 0.034 4.245 2.126 VSS + 0.025 4.247 2.126 VSS + 0.021 4.249 2.126 VSS + 0.019 Units V – V V – V V – V V – V V V V V V V V V V V V V V V V V V V V V V V V V
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Table 20. 3.3-V DC Analog Reference Specifications
Reference ARF_CR [5:3] 0b000 Reference Power Settings RefPower = high Opamp bias = high Symbol VREFHI VAGND VREFLO RefPower = high Opamp bias = low VREFHI VAGND VREFLO RefPower = medium VREFHI Opamp bias = high V AGND VREFLO RefPower = medium VREFHI Opamp bias = low VAGND VREFLO 0b001 RefPower = high Opamp bias = high VREFHI VAGND VREFLO RefPower = high Opamp bias = low VREFHI VAGND VREFLO RefPower = medium VREFHI Opamp bias = high VAGND VREFLO RefPower = medium VREFHI Opamp bias = low VAGND VREFLO 0b010 RefPower = high Opamp bias = high VREFHI VAGND VREFLO RefPower = high Opamp bias = low VREFHI VAGND VREFLO RefPower = medium VREFHI Opamp bias = high V AGND VREFLO RefPower = medium VREFHI Opamp bias = low VAGND VREFLO Reference Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Description VDD/2 + Bandgap VDD/2 VDD/2 – Bandgap VDD/2 + Bandgap VDD/2 VDD/2 – Bandgap VDD/2 + Bandgap VDD/2 VDD/2 – Bandgap VDD/2 + Bandgap VDD/2 VDD/2 – Bandgap P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4]+P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) P2[4] P2[4]–P2[6] (P2[4] = VDD/2, P2[6] = 0.5 V) VDD VDD/2 VSS VDD VDD/2 VSS VDD VDD/2 VSS VDD VDD/2 VSS Min Typ Max Units V V V V V V V V V V V V V – V V – V V – V V – V V V V V V V V V V V V V
VDD/2 + 1.200 VDD/2 + 1.290 VDD/2 + 1.365 VDD/2 – 0.030 VDD/2 VDD/2 + 0.034 VDD/2 – 1.346 VDD/2 – 1.292 VDD/2 – 1.208 VDD/2 + 1.196 VDD/2 + 1.292 VDD/2 + 1.374 VDD/2 – 0.029 VDD/2 VDD/2 + 0.031 VDD/2 – 1.349 VDD/2 – 1.295 VDD/2 – 1.227 VDD/2 + 1.204 VDD/2 + 1.293 VDD/2 + 1.369 VDD/2 – 0.030 VDD/2 VDD/2 + 0.030 VDD/2 – 1.351 VDD/2 – 1.297 VDD/2 – 1.229 VDD/2 + 1.189 VDD/2 + 1.294 VDD/2 + 1.384 VDD/2 – 0.032 VDD/2 VDD/2 + 0.029 VDD/2 – 1.353 VDD/2 – 1.297 VDD/2 – 1.230 P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + 0.105 0.008 0.095 P2[4] P2[4] P2[4] P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + 0.035 0.006 0.053 P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + 0.094 0.005 0.073 P2[4] P2[4] P2[4] P2[4] – P2[6] – P2[4] – P2[6] + P2[4] – P2[6] + 0.033 0.002 0.042 P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + 0.094 0.003 0.075 P2[4] P2[4] – P2[6] – 0.035 P2[4] P2[4] – P2[6] P2[4] P2[4] – P2[6] + 0.038
P2[4] + P2[6] – P2[4] + P2[6] – P2[4] + P2[6] + 0.095 0.003 0.080 P2[4] P2[4] – P2[6] – 0.038 VDD – 0.119 VDD/2 – 0.028 VSS VDD – 0.131 VDD/2 – 0.028 VSS VDD – 0.111 VDD/2 – 0.029 VSS VDD – 0.128 VDD/2 – 0.029 VSS P2[4] P2[4] – P2[6] VDD – 0.005 VDD/2 VSS + 0.004 VDD – 0.004 VDD/2 VSS + 0.003 VDD – 0.003 VDD/2 VSS + 0.002 VDD – 0.003 VDD/2 VSS + 0.002 P2[4] P2[4] – P2[6] + 0.038 VDD VDD/2 + 0.029 VSS + 0.022 VDD VDD/2 + 0.028 VSS + 0.021 VDD VDD/2 + 0.028 VSS + 0.017 VDD VDD/2 + 0.029 VSS + 0.019
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Table 20. 3.3-V DC Analog Reference Specifications (continued)
Reference ARF_CR [5:3] 0b011 0b100 0b101 Reference Power Settings Symbol Reference – – Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low – – – P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] – Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] – Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] – Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] – Bandgap (P2[4] = VDD/2) 2 × Bandgap Bandgap VSS 2 × Bandgap Bandgap VSS 2 × Bandgap Bandgap VSS 2 × Bandgap Bandgap VSS – Description Min – – P2[4] + 1.214 P2[4] P2[4] – 1.335 P2[4] + 1.219 P2[4] P2[4] – 1.335 P2[4] + 1.222 P2[4] P2[4] – 1.337 P2[4] + 1.224 P2[4] P2[4] – 1.339 2.510 1.276 VSS 2.513 1.275 VSS 2.516 1.275 VSS 2.520 1.275 VSS – Typ – – P2[4] + 1.291 P2[4] P2[4] – 1.292 P2[4] + 1.293 P2[4] P2[4] – 1.295 P2[4] + 1.294 P2[4] P2[4] – 1.296 P2[4] + 1.295 P2[4] P2[4] – 1.297 2.595 1.301 VSS + 0.006 2.594 1.301 VSS + 0.004 2.595 1.301 VSS + 0.003 2.595 1.300 VSS + 0.002 – Max – – P2[4] + 1.359 P2[4] P2[4] – 1.200 P2[4] + 1.357 P2[4] P2[4] – 1.243 P2[4] + 1.356 P2[4] P2[4] – 1.244 P2[4] + 1.355 P2[4] P2[4] – 1.244 2.655 1.332 VSS + 0.031 2.656 1.331 VSS + 0.021 2.657 1.331 VSS + 0.017 2.658 1.331 VSS + 0.015 – Units – – V – V V – V V – V V – V V V V V V V V V V V V V –
All power settings. – Not allowed for 3.3 V. All power settings. – Not allowed for 3.3 V. RefPower = high Opamp bias = high VREFHI VAGND VREFLO RefPower = high Opamp bias = low VREFHI VAGND VREFLO RefPower = medium VREFHI Opamp bias = high VAGND VREFLO RefPower = medium VREFHI Opamp bias = low VAGND VREFLO
0b110
RefPower = high Opamp bias = high
VREFHI VAGND VREFLO VREFHI VAGND VREFLO
RefPower = high Opamp bias = low
RefPower = medium VREFHI Opamp bias = high V AGND VREFLO RefPower = medium VREFHI Opamp bias = low VAGND VREFLO 0b111 All power settings. – Not allowed for 3.3 V.
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10.3.8 DC Analog PSoC Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 °C and are for design guidance only. Table 21. DC Analog PSoC Block Specifications
Symbol RCT CSC Description Resistor unit value (continuous time) Capacitor unit value (switched capacitor) Min – – Typ 12.2 80 Max – – Units kΩ fF Notes
10.3.9 DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V or 3.3 V at 25 °C and are for design guidance only. Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PSoC Technical Reference Manual for more information on the VLT_CR register. Table 22. DC POR and LVD Specifications
Symbol VPPOR0R VPPOR1R VPPOR2R VPPOR0 VPPOR1 VPPOR2 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Description VDD value for PPOR trip (positive ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b VDD value for PPOR trip (negative ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b PPOR hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b VDD value for LVD trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min Typ 2.91 4.39 4.55 2.82 4.39 4.55 92 0 0 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 Max Units V V V V V V mV mV mV V V V V V V V V Notes
–
–
–
–
– – – 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72
– – – 2.98[15] 3.08 3.20 4.08 4.57 4.74[16] 4.82 4.91
Notes 15. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. 16. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply.
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10.3.10 DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 °C and are for design guidance only. Table 23. DC Programming Specifications
Symbol VDDP VDDLV VDDHV VDDIWRITE Description VDD for programming and erase Low VDD for verify High VDD for verify Supply voltage for flash write operation Min 4.5 Typ 5 Max 5.5 Units V Notes This specification applies to the functional requirements of external programmer tools This specification applies to the functional requirements of external programmer tools This specification applies to the functional requirements of external programmer tools This specification applies to this device when it is executing internal flash writes
3
3.1
3.2
V
5.1
5.2
5.3
V
3
5.25
V
IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR
Supply current during programming or verify Input low voltage during programming or verify Input high voltage during programming or verify Input current when applying VILP to P1[0] or P1[1] during programming or verify Input current when applying VIHP to P1[0] or P1[1] during programming or verify Output low voltage during programming or verify Output high voltage during programming or verify Flash endurance (per block)[17] Flash endurance (total)[18] Flash data retention
– – 2.1 – – – VDD – 1.0 50,000 1,800,000 10
15 – – – – – – – – –
30 0.8 – 0.2 1.5 VSS + 0.75 VDD – – –
mA V V mA mA V V – – Years
Driving internal pull-down resistor. Driving internal pull-down resistor.
Erase/write cycles per block. Erase/write cycles.
10.3.11 DC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 °C and are for design guidance only. Table 24. DC I2C Specifications[19]
Symbol VILI2C VIHI2C Description Input low level Input high level Min – – 0.7 × VDD Typ – – – Max 0.3 × VDD 0.25 × VDD – Units V V V Notes 3.0 V ≤ VDD ≤ 3.6 V 4.75 V ≤ VDD ≤ 5.25 V 3.0 V ≤ VDD ≤ 5.25 V
Notes 17. The 50,000 cycle flash endurance per block is only guaranteed if the flash is operating within one voltage range. Voltage ranges are 3.0 V to 3.6 V and 4.75 V to 5.25 V. 18. A maximum of 36 × 50,000 block endurance cycles is allowed. This may be balanced between operations on 36 × 1 blocks of 50,000 maximum cycles each, 36 × 2 blocks of 25,000 maximum cycles each, or 36 × 4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36 × 50,000 and ensure that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs application note Design Aids – Reading and Writing PSoC® Flash – AN2015 for more information. 19. All GPIOs meet the DC GPIO VIL and VIH specifications found in the DC GPIO Specifications sections. The I2C GPIO pins also meet the mentioned specifications.
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10.4 AC Electrical Characteristics
10.4.1 AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 °C and are for design guidance only. Table 25. AC Chip Level Specifications
Symbol FIMO245V FIMO243V FIMOUSB5V Description Internal main oscillator frequency for 24 MHz (5 V) Internal main oscillator frequency for 24 MHz (3.3 V) Internal main oscillator frequency with USB (5 V) Frequency locking enabled and USB traffic present. Internal main oscillator frequency with USB (3.3 V) Frequency locking enabled and USB traffic present. CPU frequency (5 V nominal) CPU frequency (3.3 V nominal) Digital PSoC block frequency (5 V nominal) Digital PSoC block frequency (3.3 V nominal) Internal low speed oscillator frequency Internal low speed oscillator untrimmed frequency Min 23.04 22.08 23.94 Typ 24 24 24 Max 24.96[20] 25.92[21] 24.06 Units Notes MHz Trimmed for 5 V operation using factory trim values. MHz Trimmed for 3.3 V operation using factory trim values. MHz –10 °C ≤ TA ≤ 85 °C 4.35 ≤ VDD ≤ 5.15 –0 °C ≤ TA ≤ 70 °C 3.15 ≤ VDD ≤ 3.45
FIMOUSB3V
23.94
24
24.06
MHz
FCPU1 FCPU2 FBLK5 FBLK3 F32K1 F32K_U
0.093 0.086 0 0 15 5
24 12 48 24 32 –
24.96[20] 12.96[21] 49.92[20,22] 25.92[22] 64 100
MHz MHz MHz MHz kHz kHz
SLIMO Mode = 0. SLIMO Mode = 0. Refer to the AC digital block Specifications.
After a reset and before the M8C starts to run, the ILO is not trimmed. See the System Resets section of the PSoC Technical Reference Manual for details on this timing
tXRST DC24M DCILO Step24M Fout48M FMAX SRPOWER_UP tPOWERUP
External reset pulse width 24 MHz duty cycle Internal low speed oscillator duty cycle 24 MHz trim step size 48 MHz output frequency Maximum frequency of signal on row input or row output. Power supply slew rate Time from end of POR to CPU executing code
10 40 20 – 46.08 – – –
– 50 50 50 48.0 – – 16
– 60 80 – 49.92[20,21] 12.96 250 100
µs % % kHz MHz MHz
Trimmed. Utilizing factory trim values.
tjit_IMO[23]
24 MHz IMO cycle-to-cycle jitter (RMS) 24 MHz IMO long term N cycle-to-cycle jitter (RMS) 24 MHz IMO period jitter (RMS)
– – –
200 900 200
1200 6000 900
V/ms VDD slew rate during power-up. ms Power-up from 0 V. See the System Resets section of the PSoC Technical Reference Manual. ps ps N=32 ps
Notes 20. 4.75 V < VDD < 5.25 V. 21. 3.0 V < VDD < 3.6 V. SSee application note Adjusting PSoC® Trims for 3.3 V and 2.7 V Operation – AN2012 for information on trimming for operation at 3.3 V. 22. See the individual user module datasheets for information on maximum frequencies for user modules. 23. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information.
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10.4.2 AC GPIO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 °C and are for design guidance only. Table 26. AC GPIO Specifications
Symbol FGPIO tRiseF tFallF tRiseS tFallS Description GPIO operating frequency Rise time, normal strong mode, Cload = 50 pF Fall time, normal strong mode, Cload = 50 pF Rise time, slow strong mode, Cload = 50 pF Fall time, slow strong mode, Cload = 50 pF Min 0 3 2 10 10 Typ – – – 27 22 Max 12 18 18 – – Units MHz ns ns ns ns Notes Normal strong mode VDD = 4.5 to 5.25 V, 10% to 90% VDD = 4.5 to 5.25 V, 10% to 90% VDD = 3 to 5.25 V, 10% to 90% VDD = 3 to 5.25 V, 10% to 90%
Figure 11. GPIO Timing Diagram
90% G PIO Pin O utput Voltage 10%
TRiseF TRiseS
TFallF TFallS
10.4.3 AC Full Speed USB Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –10 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –10 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 °C and are for design guidance only. Table 27. AC Full Speed (12 Mbps) USB Specifications
Symbol tRFS tFSS tRFMFS tDRATEFS Description Transition rise time Transition fall time Rise/fall time matching: (tR/tF) Full speed data rate Min 4 4 90 12 – 0.25% Typ – – – 12 Max 20 20 111 12 + 0.25% Units ns ns % Mbps Notes For 50 pF load For 50 pF load For 50 pF load
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10.4.4 AC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 °C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the analog continuous time PSoC block. Power = high and Opamp bias = high is not supported at 3.3 V. Table 28. 5-V AC Operational Amplifier Specifications
Symbol tROA Description Rising settling time from 80% of ΔV to 0.1% of ΔV (10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high Falling settling time from 20% of ΔV to 0.1% of ΔV (10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high Rising slew rate (20% to 80%)(10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high Falling slew rate (20% to 80%)(10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high Gain bandwidth product Power = low, Opamp bias = low Power = medium, Opamp bias = high Power = high, Opamp bias = high Noise at 1 kHz (Power = medium, Opamp bias = high) Min Typ Max Units
– – –
– – –
3.9 0.72 0.62
µs µs µs
tSOA
– – – 0.15 1.7 6.5 0.01 0.5 4.0 0.75 3.1 5.4 –
– – – – – – – – – – – – 100
5.9 0.92 0.72 – – – – – – – – – –
µs µs µs V/µs V/µs V/µs V/µs V/µs V/µs MHz MHz MHz nV/rt-Hz
SRROA
SRFOA
BWOA
ENOA
Table 29. 3.3-V AC Operational Amplifier Specifications
Symbol tROA Description Rising settling time from 80% of ΔV to 0.1% of ΔV (10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Falling settling time from 20% of ΔV to 0.1% of ΔV (10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Rising slew rate (20% to 80%)(10 pF load, unity gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Falling slew rate (20% to 80%)(10 pF load, Unity Gain) Power = low, Opamp bias = low Power = medium, Opamp bias = high Gain bandwidth product Power = low, Opamp bias = low Power = medium, Opamp bias = high Noise at 1 kHz (Power = medium, Opamp bias = high) Min Typ Max Units
– –
– –
3.92 0.72
µs µs
tSOA
– – 0.31 2.7 0.24 1.8 0.67 2.8 –
– – – – – – – – 100
5.41 0.72 – – – – – – –
µs µs V/µs V/µs V/µs V/µs MHz MHz nV/rt-Hz
SRROA
SRFOA
BWOA
ENOA
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When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1 K resistance and the external capacitor. Figure 12. Typical AGND Noise with P2[4] Bypass
nV/rtHz 10000
0 0.01 0.1 1.0 10
1000
100 0.001
0.01
0.1 Freq (kHz)
1
10
100
At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level. Figure 13. Typical Opamp Noise
nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000
100
10 0.001
0.01
0.1
Freq ( k Hz )
1
10
100
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10.4.5 AC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V at 25 °C and are for design guidance only. Table 30. AC Low Power Comparator Specifications
Symbol tRLPC Description LPC response time Min – Typ – Max 50 Units µs Notes ≥ 50 mV overdrive comparator reference set within VREFLPC.
10.4.6 AC Digital Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters apply to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 31. AC Digital Block Specifications
Function All functions Description Block input clock frequency VDD ≥ 4.75 V VDD < 4.75 V Input clock frequency No capture, VDD ≥ 4.75 V No capture, VDD < 4.75 V With capture Capture pulse width Input clock frequency No enable input, VDD ≥ 4.75 V No enable input, VDD < 4.75 V With enable input Enable input pulse width Kill pulse width Asynchronous restart mode Synchronous restart mode Disable mode Input clock frequency VDD ≥ 4.75 V VDD < 4.75 V Input clock frequency VDD ≥ 4.75 V VDD < 4.75 V Input clock frequency Min – – – – – 50[24] – – – 50[24] Typ – – – – – – – – – – Max 49.92 25.92 49.92 25.92 25.92 – 49.92 25.92 25.92 – Unit MHz MHz MHz MHz MHz ns MHz MHz MHz ns Notes
Timer
Counter
20 50[24] 50[24] – – – – –
– – – – – – – –
– – – 49.92 25.92 49.92 25.92 24.6
ns ns ns MHz MHz MHz MHz MHz
CRCPRS (PRS Mode) CRCPRS (CRC Mode) SPIM SPIS
Input clock frequency Input clock (SCLK) frequency Width of SS_negated between transmissions
– – 50[24]
– – –
8.2 4.1 –
MHz MHz ns
The SPI serial clock (SCLK) frequency is equal to the input clock frequency divided by 2. The input clock is the SPI SCLK in SPIS mode.
Note 24. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period).
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Table 31. AC Digital Block Specifications (continued)
Function Transmitter Description Input clock frequency VDD ≥ 4.75 V, 2 stop bits VDD ≥ 4.75 V, 1 stop bit VDD < 4.75 V Input clock frequency VDD ≥ 4.75 V, 2 stop bits VDD ≥ 4.75 V, 1 stop bit VDD < 4.75 V Min – – – – – – Typ – – – – – – Max 49.92 24.6 24.6 49.92 24.6 24.6 Unit MHz MHz MHz MHz MHz MHz Notes The baud rate is equal to the input clock frequency divided by 8.
Receiver
The baud rate is equal to the input clock frequency divided by 8.
10.4.7 AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 °C and are for design guidance only. Table 32. AC External Clock Specifications
Symbol FOSCEXT – – Duty cycle Power-up to IMO switch Description Frequency for USB applications Min 23.94 47 150 Typ 24 50 – Max 24.06 53 – Units MHz % µs Notes
10.4.8 AC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 °C and are for design guidance only. Table 33. 5-V AC Analog Output Buffer Specifications
Symbol tROB Description Rising settling time to 0.1%, 1 V Step, 100 pF load Power = low Power = high Falling settling time to 0.1%, 1 V Step, 100 pF load Power = low Power = high Rising slew rate (20% to 80%), 1 V Step, 100 pF load Power = low Power = high Falling slew rate (80% to 20%), 1 V Step, 100 pF load Power = low Power = high Small signal bandwidth, 20 mVpp, 3 dB BW, 100 pF load Power = low Power = high Large signal bandwidth, 1 Vpp, 3 dB BW, 100 pF load Power = low Power = high Min – – – – 0.65 0.65 0.65 0.65 0.8 0.8 300 300 Typ – – – – – – – – – – – – Max 2.5 2.5 2.2 2.2 – – – – – – – – Units µs µs µs µs V/µs V/µs V/µs V/µs MHz MHz kHz kHz Notes
tSOB
SRROB
SRFOB
BWOBSS
BWOBLS
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Table 34. 3.3-V AC Analog Output Buffer Specifications
Symbol tROB Description Rising settling time to 0.1%, 1 V Step, 100 pF load Power = low Power = high Falling settling time to 0.1%, 1 V Step, 100 pF load Power = low Power = high Rising slew rate (20% to 80%), 1 V Step, 100 pF load Power = low Power = high Falling slew rate (80% to 20%), 1 V Step, 100 pF load Power = low Power = high Small signal bandwidth, 20 mVpp, 3dB BW, 100 pF load Power = low Power = high Large signal bandwidth, 1 Vpp, 3dB BW, 100 pF load Power = low Power = high Min – – – – 0.5 0.5 0.5 0.5 0.7 0.7 200 200 Typ – – – – – – – – – – – – Max 3.8 3.8 2.6 2.6 – – – – – – – – Units µs µs µs µs V/µs V/µs V/µs V/µs MHz MHz kHz kHz Notes
tSOB
SRROB
SRFOB
BWOBSS
BWOBLS
10.4.9 AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at to 5 V and 3.3 V at 25 °C and are for design guidance only. Table 35. AC Programming Specifications
Symbol tRSCLK tFSCLK tSSCLK tHSCLK FSCLK tERASEB tWRITE tDSCLK tDSCLK3 tERASEALL tPROGRAM_HOT tPROGRAM_COLD Rise time of SCLK Fall time of SCLK Data setup time to falling edge of SCLK Data hold time from falling edge of SCLK Frequency of SCLK Flash erase time (block) Flash block write time Data out delay from falling edge of SCLK Data out delay from falling edge of SCLK Flash erase time (bulk) Flash block erase + flash block write time Flash block erase + flash block write time Description Min 1 1 40 40 0 – – – – – – – Typ – – – – – 10 40 – – 40 – – Max 20 20 – – 8 – – 45 50 – 100[25] 200[25] Units ns ns ns ns MHz ms ms ns ns ms ms ms VDD > 3.6 3.0 ≤ VDD ≤ 3.6 Erase all blocks and protection fields at once 0 °C ≤ Tj ≤ 100 °C –40 °C ≤ Tj ≤ 0 °C Notes
Note 25. For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs application note Design Aids – Reading and Writing PSoC® Flash – AN2015 for more information.
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10.4.10 AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V and –40 °C ≤ TA ≤ 85 °C, or 3.0 V to 3.6 V and –40 °C ≤ TA ≤ 85 °C, respectively. Typical parameters are measured at 5 V and 3.3 V at 25 °C and are for design guidance only. Table 36. AC Characteristics of the I2C SDA and SCL Pins for VDD
Symbol FSCLI2C tHDSTAI2C tLOWI2C tHIGHI2C tSUSTAI2C tHDDATI2C tSUDATI2C tSUSTOI2C tBUFI2C tSPI2C Description SCL clock frequency Hold time (repeated) start condition. After this period, the first clock pulse is generated Low period of the SCL clock High period of the SCL clock Setup time for a repeated start condition Data hold time Data setup time Setup time for stop condition Bus free time between a stop and start condition Pulse width of spikes suppressed by the input filter Standard Mode Min Max 0 100 4.0 – 4.7 4.0 4.7 0 250 4.0 4.7 – – – – – – – – – Fast Mode Min Max 0 400 0.6 – 1.3 0.6 0.6 0 100[26] 0.6 1.3 0 – – – – – – – 50 Units kHz µs µs µs µs µs ns µs µs ns Notes
Figure 14. Definition for Timing for Fast/Standard Mode on the I2C Bus
I2C_SDA TSUDATI2C THDSTAI2C I2C_SCL TSPI2C
THDDATI2CTSUSTAI2C
TBUFI2C
THIGHI2C TLOWI2C S START Condition Sr Repeated START Condition
TSUSTOI2C P STOP Condition S
Note 26. A fast-mode I2C-bus device can be used in a standard-mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns it must meet. This automatically is the case if the device does not stretch the LOW period of the SCL signal. If the device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
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10.5 Thermal Impedance
Package 56-Pin QFN[28] 68-Pin QFN[28] 100-Ball VFBGA 100-Pin TQFP Typical θJA [27] 12.93 °C/W 13.05 °C/W 65 °C/W 51 °C/W
10.6 Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability. Package 56-Pin QFN 68-Pin QFN 100-Ball VFBGA 100-Pin TQFP Maximum Peak Temperature Time at Maximum Temperature 260 °C 20 s 260 °C 20 s 260 °C 20 s 260 °C 20 s
Notes 27. TJ = TA + POWER × θJA. 28. To achieve the thermal impedance specified for the QFN package,refer to Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages available at http://www.amkor.com.
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11. Development Tool Selection
11.1 Software
11.1.1 PSoC Designer At the core of the PSoC development software suite is PSoC Designer, used to generate PSoC firmware applications. PSoC Designer is available free of charge at http://www.cypress.com and includes a free C compiler. 11.1.2 PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer. PSoC Programmer software is compatible with both PSoC ICE-Cube in-circuit emulator and PSoC MiniProg. PSoC programmer is available free of charge at http://www.cypress.com.
■ ■ ■ ■
28-Pin CY8C27443-24PXI PDIP PSoC device sample PSoC Designer software CD Getting Started guide USB 2.0 cable
11.3.2 CY3210-PSoCEval1 The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes:
■ ■ ■ ■ ■ ■
Evaluation board with LCD module MiniProg programming unit 28-Pin CY8C29466-24PXI PDIP PSoC device sample (2) PSoC Designer software CD Getting Started guide USB 2.0 cable
11.2 Development Kits
All development kits can be purchased from the Cypress Online Store. 11.2.1 CY3215-DK Basic Development Kit The CY3215-DK is for prototyping and development with PSoC Designer. This kit supports in-circuit emulation, and the software interface enables you to run, halt, and single step the processor, and view the content of specific memory locations. Advance emulation features are also supported through PSoC Designer. The kit includes:
■ ■ ■ ■ ■ ■ ■ ■ ■ ■
11.3.3 CY3214-PSoCEvalUSB The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LTXI PSoC device. The board supports both USB and capacitive sensing development and debugging support. This evaluation board also includes an LCD module, potentiometer, LEDs, an enunciator and plenty of breadboarding space to meet all of your evaluation needs. The kit includes:
■ ■ ■ ■ ■ ■ ■
PSoC Designer software CD ICE-Cube in-circuit Emulator ICE Flex-Pod for CY8C29x66 family Cat-5 adapter MiniEval programming board 110 ~ 240 V power supply, Euro-Plug adapter iMAGEcraft C compiler (registration required) ISSP cable USB 2.0 cable and Blue Cat-5 cable Two CY8C29466-24PXI 28-PDIP chip samples
PSoCEvalUSB board LCD module MIniProg programming unit Mini USB cable PSoC Designer and Example Projects CD Getting Started guide Wire pack
11.4 Device Programmers
All device programmers can be purchased from the Cypress Online Store. 11.4.1 CY3216 Modular Programmer The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes:
■ ■ ■ ■
11.3 Evaluation Tools
All evaluation tools can be purchased from the Cypress Online Store. 11.3.1 CY3210-MiniProg1 The CY3210-MiniProg1 kit enables you to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes:
■ ■ ■
Modular programmer base Three programming module cards MiniProg programming unit PSoC Designer software CD
MiniProg programming unit MiniEval socket programming and evaluation board 28-Pin CY8C29466-24PXI PDIP PSoC device sample
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■ ■
Getting Started guide USB 2.0 cable
■ ■ ■ ■
CY3207 programmer unit PSoC ISSP software CD 110 ~ 240 V power supply, Euro-Plug adapter USB 2.0 cable
11.4.2 CY3207ISSP In-System Serial Programmer (ISSP) The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. Note: CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes:
11.5 Accessories (Emulation and Programming)
Table 37. Emulation and Programming Accessories Part # CY8C24794-24LQXI Pin Package 56-pin QFN Flex-Pod Kit[29] CY3250-24X94QFN None Foot Kit[30] Adapter[31] Adapters can be found at http://www.emulation.com.
Notes 29. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. 30. Foot kit includes surface mount feet that are soldered to the target PCB. 31. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters are found at http://www.emulation.com.
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12. Ordering Information
Table 38. CY8C24x94 PSoC Device’s Key Features and Ordering Information Analog Outputs 2 2 2 2 2 2 2 2 2 2 2 2 2 Digital I/O Pins Analog Blocks Analog Inputs Digital Blocks Temperature Range
100-pin OCD TQFP[32] 100-ball OCD (6 × 6 mm) VFBGA[32] 68-pin OCD (8 × 8 mm) QFN (Sawn) 68-pin OCD (8 × 8 mm) QFN (Sawn) (Tape and Reel) 56-pin (7 × 7 mm) QFN 56-pin (7 × 7 mm) QFN (Tape and Reel) 56-pin (8 × 8 mm) QFN (Sawn) 56-pin (8 × 8 mm) QFN (Sawn) (Tape and Reel) 56-pin (8 × 8 mm) QFN (Sawn) 56-pin (8 × 8 mm) QFN (Sawn) (Tape and Reel) 100-ball (6 × 6 mm) VFBGA 68-pin (8 × 8 mm) QFN (Sawn) 68-pin QFN (8 × 8 mm) (Sawn) (Tape and Reel)
51-85048 51-85209 001-09618
CY8C24094-24AXI CY8C24094-24BVXI CY8C24094-24LTXI CY8C24094-24LTXIT
16 K 16 K 16 K 16 K
1K 1K 1K 1K
–40 °C to +85 °C 4 –40 °C to +85 °C 4 –40 °C to +85 °C 4 –40 °C to +85 °C 4
6 6 6 6
56 56 56 56
48 48 48 48
Yes Yes Yes Yes
001-58740
CY8C24794-24LQXI CY8C24794-24LQXIT CY8C24794-24LTXI CY8C24794-24LTXIT
16 K 16 K 16 K 16 K 16 K 16 K 16 K 16 K 16 K
1K 1K 1K 1K 1K 1K 1K 1K 1K
–40 °C to +85 °C 4 –40 °C to +85 °C 4 –40 °C to +85 °C 4 –40 °C to +85 °C 4 –40 °C to +85 °C 4 –40 °C to +85 °C 4 –40 °C to +85 °C 4 –40 °C to +85 °C 4 –40 °C to +85 °C 4
6 6 6 6 6 6 6 6 6
50 50 50 50 49 49 56 56 56
48 48 48 48 47 47 48 48 48
No No No No Yes Yes Yes Yes Yes
001-53450
001-53450
CY8C24894-24LTXI CY8C24894-24LTXIT
51-85209 001-09618
CY8C24994-24BVXI CY8C24994-24LTXI CY8C24994-24LTXIT
Note For die sales information, contact a local Cypress sales office or Field Applications Engineer (FAE).
Note 32. This part may be used for in-circuit debugging. It is NOT available for production.
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XRES Pin
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Ordering Code
Package diagram
Package
Flash (Bytes)
SRAM (Bytes)
CY8C24094, CY8C24794 CY8C24894, CY8C24994
12.1 Ordering Code Definitions
CY 8 C 24 XXX- SP XXT Package Type: T = Tape and Reel PX = PDIP Pb-free SX = SOIC Pb-free PVX = SSOP Pb-free LFX = QFN (punched, 8 × 8 mm), Pb-free LTX = QFN (sawn, 8 × 8 mm), Pb-free LQX = QFN (sawn, 7 × 7 mm), Pb-free AX = TQFP Pb-free BVX = VFBGA Pb-free Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = PSoC Company ID: CY = Cypress Thermal Rating: C = Commercial I = Industrial E = Extended
13. Packaging Dimensions
This section illustrates the package specification for the CY8C24x94 PSoC devices, along with the thermal impedance for the package and solder reflow peak temperatures. Important Note Emulation tools may require a larger area on the target PCB than the chip's footprint. For a detailed description of the emulation tools' dimensions, refer to the emulator pod dimension drawings athttp://www.cypress.com/design/MR10161. Figure 15. 56-Pin (7 × 7 × 0.6 mm) QFN
SOLDERABLE EXPOSED PAD
TOP VIEW
NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED PAD
SIDE VIEW
BOTTOM VIEW
2. BASED ON REF JEDEC # MO-220 3. PACKAGE WEIGHT: 0.0928 grams 4. ALL DIMENSIONS ARE IN MILLIMETERS
001-58740 **
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Figure 16. 56-Pin (8 × 8 mm) QFN
TOP VIEW SIDE VIEW
0.08[0.003] A 7.90[0.311] 8.10[0.319] 7.70[0.303] 7.80[0.307] N 1 0.80[0.031] DIA. 2 1.00[0.039] MAX. 0.05[0.002] MAX. 0.80[0.031] MAX. 0.20[0.008] REF. C 4.5 0.18[0.007] 0.28[0.011] N 1 2 0.45[0.018] PIN1 ID 0.20[0.008] R.
BOTTOM VIEW
7.70[0.303] 7.80[0.307]
7.90[0.311] 8.10[0.319]
5.2
0°-12°
C
SEATING PLANE
0.30[0.012] 0.50[0.020] 6.45[0.254] 6.55[0.258]
0.50[0.020]
0.24[0.009] 0.60[0.024]
(4X)
NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED METAL. 2. REFERENCE JEDEC#: MO-220 3. PACKAGE WEIGHT: 0.162g 4. ALL DIMENSIONS ARE IN MM [MIN/MAX] 5. PACKAGE CODE PART # LF56A LY56A DESCRIPTION STANDARD PB-FREE
001-12921 *A
Figure 17. 56-Pin QFN (8 × 8 × 0.9 mm) – Sawn
001-53450 *B
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6.45[0.254] 6.55[0.258]
SOLDERABLE EXPOSED PAD
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Figure 18. 68-Pin Sawn QFN (8 × 8 mm × 0.90 mm)
TOP VIEW
SIDE VIEW
BOTTOM VIEW
0.900±0.100 8.000±0.100 0.200 REF 5.7±0.10 0.400 PITCH PIN1 ID R 0.20
6 8 1
PIN 1 DOT
5 2 5 1 5 1
5 2
6 8
1
8.000±0.100
5.7±0.10
0.20±0.05
1 7 1 8 3 4
3 5
0.05 MAX
SEATING PLANE
0.400±0.1005
3 3 4
6.40 REF
1 8
1 7
NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED METAL.
2. REFERENCE JEDEC#: MO-220 3. PACKAGE WEIGHT: 0.17g 4. ALL DIMENSIONS ARE IN MILLIMETERS
0.08
C
001-09618 *C
Figure 19. 100-Ball (6 × 6 mm) VFBGA
TOP VIEW BOTTOM VIEW A1 CORNER Ø0.05 M C A1 CORNER 1 2 3 4 5 6 7 8 9 10 A B C D E F G H J K Ø0.15 M C A B Ø0.30±0.05(100X) 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K
6.00±0.10
6.00±0.10
4.50
0.50
2.25
A B 6.00±0.10
A
2.25 0.50 4.50 B 6.00±0.10
0.45 REF.
0.10 C
0.21±0.05
0.08 C
0.15(4X)
SEATING PLANE 0.21 REF. 1.00 MAX C
REFERENCE JEDEC MO-195C PKG. WEIGHT: TBD (NEW PKG.)
51-85209 *C
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6.40 REF
LASER MARK
SOLDERABLE EXPOSED PAD
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Figure 20. 100-Pin (14 × 14 × 1.4 mm) TQFP
51-85048 *D
Important Note
■ ■
For information on the preferred dimensions for mounting QFN packages, refer to Application Note, Application Notes for Surface Mount Assembly of Amkor's MicroLeadFrame (MLF) Packages available at http://www.amkor.com. Pinned vias for thermal conduction are not required for the low power PSoC device.
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14. Acronyms
14.1 Acronyms Used
The following table lists the acronyms that are used in this document. Acronym AC ADC API CMOS CPU CRC CT DAC DC DTMF alternating current analog-to-digital converter application programming interface complementary metal oxide semiconductor central processing unit cyclic redundancy check continuous time digital-to-analog converter direct current dual-tone multi-frequency Description Acronym MIPS OCD PCB PDIP PGA POR PPOR PRS PSoC® PWM QFN SAR SC SLIMO SOIC SPI™ SRAM SROM TQFP UART USB VFBGA WDT XRES on-chip debug printed circuit board plastic dual-in-line package programmable gain amplifier power-on reset precision power-on reset pseudo-random sequence Programmable System-on-Chip™ pulse-width modulator quad flat no leads successive approximation register switched capacitor slow IMO small-outline integrated circuit serial peripheral interface static random-access memory supervisory read-only memory thin quad flat pack universal asynchronous receiver / transmitter universal serial bus very fine-pitch ball grid array watchdog timer external reset Description million instructions per second
EEPROM electrically erasable programmable read-only memory GPIO ICE IDE ILO IMO I/O IrDA ISSP LCD LED LPC LVD MAC MCU general purpose I/O in-circuit emulator integrated development environment internal low speed oscillator internal main oscillator input/output infrared data association In-System Serial Programming liquid crystal display light-emitting diode low power comparator low voltage detect multiply-accumulate microcontroller unit
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15. Document Conventions
15.1 Units of Measure
Symbol °C dB fF kHz kΩ MHz μA μs μV mA mm ms Unit of Measure degree Celsius decibels femto farad kilohertz kilohm megahertz microampere microsecond microvolts milli-ampere milli-meter milli-second Symbol mV nA ns nV Ω pA pF ps % rt-Hz V W Unit of Measure milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad picosecond percent root hertz volts watts
15.2 Numeric Conventions
Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, ‘01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.
Glossary
active high 1. A logic signal having its asserted state as the logic 1 state. 2. A logic signal having the logic 1 state as the higher voltage of the two states. The basic programmable opamp circuits. These are SC (switched capacitor) and CT (continuous time) blocks. These blocks can be interconnected to provide ADCs, DACs, multi-pole filters, gain stages, and much more. A device that changes an analog signal to a digital signal of corresponding magnitude. Typically, an ADC converts a voltage to a digital number. The digital-to-analog (DAC) converter performs the reverse operation. A series of software routines that comprise an interface between a computer application and lower level services and functions (for example, user modules and libraries). APIs serve as building blocks for programmers that create software applications. A signal whose data is acknowledged or acted upon immediately, irrespective of any clock signal. A stable voltage reference design that matches the positive temperature coefficient of VT with the negative temperature coefficient of VBE, to produce a zero temperature coefficient (ideally) reference. 1. The frequency range of a message or information processing system measured in hertz. 2. The width of the spectral region over which an amplifier (or absorber) has substantial gain (or loss); it is sometimes represented more specifically as, for example, full width at half maximum. 1. A systematic deviation of a value from a reference value. 2. The amount by which the average of a set of values departs from a reference value. 3. The electrical, mechanical, magnetic, or other force (field) applied to a device to establish a reference level to operate the device. Page 52 of 59
analog blocks
analog-to-digital (ADC)
API (Application Programming Interface) asynchronous Bandgap reference
bandwidth
bias
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Glossary
block
(continued) 1. A functional unit that performs a single function, such as an oscillator. 2. A functional unit that may be configured to perform one of several functions, such as a digital PSoC block or an analog PSoC block. 1. A storage area for data that is used to compensate for a speed difference, when transferring data from one device to another. Usually refers to an area reserved for IO operations, into which data is read, or from which data is written. 2. A portion of memory set aside to store data, often before it is sent to an external device or as it is received from an external device. 3. An amplifier used to lower the output impedance of a system. 1. A named connection of nets. Bundling nets together in a bus makes it easier to route nets with similar routing patterns. 2. A set of signals performing a common function and carrying similar data. Typically represented using vector notation; for example, address[7:0]. 3. One or more conductors that serve as a common connection for a group of related devices. The device that generates a periodic signal with a fixed frequency and duty cycle. A clock is sometimes used to synchronize different logic blocks. An electronic circuit that produces an output voltage or current whenever two input levels simultaneously satisfy predetermined amplitude requirements. A program that translates a high level language, such as C, into machine language. In PSoC devices, the register space accessed when the XIO bit, in the CPU_F register, is set to ‘1’. An oscillator in which the frequency is controlled by a piezoelectric crystal. Typically a piezoelectric crystal is less sensitive to ambient temperature than other circuit components.
buffer
bus
clock
comparator
compiler configuration space crystal oscillator
cyclic redundancy A calculation used to detect errors in data communications, typically performed using a linear check (CRC) feedback shift register. Similar calculations may be used for a variety of other purposes such as data compression. data bus A bi-directional set of signals used by a computer to convey information from a memory location to the central processing unit and vice versa. More generally, a set of signals used to convey data between digital functions. A hardware and software system that allows the user to analyze the operation of the system under development. A debugger usually allows the developer to step through the firmware one step at a time, set break points, and analyze memory. A period of time when neither of two or more signals are in their active state or in transition. The 8-bit logic blocks that can act as a counter, timer, serial receiver, serial transmitter, CRC generator, pseudo-random number generator, or SPI. A device that changes a digital signal to an analog signal of corresponding magnitude. The analogto-digital (ADC) converter performs the reverse operation. The relationship of a clock period high time to its low time, expressed as a percent.
debugger
dead band digital blocks
digital-to-analog (DAC) duty cycle
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Glossary
emulator
(continued) Duplicates (provides an emulation of) the functions of one system with a different system, so that the second system appears to behave like the first system. An active high signal that is driven into the PSoC device. It causes all operation of the CPU and blocks to stop and return to a pre-defined state. An electrically programmable and erasable, non-volatile technology that provides users with the programmability and data storage of EPROMs, plus in-system erasability. Non-volatile means that the data is retained when power is off. The smallest amount of Flash ROM space that may be programmed at one time and the smallest amount of Flash space that may be protected. A Flash block holds 64 bytes. The number of cycles or events per unit of time, for a periodic function. The ratio of output current, voltage, or power to input current, voltage, or power, respectively. Gain is usually expressed in dB. A two-wire serial computer bus by Philips Semiconductors (now NXP Semiconductors). I2C is an Inter-Integrated Circuit. It is used to connect low-speed peripherals in an embedded system. The original system was created in the early 1980s as a battery control interface, but it was later used as a simple internal bus system for building control electronics. I2C uses only two bi-directional pins, clock and data, both running at +5V and pulled high with resistors. The bus operates at 100 kbits/second in standard mode and 400 kbits/second in fast mode. The in-circuit emulator that allows users to test the project in a hardware environment, while viewing the debugging device activity in a software environment (PSoC Designer).
external reset (XRES) flash
Flash block
frequency gain I2C
ICE
input/output (I/O) A device that introduces data into or extracts data from a system. interrupt A suspension of a process, such as the execution of a computer program, caused by an event external to that process, and performed in such a way that the process can be resumed. A block of code that normal code execution is diverted to when the M8C receives a hardware interrupt. Many interrupt sources may each exist with its own priority and individual ISR code block. Each ISR code block ends with the RETI instruction, returning the device to the point in the program where it left normal program execution. 1. A misplacement of the timing of a transition from its ideal position. A typical form of corruption that occurs on serial data streams. 2. The abrupt and unwanted variations of one or more signal characteristics, such as the interval between successive pulses, the amplitude of successive cycles, or the frequency or phase of successive cycles.
interrupt service routine (ISR)
jitter
low-voltage detect A circuit that senses VDD and provides an interrupt to the system when VDD falls lower than a (LVD) selected threshold. M8C An 8-bit Harvard-architecture microprocessor. The microprocessor coordinates all activity inside a PSoC by interfacing to the Flash, SRAM, and register space. A device that controls the timing for data exchanges between two devices. Or when devices are cascaded in width, the master device is the one that controls the timing for data exchanges between the cascaded devices and an external interface. The controlled device is called the slave device.
master device
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Glossary
(continued) An integrated circuit chip that is designed primarily for control systems and products. In addition to a CPU, a microcontroller typically includes memory, timing circuits, and IO circuitry. The reason for this is to permit the realization of a controller with a minimal quantity of chips, thus achieving maximal possible miniaturization. This in turn, reduces the volume and the cost of the controller. The microcontroller is normally not used for general-purpose computation as is a microprocessor. The reference to a circuit containing both analog and digital techniques and components. A device that imposes a signal on a carrier. 1. A disturbance that affects a signal and that may distort the information carried by the signal. 2. The random variations of one or more characteristics of any entity such as voltage, current, or data. A circuit that may be crystal controlled and is used to generate a clock frequency. A technique for testing transmitting data. Typically, a binary digit is added to the data to make the sum of all the digits of the binary data either always even (even parity) or always odd (odd parity). An electronic circuit that controls an oscillator so that it maintains a constant phase angle relative to a reference signal. The pin number assignment: the relation between the logical inputs and outputs of the PSoC device and their physical counterparts in the printed circuit board (PCB) package. Pinouts involve pin numbers as a link between schematic and PCB design (both being computer generated files) and may also involve pin names. A group of pins, usually eight. A circuit that forces the PSoC device to reset when the voltage is lower than a pre-set level. This is one type of hardware reset. Cypress Semiconductor’s PSoC® is a registered trademark and Programmable System-onChip™ is a trademark of Cypress.
microcontroller
mixed-signal modulator noise
oscillator parity
phase-locked loop (PLL) pinouts
port power on reset (POR) PSoC®
PSoC Designer™ The software for Cypress’ Programmable System-on-Chip technology. pulse width An output in the form of duty cycle which varies as a function of the applied measurand modulator (PWM) RAM An acronym for random access memory. A data-storage device from which data can be read out and new data can be written in. A storage device with a specific capacity, such as a bit or byte. A means of bringing a system back to a know state. See hardware reset and software reset. An acronym for read only memory. A data-storage device from which data can be read out, but new data cannot be written in. 1. Pertaining to a process in which all events occur one after the other. 2. Pertaining to the sequential or consecutive occurrence of two or more related activities in a single device or channel.
register reset ROM
serial
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Glossary
settling time
(continued) The time it takes for an output signal or value to stabilize after the input has changed from one value to another. A memory storage device that sequentially shifts a word either left or right to output a stream of serial data. A device that allows another device to control the timing for data exchanges between two devices. Or when devices are cascaded in width, the slave device is the one that allows another device to control the timing of data exchanges between the cascaded devices and an external interface. The controlling device is called the master device. An acronym for static random access memory. A memory device allowing users to store and retrieve data at a high rate of speed. The term static is used because, after a value has been loaded into an SRAM cell, it remains unchanged until it is explicitly altered or until power is removed from the device. An acronym for supervisory read only memory. The SROM holds code that is used to boot the device, calibrate circuitry, and perform Flash operations. The functions of the SROM may be accessed in normal user code, operating from Flash. A signal following a character or block that prepares the receiving device to receive the next character or block. 1. A signal whose data is not acknowledged or acted upon until the next active edge of a clock signal. 2. A system whose operation is synchronized by a clock signal. A function whose output can adopt three states: 0, 1, and Z (high-impedance). The function does not drive any value in the Z state and, in many respects, may be considered to be disconnected from the rest of the circuit, allowing another output to drive the same net. A UART or universal asynchronous receiver-transmitter translates between parallel bits of data and serial bits. Pre-build, pre-tested hardware/firmware peripheral functions that take care of managing and configuring the lower level Analog and Digital PSoC Blocks. User Modules also provide high level API (Application Programming Interface) for the peripheral function. The bank 0 space of the register map. The registers in this bank are more likely to be modified during normal program execution and not just during initialization. Registers in bank 1 are most likely to be modified only during the initialization phase of the program. A name for a power net meaning "voltage drain." The most positive power supply signal. Usually 5 V or 3.3 V. A name for a power net meaning "voltage source." The most negative power supply signal. A timer that must be serviced periodically. If it is not serviced, the CPU resets after a specified period of time.
shift register
slave device
SRAM
SROM
stop bit
synchronous
tri-state
UART
user modules
user space
VDD
VSS watchdog timer
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CY8C24094, CY8C24794 CY8C24894, CY8C24994
16. Document History Page
Document Title: CY8C24094, CY8C24794, CY8C24894, CY8C24994 PSoC® Programmable System-on-Chip™ Document Number: 38-12018 Revision ** *A *B ECN 133189 251672 289742 Orig. of Change NWJ SFV HMT Submission Date 01/27/2004 See ECN See ECN Description of Change New silicon and new document – Advance datasheet. First Preliminary datasheet. Changed title to encompass only the CY8C24794 because the CY8C24494 and CY8C24694 are not being offered by Cypress. Add standard DS items from SFV memo. Add Analog Input Mux on pinouts. 2 MACs. Change 512 bytes of SRAM to 1 K. Add dimension key to package. Remove HAPI. Update diagrams, registers and specs. Add CY logo. Update CY copyright. Update new CY.com URLs. Re-add ISSP programming pinout notation. Add Reflow Temp. table. Update features (MAC, Oscillator, and voltage range), registers (INT_CLR2/MSK2, second MAC), and specs. (Rext, IMO, analog output buffer...). Add new color and logo. Expand analog arch. diagram. Fix I/O #. Update Electrical Specifications. Add USB temperature specifications. Make datasheet Final. Remove USB logo. Add URL to preferred dimensions for mounting MLF packages. Add new device, CY8C24894 56-pin MLF with XRES pin. Add Fimousb3v char. to specs. Upgrade to CY Perform logo and update corporate address and copyright. Add ISSP note to pinout tables. Update typical and recommended Storage Temperature per industrial specs. Update Low Output Level maximum I/OL budget. Add FLS_PR1 to Register Map Bank 1 for users to specify which Flash bank should be used for SROM operations. Add two new devices for a 68-pin QFN and 100-ball VFBGA under RPNs: CY8C24094 and CY8C24994. Add two packages for 68-pin QFN. Add OCD non-production pinouts and package diagrams. Update CY branding and QFN convention. Add new Dev. Tool section. Update copyright and trademarks. Add Low Power Comparator (LPC) AC/DC electrical spec. tables. Add CY8C20x34 to PSoC Device Characteristics table. Add detailed dimensions to 56-pin QFN package diagram and update revision. Secure one package diagram/manufacturing per QFN. Update emulation pod/feet kit part numbers. Fix pinout type-o per TestTrack. Add CapSense SNR requirement reference. Update figure standards. Update Technical Training paragraphs. Add QFN package clarifications and dimensions. Update ECN-ed Amkor dimensioned QFN package diagram revisions. Reword SNR reference. Add new 56-pin QFN spec. Add footnote on AGND descriptions to avoid using P2[4] for digital signaling as it may add noise to AGND. Remove reference to CMP_GO_EN1 in Map Bank 1 Table on Address 65; this register has no functionality on 24xxx. Add footnote on die sales. Add description 'Optional External Clock Input’ on P1[4] to match description of P1[4]. Updated Programmable Pin Configuration detail. Changed title from PSoC® Mixed-Signal Array to PSoC® Programmable System-on-Chip™ Added package diagram 001-09618 and updated Ordering Information table
*C
335236
HMT
See ECN
*D *E *F *G
344318 346774 349566 393164
HMT HMT HMT HMT
See ECN See ECN See ECN See ECN
*H
469243
HMT
See ECN
*I
561158
HMT
See ECN
*J
728238
HMT
See ECN
*K
2552459
AZIE/PYRS
08/14/08
*L
2616550 OGNE/PYRS
12/05/08
*M
2657956
DPT/PYRS
02/11/09
Document Number: 38-12018 Rev. *Z
Page 57 of 59
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CY8C24094, CY8C24794 CY8C24894, CY8C24994
Document Title: CY8C24094, CY8C24794, CY8C24894, CY8C24994 PSoC® Programmable System-on-Chip™ Document Number: 38-12018 *N 2708135 BRW 05/18/2009 Added Note in the Pin Information section on page 8. Removed reference to Hi-Tech Lite Compiler in the section Development Tools Selection on page 42. Added 56-Pin QFN (Sawn) package diagram and updated ordering information Updated the following parameters: DCILO, F32K_U, FIMO6, TPOWERUP, TERASE_ALL, TPROGRAM_HOT, and TPROGRAM_COLD. Added SRPOWER_UP parameter in AC specs table. Ordering Information table: Changed XRES Pin value for CY8C24894-24LTXI and CY8C24894-24LTXIT to ‘Yes’. Ordering Information: Updated CY8C24894-24LTXI and CY8C24894-24LTXIT parts as Sawn and updated the Digital I/O and Analog Pin values Added Contents page. Updated 68 QFN package diagram (51-85124) Added package diagram 001-58740 and updated Development Tools section. Modified Note 9 to remove voltage range 2.4 V to 3.0 V Updated Cypress website links Added TXRST, DC24M, TBAKETEMP and TBAKETIME parameters Removed reference to 2.4 V Removed sections ‘Third Party Tools’ ‘Build a PSoC Emulator into your Board’ Updated package diagrams Removed inactive parts from ordering information table. Updated content to match current style guide and datasheet template. No technical updates Added PSoC Device Characteristics table . Added DC I2C Specifications table. Added F32K_U max limit. Added Tjit_IMO specification, removed existing jitter specifications. Updated Analog reference tables. Updated Units of Measure, Acronyms, Glossary, and References sections. Updated solder reflow specifications. No specific changes were made to AC Digital Block Specifications table and I2C Timing Diagram. They were updated for clearer understanding. Updated Figure 12 since the labelling for y-axis was incorrect. Template and styles update. Sunset review; no updates. Updated solder reflow specifications. Removed FIMO6 spec from AC chip-level specifications table. Removed the following pruned parts from the ordering information table and their references in the datasheet. 1) CY8C24794-24LFXI 2) CY8C24794-24LFXIT 3) CY8C24894-24LFXI 4) CY8C24894-24LFXIT Updated ordering information. Removed the package diagram spec 51-85214 since there are no MPNs in the ordering information table that corresponds with this package. Updated ordering code definitions for clearer understanding.
*O *P
2718162 2762161
DPT RLRM
06/11/2009 09/10/2009
*Q *R
2768530 2817938
RLRM KRIS
09/24/09 11/30/09
*S *T *U
2846641 2867363 2901653
RLRM ANUP NJF
1/12/10 01/27/10 03/30/2010
*V *W
2938528 3028596
VMAD NJF
05/28/2010 09/20/10
*X *Y
3082244 3111357
NXZ BTK/NJF/ ARVM
11/09/2010 12/15/10
*Z
3126167
BTK/ANBA/ PKS
01/03/11
Document Number: 38-12018 Rev. *Z
Page 58 of 59
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CY8C24094, CY8C24794 CY8C24894, CY8C24994
17. Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations.
Products
Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless
PSoC Solutions
psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5
© Cypress Semiconductor Corporation, 2004-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 38-12018 Rev. *Z
®
Revised January 3, 2011
Page 59 of 59
PSoC Designer™ is a trademark and PSoC is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations.
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