Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
PSoC® 3: CY8C32 Family Data Sheet
®
Programmable System-on-Chip (PSoC )
General Description
PSoC® 3 is a true programmable embedded system-on-chip, integrating configurable analog and digital peripherals, memory, and a
microcontroller on a single chip. The PSoC 3 architecture boosts performance through:
8051 core plus DMA controller at up to 50 MHz
Ultra low power with industry's widest voltage range
Programmable digital and analog peripherals enable custom functions
Flexible routing of any analog or digital peripheral function to any pin
PSoC devices employ a highly configurable system-on-chip architecture for embedded control design. They integrate configurable
analog and digital circuits, controlled by an on-chip microcontroller. A single PSoC device can integrate as many as 100 digital and
analog peripheral functions, reducing design time, board space, power consumption, and system cost while improving system quality.
Features
Operating characteristics
Analog peripherals
Voltage range: 1.71 to 5.5 V, up to six power domains
[1]
Temperature range (ambient) –40 to 85 °C
DC to 50-MHz operation
Power modes
• Active mode 1.2 mA at 6 MHz, and 12 mA at 48 MHz
• 1-µA sleep mode
• 200-nA hibernate mode with RAM retention
Boost regulator from 0.5-V input up to 5-V output
Performance
8-bit 8051 CPU, 32 interrupt inputs
24-channel direct memory access (DMA) controller
Configurable 8- to 12-bit delta-sigma ADC
8-bit DAC
Two comparators
®
CapSense support, up to 62 sensors
1.024 V ±1% internal voltage reference
Memories
Up to 64 KB program flash, with cache and security features
Up to 8 KB additional flash for error correcting code (ECC)
Up to 8 KB RAM
Up to 2 KB EEPROM
Digital peripherals
Four 16-bit timer, counter, and PWM (TCPWM) blocks
I2C, 1 Mbps bus speed
USB 2.0 certified Full-Speed (FS) 12 Mbps peripheral
interface (TID#40770053) using internal oscillator[2]
16 to 24 universal digital blocks (UDB), programmable to
create any number of functions:
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• I2C, UART, SPI, I2S, LIN 2.0 interfaces
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generators
• Quadrature decoders
• Gate-level logic functions
Programmable clocking
3- to 24-MHz internal oscillator, 2% accuracy at 3 MHz
4- to 25-MHz external crystal oscillator
Internal PLL clock generation up to 50 MHz
Low-power internal oscillator at 1, 33, and 100 kHz
32.768-kHz external watch crystal oscillator
12 clock dividers routable to any peripheral or I/O
Versatile I/O system
29 to 72 I/O pins – up to 62 general-purpose I/Os (GPIOs)
Up to eight performance I/O (SIO) pins
• 25 mA current sink
• Programmable input threshold and output high voltages
• Can act as a general-purpose comparator
• Hot swap capability and overvoltage tolerance
Up to two USBIO pins that can be used as GPIOs
Route any digital or analog peripheral to any GPIO
LCD direct drive from any GPIO, up to 46 × 16 segments
CapSense support from any GPIO
1.2-V to 5.5-V interface voltages, up to four power domains
Programming and debug
JTAG (4-wire), serial wire debug (SWD) (2-wire), and single
wire viewer (SWV) interfaces
2
Bootloader programming through I C, SPI, UART, USB, and
other interfaces
Package options: 48-pin SSOP, 48-pin QFN, 68-pin QFN,
100-pin TQFP, and 72-pin WLCSP
Development support with free PSoC Creator™ tool
Schematic and firmware design support
Over 100 PSoC Components™ integrate multiple ICs and
system interfaces into one PSoC. Components are free
embedded ICs represented by icons. Drag and drop
component icons to design systems in PSoC Creator.
Includes free Keil 8051 compiler
Supports device programming and debugging
Notes
1. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. This feature on select devices only. See Ordering Information on page 111 for details.
Cypress Semiconductor Corporation
Document Number: 001-56955 Rev. AB
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised June 23, 2022
PSoC® 3: CY8C32 Family Data Sheet
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP. Following is an abbreviated list for PSoC 3:
Overview: PSoC Portfolio, PSoC Roadmap
Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP
In addition, PSoC Creator includes a device selection tool.
Application notes: Cypress offers a large number of PSoC
application notes and code examples covering a broad range
of topics, from basic to advanced level. Recommended application notes for getting started with PSoC 3 are:
AN54181: Getting Started With PSoC 3
AN61290: Hardware Design Considerations
AN57821: Mixed Signal Circuit Board Layout
AN58304: Pin Selection for Analog Designs
AN81623: Digital Design Best Practices
AN73854: Introduction To Bootloaders
Development Kits:
CY8CKIT-030 is designed for analog performance, for developing high-precision analog, low-power, and low-voltage applications.
CY8CKIT-001 provides a common development platform for
any one of the PSoC 1, PSoC 3, PSoC 4, or PSoC 5LP
families of devices.
The MiniProg3 device provides an interface for flash programming and debug.
Technical Reference Manuals (TRM)
Architecture TRM
Registers TRM
Programming Specification
PSoC Creator
PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100
pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can:
3. Configure components using the configuration tools
1. Drag and drop component icons to build your hardware
system design in the main design workspace
4. Explore the library of 100+ components
2. Codesign your application firmware with the PSoC hardware,
5. Review component datasheets
using the PSoC Creator IDE C compiler
Figure 1. Multiple-Sensor Example Project in PSoC Creator
Document Number: 001-56955 Rev. AB
Page 2 of 128
PSoC® 3: CY8C32 Family Data Sheet
Contents
1. Architectural Overview ................................................ 4
2. Pinouts .......................................................................... 6
3. Pin Descriptions ......................................................... 12
4. CPU .............................................................................. 13
4.1 8051 CPU ............................................................ 13
4.2 Addressing Modes ............................................... 13
4.3 Instruction Set ..................................................... 14
4.4 DMA and PHUB .................................................. 18
4.5 Interrupt Controller .............................................. 20
5. Memory ........................................................................ 24
5.1 Static RAM .......................................................... 24
5.2 Flash Program Memory ....................................... 24
5.3 Flash Security ...................................................... 24
5.4 EEPROM ............................................................. 24
5.5 Nonvolatile Latches (NVLs) ................................. 25
5.6 External Memory Interface .................................. 26
5.7 Memory Map ....................................................... 26
6. System Integration ..................................................... 28
6.1 Clocking System .................................................. 28
6.2 Power System ..................................................... 31
6.3 Reset ................................................................... 36
6.4 I/O System and Routing ...................................... 37
7. Digital Subsystem ...................................................... 45
7.1 Example Peripherals ........................................... 45
7.2 Universal Digital Block ......................................... 47
7.3 UDB Array Description ........................................ 50
7.4 DSI Routing Interface Description ....................... 50
7.5 USB ..................................................................... 52
7.6 Timers, Counters, and PWMs ............................. 52
7.7 I2C ....................................................................... 53
8. Analog Subsystem ..................................................... 55
8.1 Analog Routing .................................................... 56
8.2 Delta-sigma ADC ................................................. 58
8.3 Comparators ........................................................ 59
8.4 LCD Direct Drive ................................................. 60
8.5 CapSense ............................................................ 61
8.6 Temp Sensor ....................................................... 61
8.7 DAC ..................................................................... 61
Document Number: 001-56955 Rev. AB
9. Programming, Debug Interfaces, Resources ........... 62
9.1 JTAG Interface .................................................... 62
9.2 Serial Wire Debug Interface ................................ 64
9.3 Debug Features ................................................... 65
9.4 Trace Features .................................................... 65
9.5 Single Wire Viewer Interface ............................... 65
9.6 Programming Features ........................................ 65
9.7 Device Security ................................................... 65
9.8 CSP Package Bootloader .................................... 66
10. Development Support .............................................. 66
10.1 Documentation .................................................. 66
10.2 Online ................................................................ 66
10.3 Tools .................................................................. 66
11. Electrical Specifications .......................................... 67
11.1 Absolute Maximum Ratings ............................... 67
11.2 Device Level Specifications ............................... 68
11.3 Power Regulators .............................................. 72
11.4 Inputs and Outputs ............................................ 76
11.5 Analog Peripherals ............................................ 84
11.6 Digital Peripherals ............................................. 96
11.7 Memory ............................................................. 99
11.8 PSoC System Resources ................................ 105
11.9 Clocking ........................................................... 107
12. Ordering Information .............................................. 111
12.1 Part Numbering Conventions .......................... 112
13. Packaging ................................................................ 113
14. Acronyms ................................................................ 117
15. Reference Documents ............................................ 118
16. Document Conventions ......................................... 119
16.1 Units of Measure ............................................. 119
17. Revision History ..................................................... 120
18. Sales, Solutions, and Legal Information .............. 128
Worldwide Sales and Design Support ..................... 128
Products .................................................................. 128
PSoC® Solutions .................................................... 128
Cypress Developer Community ............................... 128
Technical Support ................................................... 128
Page 3 of 128
PSoC® 3: CY8C32 Family Data Sheet
1. Architectural Overview
Introducing the CY8C32 family of ultra low-power, flash Programmable System-on-Chip (PSoC®) devices, part of a scalable 8-bit
PSoC 3 and 32-bit PSoC 5 platform. The CY8C32 family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables
a high level of integration in a wide variety of consumer, industrial, and medical applications.
Figure 1-1. Simplified Block Diagram
Analog Interconnect
Quadrature Decoder
UDB
UDB
Sequencer
Usage Example for UDB
IMO
I2C
Universal Digital Block Array ( 24 x UDB)
8- Bit
Timer
UDB
UDB
16- Bit
PWM
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
22
12- Bit SPI
UDB
UDB
UDB
UDB
8- Bit
Timer
Logic
UDB
8- Bit SPI
I2C Slave
Master/
Slave
16- Bit PRS
UDB
UDB
FS USB
2.0
Logic
UDB
UDB
UDB
UART
UDB
USB
PHY
GPIOs
GPIOs
Clock Tree
32.768 KHz
( Optional)
Digital System
System Wide
Resources
Xtal
Osc
SIO
4- 25 MHz
( Optional)
GPIOs
Digital Interconnect
12- Bit PWM
RTC
Timer
System Bus
GPIOs
Memory System
EEPROM
EMIF
SRAM
CPU System
8051 or
Cortex M3
CPU
Interrupt
Controller
Program
Debug &
Trace
PHUB
DMA
FLASH
ILO
Program &
Debug
GPIOs
WDT
and
Wake
Boundary
Scan
Power Management
System
Analog System
LCD Direct
Drive
ADC
POR and
LVD
1x
Del Sig
ADC
Temperature
Sensor
DAC
SMP
CapSense
+
2x
CMP
-
GPIOs
1.71 to
5.5V
Sleep
Power
1.8V LDO
GPIOs
SIOs
Clocking System
0. 5 to 5.5V
( Optional)
Figure 1-1 illustrates the major components of the CY8C32
family. They are:
8051 CPU subsystem
Nonvolatile subsystem
Programming, debug, and test subsystem
Inputs and outputs
Clocking
Power
PSoC’s digital subsystem provides half of its unique
configurability. It connects a digital signal from any peripheral to
any pin through the Digital System Interconnect (DSI). It also
provides functional flexibility through an array of small, fast,
low-power UDBs. PSoC Creator provides a library of prebuilt and
tested standard digital peripherals (UART, SPI, LIN, PRS, CRC,
timer, counter, PWM, AND, OR, and so on) that are mapped to
the UDB array. You can also easily create a digital circuit using
boolean primitives by means of graphical design entry. Each
UDB contains programmable array logic (PAL)/programmable
logic device (PLD) functionality, together with a small state
machine engine to support a wide variety of peripherals.
Digital subsystem
Analog subsystem
Document Number: 001-56955 Rev. AB
Page 4 of 128
PSoC® 3: CY8C32 Family Data Sheet
In addition to the flexibility of the UDB array, PSoC also provides
configurable digital blocks targeted at specific functions. For the
CY8C32 family these blocks can include four 16-bit timers,
counters, and PWM blocks; I2C slave, master, and multimaster;
and FS USB.
For more details on the peripherals see the “Example
Peripherals” section on page 45 of this datasheet. For
information on UDBs, DSI, and other digital blocks, see the
“Digital Subsystem” section on page 45 of this datasheet.
PSoC’s analog subsystem is the second half of its unique
configurability. All analog performance is based on a highly
accurate absolute voltage reference with less than 1-percent
error over temperature and voltage. The configurable analog
subsystem includes:
Analog muxes
Comparators
Voltage references
ADC
DAC
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals. The heart of the analog
subsystem is a fast, accurate, configurable delta-sigma ADC
with these features:
Less than 100 µV offset
A gain error of 0.2 percent
INL less than ±1 LSB
DNL less than ±1 LSB
SINAD better than 66 dB
This converter addresses a wide variety of precision analog
applications, including some of the most demanding sensors.
A high-speed voltage or current DAC supports 8-bit output
signals at an update rate of 8 Msps in current DAC (IDAC) and
1 Msps in voltage DAC (VDAC). It can be routed out of any GPIO
pin. You can create higher resolution voltage PWM DAC outputs
using the UDB array. This can be used to create a pulse width
modulated (PWM) DAC of up to 10 bits, at up to 48 kHz. The
digital DACs in each UDB support PWM, PRS, or delta-sigma
algorithms with programmable widths.
In addition to the ADC and DAC, the analog subsystem provides
multiple comparators.
See the “Analog Subsystem” section on page 55 of this
datasheet for more details.
PSoC’s 8051 CPU subsystem is built around a single cycle
pipelined 8051 8-bit processor running at up to 50 MHz. The
CPU subsystem includes a programmable nested vector
interrupt controller, DMA controller, and RAM. PSoC’s nested
vector interrupt controller provides low latency by allowing the
CPU to vector directly to the first address of the interrupt service
routine, bypassing the jump instruction required by other
architectures. The DMA controller enables peripherals to
exchange data without CPU involvement. This allows the CPU
to run slower (saving power) or use those CPU cycles to improve
the performance of firmware algorithms. The single cycle 8051
CPU runs ten times faster than a standard 8051 processor. The
processor speed itself is configurable, allowing you to tune active
power consumption for specific applications.
PSoC’s nonvolatile subsystem consists of flash, byte-writeable
EEPROM, and nonvolatile configuration options. It provides up
to 64 KB of on-chip flash. The CPU can reprogram individual
blocks of flash, enabling bootloaders. You can enable an ECC
for high reliability applications. A powerful and flexible protection
model secures the user's sensitive information, allowing
selective memory block locking for read and write protection. Up
to 2 KB of byte-writeable EEPROM is available on-chip to store
application data. Additionally, selected configuration options
such as boot speed and pin drive mode are stored in nonvolatile
memory. This allows settings to activate immediately after POR.
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the VDDIO pins. Every GPIO
has analog I/O, LCD drive[3], CapSense, flexible interrupt
generation, slew rate control, and digital I/O capability. The SIOs
on PSoC allow Voh to be set independently of VDDIO when used
as outputs. When SIOs are in input mode they are high
impedance. This is true even when the device is not powered or
when the pin voltage goes above the supply voltage. This makes
the SIO ideally suited for use on an I2C bus where the PSoC may
not be powered when other devices on the bus are. The SIO pins
also have high current sink capability for applications such as
LED drives. The programmable input threshold feature of the
SIO can be used to make the SIO function as a general purpose
analog comparator. For devices with FS USB the USB physical
interface is also provided (USBIO). When not using USB these
pins may also be used for limited digital functionality and device
programming. All of the features of the PSoC I/Os are covered
in detail in the “I/O System and Routing” section on page 37 of
this datasheet.
The PSoC device incorporates flexible internal clock generators,
designed for high stability and factory trimmed for high accuracy.
The Internal Main Oscillator (IMO) is the clock base for the
system, and has 2-percent accuracy at 3 MHz. The IMO can be
configured to run from 3 MHz up to 24 MHz. Multiple clock
derivatives can be generated from the main clock frequency to
meet application needs. The device provides a PLL to generate
clock frequencies up to 50 MHz from the IMO, external crystal,
or external reference clock. It also contains a separate, very
low-power Internal Low-Speed Oscillator (ILO) for the sleep and
watchdog timers. A 32.768-kHz external watch crystal is also
supported for use in RTC applications. The clocks, together with
programmable clock dividers, provide the flexibility to integrate
most timing requirements.
The CY8C32 family supports a wide supply operating range from
1.71 V to 5.5 V. This allows operation from regulated supplies
such as 1.8 ± 5 percent, 2.5 V ±10 percent, 3.3 V ± 10 percent,
or 5.0 V ± 10 percent, or directly from a wide range of battery
types. In addition, it provides an integrated high efficiency
synchronous boost converter that can power the device from
supply voltages as low as 0.5 V.
Notes
3. This feature on select devices only. See Ordering Information on page 111 for details.
Document Number: 001-56955 Rev. AB
Page 5 of 128
PSoC® 3: CY8C32 Family Data Sheet
This enables the device to be powered directly from a single
battery or solar cell. In addition, you can use the boost converter
to generate other voltages required by the device, such as a
3.3-V supply for LCD glass drive. The boost’s output is available
on the VBOOST pin, allowing other devices in the application to
be powered from the PSoC.
PSoC supports a wide range of low-power modes. These include
a 200-nA hibernate mode with RAM retention and a 1-µA sleep
mode with RTC. In the second mode the optional 32.768-kHz
watch crystal runs continuously and maintains an accurate RTC.
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low-power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 1.2 mA when the CPU is running at
6 MHz, or 0.8 mA running at 3 MHz.
2. Pinouts
Each VDDIO pin powers a specific set of I/O pins. (The USBIOs
are powered from VDDD.) Using the VDDIO pins, a single PSoC
can support multiple voltage levels, reducing the need for
off-chip level shifters. The black lines drawn on the pinout
diagrams in Figure 2-3 through Figure 2-6, as well as Table 2-1,
show the pins that are powered by each VDDIO.
Each VDDIO may source up to 100 mA total to its associated I/O
pins, as shown in Figure 2-1.
Figure 2-1. VDDIO Current Limit
IDDIO X
mA
VDDIO X
I/O Pins
The details of the PSoC power modes are covered in the “Power
System” section on page 31 of this datasheet.
PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for
programming, debug, and test. The 1-wire SWV may also be
used for “printf” style debugging. By combining SWD and SWV,
you can implement a full debugging interface with just three pins.
Using these standard interfaces enables you to debug or
program the PSoC with a variety of hardware solutions from
Cypress or third party vendors. PSoC supports on-chip break
points and 4-KB instruction and data race memory for debug.
Details of the programming, test, and debugging interfaces are
discussed in the “Programming, Debug Interfaces, Resources”
section on page 62 of this datasheet.
PSoC
Conversely, for the 100-pin and 68-pin devices, the set of I/O
pins associated with any VDDIO may sink up to 100 mA total, as
shown in Figure 2-2.
Figure 2-2. I/O Pins Current Limit
Ipins
VDDIO X
mA
I/O Pins
PSoC
VSSD
For the 48-pin devices, the set of I/O pins associated with
VDDIO0 plus VDDIO2 may sink up to 100 mA total. The set of
I/O pins associated with VDDIO1 plus VDDIO3 may sink up to a
total of 100 mA.
Document Number: 001-56955 Rev. AB
Page 6 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 2-3. 48-pin SSOP Part Pinout
(SIO) P12[2]
(SIO) P12[3]
(GPIO) P0[0]
(GPIO) P0[1]
(GPIO) P0[2]
(EXTREF0, GPIO) P0[3]
VDDIO0
(GPIO) P0[4]
(GPIO) P0[5]
(IDAC0, GPIO) P0[6]
(GPIO) P0[7]
VCCD
VSSD
VDDD
(GPIO) P2[3]
(GPIO) P2[4]
VDDIO2
(GPIO) P2[5]
(GPIO) P2[6]
(GPIO) P2[7]
VSSB
IND
VBOOST
VBAT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDDA
VSSA
VCCA
P15[3] (GPIO, KHZ XTAL: XI)
P15[2] (GPIO, KHZ XTAL: XO)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
VDDIO3
P15[1] (GPIO, MHZ XTAL: XI)
P15[0] (GPIO, MHZ XTAL: XO)
VCCD
VSSD
VDDD
[4]
P15[7] (USBIO, D-, SWDCK) [4]
P15[6] (USBIO, D+, SWDIO)
P1[7] (GPIO)
P1[6] (GPIO)
VDDIO1
P1[5] (GPIO, NTRST)
P1[4] (GPIO, TDI)
P1[3] (GPIO, TDO, SWV)
P1[2] (GPIO, CONFIGURABLE XRES)
P1[1] (GPIO, TCK, SWDCK)
P1[0] (GPIO, TMS, SWDIO)
48
47
Lines show 46
VDDIO to I/O
45
supply
association 44
43
42
41
40
39
38
37
SSOP
36
35
34
33
32
31
30
29
28
27
26
25
[4]
VDDIO0
P0[4] (GPIO)
38
37
P0[6] (GPIO, IDAC0)
P0[5] (GPIO)
VCCD
P0[7] (GPIO)
41
40
39
43
42
P0[3] (EXTREF0, GPIO)
P0[2] (GPIO)
34
33
32
P0[1] (GPIO)
P0[0] (GPIO)
30
29
28
27
P12[2] (SIO)
VDDA
VSSA
VCCA
P15[3] (GPIO, KHZ XTAL: XI)
P15[2] (GPIO, KHZ XTAL: XO)
P12[1] (SIO, I2C1: SDA)
(SIO, I2C1: SCL) P12[0]
(GPIO, MHZ XTAL: XI) P15[1]
VDDIO3
(GPIO, MHZ XTAL: XO) P15[0]
17
18
19
20
21
22
23
24
26
25
P12[3] (SIO)
[4]
15
16
(GPIO) P1[7]
(USBIO, D+, SWDIO) P15[6]
(USBIO, D-, SWDCK) P15[7]
11
12
36
35
31
( TOP VIEW)
7
8
9
10
13
14
(GPIO, TDI) P1[4]
(GPIO, NTRST) P1[5]
QFN
VDDIO1
(GPIO, Configurable XRES) P1[2]
(GPIO, TDO, SWV) P1[3]
5
6
(GPIO) P1[6]
VBAT
(GPIO, TMS, SWDIO) P1[0]
(GPIO, TCK, SWDCK) P1[1]
Lines show
VDDIO to I/O
supply
association
VSSD
VCCD
3
4
IND
VBOOST
2
VDDD
VSSB
P2[3] (GPIO)
P2[4] (GPIO)
46
45
44
1
VDDD
VSSD
P2[5] (GPIO)
VDDIO2
(GPIO) P2[6]
(GPIO) P2[7]
47
48
Figure 2-4. 48-pin QFN Part Pinout[5]
Notes
4. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
5. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal. For more information, see AN72845, Design Guidelines for QFN Devices.
Document Number: 001-56955 Rev. AB
Page 7 of 128
PSoC® 3: CY8C32 Family Data Sheet
P0[5] (GPIO)
P0[4] (GPIO)
VDDIO0
53
52
P0[7] (GPIO)
P0[6] (GPIO, IDAC0)
55
54
58
57
56
P15[5] (GPOI)
P15[4] (GPIO)
VDDD
VSSD
VCCD
P2[2] (GPIO)
P2[1] (GPIO)
P2[0] (GPIO)
63
62
61
60
59
64
VDDIO2
P2[4] (GPIO)
P2[3] (GPIO)
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
Lines show VDDIO
to I/O supply
association
QFN
34
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, 12C1: SCL)
P3[7] (GPIO)
P3[6] (GPIO)
VDDIO3
(GPIO) P3[5]
(GPIO) P3[3]
(GPIO) P3[4]
31
32
33
28
29
30
(MHZ XTAL: XI, GPIO) P15[1]
(GPIO) P3[0]
(GPIO) P3[1]
(EXTREF1, GPIO) P3[2]
24
25
26
27
VSSD
VCCD
(MHZ XTAL: XO, GPIO) P15[0]
VDDD
P0[3] (GPIO, EXTREF0)
P0[2] (GPIO)
P0[1] (GPIO)
P0[0] (GPIO)
P12[3] (SIO)
P12[2] (SIO)
VSSD
VDDA
VSSA
VCCA
P15[3] (GPIO, KHZ XTAL: XI)
P15[2] (GPIO, KHZ XTAL: XO)
[7]
[7]
(GPIO) P1[7]
(SIO) P12[6]
(SIO) P12[7]
(USBIO, D+, SWDIO) P15[6]
(USBIO, D-, SWDCK) P15[7]
(GPIO) P1[6]
23
(TOP VIEW)
18
19
(TMS, SWDIO,
(TCK, SWDCK,
(Configurable XRES,
(TDO, SWV,
(TDI,
(NTRST,
XRES
GPIO) P1[0]
GPIO) P1[1]
GPIO) P1[2]
GPIO) P1[3]
GPIO) P1[4]
GPIO) P1[5]
VDDIO1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
20
21
22
(GPIO) P2[6]
(GPIO) P2[7]
(I2C0: SCL, SIO) P12[4]
(I2C0: SDA, SIO) P12[5]
VSSB
IND
VBOOST
VBAT
VSSD
66
65
68
67
P2[5] (GPIO)
Figure 2-5. 68-pin QFN Part Pinout[6]
Notes
6. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal. For more information, see AN72845, Design Guidelines for QFN Devices.
7. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-56955 Rev. AB
Page 8 of 128
PSoC® 3: CY8C32 Family Data Sheet
P0[6] (GPIO, IDAC0)
P0[5] (GPIO)
P0[4] (GPIO)
VCCA
NC
NC
NC
NC
NC
NC
P15[3] (GPIO, KHZ XTAL: XI)
P15[2] (GPIO, KHZ XTAL: XO)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
P3[7] (GPIO)
P3[6] (GPIO)
(GPIO) P3[5]
VDDIO3
47
48
49
50
(GPIO) P3[0]
(GPIO) P3[1]
(EXTREF1, GPIO) P3[2]
(GPIO) P3[3]
(GPIO) P3[4]
42
43
44
45
46
(MHZ XTAL: XO, GPIO) P15[0]
(MHZ XTAL: XI, GPIO) P15[1]
NC
NC
39
40
41
36
37
38
(USBIO, D-, SWDCK) P15[7]
VDDD
VSSD
VCCD
54
53
52
51
VDDIO0
P0[3] (GPIO,EXTREF0)
P0[2] (GPIO)
P0[1] (GPIO)
P0[0] (GPIO)
P4[1] (GPIO)
P4[0] (GPIO)
P12[3] (SIO)
P12[2] (SIO)
VSSD
VDDA
VSSA
[8]
[8]
32
33
34
35
(GPIO) P5[5]
(GPIO) P5[6]
(GPIO) P5[7]
(USBIO, D+, SWDIO) P15[6]
77
76
80
79
78
P4[5] (GPIO)
P4[4] (GPIO)
P4[3] (GPIO)
P4[2] (GPIO)
P0[7] (GPIO)
VCCD
P4[7] (GPIO)
P4[6] (GPIO)
VDDD
VSSD
87
86
85
84
83
82
81
90
89
88
P15[4] (GPIO)
P6[3] (GPIO)
P6[2] (GPIO)
P6[1] (GPIO)
P6[0] (GPIO)
P2[1] (GPIO)
P2[0] (GPIO)
P15[5] (GPIO)
95
94
93
92
91
96
P2[4] (GPIO)
P2[3] (GPIO)
P2[2] (GPIO)
98
97
28
29
30
31
TQFP
VDDIO1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
Lines show VDDIO
to I/O supply
association
26
27
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
(GPIO) P1[6]
(GPIO) P1[7]
(SIO) P12[6]
(SIO) P12[7]
(GPIO) P5[4]
(GPIO) P2[5]
(GPIO) P2[6]
(GPIO) P2[7]
(I2C0: SCL, SIO) P12[4]
(I2C0: SDA, SIO) P12[5]
(GPIO) P6[4]
(GPIO) P6[5]
(GPIO) P6[6]
(GPIO) P6[7]
VSSB
IND
VBOOST
VBAT
VSSD
XRES
(GPIO) P5[0]
(GPIO) P5[1]
(GPIO) P5[2]
(GPIO) P5[3]
(TMS, SWDIO, GPIO) P1[0]
(TCK, SWDCK, GPIO) P1[1]
(Configurable XRES, GPIO) P1[2]
(TDO, SWV, GPIO) P1[3]
(TDI, GPIO) P1[4]
(NTRST, GPIO) P1[5]
100
99
VDDIO2
Figure 2-6. 100-pin TQFP Part Pinout
Table 2-1. VDDIO and Port Pin Associations
VDDIO
Port Pins
VDDIO0
P0[7:0], P4[7:0], P12[3:2]
VDDIO1
P1[7:0], P5[7:0], P12[7:6]
VDDIO2
P2[7:0], P6[7:0], P12[5:4], P15[5:4]
VDDIO3
P3[7:0], P12[1:0], P15[3:0]
VDDD
P15[7:6] (USB D+, D-)
Note
8. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-56955 Rev. AB
Page 9 of 128
PSoC® 3: CY8C32 Family Data Sheet
Table 2-2 shows the pinout for the 72-pin CSP package. Since there are four VDDIO pins, the set of I/O pins associated with any VDDIO
may sink up to 100 mA total, same as for the 100-pin and 68-pin devices.
Table 2-2. CSP Pinout
Ball
Name
Ball
Name
Ball
Name
G6
E5
P2[5]
F1
VDDD
A5
VDDA
P2[6]
E1
VSSD
A6
VSSD
F5
P2[7]
E2
VCCD
B6
P12[2]
J7
P12[4]
C1
P15[0]
C6
P12[3]
H6
P12[5]
C2
P15[1]
A7
P0[0]
J6
VSSB
D2
P3[0]
B7
P0[1]
J5
Ind
D3
P3[1]
B5
P0[2]
H5
VBOOST
D4
P3[2]
C5
P0[3]
J4
VBAT
D5
P3[3]
A8
VIO0
H4
VSSD
B4
P3[4]
D6
P0[4]
J3
XRES_N
B3
P3[5]
D7
P0[5]
H3
P1[0]
A1
VIO3
C7
P0[6]
G3
P1[1]
B2
P3[6]
C8
P0[7]
H2
P1[2]
A2
P3[7]
E8
VCCD
J2
P1[3]
C3
P12[0]
F8
VSSD
G4
P1[4]
C4
P12[1]
G8
VDDD
G5
P1[5]
E3
P15[2]
E7
P15[4]
J1
VIO1
E4
P15[3]
F7
P15[5]
F4
P1[6]
B1[9]
NC
G7
P2[0]
P1[7]
[9]
NC
H7
P2[1]
[9]
F3
B8
H1
P12[6]
D1
NC
H8
P2[2]
G1
P12[7]
D8[9]
NC
F6
P2[3]
G2
P15[6]
A3
VCCA
E6
P2[4]
F2
P15[7]
A4
VSSA
J8
VIO2
Figure 2-7 and Figure 2-8 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog
performance on a two layer board.
The two pins labeled VDDD must be connected together.
The two pins labeled VCCD must be connected together, with capacitance added, as shown in Figure 2-7 and Power System on
page 31. The trace between the two VCCD pins should be as short as possible.
The two pins labeled VSSD must be connected together.
For information on circuit board layout issues for mixed signals, refer to the application note AN57821 - Mixed Signal Circuit Board
Layout Considerations for PSoC® 3 and PSoC 5.
Note
9. These pins are Do Not Use (DNU); they must be left floating.
Document Number: 001-56955 Rev. AB
Page 10 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 2-7. Example Schematic for 100-pin TQFP Part with Power Connections
VDDD
C1
1uF
VDDD
VSSD
VSSD
VDDD
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDA
C8
0.1uF
C17
1uF
VSSD
VSSA
VSSD
VDDA
VSSA
VCCA
VDDA
C9
1uF
C10
0.1uF
VSSA
VDDD
C11
0.1uF
VCCD
VDDD
VSSD
C12
0.1uF
VSSD
VDDD
VDDIO0
OA0-, REF0, P0[3]
OA0+, P0[2]
OA0OUT, P0[1]
OA2OUT, P0[0]
P4[1]
P4[0]
SIO, P12[3]
SIO, P12[2]
VSSD
VDDA
VSSA
VCCA
NC
NC
NC
NC
NC
NC
KHZXIN, P15[3]
KHZXOUT, P15[2]
SIO, P12[1]
SIO, P12[0]
OA3OUT, P3[7]
OA1OUT, P3[6]
VDDIO1
P1[6]
P1[7]
P12[6], SIO
P12[7], SIO
P5[4]
P5[5]
P5[6]
P5[7]
P15[6], USB D+
P15[7], USB DVDDD
VSSD
VCCD
NC
NC
P15[0], MHZXOUT
P15[1], MHZXIN
P3[0], IDAC1
P3[1], IDAC3
P3[2], OA3-, REF1
P3[3], OA3+
P3[4], OA1P3[5], OA1+
VDDIO3
P2[5]
P2[6]
P2[7]
P12[4], SIO
P12[5], SIO
P6[4]
P6[5]
P6[6]
P6[7]
VSSB
IND
VBOOST
VBAT
VSSD
XRES
P5[0]
P5[1]
P5[2]
P5[3]
P1[0], SWIO, TMS
P1[1], SWDIO, TCK
P1[2]
P1[3], SWV, TDO
P1[4], TDI
P1[5], NTRST
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSSD
VCCD
VSSD
VDDIO2
P2[4]
P2[3]
P2[2]
P2[1]
P2[0]
P15[5]
P15[4]
P6[3]
P6[2]
P6[1]
P6[0]
VDDD
VSSD
VCCD
P4[7]
P4[6]
P4[5]
P4[4]
P4[3]
P4[2]
IDAC2, P0[7]
IDAC0, P0[6]
OA2-, P0[5]
OA2+, P0[4]
VSSD
VSSD
C2
0.1uF
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
C6
0.1uF
VDDD
VDDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDDD
C15
1uF
C16
0.1uF
VSSD
VSSD
Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended,
as shown in Figure 2-8 on page 12.
For more information on pad layout, refer to http://www.cypress.com/cad-resources/psoc-3-cad-libraries.
Document Number: 001-56955 Rev. AB
Page 11 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 2-8. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance
VSSA
VDDD
VSSD
VDDA
VSSA
Plane
VSSD
Plane
3. Pin Descriptions
nTRST
IDAC0
Optional JTAG test reset programming and debug port
connection to reset the JTAG connection.
Low resistance output pin for high current DAC (IDAC).
SIO
Extref0, Extref1
Special I/O provides interfaces to the CPU, digital peripherals
and interrupts with a programmable high threshold voltage,
analog comparator, high sink current, and high impedance state
when the device is unpowered.
External reference input to the analog system.
GPIO
General purpose I/O pin provides interfaces to the CPU, digital
peripherals, analog peripherals, interrupts, LCD segment drive,
and CapSense.
I2C0: SCL, I2C1: SCL
SWDCK
Serial wire debug clock programming and debug port
connection.
I2C SCL line providing wake from sleep on an address match.
Any I/O pin can be used for I2C SCL if wake from sleep is not
required.
SWDIO
I2C0: SDA, I2C1: SDA
SWV.
2C
I SDA line providing wake from sleep on an address match.
Any I/O pin can be used for I2C SDA if wake from sleep is not
required.
Ind
Inductor connection to boost pump.
kHz XTAL: Xo, kHz XTAL: Xi
32.768-kHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi
4- to 25- MHz crystal oscillator pin.
Document Number: 001-56955 Rev. AB
Serial wire debug input and output programming and debug port
connection.
Single wire viewer debug output.
TCK
JTAG test clock programming and debug port connection.
TDI
JTAG test data in programming and debug port connection.
TDO
JTAG test data out programming and debug port connection.
TMS
JTAG test mode select programming and debug port connection.
Page 12 of 128
PSoC® 3: CY8C32 Family Data Sheet
USBIO, D+
XRES (and configurable XRES)
Provides D+ connection directly to a USB 2.0 bus. May be used
as a digital I/O pin. Pins are Do Not Use (DNU) on devices
without USB.
External reset pin. Active low with internal pull-up. Pin P1[2] may
be configured to be a XRES pin; see “Nonvolatile Latches
(NVLs)” on page 25.
USBIO, D–
Provides D– connection directly to a USB 2.0 bus. May be used
as a digital I/O pin. Pins are No Connect (NC) on devices without
USB.
VBOOST
Power sense connection to boost pump.
VBAT
Battery supply to boost pump.
VCCA.
Output of the analog core regulator or the input to the
analog core. Requires a 1uF capacitor to VSSA. The regulator
output is not designed to drive external circuits. Note that if you
use the device with an external core regulator (externally
regulated mode), the voltage applied to this pin must not
exceed the allowable range of 1.71 V to 1.89 V. When using
the internal core regulator, (internally regulated mode, the
default), do not tie any power to this pin. For details see Power
System on page 31.
VCCD.
Output of the digital core regulator or the input to the digital
core. The two VCCD pins must be shorted together, with the
trace between them as short as possible, and a 1uF capacitor to
VSSD. The regulator output is not designed to drive external
circuits. Note that if you use the device with an external core
regulator (externally regulated mode), the voltage applied to
this pin must not exceed the allowable range of 1.71 V to
1.89 V. When using the internal core regulator (internally
regulated mode, the default), do not tie any power to this pin. For
details see Power System on page 31.
VDDA
Supply for all analog peripherals and analog core regulator.
VDDA must be the highest voltage present on the device. All
other supply pins must be less than or equal to VDDA.
VDDD
Supply for all digital peripherals and digital core regulator. VDDD
must be less than or equal to VDDA.
VSSA
Ground for all analog peripherals.
VSSB
Ground connection for boost pump.
VSSD
Ground for all digital logic and I/O pins.
VDDIO0, VDDIO1, VDDIO2, VDDIO3
Supply for I/O pins. See pinouts for specific I/O pin to VDDIO
mapping. Each VDDIO must be tied to a valid operating voltage
(1.71 V to 5.5 V), and must be less than or equal to VDDA.
Document Number: 001-56955 Rev. AB
4. CPU
4.1 8051 CPU
The CY8C32 devices use a single cycle 8051 CPU, which is fully
compatible with the original MCS-51 instruction set. The
CY8C32 family uses a pipelined RISC architecture, which
executes most instructions in 1 to 2 cycles to provide peak
performance of up to 24 MIPS with an average of 2 cycles per
instruction. The single cycle 8051 CPU runs ten times faster than
a standard 8051 processor.
The 8051 CPU subsystem includes these features:
Single cycle 8051 CPU
Up to 64 KB of flash memory, up to 2 KB of EEPROM, and up
to 8 KB of SRAM
512-byte instruction cache between CPU and flash
Programmable nested vector interrupt controller
Direct memory access (DMA) controller
Peripheral HUB (PHUB)
External memory interface (EMIF)
4.2 Addressing Modes
The following addressing modes are supported by the 8051:
Direct Addressing: The operand is specified by a direct 8-bit
address field. Only the internal RAM and the SFRs can be
accessed using this mode.
Indirect Addressing: The instruction specifies the register which
contains the address of the operand. The registers R0 or R1
are used to specify the 8-bit address, while the data pointer
(DPTR) register is used to specify the 16-bit address.
Register Addressing: Certain instructions access one of the
registers (R0 to R7) in the specified register bank. These
instructions are more efficient because there is no need for an
address field.
Register Specific Instructions: Some instructions are specific
to certain registers. For example, some instructions always act
on the accumulator. In this case, there is no need to specify the
operand.
Immediate Constants: Some instructions carry the value of the
constants directly instead of an address.
Indexed Addressing: This type of addressing can be used only
for a read of the program memory. This mode uses the data
pointer as the base and the accumulator value as an offset to
read a program memory.
Bit Addressing: In this mode, the operand is one of 256 bits.
Page 13 of 128
PSoC® 3: CY8C32 Family Data Sheet
4.3 Instruction Set
4.3.1 Instruction Set Summary
The 8051 instruction set is highly optimized for 8-bit handling and
Boolean operations. The types of instructions supported include:
4.3.1.1 Arithmetic Instructions
Arithmetic instructions
Logical instructions
Data transfer instructions
Arithmetic instructions support the direct, indirect, register,
immediate constant, and register-specific instructions.
Arithmetic modes are used for addition, subtraction,
multiplication, division, increment, and decrement operations.
Table 4-1 lists the different arithmetic instructions.
Boolean instructions
Program branching instructions
Table 4-1. Arithmetic Instructions
Mnemonic
Description
Bytes
Cycles
1
1
ADD
A,Rn
Add register to accumulator
ADD
A,Direct
Add direct byte to accumulator
2
2
ADD
A,@Ri
Add indirect RAM to accumulator
1
2
ADD
A,#data
Add immediate data to accumulator
2
2
ADDC A,Rn
Add register to accumulator with carry
1
1
ADDC A,Direct
Add direct byte to accumulator with carry
2
2
ADDC A,@Ri
Add indirect RAM to accumulator with carry
1
2
ADDC A,#data
Add immediate data to accumulator with carry
2
2
SUBB A,Rn
Subtract register from accumulator with borrow
1
1
SUBB A,Direct
Subtract direct byte from accumulator with borrow
2
2
SUBB A,@Ri
Subtract indirect RAM from accumulator with borrow
1
2
SUBB A,#data
Subtract immediate data from accumulator with borrow
2
2
INC
A
Increment accumulator
1
1
INC
Rn
Increment register
1
2
INC
Direct
Increment direct byte
2
3
INC
@Ri
Increment indirect RAM
1
3
DEC
A
Decrement accumulator
1
1
DEC
Rn
Decrement register
1
2
DEC
Direct
Decrement direct byte
2
3
DEC
@Ri
Decrement indirect RAM
1
3
INC
DPTR
Increment data pointer
1
1
MUL
Multiply accumulator and B
1
2
DIV
Divide accumulator by B
1
6
DAA
Decimal adjust accumulator
1
3
Document Number: 001-56955 Rev. AB
Page 14 of 128
PSoC® 3: CY8C32 Family Data Sheet
4.3.1.2 Logical Instructions
The logical instructions perform Boolean operations such as AND, OR, XOR on bytes, rotate of accumulator contents, and swap of
nibbles in an accumulator. The Boolean operations on the bytes are performed on the bit-by-bit basis. Table 4-2Table 4-2 on page 15
shows the list of logical instructions and their description.
Table 4-2. Logical Instructions
Bytes
Cycles
ANL
A,Rn
Mnemonic
AND register to accumulator
Description
1
1
ANL
A,Direct
AND direct byte to accumulator
2
2
ANL
A,@Ri
AND indirect RAM to accumulator
1
2
ANL
A,#data
AND immediate data to accumulator
2
2
ANL
Direct, A
AND accumulator to direct byte
2
3
ANL
Direct, #data
AND immediate data to direct byte
3
3
ORL
A,Rn
OR register to accumulator
1
1
ORL
A,Direct
OR direct byte to accumulator
2
2
ORL
A,@Ri
OR indirect RAM to accumulator
1
2
ORL
A,#data
OR immediate data to accumulator
2
2
ORL
Direct, A
OR accumulator to direct byte
2
3
ORL
Direct, #data
OR immediate data to direct byte
3
3
XRL
A,Rn
XOR register to accumulator
1
1
XRL
A,Direct
XOR direct byte to accumulator
2
2
XRL
A,@Ri
XOR indirect RAM to accumulator
1
2
XRL
A,#data
XOR immediate data to accumulator
2
2
XRL
Direct, A
XOR accumulator to direct byte
2
3
XRL
Direct, #data
XOR immediate data to direct byte
3
3
CLR
A
Clear accumulator
1
1
CPL
A
Complement accumulator
1
1
RL
A
Rotate accumulator left
1
1
RLC
A
Rotate accumulator left through carry
1
1
RR
A
Rotate accumulator right
1
1
RRC A
Rotate accumulator right though carry
1
1
SWAP A
Swap nibbles within accumulator
1
1
Document Number: 001-56955 Rev. AB
Page 15 of 128
PSoC® 3: CY8C32 Family Data Sheet
4.3.1.3 Data Transfer Instructions
The data transfer instructions are of three types: the core RAM,
xdata RAM, and the lookup tables. The core RAM transfer
includes transfer between any two core RAM locations or SFRs.
These instructions can use direct, indirect, register, and
immediate addressing. The xdata RAM transfer includes only the
transfer between the accumulator and the xdata RAM location.
It can use only indirect addressing. The lookup tables involve
nothing but the read of program memory using the Indexed
addressing mode. Table 4-3 lists the various data transfer
instructions available.
4.3.1.4 Boolean Instructions
The 8051 core has a separate bit-addressable memory location.
It has 128 bits of bit addressable RAM and a set of SFRs that are
bit addressable. The instruction set includes the whole menu of
bit operations such as move, set, clear, toggle, OR, and AND
instructions and the conditional jump instructions. Table 4-4 on
page 17Table 4-4 lists the available Boolean instructions.
Table 4-3. Data Transfer Instructions
Bytes
Cycles
MOV
A,Rn
Mnemonic
Move register to accumulator
Description
1
1
MOV
A,Direct
Move direct byte to accumulator
2
2
MOV
A,@Ri
Move indirect RAM to accumulator
1
2
MOV
A,#data
Move immediate data to accumulator
2
2
MOV
Rn,A
Move accumulator to register
1
1
MOV
Rn,Direct
Move direct byte to register
2
3
MOV
Rn, #data
Move immediate data to register
2
2
MOV
Direct, A
Move accumulator to direct byte
2
2
MOV
Direct, Rn
Move register to direct byte
2
2
MOV
Direct, Direct
Move direct byte to direct byte
3
3
MOV
Direct, @Ri
Move indirect RAM to direct byte
2
3
MOV
Direct, #data
Move immediate data to direct byte
3
3
MOV
@Ri, A
Move accumulator to indirect RAM
1
2
MOV
@Ri, Direct
Move direct byte to indirect RAM
2
3
MOV
@Ri, #data
Move immediate data to indirect RAM
2
2
MOV
DPTR, #data16
Load data pointer with 16-bit constant
3
3
MOVC A, @A+DPTR
Move code byte relative to DPTR to accumulator
1
5
MOVC A, @A + PC
Move code byte relative to PC to accumulator
1
4
MOVX A,@Ri
Move external RAM (8-bit) to accumulator
1
4
MOVX A, @DPTR
Move external RAM (16-bit) to accumulator
1
3
MOVX @Ri, A
Move accumulator to external RAM (8-bit)
1
5
MOVX @DPTR, A
Move accumulator to external RAM (16-bit)
1
4
PUSH Direct
Push direct byte onto stack
2
3
POP
Direct
Pop direct byte from stack
2
2
XCH
A, Rn
Exchange register with accumulator
1
2
XCH
A, Direct
Exchange direct byte with accumulator
2
3
XCH
A, @Ri
Exchange indirect RAM with accumulator
1
3
Exchange low order indirect digit RAM with accumulator
1
3
XCHD A, @Ri
Document Number: 001-56955 Rev. AB
Page 16 of 128
PSoC® 3: CY8C32 Family Data Sheet
Table 4-4. Boolean Instructions
Mnemonic
Description
Bytes
Cycles
CLR
C
Clear carry
1
1
CLR
bit
Clear direct bit
2
3
SETB C
Set carry
1
1
SETB bit
Set direct bit
2
3
CPL
C
Complement carry
1
1
CPL
bit
Complement direct bit
2
3
ANL
C, bit
AND direct bit to carry
2
2
ANL
C, /bit
AND complement of direct bit to carry
2
2
ORL C, bit
OR direct bit to carry
2
2
ORL C, /bit
OR complement of direct bit to carry
2
2
MOV C, bit
Move direct bit to carry
2
2
MOV bit, C
Move carry to direct bit
2
3
JC
Jump if carry is set
2
3
Jump if no carry is set
2
3
rel
JNC rel
JB
Jump if direct bit is set
3
5
JNB bit, rel
bit, rel
Jump if direct bit is not set
3
5
JBC bit, rel
Jump if direct bit is set and clear bit
3
5
Document Number: 001-56955 Rev. AB
Page 17 of 128
PSoC® 3: CY8C32 Family Data Sheet
4.3.1.5 Program Branching Instructions
The 8051 supports a set of conditional and unconditional jump instructions that help to modify the program execution flow. Table 4-5
shows the list of jump instructions.
Table 4-5. Jump Instructions
Mnemonic
ACALL addr11
LCALL addr16
RET
RETI
AJMP addr11
LJMP addr16
SJMP rel
JMP @A + DPTR
JZ rel
JNZ rel
CJNE A,Direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE @Ri, #data, rel
DJNZ Rn,rel
DJNZ Direct, rel
NOP
Description
Absolute subroutine call
Long subroutine call
Return from subroutine
Return from interrupt
Absolute jump
Long jump
Short jump (relative address)
Jump indirect relative to DPTR
Jump if accumulator is zero
Jump if accumulator is nonzero
Compare direct byte to accumulator and jump if not equal
Compare immediate data to accumulator and jump if not equal
Compare immediate data to register and jump if not equal
Compare immediate data to indirect RAM and jump if not equal
Decrement register and jump if not zero
Decrement direct byte and jump if not zero
No operation
4.4 DMA and PHUB
The PHUB and the DMA controller are responsible for data
transfer between the CPU and peripherals, and also data
transfers between peripherals. The PHUB and DMA also control
device configuration during boot. The PHUB consists of:
A central hub that includes the DMA controller, arbiter, and
router
Multiple spokes that radiate outward from the hub to most
peripherals
There are two PHUB masters: the CPU and the DMA controller.
Both masters may initiate transactions on the bus. The DMA
channels can handle peripheral communication without CPU
intervention. The arbiter in the central hub determines which
DMA channel is the highest priority if there are multiple requests.
4.4.1 PHUB Features
CPU and DMA controller are both bus masters to the PHUB
Eight Multi-layer AHB Bus parallel access paths (spokes) for
peripheral access
Document Number: 001-56955 Rev. AB
Bytes
2
3
1
1
2
3
2
1
2
2
3
3
3
3
2
3
1
Cycles
4
4
4
4
3
4
3
5
4
4
5
4
4
5
4
5
1
Simultaneous CPU and DMA access to peripherals located on
different spokes
Simultaneous DMA source and destination burst transactions
on different spokes
Supports 8, 16, 24, and 32-bit addressing and data
Table 4-6. PHUB Spokes and Peripherals
PHUB Spokes
Peripherals
0
SRAM
1
IOs, PICU, EMIF
2
PHUB local configuration, Power manager,
Clocks, IC, SWV, EEPROM, Flash
programming interface
3
Analog interface and trim, Decimator
4
USB, USB, I2C, Timers, Counters, and PWMs
5
Reserved
6
UDBs group 1
7
UDBs group 2
Page 18 of 128
PSoC® 3: CY8C32 Family Data Sheet
4.4.2 DMA Features
Table 4-7. Priority Levels
24 DMA channels
Priority Level
% Bus Bandwidth
0
100.0
1
100.0
TDs can be dynamically updated
2
50.0
Eight levels of priority per channel
3
25.0
Any digitally routable signal, the CPU, or another DMA channel,
4
12.5
5
6.2
Each channel can generate up to two interrupts per transfer
6
3.1
Transactions can be stalled or canceled
7
1.5
Each channel has one or more transaction descriptors (TDs)
to configure channel behavior. Up to 128 total TDs can be
defined
can trigger a transaction
Supports transaction size of infinite or 1 to 64k bytes
TDs may be nested and/or chained for complex transactions
4.4.3 Priority Levels
The CPU always has higher priority than the DMA controller
when their accesses require the same bus resources. Due to the
system architecture, the CPU can never starve the DMA. DMA
channels of higher priority (lower priority number) may interrupt
current DMA transfers. In the case of an interrupt, the current
transfer is allowed to complete its current transaction. To ensure
latency limits when multiple DMA accesses are requested
simultaneously, a fairness algorithm guarantees an interleaved
minimum percentage of bus bandwidth for priority levels 2
through 7. Priority levels 0 and 1 do not take part in the fairness
algorithm and may use 100 percent of the bus bandwidth. If a tie
occurs on two DMA requests of the same priority level, a simple
round robin method is used to evenly share the allocated
bandwidth. The round robin allocation can be disabled for each
DMA channel, allowing it to always be at the head of the line.
Priority levels 2 to 7 are guaranteed the minimum bus bandwidth
shown in Table 4-7 after the CPU and DMA priority levels 0 and
1 have satisfied their requirements.
When the fairness algorithm is disabled, DMA access is granted
based solely on the priority level; no bus bandwidth guarantees
are made.
4.4.4 Transaction Modes Supported
The flexible configuration of each DMA channel and the ability to
chain multiple channels allow the creation of both simple and
complex use cases. General use cases include, but are not
limited to:
4.4.4.1 Simple DMA
In a simple DMA case, a single TD transfers data between a
source and sink (peripherals or memory location). The basic
timing diagrams of DMA read and write cycles are shown in
Figure 4-1. For more description on other transfer modes, refer
to the Technical Reference Manual.
Figure 4-1. DMA Timing Diagram
ADDRESS Phase
DATA Phase
ADDRESS Phase
CLK
DATA Phase
CLK
ADDR 16/32
A
ADDR 16/32
B
WRITE
A
B
WRITE
DATA (A)
DATA
READY
DATA (A)
DATA
READY
Basic DMA Read Transfer without wait states
4.4.4.2 Auto Repeat DMA
Auto repeat DMA is typically used when a static pattern is
repetitively read from system memory and written to a peripheral.
This is done with a single TD that chains to itself.
4.4.4.3 Ping Pong DMA
A ping pong DMA case uses double buffering to allow one buffer
to be filled by one client while another client is consuming the
Document Number: 001-56955 Rev. AB
Basic DMA Write Transfer without wait states
data previously received in the other buffer. In its simplest form,
this is done by chaining two TDs together so that each TD calls
the opposite TD when complete.
4.4.4.4 Circular DMA
Circular DMA is similar to ping pong DMA except it contains more
than two buffers. In this case there are multiple TDs; after the last
TD is complete it chains back to the first TD.
Page 19 of 128
PSoC® 3: CY8C32 Family Data Sheet
4.4.4.5 Scatter Gather DMA
4.5 Interrupt Controller
In the case of scatter gather DMA, there are multiple
noncontiguous sources or destinations that are required to
effectively carry out an overall DMA transaction. For example, a
packet may need to be transmitted off of the device and the
packet elements, including the header, payload, and trailer, exist
in various noncontiguous locations in memory. Scatter gather
DMA allows the segments to be concatenated together by using
multiple TDs in a chain. The chain gathers the data from the
multiple locations. A similar concept applies for the reception of
data onto the device. Certain parts of the received data may need
to be scattered to various locations in memory for software
processing convenience. Each TD in the chain specifies the
location for each discrete element in the chain.
The interrupt controller provides a mechanism for hardware
resources to change program execution to a new address,
independent of the current task being executed by the main
code. The interrupt controller provides enhanced features not
found on original 8051 interrupt controllers:
4.4.4.6 Packet Queuing DMA
Packet queuing DMA is similar to scatter gather DMA but
specifically refers to packet protocols. With these protocols,
there may be separate configuration, data, and status phases
associated with sending or receiving a packet.
For instance, to transmit a packet, a memory mapped
configuration register can be written inside a peripheral,
specifying the overall length of the ensuing data phase. The CPU
can set up this configuration information anywhere in system
memory and copy it with a simple TD to the peripheral. After the
configuration phase, a data phase TD (or a series of data phase
TDs) can begin (potentially using scatter gather). When the data
phase TD(s) finish, a status phase TD can be invoked that reads
some memory mapped status information from the peripheral
and copies it to a location in system memory specified by the
CPU for later inspection. Multiple sets of configuration, data, and
status phase “subchains” can be strung together to create larger
chains that transmit multiple packets in this way. A similar
concept exists in the opposite direction to receive the packets.
4.4.4.7 Nested DMA
One TD may modify another TD, as the TD configuration space
is memory mapped similar to any other peripheral. For example,
a first TD loads a second TD’s configuration and then calls the
second TD. The second TD moves data as required by the
application. When complete, the second TD calls the first TD,
which again updates the second TD’s configuration. This
process repeats as often as necessary.
Thirty two interrupt vectors
Jumps directly to ISR anywhere in code space with dynamic
vector addresses
Multiple sources for each vector
Flexible interrupt to vector matching
Each interrupt vector is independently enabled or disabled
Each interrupt can be dynamically assigned one of eight
priorities
Eight level nestable interrupts
Multiple I/O interrupt vectors
Software can send interrupts
Software can clear pending interrupts
When an interrupt is pending, the current instruction is
completed and the program counter is pushed onto the stack.
Code execution then jumps to the program address provided by
the vector. After the ISR is completed, a RETI instruction is
executed and returns execution to the instruction following the
previously interrupted instruction. To do this the RETI instruction
pops the program counter from the stack.
If the same priority level is assigned to two or more interrupts,
the interrupt with the lower vector number is executed first. Each
interrupt vector may choose from three interrupt sources: Fixed
Function, DMA, and UDB. The fixed function interrupts are direct
connections to the most common interrupt sources and provide
the lowest resource cost connection. The DMA interrupt sources
provide direct connections to the two DMA interrupt sources
provided per DMA channel. The third interrupt source for vectors
is from the UDB digital routing array. This allows any digital signal
available to the UDB array to be used as an interrupt source.
Fixed function interrupts and all interrupt sources may be routed
to any interrupt vector using the UDB interrupt source
connections.
Figure 4-2 on page 21 represents typical flow of events when an
interrupt triggered. Figure 4-3 on page 22 shows the interrupt
structure and priority polling.
Document Number: 001-56955 Rev. AB
Page 20 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 4-2. Interrupt Processing Timing Diagram
1
2
3
4
5
6
7
8
9
10
11
S
CLK
Arrival of new Interrupt
INT_INPUT
S
Pend bit is set on next clock active edge
POST and PEND bits cleared after IRQ is sleared
PEND
S
Interrupt is posted to ascertain the priority
POST
S
IRQ cleared after receiving IRA
Interrupt request sent to core for processing
IRQ
ACTIVE_INT_NUM
(#10)
NA
NA
INT_VECT_ADDR
0x0010
S
S
The active interrupt
number is posted to core
The active interrupt ISR
address is posted to core
0x0000
S
S
NA
S
IRA
S
IRC
Interrupt generation and posting to CPU
CPU Response
Int. State
Clear
S
Completing current instruction and branching to vector address
Complete ISR and return
TIME
Notes
1: Interrupt triggered asynchronous to the clock
2: The PEND bit is set on next active clock edge to indicate the interrupt arrival
3: POST bit is set following the PEND bit
4: Interrupt request and the interrupt number sent to CPU core after evaluation priority (Takes 3 clocks)
5: ISR address is posted to CPU core for branching
6: CPU acknowledges the interrupt request
7: ISR address is read by CPU for branching
8, 9: PEND and POST bits are cleared respectively after receiving the IRA from core
10: IRA bit is cleared after completing the current instruction and starting the instruction execution from ISR location (Takes 7 cycles)
11: IRC is set to indicate the completion of ISR, Active int. status is restored with previous status
The total interrupt latency (ISR execution)
= POST + PEND + IRQ + IRA + Completing current instruction and branching
= 1+1+1+2+7 cycles
= 12 cycles
Document Number: 001-56955 Rev. AB
Page 21 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 4-3. Interrupt Structure
Interrupt Polling logic
Interrupts form Fixed
function blocks, DMA and
UDBs
Highest Priority
Interrupt Enable/
Disable, PEND and
POST logic
Interrupts 0 to 31
from UDBs
0
Interrupts 0 to 31
from Fixed
Function Blocks
1
IRQ
8 Level
Priority
decoder
for all
interrupts
Polling sequence
Interrupt
routing logic
to select 32
sources
Interrupt 2 to 30
Interrupts 0 to
31 from DMA
Individual
Enable Disable
bits
0 to 31
ACTIVE_INT_NUM
[15:0]
INT_VECT_ADDR
IRA
IRC
31
Global Enable
disable bit
Document Number: 001-56955 Rev. AB
Lowest Priority
Page 22 of 128
PSoC® 3: CY8C32 Family Data Sheet
Table 4-8. Interrupt Vector Table
#
Fixed Function
DMA
phub_termout0[0]
UDB
0
LVD
udb_intr[0]
1
Cache/ECC
phub_termout0[1]
udb_intr[1]
2
Reserved
phub_termout0[2]
udb_intr[2]
3
Sleep (Pwr Mgr)
phub_termout0[3]
udb_intr[3]
4
PICU[0]
phub_termout0[4]
udb_intr[4]
5
PICU[1]
phub_termout0[5]
udb_intr[5]
6
PICU[2]
phub_termout0[6]
udb_intr[6]
7
PICU[3]
phub_termout0[7]
udb_intr[7]
8
PICU[4]
phub_termout0[8]
udb_intr[8]
9
PICU[5]
phub_termout0[9]
udb_intr[9]
10
PICU[6]
phub_termout0[10] udb_intr[10]
11
PICU[12]
phub_termout0[11] udb_intr[11]
12
PICU[15]
phub_termout0[12] udb_intr[12]
13
Comparators
Combined
phub_termout0[13] udb_intr[13]
14
Reserved
phub_termout0[14] udb_intr[14]
15
I2C
phub_termout0[15] udb_intr[15]
16
Reserved
phub_termout1[0]
udb_intr[16]
17
Timer/Counter0
phub_termout1[1]
udb_intr[17]
18
Timer/Counter1
phub_termout1[2]
udb_intr[18]
19
Timer/Counter2
phub_termout1[3]
udb_intr[19]
20
Timer/Counter3
phub_termout1[4]
udb_intr[20]
21
USB SOF Int
phub_termout1[5]
udb_intr[21]
22
USB Arb Int
phub_termout1[6]
udb_intr[22]
23
USB Bus Int
phub_termout1[7]
udb_intr[23]
24
USB Endpoint[0]
phub_termout1[8]
udb_intr[24]
25
USB Endpoint Data phub_termout1[9]
udb_intr[25]
26
Reserved
phub_termout1[10] udb_intr[26]
27
LCD
phub_termout1[11] udb_intr[27]
28
Reserved
phub_termout1[12] udb_intr[28]
29
Decimator Int
phub_termout1[13] udb_intr[29]
30
PHUB Error Int
phub_termout1[14] udb_intr[30]
31
EEPROM Fault Int
phub_termout1[15] udb_intr[31]
Document Number: 001-56955 Rev. AB
Page 23 of 128
PSoC® 3: CY8C32 Family Data Sheet
5. Memory
5.1 Static RAM
CY8C32 Static RAM (SRAM) is used for temporary data storage.
Up to 8 KB of SRAM is provided and can be accessed by the
8051 or the DMA controller. See Memory Map on page 26.
Simultaneous access of SRAM by the 8051 and the DMA
controller is possible if different 4-KB blocks are accessed.
5.2 Flash Program Memory
Flash memory in PSoC devices provides nonvolatile storage for
user firmware, user configuration data, bulk data storage, and
optional ECC data. The main flash memory area contains up to
64 KB of user program space.
Up to an additional 8 KB of flash space is available for Error
Correcting Codes (ECC). If ECC is not used this space can store
device configuration data and bulk user data. User code may not
be run out of the ECC flash memory section. ECC can correct
one bit error and detect two bit errors per 8 bytes of firmware
memory; an interrupt can be generated when an error is
detected.
The CPU reads instructions located in flash through a cache
controller. This improves instruction execution rate and reduces
system power consumption by requiring less frequent flash
access. The cache has 8 lines at 64 bytes per line for a total of
512 bytes. It is fully associative, automatically controls flash
power, and can be enabled or disabled. If ECC is enabled, the
cache controller also performs error checking and correction,
and interrupt generation.
Flash programming is performed through a special interface and
preempts code execution out of flash. The flash programming
interface performs flash erasing, programming and setting code
protection levels. Flash in-system serial programming (ISSP),
typically used for production programming, is possible through
both the SWD and JTAG interfaces. In-system programming,
typically used for bootloaders, is also possible using serial
interfaces such as I2C, USB, UART, and SPI, or any
communications protocol.
5.3 Flash Security
All PSoC devices include a flexible flash-protection model that
prevents access and visibility to on-chip flash memory. This
prevents duplication or reverse engineering of proprietary code.
Flash memory is organized in blocks, where each block contains
256 bytes of program or data and 32 bytes of ECC or
configuration data. A total of up to 256 blocks is provided on
64-KB flash devices.
The device offers the ability to assign one of four protection
levels to each row of flash. Table 5-1 lists the protection modes
available. Flash protection levels can only be changed by
performing a complete flash erase. The Full Protection and Field
Upgrade settings disable external access (through a debugging
tool such as PSoC Creator, for example). If your application
requires code update through a boot loader, then use the Field
Upgrade setting. Use the Unprotected setting only when no
security is needed in your application. The PSoC device also
offers an advanced security feature called Device Security which
permanently disables all test, programming, and debug ports,
Document Number: 001-56955 Rev. AB
protecting your application from external access (see the
“Device Security” section on page 65). For more information
about how to take full advantage of the security features in
PSoC, see the PSoC 3 TRM.
Table 5-1. Flash Protection
Protection
Setting
Allowed
Not Allowed
Unprotected
External read and write –
+ internal read and write
Factory
Upgrade
External write + internal
read and write
External read
Field Upgrade Internal read and write
External read and
write
Full Protection Internal read
External read and
write + internal write
Disclaimer
Note the following details of the flash code protection features on
Cypress devices.
Cypress products meet the specifications contained in their
particular Cypress datasheets. Cypress believes that its family of
products is one of the most secure families of its kind on the
market today, regardless of how they are used. There may be
methods, unknown to Cypress, that can breach the code
protection features. Any of these methods, to our knowledge,
would be dishonest and possibly illegal. Neither Cypress nor any
other semiconductor manufacturer can guarantee the security of
their code. Code protection does not mean that we are
guaranteeing the product as “unbreakable.”
Cypress is willing to work with the customer who is concerned
about the integrity of their code. Code protection is constantly
evolving. We at Cypress are committed to continuously
improving the code protection features of our products.
5.4 EEPROM
PSoC EEPROM memory is a byte-addressable nonvolatile
memory. The CY8C32 has up to 2 KB of EEPROM memory to
store user data. Reads from EEPROM are random access at the
byte level. Reads are done directly; writes are done by sending
write commands to an EEPROM programming interface. CPU
code execution can continue from flash during EEPROM writes.
EEPROM is erasable and writeable at the row level. The
EEPROM is divided into 128 rows of 16 bytes each. The factory
default values of all EEPROM bytes are 0.
Because the EEPROM is mapped to the 8051 xdata space, the
CPU cannot execute out of EEPROM. There is no ECC
hardware associated with EEPROM. If ECC is required it must
be handled in firmware.
It can take as much as 20 milliseconds to write to EEPROM or
flash. During this time the device should not be reset, or
unexpected changes may be made to portions of EEPROM or
flash. Reset sources (see Section 6.3.1) include XRES pin,
software reset, and watchdog; care should be taken to make
sure that these are not inadvertently activated. In addition, the
low voltage detect circuits should be configured to generate an
interrupt instead of a reset.
Page 24 of 128
PSoC® 3: CY8C32 Family Data Sheet
5.5 Nonvolatile Latches (NVLs)
PSoC has a 4-byte array of nonvolatile latches (NVLs) that are used to configure the device at reset. The NVL register map is shown
in Table 5-2.
Table 5-2. Device Configuration NVL Register Map
Register Address
0x00
0x01
0x02
7
6
5
4
3
2
PRT3RDM[1:0]
PRT2RDM[1:0]
PRT1RDM[1:0]
PRT12RDM[1:0]
PRT6RDM[1:0]
PRT5RDM[1:0]
XRESMEN
0x03
1
PRT4RDM[1:0]
DBGEN
DIG_PHS_DLY[3:0]
0
PRT0RDM[1:0]
PRT15RDM[1:0]
ECCEN
DPS[1:0]
The details for individual fields and their factory default settings are shown in Table 5-3:.
Table 5-3. Fields and Factory Default Settings
Field
Description
Settings
PRTxRDM[1:0]
Controls reset drive mode of the corresponding IO port. 00b (default) - high impedance analog
See “Reset Configuration” on page 44. All pins of the 01b - high impedance digital
port are set to the same mode.
10b - resistive pull up
11b - resistive pull down
XRESMEN
Controls whether pin P1[2] is used as a GPIO or as an 0 (default for 68-pin 72-pin, and 100-pin parts) - GPIO
1 (default for 48-pin parts) - external reset
external reset. See “Pin Descriptions” on page 12,
XRES description.
DBGEN
Debug Enable allows access to the debug system, for 0 - access disabled
third-party programmers.
1 (default) - access enabled
DPS[1:0]
Controls the usage of various P1 pins as a debug port. 00b - 5-wire JTAG
See “Programming, Debug Interfaces, Resources” on 01b (default) - 4-wire JTAG
10b - SWD
page 62.
11b - debug ports disabled
ECCEN
Controls whether ECC flash is used for ECC or for
general configuration and data storage. See “Flash
Program Memory” on page 24.
0 - ECC disabled
1 (default) - ECC enabled
DIG_PHS_DLY[3:0]
Selects the digital clock phase delay.
See the TRM for details.
Although PSoC Creator provides support for modifying the device configuration NVLs, the number of NVL erase / write cycles is limited
– see “Nonvolatile Latches (NVL))” on page 100.
Document Number: 001-56955 Rev. AB
Page 25 of 128
PSoC® 3: CY8C32 Family Data Sheet
5.6 External Memory Interface
CY8C32 provides an external memory interface (EMIF) for
connecting to external memory devices. The connection allows
read and write accesses to external memories. The EMIF
operates in conjunction with UDBs, I/O ports, and other
hardware to generate external memory address and control
signals. At 33 MHz, each memory access cycle takes four bus
clock cycles.
Figure 5-1 is the EMIF block diagram. The EMIF supports
synchronous and asynchronous memories. The CY8C32
supports only one type of external memory device at a time.
External memory can be accessed via the 8051 xdata space; up
to 24 address bits can be used. See “xdata Space” section on
page 28. The memory can be 8 or 16 bits wide.
Figure 5-1. EMIF Block Diagram
Address Signals
External_ MEM_ ADDR[23:0]
I/O
PORTs
Data Signals
External_ MEM_ DATA[15:0]
I/O
PORTs
Control Signals
I/O
PORTs
Data,
Address,
and Control
Signals
I/O IF
PHUB
Data,
Address,
and Control
Signals
Control
DSI Dynamic Output
Control
UDB
DSI to Port
Data,
Address,
and Control
Signals
EM Control
Signals
Other
Control
Signals
EMIF
5.7 Memory Map
5.7.2 Internal Data Space
The CY8C32 8051 memory map is very similar to the MCS-51
memory map.
The CY8C32 8051 internal data space is 384 bytes, compressed
within a 256-byte space. This space consists of 256 bytes of
RAM (in addition to the SRAM mentioned in Static RAM on page
24) and a 128-byte space for Special Function Registers (SFRs).
See Figure 5-2. The lowest 32 bytes are used for 4 banks of
registers R0-R7. The next 16 bytes are bit-addressable.
5.7.1 Code Space
The CY8C32 8051 code space is 64 KB. Only main flash exists
in this space. See the “Flash Program Memory” section on
page 24.
Document Number: 001-56955 Rev. AB
Page 26 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 5-2. 8051 Internal Data Space
0x00
In addition to the register or bit address modes used with the
lower 48 bytes, the lower 128 bytes can be accessed with direct
or indirect addressing. With direct addressing mode, the upper
128 bytes map to the SFRs. With indirect addressing mode, the
upper 128 bytes map to RAM. Stack operations use indirect
addressing; the 8051 stack space is 256 bytes. See the
“Addressing Modes” section on page 13
4 Banks, R0-R7 Each
0x1F
0x20
Bit-Addressable Area
0x2F
0x30
Lower Core RAM Shared with Stack Space
(direct and indirect addressing)
0x7F
0x80
Upper Core RAM Shared
with Stack Space
(indirect addressing)
0xFF
SFR
Special Function Registers
(direct addressing)
5.7.3 SFRs
The special function register (SFR) space provides access to frequently accessed registers. The memory map for the SFR memory
space is shown in Table 5-4.
Table 5-4. SFR Map
Address
0×F8
0×F0
0×E8
0×E0
0×D8
0×D0
0×C8
0×C0
0×B8
0×B0
0×A8
0×A0
0×98
0×90
0×88
0×80
0/8
SFRPRT15DR
B
SFRPRT12DR
ACC
SFRPRT6DR
PSW
SFRPRT5DR
SFRPRT4DR
–
SFRPRT3DR
IE
P2AX
SFRPRT2DR
SFRPRT1DR
–
SFRPRT0DR
1/9
SFRPRT15PS
–
SFRPRT12PS
–
SFRPRT6PS
–
SFRPRT5PS
SFRPRT4PS
–
SFRPRT3PS
–
–
SFRPRT2PS
SFRPRT1PS
SFRPRT0PS
SP
2/A
SFRPRT15SEL
SFRPRT12SEL
MXAX
–
SFRPRT6SEL
–
SFRPRT5SEL
SFRPRT4SEL
–
SFRPRT3SEL
–
SFRPRT1SEL
SFRPRT2SEL
–
SFRPRT0SEL
DPL0
The CY8C32 family provides the standard set of registers found
on industry standard 8051 devices. In addition, the CY8C32
devices add SFRs to provide direct access to the I/O ports on the
device. The following sections describe the SFRs added to the
CY8C32 family.
5.7.3.1 XData Space Access SFRs
The 8051 core features dual DPTR registers for faster data
transfer operations. The data pointer select SFR, DPS, selects
which data pointer register, DPTR0 or DPTR1, is used for the
following instructions:
MOVX @DPTR, A
MOVX A, @DPTR
MOVC A, @A+DPTR
JMP @A+DPTR
INC DPTR
MOV DPTR, #data16
Document Number: 001-56955 Rev. AB
3/B
–
–
–
–
–
–
–
–
–
–
–
–
–
DPX0
–
DPH0
4/C
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DPL1
5/D
–
–
–
–
–
–
–
–
–
–
–
–
–
DPX1
–
DPH1
6/E
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
DPS
7/F
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
The extended data pointer SFRs, DPX0, DPX1, MXAX, and
P2AX, hold the most significant parts of memory addresses
during access to the xdata space. These SFRs are used only
with the MOVX instructions.
During a MOVX instruction using the DPTR0/DPTR1 register,
the most significant byte of the address is always equal to the
contents of DPX0/DPX1.
During a MOVX instruction using the R0 or R1 register, the most
significant byte of the address is always equal to the contents of
MXAX, and the next most significant byte is always equal to the
contents of P2AX.
5.7.3.2 I/O Port SFRs
The I/O ports provide digital input sensing, output drive, pin
interrupts, connectivity for analog inputs and outputs, LCD, and
access to peripherals through the DSI. Full information on I/O
ports is found in I/O System and Routing on page 37.
Page 27 of 128
PSoC® 3: CY8C32 Family Data Sheet
I/O ports are linked to the CPU through the PHUB and are also
available in the SFRs. Using the SFRs allows faster access to a
limited set of I/O port registers, while using the PHUB allows boot
configuration and access to all I/O port registers.
Each SFR supported I/O port provides three SFRs:
SFRPRTxDR sets the output data state of the port (where x is
port number and includes ports 0 – 6, 12 and 15).
The SFRPRTxSEL selects whether the PHUB PRTxDR
register or the SFRPRTxDR controls each pin’s output buffer
within the port. If a SFRPRTxSEL[y] bit is high, the
corresponding SFRPRTxDR[y] bit sets the output state for that
pin. If a SFRPRTxSEL[y] bit is low, the corresponding
PRTxDR[y] bit sets the output state of the pin (where y varies
from 0 to 7).
The SFRPRTxPS is a read only register that contains pin state
values of the port pins.
5.7.4 xdata Space
The 8051 xdata space is 24-bit, or 16 MB in size. The majority of
this space is not “external”—it is used by on-chip components.
See Table 5-5. External, that is, off-chip, memory can be
accessed using the EMIF. See External Memory Interface on
page 26.
6. System Integration
6.1 Clocking System
The clocking system generates, divides, and distributes clocks
throughout the PSoC system. For the majority of systems, no
external crystal is required. The IMO and PLL together can
generate up to a 50 MHz clock, accurate to ±2 percent over
voltage and temperature. Additional internal and external clock
sources allow each design to optimize accuracy, power, and
cost. Any of the clock sources can be used to generate other
clock frequencies in the 16-bit clock dividers and UDBs for
anything the user wants, for example a UART baud rate
generator.
Clock generation and distribution is automatically configured
through the PSoC Creator IDE graphical interface. This is based
on the complete system’s requirements. It greatly speeds the
design process. PSoC Creator allows you to build clocking
systems with minimal input. You can specify desired clock
frequencies and accuracies, and the software locates or builds a
clock that meets the required specifications. This is possible
because of the programmability inherent in PSoC.
Key features of the clocking system include:
Seven general purpose clock sources
0×00 4000 – 0×00 42FF
Clocking, PLLs, and oscillators
0×00 4300 – 0×00 43FF
Power management
0×00 4400 – 0×00 44FF
Interrupt controller
0×00 4500 – 0×00 45FF
Ports interrupt control
0×00 4700 – 0×00 47FF
Flash programming interface
3- to 24-MHz IMO, ±2 percent at 3 MHz
4- to 25-MHz external crystal oscillator (MHzECO)
Clock doubler provides a doubled clock frequency output for
the USB block, see USB Clock Domain on page 31
DSI signal from an external I/O pin or other logic
24- to 50- MHz fractional PLL sourced from IMO, MHzECO,
or DSI
1-kHz, 33-kHz, 100-kHz ILO for watchdog timer (WDT) and
sleep timer
32.768-kHz external crystal oscillator (kHzECO) for RTC
IMO has a USB mode that auto locks to the USB bus clock
requiring no external crystal for USB. (USB equipped parts only)
0×00 4800 – 0×00 48FF
Cache controller
Independently sourced clock in all clock dividers
0×00 4900 – 0×00 49FF
I 2C
Eight 16-bit clock dividers for the digital system
Table 5-5. XDATA Data Address Map
Address Range
0×00 0000 – 0×00 1FFF
Purpose
SRAM
controller
0×00 4E00 – 0×00 4EFF Decimator
Four 16-bit clock dividers for the analog system
0×00 4F00 – 0×00 4FFF Fixed timer/counter/PWMs
Dedicated 16-bit divider for the bus clock
0×00 5000 – 0×00 51FF
I/O ports control
Dedicated 4-bit divider for the CPU clock
0×00 5400 – 0×00 54FF
External Memory Interface (EMIF)
control registers
Automatic clock configuration in PSoC Creator
0×00 5800 – 0×00 5FFF
Analog Subsystem interface
0×00 6000 – 0×00 60FF
USB controller
0×00 6400 – 0×00 6FFF
UDB Working Registers
0×00 7000 – 0×00 7FFF
PHUB configuration
0×00 8000 – 0×00 8FFF
EEPROM
0×01 0000 – 0×01 FFFF Digital Interconnect configuration
0×05 0220 – 0×05 02F0
Debug controller
0×08 0000 – 0×08 1FFF
Flash ECC bytes
0×80 0000 – 0×FF FFFF External Memory Interface
Document Number: 001-56955 Rev. AB
Page 28 of 128
PSoC® 3: CY8C32 Family Data Sheet
Table 6-1. Oscillator Summary
Source
IMO
MHzECO
Fmin
3 MHz
4 MHz
Tolerance at Fmin
±2% over voltage and temperature
Crystal dependent
Fmax
24 MHz
25 MHz
Tolerance at Fmax
±4%
Crystal dependent
DSI
PLL
Doubler
ILO
0 MHz
24 MHz
48 MHz
1 kHz
Input dependent
Input dependent
Input dependent
–50%, +100%
33 MHz
50 MHz
48 MHz
100 kHz
Input dependent
Input dependent
Input dependent
–55%, +100%
kHzECO
32 kHz
Crystal dependent
32 kHz
Crystal dependent
Startup Time
13-µs max
5 ms typ, max is
crystal dependent
Input dependent
250 µs max
1 µs max
15 ms max in lowest
power mode
500 ms typ, max is
crystal dependent
Figure 6-1. Clocking Subsystem
3-24 MHz
IMO
4-25 MHz
ECO
External IO
or DSI
0-33 MHz
32 kHz ECO
1,33,100 kHz
ILO
CPU
Clock
CPU Clock Divider
4 bit
48 MHz
Doubler for
USB
24-50 MHz
PLL
Master
Mux
Bus
Clock
Bus Clock Divider
16 bit
7
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
7
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Document Number: 001-56955 Rev. AB
Page 29 of 128
PSoC® 3: CY8C32 Family Data Sheet
6.1.1 Internal Oscillators
Figure 6-1 shows that there are two internal oscillators. They can
be routed directly or divided. The direct routes may not have a
50% duty cycle. Divided clocks have a 50% duty cycle.
6.1.1.1 Internal Main Oscillator
In most designs the IMO is the only clock source required, due
to its ±2-percent accuracy. The IMO operates with no external
components and outputs a stable clock. A factory trim for each
frequency range is stored in the device. With the factory trim,
tolerance varies from ±2 percent at 3 MHz, up to ±4-percent at
24 MHz. The IMO, in conjunction with the PLL, allows generation
of other clocks up to the device's maximum frequency (see
Phase-locked Loop)
The IMO provides clock outputs at 3, 6, 12, and 24 MHz.
6.1.1.2 Clock Doubler
The clock doubler outputs a clock at twice the frequency of the
input clock. The doubler works at input frequency of 24 MHz,
providing 48 MHz for the USB. It can be configured to use a clock
from the IMO, MHzECO, or the DSI (external pin).
6.1.1.3 Phase-locked Loop
The PLL allows low-frequency, high-accuracy clocks to be
multiplied to higher frequencies. This is a tradeoff between
higher clock frequency and accuracy and, higher power
consumption and increased startup time.
The PLL block provides a mechanism for generating clock
frequencies based upon a variety of input sources. The PLL
outputs clock frequencies in the range of 24 to 50 MHz. Its input
and feedback dividers supply 4032 discrete ratios to create
almost any desired clock frequency. The accuracy of the PLL
output depends on the accuracy of the PLL input source. The
most common PLL use is to multiply the IMO clock at 3 MHz,
where it is most accurate to generate the other clocks up to the
device’s maximum frequency.
The PLL achieves phase lock within 250 µs (verified by bit
setting). It can be configured to use a clock from the IMO,
MHzECO or DSI (external pin). The PLL clock source can be
used until lock is complete and signaled with a lock bit. The lock
signal can be routed through the DSI to generate an interrupt.
Disable the PLL before entering low-power modes.
6.1.1.4 Internal Low-Speed Oscillator
The ILO provides clock frequencies for low-power consumption,
including the watchdog timer, and sleep timer. The ILO
generates up to three different clocks: 1 kHz, 33 kHz, and
100 kHz.
The 1 kHz clock (CLK1K) is typically used for a background
‘heartbeat’ timer. This clock inherently lends itself to low-power
supervisory operations such as the watchdog timer and long
sleep intervals using the central timewheel (CTW).
The central timewheel is a 1 kHz, free running, 13-bit counter
clocked by the ILO. The central timewheel is always enabled,
except in hibernate mode and when the CPU is stopped during
debug on chip mode. It can be used to generate periodic
interrupts for timing purposes or to wake the system from a
low-power mode. Firmware can reset the central timewheel.
Systems that require accurate timing should use the RTC
capability instead of the central timewheel.
Document Number: 001-56955 Rev. AB
The 100-kHz clock (CLK100K) can be used as a low power
master clock. It can also generate time intervals using the fast
timewheel.
The fast timewheel is a 5-bit counter, clocked by the 100-kHz
clock. It features programmable settings and automatically
resets when the terminal count is reached. An optional interrupt
can be generated each time the terminal count is reached. This
enables flexible, periodic interrupts of the CPU at a higher rate
than is allowed using the central timewheel.
The 33-kHz clock (CLK33K) comes from a divide-by-3 operation
on CLK100K. This output can be used as a reduced accuracy
version of the 32.768-kHz ECO clock with no need for a crystal.
6.1.2 External Oscillators
Figure 6-1 shows that there are two external oscillators. They
can be routed directly or divided. The direct routes may not have
a 50% duty cycle. Divided clocks have a 50% duty cycle.
6.1.2.1 MHz External Crystal Oscillator
The MHzECO provides high frequency, high precision clocking
using an external crystal (see Figure 6-2). It supports a wide
variety of crystal types, in the range of 4 to 25 MHz. When used
in conjunction with the PLL, it can generate other clocks up to the
device's maximum frequency (see “Phase-locked Loop” section
on page 30). The GPIO pins connecting to the external crystal
and capacitors are fixed. MHzECO accuracy depends on the
crystal chosen.
Figure 6-2. MHzECO Block Diagram
4 - 25 MHz
Crystal Osc
Xi
(Pin P15[1])
External
Components
XCLK_MHZ
Xo
(Pin P15[0])
4 – 25 MHz
crystal
Capacitors
6.1.2.2 32.768-kHz ECO
The 32.768-kHz External Crystal Oscillator (32kHzECO)
provides precision timing with minimal power consumption using
an external 32.768-kHz watch crystal (see Figure 6-3). The
32kHzECO also connects directly to the sleep timer and provides
the source for the RTC. The RTC uses a 1-second interrupt to
implement the RTC functionality in firmware.
The oscillator works in two distinct power modes. This allows
users to trade off power consumption with noise immunity from
neighboring circuits. The GPIO pins connected to the external
crystal and capacitors are fixed.
Page 30 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 6-3. 32kHzECO Block Diagram
32 kHz
Crystal Osc
Xi
(Pin P15[3])
XCLK32K
Xo
(Pin P15[2])
External
Components
32 kHz
crystal
Capacitors
It is recommended that the external 32.768-kHz watch crystal
have a load capacitance (CL) of 6 pF or 12.5 pF. Check the
crystal manufacturer's datasheet. The two external capacitors,
CL1 and CL2, are typically of the same value, and their total
capacitance, CL1CL2 / (CL1 + CL2), including pin and trace
capacitance, should equal the crystal CL value. For more
information, refer to application note AN54439: PSoC 3 and
PSoC 5 External Oscillators. See also pin capacitance
specifications in the “GPIO” section on page 76.
6.1.2.3 Digital System Interconnect
The DSI provides routing for clocks taken from external clock
oscillators connected to I/O. The oscillators can also be
generated within the device in the digital system and Universal
Digital Blocks.
While the primary DSI clock input provides access to all clocking
resources, up to eight other DSI clocks (internally or externally
generated) may be routed directly to the eight digital clock
dividers. This is only possible if there are multiple precision clock
sources.
6.1.3 Clock Distribution
All seven clock sources are inputs to the central clock distribution
system. The distribution system is designed to create multiple
high precision clocks. These clocks are customized for the
design’s requirements and eliminate the common problems
found with limited resolution prescalers attached to peripherals.
The clock distribution system generates several types of clock
trees.
Bus Clock 16-bit divider uses the master clock to generate the
bus clock used for data transfers. Bus clock is the source clock
for the CPU clock divider.
Eight fully programmable 16-bit clock dividers generate digital
system clocks for general use in the digital system, as
configured by the design’s requirements. Digital system clocks
can generate custom clocks derived from any of the seven
clock sources for any purpose. Examples include baud rate
generators, accurate PWM periods, and timer clocks, and
many others. If more than eight digital clock dividers are
required, the Universal Digital Blocks (UDBs) and fixed function
Timer/Counter/PWMs can also generate clocks.
Four 16-bit clock dividers generate clocks for the analog system
components that require clocking, such as ADC. The analog
clock dividers include skew control to ensure that critical analog
events do not occur simultaneously with digital switching
events. This is done to reduce analog system noise.
Each clock divider consists of an 8-input multiplexer, a 16-bit
clock divider (divide by 2 and higher) that generates ~50 percent
duty cycle clocks, master clock resynchronization logic, and
deglitch logic. The outputs from each digital clock tree can be
routed into the digital system interconnect and then brought back
into the clock system as an input, allowing clock chaining of up
to 32 bits.
6.1.4 USB Clock Domain
The USB clock domain is unique in that it operates largely
asynchronously from the main clock network. The USB logic
contains a synchronous bus interface to the chip, while running
on an asynchronous clock to process USB data. The USB logic
requires a 48 MHz frequency. This frequency can be generated
from different sources, including DSI clock at 48 MHz or doubled
value of 24 MHz from internal oscillator, DSI signal, or crystal
oscillator.
6.2 Power System
The power system consists of separate analog, digital, and I/O
supply pins, labeled VDDA, VDDD, and VDDIOX, respectively. It
also includes two internal 1.8 V regulators that provide the digital
(VCCD) and analog (VCCA) supplies for the internal core logic.
The output pins of the regulators (VCCD and VCCA) and the
VDDIO pins must have capacitors connected as shown in
Figure 6-4. The two VCCD pins must be shorted together, with
as short a trace as possible, and connected to a 1-µF
±10-percent X5R capacitor. The power system also contains a
sleep regulator, an I2C regulator, and a hibernate regulator.
The master clock is used to select and supply the fastest clock
in the system for general clock requirements and clock
synchronization of the PSoC device.
Document Number: 001-56955 Rev. AB
Page 31 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 6-4. PSoC Power System
VDDD
1 µF
VDDIO2
VDDD
I/O Supply
VSSD
VCCD
VDDIO 2
VDDIO0
0.1µF
0.1µF
I/O Supply
VDDIO0
0.1µF
I2C
Regulator
Sleep
Regulator
Digital
Domain
VDDA
VDDA
Analog
Regulator
Digital
Regulators
VSSB
VCCA
0.1µF
1 µF
VSSA
VDDD
VSSD
I/O Supply
VCCD
VDDIO1
Hibernate
Regulator
0.1µF
I/O Supply
VDDIO3
Analog
Domain
0.1µF
0.1µF
VDDIO1
VDDD
VDDIO3
Notes
The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as
shown in Figure 2-8 on page 12.
It is good practice to check the datasheets for your bypass capacitors, specifically the working voltage and the DC bias specifications.
With some capacitors, the actual capacitance can decrease considerably when the DC bias (VDDX or VCCX in Figure 6-4) is a
significant percentage of the rated working voltage.
You can power the device in internally regulated mode, where the voltage applied to the VDDx pins is as high as 5.5 V, and the
internal regulators provide the core voltages. In this mode, do not apply power to the VCCx pins, and do not tie the VDDx pins
to the VCCx pins.
You can also power the device in externally regulated mode, that is, by directly powering the VCCD and VCCA pins. In this
configuration, the VDDD pins should be shorted to the VCCD pins and the VDDA pin should be shorted to the VCCA pin. The
allowed supply range in this configuration is 1.71 V to 1.89 V. After power up in this configuration, the internal regulators are on by
default, and should be disabled to reduce power consumption.
Document Number: 001-56955 Rev. AB
Page 32 of 128
PSoC® 3: CY8C32 Family Data Sheet
6.2.1 Power Modes
PSoC 3 devices have four different power modes, as shown in
Table 6-2 and Table 6-3. The power modes allow a design to
easily provide required functionality and processing power while
simultaneously minimizing power consumption and maximizing
battery life in low-power and portable devices.
PSoC 3 power modes, in order of decreasing power
consumption are:
Active
Alternate Active
Active is the main processing mode. Its functionality is
configurable. Each power controllable subsystem is enabled or
disabled by using separate power configuration template
registers. In alternate active mode, fewer subsystems are
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
optimized to provide timed sleep intervals and RTC functionality.
The lowest power mode is hibernate, which retains register and
SRAM state, but no clocks, and allows wakeup only from I/O
pins. Figure 6-5 illustrates the allowable transitions between
power modes. Sleep and hibernate modes should not be entered
until all VDDIO supplies are at valid voltage levels.
Sleep
Hibernate
Table 6-2. Power Modes
Power Modes
Description
Entry Condition Wakeup Source
Active Clocks
Regulator
Active
Primary mode of operation, all Wakeup, reset,
peripherals available (program- manual register
entry
mable)
Any interrupt
Any
All regulators available.
(programmable) Digital and analog
regulators can be disabled
if external regulation used.
Alternate
Active
Manual register
Similar to Active mode, and is
entry
typically configured to have
fewer peripherals active to
reduce power. One possible
configuration is to use the UDBs
for processing, with the CPU
turned off
Any interrupt
Any
All regulators available.
(programmable) Digital and analog
regulators can be disabled
if external regulation used.
Sleep
All subsystems automatically
disabled
Comparator,
ILO/kHzECO
PICU, I2C, RTC,
CTW, LVD
Both digital and analog
regulators buzzed.
Digital and analog
regulators can be disabled
if external regulation used.
Hibernate
Manual register
All subsystems automatically
entry
disabled
Lowest power consuming mode
with all peripherals and internal
regulators disabled, except
hibernate regulator is enabled
Configuration and memory
contents retained
PICU
Only hibernate regulator
active.
Manual register
entry
Table 6-3. Power Modes Wakeup Time and Power Consumption
Sleep
Modes
Wakeup
Time
Current
(typ)
Code
Execution
Digital
Resources
Analog
Resources
Clock Sources
Available
Wakeup Sources
Reset
Sources
Active
–
1.2 mA[10]
Yes
All
All
All
–
All
Alternate
Active
–
–
User
defined
All
All
All
–
All
Vddsio
25 °C, Vddsio = 0 V, VIH = 3.0 V
–
–
10
µA
–
–
7
pF
Single ended mode (GPIO mode)
–
40
–
mV
Differential mode
–
35
–
mV
–
–
100
µA
CIN
Input Capacitance[39]
VH
Input voltage hysteresis
(Schmitt-Trigger)[39]
Idiode
Current through protection diode
to VSSIO
Notes
38. See Figure 6-10 on page 40 and Figure 6-13 on page 43 for more information on SIO reference
39. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. AB
Page 78 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 11-17. SIO Output High Voltage and Current,
Unregulated Mode
Figure 11-18. SIO Output Low Voltage and Current,
Unregulated Mode
Figure 11-19. SIO Output High Voltage and Current,
Regulated Mode
Table 11-12. SIO AC Specifications
Parameter
TriseF
TfallF
TriseS
TfallS
Description
Rise time in Fast Strong Mode
(90/10%)[40]
Fall time in Fast Strong Mode
(90/10%)[40]
Rise time in Slow Strong Mode
(90/10%)[40]
Fall time in Slow Strong Mode
(90/10%)[40]
Conditions
Cload = 25 pF, VDDIO = 3.3 V
Min
–
Typ
–
Max
12
Units
ns
Cload = 25 pF, VDDIO = 3.3 V
–
–
12
ns
Cload = 25 pF, VDDIO = 3.0 V
–
–
75
ns
Cload = 25 pF, VDDIO = 3.0 V
–
–
60
ns
Note
40. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. AB
Page 79 of 128
PSoC® 3: CY8C32 Family Data Sheet
Table 11-12. SIO AC Specifications (continued)
Parameter
Fsioout
Fsioin
Description
SIO output operating frequency
2.7 V < VDDIO < 5.5 V, Unregulated output (GPIO) mode, fast
strong drive mode
1.71 V < VDDIO < 2.7 V, Unregulated output (GPIO) mode, fast
strong drive mode
3.3 V < VDDIO < 5.5 V, Unregulated output (GPIO) mode, slow
strong drive mode
1.71 V < VDDIO < 3.3 V, Unregulated output (GPIO) mode, slow
strong drive mode
2.7 V < VDDIO < 5.5 V, Regulated
output mode, fast strong drive
mode
1.71 V < VDDIO < 2.7 V, Regulated
output mode, fast strong drive
mode
1.71 V < VDDIO < 5.5 V, Regulated
output mode, slow strong drive
mode
SIO input operating frequency
1.71 V < VDDIO < 5.5 V
Conditions
Min
Typ
Max
Units
90/10% VDDIO into 25 pF
–
–
33
MHz
90/10% VDDIO into 25 pF
–
–
16
MHz
90/10% VDDIO into 25 pF
–
–
5
MHz
90/10% VDDIO into 25 pF
–
–
4
MHz
Output continuously switching
into 25 pF
–
–
20
MHz
Output continuously switching
into 25 pF
–
–
10
MHz
Output continuously switching
into 25 pF
–
–
2.5
MHz
90/10% VDDIO
–
–
33
MHz
Figure 11-20. SIO Output Rise and Fall Times, Fast Strong
Mode, VDDIO = 3.3 V, 25 pF Load
Document Number: 001-56955 Rev. AB
Figure 11-21. SIO Output Rise and Fall Times, Slow Strong
Mode, VDDIO = 3.3 V, 25 pF Load
Page 80 of 128
PSoC® 3: CY8C32 Family Data Sheet
Table 11-13. SIO Comparator Specifications[41]
Parameter
Vos
Description
Min
Typ
Max
Units
VDDIO = 2 V
–
–
68
mV
VDDIO = 2.7 V
–
–
72
VDDIO = 5.5 V
–
–
82
–
–
250
μV/°C
VDDIO = 2 V
30
–
–
dB
VDDIO = 2.7 V
35
–
–
VDDIO = 5.5 V
40
–
–
–
–
30
Offset voltage
TCVos
Offset voltage drift with temp
CMRR
Common mode rejection ratio
Tresp
Conditions
Response time
ns
11.4.3 USBIO
For operation in GPIO mode, the standard range for VDDD applies, see Device Level Specifications on page 68.
Table 11-14. USBIO DC Specifications
Min
Typ
Max
Units
Rusbi
Parameter
USB D+ pull-up resistance
Description
With idle bus
Conditions
0.900
–
1.575
k
Rusba
USB D+ pull-up resistance
While receiving traffic
1.425
–
3.090
k
Vohusb
Static output high
15 k ±5% to Vss, internal pull-up
enabled
2.8
–
3.6
V
Volusb
Static output low
15 k ±5% to Vss, internal pull-up
enabled
–
–
0.3
V
Vohgpio
Output voltage high, GPIO mode
IOH = 4 mA, VDDD 3 V
2.4
–
–
V
Volgpio
Output voltage low, GPIO mode
IOL = 4 mA, VDDD 3 V
–
–
0.3
V
Vdi
Differential input sensitivity
|(D+)–(D–)|
–
–
0.2
V
Vcm
Differential input common mode
range
–
0.8
–
2.5
V
0.8
–
2
V
3
–
7
k
21.78
(–1%)
22
22.22
(+1%)
28
–
44
Vse
Single ended receiver threshold
–
Rps2
PS/2 pull-up resistance
In PS/2 mode, with PS/2 pull-up
enabled
External USB series resistor
In series with each USB pin
Zo
USB driver output impedance
Including Rext
CIN
USB transceiver input capacitance –
–
–
20
pF
IIL[41]
Input leakage current (absolute
value)
–
–
2
nA
Rext
25 °C, VDDD = 3.0 V
Note
41. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. AB
Page 81 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 11-22. USBIO Output High Voltage and Current, GPIO
Mode
Figure 11-23. USBIO Output Low Voltage and Current, GPIO
Mode
Table 11-15. USBIO AC Specifications
Parameter
Description
Tdrate
Full-speed data rate average bit rate
Tjr1
Tjr2
Tdj1
Tdj2
Tfdeop
Tfeopt
Tfeopr
Tfst
Fgpio_out
Tr_gpio
Tf_gpio
Conditions
Receiver data jitter tolerance to next
transition
Receiver data jitter tolerance to pair
transition
Driver differential jitter to next
transition
Driver differential jitter to pair transition
Source jitter for differential transition to
SE0 transition
Source SE0 interval of EOP
Receiver SE0 interval of EOP
Width of SE0 interval during differential transition
GPIO mode output operating
3 V VDDD 5.5 V
frequency
VDDD = 1.71 V
Rise time, GPIO mode, 10%/90%
VDDD > 3 V, 25 pF load
VDDD
VDDD = 1.71 V, 25 pF load
Fall time, GPIO mode, 90%/10% VDDD VDDD > 3 V, 25 pF load
VDDD = 1.71 V, 25 pF load
Document Number: 001-56955 Rev. AB
Min
12 – 0.25%
Typ
12
Units
MHz
–
Max
12 +
0.25%
8
–8
–5
–
5
ns
–3.5
–
3.5
ns
–4
–2
–
–
4
5
ns
ns
160
82
–
–
–
–
175
–
14
ns
ns
ns
–
–
–
–
–
–
–
–
–
–
–
–
20
6
12
40
12
40
MHz
MHz
ns
ns
ns
ns
ns
Page 82 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 11-24. USBIO Output Rise and Fall Times, GPIO Mode,
VDDD = 3.3 V, 25 pF Load
Table 11-16. USB Driver AC Specifications
Parameter
Description
Tr
Transition rise time
Tf
Transition fall time
TR
Rise/fall time matching
Vcrs
Conditions
VUSB_5, VUSB_3.3, see USB DC
Specifications on page 98
Output signal crossover voltage
Min
–
–
90%
Typ
–
–
–
Max
20
20
111%
Units
ns
ns
1.3
–
2
V
Min
0.7 VDDIO
–
Typ
–
–
Units
V
V
3.5
–
–
5.6
3
100
Max
–
0.3
VDDIO
8.5
–
–
–
–
100
µA
Min
1
Typ
–
Max
–
Units
µs
11.4.4 XRES
Table 11-17. XRES DC Specifications
Parameter
Description
VIH
Input voltage high threshold
VIL
Input voltage low threshold
Rpullup
CIN
VH
Idiode
Conditions
Pull-up resistor
Input capacitance[42]
Input voltage hysteresis
(Schmitt-Trigger)[42]
Current through protection diode to
VDDIO and VSSIO
k
pF
mV
Table 11-18. XRES AC Specifications
Parameter
Description
TRESET
Reset pulse width
Conditions
Note
42. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. AB
Page 83 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.5 Analog Peripherals
Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.5.1 Delta-sigma ADC
Unless otherwise specified, operating conditions are:
Operation in continuous sample mode
fclk = 6.144 MHz
Reference = 1.024 V internal reference bypassed on P3.2 or P0.3
Unless otherwise specified, all charts and graphs show typical values
Table 11-19. 12-bit Delta-sigma ADC DC Specifications
Parameter
Description
Conditions
Resolution
Number of channels, single ended
Number of channels, differential
Monotonic
Ge
Gain error
Gd
Gain drift
Vos
Input offset voltage
Temperature coefficient, input offset
voltage
Input voltage range, single ended[44]
Input voltage range, differential
unbuffered[44]
Input voltage range, differential,
buffered[44]
Integral non linearity[44]
Differential non linearity[44]
Integral non linearity[44]
Differential non linearity[44]
ADC input resistance
TCVos
INL12
DNL12
INL8
DNL8
Rin_Buff
Rin_ADC12 ADC input resistance
Differential pair is formed using a
pair of GPIOs.
Yes
Buffered, buffer gain = 1, Range =
±1.024 V, 25 °C
Buffered, buffer gain = 1, Range =
±1.024 V
Buffered, 12-bit mode
Buffer gain = 1, 12-bit,
Range = ±1.024 V
Range = ±1.024 V, unbuffered
Range = ±1.024 V, unbuffered
Range = ±1.024 V, unbuffered
Range = ±1.024 V, unbuffered
Input buffer used
Input buffer bypassed, 12 bit,
Range = ±1.024 V
Rin_ExtRef ADC external reference input resistance
ADC external reference input voltage, see
Vextref
also internal reference in Voltage
Pins P0[3], P3[2]
Reference on page 86
Current Consumption
IDD_12
IDDA + IDDD current consumption, 12 bit[44] 192 ksps, unbuffered
Buffer current consumption[44]
IBUFF
Min
8
Typ
–
Units
bits
–
Max
12
No. of
GPIO
No. of
GPIO/2
–
–
–
–
–
–
–
–
±0.2
%
–
–
50
–
–
±0.1
ppm/°
C
mV
–
–
1
µV/°C
VSSA
–
VDDA
V
VSSA
–
VDDA
V
VSSA
–
VDDA – 1
V
–
–
–
–
10
–
–
–
–
–
±1
±1
±1
±1
–
LSB
LSB
LSB
LSB
M
–
148[45]
–
k
–
70[45, 46]
–
k
0.9
–
1.3
V
–
–
–
–
1.95
2.5
mA
mA
–
–
–
Notes
44. Based on device characterization (not production tested).
45. By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional to
the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual.
46. Recommend an external reference device with an output impedance 2.7 V,
VIN 0.5 V
–
Typ
Max
Units
10
mV
Input offset voltage in slow mode
Factory trim, VIN 0.5 V
–
Input offset voltage in fast mode[49]
Custom trim
–
Input offset voltage in slow mode[49]
Custom trim
–
–
4
mV
Input offset voltage in ultra low-power
mode
VDDA ≤ 4.6 V
–
±12
–
mV
VHYST
Hysteresis
Hysteresis enable mode
–
10
32
mV
VICM
Input common mode voltage
High current / fast mode
VSSA
–
VDDA
V
Low current / slow mode
VSSA
–
VDDA
V
Ultra low power mode
VDDA ≤ 4.6 V
VSSA
–
VDDA –
1.15
VOS
–
9
mV
4
mV
CMRR
Common mode rejection ratio
–
50
–
dB
ICMP
High current mode/fast mode[50]
–
–
400
µA
–
–
100
µA
–
6
–
µA
Low current mode/slow mode[50]
Ultra low-power mode[50]
VDDA ≤ 4.6 V
Table 11-25. Comparator AC Specifications
Parameter
Description
Response time, high current mode[50]
Tresp
Response time, low current
mode[50]
Conditions
Min
Typ
Max
Units
50 mV overdrive, measured pin-to-pin
–
75
110
ns
50 mV overdrive, measured pin-to-pin
–
155
200
ns
–
55
–
µs
Response time, ultra low-power mode[50] 50 mV overdrive, measured
pin-to-pin, VDDA ≤ 4.6 V
Notes
48. The resistance of the analog global and analog mux bus is high if VDDA 2.7 V, and the chip is in either sleep or hibernate mode. Use of analog global and analog
mux bus under these conditions is not recommended
49. The recommended procedure for using a custom trim value for the on-chip comparators can be found in the TRM.
50. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. AB
Page 86 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.5.5 Current Digital-to-analog Converter (IDAC)
All specifications are based on use of the low-resistance IDAC output pins (see Pin Descriptions on page 12 for details). See the IDAC
component data sheet in PSoC Creator for full electrical specifications and APIs.
Unless otherwise specified, all charts and graphs show typical values.
Table 11-26. IDAC DC Specifications
Parameter
Description
Conditions
Resolution
IOUT
Output current at code = 255
Min
Typ
Max
Units
–
–
8
bits
Range = 2.04 mA, code = 255,
VDDA 2.7 V, Rload = 600
–
2.04
–
mA
Range = 2.04 mA, high speed
mode, code = 255, VDDA 2.7 V,
Rload = 300
–
2.04
–
mA
Range = 255 µA, code = 255, Rload
= 600
–
255
–
µA
Range = 31.875 µA, code = 255,
Rload = 600
–
31.875
–
µA
Monotonicity
–
–
Yes
Ezs
Zero scale error
–
0
±1
LSB
Eg
Gain error
Range = 2.04 mA, 25 °C
–
–
±2.5
%
Range = 255 µA, 25 ° C
–
–
±2.5
%
Range = 31.875 µA, 25 ° C
–
–
±3.5
%
Range = 2.04 mA
–
–
0.04
% / °C
TC_Eg
INL
DNL
Vcompliance
Temperature coefficient of gain
error
Integral nonlinearity
Differential nonlinearity
Dropout voltage, source or sink
mode
Document Number: 001-56955 Rev. AB
Range = 255 µA
–
–
0.04
% / °C
Range = 31.875 µA
–
–
0.05
% / °C
Sink mode, range = 255 µA, Codes
8 – 255, Rload = 2.4 k, Cload =
15 pF
–
±0.9
±1
LSB
Source mode, range = 255 µA,
Codes 8 – 255, Rload = 2.4 k,
Cload = 15 pF
–
±1.2
±1.6
LSB
Sink mode, range = 255 µA, Rload
= 2.4 k, Cload = 15 pF
–
±0.3
±1
LSB
Source mode, range = 255 µA,
Rload = 2.4 k, Cload = 15 pF
–
±0.3
±1
LSB
Voltage headroom at max current,
Rload to VDDA or Rload to VSSA,
VDIFF from VDDA
1
–
–
V
Page 87 of 128
PSoC® 3: CY8C32 Family Data Sheet
Table 11-26. IDAC DC Specifications (continued)
Parameter
IDD
Description
Operating current, code = 0
Min
Typ
Max
Units
Low speed mode, source mode,
range = 31.875 µA
Conditions
–
44
100
µA
Low speed mode, source mode,
range = 255 µA,
–
33
100
µA
Low speed mode, source mode,
range = 2.04 mA
–
33
100
µA
Low speed mode, sink mode,
range = 31.875 µA
–
36
100
µA
Low speed mode, sink mode,
range = 255 µA
–
33
100
µA
Low speed mode, sink mode,
range = 2.04 mA
–
33
100
µA
High speed mode, source mode,
range = 31.875 µA
–
310
500
µA
High speed mode, source mode,
range = 255 µA
–
305
500
µA
High speed mode, source mode,
range = 2.04 mA
–
305
500
µA
High speed mode, sink mode,
range = 31.875 µA
–
310
500
µA
High speed mode, sink mode,
range = 255 µA
–
300
500
µA
High speed mode, sink mode,
range = 2.04 mA
–
300
500
µA
Figure 11-26. IDAC INL vs Input Code, Range = 255 µA,
Source Mode
Document Number: 001-56955 Rev. AB
Figure 11-27. IDAC INL vs Input Code, Range = 255 µA, Sink
Mode
Page 88 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 11-28. IDAC DNL vs Input Code, Range = 255 µA,
Source Mode
Figure 11-29. IDAC DNL vs Input Code, Range = 255 µA, Sink
Mode
Figure 11-30. IDAC INL vs Temperature, Range = 255 µA, High
speed mode
Figure 11-31. IDAC DNL vs Temperature, Range = 255 µA,
High speed mode
Document Number: 001-56955 Rev. AB
Page 89 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 11-32. IDAC Full Scale Error vs Temperature, Range
= 255 µA, Source Mode
Figure 11-33. IDAC Full Scale Error vs Temperature, Range
= 255 µA, Sink Mode
Figure 11-34. IDAC Operating Current vs Temperature,
Range = 255 µA, Code = 0, Source Mode
Figure 11-35. IDAC Operating Current vs Temperature,
Range = 255 µA, Code = 0, Sink Mode
Document Number: 001-56955 Rev. AB
Page 90 of 128
PSoC® 3: CY8C32 Family Data Sheet
Table 11-27. IDAC AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
FDAC
Update rate
–
–
8
Msps
TSETTLE
Settling time to 0.5 LSB
Range = 31.875 µA or 255 µA, full
scale transition, High speed mode,
600 15-pF load
–
–
125
ns
Current noise
Range = 255 µA, source mode,
High speed mode, VDDA = 5 V,
10 kHz
–
340
–
pA/sqrtHz
Figure 11-36. IDAC Step Response, Codes 0x40 - 0xC0,
255 µA Mode, Source Mode, High speed mode, VDDA = 5 V
Figure 11-37. IDAC Glitch Response, Codes 0x7F - 0x80,
255 µA Mode, Source Mode, High speed mode, VDDA = 5 V
Figure 11-38. IDAC PSRR vs Frequency
Figure 11-39. IDAC Current Noise, 255 µA Mode,
Source Mode, High speed mode, VDDA = 5 V
60
PSRR, dB
P
50
40
30
20
10
0
0.1
1
10
100
1000
10000
Frequency, kHz
255 ȝA, code 0x7F
Document Number: 001-56955 Rev. AB
255 ȝA, code 0xFF
Page 91 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.5.6 Voltage Digital to Analog Converter (VDAC)
See the VDAC component datasheet in PSoC Creator for full electrical specifications and APIs.
Unless otherwise specified, all charts and graphs show typical values.
Table 11-28. VDAC DC Specifications
Parameter
Description
Conditions
Resolution
Min
Typ
Max
Units
–
8
–
bits
INL1
Integral nonlinearity
1 V scale
–
±2.1
±2.5
LSB
INL4
Integral nonlinearity[51]
4 V scale
–
±2.1
±2.5
LSB
DNL1
Differential nonlinearity
1 V scale
–
±0.3
±1
LSB
DNL4
Differential nonlinearity[51]
4 V scale
–
±0.3
±1
LSB
Rout
Output resistance
1 V scale
–
4
–
k
4 V scale
–
16
–
k
VOUT
Output voltage range, code = 255
1 V scale
–
1.02
–
V
4 V scale, VDDA = 5 V
–
4.08
–
V
–
–
Yes
–
Monotonicity
VOS
Zero scale error
Eg
Gain error
4 V scale
–
–
±2.5
%
TC_Eg
Temperature coefficient, gain error 1 V scale
–
–
0.03
%FSR / °C
IDD
Operating current
Figure 11-40. VDAC INL vs Input Code, 1 V Mode
1 V scale
–
0
±0.9
LSB
–
–
±2.5
%
4 V scale
–
–
0.03
%FSR / °C
Low speed mode
–
–
100
µA
High speed mode
–
–
500
µA
Figure 11-41. VDAC DNL vs Input Code, 1 V Mode
Note
51. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. AB
Page 92 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 11-42. VDAC INL vs Temperature, 1 V Mode
Figure 11-43. VDAC DNL vs Temperature, 1 V Mode
Figure 11-44. VDAC Full Scale Error vs Temperature, 1 V
Mode
Figure 11-45. VDAC Full Scale Error vs Temperature, 4 V
Mode
Figure 11-46. VDAC Operating Current vs Temperature, 1V
Mode, Low speed mode
Figure 11-47. VDAC Operating Current vs Temperature, 1 V
Mode, High speed mode
Document Number: 001-56955 Rev. AB
Page 93 of 128
PSoC® 3: CY8C32 Family Data Sheet
Table 11-29. VDAC AC Specifications t
Parameter
Description
Min
Typ
Max
Units
1 V scale
Conditions
–
–
1000
ksps
4 V scale
–
–
250
ksps
–
0.45
1
µs
4 V scale, Cload = 15 pF
–
0.8
3.2
µs
Settling time to 0.1%, step 75% to 1 V scale, Cload = 15 pF
25%
–
0.45
1
µs
4 V scale, Cload = 15 pF
–
0.7
3
µs
Range = 1 V, High speed mode,
VDDA = 5 V, 10 kHz
–
750
–
nV/sqrtHz
FDAC
Update rate
TsettleP
Settling time to 0.1%, step 25% to 1 V scale, Cload = 15 pF
75%
TsettleN
Voltage noise
Figure 11-48. VDAC Step Response, Codes 0x40 - 0xC0, 1 V
Mode, High speed mode, VDDA = 5 V
Figure 11-49. VDAC Glitch Response, Codes 0x7F - 0x80, 1 V
Mode, High speed mode, VDDA = 5 V
Figure 11-50. VDAC PSRR vs Frequency
Figure 11-51. VDAC Voltage Noise, 1 V Mode, High speed
mode, VDDA = 5 V
50
PSRR, dB
P
40
30
20
10
0
0.1
1
10
Frequency, kHz
4 V, code 0x7F
100
1000
4 V, code 0xFF
Document Number: 001-56955 Rev. AB
Page 94 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.5.7 Temperature Sensor
Table 11-30. Temperature Sensor Specifications
Parameter
Description
Temp sensor accuracy
Conditions
Range: –40 °C to +85 °C
Min
Typ
Max
Units
–
±5
–
°C
11.5.8 LCD Direct Drive
Table 11-31. LCD Direct Drive DC Specifications
Conditions
Min
Typ
Max
Units
ICC
Parameter
LCD system operating current
Description
Device sleep mode with wakeup at
400-Hz rate to refresh LCDs, bus
clock = 3 MHz, VDDIO = VDDA = 3 V,
4 commons, 16 segments, 1/4 duty
cycle, 50 Hz frame rate, no glass
connected
–
38
–
A
ICC_SEG
Current per segment driver
Strong drive mode
–
260
–
µA
VBIAS
LCD bias range (VBIAS refers to the VDDA 3 V and VDDA VBIAS
main output voltage(V0) of LCD DAC)
2
–
5
V
VDDA 3 V and VDDA VBIAS
–
9.1 × VDDA
–
mV
Drivers may be combined
–
500
5000
pF
–
–
20
mV
355
–
710
µA
Min
10
Typ
50
Max
150
Units
Hz
LCD bias step size
LCD capacitance per
segment/common driver
Long term segment offset
IOUT
Output drive current per segment
driver)
VDDIO = 5.5V, strong drive mode
Table 11-32. LCD Direct Drive AC Specifications
Parameter
Description
fLCD
LCD frame rate
Document Number: 001-56955 Rev. AB
Conditions
Page 95 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.6 Digital Peripherals
Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.6.1 Timer
The following specifications apply to the Timer/Counter/PWM peripheral in timer mode. Timers can also be implemented in UDBs; for
more information, see the Timer component datasheet in PSoC Creator.
Table 11-33. Timer DC Specifications
Parameter
Description
Block current consumption
Conditions
16-bit timer, at listed input clock
frequency
Min
Typ
Max
Units
–
–
–
µA
3 MHz
–
15
–
µA
12 MHz
–
60
–
µA
50 MHz
–
260
–
µA
Min
Typ
Max
Units
Operating frequency
DC
–
50.01
MHz
Capture pulse width (Internal)
21
–
–
ns
Capture pulse width (external)
42
–
–
ns
Timer resolution
21
–
–
ns
Table 11-34. Timer AC Specifications
Parameter
Description
Conditions
Enable pulse width
21
–
–
ns
Enable pulse width (external)
42
–
–
ns
Reset pulse width
21
–
–
ns
Reset pulse width (external)
42
–
–
ns
11.6.2 Counter
The following specifications apply to the Timer/Counter/PWM peripheral, in counter mode. Counters can also be implemented in
UDBs; for more information, see the Counter component datasheet in PSoC Creator.
Table 11-35. Counter DC Specifications
Parameter
Description
Block current consumption
Conditions
16-bit counter, at listed input clock
frequency
3 MHz
12 MHz
50 MHz
Min
–
Typ
–
Max
–
Units
µA
–
–
–
15
60
260
–
–
–
µA
µA
µA
Min
DC
21
21
21
42
21
42
21
42
Typ
–
–
–
–
–
–
–
–
–
Max
50.01
–
–
–
–
–
–
–
–
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
Table 11-36. Counter AC Specifications
Parameter
Description
Operating frequency
Capture pulse
Resolution
Pulse width
Pulse width (external)
Enable pulse width
Enable pulse width (external)
Reset pulse width
Reset pulse width (external)
Document Number: 001-56955 Rev. AB
Conditions
Page 96 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.6.3 Pulse Width Modulation
The following specifications apply to the Timer/Counter/PWM peripheral, in PWM mode. PWM components can also be implemented
in UDBs; for more information, see the PWM component datasheet in PSoC Creator.
Table 11-37. PWM DC Specifications
Parameter
Description
Block current consumption
Conditions
16-bit PWM, at listed input clock
frequency
Min
Typ
Max
Units
–
–
–
µA
3 MHz
–
15
–
µA
12 MHz
–
60
–
µA
50 MHz
–
260
–
µA
Min
Typ
Max
Units
Operating frequency
DC
–
50.01
MHz
Pulse width
21
–
–
ns
Pulse width (external)
42
–
–
ns
Kill pulse width
21
–
–
ns
Kill pulse width (external)
42
–
–
ns
Enable pulse width
21
–
–
ns
Enable pulse width (external)
42
–
–
ns
Reset pulse width
21
–
–
ns
Reset pulse width (external)
42
–
–
ns
Table 11-38. Pulse Width Modulation (PWM) AC Specifications
Parameter
Description
Conditions
11.6.4 I2C
Table 11-39. Fixed I2C DC Specifications
Parameter
Description
Block current consumption
Conditions
Min
Typ
Max
Units
Enabled, configured for 100 kbps
–
–
250
µA
Enabled, configured for 400 kbps
–
–
260
µA
Wake from sleep mode
–
–
30
µA
Min
Typ
Max
Units
–
–
1
Mbps
Typ
–
Max
200
Table 11-40. Fixed I2C AC Specifications
Parameter
Description
Conditions
Bit rate
11.6.5 Controller Area Network
Table 11-41. CAN DC Specifications[52]
Parameter
Description
IDD
Block current consumption
Conditions
Min
–
Units
µA
Conditions
Min
Typ
Max
Units
–
–
1
Mbit
Table 11-42. CAN AC Specifications[52]
Parameter
Description
Bit rate
Minimum 8 MHz clock
Note
52. Refer to ISO 11898 specification for details.
Document Number: 001-56955 Rev. AB
Page 97 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.6.6 USB
Table 11-43. USB DC Specifications
Parameter
Min
Typ
Max
Units
USB configured, USB regulator
enabled
4.35
–
5.25
V
VUSB_3.3
USB configured, USB regulator
bypassed
3.15
–
3.6
V
VUSB_3
USB configured, USB regulator
bypassed[53]
2.85
–
3.6
V
VUSB_5
Description
Device supply (VDDD) for USB
operation
Conditions
IUSB_Configured Device supply current in device active VDDD = 5 V, FCPU = 1.5 MHz
mode, bus clock and IMO = 24 MHz V
DDD = 3.3 V, FCPU = 1.5 MHz
–
10
–
mA
–
8
–
mA
–
0.5
–
mA
VDDD = 5 V, disconnected from
USB host
–
0.3
–
mA
VDDD = 3.3 V, connected to USB
host, PICU configured to wake on
USB resume signal
–
0.5
–
mA
VDDD = 3.3 V, disconnected from
USB host
–
0.3
–
mA
IUSB_Suspended Device supply current in device sleep VDDD = 5 V, connected to USB
mode
host, PICU configured to wake on
USB resume signal
11.6.7 Universal Digital Blocks (UDBs)
PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM,
AND, OR, and so on) that are mapped to the UDB array. See the component datasheets in PSoC Creator for full AC/DC specifications,
APIs, and example code.
Table 11-44. UDB AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
FMAX_TIMER Maximum frequency of 16-bit timer in
a UDB pair
–
–
50.01
MHz
FMAX_ADDER Maximum frequency of 16-bit adder in
a UDB pair
–
–
50.01
MHz
–
–
50.01
MHz
–
–
50.01
MHz
Datapath Performance
FMAX_CRC
Maximum frequency of 16-bit
CRC/PRS in a UDB pair
PLD Performance
FMAX_PLD
Maximum frequency of a two-pass
PLD function in a UDB pair
Clock to Output Performance
tCLK_OUT
Propagation delay for clock in to data 25 °C, VDDD 2.7 V
out, see Figure 11-52 on page 99.
–
20
25
ns
tCLK_OUT
Propagation delay for clock in to data Worst-case placement, routing,
out, see Figure 11-52 on page 99.
and pin selection
–
–
55
ns
Note
53. Rise/fall time matching (TR) not guaranteed, see USB Driver AC Specifications on page 83.
Document Number: 001-56955 Rev. AB
Page 98 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 11-52. Clock to Output Performance
11.7 Memory
Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.7.1 Flash
Table 11-45. Flash DC Specifications
Parameter
Description
Erase and program voltage
Conditions
VDDD pin
Min
Typ
Max
Units
1.71
–
5.5
V
Min
–
–
–
–
–
–
20
Typ
15
10
5
–
–
1.5
–
Max
20
13
7
35
15
2
–
Units
ms
ms
ms
ms
ms
seconds
years
10
–
–
Table 11-46. Flash AC Specifications
Parameter
Description
Conditions
TWRITE
Row write time (erase + program)
Row erase time
TERASE
Row program time
TBULK
Bulk erase time (16 KB to 64 KB)
Sector erase time (8 KB to 16 KB)
Total device programming time
No overhead[54]
TPROG
Flash data retention time, retention
Average ambient temp.
period measured from last erase cycle TA 55 °C, 100 K erase/program
cycles
Average ambient temp.
TA 85 °C, 10 K erase/program
cycles
Note
54. See PSoC® 3 Device Programming Specifications for a description of a low-overhead method of programming PSoC 3 flash.
Document Number: 001-56955 Rev. AB
Page 99 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.7.2 EEPROM
Table 11-47. EEPROM DC Specifications
Parameter
Description
Erase and program voltage
Conditions
Min
1.71
Typ
–
Max
5.5
Units
V
Min
–
20
Typ
10
–
Max
20
–
Units
ms
years
20
–
–
10
–
–
Min
Typ
Max
Units
VDDD pin
1.71
–
5.5
V
Conditions
Programmed at 25 °C
Min
1K
Typ
–
Max
–
Programmed at 0 °C to 70 °C
100
–
–
Average ambient temp. TA ≤ 55 °C
Average ambient temp. TA ≤ 85 °C
20
10
–
–
–
–
Units
program/
erase
cycles
program/
erase
cycles
years
years
Conditions
Min
Typ
Max
Units
1.2
–
–
V
Min
Typ
Max
Units
DC
–
50.01
MHz
Table 11-48. EEPROM AC Specifications
Parameter
Description
Conditions
TWRITE
Single row erase/write cycle time
EEPROM data retention time, retention Average ambient temp, TA 25 °C,
period measured from last erase cycle 1M erase/program cycles
Average ambient temp, TA 55 °C,
100 K erase/program cycles
Average ambient temp.
TA 85 °C, 10 K erase/program
cycles
11.7.3 Nonvolatile Latches (NVL))
Table 11-49. NVL DC Specifications
Parameter
Description
Erase and program voltage
Conditions
Table 11-50. NVL AC Specifications
Parameter
Description
NVL endurance
NVL data retention time
11.7.4 SRAM
Table 11-51. SRAM DC Specifications
Parameter
VSRAM
Description
SRAM retention voltage
Table 11-52. SRAM AC Specifications
Parameter
FSRAM
Description
SRAM operating frequency
Document Number: 001-56955 Rev. AB
Conditions
Page 100 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.7.5 External Memory Interface
Figure 11-53. Asynchronous Write and Read Cycle Timing, No Wait States
Tbus_clock
Bus Clock
EM_Addr
EM_CE
EM_WE
EM_OE
Twr_setup
Trd_hold
Trd_setup
EM_Data
Write Cycle
Read Cycle
Minimum of 4 bus clock cycles between successive EMIF accesses
Table 11-53. Asynchronous Write and Read Timing Specifications[55]
Parameter
Description
Fbus_clock Bus clock
frequency[56]
Tbus_clock Bus clock period[57]
Conditions
Min
Typ
Max
Units
–
–
33
MHz
30.3
–
–
ns
Tbus_clock – 10
–
–
ns
Twr_Setup
Time from EM_data valid to rising edge of
EM_WE and EM_CE
Trd_setup
Time that EM_data must be valid before rising
edge of EM_OE
5
–
–
ns
Trd_hold
Time that EM_data must be valid after rising
edge of EM_OE
5
–
–
ns
Notes
55. Based on device characterization (Not production tested).
56. EMIF signal timings are limited by GPIO frequency limitations. See “GPIO” section on page 76.
57. EMIF output signals are generally synchronized to bus clock, so EMIF signal timings are dependent on bus clock frequency.
Document Number: 001-56955 Rev. AB
Page 101 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 11-54. Synchronous Write and Read Cycle Timing, No Wait States
Tbus_clock
Bus Clock
EM_Clock
EM_Addr
EM_CE
EM_ADSC
EM_WE
EM_OE
Twr_setup
Trd_hold
Trd_setup
EM_Data
Write Cycle
Read Cycle
Minimum of 4 bus clock cycles between successive EMIF accesses
Table 11-54. Synchronous Write and Read Timing Specifications[58]
Parameter
Description
Fbus_clock
Bus clock frequency
Tbus_clock
Bus clock period[60]
Twr_Setup
[59]
Conditions
Min
Typ
Max
Units
–
–
33
MHz
30.3
–
–
ns
Time from EM_data valid to rising edge
of EM_Clock
Tbus_clock – 10
–
–
ns
Trd_setup
Time that EM_data must be valid before
rising edge of EM_OE
5
–
–
ns
Trd_hold
Time that EM_data must be valid after
rising edge of EM_OE
5
–
–
ns
Notes
58. Based on device characterization (Not production tested).
59. EMIF signal timings are limited by GPIO frequency limitations. See “GPIO” section on page 76.
60. EMIF output signals are generally synchronized to bus clock, so EMIF signal timings are dependent on bus clock frequency.
Document Number: 001-56955 Rev. AB
Page 102 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 11-55. Synchronous Read Cycle Timing
Tcp/2
EM_ Clock
Tceld
Tcehd
EM_ CEn
Taddriv
Taddrv
EM_ Addr
Address
Toeld
Toehd
EM_ OEn
Tds
Data
EM_ Data
Tadscld
Tadschd
EM_ ADSCn
Table 11-55. Synchronous Read Cycle Specifications
Parameter
Description
period[61]
Conditions
VDDA 3.3 V
Min
Typ
Max
Units
30.3
–
–
ns
T/2
–
–
ns
T
EMIF clock
Tcp/2
EM_Clock pulse high
Tceld
EM_CEn low to EM_Clock high
5
–
–
ns
Tcehd
EM_Clock high to EM_CEn high
T/2 – 5
–
–
ns
Taddrv
EM_Addr valid to EM_Clock high
Taddriv
EM_Clock high to EM_Addr invalid
Toeld
Toehd
5
–
–
ns
T/2 – 5
–
–
ns
EM_OEn low to EM_Clock high
5
–
–
ns
EM_Clock high to EM_OEn high
T
–
–
ns
Tds
Data valid before EM_OEn high
T + 15
–
–
ns
Tadscld
EM_ADSCn low to EM_Clock high
5
–
–
ns
Tadschd
EM_Clock high to EM_ADSCn high
T/2 – 5
–
–
ns
Note
61. Limited by GPIO output frequency, see Table 11-10 on page 77.
Document Number: 001-56955 Rev. AB
Page 103 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 11-56. Synchronous Write Cycle Timing
Tcp/2
EM_ Clock
Tceld
Tcehd
EM_ CEn
Taddriv
Taddrv
EM_ Addr
Address
Tweld
Twehd
EM_ WEn
Tdh
Tds
Data
EM_ Data
Tadschd
Tadscld
EM_ ADSCn
Table 11-56. Synchronous Write Cycle Specifications
Parameter
Description
Period[62]
Conditions
VDDA 3.3 V
Min
Typ
Max
Units
30.3
–
–
ns
T/2
–
–
ns
T
EMIF clock
Tcp/2
EM_Clock pulse high
Tceld
EM_CEn low to EM_Clock high
5
–
–
ns
Tcehd
EM_Clock high to EM_CEn high
T/2 – 5
–
–
ns
Taddrv
EM_Addr valid to EM_Clock high
Taddriv
EM_Clock high to EM_Addr invalid
Tweld
Twehd
Tds
Tdh
Tadscld
Tadschd
5
–
–
ns
T/2 – 5
–
–
ns
EM_WEn low to EM_Clock high
5
–
–
ns
EM_Clock high to EM_WEn high
T/2 – 5
–
–
ns
Data valid before EM_Clock high
5
–
–
ns
Data invalid after EM_Clock high
T
–
–
ns
EM_ADSCn low to EM_Clock high
5
–
–
ns
EM_Clock high to EM_ADSCn high
T/2 – 5
–
–
ns
Note
62. Limited by GPIO output frequency, see Table 11-10 on page 77.
Document Number: 001-56955 Rev. AB
Page 104 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.8 PSoC System Resources
Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.8.1 POR with Brown Out
For brown out detect in regulated mode, VDDD and VDDA must be 2.0 V. Brown out detect is not available in externally regulated
mode.
Table 11-57. Precise Low-Voltage Reset (PRES) with Brown Out DC Specifications
Parameter
Description
PRESR
Rising trip voltage
PRESF
Falling trip voltage
Conditions
Factory trim
Min
Typ
Max
Units
1.64
–
1.68
V
1.62
–
1.66
V
Min
Typ
Max
Units
–
–
0.5
µs
–
5
–
V/sec
Min
Typ
Max
Units
1.68
1.89
2.14
2.38
2.62
2.87
3.11
3.35
3.59
3.84
4.08
4.32
4.56
4.83
5.05
5.30
5.57
1.73
1.95
2.20
2.45
2.71
2.95
3.21
3.46
3.70
3.95
4.20
4.45
4.70
4.98
5.21
5.47
5.75
1.77
2.01
2.27
2.53
2.79
3.04
3.31
3.56
3.81
4.07
4.33
4.59
4.84
5.13
5.37
5.63
5.92
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
Min
Typ
Max
Units
–
–
1
µs
Table 11-58. Power-on Reset (POR) with Brown Out AC Specifications
Parameter
Description
Conditions
PRES_TR Response time
VDDD/VDDA droop rate
Sleep mode
11.8.2 Voltage Monitors
Table 11-59. Voltage Monitors DC Specifications
Parameter
Description
LVI
Trip voltage
HVI
Conditions
LVI_A/D_SEL[3:0] = 0000b
LVI_A/D_SEL[3:0] = 0001b
LVI_A/D_SEL[3:0] = 0010b
LVI_A/D_SEL[3:0] = 0011b
LVI_A/D_SEL[3:0] = 0100b
LVI_A/D_SEL[3:0] = 0101b
LVI_A/D_SEL[3:0] = 0110b
LVI_A/D_SEL[3:0] = 0111b
LVI_A/D_SEL[3:0] = 1000b
LVI_A/D_SEL[3:0] = 1001b
LVI_A/D_SEL[3:0] = 1010b
LVI_A/D_SEL[3:0] = 1011b
LVI_A/D_SEL[3:0] = 1100b
LVI_A/D_SEL[3:0] = 1101b
LVI_A/D_SEL[3:0] = 1110b
LVI_A/D_SEL[3:0] = 1111b
Trip voltage
Table 11-60. Voltage Monitors AC Specifications
Parameter
Description
Response time[63]
Conditions
Note
63. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. AB
Page 105 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.8.3 Interrupt Controller
Table 11-61. Interrupt Controller AC Specifications
Parameter
Description
Conditions
Delay from interrupt signal input to ISR Includes worse case completion of
code execution from ISR code
longest instruction DIV with 6
cycles
Min
Typ
Max
Units
–
–
25
Tcy CPU
Typ
Max
Units
MHz
11.8.4 JTAG Interface
Figure 11-57. JTAG Interface Timing
(1/f_TCK)
TCK
T_TDI_setup
T_TDI_hold
TDI
T_TDO_valid
T_TDO_hold
TDO
T_TMS_setup
T_TMS_hold
TMS
Table 11-62. JTAG Interface AC Specifications[64]
Parameter
f_TCK
Description
TCK frequency
Conditions
Min
3.3 V VDDD 5 V
–
–
14[65]
1.71 V VDDD < 3.3 V
–
–
7[65]
MHz
ns
T_TDI_setup
TDI setup before TCK high
(T/10) – 5
–
–
T_TMS_setup
TMS setup before TCK high
T/4
–
–
T_TDI_hold
TDI, TMS hold after TCK high
T = 1/f_TCK max
T/4
–
–
T_TDO_valid
TCK low to TDO valid
T = 1/f_TCK max
–
–
2T/5
T_TDO_hold
TDO hold after TCK high
T = 1/f_TCK max
T/4
–
–
Notes
64. Based on device characterization (Not production tested).
65. f_TCK must also be no more than 1/3 CPU clock frequency.
Document Number: 001-56955 Rev. AB
Page 106 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.8.5 SWD Interface
Figure 11-58. SWD Interface Timing
(1/f_SW DCK)
SW DCK
T_SW DI_setup T_SW D I_hold
SW DIO
(PSoC input)
T_SW D O _valid
T_SW DO _hold
SW DIO
(PSoC output)
Table 11-63. SWD Interface AC Specifications[66]
Parameter
f_SWDCK
Description
SWDCLK frequency
Conditions
3.3 V VDDD 5 V
1.71 V VDDD < 3.3 V
1.71 V VDDD < 3.3 V,
SWD over USBIO pins
T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max
T_SWDI_hold SWDIO input hold after SWDCK high
T = 1/f_SWDCK max
T_SWDO_valid SWDCK high to SWDIO output
T = 1/f_SWDCK max
Min
–
–
–
Typ
–
–
–
Max
14[67]
7[67]
5.5[67]
Units
MHz
MHz
MHz
T/4
T/4
–
–
–
–
–
–
2T/5
Min
Typ
Max
Units
–
–
33
Mbit
11.8.6 SWV Interface
Table 11-64. SWV Interface AC Specifications[29]
Parameter
Description
Conditions
SWV mode SWV bit rate
11.9 Clocking
Specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
11.9.1 Internal Main Oscillator
Table 11-65. IMO DC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
Supply current
24 MHz – USB mode
With oscillator locking to USB bus
24 MHz – non USB mode
–
–
500
µA
–
–
300
µA
12 MHz
–
–
200
µA
6 MHz
–
–
180
µA
3 MHz
–
–
150
µA
Notes
66. Based on device characterization (Not production tested).
67. f_SWDCK must also be no more than 1/3 CPU clock frequency.
Document Number: 001-56955 Rev. AB
Page 107 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 11-59. IMO Current vs. Frequency
Table 11-66. IMO AC Specifications
Parameter
Description
Conditions
Min
Typ
Max
Units
–4
–
4
%
IMO frequency stability (with factory trim)
24 MHz – Non USB mode
FIMO
24 MHz – USB mode
–0.25
–
0.25
%
12 MHz
–3
–
3
%
6 MHz
–2
–
2
%
3 MHz
–2
–
2
%
–
–
13
µs
F = 24 MHz
–
0.9
–
ns
F = 3 MHz
–
1.6
–
ns
F = 24 MHz
–
0.9
–
ns
F = 3 MHz
–
12
–
ns
Startup
time[68]
With oscillator locking to USB bus
From enable (during normal system
operation)
Jitter (peak to peak)[68]
Jp-p
Jitter (long term)[68]
Jperiod
Figure 11-60. IMO Frequency Variation vs. Temperature
Figure 11-61. IMO Frequency Variation vs. VCC
Note
68. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. AB
Page 108 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.9.2 Internal Low-Speed Oscillator
Table 11-67. ILO DC Specifications
Parameter
Description
Operating
current[69]
ICC
Conditions
Min
Typ
Max
Units
FOUT = 1 kHz
–
–
1.7
µA
FOUT = 33 kHz
–
–
2.6
µA
FOUT = 100 kHz
–
–
2.6
µA
Power down mode
–
–
15
nA
Min
Typ
Max
Units
–
–
2
ms
100 kHz
45
100
200
kHz
1 kHz
0.5
1
2
kHz
Leakage current[69]
Table 11-68. ILO AC Specifications
Parameter
Description
Startup time, all frequencies
FILO
Conditions
Turbo mode
ILO frequencies
Figure 11-62. ILO Frequency Variation vs. Temperature
Figure 11-63. ILO Frequency Variation vs. VDD
11.9.3 MHz External Crystal Oscillator
For more information on crystal or ceramic resonator selection for the MHzECO, refer to application note AN54439: PSoC 3 and PSoC
5 External Oscillators..
Table 11-69. MHzECO DC Specifications
Parameter
ICC
Description
Operating current[70]
Conditions
13.56 MHz crystal
Min
Typ
Max
Units
–
3.8
–
mA
Min
Typ
Max
Units
4
–
25
MHz
Table 11-70. MHzECO AC Specifications
Parameter
F
Description
Crystal frequency range
Conditions
Notes
69. This value is calculated, not measured.
70. Based on device characterization (Not production tested).
Document Number: 001-56955 Rev. AB
Page 109 of 128
PSoC® 3: CY8C32 Family Data Sheet
11.9.4 kHz External Crystal Oscillator
Table 11-71. kHzECO DC Specifications[71]
Parameter
Description
ICC
Operating current
DL
Drive level
Conditions
Low-power mode; CL = 6 pF
Min
Typ
Max
Units
–
0.25
1.0
µA
–
–
1
µW
Min
Typ
Max
Units
–
32.768
–
kHz
–
1
–
s
Min
Typ
Max
Units
Table 11-72. kHzECO AC Specifications
Parameter
Description
F
Frequency
TON
Startup time
Conditions
High power mode
11.9.5 External Clock Reference
Table 11-73. External Clock Reference AC Specifications[71]
Parameter
Description
Conditions
External frequency range
0
–
33
MHz
Input duty cycle range
Measured at VDDIO/2
30
50
70
%
Input edge rate
VIL to VIH
0.5
–
–
V/ns
Min
Typ
Max
Units
–
200
–
µA
Min
Typ
Max
Units
1
–
48
MHz
1
–
3
MHz
11.9.6 Phase–Locked Loop
Table 11-74. PLL DC Specifications
Parameter
IDD
Description
PLL operating current
Conditions
In = 3 MHz, Out = 24 MHz
Table 11-75. PLL AC Specifications
Parameter
Fpllin
Description
PLL input
PLL intermediate frequency[73]
Fpllout
Conditions
frequency[72]
Output of prescaler
PLL output frequency[72]
24
–
50
MHz
Lock time at startup
–
–
250
µs
(rms)[71]
–
–
250
ps
Jperiod-rms Jitter
Notes
71. Based on device characterization (Not production tested).
72. This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL.
73. PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16.
Document Number: 001-56955 Rev. AB
Page 110 of 128
PSoC® 3: CY8C32 Family Data Sheet
12. Ordering Information
In addition to the features listed in Table 12-1, every CY8C32 device includes: a precision on-chip voltage reference, precision
oscillators, flash, ECC, DMA, a fixed function I2C, 4 KB trace RAM, JTAG/SWD programming and debug, external memory interface,
and more. In addition to these features, the flexible UDBs and analog subsection support a wide range of peripherals. To assist you
in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application.
All CY8C32 derivatives incorporate device and flash security in user-selectable security levels; see the TRM for details.
Table 12-1. CY8C32 Family with Single Cycle 8051
I/O[75]
JTAG ID[76]
USBIO
SIO
GPIO
Total I/O
CAN 2.0b
Package
FS USB
16-bit Timer/PWM
UDBs[74]
CapSense
DFB
SC/CT Analog Blocks
Digital
Comparator
DAC
ADC
LCD Segment Drive
Analog
EEPROM (KB)
SRAM (KB)
Flash (KB)
Part Number
CPU Speed (MHz)
MCU Core
16 KB Flash
CY8C3244AXI-153
50
16
2
0.5
✔
12-bit Del-Sig
1
2
0
–
✔
16
4
–
–
70
62
8
0
100-pin TQFP
0×1E099069
CY8C3244LTI-130
50
16
2
0.5
✔
12-bit Del-Sig
1
2
0
–
✔
16
4
–
–
46
38
8
0
68-pin QFN
0×1E082069
CY8C3244LTI-123
50
16
2
0.5
✔
12-bit Del-Sig
1
2
0
–
✔
16
4
–
–
29
25
4
0
48-pin QFN
0×1E07B069
CY8C3244PVI-133
50
16
2
0.5
✔
12-bit Del-Sig
1
2
0
–
✔
16
4
–
–
29
25
4
0
48-pin SSOP
0×1E085069
32 KB Flash
CY8C3245AXI-158
50
32
4
1
✔
12-bit Del-Sig
1
2
0
–
✔
20
4
–
–
70
62
8
0
100-pin TQFP
0×1E09E069
CY8C3245LTI-163
50
32
4
1
✔
12-bit Del-Sig
1
2
0
–
✔
20
4
–
–
46
38
8
0
68-pin QFN
0×1E0A3069
0×1E08B069
CY8C3245LTI-139
50
32
4
1
✔
12-bit Del-Sig
1
2
0
–
✔
20
4
–
–
29
25
4
0
48-pin QFN
CY8C3245PVI-134
50
32
4
1
✔
12-bit Del-Sig
1
2
0
–
✔
20
4
–
–
29
25
4
0
48-pin SSOP
0×1E086069
CY8C3245AXI-166
50
32
4
1
✔
12-bit Del-Sig
1
2
0
–
✔
20
4
✔
–
72
62
8
2
100-pin TQFP
0×1E0A6069
0×1E090069
CY8C3245LTI-144
50
32
4
1
✔
12-bit Del-Sig
1
2
0
–
✔
20
4
✔
–
31
25
4
2
48-pin QFN
CY8C3245PVI-150
50
32
4
1
✔
12-bit Del-Sig
1
2
0
–
✔
20
4
✔
–
31
25
4
2
48-pin SSOP
0×1E096069
CY8C3245FNI-212
50
32
4
1
✔
12-bit Del-Sig
1
2
0
–
✔
20
4
–
–
46
38
8
0
72-pin WLCSP
0x1E0D4069
0×1E095069
64 KB Flash
CY8C3246LTI-149
50
64
8
2
✔
12-bit Del-Sig
1
2
0
–
✔
24
4
–
–
46
38
8
0
68-pin QFN
CY8C3246PVI-147
50
64
8
2
✔
12-bit Del-Sig
1
2
0
–
✔
24
4
✔
–
31
25
4
2
48-pin SSOP
0×1E093069
CY8C3246AXI-131
50
64
8
2
✔
12-bit Del-Sig
1
2
0
–
✔
24
4
–
–
70
62
8
0
100-pin TQFP
0×1E083069
0×1E0A2069
CY8C3246LTI-162
50
64
8
2
✔
12-bit Del-Sig
1
2
0
–
✔
24
4
–
–
29
25
4
0
48-pin QFN
CY8C3246PVI-122
50
64
8
2
✔
12-bit Del-Sig
1
2
0
–
✔
24
4
–
–
29
25
4
0
48-pin SSOP
0×1E07A069
CY8C3246AXI-138
50
64
8
2
✔
12-bit Del-Sig
1
2
0
–
✔
24
4
✔
–
72
62
8
2
100-pin TQFP
0×1E08A069
CY8C3246LTI-128
50
64
8
2
✔
12-bit Del-Sig
1
2
0
–
✔
24
4
✔
–
48
38
8
2
68-pin QFN
0×1E080069
CY8C3246LTI-125
50
64
8
2
✔
12-bit Del-Sig
1
2
0
–
✔
24
4
✔
–
31
25
4
2
48-pin QFN
0×1E07D069
CY8C3246FNI-213
50
64
8
2
✔
12-bit Del-Sig
1
2
–
–
✔
24
4
–
–
46
38
8
–
72-pin WLCSP
0x1E0D5069
Notes
74. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or
multiple UDBs. Multiple functions can share a single UDB. See the Example Peripherals on page 45 for more information on how UDBs can be used.
75. The I/O Count includes all types of digital I/O: GPIO, SIO, and the two USB I/O. See the I/O System and Routing on page 37 for details on the functionality of each of
these types of I/O.
76. The JTAG ID has three major fields. The most significant nibble (left digit) is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID.
Document Number: 001-56955 Rev. AB
Page 111 of 128
PSoC® 3: CY8C32 Family Data Sheet
12.1 Part Numbering Conventions
PSoC 3 devices follow the part numbering convention described here. All fields are single character alphanumeric (0, 1, 2, …, 9, A,
B, …, Z) unless stated otherwise.
CY8Cabcdefg-xxx
a: Architecture
ef: Package code
3: PSoC 3
5: PSoC 5
Two character alphanumeric
AX: TQFP
LT: QFN
PV: SSOP
FN: CSP
b: Family group within architecture
2: CY8C32 family
4: CY8C34 family
6: CY8C36 family
8: CY8C38 family
g: Temperature range
C: commercial
I: industrial
A: automotive
c: Speed grade
4: 50 MHz
6: 67 MHz
xxx: Peripheral set
d: Flash capacity
4: 16 KB
5: 32 KB
6: 64 KB
Three character numeric
No meaning is associated with these three characters.
Example
CY8C
3 2 4 6 P V
I
-
x x x
Cypress Prefix
3: PSoC 3
2: CY8C32 Family
Architecture
Family Group within Architecture
4: 50 MHz
Speed Grade
6: 64 KB
Flash Capacity
PV: SSOP
Package Code
I: Industrial
Temperature Range
Peripheral Set
Tape and reel versions of these devices are available and are marked with a "T" at the end of the part number.
All devices in the PSoC 3 CY8C32 family comply to RoHS-6 specifications, demonstrating the commitment by Cypress to lead-free
products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress
uses nickel-palladium-gold (NiPdAu) technology for the majority of leadframe-based packages.
A high level review of the Cypress Pb-free position is available on our website. Specific package information is also available. Package
Material Declaration Datasheets (PMDDs) identify all substances contained within Cypress packages. PMDDs also confirm the
absence of many banned substances. The information in the PMDDs will help Cypress customers plan for recycling or other “end of
life” requirements.
Document Number: 001-56955 Rev. AB
Page 112 of 128
PSoC® 3: CY8C32 Family Data Sheet
13. Packaging
Table 13-1. Package Characteristics
Parameter
Description
Conditions
Min
Typ
Max
Units
TA
Operating ambient temperature
–40
25.00
85
°C
TJ
Operating junction temperature
–40
–
100
°C
TJA
Package JA (48-pin SSOP)
–
49
–
°C/Watt
TJA
Package JA (48-pin QFN)
–
14
–
°C/Watt
TJA
Package JA (68-pin QFN)
–
15
–
°C/Watt
TJA
Package JA (100-pin TQFP)
–
34
–
°C/Watt
TJC
Package JC (48-pin SSOP)
–
24
–
°C/Watt
TJC
Package JC (48-pin QFN)
–
15
–
°C/Watt
TJC
Package JC (68-pin QFN)
–
13
–
°C/Watt
TJC
Package JC (100-pin TQFP)
–
10
–
°C/Watt
TJA
Package JA (72-pin CSP)
–
18
–
°C/Watt
TJC
Package JC (72-pin CSP)
–
0.13
–
°C/Watt
Table 13-2. Solder Reflow Peak Temperature
Package
Maximum Peak
Temperature
Maximum Time at Peak
Temperature
48-pin SSOP
260 °C
30 seconds
48-pin QFN
260 °C
30 seconds
68-pin QFN
260 °C
30 seconds
100-pin TQFP
260 °C
30 seconds
72-pin CSP
260 °C
30 seconds
Table 13-3. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
48-pin SSOP
MSL 3
48-pin QFN
MSL 3
68-pin QFN
MSL 3
100-pin TQFP
MSL 3
72-pin CSP
MSL 1
Document Number: 001-56955 Rev. AB
Page 113 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 13-1. 48-pin (300 mil) SSOP Package Outline
51-85061 *F
Figure 13-2. 48-pin QFN Package Outline
001-45616 *F
Document Number: 001-56955 Rev. AB
Page 114 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 13-3. 68-pin QFN 8×8 with 0.4 mm Pitch Package Outline (Sawn Version)
001-09618 *E
Figure 13-4. 100-pin TQFP (14 × 14 × 1.4 mm) Package Outline
51-85048 *K
Document Number: 001-56955 Rev. AB
Page 115 of 128
PSoC® 3: CY8C32 Family Data Sheet
Figure 13-5. WLCSP Package (4.25 × 4.98 × 0.60 mm)
TOP VIEW
1
2
3
4
5
6
7
SIDE VIEW
8
A
BOTTOM VIEW
8
7
6
5
4
3
2
1
A
B
B
C
C
D
D
E
E
F
F
G
G
H
H
J
J
NOTES:
1. JEDEC Publication 95; Design Guide 4.18
2. ALL DIMENSIONS ARE IN MILLIMETERS
Document Number: 001-56955 Rev. AB
001-82897 **
Page 116 of 128
PSoC® 3: CY8C32 Family Data Sheet
14. Acronyms
Table 14-1. Acronyms Used in this Document (continued)
Table 14-1. Acronyms Used in this Document
Acronym
Description
abus
analog local bus
ADC
analog-to-digital converter
AG
analog global
AHB
AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data
transfer bus
Acronym
Description
FIR
finite impulse response, see also IIR
FPB
flash patch and breakpoint
FS
full-speed
GPIO
general-purpose input/output, applies to a PSoC
pin
HVI
high-voltage interrupt, see also LVI, LVD
IC
integrated circuit
ALU
arithmetic logic unit
IDAC
current DAC, see also DAC, VDAC
AMUXBUS
analog multiplexer bus
IDE
integrated development environment
API
application programming interface
I2C, or IIC
APSR
application program status register
Inter-Integrated Circuit, a communications
protocol
ARM®
advanced RISC machine, a CPU architecture
IIR
infinite impulse response, see also FIR
ATM
automatic thump mode
ILO
internal low-speed oscillator, see also IMO
BW
bandwidth
IMO
internal main oscillator, see also ILO
CAN
Controller Area Network, a communications
protocol
CMRR
INL
integral nonlinearity, see also DNL
I/O
input/output, see also GPIO, DIO, SIO, USBIO
common-mode rejection ratio
IPOR
initial power-on reset
CPU
central processing unit
IPSR
interrupt program status register
CRC
cyclic redundancy check, an error-checking
protocol
IRQ
interrupt request
ITM
instrumentation trace macrocell
LCD
liquid crystal display
LIN
Local Interconnect Network, a communications
protocol.
LR
link register
LUT
lookup table
LVD
low-voltage detect, see also LVI
LVI
low-voltage interrupt, see also HVI
LVTTL
low-voltage transistor-transistor logic
MAC
multiply-accumulate
DAC
digital-to-analog converter, see also IDAC, VDAC
DFB
digital filter block
DIO
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
DMA
direct memory access, see also TD
DNL
differential nonlinearity, see also INL
DNU
do not use
DR
port write data registers
DSI
digital system interconnect
DWT
data watchpoint and trace
ECC
error correcting code
ECO
external crystal oscillator
EEPROM
electrically erasable programmable read-only
memory
EMI
electromagnetic interference
EMIF
external memory interface
EOC
end of conversion
EOF
end of frame
EPSR
execution program status register
ESD
electrostatic discharge
ETM
embedded trace macrocell
Document Number: 001-56955 Rev. AB
MCU
microcontroller unit
MISO
master-in slave-out
NC
no connect
NMI
nonmaskable interrupt
NRZ
non-return-to-zero
NVIC
nested vectored interrupt controller
NVL
nonvolatile latch, see also WOL
opamp
operational amplifier
PAL
programmable array logic, see also PLD
PC
program counter
PCB
printed circuit board
PGA
programmable gain amplifier
Page 117 of 128
PSoC® 3: CY8C32 Family Data Sheet
Table 14-1. Acronyms Used in this Document (continued)
Acronym
Description
Table 14-1. Acronyms Used in this Document (continued)
Acronym
Description
PHUB
peripheral hub
SOF
start of frame
PHY
physical layer
SPI
PICU
port interrupt control unit
Serial Peripheral Interface, a communications
protocol
PLA
programmable logic array
SR
slew rate
PLD
programmable logic device, see also PAL
SRAM
static random access memory
PLL
phase-locked loop
SRES
software reset
PMDD
package material declaration datasheet
SWD
serial wire debug, a test protocol
POR
power-on reset
PRES
precise low-voltage reset
PRS
pseudo random sequence
PS
port read data register
PSoC®
Programmable System-on-Chip™
SWV
single-wire viewer
TD
transaction descriptor, see also DMA
THD
total harmonic distortion
TIA
transimpedance amplifier
TRM
technical reference manual
TTL
transistor-transistor logic
TX
transmit
UART
Universal Asynchronous Transmitter Receiver, a
communications protocol
UDB
universal digital block
USB
Universal Serial Bus
USBIO
USB input/output, PSoC pins used to connect to
a USB port
voltage DAC, see also DAC, IDAC
PSRR
power supply rejection ratio
PWM
pulse-width modulator
RAM
random-access memory
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
RTL
register transfer language
RTR
remote transmission request
VDAC
RX
receive
WDT
watchdog timer
SAR
successive approximation register
WOL
write once latch, see also NVL
SC/CT
switched capacitor/continuous time
WRES
watchdog timer reset
SCL
I2C
serial clock
XRES
external reset I/O pin
SDA
I2C
serial data
XTAL
crystal
S/H
sample and hold
SINAD
signal to noise and distortion ratio
SIO
special input/output, GPIO with advanced
features. See GPIO.
SOC
start of conversion
Document Number: 001-56955 Rev. AB
15. Reference Documents
PSoC® 3, PSoC® 5 Architecture TRM
PSoC® 3 Registers TRM
Page 118 of 128
PSoC® 3: CY8C32 Family Data Sheet
16. Document Conventions
Table 16-1. Units of Measure (continued)
Symbol
16.1 Units of Measure
Table 16-1. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
dB
decibels
fF
femtofarads
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohours
kHz
kilohertz
k
kilohms
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
M
megaohms
Msps
megasamples per second
µA
microamperes
Document Number: 001-56955 Rev. AB
Unit of Measure
µF
microfarads
µH
microhenrys
µs
microseconds
µV
microvolts
µW
microwatts
mA
milliamperes
ms
milliseconds
mV
millivolts
nA
nanoamperes
ns
nanoseconds
nV
nanovolts
ohms
pF
picofarads
ppm
parts per million
ps
picoseconds
s
seconds
sps
samples per second
sqrtHz
square root of hertz
V
volts
Page 119 of 128
PSoC® 3: CY8C32 Family Data Sheet
17. Revision History
Description Title: PSoC® 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC®)
Document Number: 001-56955
Submission
Revision
ECN
Description of Change
Date
**
2796903
11/04/09 New datasheet
*A
2824546
12/09/09 Updated I2C section to reflect 1 Mbps. Updated Table 11-6 and 11- 7 (Boost AC and DC specs);
also added Shottky Diode specs. Changed current for sleep/hibernate mode to include SIO;
Added footnote to analog global specs.
Updated Figures 1-1, 6-2, 7-14, and 8-1. Updated Table 6-2 and Table 6-3 (Hibernate and
Sleep rows) and Power Modes section. Updated GPIO and SIO AC specifications. Updated
Gain error in IDAC and VDAC specifications. Updated description of VDDA spec in Table 11-1
and removed GPIO Clamp Current parameter. Updated number of UDBs on page 1.
Moved FILO from ILO DC to AC table.
Added PCB Layout and PCB Schematic diagrams.
Updated Fgpioout spec (Table 11-9). Added duty cycle frequency in PLL AC spec table. Added
note for Sleep and Hibernate modes and Active Mode specs in Table 11-2. Linked URL in
Section 10.3 to PSoC Creator site.
Updated Ja and Jc values in Table 13-1. Updated Single Sample Mode and Fast FIR Mode
sections. Updated Input Resistance specification in Del-Sig ADC table. Added Tio_init
parameter. Updated PGA and UGB AC Specs. Removed SPC ADC. Updated Boost Converter
section.
Added section 'SIO as Comparator'; updated Hysteresis spec (differential mode) in Table
11-10.
Updated VBAT condition and deleted Vstart parameter in Table 11-6.
Added 'Bytes' column for Tables 4-1 to 4-5.
*B
2873322
02/04/10 Changed maximum value of PPOR_TR to '1'. Updated VBIAS specification. Updated PCB
Schematic. Updated Figure 8-1 and Figure 6-3. Updated Interrupt Vector table, Updated Sales
links. Updated JTAG and SWD specifications. Removed Jp-p and Jperiod from ECO AC Spec
table. Added note on sleep timer in Table 11-2. Updated ILO AC and DC specifications. Added
Resolution parameter in VDAC and IDAC tables. Updated IOUT typical and maximum values.
Changed Temperature Sensor range to –40 °C to +85 °C. Removed Latchup specification from
Table 11-1. Updated DAC details
Document Number: 001-56955 Rev. AB
Page 120 of 128
PSoC® 3: CY8C32 Family Data Sheet
Description Title: PSoC® 3: CY8C32 Family Data Sheet Programmable System-on-Chip (PSoC®) (continued)
Document Number: 001-56955
Submission
Revision
ECN
Description of Change
Date
*C
2903576
04/01/10 Updated Vb pin in PCB Schematic.
Updated Tstartup parameter in AC Specifications table.
Added Load regulation and Line regulation parameters to Inductive Boost Regulator DC Specifications table.
Updated ICC parameter in LCD Direct Drive DC Specs table.
In page 1, updated internal oscillator range under Prescision programmable clocking to start
from 3 MHz.
Updated IOUT parameter in LCD Direct Drive DC Specs table.
Updated Table 6-2 and Table 6-3.
Added bullets on CapSense in page 1; added CapSense column in Section 12
Removed some references to footnote [1].
Changed INC_Rn cycles from 3 to 2 (Table 4-1).
Added footnote in PLL AC Specification table.
Added PLL intermediate frequency row with footnote in PLL AC Specs table.
Added UDBs subsection under 11.6 Digital Peripherals.
Updated Figure 2-6 (PCB Layout).
Updated Pin Descriptions section and modified Figures 6-6, 6-8, 6-9.
Updated LVD in Tables 6-2 and 6-3; modified Low-power modes bullet in page 1.
Added note to Figures 2-5 and 6-2; Updated Figure 6-2 to add capacitors for VDDA and VDDD
pins.
Updated boost converter section (6.2.2).
Updated Tstartup values in Table 11-3.
Removed IPOR rows from Table 11-53. Updated 6.3.1.1, Power Voltage Level Monitors.
Updated section 5.2 and Table 11-2 to correct suggestion of execution from flash.
Updated IMO max frequency in Figure 6-1, Table 11-63, and Table 11-64.
Updated VREF specs in Table 11-19.
Updated IDAC uncompensated gain error in Table 11-23.
Updated Delay from Interrupt signal input to ISR code execution from ISR code in Table-71.
Removed other line in table.
Added sentence to last paragraph of section 6.1.1.3.
Updated Tresp, high and low-power modes, in Table 11-22.
Updated f_TCK values in Table 11-58 and f_SWDCK values in Table 11-59.
Updated SNR condition in Table 11-18.
Updated sleep wakeup time in Table 6-3 and Tsleep in Table 11-3.
Added 1.71 V
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