CY8C3445AXE-097

PSoC® 3: CY8C34 Automotive Family Datasheet Programmable System-on-Chip (PSoC®) General Description With its unique array of configurable blocks, PSoC® 3 is a true system level solution providing microcontroller unit (MCU), memory, analog, and digital peripheral functions in a single chip while being AEC-Q100 compliant. The CY8C34 family offers a modern method of signal acquisition, signal processing, and control with high accuracy, high bandwidth, and high flexibility. Analog capability spans the range from thermocouples (near DC voltages) to ultrasonic signals. The CY8C34 family can handle dozens of data acquisition channels and analog inputs on every general-purpose input/output (GPIO) pin. The CY8C34 family is also a high-performance configurable digital system with some part numbers including interfaces such as USB, multimaster inter-integrated circuit (I2C), and controller area network (CAN). In addition to communication interfaces, the CY8C34 family has an easy to configure logic array, flexible routing to all I/O pins, and a high-performance single cycle 8051 microprocessor core. You can easily create system-level designs using a rich library of prebuilt components and boolean primitives using PSoC Creator™, a hierarchical schematic design entry tool. The CY8C34 family provides unparalleled opportunities for analog and digital bill of materials integration while easily accommodating last minute design changes through simple firmware updates. Features  Single cycle 8051 CPU DC to 50 MHz operation Multiply and divide instructions  Flash program memory, up to 64 KB, 100,000 write cycles, 20 years retention, and multiple security features  512-byte flash cache  Up to 8-KB flash error correcting code (ECC) or configuration storage  Up to 8 KB SRAM  Up to 2 KB electrically erasable programmable read-only memory (EEPROM), 1 M cycles, and 20 years retention  24-channel direct memory access (DMA) with multilayer AHB[1] bus access • Programmable chained descriptors and priorities • High bandwidth 32-bit transfer support  Low voltage, ultra low-power  Wide operating voltage range: 1.71 V to 5.5 V  0.8 mA at 3 MHz, 1.2 mA at 6 MHz, and 6.6 mA at 50 MHz  Low-power modes including: • 1-µA sleep mode with real time clock and low-voltage detect (LVD) interrupt • 200-nA hibernate mode with RAM retention  Versatile I/O system  29 to 72 I/O (62 GPIOs, eight special input/outputs (SIO), two USBIOs[2])  Any GPIO to any digital or analog peripheral routability [2]  LCD direct drive from any GPIO, up to 46 × 16 segments ® [3]  CapSense support from any GPIO  1.2-V to 5.5-V I/O interface voltages, up to four domains  Maskable, independent IRQ on any pin or port  Schmitt-trigger transistor-transistor logic (TTL) inputs  All GPIO configurable as open drain high/low, pull-up/ pull-down, High Z, or strong output  Configurable GPIO pin state at power-on reset (POR)  25 mA sink on SIO  Digital peripherals  16 to 24 programmable logic device (PLD) based universal digital blocks (UDB) [2]  Full CAN 2.0b 16 Rx, 8 Tx buffers  USB 2.0 certified Full-Speed (FS) 12 Mbps peripheral interface (TID#40770053) using internal oscillator[2]  Up to four 16-bit configurable timer, counter, and PWM blocks  Library of standard peripherals   • 8-, 16-, 24-, and 32-bit timers, counters, and PWMs • Serial peripheral interface (SPI), universal asynchronous transmitter receiver (UART), and I2C • Many others available in catalog  Library of advanced peripherals • Cyclic redundancy check (CRC) • Pseudo random sequence (PRS) generator • Local interconnect network (LIN) bus 2.0 • Quadrature decoder  Analog peripherals (1.71 V  VDDA  5.5 V)  1.024 V ± 0.1% internal voltage reference across –40 °C to +85 °C  Configurable delta-sigma ADC with 8- to 12-bit resolution • Sample rates up to 192 ksps • Programmable gain stage: ×0.25 to ×16 • 12-bit mode, 192 ksps, 66-dB signal to noise and distortion ratio (SINAD), ±1-bit INL/DNL  Up to four 8-bit, 8-Msps IDACs or 1-Msps VDACs  Four comparators with 95-ns response time  Two uncommitted opamps with 25-mA drive capability  Two configurable multifunction analog blocks. Example configurations are programmable gain amplifier (PGA), transimpedance amplifier (TIA), mixer, and sample and hold  CapSense support  Programming, debug, and trace  JTAG (4-wire), serial wire debug (SWD) (2-wire), and single wire viewer (SWV) interfaces  Eight address and one data breakpoint  4-KB instruction trace buffer 2  Bootloader programming supportable through I C, SPI, UART, USB, and other interfaces  Precision, programmable clocking  3- to 62-MHz internal oscillator over full temperature and voltage range  4- to 25-MHz crystal oscillator for crystal PPM accuracy  Internal PLL clock generation up to 50 MHz  32.768-kHz watch crystal oscillator  Low-power internal oscillator at 1, 33, and 100 kHz  Temperature and packaging  –40 °C to +85 °C degrees automotive temperature  –40 °C to +125 °C Extended temperature range  48-pin SSOP, and 100-pin TQFP package options  AEC-Q100 compliant. Notes 1. AHB – AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus 2. This feature on select devices only. See Ordering Information on page 133 for details. 3. GPIOs with opamp outputs are not recommended for use with CapSense. Cypress Semiconductor Corporation Document Number: 001-57331 Rev. *G • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised February 14, 2014 PSoC® 3: CY8C34 Automotive Family Datasheet Contents 1. Architectural Overview ..................................................3 2. Pinouts ............................................................................5 3. Pin Descriptions .............................................................9 4. CPU ................................................................................10 4.1 8051 CPU ..............................................................10 4.2 Addressing Modes .................................................10 4.3 Instruction Set .......................................................10 4.4 DMA and PHUB ....................................................15 4.5 Interrupt Controller ................................................17 5. Memory ..........................................................................21 5.1 Static RAM ............................................................21 5.2 Flash Program Memory .........................................21 5.3 Flash Security ........................................................21 5.4 EEPROM ...............................................................21 5.5 Nonvolatile Latches (NVLs) ...................................22 5.6 External Memory Interface ....................................23 5.7 Memory Map .........................................................24 6. System Integration .......................................................26 6.1 Clocking System ....................................................26 6.2 Power System .......................................................29 6.3 Reset .....................................................................31 6.4 I/O System and Routing ........................................33 7. Digital Subsystem ........................................................40 7.1 Example Peripherals .............................................40 7.2 Universal Digital Block ...........................................42 7.3 UDB Array Description ..........................................45 7.4 DSI Routing Interface Description .........................45 7.5 CAN .......................................................................47 7.6 USB .......................................................................49 7.7 Timers, Counters, and PWMs ...............................49 7.8 I2C .........................................................................50 8. Analog Subsystem .......................................................51 8.1 Analog Routing ......................................................52 8.2 Delta-sigma ADC ...................................................54 8.3 Comparators ..........................................................55 8.4 Opamps .................................................................56 8.5 Programmable SC/CT Blocks ...............................56 8.6 LCD Direct Drive ...................................................57 Document Number: 001-57331 Rev. *G 8.7 CapSense ..............................................................58 8.8 Temp Sensor .........................................................58 8.9 DAC .......................................................................59 8.10 Up/Down Mixer ....................................................59 8.11 Sample and Hold .................................................59 9. Programming, Debug Interfaces, Resources .............60 9.1 JTAG Interface ......................................................60 9.2 Serial Wire Debug Interface ..................................62 9.3 Debug Features .....................................................63 9.4 Trace Features ......................................................63 9.5 Single Wire Viewer Interface .................................63 9.6 Programming Features ..........................................63 9.7 Device Security .....................................................63 10. Development Support ................................................64 10.1 Documentation ....................................................64 10.2 Online ..................................................................64 10.3 Tools ....................................................................64 11. Electrical Specifications ............................................65 11.1 Absolute Maximum Ratings .................................65 11.2 Device Level Specifications .................................66 11.3 Power Regulators ................................................72 11.4 Inputs and Outputs ..............................................74 11.5 Analog Peripherals ..............................................85 11.6 Digital Peripherals .............................................113 11.7 Memory .............................................................119 11.8 PSoC System Resources ..................................125 11.9 Clocking .............................................................128 12. Ordering Information ................................................133 12.1 Part Numbering Conventions ............................134 13. Packaging ..................................................................135 14. Acronyms ..................................................................137 15. Reference Documents ..............................................138 16. Document Conventions ...........................................139 16.1 Units of Measure ...............................................139 17. Revision History .......................................................140 18. Sales, Solutions, and Legal Information ................143 Page 2 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 1. Architectural Overview Introducing the CY8C34 family of ultra low-power, flash Programmable System-on-Chip (PSoC®) devices, part of a scalable 8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C34 family provides configurable blocks of analog, digital, and interconnect circuitry around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables a high level of integration in a wide variety of automotive consumer, industrial, and medical applications. Figure 1-1. Simplified Block Diagram Analog Interconnect Quadrature Decoder UDB Sequencer Usage Example for UDB IMO Universal Digital Block Array (24 x UDB) 8-bit Timer UDB UDB UDB 16-bit PWM UDB UDB UDB UDB UDB UDB UDB UDB UDB UDB Master/ Slave 22  12-bit SPI UDB UDB UDB UDB 8-bit Timer UDB 8-bit SPI I 2C Slave UDB I2C CAN 2.0 16-bit PRS UDB Logic UDB FS USB 2.0 4x Timer Counter PWM Logic UDB UART UDB USB PHY GPIOs GPIOs Clock Tree 32.768 KHz (Optional) Digital System System Wide Resources Xtal Osc SIO 4 to 25 MHz (Optional) GPIOs Digital Interconnect 12- bit PWM RTC Timer System Bus Memory System EEPROM SRAM CPU System 8051 Interrupt Controller Program & Debug Program GPIOs WDT and Wake GPIOs Debug & Trace EMIF PHUB DMA FLASH ILO Boundary Scan Power Management System Analog System LCD Direct Drive ADC POR and LVD 1.8V LDO 2 x SC/CT Blocks (TIA, PGA, Mixer etc) Temperature Sensor CapSense Figure 1-1 illustrates the major components of the CY8C34 family. They are:  8051 CPU subsystem  Nonvolatile subsystem  Programming, debug, and test subsystem  Inputs and outputs  Clocking  Power  Digital subsystem  Analog subsystem Document Number: 001-57331 Rev. *G + 2x Opamp - 2 x DAC Del Sig ADC 3 per Opamp + 4x CMP - GPIOs 1.71 V to 5.5 V Sleep Power GPIOs SIOs Clocking System PSoC’s digital subsystem provides half of its unique configurability. It connects a digital signal from any peripheral to any pin through the digital system interconnect (DSI). It also provides functional flexibility through an array of small, fast, low-power UDBs. PSoC Creator provides a library of prebuilt and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR, and so on) that are mapped to the UDB array. You can also easily create a digital circuit using boolean primitives by means of graphical design entry. Each UDB contains programmable array logic (PAL)/programmable logic device (PLD) functionality, together with a small state machine engine to support a wide variety of peripherals. In addition to the flexibility of the UDB array, PSoC also provides configurable digital blocks targeted at specific functions. For the CY8C34 family these blocks can include four 16-bit timers, counters, and PWM blocks; I2C slave, master, and multimaster; FS USB; and Full CAN 2.0b. Page 3 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet For more details on the peripherals see the “Example Peripherals” section on page 40 of this data sheet. For information on UDBs, DSI, and other digital blocks, see the “Digital Subsystem” section on page 40 of this data sheet. PSoC’s analog subsystem is the second half of its unique configurability. All analog performance is based on a highly accurate absolute voltage reference with less than 0.1-percent error over temperature and voltage. The configurable analog subsystem includes:  Analog muxes  Comparators  Voltage references  Analog-to-digital converter (ADC)  Digital-to-analog converters (DACs) All GPIO pins can route analog signals into and out of the device using the internal analog bus. This allows the device to interface up to 62 discrete analog signals. The heart of the analog subsystem is a fast, accurate, configurable delta-sigma ADC with these features [4]:  Less than 100 µV offset  A gain error of 0.2 percent  INL less than ±2 LSB  DNL less than ±1 LSB  SINAD better than 84 dB in 16-bit mode This converter addresses a wide variety of precision analog applications, including some of the most demanding sensors. Two high-speed voltage or current DACs support 8-bit output signals at an update rate of up to 8 Msps. They can be routed out of any GPIO pin. You can create higher resolution voltage PWM DAC outputs using the UDB array. This can be used to create a pulse width modulated (PWM) DAC of up to 10 bits, at up to 48 kHz. The digital DACs in each UDB support PWM, PRS, or delta-sigma algorithms with programmable widths. In addition to the ADC, and DACs, the analog subsystem provides multiple:  Uncommitted opamps  Configurable switched capacitor/continuous time (SC/CT) blocks. These support:  Transimpedance amplifiers  Programmable gain amplifiers  Mixers  Other similar analog components See the “Analog Subsystem” section on page 51 of this data sheet for more details. PSoC’s 8051 CPU subsystem is built around a single cycle pipelined 8051 8-bit processor running at up to 50 MHz. The CPU subsystem includes a programmable nested vector interrupt controller, DMA controller, and RAM. PSoC’s nested vector interrupt controller provides low latency by allowing the CPU to vector directly to the first address of the interrupt service routine, bypassing the jump instruction required by other architectures. The DMA controller enables peripherals to exchange data without CPU involvement. This allows the CPU to run slower (saving power) or use those CPU cycles to improve the performance of firmware algorithms. The single cycle 8051 CPU runs ten times faster than a standard 8051 processor. The processor speed itself is configurable, allowing you to tune active power consumption for specific applications. PSoC’s nonvolatile subsystem consists of flash, byte-writeable EEPROM, and nonvolatile configuration options. It provides up to 64 KB of on-chip flash. The CPU can reprogram individual blocks of flash, enabling bootloaders. You can enable an error correcting code (ECC) for high reliability applications. A powerful and flexible protection model secures the user's sensitive information, allowing selective memory block locking for read and write protection. Up to 2 KB of byte-writeable EEPROM is available on-chip to store application data. Additionally, selected configuration options such as boot speed and pin drive mode are stored in nonvolatile memory. This allows settings to activate immediately after POR. The three types of PSoC I/O are extremely flexible. All I/Os have many drive modes that are set at POR. PSoC also provides up to four I/O voltage domains through the VDDIO pins. Every GPIO has analog I/O, LCD drive[5], CapSense[6], flexible interrupt generation, slew rate control, and digital I/O capability. The SIOs on PSoC allow VOH to be set independently of Vddio when used as outputs. When SIOs are in input mode they are high impedance. This is true even when the device is not powered or when the pin voltage goes above the supply voltage. This makes the SIO ideally suited for use on an I2C bus where the PSoC may not be powered when other devices on the bus are. The SIO pins also have high current sink capability for applications such as LED drives. The programmable input threshold feature of the SIO can be used to make the SIO function as a general purpose analog comparator. For devices with Full-Speed USB the USB physical interface is also provided (USBIO). When not using USB these pins may also be used for limited digital functionality and device programming. All of the features of the PSoC I/Os are covered in detail in the “I/O System and Routing” section on page 33 of this data sheet. The PSoC device incorporates flexible internal clock generators, designed for high stability and factory trimmed for high accuracy. The internal main oscillator (IMO) is the clock base for the system, and has 1-percent accuracy at 3 MHz. The IMO can be configured to run from 3 MHz up to 62 MHz. Multiple clock derivatives can be generated from the main clock frequency to meet application needs. The device provides a PLL to generate clock frequencies up to 50 MHz from the IMO, external crystal, or external reference clock. Notes 4. Refer Electrical Specifications on page 65 for the detailed ADC specification across entire voltage range and temperature 5. This feature on select devices only. See Ordering Information on page 133 for details. 6. GPIOs with opamp outputs are not recommended for use with CapSense. Document Number: 001-57331 Rev. *G Page 4 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet It also contains a separate, very low-power internal low-speed oscillator (ILO) for the sleep and watchdog timers. A 32.768-kHz external watch crystal is also supported for use in real-time clock (RTC) applications. The clocks, together with programmable clock dividers, provide the flexibility to integrate most timing requirements. The CY8C34 family supports a wide supply operating range from 1.71 V to 5.5 V. This allows operation from regulated supplies such as 1.8 V ± 5%, 2.5 V ±10%, 3.3 V ± 10%, or 5.0 V ± 10%, or directly from a wide range of battery types. PSoC supports a wide range of low-power modes. These include a 200-nA hibernate mode with RAM retention and a 1-µA sleep mode with RTC. In the second mode, the optional 32.768-kHz watch crystal runs continuously and maintains an accurate RTC. Power to all major functional blocks, including the programmable digital and analog peripherals, can be controlled independently by firmware. This allows low-power background processing when some peripherals are not in use. This, in turn, provides a total device current of only 1.2 mA when the CPU is running at 6 MHz, or 0.8 mA running at 3 MHz. 2. Pinouts Each VDDIO pin powers a specific set of I/O pins. (The USBIOs are powered from VDDD.) Using the VDDIO pins, a single PSoC can support multiple voltage levels, reducing the need for off-chip level shifters. The black lines drawn on the pinout diagrams in Figure 2-3 through Figure 2-4 show the pins that are powered by each VDDIO. Each VDDIO may source up to 100 mA [7] total to its associated I/O pins, as shown in Figure 2-1. Figure 2-1. VDDIO Current Limit IDDIO X = 100 mA VDDIO X I/O Pins PSoC The details of the PSoC power modes are covered in the “Power System” section on page 29 of this data sheet. PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for programming, debug, and test. The 1-wire SWV may also be used for ‘printf’ style debugging. By combining SWD and SWV, you can implement a full debugging interface with just three pins. Using these standard interfaces you can debug or program the PSoC with a variety of hardware solutions from Cypress or third party vendors. PSoC supports on-chip break points and 4-KB instruction and data race memory for debug. Details of the programming, test, and debugging interfaces are discussed in the “Programming, Debug Interfaces, Resources” section on page 60 of this data sheet. Conversely, for the 100-pin and 68-pin devices, the set of I/O pins associated with any VDDIO may sink up to 100 mA [7] total, as shown in Figure 2-2. Figure 2-2. I/O Pins Current Limit Ipins = 100 mA VDDIO X I/O Pins PSoC VSSD For the 48-pin devices, the set of I/O pins associated with VDDIO0 plus VDDIO2 may sink up to 100 mA [7] total. The set of I/O pins associated with VDDIO1 plus VDDIO3 may sink up to a total of 100 mA. Note 7. The 100 mA source/ sink current per Vddio is valid only for temperature range of –40 °C to +85 °C. For extended temperature range of –40 °C to +125 °C, the maximum source or sink current per Vddio is 40 mA. Document Number: 001-57331 Rev. *G Page 5 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 2-3. 48-pin SSOP Part Pinout (SIO) P12[2] (SIO) P12[3] (Opamp2OUT, GPIO) P0[0] (Opamp0OUT, GPIO) P0[1] (Opamp0+, GPIO) P0[2] (Opamp0-/Extref0, GPIO) P0[3] VDDIO0 (Opamp2+, GPIO) P0[4] (Opamp2-, GPIO) P0[5] (IDAC0, GPIO) P0[6] (IDAC2, GPIO) P0[7] VCCD VSSD VDDD (GPIO) P2[3] (GPIO) P2[4] VDDIO2 (GPIO) P2[5] (GPIO) P2[6] (GPIO) P2[7] VSSD NC VSSD VSSD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 Lines show 46 VDDIO to I/O 45 supply association 44 43 42 41 40 39 38 37 SSOP 36 35 34 33 32 31 30 29 28 27 26 25 VDDA VSSA VCCA P15[3] (GPIO, KHZ XTAL: XI) P15[2] (GPIO, KHZ XTAL: XO) P12[1] (SIO, I2C1: SDA) P12[0] (SIO, I2C1: SCL) VDDIO3 P15[1] (GPIO, MHZ XTAL: XI) P15[0] (GPIO, MHZ XTAL: XO) VCCD VSSD VDDD [8] P15[7] (USBIO, D-, SWDCK) [8] P15[6] (USBIO, D+, SWDIO) P1[7] (GPIO) P1[6] (GPIO) VDDIO1 P1[5] (GPIO, nTRST) P1[4] (GPIO, TDI) P1[3] (GPIO, TDO, SWV) P1[2] (GPIO, Configurable XRES) P1[1] (GPIO, TCK, SWDCK) P1[0] (GPIO, TMS, SWDIO) Note 8. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating. Document Number: 001-57331 Rev. *G Page 6 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet TQFP 77 76 P4[5] (GPIO) P4[4] (GPIO) P4[3] (GPIO) P4[2] (GPIO) P0[7] (GPIO, IDAC2) P0[6] (GPIO, IDAC0) P0[5] (GPIO, Opamp2-) P0[4] (GPIO, Opamp2+) 87 86 85 84 83 82 81 80 79 78 90 89 88 P15[4] (GPIO) P6[3] (GPIO) P6[2] (GPIO) P6[1] (GPIO) P6[0] (GPIO) VDDD VSSD VCCD P4[7] (GPIO) P4[6] (GPIO) 98 97 96 95 94 93 92 91 Lines show VDDIO to I/O supply association 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 P0[0] (GPIO, Opamp2OUT) P4[1] (GPIO) P4[0] (GPIO) P12[3] (SIO) P12[2] (SIO) VSSD VDDA VSSA VCCA NC NC NC NC NC NC P15[3] (GPIO, KHZ XTAL: XI) P15[2] (GPIO, KHZ XTAL: XO) P12[1] (SIO, I2C1: SDA) P12[0] (SIO, I2C1: SCL) P3[7] (GPIO) P3[6] (GPIO) (GPIO) P3[5] VDDIO3 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDDIO0 P0[3] (GPIO, Opamp0-/Extref0) P0[2] (GPIO, Opamp0+) P0[1] (GPIO, Opamp0OUT) [9] [9] (USBIO, D-, SWDCK) P15[7] VDDD VSSD VCCD NC NC (MHZ XTAL: XO, GPIO) P15[0] (MHZ XTAL: XI, GPIO) P15[1] (GPIO) P3[0] (GPIO) P3[1] (Extref1, GPIO) P3[2] (GPIO) P3[3] (GPIO) P3[4] 54 53 52 51 26 27 28 29 30 31 32 33 34 35 (TDI, GPIO) P1[4] (nTRST, GPIO) P1[5] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VDDIO1 (GPIO) P1[6] (GPIO) P1[7] (SIO) P12[6] (SIO) P12[7] (GPIO) P5[4] (GPIO) P5[5] (GPIO) P5[6] (GPIO) P5[7] (USBIO, D+, SWDIO) P15[6] (GPIO) P2[5] (GPIO) P2[6] (GPIO) P2[7] (I2C0: SCL, SIO) P12[4] (I2C0: SDA, SIO) P12[5] (GPIO) P6[4] (GPIO) P6[5] (GPIO) P6[6] (GPIO) P6[7] VSSD NC VSSD VSSD VSSD XRES (GPIO) P5[0] (GPIO) P5[1] (GPIO) P5[2] (GPIO) P5[3] (TMS, SWDIO, GPIO) P1[0] (TCK, SWDCK, GPIO) P1[1] (Configurable XRES, GPIO) P1[2] (TDO, SWV, GPIO) P1[3] 100 99 VDDIO2 P2[4] (GPIO) P2[3] (GPIO) P2[2] (GPIO) P2[1] (GPIO) P2[0] (GPIO) P15[5] (GPIO) Figure 2-4. 100-pin TQFP Part Pinout Figure 2-5 and Figure 2-6 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal analog performance on a two-layer board.  The two pins labeled VDDD must be connected together.  The two pins labeled VCCD must be connected together, with capacitance added, as shown in Figure 2-5 and Power System on page 29. The trace between the two VCCD pins should be as short as possible.  The two pins labeled Vssd must be connected together. For information on circuit board layout issues for mixed signals, refer to the application note, AN57821 - Mixed Signal Circuit Board Layout Considerations for PSoC® 3 and PSoC 5. Note 9. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating. Document Number: 001-57331 Rev. *G Page 7 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 2-5. Example Schematic for 100-pin TQFP Part with Power Connections VDDD C1 1uF VDDD VSSD VSSD VSSD VDDD 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 VDDA C8 0.1uF C17 1uF VSSD VSSA VSSD VDDA VSSA VCCA VDDA C9 1uF C10 0.1uF VSSA VDDD C11 0.1uF VCCD VSSD VDDD C12 0.1uF VSSD VDDD VDDIO0 OA0-, REF0, P0[3] OA0+, P0[2] OA0OUT, P0[1] OA2OUT, P0[0] P4[1] P4[0] SIO, P12[3] SIO, P12[2] VSSD VDDA VSSA VCCA NC NC NC NC NC NC KHZXIN, P15[3] KHZXOUT, P15[2] SIO, P12[1] SIO, P12[0] OA3OUT, P3[7] OA1OUT, P3[6] VDDIO1 P1[6] P1[7] P12[6], SIO P12[7], SIO P5[4] P5[5] P5[6] P5[7] P15[6], USB D+ P15[7], USB DVDDD VSSD VCCD NC NC P15[0], MHZXOUT P15[1], MHZXIN P3[0], IDAC1 P3[1], IDAC3 P3[2], OA3-, REF1 P3[3], OA3+ P3[4], OA1P3[5], OA1+ VDDIO3 P2[5] P2[6] P2[7] P12[4], SIO P12[5], SIO P6[4] P6[5] P6[6] P6[7] VSSB IND VBOOST VBAT VSSD XRES P5[0] P5[1] P5[2] P5[3] P1[0], SWIO, TMS P1[1], SWDIO, TCK P1[2] P1[3], SWV, TDO P1[4], TDI P1[5], NTRST 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VSSD VCCD VDDIO2 P2[4] P2[3] P2[2] P2[1] P2[0] P15[5] P15[4] P6[3] P6[2] P6[1] P6[0] VDDD VSSD VCCD P4[7] P4[6] P4[5] P4[4] P4[3] P4[2] IDAC2, P0[7] IDAC0, P0[6] OA2-, P0[5] OA2+, P0[4] VSSD VSSD C2 0.1uF 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 C6 0.1uF VDDD VDDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 VDDD C15 1uF C16 0.1uF VSSD VSSD Note The two Vccd pins must be connected together with as short a trace as possible. A trace under the device is recommended, as shown in Figure 2-6 on page 9. Document Number: 001-57331 Rev. *G Page 8 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 2-6. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance VDDD VSSA VSSD VDDA VSSA Plane VSSD Plane 3. Pin Descriptions IDAC0, IDAC2 Low resistance output pin for high current DACs (IDAC). Opamp0OUT, Opamp2OUT High current output of uncommitted opamp[10]. Extref0, Extref1 MHz XTAL: Xo, MHz XTAL: Xi 4- to 25-MHz crystal oscillator pin. nTRST Optional JTAG test reset programming and debug port connection to reset the JTAG connection. SIO Opamp0–, Opamp2– Special I/O provides interfaces to the CPU, digital peripherals and interrupts with a programmable high threshold voltage, analog comparator, high sink current, and high impedance state when the device is unpowered. Inverting input to uncommitted opamp. SWDCK Opamp0+, Opamp2+ Noninverting input to uncommitted opamp. Serial wire debug clock programming and debug port connection. GPIO SWDIO General purpose I/O pin provides interfaces to the CPU, digital peripherals, analog peripherals, interrupts, LCD segment drive, and CapSense[10]. Serial wire debug input and output programming and debug port connection. I2C0: SCL, I2C1: SCL Single wire viewer debug output. External reference input to the analog system. I2C SCL line providing wake from sleep on an address match. Any I/O pin can be used for I2C SCL if wake from sleep is not required. SWV TCK JTAG test clock programming and debug port connection. I2C0: SDA, I2C1: SDA TDI I2C JTAG test data in programming and debug port connection. SDA line providing wake from sleep on an address match. Any I/O pin can be used for I2C SDA if wake from sleep is not required. kHz XTAL: Xo, kHz XTAL: Xi 32.768-kHz crystal oscillator pin. TDO JTAG test data out programming and debug port connection. TMS JTAG test mode select programming and debug port connection. Note 10. GPIOs with opamp outputs are not recommended for use with CapSense. Document Number: 001-57331 Rev. *G Page 9 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet USBIO, D+ 4. CPU Provides D+ connection directly to a USB 2.0 bus. May be used as a digital I/O pin; it is powered from VDDD instead of from a VDDIO. Pins are Do Not Use (DNU) on devices without USB. 4.1 8051 CPU USBIO, D– Provides D– connection directly to a USB 2.0 bus. May be used as a digital I/O pin; it is powered from VDDD instead of from a VDDIO. Pins are Do Not Use (DNU) on devices without USB. VCCA. Output of the analog core regulator or the input to the analog core. Requires a 1uF capacitor to VSSA. The regulator output is not designed to drive external circuits. Note that if you use the device with an external core regulator (externally regulated mode), the voltage applied to this pin must not exceed the allowable range of 1.71 V to 1.89 V. When using the internal core regulator, (internally regulated mode, the default), do not tie any power to this pin. For details see Power System on page 29. VCCD. Output of the digital core regulator or the input to the digital core. The two VCCD pins must be shorted together, with the trace between them as short as possible, and a 1uF capacitor to VSSD. The regulator output is not designed to drive external circuits. Note that if you use the device with an external core regulator (externally regulated mode), the voltage applied to this pin must not exceed the allowable range of 1.71 V to 1.89 V. When using the internal core regulator (internally regulated mode, the default), do not tie any power to this pin. For details see Power System on page 29. VDDA Supply for all analog peripherals and analog core regulator. VDDA must be the highest voltage present on the device. All other supply pins must be less than or equal to VDDA. VDDD Supply for all digital peripherals and digital core regulator. VDDD must be less than or equal to VDDA. VSSA Ground for all analog peripherals. VSSD Ground for all digital logic and I/O pins. VDDIO0, VDDIO1, VDDIO2, VDDIO3 The CY8C34 devices use a single cycle 8051 CPU, which is fully compatible with the original MCS-51 instruction set. The CY8C34 family uses a pipelined RISC architecture, which executes most instructions in 1 to 2 cycles to provide peak performance of up to 33 MIPS with an average of 2 cycles per instruction. The single cycle 8051 CPU runs ten times faster than a standard 8051 processor. The 8051 CPU subsystem includes these features:  Single cycle 8051 CPU  Up to 64 KB of flash memory, up to 2 KB of EEPROM, and up to 8 KB of SRAM  512-byte instruction cache between CPU and flash  Programmable nested vector interrupt controller  DMA controller  Peripheral HUB (PHUB)  External memory interface (EMIF) 4.2 Addressing Modes The following addressing modes are supported by the 8051:  Direct Addressing: The operand is specified by a direct 8-bit address field. Only the internal RAM and the SFRs can be accessed using this mode.  Indirect Addressing: The instruction specifies the register which contains the address of the operand. The registers R0 or R1 are used to specify the 8-bit address, while the data pointer (DPTR) register is used to specify the 16-bit address.  Register Addressing: Certain instructions access one of the registers (R0 to R7) in the specified register bank. These instructions are more efficient because there is no need for an address field.  Register Specific Instructions: Some instructions are specific to certain registers. For example, some instructions always act on the accumulator. In this case, there is no need to specify the operand.  Immediate Constants: Some instructions carry the value of the constants directly instead of an address.  Indexed Addressing: This type of addressing can be used only for a read of the program memory. This mode uses the Data Pointer as the base and the accumulator value as an offset to read a program memory. Supply for I/O pins. Each VDDIO must be tied to a valid operating voltage (1.71 V to 5.5 V), and must be less than or equal to VDDA.  Bit Addressing: In this mode, the operand is one of 256 bits. XRES (and configurable XRES) 4.3 Instruction Set External reset pin. Active low with internal pull-up. Pin P1[2] may be configured to be a XRES pin; see “Nonvolatile Latches (NVLs)” on page 22. The 8051 instruction set is highly optimized for 8-bit handling and Boolean operations. The types of instructions supported include:  Arithmetic instructions  Logical instructions  Data transfer instructions  Boolean instructions Document Number: 001-57331 Rev. *G Page 10 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet  Program branching instructions 4.3.1 Instruction Set Summary 4.3.1.1 Arithmetic Instructions Arithmetic instructions support the direct, indirect, register, immediate constant, and register-specific instructions. Arithmetic modes are used for addition, subtraction, multiplication, division, increment, and decrement operations. Table 4-1 lists the different arithmetic instructions. Table 4-1. Arithmetic Instructions Bytes Cycles ADD A,Rn Mnemonic Add register to accumulator Description 1 1 ADD A,Direct Add direct byte to accumulator 2 2 ADD A,@Ri Add indirect RAM to accumulator 1 2 ADD A,#data Add immediate data to accumulator 2 2 ADDC A,Rn Add register to accumulator with carry 1 1 ADDC A,Direct Add direct byte to accumulator with carry 2 2 ADDC A,@Ri Add indirect RAM to accumulator with carry 1 2 ADDC A,#data Add immediate data to accumulator with carry 2 2 SUBB A,Rn Subtract register from accumulator with borrow 1 1 SUBB A,Direct Subtract direct byte from accumulator with borrow 2 2 SUBB A,@Ri Subtract indirect RAM from accumulator with borrow 1 2 SUBB A,#data Subtract immediate data from accumulator with borrow 2 2 INC A Increment accumulator 1 1 INC Rn Increment register 1 2 INC Direct Increment direct byte 2 3 INC @Ri Increment indirect RAM 1 3 DEC A Decrement accumulator 1 1 DEC Rn Decrement register 1 2 DEC Direct Decrement direct byte 2 3 DEC @Ri Decrement indirect RAM 1 3 INC DPTR Increment data pointer 1 1 MUL Multiply accumulator and B 1 2 DIV Divide accumulator by B 1 6 DAA Decimal adjust accumulator 1 3 Document Number: 001-57331 Rev. *G Page 11 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 4.3.1.2 Logical Instructions The logical instructions perform Boolean operations such as AND, OR, XOR on bytes, rotate of accumulator contents, and swap of nibbles in an accumulator. The Boolean operations on the bytes are performed on the bit-by-bit basis. Table 4-2 shows the list of logical instructions and their description. Table 4-2. Logical Instructions Mnemonic Description Bytes Cycles ANL A,Rn AND register to accumulator 1 1 ANL A,Direct AND direct byte to accumulator 2 2 ANL A,@Ri AND indirect RAM to accumulator 1 2 ANL A,#data AND immediate data to accumulator 2 2 ANL Direct, A AND accumulator to direct byte 2 3 ANL Direct, #data AND immediate data to direct byte 3 3 ORL A,Rn OR register to accumulator 1 1 ORL A,Direct OR direct byte to accumulator 2 2 ORL A,@Ri OR indirect RAM to accumulator 1 2 ORL A,#data OR immediate data to accumulator 2 2 ORL Direct, A OR accumulator to direct byte 2 3 ORL Direct, #data OR immediate data to direct byte 3 3 XRL A,Rn XOR register to accumulator 1 1 XRL A,Direct XOR direct byte to accumulator 2 2 XRL A,@Ri XOR indirect RAM to accumulator 1 2 XRL A,#data XOR immediate data to accumulator 2 2 XRL Direct, A XOR accumulator to direct byte 2 3 XRL Direct, #data XOR immediate data to direct byte 3 3 CLR A Clear accumulator 1 1 CPL A Complement accumulator 1 1 RL A Rotate accumulator left 1 1 RLC A Rotate accumulator left through carry 1 1 RR A Rotate accumulator right 1 1 RRC A Rotate accumulator right though carry 1 1 SWAP A Swap nibbles within accumulator 1 1 4.3.1.3 Data Transfer Instructions The data transfer instructions are of three types: the core RAM, xdata RAM, and the lookup tables. The core RAM transfer includes transfer between any two core RAM locations or SFRs. These instructions can use direct, indirect, register, and immediate addressing. The xdata RAM transfer includes only the transfer between the accumulator and the xdata RAM location. It can use only indirect addressing. The lookup tables involve nothing but the read of program memory using the Indexed Document Number: 001-57331 Rev. *G addressing mode. Table 4-3 lists the various data transfer instructions available. 4.3.1.4 Boolean Instructions The 8051 core has a separate bit-addressable memory location. It has 128 bits of bit addressable RAM and a set of SFRs that are bit addressable. The instruction set includes the whole menu of bit operations such as move, set, clear, toggle, OR, and AND instructions and the conditional jump instructions. Table 4-4 lists the available Boolean instructions. Page 12 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Table 4-3. Data Transfer Instructions Mnemonic Description Bytes Cycles 1 1 MOV A,Rn Move register to accumulator MOV A,Direct Move direct byte to accumulator 2 2 MOV A,@Ri Move indirect RAM to accumulator 1 2 MOV A,#data Move immediate data to accumulator 2 2 MOV Rn,A Move accumulator to register 1 1 MOV Rn,Direct Move direct byte to register 2 3 MOV Rn, #data Move immediate data to register 2 2 MOV Direct, A Move accumulator to direct byte 2 2 MOV Direct, Rn Move register to direct byte 2 2 MOV Direct, Direct Move direct byte to direct byte 3 3 MOV Direct, @Ri Move indirect RAM to direct byte 2 3 MOV Direct, #data Move immediate data to direct byte 3 3 MOV @Ri, A Move accumulator to indirect RAM 1 2 MOV @Ri, Direct Move direct byte to indirect RAM 2 3 MOV @Ri, #data Move immediate data to indirect RAM 2 2 MOV DPTR, #data16 Load data pointer with 16 bit constant 3 3 Move code byte relative to DPTR to accumulator 1 5 MOVC A, @A + PC Move code byte relative to PC to accumulator 1 4 MOVX A,@Ri Move external RAM (8-bit) to accumulator 1 4 MOVX A, @DPTR Move external RAM (16-bit) to accumulator 1 3 MOVX @Ri, A Move accumulator to external RAM (8-bit) 1 5 MOVX @DPTR, A Move accumulator to external RAM (16-bit) 1 4 PUSH Direct Push direct byte onto stack 2 3 POP Direct Pop direct byte from stack 2 2 XCH A, Rn Exchange register with accumulator 1 2 XCH A, Direct Exchange direct byte with accumulator 2 3 XCH A, @Ri Exchange indirect RAM with accumulator 1 3 Exchange low order indirect digit RAM with accumulator 1 3 Bytes Cycles MOVC A, @A+DPTR XCHD A, @Ri Table 4-4. Boolean Instructions Mnemonic Description CLR C Clear carry 1 1 CLR bit Clear direct bit 2 3 SETB C Set carry 1 1 SETB bit Set direct bit 2 3 CPL C Complement carry 1 1 CPL bit Complement direct bit 2 3 ANL C, bit AND direct bit to carry 2 2 Document Number: 001-57331 Rev. *G Page 13 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Table 4-4. Boolean Instructions (continued) Mnemonic Bytes Cycles AND complement of direct bit to carry 2 2 ORL C, bit OR direct bit to carry 2 2 ORL C, /bit OR complement of direct bit to carry 2 2 ANL C, /bit Description MOV C, bit Move direct bit to carry 2 2 MOV bit, C Move carry to direct bit 2 3 JC Jump if carry is set 2 3 Jump if no carry is set 2 3 rel JNC rel JB Jump if direct bit is set 3 5 JNB bit, rel bit, rel Jump if direct bit is not set 3 5 JBC bit, rel Jump if direct bit is set and clear bit 3 5 Document Number: 001-57331 Rev. *G Page 14 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 4.3.1.5 Program Branching Instructions The 8051 supports a set of conditional and unconditional jump instructions that help to modify the program execution flow. Table 4-5 shows the list of jump instructions. Table 4-5. Jump Instructions Mnemonic Description Bytes Cycles ACALL addr11 Absolute subroutine call 2 4 LCALL addr16 Long subroutine call 3 4 RET Return from subroutine 1 4 RETI Return from interrupt 1 4 AJMP addr11 Absolute jump 2 3 LJMP addr16 Long jump 3 4 SJMP rel Short jump (relative address) 2 3 JMP @A + DPTR Jump indirect relative to DPTR 1 5 JZ rel Jump if accumulator is zero 2 4 JNZ rel Jump if accumulator is nonzero 2 4 CJNE A,Direct, rel Compare direct byte to accumulator and jump if not equal 3 5 CJNE A, #data, rel Compare immediate data to accumulator and jump if not equal 3 4 CJNE Rn, #data, rel Compare immediate data to register and jump if not equal 3 4 CJNE @Ri, #data, rel Compare immediate data to indirect RAM and jump if not equal 3 5 DJNZ Rn,rel Decrement register and jump if not zero 2 4 DJNZ Direct, rel Decrement direct byte and jump if not zero 3 5 NOP No operation 1 1 4.4 DMA and PHUB 4.4.1 PHUB Features The PHUB and the DMA controller are responsible for data transfer between the CPU and peripherals, and also data transfers between peripherals. The PHUB and DMA also control device configuration during boot. The PHUB consists of:  CPU and DMA controller are both bus masters to the PHUB  A central hub that includes the DMA controller, arbiter, and  Simultaneous CPU and DMA access to peripherals located on  Multiple spokes that radiate outward from the hub to most  Simultaneous DMA source and destination burst transactions There are two PHUB masters: the CPU and the DMA controller. Both masters may initiate transactions on the bus. The DMA channels can handle peripheral communication without CPU intervention. The arbiter in the central hub determines which DMA channel is the highest priority if there are multiple requests.  Supports 8-, 16-, 24-, and 32-bit addressing and data router peripherals Document Number: 001-57331 Rev. *G  Eight multi-layer AHB bus parallel access paths (spokes) for peripheral access different spokes on different spokes Table 4-6. PHUB Spokes and Peripherals PHUB Spokes Peripherals 0 SRAM 1 IOs, PICU, EMIF 2 PHUB local configuration, Power manager, Clocks, IC, SWV, EEPROM, Flash programming interface 3 Analog interface and trim, Decimator 4 USB, CAN, I2C, Timers, Counters, and PWMs 5 Reserved 6 UDBs group 1 7 UDBs group 2 Page 15 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 4.4.2 DMA Features  24 DMA channels  Each channel has one or more transaction descriptors (TD) to configure channel behavior. Up to 128 total TDs can be defined  TDs can be dynamically updated Priority levels 2 to 7 are guaranteed the minimum bus bandwidth shown in Table 4-7 after the CPU and DMA priority levels 0 and 1 have satisfied their requirements. Table 4-7. Priority Levels Priority Level % Bus Bandwidth 0 100.0  Eight levels of priority per channel 1 100.0  Any digitally routable signal, the CPU, or another DMA channel, 2 50.0 3 25.0  Each channel can generate up to two interrupts per transfer 4 12.5  Transactions can be stalled or canceled 5 6.2  Supports transaction size of infinite or 1 to 64 KB 6 3.1  TDs may be nested and/or chained for complex transactions 7 1.5 can trigger a transaction 4.4.3 Priority Levels The CPU always has higher priority than the DMA controller when their accesses require the same bus resources. Due to the system architecture, the CPU can never starve the DMA. DMA channels of higher priority (lower priority number) may interrupt current DMA transfers. In the case of an interrupt, the current transfer is allowed to complete its current transaction. To ensure latency limits when multiple DMA accesses are requested simultaneously, a fairness algorithm guarantees an interleaved minimum percentage of bus bandwidth for priority levels 2 through 7. Priority levels 0 and 1 do not take part in the fairness algorithm and may use 100 percent of the bus bandwidth. If a tie occurs on two DMA requests of the same priority level, a simple round robin method is used to evenly share the allocated bandwidth. The round robin allocation can be disabled for each DMA channel, allowing it to always be at the head of the line. When the fairness algorithm is disabled, DMA access is granted based solely on the priority level; no bus bandwidth guarantees are made. 4.4.4 Transaction Modes Supported The flexible configuration of each DMA channel and the ability to chain multiple channels allow the creation of both simple and complex use cases. General use cases include, but are not limited to: 4.4.4.1 Simple DMA In a simple DMA case, a single TD transfers data between a source and sink (peripherals or memory location). The basic timing diagrams of DMA read and write cycles are shown in Figure 4-1. For more description on other transfer modes, refer to the Technical Reference Manual. Figure 4-1. DMA Timing Diagram ADDRESS Phase DATA Phase ADDRESS Phase CLK ADDR 16/32 DATA Phase CLK A ADDR 16/32 B WRITE A B WRITE DATA (A) DATA READY DATA DATA (A) READY Basic DMA Read Transfer without wait states Document Number: 001-57331 Rev. *G Basic DMA Write Transfer without wait states Page 16 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 4.4.4.2 Auto Repeat DMA Auto repeat DMA is typically used when a static pattern is repetitively read from system memory and written to a peripheral. This is done with a single TD that chains to itself. 4.4.4.3 Ping Pong DMA A ping pong DMA case uses double buffering to allow one buffer to be filled by one client while another client is consuming the data previously received in the other buffer. In its simplest form, this is done by chaining two TDs together so that each TD calls the opposite TD when complete. phase TD(s) finish, a status phase TD can be invoked that reads some memory mapped status information from the peripheral and copies it to a location in system memory specified by the CPU for later inspection. Multiple sets of configuration, data, and status phase ‘subchains’ can be strung together to create larger chains that transmit multiple packets in this way. A similar concept exists in the opposite direction to receive the packets. 4.4.4.7 Nested DMA Circular DMA is similar to ping pong DMA except it contains more than two buffers. In this case there are multiple TDs; after the last TD is complete it chains back to the first TD. One TD may modify another TD, as the TD configuration space is memory mapped similar to any other peripheral. For example, a first TD loads a second TD’s configuration and then calls the second TD. The second TD moves data as required by the application. When complete, the second TD calls the first TD, which again updates the second TD’s configuration. This process repeats as often as necessary. 4.4.4.5 Scatter Gather DMA 4.5 Interrupt Controller In the case of scatter gather DMA, there are multiple noncontiguous sources or destinations that are required to effectively carry out an overall DMA transaction. For example, a packet may need to be transmitted off of the device and the packet elements, including the header, payload, and trailer, exist in various noncontiguous locations in memory. Scatter gather DMA allows the segments to be concatenated together by using multiple TDs in a chain. The chain gathers the data from the multiple locations. A similar concept applies for the reception of data onto the device. Certain parts of the received data may need to be scattered to various locations in memory for software processing convenience. Each TD in the chain specifies the location for each discrete element in the chain. The interrupt controller provides a mechanism for hardware resources to change program execution to a new address, independent of the current task being executed by the main code. The interrupt controller provides enhanced features not found on original 8051 interrupt controllers: 4.4.4.4 Circular DMA 4.4.4.6 Packet Queuing DMA Packet queuing DMA is similar to scatter gather DMA but specifically refers to packet protocols. With these protocols, there may be separate configuration, data, and status phases associated with sending or receiving a packet. For instance, to transmit a packet, a memory mapped configuration register can be written inside a peripheral, specifying the overall length of the ensuing data phase. The CPU can set up this configuration information anywhere in system memory and copy it with a simple TD to the peripheral. After the configuration phase, a data phase TD (or a series of data phase TDs) can begin (potentially using scatter gather). When the data Document Number: 001-57331 Rev. *G  Thirty-two interrupt vectors  Jumps directly to ISR anywhere in code space with dynamic vector addresses  Multiple sources for each vector  Flexible interrupt to vector matching  Each interrupt vector is independently enabled or disabled  Each interrupt can be dynamically assigned one of eight priorities  Eight level nestable interrupts  Multiple I/O interrupt vectors  Software can send interrupts  Software can clear pending interrupts Figure 4-2 on page 18 represents typical flow of events when an interrupt triggered. Figure 4-3 on page 19 shows the interrupt structure and priority polling. Page 17 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 4-2. Interrupt Processing Timing Diagram 1 2 3 4 5 6 7 8 9 10 11 S Arrival of new Interrupt S Pend bit is set on next clock active edge POST and PEND bits cleared after IRQ is sleared S Interrupt is posted to ascertain the priority S Interrupt request sent to core for processing NA NA 0x0010 IRQ cleared after receiving IRA S S The active interrupt number is posted to core The active interrupt ISR address is posted to core S S NA S S Interrupt generation and posting to CPU CPU Response Int. State Clear S Completing current instruction and branching to vector address Complete ISR and return Notes  1: Interrupt triggered asynchronous to the clock  2: The PEND bit is set on next active clock edge to indicate the interrupt arrival  3: POST bit is set following the PEND bit  4: Interrupt request and the interrupt number sent to CPU core after evaluation priority (Takes 3 clocks)  5: ISR address is posted to CPU core for branching  6: CPU acknowledges the interrupt request  7: ISR address is read by CPU for branching  8, 9: PEND and POST bits are cleared respectively after receiving the IRA from core  10: IRA bit is cleared after completing the current instruction and starting the instruction execution from ISR location (Takes 7 cycles)  11: IRC is set to indicate the completion of ISR, Active int. status is restored with previous status The total interrupt latency (ISR execution) = POST + PEND + IRQ + IRA + Completing current instruction and branching = 1+1+1+2+7 cycles = 12 cycles Document Number: 001-57331 Rev. *G Page 18 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 4-3. Interrupt Structure Interrupt Polling logic Interrupts form Fixed function blocks, DMA and UDBs Highest Priority Interrupt Enable/ Disable, PEND and POST logic Interrupts 0 to 31 from UDBs 0 Interrupts 0 to 31 from Fixed Function Blocks 1 IRQ 8 Level Priority decoder for all interrupts Polling sequence Interrupt routing logic to select 32 sources Interrupt 2 to 30 Interrupts 0 to 31 from DMA Individual Enable Disable bits 0 to 31 ACTIVE_INT_NUM [15:0] INT_VECT_ADDR IRA IRC 31 Global Enable disable bit When an interrupt is pending, the current instruction is completed and the program counter is pushed onto the stack. Code execution then jumps to the program address provided by the vector. After the ISR is completed, a RETI instruction is executed and returns execution to the instruction following the previously interrupted instruction. To do this the RETI instruction pops the program counter from the stack. If the same priority level is assigned to two or more interrupts, the interrupt with the lower vector number is executed first. Each interrupt vector may choose from three interrupt sources: Fixed Function, DMA, and UDB. The fixed function interrupts are Document Number: 001-57331 Rev. *G Lowest Priority direct connections to the most common interrupt sources and provide the lowest resource cost connection. The DMA interrupt sources provide direct connections to the two DMA interrupt sources provided per DMA channel. The third interrupt source for vectors is from the UDB digital routing array. This allows any digital signal available to the UDB array to be used as an interrupt source. Fixed function interrupts and all interrupt sources may be routed to any interrupt vector using the UDB interrupt source connections. Page 19 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Table 4-8. Interrupt Vector Table # Fixed Function DMA UDB 0 LVD phub_termout0[0] udb_intr[0] 1 Cache/ECC phub_termout0[1] udb_intr[1] 2 Reserved phub_termout0[2] udb_intr[2] 3 Sleep (Pwr Mgr) phub_termout0[3] udb_intr[3] 4 PICU[0] phub_termout0[4] udb_intr[4] 5 PICU[1] phub_termout0[5] udb_intr[5] 6 PICU[2] phub_termout0[6] udb_intr[6] 7 PICU[3] phub_termout0[7] udb_intr[7] 8 PICU[4] phub_termout0[8] udb_intr[8] 9 PICU[5] phub_termout0[9] udb_intr[9] 10 PICU[6] phub_termout0[10] udb_intr[10] 11 PICU[12] phub_termout0[11] udb_intr[11] 12 PICU[15] phub_termout0[12] udb_intr[12] 13 Comparators Combined phub_termout0[13] udb_intr[13] 14 Switched Caps Combined phub_termout0[14] udb_intr[14] phub_termout0[15] udb_intr[15] 2 15 I C 16 CAN phub_termout1[0] udb_intr[16] 17 Timer/Counter0 phub_termout1[1] udb_intr[17] 18 Timer/Counter1 phub_termout1[2] udb_intr[18] 19 Timer/Counter2 phub_termout1[3] udb_intr[19] 20 Timer/Counter3 phub_termout1[4] udb_intr[20] 21 USB SOF Int phub_termout1[5] udb_intr[21] 22 USB Arb Int phub_termout1[6] udb_intr[22] 23 USB Bus Int phub_termout1[7] udb_intr[23] 24 USB Endpoint[0] phub_termout1[8] udb_intr[24] 25 USB Endpoint Data phub_termout1[9] udb_intr[25] 26 Reserved phub_termout1[10] udb_intr[26] 27 LCD phub_termout1[11] udb_intr[27] 28 Reserved phub_termout1[12] udb_intr[28] 29 Decimator Int phub_termout1[13] udb_intr[29] 30 PHUB Error Int phub_termout1[14] udb_intr[30] 31 EEPROM Fault Int phub_termout1[15] udb_intr[31] Document Number: 001-57331 Rev. *G Page 20 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 5. Memory 5.1 Static RAM CY8C34 SRAM is used for temporary data storage. Up to 8 KB of SRAM is provided and can be accessed by the 8051 or the DMA controller. See Memory Map on page 24. Simultaneous access of SRAM by the 8051 and the DMA controller is possible if different 4-KB blocks are accessed. protecting your application from external access (see the “Device Security” section on page 63). For more information about how to take full advantage of the security features in PSoC, see the PSoC 3 TRM. Table 5-1. Flash Protection Protection Setting Up to an additional 8 KB of flash space is available for ECC. If ECC is not used this space can store device configuration data and bulk user data. User code may not be run out of the ECC flash memory section. ECC can correct one bit error and detect two bit errors per 8 bytes of firmware memory; an interrupt can be generated when an error is detected. The CPU reads instructions located in flash through a cache controller. This improves instruction execution rate and reduces system power consumption by requiring less frequent flash access. The cache has 8 lines at 64 bytes per line for a total of 512 bytes. It is fully associative, automatically controls flash power, and can be enabled or disabled. If ECC is enabled, the cache controller also performs error checking and correction, and interrupt generation. Flash programming is performed through a special interface and preempts code execution out of flash. The flash programming interface performs flash erasing, programming and setting code protection levels. Flash in-system serial programming (ISSP), typically used for production programming, is possible through both the SWD and JTAG interfaces. In-system programming, typically used for bootloaders, is also possible using serial interfaces such as I2C, USB, UART, and SPI, or any communications protocol. 5.3 Flash Security All PSoC devices include a flexible flash-protection model that prevents access and visibility to on-chip flash memory. This prevents duplication or reverse engineering of proprietary code. Flash memory is organized in blocks, where each block contains 256 bytes of program or data and 32 bytes of ECC or configuration data. A total of up to 256 blocks is provided on 64-KB flash devices. The device offers the ability to assign one of four protection levels to each row of flash. Table 5-1 lists the protection modes available. Flash protection levels can only be changed by performing a complete flash erase. The Full Protection and Field Upgrade settings disable external access (through a debugging tool such as PSoC Creator, for example). If your application requires code update through a bootloader, then use the Field Upgrade setting. Use the Unprotected setting only when no security is needed in your application. The PSoC device also offers an advanced security feature called Device Security which permanently disables all test, programming, and debug ports, Document Number: 001-57331 Rev. *G Not Allowed Unprotected External read and write – + internal read and write Factory Upgrade External write + internal read and write 5.2 Flash Program Memory Flash memory in PSoC devices provides nonvolatile storage for user firmware, user configuration data, bulk data storage, and optional ECC data. The main flash memory area contains up to 64 KB of user program space. Allowed External read Field Upgrade Internal read and write External read and write Full Protection Internal read External read and write + internal write Disclaimer Note the following details of the flash code protection features on Cypress devices. Cypress products meet the specifications contained in their particular Cypress data sheets. Cypress believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as ‘unbreakable’. Cypress is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress are committed to continuously improving the code protection features of our products. 5.4 EEPROM PSoC EEPROM memory is a byte-addressable nonvolatile memory. The CY8C34 has up to 2 KB of EEPROM memory to store user data. Reads from EEPROM are random access at the byte level. Reads are done directly; writes are done by sending write commands to an EEPROM programming interface. CPU code execution can continue from flash during EEPROM writes. EEPROM is erasable and writeable at the row level. The EEPROM is divided into 128 rows of 16 bytes each. The CPU can not execute out of EEPROM. There is no ECC hardware associated with EEPROM. If ECC is required it must be handled in firmware. It can take as much as 20 milliseconds to write to EEPROM or flash. During this time the device should not be reset, or unexpected changes may be made to portions of EEPROM or flash. Reset sources (see Section 6.3.1) include XRES pin, software reset, and watchdog; care should be taken to make sure that these are not inadvertently activated. Also, the low voltage detect circuits should be configured to generate an interrupt instead of a reset. Page 21 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 5.5 Nonvolatile Latches (NVLs) PSoC has a 4-byte array of nonvolatile latches (NVLs) that are used to configure the device at reset. The NVL register map is shown in Table 5-2. Table 5-2. Device Configuration NVL Register Map Register Address 7 6 5 4 3 2 1 0 0x00 PRT3RDM[1:0] PRT2RDM[1:0] PRT1RDM[1:0] PRT0RDM[1:0] 0x01 PRT12RDM[1:0] PRT6RDM[1:0] PRT5RDM[1:0] PRT4RDM[1:0] 0x02 XRESMEN 0x03 DBGEN DIG_PHS_DLY[3:0] PRT15RDM[1:0] ECCEN DPS[1:0] CFGSPEED The details for individual fields and their factory default settings are shown in Table 5-3:. Table 5-3. Fields and Factory Default Settings Field Description Settings PRTxRDM[1:0] Controls reset drive mode of the corresponding IO port. 00b (default) - high impedance analog See “Reset Configuration” on page 39. All pins of the port 01b - high impedance digital are set to the same mode. 10b - resistive pull up 11b - resistive pull down XRESMEN Controls whether pin P1[2] is used as a GPIO or as an external reset. See “Pin Descriptions” on page 9, XRES description. 0 (default for 68-pin and 100-pin parts) - GPIO 1 (default for 48-pin parts) - external reset DBGEN Debug Enable allows access to the debug system, for third-party programmers. 0 - access disabled 1 (default) - access enabled DPS{1:0] Controls the usage of various P1 pins as a debug port. See “Programming, Debug Interfaces, Resources” on page 60. 00b - 5-wire JTAG 01b (default) - 4-wire JTAG 10b - SWD 11b - debug ports disabled ECCEN Controls whether ECC flash is used for ECC or for general 0 - ECC disabled configuration and data storage. See “Flash Program 1 (default) - ECC enabled Memory” on page 21. DIG_PHS_DLY[3:0] Selects the digital clock phase delay. See the TRM for details. Although PSoC Creator provides support for modifying the device configuration NVLs, the number of NVL erase / write cycles is limited – see Nonvolatile Latches (NVL) on page 120. Document Number: 001-57331 Rev. *G Page 22 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 5.6 External Memory Interface CY8C34 provides an EMIF for connecting to external memory devices. The connection allows read and write accesses to external memories. The EMIF operates in conjunction with UDBs, I/O ports, and other hardware to generate external memory address and control signals. At 33 MHz, each memory access cycle takes four bus clock cycles. Figure 5-1 is the EMIF block diagram. The EMIF supports synchronous and asynchronous memories. The CY8C34 supports only one type of external memory device at a time. External memory can be accessed through the 8051 xdata space; up to 24 address bits can be used. See “xdata Space” section on page 25. The memory can be 8 or 16 bits wide. Figure 5-1. EMIF Block Diagram Address Signals External_ MEM_ ADDR[23:0] IO PORTs Data Signals External_ MEM_ DATA[15:0] IO PORTs Control Signals IO PORTs Data, Address, and Control Signals IO IF PHUB Data, Address, and Control Signals Control DSI Dynamic Output Control UDB DSI to Port Data, Address, and Control Signals EM Control Signals Other Control Signals EMIF Document Number: 001-57331 Rev. *G Page 23 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 5.7 Memory Map Figure 5-2. 8051 Internal Data Space The CY8C34 8051 memory map is very similar to the MCS-51 memory map. 0x00 4 Banks, R0-R7 Each 0x1F 0x20 0x2F 0x30 5.7.1 Code Space The CY8C34 8051 code space is 64 KB. Only main flash exists in this space. See the Flash Program Memory on page 21. 5.7.2 Internal Data Space Bit Addressable Area Lower Core RAM Shared with Stack Space (direct and indirect addressing) 0x7F 0x80 The CY8C34 8051 internal data space is 384 bytes, compressed within a 256-byte space. This space consists of 256 bytes of RAM (in addition to the SRAM mentioned in Static RAM on page 21) and a 128-byte space for special function registers (SFR). See Figure 5-2. The lowest 32 bytes are used for 4 banks of registers R0-R7. The next 16 bytes are bit-addressable. 0xFF Upper Core RAM Shared with Stack Space (indirect addressing) SFR Special Function Registers (direct addressing) In addition to the register or bit address modes used with the lower 48 bytes, the lower 128 bytes can be accessed with direct or indirect addressing. With direct addressing mode, the upper 128 bytes map to the SFRs. With indirect addressing mode, the upper 128 bytes map to RAM. Stack operations use indirect addressing; the 8051 stack space is 256 bytes. See the “Addressing Modes” section on page 10. 5.7.3 SFRs The SFR space provides access to frequently accessed registers. The memory map for the SFR memory space is shown in Table 5-4. Table 5-4. SFR Map Address 0×F8 0/8 SFRPRT15DR 1/9 SFRPRT15PS 2/A SFRPRT15SEL 3/B – 4/C – 5/D – 6/E – 7/F – 0×F0 B – SFRPRT12SEL – – – – – 0×E8 SFRPRT12DR SFRPRT12PS MXAX – – – – – 0×E0 ACC – – – – – – – 0×D8 SFRPRT6DR SFRPRT6PS SFRPRT6SEL – – – – – 0×D0 PSW – – – – – – – 0×C8 SFRPRT5DR SFRPRT5PS SFRPRT5SEL – – – – – 0×C0 SFRPRT4DR SFRPRT4PS SFRPRT4SEL – – – – – – – – – – 0×B8 0×B0 SFRPRT3DR SFRPRT3PS SFRPRT3SEL – – – – – 0×A8 IE – – – – – – – 0×A0 P2AX – SFRPRT1SEL – – – – – 0×98 SFRPRT2DR SFRPRT2PS SFRPRT2SEL – – – – – 0×90 SFRPRT1DR SFRPRT1PS – DPX0 – DPX1 – – 0×88 – SFRPRT0PS SFRPRT0SEL – – – – – 0×80 SFRPRT0DR SP DPL0 DPH0 DPL1 DPH1 DPS – The CY8C34 family provides the standard set of registers found on industry standard 8051 devices. In addition, the CY8C34 devices add SFRs to provide direct access to the I/O ports on the device. The following sections describe the SFRs added to the CY8C34 family. Document Number: 001-57331 Rev. *G Page 24 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 5.7.4 XData Space Access SFRs 5.7.5.1 xdata Space The 8051 core features dual DPTR registers for faster data transfer operations. The data pointer select SFR, DPS, selects which data pointer register, DPTR0 or DPTR1, is used for the following instructions: The 8051 xdata space is 24-bit, or 16 MB in size. The majority of this space is not ‘external’—it is used by on-chip components. See Table 5-5. External, that is, off-chip, memory can be accessed using the EMIF. See External Memory Interface on page 23.  MOVX @DPTR, A  MOVX A, @DPTR  MOVC A, @A+DPTR  JMP @A+DPTR  INC DPTR  MOV DPTR, #data16 The extended data pointer SFRs, DPX0, DPX1, MXAX, and P2AX, hold the most significant parts of memory addresses during access to the xdata space. These SFRs are used only with the MOVX instructions. During a MOVX instruction using the DPTR0/DPTR1 register, the most significant byte of the address is always equal to the contents of DPX0/DPX1. During a MOVX instruction using the R0 or R1 register, the most significant byte of the address is always equal to the contents of MXAX, and the next most significant byte is always equal to the contents of P2AX. 5.7.5 I/O Port SFRs The I/O ports provide digital input sensing, output drive, pin interrupts, connectivity for analog inputs and outputs, LCD, and access to peripherals through the DSI. Full information on I/O ports is found in I/O System and Routing on page 33. I/O ports are linked to the CPU through the PHUB and are also available in the SFRs. Using the SFRs allows faster access to a limited set of I/O port registers, while using the PHUB allows boot configuration and access to all I/O port registers. Table 5-5. XDATA Data Address Map Address Range 0×00 0000 – 0×00 1FFF SRAM 0×00 4000 – 0×00 42FF Clocking, PLLs, and oscillators 0×00 4300 – 0×00 43FF Power management 0×00 4400 – 0×00 44FF Interrupt controller 0×00 4500 – 0×00 45FF Ports interrupt control 0×00 4700 – 0×00 47FF Flash programming interface 0×00 4800 - 0×00 48FF Cache controller 0×00 4900 – 0×00 49FF I2C controller 0×00 4E00 – 0×00 4EFF Decimator 0×00 4F00 – 0×00 4FFF Fixed timer/counter/PWMs 0×00 5000 – 0×00 51FF I/O ports control 0×00 5400 – 0×00 54FF EMIF control registers 0×00 5800 – 0×00 5FFF Analog subsystem interface 0×00 6000 – 0×00 60FF USB controller 0×00 6400 – 0×00 6FFF UDB Working Registers 0×00 7000 – 0×00 7FFF PHUB configuration 0×00 8000 – 0×00 8FFF EEPROM 0×00 A000 – 0×00 A400 CAN 0×00 C000 – 0×00 C800 Reserved 0×01 0000 – 0×01 FFFF Digital Interconnect configuration 0×05 0220 – 0×05 02F0 Debug controller 0×08 0000 – 0×08 1FFF Flash ECC bytes 0×80 0000 – 0×FF FFFF External memory interface Each SFR supported I/O port provides three SFRs:  SFRPRTxDR sets the output data state of the port (where × is port number and includes ports 0–6, 12 and 15).  The SFRPRTxSEL selects whether the PHUB PRTxDR Purpose register or the SFRPRTxDR controls each pin’s output buffer within the port. If a SFRPRTxSEL[y] bit is high, the corresponding SFRPRTxDR[y] bit sets the output state for that pin. If a SFRPRTxSEL[y] bit is low, the corresponding PRTxDR[y] bit sets the output state of the pin (where y varies from 0 to 7).  The SFRPRTxPS is a read only register that contains pin state values of the port pins. Document Number: 001-57331 Rev. *G Page 25 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 6. System Integration Key features of the clocking system include:  Seven general purpose clock sources 6.1 Clocking System The clocking system generates, divides, and distributes clocks throughout the PSoC system. For the majority of systems, no external crystal is required. The IMO and PLL together can generate up to a 50 MHz clock, accurate to ±1 percent over voltage and temperature. Additional internal and external clock sources allow each design to optimize accuracy, power, and cost. Any of the clock sources can be used to generate other clock frequencies in the 16-bit clock dividers and UDBs for anything the user wants, for example a UART baud rate generator. Clock generation and distribution is automatically configured through the PSoC Creator IDE graphical interface. This is based on the complete system’s requirements. It greatly speeds the design process. PSoC Creator allows you to build clocking systems with minimal input. You can specify desired clock frequencies and accuracies, and the software locates or builds a clock that meets the required specifications. This is possible because of the programmability inherent in PSoC. 3- to 62-MHz IMO, ±1% at 3 MHz 4- to 25-MHz external crystal oscillator (MHzECO)  Clock doubler provides a doubled clock frequency output for the USB block, see USB Clock Domain on page 28.  DSI signal from an external I/O pin or other logic  24- to 50-MHz fractional PLL sourced from IMO, MHzECO, or DSI  1-kHz, 33-kHz, 100-kHz ILO for WDT and sleep timer  32.768-kHz external crystal oscillator (kHzECO) for RTC  IMO has a USB mode that auto locks to the USB bus clock requiring no external crystal for USB (USB equipped parts only)    Independently sourced clock in all clock dividers  Eight 16-bit clock dividers for the digital system  Four 16-bit clock dividers for the analog system  Dedicated 16-bit divider for the bus clock  Dedicated 4-bit divider for the CPU clock  Automatic clock configuration in PSoC Creator Table 6-1. Oscillator Summary Source Fmin Tolerance at Fmin Fmax Tolerance at Fmax Startup Time IMO 3 MHz ±1% over voltage and temperature 62 MHz ±7% 13 µs max MHzECO 4 MHz Crystal dependent 25 MHz Crystal dependent 5 ms typ, max is crystal dependent DSI 0 MHz Input dependent 50 MHz Input dependent Input dependent PLL 24 MHz Input dependent 50 MHz Input dependent 250 µs max Doubler 48 MHz Input dependent 48 MHz Input dependent 1 µs max ILO 1 kHz –50%, +100% 100 kHz –55%, +100% 15 ms max in lowest power mode kHzECO 32 kHz Crystal dependent 32 kHz 500 ms typ, max is crystal dependent Document Number: 001-57331 Rev. *G Crystal dependent Page 26 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 6-1. Clocking Subsystem 3-72 MHz IMO 4-33 MHz ECO External IO or DSI 0-50 MHz 32 kHz ECO 1,33,100 kHz ILO 12-72 MHz Doubler 24-50 MHz PLL System Clock Mux Bus/CPU Clock Divider 16 bit 7 Digital Clock Divider 16 bit Digital Clock Divider 16 bit Analog Clock Divider 16 bit s k e w Digital Clock Divider 16 bit Digital Clock Divider 16 bit Analog Clock Divider 16 bit s k e w Digital Clock Divider 16 bit Digital Clock Divider 16 bit Analog Clock Divider 16 bit s k e w Digital Clock Divider 16 bit Digital Clock Divider 16 bit Analog Clock Divider 16 bit s k e w 7 6.1.1 Internal Oscillators 6.1.1.1 Internal Main Oscillator In most designs the IMO is the only clock source required, due to its ±1-percent accuracy. The IMO operates with no external components and outputs a stable clock. A factory trim for each frequency range is stored in the device. With the factory trim, tolerance varies from ±1 percent at 3 MHz, up to ±7 percent at 62 MHz. The IMO, in conjunction with the PLL, allows generation of other clocks up to the device's maximum frequency (see PLL). The IMO provides clock outputs at 3, 6, 12, 24, 48, and 62 MHz. 6.1.1.2 Clock Doubler The clock doubler outputs a clock at twice the frequency of the input clock. The doubler works at input frequency of 24 MHz, providing 48 MHz for the USB. It can be configured to use a clock from the IMO, MHzECO, or the DSI (external pin). 6.1.1.3 PLL The PLL allows low-frequency, high-accuracy clocks to be multiplied to higher frequencies. This is a trade off between higher clock frequency and accuracy and, higher power consumption and increased startup time. The PLL block provides a mechanism for generating clock frequencies based upon a variety of input sources. The PLL outputs clock frequencies in the range of 24 to 50 MHz. Its input and feedback dividers supply 4032 discrete ratios to create almost any desired clock frequency. The accuracy of the PLL output depends on the accuracy of the PLL input source. The most common PLL use is to multiply the IMO clock at 3 MHz, where it is most accurate, to generate the other clocks up to the device’s maximum frequency. The PLL achieves phase lock within 250 µs (verified by bit setting). It can be configured to use a clock from the IMO, MHzECO or DSI (external pin). The PLL clock source can be Document Number: 001-57331 Rev. *G used until lock is complete and signaled with a lock bit. The lock signal can be routed through the DSI to generate an interrupt. Disable the PLL before entering low-power modes. 6.1.1.4 Internal Low-Speed Oscillator The ILO provides clock frequencies for low-power consumption, including the watchdog timer, and sleep timer. The ILO generates up to three different clocks: 1 kHz, 33 kHz, and 100 kHz. The 1-kHz clock (CLK1K) is typically used for a background ‘heartbeat’ timer. This clock inherently lends itself to low-power supervisory operations such as the watchdog timer and long sleep intervals using the central timewheel (CTW). The central timewheel is a 1-kHz, free running, 13-bit counter clocked by the ILO. The central timewheel is always enabled, except in hibernate mode and when the CPU is stopped during debug on chip mode. It can be used to generate periodic interrupts for timing purposes or to wake the system from a low-power mode. Firmware can reset the central timewheel. Systems that require accurate timing should use the RTC capability instead of the central timewheel. The 100-kHz clock (CLK100K) can be used as a low power master clock. It can also generate time intervals using the fast timewheel. The fast timewheel is a 5-bit counter, clocked by the 100-kHz clock. It features programmable settings and automatically resets when the terminal count is reached. An optional interrupt can be generated each time the terminal count is reached. This enables flexible, periodic interrupts of the CPU at a higher rate than is allowed using the central timewheel. The 33-kHz clock (CLK33K) comes from a divide-by-3 operation on CLK100K. This output can be used as a reduced accuracy version of the 32.768-kHz ECO clock with no need for a crystal. Page 27 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 6.1.2 External Oscillators 6.1.2.1 MHz External Crystal Oscillator The MHzECO provides high frequency, high precision clocking using an external crystal (see Figure 6-2). It supports a wide variety of crystal types, in the range of 4 to 25 MHz. When used in conjunction with the PLL, it can generate other clocks up to the device's maximum frequency (see PLL). The GPIO pins connecting to the external crystal and capacitors are fixed. MHzECO accuracy depends on the crystal chosen. Figure 6-2. MHzECO Block Diagram 4 - 25 MHz Crystal Osc XCLK_MHZ 4 –25 MHz crystal External Components 6.1.2.3 Digital System Interconnect The DSI provides routing for clocks taken from external clock oscillators connected to I/O. The oscillators can also be generated within the device in the digital system and UDBs. While the primary DSI clock input provides access to all clocking resources, up to eight other DSI clocks (internally or externally generated) may be routed directly to the eight digital clock dividers. This is only possible if there are multiple precision clock sources. 6.1.3 Clock Distribution Xo (Pin P15[0]) Xi (Pin P15[1]) capacitance, should equal the crystal CL value. For more information, refer to application note AN54439: PSoC 3 and PSoC 5 External Oscillators. See also pin capacitance specifications in the “GPIO” section on page 74. Capacitors All seven clock sources are inputs to the central clock distribution system. The distribution system is designed to create multiple high precision clocks. These clocks are customized for the design’s requirements and eliminate the common problems found with limited resolution prescalers attached to peripherals. The clock distribution system generates several types of clock trees.  The master clock is used to select and supply the fastest clock in the system for general clock requirements and clock synchronization of the PSoC device.  Bus clock 16-bit divider uses the master clock to generate the 6.1.2.2 32.768-kHz ECO The 32.768-kHz external crystal oscillator (32kHzECO) provides precision timing with minimal power consumption using an external 32.768-kHz watch crystal (see Figure 6-3). The 32kHzECO also connects directly to the sleep timer and provides the source for the RTC. The RTC uses a 1-second interrupt to implement the RTC functionality in firmware. The oscillator works in two distinct power modes. This allows users to trade off power consumption with noise immunity from neighboring circuits. The GPIO pins connected to the external crystal and capacitors are fixed. Figure 6-3. 32kHzECO Block Diagram 32 kHz Crystal Osc Xi (Pin P15[3]) External Components XCLK32K Xo (Pin P15[2]) 32 kHz crystal Capacitors It is recommended that the external 32.768-kHz watch crystal have a load capacitance (CL) of 6 pF or 12.5 pF. Check the crystal manufacturer's datasheet. The two external capacitors, CL1 and CL2, are typically of the same value, and their total capacitance, CL1CL2 / (CL1 + CL2), including pin and trace Document Number: 001-57331 Rev. *G bus clock used for data transfers. Bus clock is the source clock for the CPU clock divider.  Eight fully programmable 16-bit clock dividers generate digital system clocks for general use in the digital system, as configured by the design’s requirements. Digital system clocks can generate custom clocks derived from any of the seven clock sources for any purpose. Examples include baud rate generators, accurate PWM periods, and timer clocks, and many others. If more than eight digital clock dividers are required, the UDBs and fixed function timer/counter/PWMs can also generate clocks.  Four 16-bit clock dividers generate clocks for the analog system components that require clocking, such as ADC and mixers. The analog clock dividers include skew control to ensure that critical analog events do not occur simultaneously with digital switching events. This is done to reduce analog system noise. Each clock divider consists of an 8-input multiplexer, a 16-bit clock divider (divide by 2 and higher) that generates ~50 percent duty cycle clocks, master clock resynchronization logic, and deglitch logic. The outputs from each digital clock tree can be routed into the digital system interconnect and then brought back into the clock system as an input, allowing clock chaining of up to 32 bits. 6.1.4 USB Clock Domain The USB clock domain is unique in that it operates largely asynchronously from the main clock network. The USB logic contains a synchronous bus interface to the chip, while running on an asynchronous clock to process USB data. The USB logic requires a 48 MHz frequency. This frequency can be generated from different sources, including DSI clock at 48 MHz or doubled value of 24 MHz from internal oscillator, DSI signal, or crystal oscillator. Page 28 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 6.2 Power System The power system consists of separate analog, digital, and I/O supply pins, labeled VDDA, VDDD, and VDDIOX, respectively. It also includes two internal 1.8-V regulators that provide the digital (VCCD) and analog (VCCA) supplies for the internal core logic. The output pins of the regulators (VCCD and VCCA) and the VDDIO pins must have capacitors connected as shown in Figure 6-4. The two VCCD pins must be shorted together, with as short a trace as possible, and connected to a 1-µF ±10-percent X5R capacitor. The power system also contains a sleep regulator, an I2C regulator, and a hibernate regulator. Figure 6-4. PSoC Power System VDDD 1 µF VDDIO2 VDDD I/O Supply VSSD VCCD VDDIO 2 VDDIO0 0.1 µF 0.1 µF I/O Supply VDDIO0 0.1 µF I2C Regulator Sleep Regulator Digital Domain VDDA VDDA VCCA Analog Regulator Digital Regulators VSSD 0.1 µF 1 µF . VSSA Analog Domain 0.1 µF I/O Supply VDDIO3 VDDD VSSD I/O Supply VCCD VDDIO1 Hibernate Regulator 0.1 µF 0.1 µF VDDIO1 VDDD VDDIO3 Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as shown in Figure 2-6 on page 9. You can power the device in internally regulated mode, where the voltage applied to the VDDx pins is as high as 5.5 V, and the internal regulators provide the core voltages. In this mode, do not apply power to the VCCx pins, and do not tie the VDDx pins to the VCCx pins. You can also power the device in externally regulated mode, that is, by directly powering the VCCD and VCCA pins. In this configuration, the VDDD pins should be shorted to the VCCD pins and the VDDA pin should be shorted to the VCCA pin. The allowed supply range in this configuration is 1.71 V to 1.89 V. After power up in this configuration, the internal regulators are on by default, and should be disabled to reduce power consumption. Document Number: 001-57331 Rev. *G Page 29 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 6.2.1 Power Modes PSoC 3 devices have four different power modes, as shown in Table 6-2 and Table 6-3. The power modes allow a design to easily provide required functionality and processing power while simultaneously minimizing power consumption and maximizing battery life in low-power and portable devices. PSoC 3 power modes, in order of decreasing power consumption are:  Active  Alternate Active  Sleep Active is the main processing mode. Its functionality is configurable. Each power controllable subsystem is enabled or disabled by using separate power configuration template registers. In alternate active mode, fewer subsystems are enabled, reducing power. In sleep mode most resources are disabled regardless of the template settings. Sleep mode is optimized to provide timed sleep intervals and Real Time Clock functionality. The lowest power mode is hibernate, which retains register and SRAM state, but no clocks, and allows wakeup only from I/O pins. Figure 6-5 on page 31 illustrates the allowable transitions between power modes. Sleep and hibernate modes should not be entered until all VDDIO supplies are at valid voltage levels.  Hibernate Table 6-2. Power Modes Power Modes Description Active Primary mode of operation, all peripherals available (programmable) Alternate Active Entry Condition Wakeup Source Active Clocks Regulator Wakeup, reset, Any interrupt Any All regulators available. manual register (programmable) Digital and analog entry regulators can be disabled if external regulation used. Manual register Any interrupt Any All regulators available. entry (programmable) Digital and analog regulators can be disabled if external regulation used. Similar to Active mode, and is typically configured to have fewer peripherals active to reduce power. One possible configuration is to use the UDBs for processing, with the CPU turned off All subsystems automatically Manual register disabled entry Sleep Manual register All subsystems automatically entry disabled Lowest power consuming mode with all peripherals and internal regulators disabled, except hibernate regulator is enabled Configuration and memory contents retained Hibernate Comparator, ILO/kHzECO PICU, I2C, RTC, CTW, LVD PICU Both digital and analog regulators buzzed. Digital and analog regulators can be disabled if external regulation used. Only hibernate regulator active. Table 6-3. Power Modes Wakeup Time and Power Consumption Sleep Modes Active Alternate Active Sleep Wakeup Time Current (typ) Code Execution Digital Resources Analog Resources Clock Sources Available Wakeup Sources Reset Sources – 1.2 mA[11] Yes All All All – All – – User defined All All All – All 3.6 V – 1.1 – mA – 0.7 – mA – 10 – pA Analog current consumption while device is reset [28] Input bias current [28] T = 25 °C Notes 27. If Vccd and Vcca are externally regulated, the voltage difference between Vccd and Vcca must be less than 50 mV. 28. Based on device characterization (not production tested). USBIO pins tied to ground (VSSD). Document Number: 001-57331 Rev. *G Page 69 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 11-1. Active Mode Current vs FCPU, VDD = 3.3 V, Temperature = 25 °C Document Number: 001-57331 Rev. *G Page 70 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Table 11-3. AC Specifications[29] Parameter FCPU Description CPU frequency Conditions Min Typ Max Units 1.71 V  Vddd  5.5 V, -40°C  Ta  85°C and Tj  100°C DC – 50 MHz 1.71 V  Vddd  5.5 V, -40°C  Ta  125°C and Tj  150°C DC – 50 MHz 1.71 V  Vddd  5.5 V, -40°C  Ta  85°C and Tj  100°C DC – 50 MHz 1.71 V  Vddd  5.5 V, -40°C  Ta  125°C and Tj  150°C DC – 50 MHz Fbusclk Bus frequency Svdd Vdd ramp rate – – 0.066 V/µs Tio_init Time from Vddd/Vdda/Vccd/Vcca  IPOR to I/O ports set to their reset states – – 10 µs Time from Vddd/Vdda/Vccd/Vcca  Vcca/Vccd = regulated from PRES to CPU executing code at Vdda/Vddd, no PLL used, slow reset vector IMO boot mode (12 MHz typ.) – – 66 µs Tsleep Wakeup from sleep mode - Occur- 1.71 V  Vddd  5.5 V, Tj  100°C rence of LVD interrupt to beginning of execution of next CPU instruction – – 15 µs Thibernate Wakeup from hibernate mode Application of external interrupt to beginning of execution of next CPU instruction – – 100 µs Tstartup Figure 11-2. Fcpu vs. Vdd Vdd Voltage 5.5V Valid Operating Region 3.3V 1.71V 0V DC 1 MHz 10 MHz 50 MHz CPU Frequency Note 29. Based on device characterization (not production tested). Document Number: 001-57331 Rev. *G Page 71 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.3 Power Regulators Specifications are valid for -40°C  Ta  125°C and Tj  150°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.3.1 Digital Core Regulator Table 11-4. Digital Core Regulator DC Specifications Parameter Description Vddd Input voltage Vccd Output voltage Regulator output capacitance Conditions Min Typ Max Units 1.8 - 5.5 V - 1.80 - V - 1 - µF Total capacitance on the two Vccd pins. Each capacitor is ±10%, X5R ceramic or better, see Power System on page 29 Figure 11-3. Regulators VCC vs VDD Figure 11-4. Digital Regulator PSRR vs Frequency and VDD Document Number: 001-57331 Rev. *G Page 72 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.3.2 Analog Core Regulator Table 11-5. Analog Core Regulator DC Specifications Parameter Description Vdda Input voltage Vcca Output voltage Regulator output capacitor Conditions Min Typ Max 1.8 - 5.5 V - 1.80 - V - 1 - µF ±10%, X5R ceramic or better (X7R for Ta > 85°C) Units Figure 11-5. Analog Regulator PSRR vs Frequency and VDD Document Number: 001-57331 Rev. *G Page 73 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.4 Inputs and Outputs Specifications are valid for -40°C  Ta  125°C and Tj  150°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.4.1 GPIO Table 11-6. GPIO DC Specifications Parameter Description Vih Input voltage high threshold Vil Input voltage low threshold Vih Input voltage high threshold Vih Input voltage high threshold Vil Input voltage low threshold Vil Input voltage low threshold Voh Output voltage high Vol Output voltage low Rpullup Pull up resistor Rpulldown Pull down resistor Iil Input leakage current (absolute value)[30] CIN Input capacitance[30] Conditions Min CMOS Input, PRT[x]CTL = 0 0.7  Vddio CMOS Input, PRT[x]CTL = 0 LVTTL Input, PRT[x]CTL = 1,Vddio 0.7 x Vddio < 2.7 V LVTTL Input, PRT[x]CTL = 1, Vddio 2.0 V LVTTL Input, PRT[x]CTL = 1,Vddio < 2.7 V Typ - LVTTL Input, PRT[x]CTL = 1, Vddio V Ioh = 4 mA at 3.3 Vddio Vddio - 0.6 Ioh = 1 mA at 1.8 Vddio Vddio - 0.5 Iol = 6 mA at 3.3 Vddio – Iol = 3 mA at 1.8 Vddio – Iol = 3 mA at 3.3 Vddio – 3.5 3.5 Max Units V 0.3 Vddio V V - - V - 0.3 x Vddio V - 0.8 V – – – 5.6 5.6 0.6 0.6 0.4 8.5 8.5 V V V V V k k 25°C, Vddio = 3.0 V - - 2 nA GPIOs not shared with opamp outputs, MHz ECO or kHzECO GPIOs shared with MHz ECO or kHzECO[31] – 4 7 pF – 5 7 pF GPIOs shared with opamp outputs – – 18 pF Vh Input voltage hysteresis (Schmitt-Trigger)[30] - 40 - mV Idiode Current through protection diode to Vddio and Vssio Resistance pin to analog global bus Resistance pin to analog mux bus - - 100 µA – – 320 220 – –   Rglobal Rmux 25°C, Vddio = 3.0 V 25°C, Vddio = 3.0 V Notes 30. Based on device characterization (Not production tested). 31. For information on designing with PSoC 3 oscillators, refer to the application note, AN54439 - PSoC® 3 and PSoC 5 External Oscillator. Document Number: 001-57331 Rev. *G Page 74 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 11-6. GPIO Output High Voltage and Current Figure 11-7. GPIO Output Low Voltage and Current Document Number: 001-57331 Rev. *G Page 75 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Table 11-7. GPIO AC Specifications Parameter TriseF TfallF TriseS TfallS Fgpioout Fgpioin Description Rise time in Fast Strong Mode[29] Fall time in Fast Strong Mode[29] Rise time in Slow Strong Mode[29] Fall time in Slow Strong Mode[29] GPIO output operating frequency 3 V < Vddio < 5.5 V, fast strong drive mode Min – – – – Typ – – – – Max 12 12 60 60 Units ns ns ns ns 90/10% Vddio into 25 pF, -40°C  Ta  85°C and Tj  100°C 90/10% Vddio into 25 pF, -40°C  Ta  125°C and Tj  150°C - - 33 MHz - - 24 MHz 1.71 V < Vddio < 3 V, fast strong drive 90/10% Vddio into 25 pF, -40°C  mode Ta  85°C and Tj  100°C - - 20 MHz 90/10% Vddio into 25 pF, -40°C  Ta  125°C and Tj  150°C 3 V < Vddio < 5.5 V, slow strong drive 90/10% Vddio into 25 pF, -40°C  mode Ta  85°C and Tj  100°C 90/10% Vddio into 25 pF, -40°C  Ta  125°C and Tj  150°C 1.71 V < Vddio < 3 V, slow strong drive 90/10% Vddio into 25 pF, -40°C  mode Ta  85°C and Tj  100°C 90/10% Vddio into 25 pF, -40°C  Ta  125°C and Tj  150°C GPIO input operating frequency - - 16 MHz - - 7 MHz - - 7 MHz - - 3.5 MHz - - 3.5 MHz 90/10% better than 60/40 duty cycle, -40°C  Ta  85°C and Tj  100°C 90/10% better than 60/40 duty cycle, -40°C  Ta  125°C and Tj  150°C - - 66 MHz - - 50 MHz 1.71 V < Vddio < 5.5 V Document Number: 001-57331 Rev. *G Conditions 3 V Vddio Cload = 25 pF 3 V Vddio Cload = 25 pF 3 V Vddio Cload = 25 pF 3 V Vddio Cload = 25 pF Page 76 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.4.2 SIO Table 11-8. SIO DC Specifications Parameter Description Min Typ Max Units – – 5.5 V 0.5 - 0.52 Vddio V Vddio > 3.7 1 - Vddio-1 V Vddio < 3.7 1 - Vddio - 0.5 V GPIO mode CMOS input 0.7  Vddio - - V Differential input mode With hysteresis SIO_ref + 0.2 – – V Vinmax Maximum input voltage Vinref Input voltage reference (Differential input mode) Conditions All allowed values of Vddio and Vddd Output voltage reference (Regulated output mode) Voutref Input voltage high threshold Vih Input voltage low threshold Vil GPIO mode CMOS input - - 0.3 Vddio V Differential input mode With hysteresis – – SIO_ref – 0.2 V Vddio - 0.4 - - V SIO_ref 0.65 - SIO_ref + 0.2 V SIO_ref - 0.3 - SIO_ref + 0.2 V Vddio = 3.30 V, Iol = 25 mA - - 0.8 V Vddio = 1.80 V, Iol = 4 mA - - 0.4 V Output voltage high Voh Unregulated mode Ioh = 4 mA, Vddio = 3.3 V Regulated mode [32] Ioh = 1 mA Regulated mode [32] Ioh = 0.1 mA Output voltage low Vol VDDIO = 3.3 V, IOL = 20 mA Rpullup Rpulldown Iil – – 0.4 V Pull up resistor 3.5 5.6 8.5 k Pull down resistor 3.5 5.6 8.5 k Input leakage current (absolute value)[33] Vih < Vddsio 25°C, Vddsio = 3.0 V, Vih = 3.0 V - - 14 nA Vih > Vddsio 25°C, Vddsio = 0 V, Vih = 3.0 V - - 10 µA - - 7 pF Cin Input Capacitance[33] Vh Input voltage hysteresis (Schmitt-Trigger)[33] Idiode Current through protection diode to Vssio Single ended mode (GPIO mode) – 40 – mV Differential mode – 35 – mV - - 100 µA Notes 32. See Figure 6-8 on page 35for more information on SIO reference. 33. Based on device characterization (not production tested). Document Number: 001-57331 Rev. *G Page 77 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 11-8. SIO Output High Voltage and Current, Unregulated Mode Figure 11-9. SIO Output Low Voltage and Current, Unregulated Mode Figure 11-10. SIO Output High Voltage and Current, Regulated Mode Document Number: 001-57331 Rev. *G Page 78 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Table 11-9. SIO AC Specifications Parameter Description Conditions Min Typ Max Units TriseF Rise time in Fast Strong Mode (90/10%)[29] Cload = 25 pF, Vddio = 3.3 V – – 12 ns TfallF Fall time in Fast Strong Mode (90/10%)[29] Cload = 25 pF, Vddio = 3.3 V – – 12 ns TriseS Rise time in Slow Strong Mode (90/10%)[29] Cload = 25 pF, Vddio = 3.0 V – – 80 ns TfallS Fall time in Slow Strong Mode (90/10%)[29] Cload = 25 pF, Vddio = 3.0 V – – 70 ns - - 33 MHz - - 24 MHz 1.71 V < Vddio < 3.3 V, Unregulated 90/10% Vddio into 25 pF output (GPIO) mode, fast strong drive mode - - 16 MHz 3.3 V < Vddio < 5.5 V, Unregulated 90/10% Vddio into 25 pF output (GPIO) mode, slow strong drive mode - - 5 MHz 1.71 V < Vddio < 3.3 V, Unregulated 90/10% Vddio into 25 pF output (GPIO) mode, slow strong drive mode - - 4 MHz 3.3 V < Vddio < 5.5 V, Regulated Output continuously switching into output mode, fast strong drive mode 25 pF - - 20 MHz 1.71 V < Vddio < 3.3 V, Regulated Output continuously switching into output mode, fast strong drive mode 25 pF - - 10 MHz 1.71 V < Vddio < 5.5 V, Regulated Output continuously switching into 25 pF output mode, slow strong drive mode - - 2.5 MHz 90/10% better than 60/40 duty cycle, -40°C  Ta  85°C and Tj  100°C - - 66 MHz 90/10% better than 60/40 duty cycle, -40°C  Ta  125°C and Tj  150°C - - 50 MHz SIO output operating frequency 3.3 V < Vddio < 5.5 V, Unregulated 90/10% Vddio into 25 pF, -40°C  Ta  85°C and Tj  100°C output (GPIO) mode, fast strong drive mode 90/10% Vddio into 25 pF, -40°C  Ta  125°C and Tj  150°C Fsioout SIO input operating frequency Fsioin 1.71 V < Vddio < 5.5 V Document Number: 001-57331 Rev. *G Page 79 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 11-11. SIO Output Rise and Fall Times, Fast Strong Mode, VDDIO = 3.3 V, 25 pF Load Figure 11-12. SIO Output Rise and Fall Times, Slow Strong Mode, VDDIO = 3.3 V, 25 pF Load Document Number: 001-57331 Rev. *G Page 80 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.4.3 USBIO Table 11-10. USBIO DC Specifications Parameter Description Conditions Min Typ Max Units Rusbi USB D+ pull up resistance With idle bus 0.900 - 1.575 k Rusba USB D+ pull up resistance While receiving traffic 1.425 - 3.090 k Vohusb Static output high 15 k ±5% to Vss, internal pull up enabled 2.8 - 3.6 V Volusb Static output low 15 k ±5% to Vss, internal pull up enabled - - 0.3 V Vihgpio Input voltage high, GPIO mode VDDD 3 V 2 – – V Vilgpio Input voltage low, GPIO mode VDDD 3 V – – 0.8 V Vohgpio Output voltage high, GPIO mode Ioh = 4 mA, Vddio  3 V 2.4 - - V Volgpio Output voltage low, GPIO mode Iol = 4 mA, Vddio  3 V - - 0.3 V Vdi Differential input sensitivity |(D+)-(D-)| - - 0.2 V Vcm Differential input common mode range 0.8 - 2.5 V Vse Single ended receiver threshold 0.8 - 2 V Rps2 PS/2 pull up resistance In PS/2 mode, with PS/2 pull up enabled 3 - 7 k External USB series resistor In series with each USB pin 21.78 (-1%) 22 22.22 (+1%)  USB driver output impedance Including Rext, -40°C  Ta  85°C and Tj  100°C 28 - 44  Including Rext, -40°C  Ta  125°C and Tj  150°C 28 - 46  - - 20 pF - - 2 nA Rext Zo Cin Iil [34] USB transceiver input capacitance Input leakage current (absolute value) 25°C, Vddio = 3.0 V Note 34. Based on device characterization (not production tested). Document Number: 001-57331 Rev. *G Page 81 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 11-13. USBIO Output High Voltage and Current, GPIO Mode Figure 11-14. USBIO Output Low Voltage and Current, GPIO Mode Document Number: 001-57331 Rev. *G Page 82 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Table 11-11. USBIO AC Specifications Parameter Description Conditions Min Typ Max Units Tdrate Full-speed data rate average bit rate 12 - 0.25% 12 12 + 0.25% MHz Tdjr1 Receiver data jitter tolerance to next transition -8 - 8 ns Tdjr2 Receiver data jitter tolerance to pair transition -5 - 5 ns Tudj1 Driver differential jitter to next transition -3.5 - 3.5 ns Tudj2 Driver differential jitter to pair transition -4 - 4 ns Tfdeop Source jitter for differential transition to SE0 transition -2 - 5 ns Tfeopt Source SE0 interval of EOP 160 - 175 ns Tfeopr Receiver SE0 interval of EOP 82 - - ns Tfst Width of SE0 interval during differential transition - - 14 ns Fgpio_out GPIO mode output operating frequency 3 V  Vddd  5.5 V - - 20 MHz Vddd = 1.71 V - - 6 MHz Tr_gpio Rise time, GPIO mode, 10%/90% Vddd Vddd > 3 V, 25 pF load – – 12 ns Tf_gpio Fall time, GPIO mode, 90%/10% Vddd Vddd > 3 V, 25 pF load Vddd = 1.71 V, 25 pF load Vddd = 1.71 V, 25 pF load – – 40 ns – – 12 ns – – 40 ns Figure 11-15. USBIO Output Rise and Fall Times, GPIO Mode, VDDD = 3.3 V, 25 pF Load Table 11-12. USB Driver AC Specifications Parameter Description Tr Transition rise time Tf Transition fall time TR Rise/fall time matching Vcrs Output signal crossover voltage Document Number: 001-57331 Rev. *G Conditions VUSB_5, VUSB_3.3, see Min Typ Max Units – – 20 ns ns – – 20 90% - 111% 1.3 - 2 V Page 83 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.4.4 XRES Table 11-13. XRES DC Specifications Parameter Description Conditions Min Typ Max Units Vih Input voltage high threshold CMOS Input, PRT[x]CTL = 0 0.7  Vddio - - V Vil Input voltage low threshold CMOS Input, PRT[x]CTL = 0 - - 0.3 Vddio V Rpullup Pull up resistor 3.5 5.6 8.5 k Cin Input capacitance[29] - 3 - pF Vh Input voltage hysteresis (Schmitt-Trigger)[29] - 100 - mV Idiode Current through protection diode to Vddio and Vssio - - 100 µA Min Typ Max Units 1 - - µs Table 11-14. XRES AC Specifications Parameter Treset Description Reset pulse width Document Number: 001-57331 Rev. *G Conditions Page 84 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.5 Analog Peripherals Specifications are valid for -40°C  Ta  125°C and Tj  150°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.5.1 Opamp Table 11-15. Opamp DC Specifications Parameter Description Vioff Input offset voltage TCVos Ge1 Vi Vo Iout Iout Input offset voltage drift with temperature Gain error, unity gain buffer mode Input voltage range Output voltage range Output current Output current IDD Quiescent current CMRR PSRR Common mode rejection ratio[29] Power supply rejection ratio Conditions -40°C  Ta  85°C and Tj  100°C -40°C  Ta  125°C and Tj  150°C Power mode = high Rload = 1 k Output load = 1 mA Output voltage is between Vssa +500 mV and Vdda -500 mV, and Vdda > 2.7 V, -40°C  Ta  85°C and Tj  100°C Output voltage is between Vssa +500 mV and Vdda -500 mV, and Vdda > 2.7 V, -40°C  Ta  125°C and Tj  150°C Output voltage is between Vssa +500 mV and Vdda -500 mV, and Vdda > 1.7 V and Vdda < 2.7 V Power mode = min Power mode = low Power mode = med Power mode = high Vdda  2.7 V Vdda < 2.7 V Min - Typ - Max ±2.5 ±5.0 Units mV mV – Vssa Vssa + 50 25 – ±30 µV / °C - +0.1 Vdda Vdda - 50 - % mV mV mA 20 - - mA 16 - - mA – – – – 80 85 70 250 250 330 1000 – – – 400 400 950 2500 – – – µA µA µA µA dB dB dB Figure 11-16. Opamp Voffset Histogram, 3388 samples/847 parts, 25 °C, Vdda = 5 V Document Number: 001-57331 Rev. *G Page 85 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 11-17. Opamp Voffset vs Temperature, Vdda = 5 V Figure 11-18. Opamp Voffset vs Vcommon and Vdda, 25 °C Figure 11-19. Opamp Output Voltage vs Load Current and Temperature, High Power Mode, 25 °C, Vdda = 2.7 V Document Number: 001-57331 Rev. *G Page 86 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 11-20. Opamp Operating Current vs Vdda and Power Mode Table 11-16. Opamp AC Specifications Parameter Description GBW Gain-bandwidth product SR Slew rate, 20% - 80% en Input noise density Conditions Power mode = minimum, 15 pF load Power mode = low, 15 pF load Power mode = medium, 200 pF load Power mode = high, 200 pF load Power mode = low, 15 pF load Power mode = medium, 200 pF load Power mode = high, 200 pF load Power mode = high, Vdda = 5 V, at 100 kHz Min 1 Typ – Max – Units MHz 2 1 – – – – MHz MHz 2.5 1.1 0.9 – – – – – – MHz V/µs V/µs 3 – – 45 – – V/µs nV/sqrtH z Figure 11-21. Opamp Noise vs Frequency, Power Mode = High, Vdda = 5 V Document Number: 001-57331 Rev. *G Page 87 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 11-22. Opamp Step Response, Rising Figure 11-23. Opamp Step Response, Falling Document Number: 001-57331 Rev. *G Page 88 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.5.2 Delta-Sigma ADC Unless otherwise specified, operating conditions are:  Operation in continuous sample mode  fclk = 6.144 MHz for resolution = 8 to 12 bits  Reference = 1.024 V internal reference bypassed on P3.2 or P0.3  Unless otherwise specified, all charts and graphs show typical values Table 11-17. 12-bit Delta-sigma ADC DC Specifications Parameter Description Conditions Resolution Number of channels, single ended Min Typ Max Units 8 – 20 bits – – No. of GPIO – Number of channels, differential Differential pair is formed using a pair of GPIOs. – – No. of GPIO/2 – Monotonic Yes – – – – Ge Gain error Buffered, buffer gain = 1, Range = ±1.024 V, 16-bit mode, 25 °C – – ±0.2 % Gd Gain drift Buffered, buffer gain = 1, Range = ±1.024 V, 16-bit mode – – 50 ppm/°C Buffered, 16-bit mode, full voltage range – – ±0.2 mV Buffered, 16-bit mode, VDDA = 1.8 V + 5% – – ±0.1 mV Buffer gain = 1, 16-bit, Range = ±1.024 V – – 1 µV/°C Input voltage range, single ended[35] VSSA – VDDA V Input voltage range, differential unbuffered[35] VSSA – VDDA V Input voltage range, differential, buffered[35] VSSA – VDDA – 1 V Vos TCVos Input offset voltage Temperature coefficient, input offset voltage PSRRb Power supply rejection ratio, buffered[35] Buffer gain = 1, 16-bit, Range = ±1.024 V 90 – – dB CMRRb Common mode rejection ratio, buffered[35] Buffer gain = 1, 16 bit, Range = ±1.024 V 85 – – dB INL12 Integral non linearity[35] Range = ±1.024 V, unbuffered – – ±1 LSB DNL12 Differential non linearity[35] Range = ±1.024 V, unbuffered – – ±1 LSB Range = ±1.024 V, unbuffered – – ±1 LSB Range = ±1.024 V, unbuffered – – ±1 LSB linearity[35] INL8 Integral non DNL8 Differential non linearity[35] Note 35. Based on device characterization (not production tested). Document Number: 001-57331 Rev. *G Page 89 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Table 11-17. 12-bit Delta-sigma ADC DC Specifications (continued) Parameter Min Typ Max Units Input buffer used 10 – – M Rin_ADC12 ADC input resistance Input buffer bypassed, 12 bit, Range = ±1.024 V – 148[36] – k Vextref Pins P0[3], P3[2] 0.9 – 1.3 V – – 1.95 mA – – 2.5 mA Rin_Buff Description ADC input resistance ADC external reference input voltage Conditions Current Consumption IDD_12 IBUFF IDDD + IDDA Current consumption, 12 bit [37] 192 ksps, unbuffered Buffer current consumption [37] Notes 36. By using switched capacitors at the ADC input an effective input resistance is created. Holding the gain and number of bits constant, the resistance is proportional to the inverse of the clock frequency. This value is calculated, not measured. For more information see the Technical Reference Manual. 37. Based on device characterization (Not production tested). Document Number: 001-57331 Rev. *G Page 90 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Table 11-18. Delta-sigma ADC AC Specifications Parameter Description Conditions Startup time Total harmonic distortion[37] THD Min Typ Max Units – – 4 Samples Buffer gain = 1, 16 bit, Range = ±1.024 V – – 0.0040 % 12-Bit Resolution Mode SR12 Sample rate, continuous, high power[37] Range = ±1.024 V, unbuffered 4 – 192 ksps BW12 Input bandwidth at max sample rate[37] Range = ±1.024 V, unbuffered – 44 – kHz SINAD12int Signal to noise ratio, 12-bit, internal reference[37] Range = ±1.024 V, unbuffered 66 – – dB Range = ±1.024 V, unbuffered 8 – 384 ksps Range = ±1.024 V, unbuffered – 88 – kHz Range = ±1.024 V, unbuffered 43 – – dB 8-Bit Resolution Mode Sample rate, continuous, high power[37] SR8 rate[37] BW8 Input bandwidth at max sample SINAD8int Signal to noise ratio, 8-bit, internal reference[37] Table 11-19. Delta-sigma ADC Sample Rates, Range = ±1.024 V Continuous Multi-Sample Multi-Sample Turbo Resolution, Bits Min Max Min Max Min Max 8 8000 384000 1911 91701 1829 87771 9 6400 307200 1543 74024 1489 71441 10 5566 267130 1348 64673 1307 62693 11 4741 227555 1154 55351 1123 53894 12 4000 192000 978 46900 956 45850 Document Number: 001-57331 Rev. *G Page 91 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 11-24. Delta-sigma ADC IDD vs sps, Range = ±1.024 V, Continuous Sample Mode, Input Buffer Bypassed Document Number: 001-57331 Rev. *G Page 92 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.5.3 Voltage Reference Table 11-20. Voltage Reference Specifications Parameter Vref Description Precision reference Conditions Min Typ Max Units -40°C  Ta  85°C and Tj  100°C 1.021 (-0.3%) 1.024 1.027 (+0.3%) V -40°C  Ta  125°C and Tj  150°C 1.018 (–0.6%) 1.024 1.030 (+0.6%) V After typical PCB assembly, post reflow Typical (non-optimized) board layout and 250 °C solder reflow. Device may be calibrated after assembly to improve performance. –40 °C ±0.5 % 25 °C ±0.2 % 85 °C Temperature drift[38] Box method ±0.2 % – – 30 ppm/°C Long term drift – 100 – ppm/khr Thermal cycling drift (stability)[38, 39] – 100 – ppm Figure 11-25. Voltage Reference vs. Temperature and VCCA Figure 11-26. Voltage Reference Long-Term Drift Notes 38. Based on device characterization (Not production tested). 39. After eight full cycles between –40 °C and 100 °C. Document Number: 001-57331 Rev. *G Page 93 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.5.4 Analog Globals Table 11-21. Analog Globals Specifications Parameter Description Conditions Min Typ Max Units Resistance pin-to-pin through P2[4], AGL0, DSM INP, AGL1, P2[5][40] VDDA = 3 V – 1472 2200  Rppmuxbus Resistance pin-to-pin through P2[3], amuxbusL, P2[4][40] VDDA = 3 V – 706 1100  Min Typ Rppag 11.5.5 Comparator Table 11-22. Comparator DC Specifications Parameter VOS Description Conditions Input offset voltage in fast mode Factory trim, Vdda > 2.7 V, Vin  0.5 V – Input offset voltage in slow mode Factory trim, Vin  0.5 V – Input offset voltage in fast mode[41] Custom trim – Input offset voltage in slow mode[41] Custom trim Max Units 10 mV 9 mV – 4 mV – – 4 mV Input offset voltage in ultra low-power VDDA ≤ 4.6 V mode – ±12 – mV VHYST Hysteresis Hysteresis enable mode – 10 32 mV VICM Input common mode voltage High current / fast mode VSSA – VDDA V Low current / slow mode VSSA – VDDA V Ultra low-power mode VDDA ≤ 4.6 V VSSA – VDDA – 1.15 V – 50 – dB - - 400 µA CMRR Common mode rejection ratio Icmp High current mode/fast mode[29] -40°C  Ta  85°C and Tj  100°C -40°C  Ta  125°C and Tj  150°C - - 600 µA Low current mode/slow mode[29] -40°C  Ta  85°C and Tj  100°C - - 100 µA -40°C  Ta  125°C and Tj  150°C - - 150 µA Ultra low power mode[29] VDDA < 4.6 V - 6 - µA Table 11-23. Comparator AC Specifications Parameter TRESP Min Typ Max Units Response time, high current mode[42] 50 mV overdrive, measured pin-to-pin Description – 75 110 ns Response time, low current mode[42] 50 mV overdrive, measured pin-to-pin – 155 200 ns 50 mV overdrive, measured pin-to-pin, VDDA ≤ 4.6 V – 55 – µs Response time, ultra low-power mode[42] Conditions Note 40. The resistance of the analog global and analog mux bus is high if VDDA 2.7 V, and the chip is in either sleep or hibernate mode. Use of analog global and analog mux bus under these conditions is not recommended. 41. The recommended procedure for using a custom trim value for the on-chip comparators can be found in the TRM. 42. Based on device characterization (Not production tested). Document Number: 001-57331 Rev. *G Page 94 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.5.6 IDAC All specifications are based on use of the low-resistance IDAC output pins (see Pin Descriptions on page 9 for details). See the IDAC component data sheet in PSoC Creator for full electrical specifications and APIs. Unless otherwise specified, all charts and graphs show typical values. Table 11-24. IDAC (Current Digital-to-Analog Converter) DC Specifications Parameter Description Conditions Resolution IOUT Output current at code = 255 DNL Integral nonlinearity Differential nonlinearity Typ Max Units - 8 - Range = 2.04 mA, code = 255, VDDA  2.7 V, Rload = 600  – 2.04 – mA Range = 2.04 mA, high speed mode, code = 255, VDDA  2.7 V, Rload = 300  – 2.04 – mA Range = 255 µA, code = 255, Rload = 600  – 255 – µA Range = 31.875 µA, code = 255, Rload = 600  – 31.875 – µA – – Yes Sink mode, range = 255 µA, Codes 8 – 255, Rload = 2.4 k, Cload = 15 pF – ±0.9 ±1 LSB Source mode, range = 255 µA, Codes 8 – 255, Rload = 2.4 k, Cload = 15 pF – ±1.2 ±1.5 LSB Sink mode, range = 255 µA, Rload = 2.4 k, Cload = 15 pF – ±0.3 ±1 LSB Source mode, range = 255 µA, Rload = 2.4 k, Cload = 15 pF – ±0.3 ±1 LSB - 0 ±1 LSB Monotonicity INL Min Ezs Zero scale error -40°C  Ta  85°C and Tj  100°C -40°C  Ta  125°C and Tj  150°C - - ±2 LSB Eg Gain error Range = 2.04 mA, 25 °C – – ±2.5 % TC_Eg Range = 255 µA, 25 ° C – – ±2.5 % Range = 31.875 µA, 25 ° C – – ±3.5 % – – 0.04 % / °C – – 0.04 % / °C – – 0.05 % / °C 1 – – V Temperature coefficient of gain error Range = 2.04 mA Range = 255 µA Range = 31.875 µA Vcompliance Dropout voltage, source or sink mode Voltage headroom at max current, Rload to Vdda or Rload to Vssa, Vdiff from Vdda Document Number: 001-57331 Rev. *G Page 95 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Table 11-24. IDAC (Current Digital-to-Analog Converter) DC Specifications (continued) Parameter IDD Description Operating current, code = 0 Conditions Min Typ Max Units Low speed mode, source mode, range = 31.875 µA – 44 100 µA Low speed mode, source mode, range = 255 µA, – 33 100 µA Low speed mode, source mode, range = 2.04 mA – 33 100 µA Low speed mode, sink mode, range = 31.875 µA – 36 100 µA Low speed mode, sink mode, range = 255 µA – 33 100 µA Low speed mode, sink mode, range = 2.04 mA – 33 100 µA High speed mode, source mode, range = 31.875 µA – 310 500 µA High speed mode, source mode, range = 255 µA – 305 500 µA High speed mode, source mode, range = 2.04 mA – 305 500 µA High speed mode, sink mode, range = 31.875 µA – 310 500 µA High speed mode, sink mode, range = 255 µA – 300 500 µA High speed mode, sink mode, range = 2.04 mA – 300 500 µA Figure 11-27. IDAC INL vs Input Code, Range = 255 µA, Source Mode Document Number: 001-57331 Rev. *G Page 96 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 11-28. IDAC INL vs Input Code, Range = 255 µA, Sink Mode Figure 11-29. IDAC DNL vs Input Code, Range = 255 µA, Source Mode Figure 11-30. IDAC DNL vs Input Code, Range = 255 µA, Sink Mode Document Number: 001-57331 Rev. *G Page 97 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 11-31. IDAC INL vs Temperature, Range = 255 µA, High speed mode Figure 11-32. IDAC DNL vs Temperature, Range = 255 µA, High speed mode Figure 11-33. IDAC Full Scale Error vs Temperature, Range = 255 µA, Source Mode Document Number: 001-57331 Rev. *G Page 98 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 11-34. IDAC Full Scale Error vs Temperature, Range = 255 µA, Sink Mode Figure 11-35. IDAC Operating Current vs Temperature, Range = 255 µA, Code = 0, Source Mode Figure 11-36. IDAC Operating Current vs Temperature, Range = 255 µA, Code = 0, Sink Mode Document Number: 001-57331 Rev. *G Page 99 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Table 11-25. IDAC (Current Digital-to-Analog Converter) AC Specifications Parameter Description Conditions Min Typ Max Units Fdac Update rate – – 8 Msps TSETTLE Settling time to 0.5 LSB Range = 31.875 µA or 255 µA, full scale transition, High speed mode, 600  15-pF load – – 125 ns Current noise Range = 255 µA, source mode, High speed mode, Vdda = 5 V, 10 kHz – 340 – pA/sqrtHz Figure 11-37. IDAC Step Response, Codes 0x40 - 0xC0, 255 µA Mode, Source Mode, High speed mode, Vdda = 5 V Figure 11-38. IDAC Glitch Response, Codes 0x7F - 0x80, 255 µA Mode, Source Mode, High speed mode, Vdda = 5 V Document Number: 001-57331 Rev. *G Page 100 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 11-39. IDAC PSRR vs Frequency Figure 11-40. IDAC Current Noise, 255 µA Mode, Source Mode, High speed mode, Vdda = 5 V Document Number: 001-57331 Rev. *G Page 101 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.5.7 VDAC Table 11-26. VDAC (Voltage Digital-to-Analog Converter) DC Specifications Parameter Description Conditions Min Typ Max - 8 - - 16 - k Resolution Units Output resistance[29] Rout High Vout = 4 V Vout = 1 V - 4 - k Vout Output voltage range, code = 255 Low 1 V scale – 1.02 – V 4 V scale, Vdda = 5 V – 4.08 – V INL Integral nonlinearity 1 V scale – ±2.1 ±2.5 LSB DNL Differential nonlinearity 1 V scale – ±0.3 ±1 LSB – – Yes – Eg Gain error 1 V scale, – – ±2.5 % 4 V scale – – ±2.5 % TC_Eg Temperature coefficient, gain error 1 V scale, – – 0.03 %FSR / °C 4 V scale – – 0.03 %FSR / °C VDAC_ICC Operating current Low speed mode – – 100 µA High speed mode – – 500 µA – 0 ±0.9 LSB Monotonicity VOS Zero scale error Figure 11-41. VDAC INL vs Input Code, 1 V Mode Document Number: 001-57331 Rev. *G Page 102 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 11-42. VDAC DNL vs Input Code, 1 V Mode Figure 11-43. VDAC INL vs Temperature, 1 V Mode Figure 11-44. VDAC DNL vs Temperature, 1 V Mode Document Number: 001-57331 Rev. *G Page 103 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 11-45. VDAC Full Scale Error vs Temperature, 1 V Mode Figure 11-46. VDAC Full Scale Error vs Temperature, 4 V Mode Figure 11-47. VDAC Operating Current vs Temperature, 1V Mode, Low speed mode Document Number: 001-57331 Rev. *G Page 104 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 11-48. VDAC Operating Current vs Temperature, 1 V Mode, High speed mode Document Number: 001-57331 Rev. *G Page 105 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Table 11-27. VDAC (Voltage Digital-to-Analog Converter) AC Specifications Parameter Fdac TsettleP TsettleN Description Conditions Min Typ - - Max Units 1 Msps 250 Ksps [29] Update rate 1 V mode Update rate[29] 4 V mode Settling time to 0.1%, step 25% to 75% 1 V scale, Cload = 15 pF – 0.45 1 µs 4 V scale, Cload = 15 pF – 0.8 3.2 µs Settling time to 0.1%, step 75% to 25% 1 V scale, Cload = 15 pF – 0.45 1 µs 4 V scale, Cload = 15 pF – 0.7 3 µs Voltage noise Range = 1 V, High speed mode, Vdda = 5 V, 10 kHz – 750 – nV/sqrtHz Figure 11-49. VDAC Step Response, Codes 0x40 - 0xC0, 1 V Mode, High speed mode, Vdda = 5 V Figure 11-50. VDAC Glitch Response, Codes 0x7F - 0x80, 1 V Mode, High speed mode, Vdda = 5 V Document Number: 001-57331 Rev. *G Page 106 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 11-51. VDAC PSRR vs Frequency Figure 11-52. VDAC Voltage Noise, 1 V Mode, High speed mode, Vdda = 5 V Document Number: 001-57331 Rev. *G Page 107 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.5.8 Discrete and Continuous Time Mixer The mixer is created using a SC/CT analog block; see the Mixer component data sheet in PSoC Creator for full electrical specifications and APIs. Table 11-28. Mixer DC Specifications Parameter VOS G Description Conditions Min Typ Max Units Input offset voltage – – 15 mV Quiescent current – 0.9 2 mA Gain – 0 – dB Min Typ Max Units – – 4 MHz Table 11-29. Mixer AC Specifications Parameter Description Conditions fLO Local oscillator frequency fin Input signal frequency Down mixer mode – – 14 MHz fLO Local oscillator frequency Up mixer mode – – 1 MHz fin Input signal frequency Up mixer mode SR Slew rate Down mixer mode – – 1 MHz 3 – – V/µs Note 43. Bandwidth is guaranteed for input common mode between 0.3 V and Vdda-1.2 V and for output that is between 0.05 V and Vdda-0.05 V. Document Number: 001-57331 Rev. *G Page 108 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.5.9 Transimpedance Amplifier The TIA is created using a SC/CT Analog Block, see the TIA component data sheet in PSoC Creator for full AC/DC specifications, and APIs and example code. Table 11-30. Transimpedance Amplifier (TIA) DC Specifications Parameter Vioff Description Conversion Rconv Conditions Input offset voltage Min Typ Max Units - - 10 mV resistance[44] R = 20K 40 pF load -25 - +35 % R = 30K 40 pF load -25 - +35 % R = 40K 40 pF load -25 - +35 % R = 80K 40 pF load -25 - +35 % R = 120K 40 pF load -25 - +35 % R = 250K 40 pF load -25 - +35 % R= 500K 40 pF load -25 - +35 % R = 1M 40 pF load -25 - +35 % – 1.1 2 mA Min 1000 220 25 Typ – – – Max – – – Units kHz kHz kHz Quiescent current Table 11-31. Transimpedance Amplifier (TIA) AC Specifications Parameter BW Description Input bandwidth (–3 dB) Conditions R = 20K; –40 pF load R = 120K; –40 pF load R = 1M; –40 pF load Note 44. Conversion resistance values are not calibrated. Calibrated values and details about calibration are provided in PSoC Creator component data sheets. External precision resistors can also be used. Document Number: 001-57331 Rev. *G Page 109 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.5.10 Programmable Gain Amplifier The PGA is created using a SC/CT Analog Block, see the PGA component data sheet in PSoC Creator for full AC/DC specifications, and APIs and example code. Unless otherwise specified, operating conditions are:  Operating temperature = 25 °C for typical values  Unless otherwise specified, all charts and graphs show typical values Table 11-32. PGA DC Specifications Parameter Description Conditions Min Typ Max Units Vssa – Vdda V – – 10 mV Rin of 40K, -40°C  Ta  85°C and Tj  100°C – – ±0.15 % Rin of 40K, -40°C  Ta  125°C and Tj  150°C – – ±0.15 % Rin of 40K, -40°C  Ta  85°C and Tj  100°C – – ±2.5 % Rin of 40K, -40°C  Ta  125°C and Tj  150°C – – ±4 % Rin of 40K, -40°C  Ta  85°C and Tj  100°C – – ±5 % Rin of 40K, -40°C  Ta  125°C and Tj  150°C – – ±6 % Vin Input voltage range Power mode = minimum Vos Input offset voltage Power mode = high, gain = 1 Gain Error[29] Non inverting mode, reference = Vssa Gain = 1 Ge1 Ge16 Ge50 Gain = 16 Gain = 50 TCVos Input offset voltage drift with temperature Power mode = high, gain = 1 – – ±30 µV/°C Vonl DC output nonlinearity Gain = 1 – – ±0.01 % of FSR – Cin Input capacitance – 7 pF Voh Output voltage swing VDDA – Power mode = high, gain = 1, Rload = 100 k to VDDA / 2 0.15 – – V Vol Output voltage swing Power mode = high, gain = 1, Rload = 100 k to VDDA / 2 – – VSSA + 0.15 V Vsrc Output voltage under load Iload = 250 µA, Vdda  2.7V, power mode = high – – 300 mV Idd Operating current Power mode = high – 1.5 1.65 mA PSRR Power supply rejection ratio 48 – – dB Document Number: 001-57331 Rev. *G Page 110 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 11-53. PGA Voffset Histogram, 4096 samples / 1024 parts Table 11-33. PGA AC Specifications Parameter Description Conditions Min Typ Max Units 5.5 8 – MHz BW1 –3 dB bandwidth Power mode = high, gain = 1, input = 100 mV peak-to-peak, Cl = 40 pF SR1 Slew rate Power mode = high, gain = 1, 20% to 80% 3 – – V/µs en Input noise density Power mode = high, Vdda = 5 V, at 100 kHz – 43 – nV/sqrtHz Min Typ Max Units - ±5 - °C Figure 11-54. Noise vs. Frequency, Vdda = 5 V, Power Mode = High 11.5.11 Temperature Sensor Table 11-34. Temperature Sensor Specifications Parameter Description Temp sensor accuracy Document Number: 001-57331 Rev. *G Conditions Range: –40 °C to +150 °C Page 111 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.5.12 LCD Direct Drive Table 11-35. LCD Direct Drive DC Specifications Parameter Description Conditions Min Typ Max Units Device sleep mode with wakeup at 400-Hz rate to refresh LCDs, bus clock = 3 Mhz, Vddio = Vdda = 3 V, 4 commons, 16 segments, 1/4 duty cycle, 50 Hz frame rate, no glass connected – 38 – A Current per segment driver Strong drive mode LCD bias range (VBIAS refers to the VDDA  3 V and VDDA  VBIAS main output voltage(V0) of LCD DAC) LCD bias step size VDDA  3 V and VDDA  VBIAS – 2 260 – – 5 µA V – 9.1 × VDDA – mV LCD capacitance per segment/common driver Long term segment offset Output drive current per segment driver) – 500 5000 pF – 355 – – 20 710 mV µA Min Typ Max Units 10 50 150 Hz ICC LCD system operating current ICC_SEG VBIAS IOUT Drivers may be combined Vddio = 5.5V, strong drive mode Table 11-36. LCD Direct Drive AC Specifications Parameter fLCD Description LCD frame rate Document Number: 001-57331 Rev. *G Conditions Page 112 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.6 Digital Peripherals Specifications are valid for -40°C  Ta  125°C and Tj  150°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.6.1 Timer Table 11-37. Timer DC Specifications Parameter Description Block current consumption Conditions 16-bit timer, at listed input clock frequency 3 MHz Min Typ Max Units – – – µA – 15 – µA 12 MHz – 60 – µA 50 MHz – 260 – µA Min Typ Max Units Table 11-38. Timer AC Specifications Parameter Description Operating frequency Capture pulse width (Internal) Capture pulse width (external) Timer resolution Enable pulse width Enable pulse width (external) Reset pulse width Reset pulse width (external) Conditions -40°C  Ta  85°C and Tj  100°C DC - -40°C  Ta  125°C and Tj  150°C DC - 50 [45] 50 MHz MHz -40°C  Ta  85°C and Tj  100°C 15 - - ns -40°C  Ta  125°C and Tj  150°C 21 - - ns -40°C  Ta  85°C and Tj  100°C 30 - - ns -40°C  Ta  125°C and Tj  150°C 42 - - ns -40°C  Ta  85°C and Tj  100°C 15 - - ns -40°C  Ta  125°C and Tj  150°C 21 - - ns -40°C  Ta  85°C and Tj  100°C 15 - - ns -40°C  Ta  125°C and Tj  150°C 21 - - ns -40°C  Ta  85°C and Tj  100°C 30 - - ns -40°C  Ta  125°C and Tj  150°C 42 - - ns -40°C  Ta  85°C and Tj  100°C 15 - - ns -40°C  Ta  125°C and Tj  150°C 21 - - ns -40°C  Ta  85°C and Tj  100°C 30 - - ns -40°C  Ta  125°C and Tj  150°C 42 - - ns Note 45. Applicable at -40°C to 85°C; 50 MHz at -40°C to 125°C. Document Number: 001-57331 Rev. *G Page 113 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.6.2 Counter Table 11-39. Counter DC Specifications Parameter Description Block current consumption Conditions Min Typ Max Units 16-bit counter, at listed input clock frequency – – – µA 3 MHz – 15 – µA 12 MHz – 60 – µA 50 MHz – 260 – µA Min Typ Max Units MHz MHz Table 11-40. Counter AC Specifications Parameter Description Operating frequency Capture pulse Resolution Pulse width Pulse width (external) Enable pulse width Enable pulse width (external) Reset pulse width Reset pulse width (external) Conditions -40°C  Ta  85°C and Tj  100°C DC - 50[46] -40°C  Ta  125°C and Tj  150°C DC - 50 -40°C  Ta  85°C and Tj  100°C 15 - - ns -40°C  Ta  125°C and Tj  150°C 21 - - ns -40°C  Ta  85°C and Tj  100°C 15 - - ns -40°C  Ta  125°C and Tj  150°C 21 - - ns -40°C  Ta  85°C and Tj  100°C 15 - - ns -40°C  Ta  125°C and Tj  150°C 21 - - ns -40°C  Ta  85°C and Tj  100°C 30 - - ns -40°C  Ta  125°C and Tj  150°C 42 - - ns -40°C  Ta  85°C and Tj  100°C 15 - - ns -40°C  Ta  125°C and Tj  150°C 21 - - ns -40°C  Ta  85°C and Tj  100°C 30 - - ns -40°C  Ta  125°C and Tj  150°C 42 - - ns -40°C  Ta  85°C and Tj  100°C 15 - - ns -40°C  Ta  125°C and Tj  150°C 21 - - ns -40°C  Ta  85°C and Tj  100°C 30 - - ns -40°C  Ta  125°C and Tj  150°C 42 - - ns Note 46. Applicable at -40°C to 85°C; 50 MHz at -40°C to 125°C. Document Number: 001-57331 Rev. *G Page 114 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.6.3 Pulse Width Modulation Table 11-41. PWM DC Specifications Parameter Description Block current consumption Conditions 16-bit PWM, at listed input clock frequency Min Typ Max Units – – – µA 3 MHz – 15 – µA 12 MHz – 60 – µA 50 MHz – 260 – µA Table 11-42. Pulse Width Modulation (PWM) AC Specifications Parameter Conditions Min Typ Max Units Operating frequency Description -40°C  Ta  85°C and Tj  100°C DC - 50 [47] MHz -40°C  Ta  125°C and Tj  150°C DC - 50 MHz Pulse width -40°C  Ta  85°C and Tj  100°C 15 - - ns -40°C  Ta  125°C and Tj  150°C 21 - - ns Pulse width (external) -40°C  Ta  85°C and Tj  100°C 30 - - ns -40°C  Ta  125°C and Tj  150°C 42 - - ns Kill pulse width -40°C  Ta  85°C and Tj  100°C 15 - - ns -40°C  Ta  125°C and Tj  150°C 21 - - ns Kill pulse width (external) -40°C  Ta  85°C and Tj  100°C 30 -40°C  Ta  125°C and Tj  150°C 42 - - ns Enable pulse width -40°C  Ta  85°C and Tj  100°C 15 - - ns -40°C  Ta  125°C and Tj  150°C 21 - - ns Enable pulse width (external) -40°C  Ta  85°C and Tj  100°C 30 - - ns -40°C  Ta  125°C and Tj  150°C 42 - - ns Reset pulse width -40°C  Ta  85°C and Tj  100°C 15 - - ns -40°C  Ta  125°C and Tj  150°C 21 - - ns Reset pulse width (external) -40°C  Ta  85°C and Tj  100°C 30 - - ns -40°C  Ta  125°C and Tj  150°C 42 - - ns ns Note 47. Applicable at -40°C to 85°C; 50 MHz at -40°C to 125°C. Document Number: 001-57331 Rev. *G Page 115 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.6.4 I2C Table 11-43. Fixed I2C DC Specifications Parameter Description Conditions Min Typ Max Units Block current consumption Enabled, configured for 100 kbps – – 250 µA – Enabled, configured for 400 kbps – – 260 µA – Wake from sleep mode – – 30 µA Min Typ Max Units - - 1 Mbps Min Typ Max Units 500 kbps - - 285 µA 1 Mbps - - 330 µA Min Typ Max Units - - 1 Mbit Table 11-44. Fixed I2C AC Specifications Parameter Description Conditions Bit rate 11.6.5 Controller Area Network[48] Table 11-45. CAN DC Specifications Parameter Description Block current consumption Conditions Table 11-46. CAN AC Specifications Parameter Description Bit rate Conditions Minimum 8 MHz clock Note 48. Refer to ISO 11898 specification for details. 49. Applicable at -40°C to 85°C; 50 MHz at -40°C to 125°C. Document Number: 001-57331 Rev. *G Page 116 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.6.6 USB Table 11-47. USB DC Specifications Parameter Description Min Typ Max Units USB configured, USB regulator enabled 4.35 – 5.25 V VUSB_3.3 USB configured, USB regulator bypassed 3.15 – 3.6 V VUSB_3 USB configured, USB regulator bypassed[50] 2.85 – 3.6 V – 10 – mA – 8 – mA VDDD = 5 V, connected to USB host, PICU configured to wake on USB resume signal – 0.5 – mA VDDD = 5 V, disconnected from USB host – 0.3 – mA VDDD = 3.3 V, connected to USB host, PICU configured to wake on USB resume signal – 0.5 – mA VDDD = 3.3 V, disconnected from USB host – 0.3 – mA VUSB_5 Device supply for USB operation IUSB_Configured Conditions Device supply current in device VDDD = 5 V, FCPU = 1.5 MHz active mode, bus clock and IMO = V DDD = 3.3 V, FCPU = 1.5 MHz 24 MHz IUSB_Suspended Device supply current in device sleep mode 11.6.7 Universal Digital Blocks (UDBs) PSoC Creator provides a library of pre-built and tested standard digital peripherals (UART, SPI, LIN, PRS, CRC, timer, counter, PWM, AND, OR, and so on) that are mapped to the UDB array. See the component data sheets in PSoC Creator for full AC/DC specifications, APIs, and example code. Table 11-48. UDB AC Specifications Parameter Description Conditions Min Typ Max Units Datapath Performance Fmax_timer Maximum frequency of 16-bit timer in a -40°C  Ta  85°C and Tj  100°C UDB pair -40°C  Ta  125°C and Tj  150°C - - 50 MHz - - 50 MHz Fmax_adder Maximum frequency of 16-bit adder in a -40°C  Ta  85°C and Tj  100°C UDB pair -40°C  Ta  125°C and Tj  150°C - - 50 MHz - - 50 MHz Fmax_CRC Maximum frequency of 16-bit CRC/PRS -40°C  Ta  85°C and Tj  100°C in a UDB pair -40°C  Ta  125°C and Tj  150°C - - 50 MHz - - 50 MHz - - 50 MHz - - 50 MHz PLD Performance Fmax_PLD Maximum frequency of a two-pass PLD -40°C  Ta  85°C and Tj  100°C function in a UDB pair -40°C  Ta  125°C and Tj  150°C Clock to Output Performance tclk_out Propogation delay for clock in to data out, 25 °C, Vddd  2.7 V see Figure 11-55. - 20 25 ns tclk_out Propogation delay for clock in to data out, Worst-case placement, routing, see Figure 11-55. and pin selection - – 55 ns Note 50. Rise/fall time matching (TR) not guaranteed, see . Document Number: 001-57331 Rev. *G Page 117 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 11-55. Clock to Output Performance Document Number: 001-57331 Rev. *G Page 118 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.7 Memory Specifications are valid for -40°C  Ta  125°C and Tj  150°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.7.1 Flash Table 11-49. Flash DC Specifications Parameter Description Conditions Erase and program voltage Vddd pin Min Typ Max Units 1.71 - 5.5 V Min Typ Max Units Table 11-50. Flash AC Specifications Parameter Twrite Terase Description Conditions Block write time (erase + program) Block erase time Block program time Tbulk Bulk erase time (16 KB to 64 KB)[51] KB)[51] -40°C  Ta  85°C and Tj  100°C - - 15 ms -40°C  Ta  125°C and Tj  140°C - - 15 ms -40°C  Ta  85°C and Tj  100°C - - 10 ms -40°C  Ta  125°C and Tj  140°C - - 10 ms -40°C  Ta  85°C and Tj  100°C - - 5 ms -40°C  Ta  125°C and Tj  140°C - - 5 ms -40°C  Ta  85°C and Tj  100°C - - 35 ms -40°C  Ta  125°C and Tj  140°C - - TBD ms -40°C  Ta  85°C and Tj  100°C - - 15 ms -40°C  Ta  125°C and Tj  140°C - - 15 ms Total device program time (including JTAG, etc.) No overhead [52] - - 5 seconds Flash data retention time, retention period measured from last erase cycle [53] Average ambient temp. TA  55 °C, 100 K erase/program cycles 20 – – years Retention period measured from last erase cycle after 100k progra/erase cycles at TA  85 °C 10 – – Sector erase time (8 KB to 16 Notes 51. ECC not included. 52. See PSoC® 3 Device Programming Specifications for a description of a low-overhead method of programming PSoC 3 flash. (Please take care of Foot note numbers) 53. Cypress provides a retention calculator to calculate the retention lifetime based on customers' individual temperature profiles for operation over the –40 °C to +125 °C ambient temperature range. Contact customercare@cypress.com. Document Number: 001-57331 Rev. *G Page 119 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.7.2 EEPROM Table 11-51. EEPROM DC Specifications Parameter Description Conditions Erase and program voltage Min Typ Max Units 1.71 - 5.5 V Table 11-52. EEPROM AC Specifications Parameter TWRITE Min Typ Max Units Single row erase/write cycle time Description Conditions – 2 20 ms EEPROM data retention time, retention Average ambient temp, TA  25 °C, period measured from last erase cycle 1M erase/program cycles 20 – – years Average ambient temp, TA  55 °C, 100 K erase/program cycles 20 – – Average ambient temp. TA 85 °C, 10 K erase/program cycles 10 – – Conditions Min Typ Max Units 1.71 - 5.5 V 11.7.3 Nonvolatile Latches (NVL) Table 11-53. NVL DC Specifications Parameter Description Erase and program voltage Vddd pin Table 11-54. NVL AC Specifications Parameter Description NVL endurance NVL data retention time Min Typ Max Units Programmed at 25°C Conditions 1K - - program/ erase cycles Programmed at 0-70°C 100 - - program/ erase cycles Programmed at 55°C 20 - - years Programmed at 0-70°C 10 - - years Min Typ Max Units 1.2 - - V Conditions Min Typ Max Units -40°C  Ta  85°C and Tj  100°C DC - 50 MHz -40°C  Ta  125°C and Tj  150°C DC - 50 MHz 11.7.4 SRAM Table 11-55. SRAM DC Specifications Parameter Vsram Description Conditions SRAM retention voltage Table 11-56. SRAM AC Specifications Parameter Fsram Description SRAM operating frequency Document Number: 001-57331 Rev. *G Page 120 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.7.5 External Memory Interface Figure 11-56. Asynchronous Read Cycle Timing Tcel EM_ CEn Taddrv Taddrh EM_ Addr Address Toel EM_ OEn EM_ WEn Tdoesu Tdoeh EM_ Data Data Table 11-57. Asynchronous Read Cycle Specifications Parameter Description T EMIF clock period[54] Tcel EM_CEn low time Taddrv EM_CEn low to EM_Addr valid Taddrh Address hold time after EM_Wen high Conditions Vdda  3.3 V Min Typ Max Units 30.3 – – ns 2T – 5 – 2T+ 5 ns – – 5 ns T – – ns Toel EM_OEn low time 2T – 5 – 2T + 5 ns Tdoesu Data to EM_OEn high setup time T + 15 – – ns Tdoeh Data hold time after EM_OEn high 3 – – ns Note 54. Limited by GPIO output frequency, see . Document Number: 001-57331 Rev. *G Page 121 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 11-57. Asynchronous Write Cycle Timing Taddrv Taddrh EM_ Addr Address Tcel EM_ CEn Twel EM_ WEn EM_ OEn Tdweh Tdcev EM_ Data Data Table 11-58. Asynchronous Write Cycle Specifications Parameter Description period[54] T EMIF clock Tcel EM_CEn low time Taddrv Conditions Vdda 3.3 V Min Typ Max Units 30.3 – – ns T–5 – T+5 ns EM_CEn low to EM_Addr valid – – 5 ns Taddrh Address hold time after EM_WEn high T – – ns Twel EM_WEn low time T–5 – T+5 ns Tdcev EM_CEn low to data valid – – 7 ns Tdweh Data hold time after EM_WEn high T – – ns Document Number: 001-57331 Rev. *G Page 122 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 11-58. Synchronous Read Cycle Timing Tcp/2 EM_ Clock Tceld Tcehd EM_ CEn Taddriv Taddrv EM_ Addr Address Toeld Toehd EM_ OEn Tds Data EM_ Data Tadscld Tadschd EM_ ADSCn Table 11-59. Synchronous Read Cycle Specifications Parameter Description Min Typ Max Units 30.3 – – ns T/2 – – ns EM_CEn low to EM_Clock high 5 – – ns EM_Clock high to EM_CEn high T/2 – 5 – – ns Taddrv EM_Addr valid to EM_Clock high 5 – – ns Taddriv EM_Clock high to EM_Addr invalid T/2 – 5 – – ns Toeld EM_OEn low to EM_Clock high 5 – – ns Toehd EM_Clock high to EM_OEn high T – – ns Tds Data valid before EM_OEn high T + 15 – – ns Tadscld EM_ADSCn low to EM_Clock high 5 – – ns Tadschd EM_Clock high to EM_ADSCn high T/2 – 5 – – ns T EMIF clock period[55] Tcp/2 EM_Clock pulse high Tceld Tcehd Conditions Vdda 3.3 V Note 55. Limited by GPIO output frequency, see . Document Number: 001-57331 Rev. *G Page 123 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 11-59. Synchronous Write Cycle Timing Tcp/2 EM_ Clock Tceld Tcehd EM_ CEn Taddriv Taddrv EM_ Addr Address Tweld Twehd EM_ WEn Tdh Tds Data EM_ Data Tadschd Tadscld EM_ ADSCn Table 11-60. Synchronous Write Cycle Specifications Parameter Description Period[56] Conditions Vdda 3.3 V Min Typ Max Units 30.3 – – ns T EMIF clock Tcp/2 EM_Clock pulse high T/2 – – ns Tceld EM_CEn low to EM_Clock high 5 – – ns Tcehd EM_Clock high to EM_CEn high T/2 – 5 – – ns Taddrv EM_Addr valid to EM_Clock high 5 – – ns Taddriv EM_Clock high to EM_Addr invalid T/2 – 5 – – ns Tweld EM_WEn low to EM_Clock high 5 – – ns Twehd EM_Clock high to EM_WEn high T/2 – 5 – – ns Tds Data valid before EM_Clock high 5 – – ns Tdh Data invalid after EM_Clock high T – – ns Tadscld EM_ADSCn low to EM_Clock high 5 – – ns Tadschd EM_Clock high to EM_ADSCn high T/2 – 5 – – ns Note 56. Limited by GPIO output frequency, see . Document Number: 001-57331 Rev. *G Page 124 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.8 PSoC System Resources Specifications are valid for -40°C  Ta  125°C and Tj  150°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.8.1 POR with Brown Out For brown out detect in regulated mode, Vddd and Vdda must be  2.0 V. Brown out detect is available in externally regulated mode. Table 11-61. Precise Power On Reset (PRES) with Brown Out DC Specifications Parameter Description PRESR Rising trip voltage PRESF Falling trip voltage Conditions Factory trim Min 1.64 1.62 Typ – – Max 1.68 1.66 Units V V Min – – Typ – 5 Max 0.5 – Units µs V/sec Min Typ Max Units 1.68 1.89 2.14 2.38 2.62 2.87 3.11 3.35 3.59 3.84 4.08 4.32 4.56 4.83 5.05 5.30 5.57 1.73 1.95 2.20 2.45 2.71 2.95 3.21 3.46 3.70 3.95 4.20 4.45 4.70 4.98 5.21 5.47 5.75 1.77 2.01 2.27 2.53 2.79 3.04 3.31 3.56 3.81 4.07 4.33 4.59 4.84 5.13 5.37 5.63 5.92 V V V V V V V V V V V V V V V V V Min Typ Max Units – – 1 µs Table 11-62. Precise Power On Reset (PRES) with Brown Out AC Specifications Parameter Description PRES_TR Response time VDDD/VDDA droop rate Conditions Sleep mode 11.8.2 Voltage Monitors Table 11-63. Voltage Monitors DC Specifications Parameter Description LVI Trip voltage LVI_A/D_SEL[3:0] = 0000b LVI_A/D_SEL[3:0] = 0001b LVI_A/D_SEL[3:0] = 0010b LVI_A/D_SEL[3:0] = 0011b LVI_A/D_SEL[3:0] = 0100b LVI_A/D_SEL[3:0] = 0101b LVI_A/D_SEL[3:0] = 0110b LVI_A/D_SEL[3:0] = 0111b LVI_A/D_SEL[3:0] = 1000b LVI_A/D_SEL[3:0] = 1001b LVI_A/D_SEL[3:0] = 1010b LVI_A/D_SEL[3:0] = 1011b LVI_A/D_SEL[3:0] = 1100b LVI_A/D_SEL[3:0] = 1101b LVI_A/D_SEL[3:0] = 1110b LVI_A/D_SEL[3:0] = 1111b HVI Trip voltage Conditions Table 11-64. Voltage Monitors AC Specifications Parameter Description Response time[57] Conditions Note 57. Based on device characterization (Not production tested). Document Number: 001-57331 Rev. *G Page 125 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.8.3 Interrupt Controller Table 11-65. Interrupt Controller AC Specifications Parameter Description Conditions Delay from Interrupt signal input to ISR Includes worse case completion of code execution from ISR code longest instruction DIV with 6 cycles Min - Typ - Max 25 Units Tcy CPU 11.8.4 JTAG Interface Table 11-66. JTAG Interface AC Specifications[29] Parameter f_TCK Description TCK frequency Conditions 3.3 V  VDDD  5 V 1.71 V  VDDD < 3.3 V T_TDI_setup TDI setup before TCK high T_TMS_setup T_TDI_hold T_TDO_valid T_TDO_hold TMS setup before TCK high TDI, TMS hold after TCK high TCK low to TDO valid TDO hold after TCK high T = 1/f_TCK max T = 1/f_TCK max T = 1/f_TCK max Min – – (T/10) – 5 T/4 T/4 – T/4 Typ – – – Max 14[58] 7[58] – – – – – – – 2T/5 – Units MHz MHz ns Figure 11-60. JTAG Interface Timing (1/f_TCK) TCK T_TDI_setup T_TDI_hold TDI T_TDO_valid T_TDO_hold TDO T_TMS_setup T_TMS_hold TMS Document Number: 001-57331 Rev. *G Page 126 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.8.5 SWD Interface Table 11-67. SWD Interface AC Specifications[29] Parameter f_SWDCK Description SWDCLK frequency Conditions 3.3 V  VDDD  5 V 1.71 V  VDDD < 3.3 V 1.71 V  VDDD < 3.3 V, SWD over USBIO pins T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max T_SWDI_hold SWDIO input hold after SWDCK high T = 1/f_SWDCK max T_SWDO_valid SWDCK high to SWDIO output T = 1/f_SWDCK max Min – – – Typ – – – Max 14[59] 7[59] 5.5[59] T/4 T/4 – – – – – – 2T/5 Units MHz MHz MHz Figure 11-61. SWD Interface Timing (1 /f_S W D C K ) SW DCK T_ S W D I_ setup T_ S W D I_hold S W D IO (P S oC input) T _S W D O _valid T_S W D O _hold S W D IO (P S oC output) 11.8.6 SWV Interface Table 11-68. SWV Interface AC Specifications[29] Parameter Description SWV mode SWV bit rate Conditions Min Typ Max Units - - 33 Mbit Notes 58. f_TCK must also be no more than 1/3 CPU clock frequency. 59. f_SWDCK must also be no more than 1/3 CPU clock frequency. Document Number: 001-57331 Rev. *G Page 127 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.9 Clocking Specifications are valid for -40°C  Ta  125°C and Tj  150°C, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. 11.9.1 Internal Main Oscillator Table 11-69. IMO DC Specifications Parameter Description Conditions Min Typ Max Units 62.6 MHz – – 600 µA 48 MHz – – 500 µA – – 500 µA – – 300 µA Supply current 24 MHz – USB mode With oscillator locking to USB bus 24 MHz – non USB mode 12 MHz – – 200 µA 6 MHz – – 180 µA 3 MHz – – 150 µA Figure 11-62. IMO Current vs. Frequency Document Number: 001-57331 Rev. *G Page 128 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Table 11-70. IMO AC Specifications Parameter FIMO Description Conditions IMO frequency stability (with factory trim) 62.6 MHz 48 MHz 24 MHz – Non USB mode 24 MHz – USB mode With oscillator locking to USB bus 12 MHz 6 MHz 3 MHz From enable (during normal system Startup time[60] operation) Min Typ Max Units –7 –5 –4 –0.25 –3 –2 –2 – – – – – – – – – 7 5 4 0.25 3 2 2 13 % % % % % % % µs – – 0.9 1.6 – – ns ns – – 0.9 12 – – ns ns Jitter (peak to peak)[60] Jp–p Jperiod F = 24 MHz F = 3 MHz Jitter (long term)[60] F = 24 MHz F = 3 MHz Note 60. Based on device characterization (Not production tested). Document Number: 001-57331 Rev. *G Page 129 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 11-63. IMO Frequency Variation vs. Temperature Figure 11-64. IMO Frequency Variation vs. VCC Document Number: 001-57331 Rev. *G Page 130 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.9.2 Internal Low Speed Oscillator Table 11-71. ILO DC Specifications Parameter Description Conditions Operating current[61] ICC Leakage current[61] Min Typ Max Units FOUT = 1 kHz – – 1.7 µA FOUT = 33 kHz – – 2.6 µA FOUT = 100 kHz – – 2.6 µA -40°C  Ta  85°C and Tj  100°C - 2.0 15 nA - - 200 nA Min - Typ - Max 2 Units ms 45 0.5 100 1 200 2 kHz kHz 30 0.3 100 1 300 3.5 kHz kHz 45 0.5 - 450 5 kHz kHz 150 0.3 - 500 6.5 kHz kHz Power down mode Leakage current[61] -40°C  Ta  125°C and Tj  150°C Power down mode Table 11-72. ILO AC Specifications Parameter Filo Filo Description Startup time ILO frequencies (trimmed) 100 kHz 1 kHz ILO frequencies (untrimmed) 100 kHz 1 kHz ILO frequencies (trimmed) 100 kHz 1 kHz ILO frequencies (untrimmed) 100 kHz 1 kHz Conditions Turbo mode -40°C  Ta  85°C and Tj  100°C -40°C  Ta  85°C and Tj  100°C -40°C  Ta  125°C and Tj  150°C -40°C  Ta  125°C and Tj  150°C Figure 11-65. ILO Frequency Variation vs. VDD Note 61. This value is calculated, not measured. 62. Based on device characterization (Not production tested). Document Number: 001-57331 Rev. *G Page 131 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 11.9.3 External Crystal Oscillator Table 11-73. 32 kHz External Crystal DC Specifications[63] Conditions Min Typ Max Units Icc Parameter Operating current Description Low power mode; CL = 6 pF; -40°C  Ta  125°C and Tj  150°C – 0.25 1.0 µA DL Drive level Low-power mode; CL = 6 pF – – 1 µW Min Typ Max Units Table 11-74. 32 kHz External Crystal AC Specifications Parameter Description F Frequency Ton Startup time Conditions – 32.768 – kHz – 1 – s Conditions Min 4 Typ – Max 25 Units MHz Conditions Measured at VDDIO/2 VIL to VIH Min 0 30 0.51 Typ – 50 – Max 33 70 – Units MHz % V/ns Conditions In = 3 MHz, Out = 24 MHz Min – Typ 200 Max – Units µA Conditions Output of Prescalar Min 1 1 24 24 - Typ - Max 48 3 50 50 250 250 400 Units MHz MHz MHz MHz µs ps ps High power mode Table 11-75. MHz ECO AC Specifications Parameter Description F Crystal frequency range 11.9.4 External Clock Reference Table 11-76. External Clock Reference AC Specifications Parameter Description External frequency range Input duty cycle range Input edge rate 11.9.5 Phase-Locked Loop Table 11-77. PLL DC Specifications Parameter Description IDD PLL operating current Table 11-78. PLL AC Specifications Parameter Description Fpllin PLL input frequency[64] PLL intermediate frequency[65] Fpllout PLL output frequency[64] Lock time at startup Jperiod-rms Jitter (rms)[29] -40°C  Ta  85°C and Tj  100°C -40°C  Ta  125°C and Tj  150°C -40°C  Ta  85°C and Tj  100°C -40°C  Ta  125°C and Tj  150°C Notes 63. Based on device characterization (not production tested). 64. This specification is guaranteed by testing the PLL across the specified range using the IMO as the source for the PLL. 65. PLL input divider, Q, must be set so that the input frequency is divided down to the intermediate frequency range. Value for Q ranges from 1 to 16. Document Number: 001-57331 Rev. *G Page 132 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 12. Ordering Information In addition to the features listed in Table 12-1, every CY8C34 device includes: a precision on-chip voltage reference, precision oscillators, Flash, ECC, DMA, a fixed function I2C, 4 KB trace RAM, JTAG/SWD programming and debug, external memory interface, and more. In addition to these features, the flexible UDBs and Analog Subsection support a wide range of peripherals. To assist you in selecting the ideal part, PSoC Creator makes a part recommendation after you choose the components required by your application. All CY8C34 derivatives incorporate device and Flash security in user-selectable security levels; see TRM for details. Table 12-1. CY8C34 Family with Single Cycle 8051 I/O[67] Opamps DFB CapSense UDBs[66] 16-bit Timer/PWM FS USB CAN 2.0b GPIO SIO USBIO 2 2 - ✔ 16 4 - - 29 25 4 0 48-SSOP 0x1E076069 CY8C3444AXA-116 50 16 2 0.5 ✔ 12-bit Del-Sig 2 4 2 2 - ✔ 16 4 - - 70 62 8 0 100-TQFP 0x1E074069 CY8C3444PVA-100 50 16 2 0.5 ✔ 12-bit Del-Sig 2 4 2 2 - ✔ 16 4 - - 29 25 4 0 48-SSOP 0x1E064069 CY8C3445AXE-097 50 32 4 1 ✔ 12-bit Del-Sig 2 4 2 2 - ✔ 20 4 - - 70 62 8 0 100-TQFP 0x1E061069 CY8C3445AXE-107 50 32 4 1 - 12-bit Del-Sig 2 4 2 2 - ✔ 20 4 ✔ - 72 62 8 2 100-TQFP 0x1E06B069 CY8C3445AXE-181 50 32 4 1 - 12-bit Del-Sig 2 4 2 2 - ✔ 20 4 - ✔ 70 62 8 0 100-TQFP 0x1E0B5069 Package Total I/O ADC 4 LCD Segment Drive 12-bit Del-Sig 2 EEPROM (KB) - SRAM (KB) 2 0.5 Flash (KB) CY8C3444PVE-118 50 16 Part Number CPU Speed (MHz) SC/CT Analog Blocks Digital Comparator Analog DAC MCU Core JTAG ID[68] 16 KB Flash 32 KB Flash CY8C3445AXA-104 50 32 4 1 - 12-bit Del-Sig 2 4 2 2 - ✔ 20 4 - - 70 62 8 0 100-TQFP 0x1E068069 CY8C3445AXA-108 50 32 4 1 ✔ 12-bit Del-Sig 2 4 2 2 - ✔ 20 4 ✔ - 72 62 8 2 100-TQFP 0x1E06C069 100-TQFP 0x1E0B5069 CY8C3445AXA-181 50 32 4 1 - 12-bit Del-Sig 2 4 2 2 - ✔ 20 4 - ✔ 70 62 8 0 CY8C3445PVA-090 50 32 4 1 ✔ 12-bit Del-Sig 2 4 2 2 - ✔ 20 4 ✔ - 31 25 4 2 48-SSOP 0x1E05A069 CY8C3445PVA-094 50 32 4 1 ✔ 12-bit Del-Sig 2 4 2 2 - ✔ 20 4 - - 29 25 4 0 48-SSOP 0x1E05E069 CY8C3446AXE-099 50 64 8 2 ✔ 12-bit Del-Sig 2 4 2 2 - ✔ 24 4 ✔ - 72 62 8 2 100-TQFP 0x1E063069 CY8C3446AXE-115 50 64 8 2 - 12-bit Del-Sig 2 4 2 2 - ✔ 24 4 - - 70 62 8 0 100-TQFP 0x1E073069 64 KB Flash CY8C3446PVE-082 50 64 8 2 - 12-bit Del-Sig 2 4 2 2 - ✔ 24 4 - - 29 25 4 0 48-SSOP 0x0E052069 CY8C3446PVE-102 50 64 8 2 ✔ 12-bit Del-Sig 2 4 2 2 - ✔ 24 4 - ✔ 29 25 4 0 48-SSOP 0x1E066069 CY8C3446AXA-099 50 64 8 2 ✔ 12-bit Del-Sig 2 4 2 2 - ✔ 24 4 ✔ - 72 62 8 2 100-TQFP 0x1E063069 CY8C3446AXA-105 50 64 8 2 ✔ 12-bit Del-Sig 2 4 2 2 - ✔ 24 4 - - 70 62 8 0 100-TQFP 0x1E069069 CY8C3446PVA-076 50 64 8 2 ✔ 12-bit Del-Sig 2 4 2 2 - ✔ 24 4 ✔ - 31 25 4 2 48-SSOP 0x1E04C069 CY8C3446PVA-091 50 64 8 2 ✔ 12-bit Del-Sig 2 4 2 2 - ✔ 24 4 - - 29 25 4 0 48-SSOP 0x1E05B069 CY8C3446PVA-102 50 64 8 2 ✔ 12-bit Del-Sig 2 4 2 2 - ✔ 24 4 - ✔ 29 25 4 0 48-SSOP 0x1E066069 Notes 66. UDBs support a wide variety of functionality including SPI, LIN, UART, timer, counter, PWM, PRS, and others. Individual functions may use a fraction of a UDB or multiple UDBs. Multiple functions can share a single UDB. See the “Example Peripherals” section on page 40 for more information on how UDBs may be used. 67. The I/O Count includes all types of digital I/O: GPIO, SIO, and the two USB I/O. See the ““I/O System and Routing” section on page 33” for details on the functionality of each of these types of I/O. 68. The JTAG ID has three major fields. The most significant nibble (left digit) is the version, followed by a 2 byte part number and a 3 nibble manufacturer ID. Document Number: 001-57331 Rev. *G Page 133 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 12.1 Part Numbering Conventions PSoC 3 devices follow the part numbering convention described below. All fields are single character alphanumeric (0, 1, 2, …, 9, A, B, …, Z) unless stated otherwise. CY8Cabcdefg-xxx  a: Architecture 3: PSoC 3  5: PSoC 5   b: Family Group within Architecture 2: CY8C32 family 4: CY8C34 family  6: CY8C36 family  8: CY8C38 family    c: Speed Grade  4: 50 MHz  d: Flash Capacity 4: 16 KB  5: 32 KB  6: 64 KB   ef: Package Code Two character alphanumeric AX: TQFP  LT: QFN  PV: SSOP    g: Temperature Range C: commercial 0°C to 70°C I: industrial -40°C to 85°C  A: automotive -40°C to 85°C  E: extended -40°C to 125°C    xxx: Peripheral Set   Three character numeric No meaning is associated with these three characters. Example CY8C 3 4 4 6 P V A - x x x Cypress Prefix 3: PSoC3 4: CY8C34 Family 4: 50 MHz Architecture Family Group within Architecture Speed Grade 6: 64 KB Flash Capacity PV: SSOP Package Code A: Automotive Temperature Range Peripheral Set All devices in the PSoC 3 CY8C34 family comply to RoHS-6 specifications, demonstrating the commitment by Cypress to lead-free products. Lead (Pb) is an alloying element in solders that has resulted in environmental concerns due to potential toxicity. Cypress uses nickel-palladium-gold (NiPdAu) technology for the majority of leadframe-based packages. A high level review of the Cypress Pb-free position is available on our website. Specific package information is also available. Package Material Declaration Datasheets (PMDDs) identify all substances contained within Cypress packages. PMDDs also confirm the absence of many banned substances. The information in the PMDDs will help Cypress customers plan for recycling or other "end of life" requirements. Document Number: 001-57331 Rev. *G Page 134 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 13. Packaging Table 13-1. Package Characteristics Parameter Description Conditions Min Typ Max Units TA Operating ambient temperature –40 25.00 125 °C TJ Operating junction temperature –40 – 150 °C TJA Package JA (48-pin SSOP) – 49 – °C/W TJA Package JA (100-pin TQFP) – 34 – °C/W TJC Package JC (48-pin SSOP) – 24 – °C/W TJC Package JC (100-pin TQFP) – 10 – °C/W Table 13-2. Solder Reflow Peak Temperature Package Maximum Peak Temperature Maximum Time at Peak Temperature 48-pin SSOP 260 °C 30 seconds 100-pin TQFP 260 °C 30 seconds Table 13-3. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2 Package MSL 48-pin SSOP MSL 3 100-pin TQFP MSL 3 Figure 13-1. 48-pin (300 mil) SSOP Package Outline 51-85061 *F Document Number: 001-57331 Rev. *G Page 135 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Figure 13-2. 100-pin TQFP (14 × 14 × 1.4 mm) Package Outline 51-85048 *I Document Number: 001-57331 Rev. *G Page 136 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 14. Acronyms Table 14-1. Acronyms Used in this Document (continued) Table 14-1. Acronyms Used in this Document Acronym Description Acronym Description FIR finite impulse response, see also IIR FPB flash patch and breakpoint FS full-speed GPIO general-purpose input/output, applies to a PSoC pin HVI high-voltage interrupt, see also LVI, LVD abus analog local bus ADC analog-to-digital converter AG analog global AHB AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data transfer bus IC integrated circuit ALU arithmetic logic unit IDAC current DAC, see also DAC, VDAC AMUXBUS analog multiplexer bus IDE integrated development environment application programming interface I2C, API APSR application program status register ARM® advanced RISC machine, a CPU architecture ATM automatic thump mode BW bandwidth CAN Controller Area Network, a communications protocol CMRR or IIC Inter-Integrated Circuit, a communications protocol IIR infinite impulse response, see also FIR ILO internal low-speed oscillator, see also IMO IMO internal main oscillator, see also ILO INL integral nonlinearity, see also DNL I/O input/output, see also GPIO, DIO, SIO, USBIO common-mode rejection ratio IPOR initial power-on reset CPU central processing unit IPSR interrupt program status register CRC cyclic redundancy check, an error-checking protocol IRQ interrupt request DAC digital-to-analog converter, see also IDAC, VDAC ITM instrumentation trace macrocell DFB digital filter block LCD liquid crystal display DIO digital input/output, GPIO with only digital capabilities, no analog. See GPIO. LIN Local Interconnect Network, a communications protocol. DMA direct memory access, see also TD LR link register DNL differential nonlinearity, see also INL LUT lookup table DNU do not use LVD low-voltage detect, see also LVI DR port write data registers LVI low-voltage interrupt, see also HVI DSI digital system interconnect LVTTL low-voltage transistor-transistor logic DWT data watchpoint and trace MAC multiply-accumulate ECC error correcting code MCU microcontroller unit ECO external crystal oscillator MISO master-in slave-out EEPROM electrically erasable programmable read-only memory NC no connect NMI nonmaskable interrupt NRZ non-return-to-zero NVIC nested vectored interrupt controller NVL nonvolatile latch, see also WOL EMI electromagnetic interference EMIF external memory interface EOC end of conversion EOF end of frame EPSR execution program status register ESD electrostatic discharge ETM embedded trace macrocell Document Number: 001-57331 Rev. *G opamp operational amplifier PAL programmable array logic, see also PLD PC program counter PCB printed circuit board PGA programmable gain amplifier Page 137 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet Table 14-1. Acronyms Used in this Document (continued) Acronym Description Table 14-1. Acronyms Used in this Document (continued) Acronym Description PHUB peripheral hub SOF start of frame PHY physical layer SPI PICU port interrupt control unit Serial Peripheral Interface, a communications protocol PLA programmable logic array SR slew rate PLD programmable logic device, see also PAL SRAM static random access memory PLL phase-locked loop SRES software reset PMDD package material declaration data sheet SWD serial wire debug, a test protocol POR power-on reset SWV single-wire viewer PRES precise low-voltage reset TD transaction descriptor, see also DMA PRS pseudo random sequence THD total harmonic distortion PS port read data register TIA transimpedance amplifier PSoC® Programmable System-on-Chip™ TRM technical reference manual PSRR power supply rejection ratio TTL transistor-transistor logic PWM pulse-width modulator TX transmit RAM random-access memory UART Universal Asynchronous Transmitter Receiver, a communications protocol UDB universal digital block RISC reduced-instruction-set computing RMS root-mean-square RTC real-time clock RTL register transfer language RTR RX USB Universal Serial Bus USBIO USB input/output, PSoC pins used to connect to a USB port remote transmission request VDAC voltage DAC, see also DAC, IDAC receive WDT watchdog timer SAR successive approximation register WOL write once latch, see also NVL SC/CT switched capacitor/continuous time WRES watchdog timer reset 2C serial clock SCL I SDA I2C serial data S/H sample and hold SINAD signal to noise and distortion ratio SIO special input/output, GPIO with advanced features. See GPIO. SOC start of conversion Document Number: 001-57331 Rev. *G XRES external reset I/O pin XTAL crystal 15. Reference Documents PSoC® 3, PSoC® 5 Architecture TRM PSoC® 3 Registers TRM Page 138 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 16. Document Conventions 16.1 Units of Measure Table 16-1. Units of Measure Symbol Unit of Measure °C degrees Celsius dB decibels fF femtofarads Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohours kHz kilohertz k kilohms ksps kilosamples per second LSB least significant bit Mbps megabits per second MHz megahertz M megaohms Msps megasamples per second µA microamperes µF microfarads µH microhenrys µs microseconds µV microvolts µW microwatts mA milliamperes ms milliseconds mV millivolts nA nanoamperes ns nanoseconds nV nanovolts  ohms pF picofarads ppm parts per million ps picoseconds s seconds sps samples per second sqrtHz square root of hertz V volts Document Number: 001-57331 Rev. *G Page 139 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 17. Revision History Description Title: PSoC® 3: CY8C34 Automotive Family Datasheet, Programmable System-on-Chip (PSoC®) Document Number: 001-57331 Submission Orig. of Revision ECN Description of Change Date Change ** 2800070 01/05/10 SECA New data sheet. *A 2921624 04/26/10 MKEA Updated Active Mode Idd values in Table 11-2 Updated Boost AC and DC specifications Updated solder paste reflow temperature (Table 11-3) Moved Filo spec from ILO DC to ILO AC table Updated Figure 7-14, Interrupt and DMA processing Added Bytes column in Tables 4-1 and 4-5 Updated Figure 6-3, Power mode transitions Updated JTAG and SWD specifications Updated Interrupt Vector table Updated Sales links Updated PCB Schematic Updated Vbias spec Added UDBs subsection under 11.6 Digital Peripherals Updated Iout parameter in LCD Direct Drive DC Specs table Added footnote in PLL AC Specification table Added Load regulation and Line regulation parameters to Inductive Boost Regulator DC Specifications table Updated Icc parameter in LCD Direct Drive DC Specs table Updated Tstartup parameter in AC Specifications table Updated LVD in Tables 6-2 and 6-3 In page 1, updated internal oscillator range under Prescision programmable clocking to start from 3 MHz Updated Pin Descriptions section and modified Figures 6-6, 6-8, 6-9 Added PLL intermediate frequency row with footnote in PLL AC Specs table Added bullets on CapSense in page 1; added CapSense column in Section Updated Figure 2-6 (PCB Layout) Updated Tstartup values in Table 11-3 Updated IMO frequency Updated section 5.2 and Table 11-2 to correct suggestion of execution from Flash Updated Vref specs in Table 11-21. Updated IDAC uncompensated gain error in Table 11-25. Updated Tresp, high and low power modes, in Table 11-24. Updated Delay from Interrupt signal input to ISR code execution from ISR code in Table 71. Updated sleep wakeup time in Table 6-3 and Tsleep in Table 11-3. Updated SNR condition in Table 11-20 *B 3490494 01/11/2012 GIR Updated Figure 6-7 on page 34 *C 3994809 05/08/2013 KPAT Updated all tables in Electrical Specifications. Updated Ordering Information (Updated part numbers, JTAG ID). Removed all references of Vboost across the document. *D 4040790 06/27/2013 RASB Changed status from Preliminary to FInal. Updated Features. Updated Architectural Overview. Updated Pinouts. Updated Pin Descriptions. Updated Memory. Updated System Integration. Updated Digital Subsystem. Updated Analog Subsystem. Updated Electrical Specifications. Document Number: 001-57331 Rev. *G Page 140 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 17. Revision History (continued) Description Title: PSoC® 3: CY8C34 Automotive Family Datasheet, Programmable System-on-Chip (PSoC®) Document Number: 001-57331 Submission Orig. of Revision ECN Description of Change Date Change *E 4109902 08/31/2013 NFB / Updated Features. ANMD Updated Architectural Overview: Added Note 4 and referred the same note in features in “The heart of the analog subsystem is a fast, accurate, configurable delta-sigma ADC with these features”. Updated Pinouts: Updated Figure 2-5. Updated Memory: Updated EEPROM: Updated description. Updated Nonvolatile Latches (NVLs): Updated Table 5-2 and Table 5-3. Updated Memory Map: Updated I/O Port SFRs: Updated xdata Space: Updated Table 5-5. Updated Digital Subsystem: Updated Universal Digital Block: Updated PLD Module: Updated Figure 7-3. Updated I2C: Updated description. Updated Analog Subsystem: Updated Programmable SC/CT Blocks: Updated PGA: Updated Table 8-3. Updated Electrical Specifications: Updated Device Level Specifications: Updated Table 11-2. Updated Inputs and Outputs: Updated GPIO: Removed figure “GPIO Output Rise and Fall Times, Fast Strong Mode, VDDIO = 3.3 V, 25 pF Load” and figure “GPIO Output Rise and Fall Times, Slow Strong Mode, VDDIO = 3.3 V, 25 pF Load”. Updated Analog Peripherals: Updated Delta-Sigma ADC: Updated Table 11-17. Updated Table 11-18. Updated Voltage Reference: Updated Table 11-20. Updated Programmable Gain Amplifier: Updated Table 11-33. Updated Memory: Updated Flash: Updated Table 11-50. Updated Packaging: spec 51-85048 – Changed revision from *G to *H. Updated in new template. Document Number: 001-57331 Rev. *G Page 141 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 17. Revision History (continued) Description Title: PSoC® 3: CY8C34 Automotive Family Datasheet, Programmable System-on-Chip (PSoC®) Document Number: 001-57331 Submission Orig. of Revision ECN Description of Change Date Change *F 4174914 10/26/2013 NFB / Updated Pinouts: ANMD Added Note 7 and referred the same note in 100 mA in description. Updated Electrical Specifications: Updated Absolute Maximum Ratings: Updated Table 11-1. Added Note 17 and referred the same note in Table 11-1. Added Note 19 and referred the same note in Ivddio parameter in Table 11-1. Updated Analog Peripherals: Updated Opamp: Updated Table 11-15. Updated Voltage Reference: Updated Table 11-20. *G 4281204 02/14/2014 ANMD Updated Packaging: Updated Table 13-1. Updated Digital Subsystem: Updated I2C: Updated Note 16. Updated Electrical Specifications: Updated Analog Peripherals: Updated Delta-Sigma ADC: Updated Table 11-17: Updated Conditions of Vos parameter. Updated Memory: Updated Flash: Updated Table 11-50: Added Note 53 and referred the same note in “Flash data retention time, retention period measured from last erase cycle” in description column. Replaced “Tjavg” with “TA” in last row in conditions column. Updated Packaging: spec 51-85048 – Changed revision from *H to *I. Completing Sunset Review. Document Number: 001-57331 Rev. *G Page 142 of 143 PSoC® 3: CY8C34 Automotive Family Datasheet 18. Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. PSoC® Solutions Products Automotive cypress.com/go/automotive Clocks & Buffers cypress.com/go/clocks Interface cypress.com/go/interface Lighting & Power Control cypress.com/go/powerpsoc cypress.com/go/plc Memory cypress.com/go/memory PSoC cypress.com/go/psoc Touch Sensing psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP Cypress Developer Community Community | Forums | Blogs | Video | Training Technical Support cypress.com/go/support cypress.com/go/touch USB Controllers cypress.com/go/USB Wireless/RF cypress.com/go/wireless © Cypress Semiconductor Corporation, 2010-2014. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-57331 Rev. *G ® ® ® ® Revised February 14, 2014 ® Page 143 of 143 CapSense , PSoC 3, PSoC 5, and PSoC Creator™ are trademarks and PSoC is a registered trademark of Cypress Semiconductor Corp. ARM is a registered trademark, and Keil, and RealView are trademarks, of ARM Limited. All other trademarks or registered trademarks referenced herein are property of the respective corporations.