Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
PSoC® 3: CY8C34 Family Datasheet
®
Programmable System-on-Chip (PSoC )
General Description
PSoC® 3 is a true programmable embedded system-on-chip, integrating configurable analog and digital peripherals, memory, and a
microcontroller on a single chip. The PSoC 3 architecture boosts performance through:
8051 core plus DMA controller at up to 50 MHz
Ultra low power with industry's widest voltage range
Programmable digital and analog peripherals enable custom functions
Flexible routing of any analog or digital peripheral function to any pin
PSoC devices employ a highly configurable system-on-chip architecture for embedded control design. They integrate configurable
analog and digital circuits, controlled by an on-chip microcontroller. A single PSoC device can integrate as many as 100 digital and
analog peripheral functions, reducing design time, board space, power consumption, and system cost while improving system quality.
Features
Operating characteristics
Analog peripherals
Voltage range: 1.71 to 5.5 V, up to six power domains
[1]
Temperature range (ambient) –40 to 85 °C
DC to 50-MHz operation
Power modes
• Active mode 1.2 mA at 6 MHz, and 12 mA at 48 MHz
• 1-µA sleep mode
• 200-nA hibernate mode with RAM retention
Boost regulator from 0.5-V input up to 5-V output
Configurable 8- to 12-bit delta-sigma ADC
Two 8-bit DACs
Four comparators
Two opamps
Two programmable analog blocks, to create:
• Programmable gain amplifier (PGA)
• Transimpedance amplifier (TIA)
• Mixer
• Sample and hold circuit
®
CapSense support, up to 62 sensors
1.024 V ±1% internal voltage reference
Performance
8-bit 8051 CPU, 32 interrupt inputs
24-channel direct memory access (DMA) controller
Versatile I/O system
Memories
29 to 72 I/O pins – up to 62 general-purpose I/Os (GPIOs)
Up to eight performance I/O (SIO) pins
• 25 mA current sink
• Programmable input threshold and output high voltages
• Can act as a general-purpose comparator
• Hot swap capability and overvoltage tolerance
Two USBIO pins that can be used as GPIOs
Route any digital or analog peripheral to any GPIO
LCD direct drive from any GPIO, up to 46 × 16 segments
CapSense support from any GPIO
1.2-V to 5.5-V interface voltages, up to four power domains
Up to 64 KB program flash, with cache and security features
Up to 8 KB additional flash for error correcting code (ECC)
Up to 8 KB RAM
Up to 2 KB EEPROM
Digital peripherals
Four 16-bit timer, counter, and PWM (TCPWM) blocks
I2C, 1 Mbps bus speed
USB 2.0 certified Full-Speed (FS) 12 Mbps peripheral
interface (TID#40770053) using internal oscillator[2]
Full CAN 2.0b, 16 Rx, 8 Tx buffers
16 to 24 universal digital blocks (UDB), programmable to
create any number of functions:
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• I2C, UART, SPI, I2S, LIN 2.0 interfaces
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generators
• Quadrature decoders
• Gate-level logic functions
Programming and debug
JTAG (4-wire), serial wire debug (SWD) (2-wire), and single
wire viewer (SWV) interfaces
2
Bootloader programming through I C, SPI, UART, USB, and
other interfaces
Package options: 48-pin SSOP, 48-pin QFN, 68-pin QFN, and
100-pin TQFP
Development support with free PSoC Creator™ tool
Programmable clocking
3- to 62-MHz internal oscillator, 2% accuracy at 3 MHz
4- to 25-MHz external crystal oscillator
Internal PLL clock generation up to 50 MHz
Low-power internal oscillator at 1, 33, and 100 kHz
32.768-kHz external watch crystal oscillator
12 clock dividers routable to any peripheral or I/O
Schematic and firmware design support
Over 100 PSoC Components™ integrate multiple ICs and
system interfaces into one PSoC. Components are free
embedded ICs represented by icons. Drag and drop
component icons to design systems in PSoC Creator.
Includes free Keil 8051 compiler
Supports device programming and debugging
Notes
1. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. This feature on select devices only. See Ordering Information on page 121 for details.
Cypress Semiconductor Corporation
Document Number: 001-53304 Rev. AA
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 3, 2019
PSoC® 3: CY8C34 Family Datasheet
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP. Following is an abbreviated list for PSoC 3:
Overview: PSoC Portfolio, PSoC Roadmap
Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP
In addition, PSoC Creator includes a device selection tool.
Application notes: Cypress offers a large number of PSoC
application notes and code examples covering a broad range
of topics, from basic to advanced level. Recommended application notes for getting started with PSoC 3 are:
AN54181: Getting Started With PSoC 3
AN61290: Hardware Design Considerations
AN57821: Mixed Signal Circuit Board Layout
AN58304: Pin Selection for Analog Designs
AN81623: Digital Design Best Practices
AN73854: Introduction To Bootloaders
Development Kits:
CY8CKIT-030 is designed for analog performance, for developing high-precision analog, low-power, and low-voltage applications.
CY8CKIT-001 provides a common development platform for
any one of the PSoC 1, PSoC 3, PSoC 4, or PSoC 5LP
families of devices.
The MiniProg3 device provides an interface for flash programming and debug.
Technical Reference Manuals (TRM)
Architecture TRM
Registers TRM
Programming Specification
PSoC Creator
PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100
pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can:
1. Drag and drop component icons to build your hardware
3. Configure components using the configuration tools
system design in the main design workspace
4. Explore the library of 100+ components
2. Codesign your application firmware with the PSoC hardware,
5. Review component datasheets
using the PSoC Creator IDE C compiler
Figure 1. Multiple-Sensor Example Project in PSoC Creator
Document Number: 001-53304 Rev. AA
Page 2 of 137
PSoC® 3: CY8C34 Family Datasheet
Contents
1. Architectural Overview ..................................................... 4
2. Pinouts ............................................................................... 6
3. Pin Descriptions .............................................................. 11
4. CPU ................................................................................... 12
4.1 8051 CPU ................................................................. 12
4.2 Addressing Modes .................................................... 12
4.3 Instruction Set .......................................................... 13
4.4 DMA and PHUB ....................................................... 17
4.5 Interrupt Controller ................................................... 18
5. Memory ............................................................................. 22
5.1 Static RAM ............................................................... 22
5.2 Flash Program Memory ............................................ 22
5.3 Flash Security ........................................................... 22
5.4 EEPROM .................................................................. 22
5.5 Nonvolatile Latches (NVLs) ...................................... 23
5.6 External Memory Interface ....................................... 24
5.7 Memory Map ............................................................ 25
6. System Integration .......................................................... 27
6.1 Clocking System ....................................................... 27
6.2 Power System .......................................................... 30
6.3 Reset ........................................................................ 34
6.4 I/O System and Routing ........................................... 36
7. Digital Subsystem ........................................................... 43
7.1 Example Peripherals ................................................ 43
7.2 Universal Digital Block .............................................. 45
7.3 UDB Array Description ............................................. 48
7.4 DSI Routing Interface Description ............................ 49
7.5 CAN .......................................................................... 50
7.6 USB .......................................................................... 52
7.7 Timers, Counters, and PWMs .................................. 53
7.8 I2C ............................................................................ 54
8. Analog Subsystem .......................................................... 56
8.1 Analog Routing ......................................................... 57
8.2 Delta-sigma ADC ...................................................... 59
8.3 Comparators ............................................................. 60
8.4 Opamps .................................................................... 61
8.5 Programmable SC/CT Blocks .................................. 61
8.6 LCD Direct Drive ...................................................... 63
8.7 CapSense ................................................................. 64
8.8 Temp Sensor ............................................................ 64
8.9 DAC .......................................................................... 64
8.10 Up/Down Mixer ....................................................... 64
8.11 Sample and Hold .................................................... 65
Document Number: 001-53304 Rev. AA
9. Programming, Debug Interfaces, Resources ................ 65
9.1 JTAG Interface ......................................................... 66
9.2 Serial Wire Debug Interface ..................................... 67
9.3 Debug Features ........................................................ 68
9.4 Trace Features ......................................................... 68
9.5 Single Wire Viewer Interface .................................... 68
9.6 Programming Features ............................................. 68
9.7 Device Security ........................................................ 68
10. Development Support ................................................... 69
10.1 Documentation ....................................................... 69
10.2 Online ..................................................................... 69
10.3 Tools ....................................................................... 69
11. Electrical Specifications ............................................... 70
11.1 Absolute Maximum Ratings .................................... 70
11.2 Device Level Specifications .................................... 71
11.3 Power Regulators ................................................... 75
11.4 Inputs and Outputs ................................................. 79
11.5 Analog Peripherals ................................................. 88
11.6 Digital Peripherals ................................................ 105
11.7 Memory ................................................................ 108
11.8 PSoC System Resources ..................................... 114
11.9 Clocking ................................................................ 117
12. Ordering Information ................................................... 121
12.1 Part Numbering Conventions ............................... 122
13. Packaging ..................................................................... 123
14. Acronyms ..................................................................... 126
15. Reference Documents ................................................. 127
16. Document Conventions .............................................. 128
16.1 Units of Measure .................................................. 128
17. Revision History .......................................................... 129
18. Sales, Solutions, and Legal Information ................... 137
Worldwide Sales and Design Support.......................... 137
Products ....................................................................... 137
PSoC® Solutions ......................................................... 137
Cypress Developer Community.................................... 137
Technical Support ........................................................ 137
Page 3 of 137
PSoC® 3: CY8C34 Family Datasheet
1. Architectural Overview
Introducing the CY8C34 family of ultra low-power, flash Programmable System-on-Chip (PSoC®) devices, part of a scalable
8-bit PSoC 3 and 32-bit PSoC 5 platform. The CY8C34 family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables
a high level of integration in a wide variety of consumer, industrial, and medical applications.
Figure 1-1. Simplified Block Diagram
Analog Interconnect
8- Bit
Timer
Quadrature Decoder
UDB
Sequencer
Usage Example for UDB
Universal Digital Block Array ( 24 x UDB)
UDB
UDB
UDB
16- Bit
PWM
UDB
UDB
12- Bit SPI
UDB
UDB
UDB
UDB
8- Bit
Timer
Logic
UDB
UDB
UDB
UDB
UDB
UDB
UDB
Master/
Slave
UDB
8- Bit SPI
I2C Slave
UDB
I2C
CAN
2.0
16- Bit PRS
UDB
FS USB
2.0
4x
Timer
Counter
PWM
Logic
UDB
UDB
UDB
UART
UDB
22 Ω
USB
PHY
GPIOs
GPIOs
IMO
Clock Tree
32.768 KHz
( Optional)
Digital System
System Wide
Resources
Xtal
Osc
SIO
4- 25 MHz
( Optional)
GPIOs
Digital Interconnect
12- Bit PWM
RTC
Timer
System Bus
GPIOs
Memory System
EEPROM
EMIF
SRAM
CPU System
8051 or
Cortex M3
CPU
Interrupt
Controller
Program
Debug &
Trace
PHUB
DMA
FLASH
ILO
Program &
Debug
GPIOs
WDT
and
Wake
Boundary
Scan
Power Management
System
Analog System
LCD Direct
Drive
ADC
POR and
LVD
1.8V LDO
SMP
+
2x
Opamp
-
2 x SC/ CT Blocks
(TIA, PGA, Mixer etc)
Temperature
Sensor
Del Sig
ADC
+
4x
CMP
2x DAC
CapSense
3 per
Opamp
-
GPIOs
1.71 to
5.5V
Sleep
Power
GPIOs
SIOs
Clocking System
0. 5 to 5.5V
( Optional)
Figure 1-1 illustrates the major components of the CY8C34
family. They are:
8051 CPU subsystem
Nonvolatile subsystem
Programming, debug, and test subsystem
Inputs and outputs
Clocking
Power
Digital subsystem
Document Number: 001-53304 Rev. AA
Analog subsystem
PSoC’s digital subsystem provides half of its unique
configurability. It connects a digital signal from any peripheral to
any pin through the digital system interconnect (DSI). It also
provides functional flexibility through an array of small, fast, lowpower UDBs. PSoC Creator provides a library of prebuilt and
tested standard digital peripherals (UART, SPI, LIN, PRS, CRC,
timer, counter, PWM, AND, OR, and so on) that are mapped to
the UDB array. You can also easily create a digital circuit using
boolean primitives by means of graphical design entry. Each
UDB contains programmable array logic (PAL)/PLD functionality,
together with a small state machine engine to support a wide
variety of peripherals.
Page 4 of 137
PSoC® 3: CY8C34 Family Datasheet
In addition to the flexibility of the UDB array, PSoC also provides
configurable digital blocks targeted at specific functions. For the
CY8C34 family these blocks can include four 16-bit timer,
counter, and PWM blocks; I2C slave, master, and multi-master;
Full-Speed USB; and Full CAN 2.0b.
For more details on the peripherals see the “Example
Peripherals” section on page 43 of this data sheet. For
information on UDBs, DSI, and other digital blocks, see the
“Digital Subsystem” section on page 43 of this data sheet.
PSoC’s analog subsystem is the second half of its unique
configurability. All analog performance is based on a highly
accurate absolute voltage reference with less than 1-percent
error over temperature and voltage. The configurable analog
subsystem includes:
Analog muxes
Comparators
Voltage references
Analog-to-digital converter (ADC)
Digital-to-analog converters (DACs)
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals. The heart of the analog
subsystem is a fast, accurate, configurable delta-sigma ADC
with these features:
Less than 100 µV offset
A gain error of 0.2 percent
INL less than ±1 LSB
DNL less than ±1 LSB
SINAD better than 66 dB
This converter addresses a wide variety of precision analog
applications, including some of the most demanding sensors.
Two high-speed voltage or current DACs support 8-bit output
signals at update rate of 8 Msps in current DAC (IDAC) and
1 Msps in voltage DAC (VDAC). They can be routed out of any
GPIO pin. You can create higher resolution voltage PWM DAC
outputs using the UDB array. This can be used to create a pulse
width modulated (PWM) DAC of up to 10 bits, at up to 48 kHz.
The digital DACs in each UDB support PWM, PRS, or
delta-sigma algorithms with programmable widths.
In addition to the ADC and DACs, the analog subsystem
provides multiple:
Uncommitted opamps
Configurable switched capacitor/continuous time (SC/CT)
blocks. These support:
Transimpedance amplifiers
Programmable gain amplifiers
Mixers
Other similar analog components
See the “Analog Subsystem” section on page 56 of this data
sheet for more details.
PSoC’s 8051 CPU subsystem is built around a single cycle
pipelined 8051 8-bit processor running at up to 50 MHz. The
CPU subsystem includes a programmable nested vector
interrupt controller, DMA controller, and RAM. PSoC’s nested
vector interrupt controller provides low latency by allowing the
CPU to vector directly to the first address of the interrupt service
routine, bypassing the jump instruction required by other
architectures. The DMA controller enables peripherals to
exchange data without CPU involvement. This allows the CPU
to run slower (saving power) or use those CPU cycles to improve
the performance of firmware algorithms. The single cycle 8051
CPU runs ten times faster than a standard 8051 processor. The
processor speed itself is configurable, allowing you to tune active
power consumption for specific applications.
PSoC’s nonvolatile subsystem consists of flash, byte-writeable
EEPROM, and nonvolatile configuration options. It provides up
to 64 KB of on-chip flash. The CPU can reprogram individual
blocks of flash, enabling bootloaders. You can enable an error
correcting code (ECC) for high reliability applications. A powerful
and flexible protection model secures the user's sensitive
information, allowing selective memory block locking for read
and write protection. Up to 2 KB of byte-writeable EEPROM is
available on-chip to store application data. Additionally, selected
configuration options such as boot speed and pin drive mode are
stored in nonvolatile memory. This allows settings to activate
immediately after power-on reset (POR).
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the VDDIO pins. Every GPIO
has analog I/O, LCD drive[3], CapSense[4], flexible interrupt
generation, slew rate control, and digital I/O capability. The SIOs
on PSoC allow VOH to be set independently of VDDIO when
used as outputs. When SIOs are in input mode they are high
impedance. This is true even when the device is not powered or
when the pin voltage goes above the supply voltage. This makes
the SIO ideally suited for use on an I2C bus where the PSoC may
not be powered when other devices on the bus are. The SIO pins
also have high current sink capability for applications such as
LED drives. The programmable input threshold feature of the
SIO can be used to make the SIO function as a general purpose
analog comparator. For devices with Full-Speed USB the USB
physical interface is also provided (USBIO). When not using
USB these pins may also be used for limited digital functionality
and device programming. All of the features of the PSoC I/Os are
covered in detail in the “I/O System and Routing” section on
page 36 of this data sheet.
The PSoC device incorporates flexible internal clock generators,
designed for high stability and factory trimmed for high accuracy.
The Internal Main Oscillator (IMO) is the clock base for the
system, and has 2-percent accuracy at 3 MHz. The IMO can be
configured to run from 3 MHz up to 24 MHz. Multiple clock
derivatives can be generated from the main clock frequency to
meet application needs.
Notes
3. This feature on select devices only. See Ordering Information on page 121 for details.
4. GPIOs with opamp outputs are not recommended for use with CapSense.
Document Number: 001-53304 Rev. AA
Page 5 of 137
PSoC® 3: CY8C34 Family Datasheet
The device provides a PLL to generate clock frequencies up to
50 MHz from the IMO, external crystal, or external reference
clock. It also contains a separate, very low-power Internal
low-speed oscillator (ILO) for the sleep and watchdog timers. A
32.768-kHz external watch crystal is also supported for use in
RTC applications. The clocks, together with programmable clock
dividers, provide the flexibility to integrate most timing
requirements.
The CY8C34 family supports a wide supply operating range from
1.71 V to 5.5 V. This allows operation from regulated supplies
such as 1.8 V ± 5 percent, 2.5 V ±10 percent, 3.3 V ± 10 percent,
or 5.0 V ± 10 percent, or directly from a wide range of battery
types. In addition, it provides an integrated high efficiency
synchronous boost converter that can power the device from
supply voltages as low as 0.5 V. This enables the device to be
powered directly from a single battery or solar cell. In addition,
you can use the boost converter to generate other voltages
required by the device, such as a 3.3-V supply for LCD glass
drive. The boost’s output is available on the VBOOST pin, allowing
other devices in the application to be powered from the PSoC.
PSoC supports a wide range of low-power modes. These include
a 200-nA hibernate mode with RAM retention and a 1-µA sleep
mode with RTC. In the second mode the optional 32.768-kHz
watch crystal runs continuously and maintains an accurate RTC.
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low-power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 1.2 mA when the CPU is running at
6 MHz, or 0.8 mA running at 3 MHz.
The details of the PSoC power modes are covered in the “Power
System” section on page 30 of this data sheet.
PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for
programming, debug, and test. The 1-wire SWV may also be
used for ‘printf’ style debugging. By combining SWD and SWV,
you can implement a full debugging interface with just three pins.
Using these standard interfaces enables you to debug or
program the PSoC with a variety of hardware solutions from
Cypress or third party vendors. PSoC supports on-chip break
points and 4 KB instruction and data race memory for debug.
Details of the programming, test, and debugging interfaces are
discussed in the “Programming, Debug Interfaces, Resources”
section on page 65 of this data sheet.
2. Pinouts
Each VDDIO pin powers a specific set of I/O pins. (The USBIOs
are powered from VDDD.) Using the VDDIO pins, a single PSoC
can support multiple voltage levels, reducing the need for
off-chip level shifters. The black lines drawn on the pinout
diagrams in Figure 2-3 through Figure 2-6, as well as Table 2-1,
show the pins that are powered by each VDDIO.
Each VDDIO may source up to 100 mA total to its associated I/O
pins, as shown in Figure 2-1.
Figure 2-1. VDDIO Current Limit
IDDIO X
mA
VDDIO X
I/O Pins
PSoC
Conversely, for the 100-pin and 68-pin devices, the set of I/O
pins associated with any VDDIO may sink up to 100 mA total, as
shown in Figure 2-2.
Figure 2-2. I/O Pins Current Limit
Ipins
VDDIO X
mA
I/O Pins
PSoC
VSSD
For the 48-pin devices, the set of I/O pins associated with
VDDIO0 plus VDDIO2 may sink up to 100 mA total. The set of
I/O pins associated with VDDIO1 plus VDDIO3 may sink up to a
total of 100 mA.
Document Number: 001-53304 Rev. AA
Page 6 of 137
PSoC® 3: CY8C34 Family Datasheet
Figure 2-3. 48-pin SSOP Part Pinout
(SIO) P12[2]
(SIO) P12[3]
(OPAMP2OUT, GPIO) P0[0]
(OPAMP0OUT, GPIO) P0[1]
(OPAMP0+, GPIO) P0[2]
(OPAMP0-/EXTREF0, GPIO) P0[3]
VDDIO0
(OPAMP2+, GPIO) P0[4]
(OPAMP2-, GPIO) P0[5]
(IDAC0, GPIO) P0[6]
(IDAC2, GPIO) P0[7]
VCCD
VSSD
VDDD
(GPIO) P2[3]
(GPIO) P2[4]
VDDIO2
(GPIO) P2[5]
(GPIO) P2[6]
(GPIO) P2[7]
VSSB
IND
VBOOST
VBAT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
Lines show
46
VDDIO to I/O
45
supply
44
association
43
42
41
40
39
38
SSOP 37
36
35
34
33
32
31
30
29
28
27
26
25
VDDA
VSSA
VCCA
P15[3] (GPIO, KHZ XTAL: XI)
P15[2] (GPIO, KHZ XTAL: XO)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
VDDIO3
P15[1] (GPIO, MHZ XTAL: XI)
P15[0] (GPIO, MHZ XTAL: XO)
VCCD
VSSD
VDDD
[5]
P15[7] (USBIO, D-, SWDCK)
[5]
P15[6] (USBIO, D+, SWDIO)
P1[7] (GPIO)
P1[6] (GPIO)
VDDIO1
P1[5] (GPIO, NTRST)
P1[4] (GPIO, TDI)
P1[3] (GPIO, TDO, SWV)
P1[2] (GPIO, CONFIGURABLE XRES)
P1[1] (GPIO, TCK, SWDCK)
P1[0] (GPIO, TMS, SWDIO)
VDDIO1
(GPIO, Configurable XRES) P1[2]
(GPIO, TDO, SWV) P1[3]
(GPIO, TDI) P1[4]
(GPIO, NTRST) P1[5]
7
8
9
10
11
12
46
45
44
43
42
41
40
39
38
37
Lines show
VDDIO to I/O
supply
association
QFN
(TOP VIEW
)
36 P0[3] (OPAMP0-/EXTREF0, GPIO)
35 P0[2] (OPAMP0+, GPIO)
34 P0[1] (OPAMP0OUT, GPIO)
33 P0[0] (OPAMP2OUT, GPIO)
32 P12[3] (SIO)
31 P12[2] (SIO)
30 VDDA
29 VSSA
28 VCCA
27 P15[3] (GPIO, KHZ XTAL: XI)
26 P15[2] (GPIO, KHZ XTAL: XO)
25 P12[1] (SIO, I2C1: SDA)
13
14
15
16
17
18
19
20
21
22
23
24
VSSB
IND
VBOOST
VBAT
(GPIO, TMS, SWDIO) P1[0]
(GPIO, TCK, SWDCK) P1[1]
1
2
3
4
5
6
(GPIO) P1[6]
(GPIO) P1[7]
[6]
(USBIO, D+, SWDIO) P15[6]
[6]
(USBIO, D-, SWDCK) P15[7]
VDDD
VSSD
VCCD
(GPIO, MHZ XTAL: XO) P15[0]
(GPIO, MHZ XTAL: XI) P15[1]
VDDIO3
(SIO, I2C1: SCL) P12[0]
(GPIO) P2[6]
(GPIO) P2[7]
48
47
P2[5] (GPIO)
VDDIO2
P2[4] (GPIO)
P2[3] (GPIO)
VDDD
VSSD
VCCD
P0[7] (IDAC2, GPIO)
P0[6] (IDAC0, GPIO)
P0[5] (OPAMP2-, GPIO)
P0[4] (OPAMP2+, GPIO)
VDDIO0
Figure 2-4. 48-pin QFN Part Pinout[7]
Notes
5. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
6. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
7. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal. For more information, see AN72845, Design Guidelines for QFN Devices.
Document Number: 001-53304 Rev. AA
Page 7 of 137
PSoC® 3: CY8C34 Family Datasheet
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
P2[5] (GPIO)
VDDIO2
P2[4] (GPIO)
P2[3] (GPIO)
P2[2] (GPIO)
P2[1] (GPIO)
P2[0] (GPIO)
P15[5] (GPOI)
P15[4] (GPIO)
VDDD
VSSD
VCCD
P0[7] (GPIO, IDAC2)
P0[6] (GPIO, IDAC0)
P0[5] (GPIO, OPAMP2-)
P0[4] (GPIO, OPAMP2+)
VDDIO0
Figure 2-5. 68-Pin QFN Part Pinout[9]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
51
50
Lines show VDDIO
to I/O supply
association
QFN
(Top View)
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
P0[3] (GPIO, OPAMP0-/EXTREF0)
P0[2] (GPIO, OPAMP0+)
P0[1] (GPIO, OPAMP0OUT)
P0[0] (GPIO, OPAMP2OUT)
P12[3] (SIO)
P12[2] (SIO)
VSSD
VDDA
VSSA
VCCA
P15[3] (GPIO, KHZ XTAL: XI)
P15[2] (GPIO, KHZ XTAL: XO)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, 12C1: SCL)
P3[7] (GPIO)
P3[6] (GPIO)
VDDIO3
(GPIO) P1[6]
(GPIO) P1[7]
(SIO) P12[6]
(SIO) P12[7]
[8]
(USBIO, D+, SWDIO) P15[6]
[8] (USBIO, D-, SWDCK) P15[7]
VDDD
VSSD
VCCD
(MHZ XTAL: XO, GPIO) P15[0]
(MHZ XTAL: XI, GPIO) P15[1]
(GPIO) P3[0]
(GPIO) P3[1]
(EXTREF1, GPIO) P3[2]
(GPIO) P3[3]
(GPIO) P3[4]
(GPIO) P3[5]
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
(GPIO) P2[6]
(GPIO) P2[7]
(I2C0: SCL, SIO) P12[4]
(I2C0: SDA, SIO) P12[5]
VSSB
IND
VBOOST
VBAT
VSSD
XRES
(TMS, SWDIO, GPIO) P1[0]
(TCK, SWDCK, GPIO) P1[1]
(CONFIGURABLE XRES, GPIO) P1[2]
(TDO, SWV, GPIO) P1[3]
(TDI, GPIO) P1[4]
(NTRST, GPIO) P1[5]
VDDIO1
Notes
8. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
9. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal. For more information, see AN72845, Design Guidelines for QFN Devices.
Document Number: 001-53304 Rev. AA
Page 8 of 137
PSoC® 3: CY8C34 Family Datasheet
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
P4[5] (GPIO)
P4[4] (GPIO)
P4[3] (GPIO)
P4[2] (GPIO)
P0[7] (GPIO, IDAC2)
P0[6] (GPIO, IDAC0)
P0[5] (GPIO, OPAMP2-)
P0[4] (GPIO,
OPAMP2+)
75
74
Lines show
VDDIO to I/O
supply
association
TQFP
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
54
53
52
51
VDDIO0
P0[3] (GPIO, OPAMP0-/EXTREF0)
P0[2] (GPIO, OPAMP0+)
P0[1] (GPIO, OPAMP0OUT)
P0[0] (GPIO, OPAMP2OUT)
P4[1] (GPIO)
P4[0] (GPIO)
P12[3] (SIO)
P12[2] (SIO)
VSSD
VDDA
VSSA
VCCA
NC
NC
NC
NC
NC
NC
P15[3] (GPIO, KHZ XTAL: XI)
P15[2] (GPIO, KHZ XTAL: XO)
P12[1] (SIO, I2C1: SDA)
P12[0] (SIO, I2C1: SCL)
P3[7] (GPIO)
P3[6] (GPIO)
VDDIO1
(GPIO) P1[6]
(GPIO) P1[7]
(SIO) P12[6]
(SIO) P12[7]
(GPIO) P5[4]
(GPIO) P5[5]
(GPIO) P5[6]
[10]
(GPIO) P5[7]
[10] (USBIO, D+, SWDIO) P15[6]
(USBIO, D-, SWDCK) P15[7]
VDDD
VSSD
VCCD
NC
NC
(MHZ XTAL: XO, GPIO) P15[0]
(MHZ XTAL: XI, GPIO) P15[1]
(GPIO) P3[0]
(GPIO) P3[1]
(EXTREF1, GPIO) P3[2]
(GPIO) P3[3]
(GPIO) P3[4]
(GPIO) P3[5]
VDDIO3
(GPIO) P2[5]
(GPIO) P2[6]
(GPIO) P2[7]
(I2C0: SCL, SIO) P12[4]
(I2C0: SDA, SIO) P12[5]
(GPIO) P6[4]
(GPIO) P6[5]
(GPIO) P6[6]
(GPIO) P6[7]
VSSB
IND
VBOOST
VBAT
VSSD
XRES
(GPIO) P5[0]
(GPIO) P5[1]
(GPIO) P5[2]
(GPIO) P5[3]
(TMS, SWDIO, GPIO) P1[0]
(TCK, SWDCK, GPIO) P1[1]
(CONFIGURABLE XRES, GPIO) P1[2]
(TDO, SWV, GPIO) P1[3]
(TDI, GPIO) P1[4]
(NTRST, GPIO) P1[5]
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
VDDIO2
P2[4] (GPIO)
P2[3] (GPIO)
P2[2] (GPIO)
P2[1] (GPIO)
P2[0] (GPIO)
P15[5] (GPIO)
P15[4] (GPIO)
P6[3] (GPIO)
P6[2] (GPIO)
P6[1] (GPIO)
P6[0] (GPIO)
VDDD
VSSD
VCCD
P4[7] (GPIO)
P4[6] (GPIO)
Figure 2-6. 100-pin TQFP Part Pinout
Table 2-1. VDDIO and Port Pin Associations
VDDIO
Port Pins
VDDIO0
P0[7:0], P4[7:0], P12[3:2]
VDDIO1
P1[7:0], P5[7:0], P12[7:6]
VDDIO2
P2[7:0], P6[7:0], P12[5:4], P15[5:4]
VDDIO3
P3[7:0], P12[1:0], P15[3:0]
VDDD
P15[7:6] (USB D+, D-)
Note
10. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-53304 Rev. AA
Page 9 of 137
PSoC® 3: CY8C34 Family Datasheet
Figure 2-7 and Figure 2-8 on page 11 show an example schematic and an example PCB layout, for the 100-pin TQFP part, for optimal
analog performance on a two-layer board.
The two pins labeled VDDD must be connected together.
The two pins labeled VCCD must be connected together, with capacitance added, as shown in Figure 2-7 and Power System on
page 30. The trace between the two VCCD pins should be as short as possible.
The two pins labeled VSSD must be connected together.
For information on circuit board layout issues for mixed signals, refer to the application note AN57821 - Mixed Signal Circuit Board
Layout Considerations for PSoC® 3 and PSoC 5.
Figure 2-7. Example Schematic for 100-pin TQFP Part With Power Connections
VDDD
C1
1uF
VDDD
VSSD
VSSD
VDDD
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDA
C8
0.1uF
VSSD
VSSD
VDDA
VSSA
VCCA
C17
1uF
VSSA
VDDA
C9
1uF
C10
0.1uF
VSSA
VDDD
C11
0.1uF
VCCD
VDDD
VSSD
C12
0.1uF
VSSD
VDDD
VDDIO0
OA0-, REF0, P0[3]
OA0+, P0[2]
OA0OUT, P0[1]
OA2OUT, P0[0]
P4[1]
P4[0]
SIO, P12[3]
SIO, P12[2]
VSSD
VDDA
VSSA
VCCA
NC
NC
NC
NC
NC
NC
KHZXIN, P15[3]
KHZXOUT, P15[2]
SIO, P12[1]
SIO, P12[0]
OA3OUT, P3[7]
OA1OUT, P3[6]
VDDIO1
P1[6]
P1[7]
P12[6], SIO
P12[7], SIO
P5[4]
P5[5]
P5[6]
P5[7]
P15[6], USB D+
P15[7], USB DVDDD
VSSD
VCCD
NC
NC
P15[0], MHZXOUT
P15[1], MHZXIN
P3[0], IDAC1
P3[1], IDAC3
P3[2], OA3-, REF1
P3[3], OA3+
P3[4], OA1P3[5], OA1+
VDDIO3
P2[5]
P2[6]
P2[7]
P12[4], SIO
P12[5], SIO
P6[4]
P6[5]
P6[6]
P6[7]
VSSB
IND
VBOOST
VBAT
VSSD
XRES
P5[0]
P5[1]
P5[2]
P5[3]
P1[0], SWIO, TMS
P1[1], SWDIO, TCK
P1[2]
P1[3], SWV, TDO
P1[4], TDI
P1[5], NTRST
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSSD
VCCD
VSSD
VDDIO2
P2[4]
P2[3]
P2[2]
P2[1]
P2[0]
P15[5]
P15[4]
P6[3]
P6[2]
P6[1]
P6[0]
VDDD
VSSD
VCCD
P4[7]
P4[6]
P4[5]
P4[4]
P4[3]
P4[2]
IDAC2, P0[7]
IDAC0, P0[6]
OA2-, P0[5]
OA2+, P0[4]
VSSD
VSSD
C2
0.1uF
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
C6
0.1uF
VDDD
VDDD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDDD
C15
1uF
C16
0.1uF
VSSD
VSSD
Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended,
as shown in Figure 2-8 on page 11.
For more information on pad layout, refer to http://www.cypress.com/cad-resources/psoc-3-cad-libraries.
Document Number: 001-53304 Rev. AA
Page 10 of 137
PSoC® 3: CY8C34 Family Datasheet
Figure 2-8. Example PCB Layout for 100-pin TQFP Part for Optimal Analog Performance
VSSA
VDDD
VSSD
VDDA
VSSA
Plane
VSSD
Plane
3. Pin Descriptions
IDAC0, IDAC2
Low resistance output pin for high current DACs (IDAC).
OpAmp0out, OpAmp2out
High current output of uncommitted opamp[11].
Extref0, Extref1
MHz XTAL: Xo, MHz XTAL: Xi
4- to 25-MHz crystal oscillator pin.
nTRST
Optional JTAG test reset programming and debug port
connection to reset the JTAG connection.
SIO
Opamp0–, Opamp2–
Special I/O provides interfaces to the CPU, digital peripherals
and interrupts with a programmable high threshold voltage,
analog comparator, high sink current, and high impedance state
when the device is unpowered.
Inverting input to uncommitted opamp.
SWDCK
Opamp0+, Opamp2+
Noninverting input to uncommitted opamp.
Serial wire debug clock programming and debug port
connection.
GPIO
SWDIO
General purpose I/O pin provides interfaces to the CPU, digital
peripherals, analog peripherals, interrupts, LCD segment drive,
and CapSense[11].
Serial wire debug input and output programming and debug port
connection.
I2C0: SCL, I2C1: SCL
Single wire viewer debug output.
External reference input to the analog system.
I2C SCL line providing wake from sleep on an address match.
Any I/O pin can be used for I2C SCL if wake from sleep is not
required.
SWV
TCK
JTAG test clock programming and debug port connection.
I2C0: SDA, I2C1: SDA
TDI
I2C
JTAG test data In programming and debug port connection.
SDA line providing wake from sleep on an address match.
Any I/O pin can be used for I2C SDA if wake from sleep is not
required.
Ind
Inductor connection to boost pump.
kHz XTAL: Xo, kHz XTAL: Xi
TDO
JTAG test data out programming and debug port connection.
TMS
JTAG test mode select programming and debug port connection.
32.768-kHz crystal oscillator pin.
Note
11. GPIOs with opamp outputs are not recommended for use with CapSense.
Document Number: 001-53304 Rev. AA
Page 11 of 137
PSoC® 3: CY8C34 Family Datasheet
USBIO, D+
XRES (and configurable XRES)
Provides D+ connection directly to a USB 2.0 bus. May be used
as a digital I/O pin. Pins are Do Not Use (DNU) on devices
without USB.
External reset pin. Active low with internal pull-up. Pin P1[2] may
be configured to be a XRES pin; see “Nonvolatile Latches
(NVLs)” on page 23.
USBIO, D–
Provides D– connection directly to a USB 2.0 bus. May be used
as a digital I/O pin. Pins are No Connect (NC) on devices without
USB.
VBOOST
Power sense connection to boost pump.
VBAT
Battery supply to boost pump.
VCCA.
Output of the analog core regulator or the input to the
analog core. Requires a 1uF capacitor to VSSA. The regulator
output is not designed to drive external circuits. Note that if you
use the device with an external core regulator (externally
regulated mode), the voltage applied to this pin must not
exceed the allowable range of 1.71 V to 1.89 V. When using
the internal core regulator, (internally regulated mode, the
default), do not tie any power to this pin. For details see Power
System on page 30.
VCCD.
Output of the digital core regulator or the input to the digital
core. The two VCCD pins must be shorted together, with the
trace between them as short as possible, and a 1uF capacitor to
VSSD. The regulator output is not designed to drive external
circuits. Note that if you use the device with an external core
regulator (externally regulated mode), the voltage applied to
this pin must not exceed the allowable range of 1.71 V to
1.89 V. When using the internal core regulator (internally
regulated mode, the default), do not tie any power to this pin. For
details see Power System on page 30.
VDDA
Supply for all analog peripherals and analog core regulator.
VDDA must be the highest voltage present on the device. All
other supply pins must be less than or equal to VDDA.
VDDD
Supply for all digital peripherals and digital core regulator. VDDD
must be less than or equal to VDDA.
VSSA
Ground for all analog peripherals.
VSSB
Ground connection for boost pump.
VSSD
Ground for all digital logic and I/O pins.
VDDIO0, VDDIO1, VDDIO2, VDDIO3
Supply for I/O pins. See pinouts for specific I/O pin to VDDIO
mapping. Each VDDIO must be tied to a valid operating voltage
(1.71 V to 5.5 V), and must be less than or equal to VDDA.
Document Number: 001-53304 Rev. AA
4. CPU
4.1 8051 CPU
The CY8C34 devices use a single cycle 8051 CPU, which is fully
compatible with the original MCS-51 instruction set. The
CY8C34 family uses a pipelined RISC architecture, which
executes most instructions in 1 to 2 cycles to provide peak
performance of up to 24 MIPS with an average of 2 cycles per
instruction. The single cycle 8051 CPU runs ten times faster than
a standard 8051 processor.
The 8051 CPU subsystem includes these features:
Single cycle 8051 CPU
Up to 64 KB of flash memory, up to 2 KB of EEPROM, and up
to 8 KB of SRAM
512-byte instruction cache between CPU and flash
Programmable nested vector interrupt controller
Direct memory access (DMA) controller
Peripheral HUB (PHUB)
External memory interface (EMIF)
4.2 Addressing Modes
The following addressing modes are supported by the 8051:
Direct Addressing: The operand is specified by a direct 8-bit
address field. Only the internal RAM and the SFRs can be
accessed using this mode.
Indirect Addressing: The instruction specifies the register which
contains the address of the operand. The registers R0 or R1
are used to specify the 8-bit address, while the data pointer
(DPTR) register is used to specify the 16-bit address.
Register Addressing: Certain instructions access one of the
registers (R0 to R7) in the specified register bank. These
instructions are more efficient because there is no need for an
address field.
Register Specific Instructions: Some instructions are specific
to certain registers. For example, some instructions always act
on the accumulator. In this case, there is no need to specify the
operand.
Immediate Constants: Some instructions carry the value of the
constants directly instead of an address.
Indexed Addressing: This type of addressing can be used only
for a read of the program memory. This mode uses the Data
Pointer as the base and the accumulator value as an offset to
read a program memory.
Bit Addressing: In this mode, the operand is one of 256 bits.
Page 12 of 137
PSoC® 3: CY8C34 Family Datasheet
4.3 Instruction Set
4.3.1 Instruction Set Summary
The 8051 instruction set is highly optimized for 8-bit handling and
Boolean operations. The types of instructions supported include:
4.3.1.1 Arithmetic Instructions
Arithmetic instructions
Logical instructions
Data transfer instructions
Arithmetic instructions support the direct, indirect, register,
immediate constant, and register-specific instructions.
Arithmetic modes are used for addition, subtraction,
multiplication, division, increment, and decrement operations.
Table 4-1 lists the different arithmetic instructions.
Boolean instructions
Program branching instructions
Table 4-1. Arithmetic Instructions
Mnemonic
Description
Bytes
Cycles
ADD
A,Rn
Add register to accumulator
1
1
ADD
A,Direct
Add direct byte to accumulator
2
2
ADD
A,@Ri
Add indirect RAM to accumulator
1
2
ADD
A,#data
Add immediate data to accumulator
2
2
ADDC A,Rn
Add register to accumulator with carry
1
1
ADDC A,Direct
Add direct byte to accumulator with carry
2
2
ADDC A,@Ri
Add indirect RAM to accumulator with carry
1
2
ADDC A,#data
Add immediate data to accumulator with carry
2
2
SUBB A,Rn
Subtract register from accumulator with borrow
1
1
SUBB A,Direct
Subtract direct byte from accumulator with borrow
2
2
SUBB A,@Ri
Subtract indirect RAM from accumulator with borrow
1
2
SUBB A,#data
Subtract immediate data from accumulator with borrow
2
2
INC
A
Increment accumulator
1
1
INC
Rn
Increment register
1
2
INC
Direct
Increment direct byte
2
3
INC
@Ri
Increment indirect RAM
1
3
DEC
A
Decrement accumulator
1
1
DEC
Rn
Decrement register
1
2
DEC
Direct
Decrement direct byte
2
3
DEC
@Ri
Decrement indirect RAM
1
3
INC
DPTR
Increment data pointer
1
1
MUL
Multiply accumulator and B
1
2
DIV
Divide accumulator by B
1
6
DAA
Decimal adjust accumulator
1
3
Document Number: 001-53304 Rev. AA
Page 13 of 137
PSoC® 3: CY8C34 Family Datasheet
4.3.1.2 Logical Instructions
The logical instructions perform Boolean operations such as AND, OR, XOR on bytes, rotate of accumulator contents, and swap of
nibbles in an accumulator. The Boolean operations on the bytes are performed on the bit-by-bit basis. Table 4-2 shows the list of
logical instructions and their description.
Table 4-2. Logical Instructions
Mnemonic
Description
Bytes
Cycles
ANL
A,Rn
AND register to accumulator
1
1
ANL
A,Direct
AND direct byte to accumulator
2
2
ANL
A,@Ri
AND indirect RAM to accumulator
1
2
ANL
A,#data
AND immediate data to accumulator
2
2
ANL
Direct, A
AND accumulator to direct byte
2
3
ANL
Direct, #data
AND immediate data to direct byte
3
3
ORL
A,Rn
OR register to accumulator
1
1
ORL
A,Direct
OR direct byte to accumulator
2
2
ORL
A,@Ri
OR indirect RAM to accumulator
1
2
ORL
A,#data
OR immediate data to accumulator
2
2
ORL
Direct, A
OR accumulator to direct byte
2
3
ORL
Direct, #data
OR immediate data to direct byte
3
3
XRL
A,Rn
XOR register to accumulator
1
1
XRL
A,Direct
XOR direct byte to accumulator
2
2
XRL
A,@Ri
XOR indirect RAM to accumulator
1
2
XRL
A,#data
XOR immediate data to accumulator
2
2
XRL
Direct, A
XOR accumulator to direct byte
2
3
XRL
Direct, #data
XOR immediate data to direct byte
3
3
CLR
A
Clear accumulator
1
1
CPL
A
Complement accumulator
1
1
RL
A
Rotate accumulator left
1
1
RLC
A
Rotate accumulator left through carry
1
1
RR
A
Rotate accumulator right
1
1
RRC A
Rotate accumulator right though carry
1
1
SWAP A
Swap nibbles within accumulator
1
1
Document Number: 001-53304 Rev. AA
Page 14 of 137
PSoC® 3: CY8C34 Family Datasheet
4.3.1.3 Data Transfer Instructions
4.3.1.4 Boolean Instructions
The data transfer instructions are of three types: the core RAM,
xdata RAM, and the lookup tables. The core RAM transfer
includes transfer between any two core RAM locations or SFRs.
These instructions can use direct, indirect, register, and
immediate addressing. The xdata RAM transfer includes only the
transfer between the accumulator and the xdata RAM location.
It can use only indirect addressing. The lookup tables involve
nothing but the read of program memory using the Indexed
addressing mode. Table 4-3 lists the various data transfer
instructions available.
The 8051 core has a separate bit addressable memory location.
It has 128 bits of bit-addressable RAM and a set of SFRs that are
bit addressable. The instruction set includes the whole menu of
bit operations such as move, set, clear, toggle, OR, and AND
instructions and the conditional jump instructions. Table 4-4 on
page 16 lists the available Boolean instructions.
Table 4-3. Data Transfer Instructions
Mnemonic
Description
Bytes
Cycles
MOV
A,Rn
Move register to accumulator
1
1
MOV
A,Direct
Move direct byte to accumulator
2
2
MOV
A,@Ri
Move indirect RAM to accumulator
1
2
MOV
A,#data
Move immediate data to accumulator
2
2
MOV
Rn,A
Move accumulator to register
1
1
MOV
Rn,Direct
Move direct byte to register
2
3
MOV
Rn, #data
Move immediate data to register
2
2
MOV
Direct, A
Move accumulator to direct byte
2
2
MOV
Direct, Rn
Move register to direct byte
2
2
MOV
Direct, Direct
Move direct byte to direct byte
3
3
MOV
Direct, @Ri
Move indirect RAM to direct byte
2
3
MOV
Direct, #data
Move immediate data to direct byte
3
3
MOV
@Ri, A
Move accumulator to indirect RAM
1
2
MOV
@Ri, Direct
Move direct byte to indirect RAM
2
3
MOV
@Ri, #data
Move immediate data to indirect RAM
2
2
MOV
DPTR, #data16
Load data pointer with 16-bit constant
3
3
MOVC A, @A+DPTR
Move code byte relative to DPTR to accumulator
1
5
MOVC A, @A + PC
Move code byte relative to PC to accumulator
1
4
MOVX A,@Ri
Move external RAM (8-bit) to accumulator
1
4
MOVX A, @DPTR
Move external RAM (16-bit) to accumulator
1
3
MOVX @Ri, A
Move accumulator to external RAM (8-bit)
1
5
MOVX @DPTR, A
Move accumulator to external RAM (16-bit)
1
4
PUSH Direct
Push direct byte onto stack
2
3
POP
Direct
Pop direct byte from stack
2
2
XCH
A, Rn
Exchange register with accumulator
1
2
XCH
A, Direct
Exchange direct byte with accumulator
2
3
XCH
A, @Ri
Exchange indirect RAM with accumulator
1
3
Exchange low order indirect digit RAM with accumulator
1
3
XCHD A, @Ri
Document Number: 001-53304 Rev. AA
Page 15 of 137
PSoC® 3: CY8C34 Family Datasheet
Table 4-4. Boolean Instructions
Mnemonic
Description
Bytes
Cycles
CLR
C
Clear carry
1
1
CLR
bit
Clear direct bit
2
3
SETB C
Set carry
1
1
SETB bit
Set direct bit
2
3
CPL
Complement carry
1
1
C
CPL
bit
Complement direct bit
2
3
ANL
C, bit
AND direct bit to carry
2
2
ANL
C, /bit
AND complement of direct bit to carry
2
2
OR direct bit to carry
2
2
ORL C, /bit
OR complement of direct bit to carry
2
2
MOV C, bit
Move direct bit to carry
2
2
MOV bit, C
Move carry to direct bit
2
3
JC
Jump if carry is set
2
3
JNC rel
Jump if no carry is set
2
3
JB
Jump if direct bit is set
3
5
JNB bit, rel
Jump if direct bit is not set
3
5
JBC bit, rel
Jump if direct bit is set and clear bit
3
5
ORL C, bit
rel
bit, rel
4.3.1.5 Program Branching Instructions
The 8051 supports a set of conditional and unconditional jump instructions that help to modify the program execution flow. Table 4-5
shows the list of jump instructions.
Table 4-5. Jump Instructions
Mnemonic
Description
Bytes
Cycles
ACALL addr11
Absolute subroutine call
2
4
LCALL addr16
Long subroutine call
3
4
RET
Return from subroutine
1
4
RETI
Return from interrupt
1
4
AJMP addr11
Absolute jump
2
3
LJMP addr16
Long jump
3
4
SJMP rel
Short jump (relative address)
2
3
JMP @A + DPTR
Jump indirect relative to DPTR
1
5
JZ rel
Jump if accumulator is zero
2
4
JNZ rel
Jump if accumulator is nonzero
2
4
CJNE A,Direct, rel
Compare direct byte to accumulator and jump if not equal
3
5
CJNE A, #data, rel
Compare immediate data to accumulator and jump if not equal
3
4
CJNE Rn, #data, rel
Compare immediate data to register and jump if not equal
3
4
CJNE @Ri, #data, rel
Compare immediate data to indirect RAM and jump if not equal
3
5
DJNZ Rn,rel
Decrement register and jump if not zero
2
4
DJNZ Direct, rel
Decrement direct byte and jump if not zero
3
5
NOP
No operation
1
1
Document Number: 001-53304 Rev. AA
Page 16 of 137
PSoC® 3: CY8C34 Family Datasheet
4.4 DMA and PHUB
Any digitally routable signal, the CPU, or another DMA channel,
The PHUB and the DMA controller are responsible for data
transfer between the CPU and peripherals, and also data
transfers between peripherals. The PHUB and DMA also control
device configuration during boot. The PHUB consists of:
A central hub that includes the DMA controller, arbiter, and
router
Multiple spokes that radiate outward from the hub to most
peripherals
There are two PHUB masters: the CPU and the DMA controller.
Both masters may initiate transactions on the bus. The DMA
channels can handle peripheral communication without CPU
intervention. The arbiter in the central hub determines which
DMA channel is the highest priority if there are multiple requests.
4.4.1 PHUB Features
CPU and DMA controller are both bus masters to the PHUB
Eight Multi-layer AHB Bus parallel access paths (spokes) for
peripheral access
Simultaneous CPU and DMA access to peripherals located on
different spokes
Simultaneous DMA source and destination burst transactions
on different spokes
Supports 8, 16, 24, and 32-bit addressing and data
Table 4-6. PHUB Spokes and Peripherals
can trigger a transaction
Each channel can generate up to two interrupts per transfer
Transactions can be stalled or canceled
Supports transaction size of infinite or 1 to 64 KB
TDs may be nested and/or chained for complex transactions
4.4.3 Priority Levels
The CPU always has higher priority than the DMA controller
when their accesses require the same bus resources. Due to the
system architecture, the CPU can never starve the DMA. DMA
channels of higher priority (lower priority number) may interrupt
current DMA transfers. In the case of an interrupt, the current
transfer is allowed to complete its current transaction. To ensure
latency limits when multiple DMA accesses are requested
simultaneously, a fairness algorithm guarantees an interleaved
minimum percentage of bus bandwidth for priority levels 2
through 7. Priority levels 0 and 1 do not take part in the fairness
algorithm and may use 100 percent of the bus bandwidth. If a tie
occurs on two DMA requests of the same priority level, a simple
round robin method is used to evenly share the allocated
bandwidth. The round robin allocation can be disabled for each
DMA channel, allowing it to always be at the head of the line.
Priority levels 2 to 7 are guaranteed the minimum bus bandwidth
shown in Table 4-7 after the CPU and DMA priority levels 0 and
1 have satisfied their requirements.
Table 4-7. Priority Levels
Priority Level
% Bus Bandwidth
SRAM
0
100.0
1
IOs, PICU, EMIF
1
100.0
2
PHUB local configuration, Power manager,
Clocks, IC, SWV, EEPROM, Flash
programming interface
2
50.0
3
25.0
4
12.5
5
6.2
6
3.1
7
1.5
PHUB Spokes
0
Peripherals
3
Analog interface and trim, Decimator
4
USB, CAN, I2C, Timers, Counters, and PWMs
5
Reserved
6
UDBs group 1
7
UDBs group 2
4.4.2 DMA Features
When the fairness algorithm is disabled, DMA access is granted
based solely on the priority level; no bus bandwidth guarantees
are made.
Twenty-four DMA channels
4.4.4 Transaction Modes Supported
Each channel has one or more Transaction Descriptors (TDs)
The flexible configuration of each DMA channel and the ability to
chain multiple channels allow the creation of both simple and
complex use cases. General use cases include, but are not
limited to:
to configure channel behavior. Up to 128 total TDs can be
defined
TDs can be dynamically updated
Eight levels of priority per channel
Document Number: 001-53304 Rev. AA
Page 17 of 137
PSoC® 3: CY8C34 Family Datasheet
4.4.4.1 Simple DMA
In a simple DMA case, a single TD transfers data between a source and sink (peripherals or memory location). The basic timing
diagrams of DMA read and write cycles are shown in Figure 4-1. For more description on other transfer modes, refer to the Technical
Reference Manual.
Figure 4-1. DMA Timing Diagram
ADDRESS Phase
DATA Phase
ADDRESS Phase
CLK
DATA Phase
CLK
ADDR 16/32
A
ADDR 16/32
B
WRITE
A
B
WRITE
DATA (A)
DATA
READY
DATA (A)
DATA
READY
Basic DMA Write Transfer without wait states
Basic DMA Read Transfer without wait states
A ping pong DMA case uses double buffering to allow one buffer
to be filled by one client while another client is consuming the
data previously received in the other buffer. In its simplest form,
this is done by chaining two TDs together so that each TD calls
the opposite TD when complete.
can set up this configuration information anywhere in system
memory and copy it with a simple TD to the peripheral. After the
configuration phase, a data phase TD (or a series of data phase
TDs) can begin (potentially using scatter gather). When the data
phase TD(s) finish, a status phase TD can be invoked that reads
some memory mapped status information from the peripheral
and copies it to a location in system memory specified by the
CPU for later inspection. Multiple sets of configuration, data, and
status phase “subchains” can be strung together to create larger
chains that transmit multiple packets in this way. A similar
concept exists in the opposite direction to receive the packets.
4.4.4.4 Circular DMA
4.4.4.7 Nested DMA
4.4.4.2 Auto Repeat DMA
Auto repeat DMA is typically used when a static pattern is
repetitively read from system memory and written to a peripheral.
This is done with a single TD that chains to itself.
4.4.4.3 Ping Pong DMA
Circular DMA is similar to ping pong DMA except it contains more
than two buffers. In this case there are multiple TDs; after the last
TD is complete it chains back to the first TD.
4.4.4.5 Scatter Gather DMA
In the case of scatter gather DMA, there are multiple
noncontiguous sources or destinations that are required to
effectively carry out an overall DMA transaction. For example, a
packet may need to be transmitted off of the device and the
packet elements, including the header, payload, and trailer, exist
in various noncontiguous locations in memory. Scatter gather
DMA allows the segments to be concatenated together by using
multiple TDs in a chain. The chain gathers the data from the
multiple locations. A similar concept applies for the reception of
data onto the device. Certain parts of the received data may need
to be scattered to various locations in memory for software
processing convenience. Each TD in the chain specifies the
location for each discrete element in the chain.
One TD may modify another TD, as the TD configuration space
is memory mapped similar to any other peripheral. For example,
a first TD loads a second TD’s configuration and then calls the
second TD. The second TD moves data as required by the
application. When complete, the second TD calls the first TD,
which again updates the second TD’s configuration. This
process repeats as often as necessary.
4.5 Interrupt Controller
The interrupt controller provides a mechanism for hardware
resources to change program execution to a new address,
independent of the current task being executed by the main
code. The interrupt controller provides enhanced features not
found on original 8051 interrupt controllers:
Thirty two interrupt vectors
Jumps directly to ISR anywhere in code space with dynamic
vector addresses
4.4.4.6 Packet Queuing DMA
Multiple sources for each vector
Packet queuing DMA is similar to scatter gather DMA but
specifically refers to packet protocols. With these protocols,
there may be separate configuration, data, and status phases
associated with sending or receiving a packet.
Flexible interrupt to vector matching
For instance, to transmit a packet, a memory mapped
configuration register can be written inside a peripheral,
specifying the overall length of the ensuing data phase. The CPU
Document Number: 001-53304 Rev. AA
Each interrupt vector is independently enabled or disabled
Each interrupt can be dynamically assigned one of eight
priorities
Eight level nestable interrupts
Page 18 of 137
PSoC® 3: CY8C34 Family Datasheet
Multiple I/O interrupt vectors
direct connections to the most common interrupt sources and provide the lowest
resource cost connection. The DMA interrupt sources provide direct connections to
the two DMA interrupt sources provided per DMA channel. The third interrupt source
for vectors is from the UDB digital routing array. This allows any digital signal
available to the UDB array to be used as an interrupt source. Fixed function interrupts
and all interrupt sources may be routed to any interrupt vector using the UDB interrupt
source connections.
Software can send interrupts
Software can clear pending interrupts
When an interrupt is pending, the current instruction is completed and the program
counter is pushed onto the stack. Code execution then jumps to the program address
provided by the vector. After the ISR is completed, a RETI instruction is executed and
returns execution to the instruction following the previously interrupted instruction. To
do this the RETI instruction pops the program counter from the stack.
Figure 4-2 represents typical flow of events when an interrupt triggered. Figure 4-3
on page 20 shows the interrupt structure and priority polling.
If the same priority level is assigned to two or more interrupts, the interrupt with the
lower vector number is executed first. Each interrupt vector may choose from three
interrupt sources: Fixed Function, DMA, and UDB. The fixed function interrupts are
Figure 4-2. Interrupt Processing Timing Diagram
1
2
3
4
5
6
7
8
9
10
11
S
CLK
Arrival of new Interrupt
INT_INPUT
S
Pend bit is set on next clock active edge
POST and PEND bits cleared after IRQ is sleared
PEND
S
Interrupt is posted to ascertain the priority
POST
S
IRQ cleared after receiving IRA
Interrupt request sent to core for processing
IRQ
ACTIVE_INT_NUM
(#10)
INT_VECT_ADDR
NA
NA
0x0010
S
S
The active interrupt
number is posted to core
The active interrupt ISR
address is posted to core
0x0000
S
S
NA
S
IRA
S
IRC
Interrupt generation and posting to CPU
CPU Response
Int. State
Clear
S
Completing current instruction and branching to vector address
Complete ISR and return
TIME
Notes
1: Interrupt triggered asynchronous to the clock
2: The PEND bit is set on next active clock edge to indicate the interrupt arrival
3: POST bit is set following the PEND bit
4: Interrupt request and the interrupt number sent to CPU core after evaluation priority (Takes 3 clocks)
5: ISR address is posted to CPU core for branching
Document Number: 001-53304 Rev. AA
Page 19 of 137
PSoC® 3: CY8C34 Family Datasheet
6: CPU acknowledges the interrupt request
7: ISR address is read by CPU for branching
8, 9: PEND and POST bits are cleared respectively after receiving the IRA from core
10: IRA bit is cleared after completing the current instruction and starting the instruction execution from ISR location (takes 7 cycles)
11: IRC is set to indicate the completion of ISR, Active int. status is restored with previous status
The total interrupt latency (ISR execution)
= POST + PEND + IRQ + IRA + Completing current instruction and branching
= 1+1+1+2+7 cycles
= 12 cycles
Figure 4-3. Interrupt Structure
Interrupt Polling logic
Interrupts form Fixed
function blocks, DMA and
UDBs
Highest Priority
Interrupt Enable/
Disable, PEND and
POST logic
Interrupts 0 to 31
from UDBs
0
Interrupts 0 to 31
from Fixed
Function Blocks
1
IRQ
8 Level
Priority
decoder
for all
interrupts
Polling sequence
Interrupt
routing logic
to select 32
sources
Interrupt 2 to 30
Interrupts 0 to
31 from DMA
Individual
Enable Disable
bits
0 to 31
ACTIVE_INT_NUM
[15:0]
INT_VECT_ADDR
IRA
IRC
31
Global Enable
disable bit
Document Number: 001-53304 Rev. AA
Lowest Priority
Page 20 of 137
PSoC® 3: CY8C34 Family Datasheet
Table 4-8. Interrupt Vector Table
#
Fixed Function
DMA
phub_termout0[0]
UDB
0
LVD
udb_intr[0]
1
Cache/ECC
phub_termout0[1]
udb_intr[1]
2
Reserved
phub_termout0[2]
udb_intr[2]
3
Sleep (Pwr Mgr)
phub_termout0[3]
udb_intr[3]
4
PICU[0]
phub_termout0[4]
udb_intr[4]
5
PICU[1]
phub_termout0[5]
udb_intr[5]
6
PICU[2]
phub_termout0[6]
udb_intr[6]
7
PICU[3]
phub_termout0[7]
udb_intr[7]
8
PICU[4]
phub_termout0[8]
udb_intr[8]
9
PICU[5]
phub_termout0[9]
udb_intr[9]
10
PICU[6]
phub_termout0[10] udb_intr[10]
11
PICU[12]
phub_termout0[11]
12
PICU[15]
phub_termout0[12] udb_intr[12]
13
Comparators
Combined
phub_termout0[13] udb_intr[13]
14
Switched Caps
Combined
phub_termout0[14] udb_intr[14]
15
I2C
phub_termout0[15] udb_intr[15]
16
CAN
phub_termout1[0]
udb_intr[16]
17
Timer/Counter0
phub_termout1[1]
udb_intr[17]
18
Timer/Counter1
phub_termout1[2]
udb_intr[18]
19
Timer/Counter2
phub_termout1[3]
udb_intr[19]
20
Timer/Counter3
phub_termout1[4]
udb_intr[20]
21
USB SOF Int
phub_termout1[5]
udb_intr[21]
22
USB Arb Int
phub_termout1[6]
udb_intr[22]
23
USB Bus Int
phub_termout1[7]
udb_intr[23]
24
USB Endpoint[0]
phub_termout1[8]
udb_intr[24]
25
USB Endpoint Data phub_termout1[9]
udb_intr[25]
26
Reserved
phub_termout1[10] udb_intr[26]
27
LCD
phub_termout1[11]
28
Reserved
phub_termout1[12] udb_intr[28]
udb_intr[11]
udb_intr[27]
29
Decimator Int
phub_termout1[13] udb_intr[29]
30
PHUB Error Int
phub_termout1[14] udb_intr[30]
31
EEPROM Fault Int
phub_termout1[15] udb_intr[31]
Document Number: 001-53304 Rev. AA
Page 21 of 137
PSoC® 3: CY8C34 Family Datasheet
5. Memory
5.1 Static RAM
CY8C34 Static RAM (SRAM) is used for temporary data storage.
Up to 8 KB of SRAM is provided and can be accessed by the
8051 or the DMA controller. See Memory Map on page 25.
Simultaneous access of SRAM by the 8051 and the DMA
controller is possible if different 4-KB blocks are accessed.
“Device Security” section on page 68). For more information
about how to take full advantage of the security features in
PSoC, see the PSoC 3 TRM.
Table 5-1. Flash Protection
Protection
Setting
Allowed
Not Allowed
Unprotected
External read and write + internal read and write
Flash memory in PSoC devices provides nonvolatile storage for
user firmware, user configuration data, bulk data storage, and
optional ECC data. The main flash memory area contains up to
64 KB of user program space.
Factory
Upgrade
External write + internal
read and write
External read
Field Upgrade
Internal read and write
External read and
write
Up to an additional 8 KB of flash space is available for Error
Correcting Codes (ECC). If ECC is not used this space can store
device configuration data and bulk user data. User code may not
be run out of the ECC flash memory section. ECC can correct
one bit error and detect two bit errors per 8 bytes of firmware
memory; an interrupt can be generated when an error is
detected.
Full Protection
Internal read
External read and
write + internal write
5.2 Flash Program Memory
The CPU reads instructions located in flash through a cache
controller. This improves instruction execution rate and reduces
system power consumption by requiring less frequent flash
access. The cache has 8 lines at 64 bytes per line for a total of
512 bytes. It is fully associative, automatically controls flash
power, and can be enabled or disabled. If ECC is enabled, the
cache controller also performs error checking and correction,
and interrupt generation.
Flash programming is performed through a special interface and
preempts code execution out of flash. The flash programming
interface performs flash erasing, programming and setting code
protection levels. Flash in-system serial programming (ISSP),
typically used for production programming, is possible through
both the SWD and JTAG interfaces. In-system programming,
typically used for bootloaders, is also possible using serial
interfaces such as I2C, USB, UART, and SPI, or any
communications protocol.
5.3 Flash Security
All PSoC devices include a flexible flash-protection model that
prevents access and visibility to on-chip flash memory. This
prevents duplication or reverse engineering of proprietary code.
Flash memory is organized in blocks, where each block contains
256 bytes of program or data and 32 bytes of ECC or
configuration data. A total of up to 256 blocks is provided on
64-KB flash devices.
The device offers the ability to assign one of four protection
levels to each row of flash. Table 5-1 lists the protection modes
available. Flash protection levels can only be changed by
performing a complete flash erase. The Full Protection and Field
Upgrade settings disable external access (through a debugging
tool such as PSoC Creator, for example). If your application
requires code update through a boot loader, then use the Field
Upgrade setting. Use the Unprotected setting only when no
security is needed in your application. The PSoC device also
offers an advanced security feature called Device Security which
permanently disables all test, programming, and debug ports,
protecting your application from external access (see the
Document Number: 001-53304 Rev. AA
Disclaimer
Note the following details of the flash code protection features on
Cypress devices.
Cypress products meet the specifications contained in their
particular Cypress data sheets. Cypress believes that its family
of products is one of the most secure families of its kind on the
market today, regardless of how they are used. There may be
methods, unknown to Cypress, that can breach the code
protection features. Any of these methods, to our knowledge,
would be dishonest and possibly illegal. Neither Cypress nor any
other semiconductor manufacturer can guarantee the security of
their code. Code protection does not mean that we are
guaranteeing the product as “unbreakable.”
Cypress is willing to work with the customer who is concerned
about the integrity of their code. Code protection is constantly
evolving. We at Cypress are committed to continuously
improving the code protection features of our products.
5.4 EEPROM
PSoC EEPROM memory is a byte-addressable nonvolatile
memory. The CY8C34 has up to 2 KB of EEPROM memory to
store user data. Reads from EEPROM are random access at the
byte level. Reads are done directly; writes are done by sending
write commands to an EEPROM programming interface. CPU
code execution can continue from flash during EEPROM writes.
EEPROM is erasable and writeable at the row level. The
EEPROM is divided into 128 rows of 16 bytes each. The factory
default values of all EEPROM bytes are 0.
Because the EEPROM is mapped to the 8051 xdata space, the
CPU cannot execute out of EEPROM. There is no ECC
hardware associated with EEPROM. If ECC is required it must
be handled in firmware.
It can take as much as 20 milliseconds to write to EEPROM or
flash. During this time the device should not be reset, or
unexpected changes may be made to portions of EEPROM or
flash. Reset sources (see Section 6.3.1) include XRES pin,
software reset, and watchdog; care should be taken to make
sure that these are not inadvertently activated. In addition, the
low voltage detect circuits should be configured to generate an
interrupt instead of a reset.
Page 22 of 137
PSoC® 3: CY8C34 Family Datasheet
5.5 Nonvolatile Latches (NVLs)
PSoC has a 4-byte array of nonvolatile latches (NVLs) that are used to configure the device at reset. The NVL register map is shown
in Table 5-2.
Table 5-2. Device Configuration NVL Register Map
Register Address
7
6
5
4
3
2
1
0
0x00
PRT3RDM[1:0]
PRT2RDM[1:0]
PRT1RDM[1:0]
PRT0RDM[1:0]
0x01
PRT12RDM[1:0]
PRT6RDM[1:0]
PRT5RDM[1:0]
PRT4RDM[1:0]
0x02
XRESMEN
0x03
DBGEN
DIG_PHS_DLY[3:0]
PRT15RDM[1:0]
ECCEN
DPS[1:0]
The details for individual fields and their factory default settings are shown in Table 5-3:.
Table 5-3. Fields and Factory Default Settings
Field
Description
Settings
PRTxRDM[1:0]
Controls reset drive mode of the corresponding IO
00b (default) - high impedance analog
port. See “Reset Configuration” on page 42. All pins 01b - high impedance digital
of the port are set to the same mode.
10b - resistive pull up
11b - resistive pull down
XRESMEN
Controls whether pin P1[2] is used as a GPIO or as 0 (default for 68-pin 72-pin, and 100-pin parts) - GPIO
an external reset. See “Pin Descriptions” on page 11, 1 (default for 48-pin parts) - external reset
XRES description.
DBGEN
Debug Enable allows access to the debug system, for 0 - access disabled
third-party programmers.
1 (default) - access enabled
DPS[1:0]
Controls the usage of various P1 pins as a debug port. 00b - 5-wire JTAG
See “Programming, Debug Interfaces, Resources” on 01b (default) - 4-wire JTAG
page 65.
10b - SWD
11b - debug ports disabled
ECCEN
Controls whether ECC flash is used for ECC or for
general configuration and data storage. See “Flash
Program Memory” on page 22.
0 - ECC disabled
1 (default) - ECC enabled
DIG_PHS_DLY[3:0]
Selects the digital clock phase delay.
See the TRM for details.
Although PSoC Creator provides support for modifying the device configuration NVLs, the number of NVL erase / write cycles is limited
– see “Nonvolatile Latches (NVL))” on page 109.
Document Number: 001-53304 Rev. AA
Page 23 of 137
PSoC® 3: CY8C34 Family Datasheet
5.6 External Memory Interface
CY8C34 provides an External Memory Interface (EMIF) for
connecting to external memory devices. The connection allows
read and write accesses to external memories. The EMIF
operates in conjunction with UDBs, I/O ports, and other
hardware to generate external memory address and control
signals. At 33 MHz, each memory access cycle takes four bus
clock cycles.
Figure 5-1 is the EMIF block diagram. The EMIF supports
synchronous and asynchronous memories. The CY8C34
supports only one type of external memory device at a time.
External memory can be accessed via the 8051 xdata space; up
to 24 address bits can be used. See “xdata Space” section on
page 26. The memory can be 8 or 16 bits wide.
Figure 5-1. EMIF Block Diagram
Address Signals
External_ MEM_ ADDR[23:0]
I/O
PORTs
Data Signals
External_ MEM_ DATA[15:0]
I/O
PORTs
Control Signals
I/O
PORTs
Data,
Address,
and Control
Signals
I/O IF
PHUB
Data,
Address,
and Control
Signals
Control
DSI Dynamic Output
Control
UDB
DSI to Port
Data,
Address,
and Control
Signals
EM Control
Signals
Other
Control
Signals
EMIF
Document Number: 001-53304 Rev. AA
Page 24 of 137
PSoC® 3: CY8C34 Family Datasheet
5.7 Memory Map
Figure 5-2. 8051 Internal Data Space
The CY8C34 8051 memory map is very similar to the MCS-51
memory map.
5.7.1 Code Space
The CY8C34 8051 code space is 64 KB. Only main flash exists
in this space. See the “Flash Program Memory” section on
page 22.
0x00
4 Banks, R0-R7 Each
0x1F
0x20
Bit-Addressable Area
0x2F
0x30
0x7F
Lower Core RAM Shared with Stack Space
(direct and indirect addressing)
0x80
5.7.2 Internal Data Space
The CY8C34 8051 internal data space is 384 bytes, compressed
within a 256-byte space. This space consists of 256 bytes of
RAM (in addition to the SRAM mentioned in Static RAM on page
22) and a 128-byte space for Special Function Registers (SFRs).
See Figure 5-2. The lowest 32 bytes are used for 4 banks of
registers R0-R7. The next 16 bytes are bit-addressable.
0xFF
Upper Core RAM Shared
with Stack Space
(indirect addressing)
SFR
Special Function Registers
(direct addressing)
In addition to the register or bit address modes used with the
lower 48 bytes, the lower 128 bytes can be accessed with direct
or indirect addressing. With direct addressing mode, the upper
128 bytes map to the SFRs. With indirect addressing mode, the
upper 128 bytes map to RAM. Stack operations use indirect
addressing; the 8051 stack space is 256 bytes. See the
“Addressing Modes” section on page 12
5.7.3 SFRs
The Special Function Register (SFR) space provides access to frequently accessed registers. The memory map for the SFR memory
space is shown in Table 5-4.
Table 5-4. SFR Map
Address
0/8
0×F8
SFRPRT15DR
0×F0
B
0×E8
SFRPRT12DR
0×E0
ACC
0×D8
SFRPRT6DR
0×D0
PSW
0×C8
0×C0
1/9
SFRPRT15PS
2/A
3/B
4/C
5/D
6/E
7/F
SFRPRT15SEL
SFRPRT12SEL
SFRPRT12PS
MXAX
SFRPRT6PS
SFRPRT6SEL
SFRPRT5DR
SFRPRT5PS
SFRPRT5SEL
SFRPRT4DR
SFRPRT4PS
SFRPRT4SEL
SFRPRT3DR
SFRPRT3PS
SFRPRT3SEL
0×B8
0×B0
0×A8
IE
0×A0
P2AX
SFRPRT1SEL
0×98
SFRPRT2DR
SFRPRT2PS
0×90
SFRPRT1DR
SFRPRT1PS
0×88
0×80
SFRPRT0DR
SFRPRT2SEL
DPX0
SFRPRT0PS
SFRPRT0SEL
SP
DPL0
Document Number: 001-53304 Rev. AA
DPH0
DPX1
DPL1
DPH1
DPS
Page 25 of 137
PSoC® 3: CY8C34 Family Datasheet
The CY8C34 family provides the standard set of registers found
on industry standard 8051 devices. In addition, the CY8C34
devices add SFRs to provide direct access to the I/O ports on the
device. The following sections describe the SFRs added to the
CY8C34 family.
5.7.4 XData Space Access SFRs
The 8051 core features dual DPTR registers for faster data
transfer operations. The data pointer select SFR, DPS, selects
which data pointer register, DPTR0 or DPTR1, is used for the
following instructions:
MOVX @DPTR, A
MOVX A, @DPTR
MOVC A, @A+DPTR
JMP @A+DPTR
INC DPTR
MOV DPTR, #data16
The extended data pointer SFRs, DPX0, DPX1, MXAX, and
P2AX, hold the most significant parts of memory addresses
during access to the xdata space. These SFRs are used only
with the MOVX instructions.
During a MOVX instruction using the DPTR0/DPTR1 register,
the most significant byte of the address is always equal to the
contents of DPX0/DPX1. During a MOVX instruction using the
R0 or R1 register, the most significant byte of the address is
always equal to the contents of MXAX, and the next most
significant byte is always equal to the contents of P2AX.
5.7.5 I/O Port SFRs
The I/O ports provide digital input sensing, output drive, pin
interrupts, connectivity for analog inputs and outputs, LCD, and
access to peripherals through the DSI. Full information on I/O
ports is found in I/O System and Routing on page 36.
I/O ports are linked to the CPU through the PHUB and are also
available in the SFRs. Using the SFRs allows faster access to a
limited set of I/O port registers, while using the PHUB allows boot
configuration and access to all I/O port registers.
Each SFR supported I/O port provides three SFRs:
SFRPRTxDR sets the output data state of the port (where x is
5.7.5.1 xdata Space
The 8051 xdata space is 24-bit, or 16 MB in size. The majority of
this space is not “external”—it is used by on-chip components.
See Table 5-5. External, that is, off-chip, memory can be
accessed using the EMIF. See External Memory Interface on
page 24.
Table 5-5. XDATA Data Address Map
Address Range
0×00 0000 – 0×00 1FFF
0×00 4000 – 0×00 42FF
0×00 4300 – 0×00 43FF
0×00 4400 – 0×00 44FF
0×00 4500 – 0×00 45FF
0×00 4700 – 0×00 47FF
0×00 4800 - 0×00 48FF
0×00 4900 – 0×00 49FF
0×00 4E00 – 0×00
4EFF
0×00 4F00 – 0×00
4FFF
0×00 5000 – 0×00 51FF
0×00 5400 – 0×00 54FF
0×00 5800 – 0×00 5FFF
0×00 6000 – 0×00 60FF
0×00 6400 – 0×00 6FFF
0×00 7000 – 0×00 7FFF
0×00 8000 – 0×00 8FFF
0×00 A000 – 0×00
A400
0×01 0000 – 0×01
FFFF
0×05 0220 – 0×05 02F0
0×08 0000 – 0×08 1FFF
0×80 0000 – 0×FF
FFFF
Purpose
SRAM
Clocking, PLLs, and oscillators
Power management
Interrupt controller
Ports interrupt control
Flash programming interface
Cache controller
I2C controller
Decimator
Fixed timer/counter/PWMs
I/O ports control
External Memory Interface (EMIF)
control registers
Analog Subsystem interface
USB controller
UDB Working Registers
PHUB configuration
EEPROM
CAN
Digital Interconnect configuration
Debug controller
Flash ECC bytes
External Memory Interface
port number and includes ports 0-6, 12 and 15)
The SFRPRTxSEL selects whether the PHUB PRTxDR
register or the SFRPRTxDR controls each pin’s output buffer
within the port. If a SFRPRTxSEL[y] bit is high, the
corresponding SFRPRTxDR[y] bit sets the output state for that
pin. If a SFRPRTxSEL[y] bit is low, the corresponding
PRTxDR[y] bit sets the output state of the pin (where y varies
from 0 to 7).
The SFRPRTxPS is a read only register that contains pin state
values of the port pins.
Document Number: 001-53304 Rev. AA
Page 26 of 137
PSoC® 3: CY8C34 Family Datasheet
6. System Integration
Seven general purpose clock sources
3- to 24-MHz IMO, ±2 percent at 3 MHz
4- to 25-MHz external crystal oscillator (MHzECO)
Clock doubler provides a doubled clock frequency output for
the USB block, see USB Clock Domain on page 30
DSI signal from an external I/O pin or other logic
24- to 50- MHz fractional PLL sourced from IMO, MHzECO,
or DSI
1 kHz, 33 kHz, 100 kHz ILO for Watch Dog Timer (WDT) and
Sleep Timer
32.768-kHz external crystal oscillator (kHzECO) for RTC
IMO has a USB mode that auto locks to the USB bus clock
requiring no external crystal for USB. (USB equipped parts only)
6.1 Clocking System
The clocking system generates, divides, and distributes clocks
throughout the PSoC system. For the majority of systems, no
external crystal is required. The IMO and PLL together can
generate up to a 50 MHz clock, accurate to ±2 percent over
voltage and temperature. Additional internal and external clock
sources allow each design to optimize accuracy, power, and
cost. Any of the clock sources can be used to generate other
clock frequencies in the 16-bit clock dividers and UDBs for
anything the user wants, for example a UART baud rate
generator.
Clock generation and distribution is automatically configured
through the PSoC Creator IDE graphical interface. This is based
on the complete system’s requirements. It greatly speeds the
design process. PSoC Creator allows you to build clocking
systems with minimal input. You can specify desired clock
frequencies and accuracies, and the software locates or builds a
clock that meets the required specifications. This is possible
because of the programmability inherent in PSoC.
Key features of the clocking system include:
Independently sourced clock in all clock dividers
Eight 16-bit clock dividers for the digital system
Four 16-bit clock dividers for the analog system
Dedicated 16-bit divider for the bus clock
Dedicated 4-bit divider for the CPU clock
Automatic clock configuration in PSoC Creator
Table 6-1. Oscillator Summary
Source
IMO
MHzECO
Fmin
3 MHz
4 MHz
Tolerance at Fmin
±2% over voltage and temperature
Crystal dependent
Fmax
24 MHz
25 MHz
Tolerance at Fmax
±4%
Crystal dependent
Startup Time
13 µs max
5 ms typ, max is
crystal dependent
DSI
PLL
Doubler
ILO
0 MHz
24 MHz
48 MHz
1 kHz
Input dependent
Input dependent
Input dependent
–50%, +100%
33 MHz
50 MHz
48 MHz
100 kHz
Input dependent
Input dependent
Input dependent
–55%, +100%
Input dependent
250 µs max
1 µs max
15 ms max in lowest
power mode
kHzECO
32 kHz
Crystal dependent
32 kHz
Crystal dependent
500 ms typ, max is
crystal dependent
Document Number: 001-53304 Rev. AA
Page 27 of 137
PSoC® 3: CY8C34 Family Datasheet
Figure 6-1. Clocking Subsystem
3-24 MHz
IMO
4-25 MHz
ECO
External IO
or DSI
0-33 MHz
32 kHz ECO
1,33,100 kHz
ILO
CPU Clock Divider
4 bit
48 MHz
Doubler for
USB
24-50 MHz
PLL
Master
Mux
Bus
Clock
Bus Clock Divider
16 bit
7
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
7
6.1.1 Internal Oscillators
Figure 6-1 shows that there are two internal oscillators. They can
be routed directly or divided. The direct routes may not have a
50% duty cycle. Divided clocks have a 50% duty cycle.
6.1.1.1 Internal Main Oscillator
In most designs the IMO is the only clock source required, due
to its ±2-percent accuracy. The IMO operates with no external
components and outputs a stable clock. A factory trim for each
frequency range is stored in the device. With the factory trim,
tolerance varies from ±2 percent at 3 MHz, up to ±4 percent at
24 MHz. The IMO, in conjunction with the PLL, allows generation
of other clocks up to the device's maximum frequency (see
Phase-Locked Loop).
CPU
Clock
The PLL block provides a mechanism for generating clock
frequencies based upon a variety of input sources. The PLL
outputs clock frequencies in the range of 24 to 50 MHz. Its input
and feedback dividers supply 4032 discrete ratios to create
almost any desired clock frequency. The accuracy of the PLL
output depends on the accuracy of the PLL input source. The
most common PLL use is to multiply the IMO clock at 3 MHz,
where it is most accurate to generate the other clocks up to the
device’s maximum frequency.
The IMO provides clock outputs at 3, 6, 12, and 24 MHz.
The PLL achieves phase lock within 250 µs (verified by bit
setting). It can be configured to use a clock from the IMO,
MHzECO or DSI (external pin). The PLL clock source can be
used until lock is complete and signaled with a lock bit. The lock
signal can be routed through the DSI to generate an interrupt.
Disable the PLL before entering low-power modes.
6.1.1.2 Clock Doubler
6.1.1.4 Internal Low-Speed Oscillator
The clock doubler outputs a clock at twice the frequency of the
input clock. The doubler works at input frequency of 24 MHz,
providing 48 MHz for the USB. It can be configured to use a clock
from the IMO, MHzECO, or the DSI (external pin).
6.1.1.3 Phase-Locked Loop
The PLL allows low-frequency, high-accuracy clocks to be
multiplied to higher frequencies. This is a trade off between
higher clock frequency and accuracy and, higher power
consumption and increased startup time.
Document Number: 001-53304 Rev. AA
The ILO provides clock frequencies for low-power consumption,
including the watchdog timer, and sleep timer. The ILO
generates up to three different clocks: 1 kHz, 33 kHz, and
100 kHz.
The 1 kHz clock (CLK1K) is typically used for a background
‘heartbeat’ timer. This clock inherently lends itself to low-power
supervisory operations such as the watchdog timer and long
sleep intervals using the central timewheel (CTW).
The central timewheel is a 1 kHz, free running, 13-bit counter
clocked by the ILO. The central timewheel is always enabled
except in hibernate mode and when the CPU is stopped during
Page 28 of 137
PSoC® 3: CY8C34 Family Datasheet
debug on chip mode. It can be used to generate periodic
interrupts for timing purposes or to wake the system from a
low-power mode. Firmware can reset the central timewheel.
Systems that require accurate timing should use the RTC
capability instead of the central timewheel.
The 100-kHz clock (CLK100K) can be used as a low power
master clock. It can also generate time intervals using the fast
timewheel.
The oscillator works in two distinct power modes. This allows
users to trade off power consumption with noise immunity from
neighboring circuits. The GPIO pins connected to the external
crystal and capacitors are fixed.
Figure 6-3. 32kHzECO Block Diagram
32 kHz
Crystal Osc
The fast timewheel is a 5-bit counter, clocked by the 100-kHz
clock. It features programmable settings and automatically
resets when the terminal count is reached. An optional interrupt
can be generated each time the terminal count is reached. This
enables flexible, periodic interrupts of the CPU at a higher rate
than is allowed using the central timewheel.
The 33 kHz clock (CLK33K) comes from a divide-by-3 operation
on CLK100K. This output can be used as a reduced accuracy
version of the 32.768-kHz ECO clock with no need for a crystal.
6.1.2 External Oscillators
Figure 6-1 shows that there are two external oscillators. They
can be routed directly or divided. The direct routes may not have
a 50% duty cycle. Divided clocks have a 50% duty cycle.
6.1.2.1 MHz External Crystal Oscillator
Xi
(Pin P15[3])
XCLK32K
Xo
(Pin P15[2])
External
Components
32 kHz
crystal
Capacitors
The MHzECO provides high frequency, high precision clocking
using an external crystal (see Figure 6-2). It supports a wide
variety of crystal types, in the range of 4 to 25 MHz. When used
in conjunction with the PLL, it can generate other clocks up to the
device's maximum frequency (see “Phase-Locked Loop” section
on page 28). The GPIO pins connecting to the external crystal
and capacitors are fixed. MHzECO accuracy depends on the
crystal chosen.
It is recommended that the external 32.768-kHz watch crystal
have a load capacitance (CL) of 6 pF or 12.5 pF. Check the
crystal manufacturer's datasheet. The two external capacitors,
CL1 and CL2, are typically of the same value, and their total
capacitance, CL1CL2 / (CL1 + CL2), including pin and trace
capacitance, should equal the crystal CL value. For more
information, refer to application note AN54439: PSoC 3 and
PSoC 5 External Oscillators. See also pin capacitance
specifications in the “GPIO” section on page 79.
Figure 6-2. MHzECO Block Diagram
6.1.2.3 Digital System Interconnect
4 – 25 MHz
Crystal Osc
XCLK_MHZ
The DSI provides routing for clocks taken from external clock
oscillators connected to I/O. The oscillators can also be
generated within the device in the digital system and Universal
Digital Blocks.
While the primary DSI clock input provides access to all clocking
resources, up to eight other DSI clocks (internally or externally
generated) may be routed directly to the eight digital clock
dividers. This is only possible if there are multiple precision clock
sources.
Xi
(Pin P15[1])
External
Components
Xo
(Pin P15[0])
4 – 25 MHz
crystal
Capacitors
6.1.2.2 32.768-kHz ECO
The 32.768-kHz External Crystal Oscillator (32kHzECO)
provides precision timing with minimal power consumption using
an external 32.768-kHz watch crystal (see Figure 6-3). The
32kHzECO also connects directly to the sleep timer and provides
the source for the RTC. The RTC uses a 1-second interrupt to
implement the RTC functionality in firmware.
Document Number: 001-53304 Rev. AA
6.1.3 Clock Distribution
All seven clock sources are inputs to the central clock distribution
system. The distribution system is designed to create multiple
high precision clocks. These clocks are customized for the
design’s requirements and eliminate the common problems
found with limited resolution prescalers attached to peripherals.
The clock distribution system generates several types of clock
trees.
The master clock is used to select and supply the fastest clock
in the system for general clock requirements and clock
synchronization of the PSoC device.
Bus Clock 16-bit divider uses the master clock to generate the
bus clock used for data transfers. Bus clock is the source clock
for the CPU clock divider.
Eight fully programmable 16-bit clock dividers generate digital
system clocks for general use in the digital system, as
configured by the design’s requirements. Digital system clocks
Page 29 of 137
PSoC® 3: CY8C34 Family Datasheet
6.1.4 USB Clock Domain
can generate custom clocks derived from any of the seven
clock sources for any purpose. Examples include baud rate
generators, accurate PWM periods, and timer clocks, and
many others. If more than eight digital clock dividers are
required, the Universal Digital Blocks (UDBs) and fixed function
Timer/Counter/PWMs can also generate clocks.
Four 16-bit clock dividers generate clocks for the analog system
components that require clocking, such as ADC and mixers.
The analog clock dividers include skew control to ensure that
critical analog events do not occur simultaneously with digital
switching events. This is done to reduce analog system noise.
Each clock divider consists of an 8-input multiplexer, a 16-bit
clock divider (divide by 2 and higher) that generates ~50 percent
duty cycle clocks, master clock resynchronization logic, and
deglitch logic. The outputs from each digital clock tree can be
routed into the digital system interconnect and then brought back
into the clock system as an input, allowing clock chaining of up
to 32 bits.
The USB clock domain is unique in that it operates largely
asynchronously from the main clock network. The USB logic
contains a synchronous bus interface to the chip, while running
on an asynchronous clock to process USB data. The USB logic
requires a 48 MHz frequency. This frequency can be generated
from different sources, including DSI clock at 48 MHz or doubled
value of 24 MHz from internal oscillator, DSI signal, or crystal
oscillator.
6.2 Power System
The power system consists of separate analog, digital, and I/O
supply pins, labeled VDDA, VDDD, and VDDIOX, respectively. It
also includes two internal 1.8 V regulators that provide the digital
(VCCD) and analog (Vcca) supplies for the internal core logic.
The output pins of the regulators (VCCD and VCCA) and the
VDDIO pins must have capacitors connected as shown in
Figure 6-4. The two VCCD pins must be shorted together, with
as short a trace as possible, and connected to a 1 µF ±10 percent
X5R capacitor. The power system also contains a sleep
regulator, an I2C regulator, and a hibernate regulator.
Figure 6-4. PSoC Power System
VDDD
1 µF
VDDIO2
VDDD
I /O Supply
VSSD
VCCD
VDDIO 2
VDDIO0
0.1 µ F
0.1µF
I/O Supply
VDDIO0
0.1 µF
I2C
Regulator
Sleep
Regulator
Digital
Domain
VDDA
VDDA
VCCA
Analog
Regulator
Digital
Regulators
VSSB
0.1µF
1 µF
VSSA
VDDD
VSSD
I/O Supply
VCCD
VDDIO1
Hibernate
Regulator
0.1 µF
I/O Supply
VDDIO3
Analog
Domain
0.1 µF
0.1µF
VDDIO1
VDDD
VDDIO3
Notes
The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as
shown in Figure 2-8 on page 11.
It is good practice to check the datasheets for your bypass capacitors, specifically the working voltage and the DC bias specifications.
With some capacitors, the actual capacitance can decrease considerably when the DC bias (VDDX or VCCX in Figure 6-4) is a
significant percentage of the rated working voltage.
You can power the device in internally regulated mode, where the voltage applied to the VDDx pins is as high as 5.5 V, and the
internal regulators provide the core voltages. In this mode, do not apply power to the VCCx pins, and do not tie the VDDx pins
to the VCCx pins.
You can also power the device in externally regulated mode, that is, by directly powering the VCCD and VCCA pins. In this
configuration, the VDDD pins should be shorted to the VCCD pins and the VDDA pin should be shorted to the VCCA pin. The
allowed supply range in this configuration is 1.71 V to 1.89 V. After power up in this configuration, the internal regulators are on by
default, and should be disabled to reduce power consumption.
Document Number: 001-53304 Rev. AA
Page 30 of 137
PSoC® 3: CY8C34 Family Datasheet
6.2.1 Power Modes
Active is the main processing mode. Its functionality is
configurable. Each power controllable subsystem is enabled or
disabled by using separate power configuration template
registers. In alternate active mode, fewer subsystems are
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
optimized to provide timed sleep intervals and RTC functionality.
The lowest power mode is hibernate, which retains register and
SRAM state, but no clocks, and allows wakeup only from I/O
pins. Figure 6-5 on page 32 illustrates the allowable transitions
between power modes. Sleep and hibernate modes should not
be entered until all VDDIO supplies are at valid voltage levels.
PSoC 3 devices have four different power modes, as shown in
Table 6-2 and Table 6-3. The power modes allow a design to
easily provide required functionality and processing power while
simultaneously minimizing power consumption and maximizing
battery life in low-power and portable devices.
PSoC 3 power modes, in order of decreasing power
consumption are:
Active
Alternate Active
Sleep
Hibernate
Table 6-2. Power Modes
Power Modes
Description
Entry Condition Wakeup Source
Active Clocks
Regulator
Active
Primary mode of operation, all
peripherals available (programmable)
Wakeup, reset,
manual register
entry
Any interrupt
Any
(programmable)
All regulators available.
Digital and analog
regulators can be disabled if
external regulation used.
Alternate
Active
Similar to Active mode, and is
Manual register
typically configured to have fewer entry
peripherals active to reduce
power. One possible
configuration is to use the UDBs
for processing, with the CPU
turned off
Any interrupt
Any
(programmable)
All regulators available.
Digital and analog
regulators can be disabled if
external regulation used.
Sleep
All subsystems automatically
disabled
Comparator,
ILO/kHzECO
PICU, I2C, RTC,
CTW, LVD
Both digital and analog
regulators buzzed.
Digital and analog
regulators can be disabled if
external regulation used.
Hibernate
All subsystems automatically
Manual register
disabled
entry
Lowest power consuming mode
with all peripherals and internal
regulators disabled, except
hibernate regulator is enabled
Configuration and memory
contents retained
PICU
Only hibernate regulator
active.
Manual register
entry
Table 6-3. Power Modes Wakeup Time and Power Consumption
Sleep
Modes
Wakeup
Time
Current
(typ)
Code
Execution
Digital
Resources
Analog
Resources
Clock Sources
Available
Wakeup Sources
Reset
Sources
Active
–
1.2 mA[12]
Yes
All
All
All
–
All
Alternate
Active
–
–
User
defined
All
All
All
–
All
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