PSoC® 4: PSoC 4000S Datasheet
®
Programmable System-on-Chip (PSoC )
Functional Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
ARM® Cortex®-M0+ CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing.
The PSoC 4000S product family is a member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard
communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, programmable
general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC 4000S products will
be upward compatible with members of the PSoC 4 platform for new applications and design needs.
Features
32-bit MCU Subsystem
LCD Drive Capability
■
48-MHz ARM Cortex-M0+ CPU
■
Up to 32 KB of flash with Read Accelerator
■
Up to 4 KB of SRAM
■
Timing and Pulse-Width Modulation
Programmable Analog
■
Single-slope 10-bit ADC function provided by Capacitance
sensing block
■
Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
■
Two low-power comparators that operate in Deep Sleep
low-power mode
■
Five 16-bit timer/counter/pulse-width modulator (TCPWM)
blocks
■
Center-aligned, Edge, and Pseudo-random modes
■
Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
Up to 36 Programmable GPIO Pins
■
48-pin TQFP, 40-pin QFN, 32-pin QFN, 24-pin QFN, 32-pin
TQFP, and 25-ball WLCSP packages
■
Any GPIO pin can be CapSense, analog, or digital
■
Drive modes, strengths, and slew rates are programmable
Programmable Digital
Programmable logic blocks allowing Boolean operations to be
performed on port inputs and outputs
Low-Power 1.71-V to 5.5-V Operation
■
LCD segment drive capability on GPIOs
Deep Sleep mode with operational analog and 2.5 A digital
system current
PSoC Creator Design Environment
■
Integrated Development Environment (IDE) provides
schematic design entry and build (with analog and digital
automatic routing)
Applications Programming Interface (API) component for all
fixed-function and programmable peripherals
Capacitive Sensing
■
Cypress CapSense Sigma-Delta (CSD) provides best-in-class
signal-to-noise ratio (SNR) (>5:1) and water tolerance
■
■
Cypress-supplied software component makes capacitive
sensing design easy
Industry-Standard Tool Compatibility
■
Automatic hardware tuning (SmartSense™)
■
After schematic entry, development can be done with
ARM-based industry-standard development tools
Serial Communication
■
Two independent run-time reconfigurable Serial
Communication Blocks (SCBs) with re-configurable I2C, SPI,
or UART functionality
Cypress Semiconductor Corporation
Document Number: 002-00123 Rev. *K
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 17, 2017
PSoC® 4: PSoC 4000S Datasheet
Contents
Logic Block Diagram ........................................................ 3
Functional Overview ........................................................ 4
CPU and Memory Subsystem ..................................... 4
System Resources ...................................................... 4
Analog Blocks .............................................................. 5
Programmable Digital Blocks ...................................... 5
Fixed Function Digital .................................................. 5
GPIO ........................................................................... 6
Special Function Peripherals ....................................... 6
Pinouts .............................................................................. 7
Alternate Pin Functions ............................................... 8
Power ............................................................................... 10
Mode 1: 1.8 V to 5.5 V External Supply .................... 10
Mode 2: 1.8 V ±5% External Supply .......................... 10
Development Support .................................................... 11
Documentation .......................................................... 11
Online ........................................................................ 11
Tools .......................................................................... 11
Electrical Specifications ................................................ 12
Absolute Maximum Ratings ....................................... 12
Document Number: 002-00123 Rev. *K
Device Level Specifications ....................................... 13
Analog Peripherals .................................................... 16
Digital Peripherals ..................................................... 20
Memory ..................................................................... 23
System Resources .................................................... 23
Ordering Information ...................................................... 26
Packaging ........................................................................ 28
Package Diagrams .................................................... 29
Acronyms ........................................................................ 33
Document Conventions ................................................. 35
Units of Measure ....................................................... 35
Document History Page ................................................. 36
Sales, Solutions, and Legal Information ...................... 37
Worldwide Sales and Design Support ....................... 37
Products .................................................................... 37
PSoC®Solutions ....................................................... 37
Cypress Developer Community ................................. 37
Technical Support ..................................................... 37
Page 2 of 37
PSoC® 4: PSoC 4000S Datasheet
Logic Block Diagram
Figure 1. Block Diagram
CPU Subsystem
SWD/ TC
32- bit
48 MHz
System Resources
Lite
SRAM Controller
ROM Controller
WCO
2x LP Comparator
Peripheral Interconnect (MMIO)
PCLK
2x SCB-I2C/SPI/UART
Test
TestMode Entry
Digital DFT
Analog DFT
ROM
8 KB
Peripherals
5x TCPWM
Reset
Reset Control
XRES
Read Accelerator
SRAM
4 KB
System Interconnect ( Single Layer AHB)
IOSS GPIO (5x ports)
Clock
Clock Control
WDT
ILO
IMO
FLASH
32 KB
FAST MUL
NVIC, IRQMUX
AHB- Lite
Power
Sleep Control
WIC
POR
REF
PWRSYS
SPCIF
Cortex
M0+
CapSense
PSoC 4000S
Architecture
High Speed I/ O Matrix & 2 x Programmable I/O
Power Modes
Active/ Sleep
DeepSleep
36x GPIOs, LCD
I/O Subsystem
PSoC 4000S devices include extensive support for
programming, testing, debugging, and tracing both hardware
and firmware.
The ARM Serial-Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE provides fully integrated programming
and debug support for the PSoC 4000S devices. The SWD
interface is fully compatible with industry-standard third-party
tools. The PSoC 4000S family provides a level of security not
possible with multi-chip application solutions or with
microcontrollers. It has the following advantages:
■
Allows disabling of debug features
■
Robust flash protection
■
Allows customer-proprietary functionality to be implemented in
on-chip programmable blocks
Document Number: 002-00123 Rev. *K
The debug circuits are enabled by default and can be disabled
in firmware. If they are not enabled, the only way to re-enable
them is to erase the entire device, clear flash protection, and
reprogram the device with new firmware that enables debugging.
Thus firmware control of debugging cannot be over-ridden
without erasing the firmware thus providing security.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. All programming, debug, and test interfaces are
disabled when maximum device security is enabled. Therefore,
PSoC 4000S, with device security enabled, may not be returned
for failure analysis. This is a trade-off the PSoC 4000S allows the
customer to make.
Page 3 of 37
PSoC® 4: PSoC 4000S Datasheet
Functional Overview
CPU and Memory Subsystem
CPU
The Cortex-M0+ CPU in the PSoC 4000S is part of the 32-bit
MCU subsystem, which is optimized for low-power operation
with extensive clock gating. Most instructions are 16 bits in length
and the CPU executes a subset of the Thumb-2 instruction set.
It includes a nested vectored interrupt controller (NVIC) block
with eight interrupt inputs and also includes a Wakeup Interrupt
Controller (WIC). The WIC can wake the processor from Deep
Sleep mode, allowing power to be switched off to the main
processor when the chip is in Deep Sleep mode.
The CPU also includes a debug interface, the serial wire debug
(SWD) interface, which is a two-wire form of JTAG. The debug
configuration used for PSoC 4000S has four breakpoint
(address) comparators and two watchpoint (data) comparators.
Flash
Clock System
The PSoC 4000S clock system is responsible for providing
clocks to all subsystems that require clocks and for switching
between different clock sources without glitching. In addition, the
clock system ensures that there are no metastable conditions.
The clock system for the PSoC 4000S consists of the internal
main oscillator (IMO), internal low-frequency oscillator (ILO), a
32 kHz Watch Crystal Oscillator (WCO) and provision for an
external clock. Clock dividers are provided to generate clocks for
peripherals on a fine-grained basis. Fractional dividers are also
provided to enable clocking of higher data rates for UARTs.
The HFCLK signal can be divided down to generate
synchronous clocks for the analog and digital peripherals. There
are eight clock dividers for the PSoC 4000S, two of those are
fractional dividers. The 16-bit capability allows flexible generation of fine-grained frequency values, and is fully supported in
PSoC Creator.
Figure 2. PSoC 4000S MCU Clocking Architecture
The PSoC 4000S device has a flash module with a flash
accelerator, tightly coupled to the CPU to improve average
access times from the flash block. The low-power flash block is
designed to deliver two wait-state (WS) access time at 48 MHz.
The flash accelerator delivers 85% of single-cycle SRAM access
performance on average.
IMO
Divide By
2,4,8
HFCLK
External Clock
ILO
LFCLK
SRAM
Four KB of SRAM are provided with zero wait-state access at
48 MHz.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
System Resources
HFCLK
SYSCLK
Prescaler
Integer
Dividers
Fractional
Dividers
6X 16-bit
2X 16.5-bit
Power System
The power system is described in detail in the section Power on
page 10. It provides assurance that voltage levels are as
required for each respective mode and either delays mode entry
(for example, on power-on reset (POR)) until voltage levels are
as required for proper functionality, or generates resets (for
example, on brown-out detection). The PSoC 4000S operates
with a single external supply over the range of either 1.8 V ±5%
(externally regulated) or 1.8 to 5.5 V (internally regulated) and
has three different power modes, transitions between which are
managed by the power system. The PSoC 4000S provides
Active, Sleep, and Deep Sleep low-power modes.
All subsystems are operational in Active mode. The CPU
subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep
mode, while all peripherals and interrupts are active with
instantaneous wake-up on a wake-up event. In Deep Sleep
mode, the high-speed clock and associated circuitry is switched
off; wake-up from this mode takes 35 µs. The opamps can
remain operational in Deep Sleep mode.
Document Number: 002-00123 Rev. *K
IMO Clock Source
The IMO is the primary source of internal clocking in the
PSoC 4000S. It is trimmed during testing to achieve the specified
accuracy.The IMO default frequency is 24 MHz and it can be
adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO tolerance
with Cypress-provided calibration settings is ±2%.
ILO Clock Source
The ILO is a very low power, nominally 40-kHz oscillator, which
is primarily used to generate clocks for the watchdog timer
(WDT) and peripheral operation in Deep Sleep mode. ILO-driven
counters can be calibrated to the IMO to improve accuracy.
Cypress provides a software component, which does the
calibration.
Watch Crystal Oscillator (WCO)
The PSoC 4000S clock subsystem also implements a
low-frequency (32-kHz watch crystal) oscillator that can be used
for precision timing applications.
Page 4 of 37
PSoC® 4: PSoC 4000S Datasheet
Watchdog Timer
A watchdog timer is implemented in the clock block running from
the ILO; this allows watchdog operation during Deep Sleep and
generates a watchdog reset if not serviced before the set timeout
occurs. The watchdog reset is recorded in a Reset Cause
register, which is firmware readable.
Reset
The PSoC 4000S can be reset from a variety of sources
including a software reset. Reset events are asynchronous and
guarantee reversion to a known state. The reset cause is
recorded in a register, which is sticky through reset and allows
software to determine the cause of the reset. An XRES pin is
reserved for external reset by asserting it active low. The XRES
pin has an internal pull-up resistor that is always enabled.
Voltage Reference
The PSoC 4000S reference system generates all internally
required references. A 1.2-V voltage reference is provided for the
comparator. The IDACs are based on a ±5% reference.
Analog Blocks
Low-power Comparators (LPC)
The PSoC 4000S has a pair of low-power comparators, which
can also operate in Deep Sleep modes. This allows the analog
system blocks to be disabled while retaining the ability to monitor
external voltage levels during low-power modes. The
comparator outputs are normally synchronized to avoid
metastability unless operating in an asynchronous power mode
where the system wake-up circuit is activated by a comparator
switch event. The LPC outputs can be routed to pins.
Current DACs
The PSoC 4000S has two IDACs, which can drive any of the pins
on the chip. These IDACs have programmable current ranges.
Analog Multiplexed Buses
The PSoC 4000S has two concentric independent buses that go
around the periphery of the chip. These buses (called amux
buses) are connected to firmware-programmable analog
switches that allow the chip's internal resources (IDACs,
comparator) to connect to any pin on the I/O Ports.
Programmable Digital Blocks
The programmable I/O (Smart I/O) block is a fabric of switches
and LUTs that allows Boolean functions to be performed in
signals being routed to the pins of a GPIO port. The Smart I/O
can perform logical operations on input pins to the chip and on
signals going out as outputs.
Fixed Function Digital
Timer/Counter/PWM (TCPWM) Block
The TCPWM block consists of a 16-bit counter with
user-programmable period length. There is a capture register to
record the count value at the time of an event (which may be an
I/O event), a period register that is used to either stop or
auto-reload the counter when its count is equal to the period
register, and compare registers to generate compare value
signals that are used as PWM duty cycle outputs. The block also
provides true and complementary outputs with programmable
offset between them to allow use as dead-band programmable
complementary PWM outputs. It also has a Kill input to force
outputs to a predetermined state; for example, this is used in
motor drive systems when an over-current state is indicated and
the PWM driving the FETs needs to be shut off immediately with
no time for software intervention. There are five TCPWM blocks
in the PSoC 4000S.
Serial Communication Block (SCB)
The PSoC 4000S has two serial communication blocks, which
can be programmed to have SPI, I2C, or UART functionality.
I2C Mode: The hardware I2C block implements a full
multi-master and slave interface (it is capable of multi-master
arbitration). This block is capable of operating at speeds of up to
400 kbps (Fast Mode) and has flexible buffering options to
reduce interrupt overhead and latency for the CPU. It also
supports EZI2C that creates a mailbox address range in the
memory of the PSoC 4000S and effectively reduces I2C communication to reading from and writing to an array in memory. In
addition, the block supports an 8-deep FIFO for receive and
transmit which, by increasing the time given for the CPU to read
data, greatly reduces the need for clock stretching caused by the
CPU not having read data on time.
The I2C peripheral is compatible with the I2C Standard-mode and
Fast-mode devices as defined in the NXP I2C-bus specification
and user manual (UM10204). The I2C bus I/O is implemented
with GPIO in open-drain modes.
The PSoC 4000S is not completely compliant with the I2C spec
in the following respect:
■
GPIO cells are not overvoltage tolerant and, therefore, cannot
be hot-swapped or powered up independently of the rest of the
I2C system.
UART Mode: This is a full-feature UART operating at up to
1 Mbps. It supports automotive single-wire interface (LIN),
infrared interface (IrDA), and SmartCard (ISO7816) protocols, all
of which are minor variants of the basic UART protocol. In
addition, it supports the 9-bit multiprocessor mode that allows
addressing of peripherals connected over common RX and TX
lines. Common UART functions such as parity error, break
detect, and frame error are supported. An 8-deep FIFO allows
much greater CPU service latencies to be tolerated.
SPI Mode: The SPI mode supports full Motorola SPI, TI SSP
(adds a start pulse used to synchronize SPI Codecs), and
National Microwire (half-duplex form of SPI). The SPI block can
use the FIFO.
Document Number: 002-00123 Rev. *K
Page 5 of 37
PSoC® 4: PSoC 4000S Datasheet
GPIO
The PSoC 4000S has up to 36 GPIOs. The GPIO block implements the following:
■
Eight drive modes:
❐ Analog input mode (input and output buffers disabled)
❐ Input only
❐ Weak pull-up with strong pull-down
❐ Strong pull-up with weak pull-down
❐ Open drain with strong pull-down
❐ Open drain with strong pull-up
❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
Input threshold select (CMOS or LVTTL).
Shield voltage can be driven on another analog multiplex bus to
provide water-tolerance capability. Water tolerance is provided
by driving the shield electrode in phase with the sense electrode
to keep the shield capacitance from attenuating the sensed
input. Proximity sensing can also be implemented.
■
Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes
The CapSense block has two IDACs, which can be used for
general purposes if CapSense is not being used (both IDACs are
available in that case) or if CapSense is used without water
tolerance (one IDAC is available).
The CapSense block also provides a 10-bit Slope ADC function,
which can be used in conjunction with the CapSense function.
The CapSense block is an advanced, low-noise, programmable
block with programmable voltage references and current source
ranges for improved sensitivity and flexibility. It can also use an
external reference voltage. It has a full-wave CSD mode that
alternates sensing to VDDA and Ground to null out power-supply
related noise.
■
Selectable slew rates for dV/dt related noise control to improve
EMI
LCD Segment Drive
■
The pins are organized in logical entities called ports, which are
8-bit in width (less for Ports 2 and 3). During power-on and reset,
the blocks are forced to the disable state so as not to crowbar
any inputs and/or cause excess turn-on current. A multiplexing
network known as a high-speed I/O matrix is used to multiplex
between various signals that may connect to an I/O pin.
Data output and pin state registers store, respectively, the values
to be driven on the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled and each
I/O port has an interrupt request (IRQ) and interrupt service
routine (ISR) vector associated with it (5 for PSoC 4000S).
Special Function Peripherals
CapSense
CapSense is supported in the PSoC 4000S through a CapSense
Sigma-Delta (CSD) block that can be connected to any pins
through an analog multiplex bus via analog switches. CapSense
function can thus be provided on any available pin or group of
pins in a system under software control. A PSoC Creator
component is provided for the CapSense block to make it easy
for the user.
Document Number: 002-00123 Rev. *K
The PSoC 4000S has an LCD controller, which can drive up to
8 commons and up to 28 segments. It uses full digital methods
to drive the LCD segments requiring no generation of internal
LCD voltages. The two methods used are referred to as Digital
Correlation and PWM. Digital Correlation pertains to modulating
the frequency and drive levels of the common and segment
signals to generate the highest RMS voltage across a segment
to light it up or to keep the RMS signal to zero. This method is
good for STN displays but may result in reduced contrast with TN
(cheaper) displays. PWM pertains to driving the panel with PWM
signals to effectively use the capacitance of the panel to provide
the integration of the modulated pulse-width to generate the
desired LCD voltage. This method results in higher power
consumption but can result in better results when driving TN
displays. LCD operation is supported during Deep Sleep
refreshing a small display buffer (4 bits; 1 32-bit register per port).
Page 6 of 37
PSoC® 4: PSoC 4000S Datasheet
Pinouts
The following table provides the pin list for PSoC 4000S for the 48-pin TQFP, 40-pin QFN, 32-pin QFN, 24-pin QFN, 32-pin TQFP,
and 25-ball CSP packages. All port pins support GPIO. Pin 11 is a No-Connect in the 48-TQFP.
Table 1. PSoC 4000S Pin List
48-pin TQFP
32-pin QFN
24-pin QFN
25-ball CSP
40-pin QFN
32-pin TQFP
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
28
P0.0
17
P0.0
13
P0.0
D1
P0.0
22
P0.0
17
P0.0
29
P0.1
18
P0.1
14
P0.1
C3
P0.1
23
P0.1
18
P0.1
30
P0.2
19
P0.2
24
P0.2
19
P0.2
31
P0.3
20
P0.3
25
P0.3
20
P0.3
32
P0.4
21
P0.4
15
P0.4
C2
P0.4
26
P0.4
21
P0.4
33
P0.5
22
P0.5
16
P0.5
C1
P0.5
27
P0.5
22
P0.5
34
P0.6
23
P0.6
17
P0.6
B1
P0.6
28
P0.6
23
P0.6
35
P0.7
B2
P0.7
29
P0.7
36
XRES
24
XRES
18
XRES
B3
XRES
30
XRES
24
XRES
37
VCCD
25
VCCD
19
VCCD
A1
VCCD
31
VCCD
25
VCCD
38
VSSD
26
VSSD
20
VSSD
A2
VSS
26
VSSD
39
VDDD
27
VDD
21
VDD
A3
VDD
32
VDDD
27
VDD
40
VDDA
27
VDD
21
VDD
A3
VDD
33
VDDA
27
VDD
41
VSSA
28
VSSA
22
VSSA
A2
VSS
34
VSSA
28
VSSA
42
P1.0
29
P1.0
35
P1.0
29
P1.0
43
P1.1
30
P1.1
36
P1.1
30
P1.1
44
P1.2
31
P1.2
23
P1.2
A4
P1.2
37
P1.2
31
P1.2
45
P1.3
32
P1.3
24
P1.3
B4
P1.3
38
P1.3
32
P1.3
46
P1.4
39
P1.4
47
P1.5
48
P1.6
1
P1.7
1
P1.7
1
P1.7
A5
P1.7
40
P1.7
1
P1.7
2
P2.0
2
P2.0
2
P2.0
B5
P2.0
1
P2.0
2
P2.0
3
P2.1
3
P2.1
3
P2.1
C5
P2.1
2
P2.1
3
P2.1
4
P2.2
4
P2.2
3
P2.2
4
P2.2
5
P2.3
5
P2.3
4
P2.3
5
P2.3
6
P2.4
5
P2.4
7
P2.5
6
P2.5
6
P2.5
6
P2.5
8
P2.6
7
P2.6
4
P2.6
D5
P2.6
7
P2.6
7
P2.6
9
P2.7
8
P2.7
5
P2.7
C4
P2.7
8
P2.7
8
P2.7
10
VSSD
A2
VSS
9
VSSD
12
P3.0
9
P3.0
E5
P3.0
10
P3.0
9
P3.0
13
P3.1
10
P3.1
14
P3.2
11
16
P3.3
12
6
P3.0
D4
P3.1
11
P3.1
10
P3.1
P3.2
7
P3.2
E4
P3.2
12
P3.2
11
P3.2
P3.3
8
P3.3
D3
P3.3
13
P3.3
12
P3.3
Document Number: 002-00123 Rev. *K
Page 7 of 37
PSoC® 4: PSoC 4000S Datasheet
Table 1. PSoC 4000S Pin List (continued)
48-pin TQFP
Pin
Name
17
32-pin QFN
Pin
Name
24-pin QFN
Pin
Name
25-ball CSP
Pin
Name
40-pin QFN
Pin
Name
P3.4
14
P3.4
18
P3.5
15
P3.5
19
P3.6
16
P3.6
20
P3.7
17
P3.7
21
VDDD
32-pin TQFP
Pin
Name
22
P4.0
13
P4.0
9
P4.0
E3
P4.0
18
P4.0
13
P4.0
23
P4.1
14
P4.1
10
P4.1
D2
P4.1
19
P4.1
14
P4.1
24
P4.2
15
P4.2
11
P4.2
E2
P4.2
20
P4.2
15
P4.2
25
P4.3
16
P4.3
12
P4.3
E1
P4.3
21
P4.3
16
P4.3
Descriptions of the Pin functions are as follows:
VDDD: Power supply for the digital section.
VDDA: Power supply for the analog section.
VSSD, VSSA: Ground pins for the digital and analog sections respectively.
VCCD: Regulated digital supply (1.8 V ±5%)
VDD: Power supply to all sections of the chip
VSS: Ground for all sections of the chip
Alternate Pin Functions
Each port pin can be assigned to one of multiple functions; it can, for instance, be an analog I/O, a digital peripheral function, an LCD
pin, or a CapSense pin. The pin assignments are shown in the following table.
Port/
Pin
Analog
P0.0
lpcomp.in_p[0]
tcpwm.tr_in[0]
P0.1
lpcomp.in_n[0]
tcpwm.tr_in[1]
P0.2
lpcomp.in_p[1]
P0.3
lpcomp.in_n[1]
Smart I/O
Alternate Function 1 Alternate Function 2 Alternate Function 3
Deep Sleep 1
Deep Sleep 2
scb[0].spi_select1:0
scb[0].spi_select2:0
scb[0].spi_select3:0
P0.4
wco.wco_in
scb[1].uart_rx:0
scb[1].i2c_scl:0
scb[1].spi_mosi:1
P0.5
wco.wco_out
scb[1].uart_tx:0
scb[1].i2c_sda:0
scb[1].spi_miso:1
P0.6
srss.ext_clk
P0.7
scb[1].uart_cts:0
scb[1].spi_clk:1
scb[1].uart_rts:0
scb[1].spi_select0:1
P1.0
tcpwm.line[2]:1
scb[0].uart_rx:1
scb[0].i2c_scl:0
scb[0].spi_mosi:1
P1.1
tcpwm.line_compl[2]:1
scb[0].uart_tx:1
scb[0].i2c_sda:0
scb[0].spi_miso:1
P1.2
tcpwm.line[3]:1
scb[0].uart_cts:1
tcpwm.tr_in[2]
P1.3
tcpwm.line_compl[3]:1
scb[0].uart_rts:1
tcpwm.tr_in[3]
scb[0].spi_clk:1
scb[0].spi_select0:1
P1.4
scb[0].spi_select1:1
P1.5
scb[0].spi_select2:1
Document Number: 002-00123 Rev. *K
Page 8 of 37
PSoC® 4: PSoC 4000S Datasheet
Port/
Pin
Analog
Smart I/O
Alternate Function 1 Alternate Function 2 Alternate Function 3
Deep Sleep 1
P1.6
Deep Sleep 2
scb[0].spi_select3:1
P1.7
P2.0
prgio[0].io[0]
tcpwm.line[4]:0
csd.comp
tcpwm.tr_in[4]
scb[1].i2c_scl:1
scb[1].spi_mosi:2
P2.1
prgio[0].io[1]
tcpwm.line_compl[4]:0
P2.2
prgio[0].io[2]
tcpwm.tr_in[5]
scb[1].i2c_sda:1
scb[1].spi_miso:2
scb[1].spi_clk:2
P2.3
prgio[0].io[3]
scb[1].spi_select0:2
P2.4
prgio[0].io[4]
tcpwm.line[0]:1
scb[1].spi_select1:1
P2.5
prgio[0].io[5]
tcpwm.line_compl[0]:1
scb[1].spi_select2:1
P2.6
prgio[0].io[6]
tcpwm.line[1]:1
P2.7
prgio[0].io[7]
tcpwm.line_compl[1]:1
P3.0
prgio[1].io[0]
tcpwm.line[0]:0
scb[1].uart_rx:1
scb[1].i2c_scl:2
scb[1].spi_mosi:0
P3.1
prgio[1].io[1]
tcpwm.line_compl[0]:0
scb[1].uart_tx:1
scb[1].i2c_sda:2
scb[1].spi_miso:0
P3.2
prgio[1].io[2]
tcpwm.line[1]:0
scb[1].uart_cts:1
cpuss.swd_data
scb[1].spi_clk:0
P3.3
prgio[1].io[3]
tcpwm.line_compl[1]:0
scb[1].uart_rts:1
cpuss.swd_clk
scb[1].spi_select0:0
P3.4
prgio[1].io[4]
tcpwm.line[2]:0
P3.5
prgio[1].io[5]
tcpwm.line_compl[2]:0
tcpwm.tr_in[7]
scb[1].spi_select2:0
P3.6
prgio[1].io[6]
tcpwm.line[3]:0
tcpwm.tr_in[8]
scb[1].spi_select3:0
P3.7
prgio[1].io[7]
tcpwm.line_compl[3]:0
tcpwm.tr_in[9]
scb[1].spi_select3:1
lpcomp.comp[0]:1
tcpwm.tr_in[6]
scb[1].spi_select1:0
lpcomp.comp[1]:1
P4.0
csd.vref_ext
scb[0].uart_rx:0
tcpwm.tr_in[10]
scb[0].i2c_scl:1
scb[0].spi_mosi:0
P4.1
csd.cshieldpads
scb[0].uart_tx:0
tcpwm.tr_in[11]
scb[0].i2c_sda:1
scb[0].spi_miso:0
P4.2
csd.cmodpad
scb[0].uart_cts:0
lpcomp.comp[0]:0
scb[0].spi_clk:0
P4.3
csd.csh_tank
scb[0].uart_rts:0
lpcomp.comp[1]:0
scb[0].spi_select0:0
Document Number: 002-00123 Rev. *K
Page 9 of 37
PSoC® 4: PSoC 4000S Datasheet
Power
Mode 1: 1.8 V to 5.5 V External Supply
The following power system diagram shows the set of power
supply pins as implemented for the PSoC 4000S. The system
has one regulator in Active mode for the digital circuitry. There is
no analog regulator; the analog circuits run directly from the VDD
input.
Figure 3. Power Supply Connections
VDDA
VDDD
VDDA
VSSA
Mode 2: 1.8 V ±5% External Supply
VDDD
Analog
Domain
In this mode, the PSoC 4000S is powered by an external power
supply that must be within the range of 1.71 to 1.89 V; note that
this range needs to include the power supply ripple too. In this
mode, the VDD and VCCD pins are shorted together and
bypassed. The internal regulator can be disabled in the firmware.
Digital
Domain
VSSD
1.8 Volt
Regulator
In this mode, the PSoC 4000S is powered by an external power
supply that can be anywhere in the range of 1.8 to 5.5 V. This
range is also designed for battery-powered operation. For
example, the chip can be powered from a battery system that
starts at 3.5 V and works down to 1.8 V. In this mode, the internal
regulator of the PSoC 4000S supplies the internal logic and its
output is connected to the VCCD pin. The VCCD pin must be
bypassed to ground via an external capacitor (0.1 µF; X5R
ceramic or better) and must not be connected to anything else.
Bypass capacitors must be used from VDDD to ground. The
typical practice for systems in this frequency range is to use a
capacitor in the 1-µF range, in parallel with a smaller capacitor
(0.1 µF, for example). Note that these are simply rules of thumb
and that, for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated to
design and obtain optimal bypassing.
VCCD
An example of a bypass scheme is shown in the following
diagram.
There are two distinct modes of operation. In Mode 1, the supply
voltage range is 1.8 V to 5.5 V (unregulated externally; internal
regulator operational). In Mode 2, the supply range is1.8 V ±5%
(externally regulated; 1.71 to 1.89, internal regulator bypassed).
Figure 4. External Supply Range from 1.8 V to 5.5 V with Internal Regulator Active
Power supply bypass connections example
1.8V to 5.5V
V DD
PSoC 4000S
1.8V to 5.5V
VDDA
F
0.1F
0.1F
V CCD
0.1F
V SS
Document Number: 002-00123 Rev. *K
Page 10 of 37
PSoC® 4: PSoC 4000S Datasheet
Development Support
The PSoC 4000S has a rich set of documentation, development
tools, and online resources to assist you during your
development process. Visit www.cypress.com/go/psoc4 to find
out more.
Documentation
A suite of documentation supports the PSoC 4000S to ensure
that you can find answers to your questions quickly. This section
contains a list of some of the key documents.
Software User Guide: A step-by-step guide for using
PSoC Creator. The software user guide shows you how the
PSoC Creator build process works in detail, how to use source
control with PSoC Creator, and much more.
Component Datasheets: The flexibility of PSoC allows the
creation of new peripherals (components) long after the device
has gone into production. Component data sheets provide all of
the information needed to select and use a particular component,
including a functional description, API documentation, example
code, and AC/DC specifications.
Technical Reference Manual: The Technical Reference Manual
(TRM) contains all the technical detail you need to use a PSoC
device, including a complete description of all PSoC registers.
The TRM is available in the Documentation section at
www.cypress.com/psoc4.
Online
In addition to print documentation, the Cypress PSoC forums
connect you with fellow PSoC users and experts in PSoC from
around the world, 24 hours a day, 7 days a week.
Tools
With industry standard cores, programming, and debugging
interfaces, the PSoC 4000S is part of a development tool
ecosystem. Visit us at www.cypress.com/go/psoccreator for the
latest information on the revolutionary, easy to use PSoC Creator
IDE, supported third party compilers, programmers, debuggers,
and development kits.
Application Notes: PSoC application notes discuss a particular
application of PSoC in depth; examples include brushless DC
motor control and on-chip filtering. Application notes often
include example projects in addition to the application note
document.
Document Number: 002-00123 Rev. *K
Page 11 of 37
PSoC® 4: PSoC 4000S Datasheet
Electrical Specifications
Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings[1]
Spec ID#
SID1
Parameter
Description
Min
Typ
Max
VDDD_ABS
Digital supply relative to VSS
–0.5
–
6
SID2
VCCD_ABS
Direct digital core voltage input relative
to VSS
–0.5
–
1.95
SID3
VGPIO_ABS
GPIO voltage
–0.5
–
VDD+0.5
SID4
IGPIO_ABS
Maximum current per GPIO
–25
–
25
SID5
IGPIO_injection
GPIO injection current, Max for VIH >
VDDD, and Min for VIL < VSS
–0.5
–
0.5
BID44
ESD_HBM
Electrostatic discharge human body
model
2200
–
–
Units
Details/
Conditions
–
V
–
–
–
mA
Current injected
per pin
–
V
BID45
ESD_CDM
Electrostatic discharge charged device
model
500
–
–
BID46
LU
Pin current for latch-up
–140
–
140
–
mA
–
Note
1. Usage above the absolute maximum conditions listed in Table 2 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended
periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 002-00123 Rev. *K
Page 12 of 37
PSoC® 4: PSoC 4000S Datasheet
Device Level Specifications
All specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
Table 3. DC Specifications
Typical values measured at VDD = 3.3 V and 25 °C.
Spec ID#
Parameter
Description
Min
Typ
Max
SID53
VDD
Power supply input voltage
1.8
–
5.5
SID255
VDD
Power supply input voltage (VCCD =
VDD= VDDA)
1.71
–
1.89
SID54
VCCD
Output voltage (for core logic)
–
1.8
–
SID55
CEFC
External regulator voltage bypass
–
0.1
–
SID56
CEXC
Power supply bypass capacitor
–
1
–
Units
Details/
Conditions
Internally
regulated supply
V
Internally
unregulated
supply
–
µF
X5R ceramic or
better
X5R ceramic or
better
Active Mode, VDD = 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25 °C.
SID10
IDD5
Execute from flash; CPU at 6 MHz
–
1.2
2.0
SID16
IDD8
Execute from flash; CPU at 24 MHz
–
2.4
4.0
SID19
IDD11
Execute from flash; CPU at 48 MHz
–
4.6
5.9
–
–
mA
–
Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on)
SID22
SID25
IDD17
I2C wakeup WDT, and Comparators on
–
1.1
1.6
IDD20
I2C wakeup,
–
1.4
1.9
WDT, and Comparators on
mA
6 MHz
12 MHz
Sleep Mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed)
SID28
SID28A
IDD23
I2C wakeup, WDT, and Comparators on
–
0.7
0.9
mA
6 MHz
IDD23A
I2C wakeup,
–
0.9
1.1
mA
12 MHz
–
2.5
60
µA
–
–
2.5
60
µA
–
WDT, and Comparators on
Deep Sleep Mode, VDD = 1.8 V to 3.6 V (Regulator on)
SID31
IDD26
I2C wakeup and WDT on
Deep Sleep Mode, VDD = 3.6 V to 5.5 V (Regulator on)
SID34
IDD29
I2C wakeup and WDT on
Deep Sleep Mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed)
SID37
IDD32
I2C wakeup and WDT on
–
2.5
60
µA
–
IDD_XR
Supply current while XRES asserted
–
2
5
mA
–
Min
Typ
Max
Units
Details/
Conditions
DC
–
48
MHz
XRES Current
SID307
Table 4. AC Specifications
Spec ID#
SID48
Parameter
Description
FCPU
CPU frequency
SID49
TSLEEP
Wakeup from Sleep mode
–
0
–
SID50[3]
TDEEPSLEEP
Wakeup from Deep Sleep mode
–
35
–
[3]
1.71 VDD 5.5
µs
Note
2. Guaranteed by characterization.
Document Number: 002-00123 Rev. *K
Page 13 of 37
PSoC® 4: PSoC 4000S Datasheet
GPIO
Table 5. GPIO DC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID57
VIH[3]
Input voltage high threshold
0.7 VDDD
–
–
CMOS Input
SID58
VIL
Input voltage low threshold
–
–
CMOS Input
SID241
VIH[3]
LVTTL input, VDDD < 2.7 V
0.7 VDDD
0.3
VDDD
–
–
–
SID242
VIL
LVTTL input, VDDD < 2.7 V
–
–
0.3
VDDD
–
SID243
VIH[3]
LVTTL input, VDDD 2.7 V
2.0
–
–
SID244
VIL
LVTTL input, VDDD 2.7 V
–
–
0.8
SID59
VOH
Output voltage high level
VDDD –0.6
–
–
IOH = 4 mA at 3 V VDDD
SID60
VOH
Output voltage high level
VDDD –0.5
–
–
IOH = 1 mA at 3 V VDDD
SID61
VOL
Output voltage low level
–
–
0.6
IOL = 4 mA at 1.8 V
VDDD
SID62
VOL
Output voltage low level
–
–
0.6
IOL = 10 mA at 3 V VDDD
SID62A
VOL
Output voltage low level
–
–
0.4
IOL = 3 mA at 3 V VDDD
SID63
RPULLUP
Pull-up resistor
3.5
5.6
8.5
SID64
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
SID65
IIL
Input leakage current (absolute
value)
–
–
2
nA
SID66
CIN
Input capacitance
–
–
7
pF
–
mV
VDD < 4.5 V
[4]
V
kΩ
–
–
–
–
25 °C, VDDD = 3.0 V
VDDD 2.7 V
SID67
VHYSTTL
Input hysteresis LVTTL
25
40
–
SID68[4]
VHYSCMOS
Input hysteresis CMOS
0.05 × VDDD
–
–
SID68A[4]
VHYSCMOS5V5 Input hysteresis CMOS
200
–
–
SID69[4]
IDIODE
Current through protection diode to
VDD/VSS
–
–
100
µA
–
SID69A[4]
ITOT_GPIO
Maximum total source or sink chip
current
–
–
200
mA
–
VDD > 4.5 V
Notes
3. VIH must not exceed VDDD + 0.2 V.
4. Guaranteed by characterization.
Document Number: 002-00123 Rev. *K
Page 14 of 37
PSoC® 4: PSoC 4000S Datasheet
Table 6. GPIO AC Specifications
(Guaranteed by Characterization)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
3.3 V VDDD, Cload =
25 pF
SID70
TRISEF
Rise time in fast strong mode
2
–
12
SID71
TFALLF
Fall time in fast strong mode
2
–
12
SID72
TRISES
Rise time in slow strong mode
10
–
60
–
3.3 V VDDD, Cload =
25 pF
SID73
TFALLS
Fall time in slow strong mode
10
–
60
–
3.3 V VDDD, Cload =
25 pF
SID74
FGPIOUT1
GPIO FOUT; 3.3 V VDDD 5.5 V
Fast strong mode
–
–
33
90/10%, 25 pF load,
60/40 duty cycle
SID75
FGPIOUT2
GPIO FOUT; 1.71 VVDDD3.3 V
Fast strong mode
–
–
16.7
90/10%, 25 pF load,
60/40 duty cycle
SID76
FGPIOUT3
GPIO FOUT; 3.3 V VDDD 5.5 V
Slow strong mode
–
–
7
SID245
FGPIOUT4
GPIO FOUT; 1.71 V VDDD 3.3 V
Slow strong mode.
–
–
3.5
90/10%, 25 pF load,
60/40 duty cycle
SID246
FGPIOIN
GPIO input operating frequency;
1.71 V VDDD 5.5 V
–
–
48
90/10% VIO
Min
Typ
Max
ns
MHz
3.3 V VDDD, Cload =
25 pF
90/10%, 25 pF load,
60/40 duty cycle
XRES
Table 7. XRES DC Specifications
Spec ID#
Parameter
Description
Units
SID77
VIH
Input voltage high threshold
0.7 × VDDD
–
–
SID78
VIL
Input voltage low threshold
–
–
0.3 VDDD
SID79
RPULLUP
Pull-up resistor
–
60
–
kΩ
SID80
CIN
Input capacitance
–
–
7
pF
V
Details/
Conditions
CMOS Input
–
–
Typical hysteresis is
200 mV for VDD > 4.5 V
SID81[5]
VHYSXRES
Input voltage hysteresis
–
100
–
mV
SID82
IDIODE
Current through protection
diode to VDD/VSS
–
–
100
µA
Min
Typ
Max
Units
Details/
Conditions
Table 8. XRES AC Specifications
Spec ID#
SID83[5]
BID194[5]
Parameter
Description
TRESETWIDTH
Reset pulse width
1
–
–
µs
–
TRESETWAKE
Wake-up time from reset
release
–
–
2.7
ms
–
Note
5. Guaranteed by characterization.
Document Number: 002-00123 Rev. *K
Page 15 of 37
PSoC® 4: PSoC 4000S Datasheet
Analog Peripherals
Table 9. Comparator DC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID84
VOFFSET1
Input offset voltage, Factory trim
–
–
±10
SID85
VOFFSET2
Input offset voltage, Custom trim
–
–
±4
SID86
VHYST
Hysteresis when enabled
–
10
35
–
Modes 1 and 2
SID87
VICM1
Input common mode voltage in normal mode
0
–
VDDD-0.1
SID247
VICM2
Input common mode voltage in low power mode
0
–
VDDD
SID247A
VICM3
Input common mode voltage in ultra low power
mode
0
–
VDDD-1.15
SID88
CMRR
Common mode rejection ratio
50
–
–
SID88A
CMRR
Common mode rejection ratio
42
–
–
SID89
ICMP1
Block current, normal mode
–
–
400
SID248
ICMP2
Block current, low power mode
–
–
100
SID259
ICMP3
Block current in ultra low-power mode
–
6
28
SID90
ZCMP
DC Input impedance of comparator
35
–
–
–
mV
V
dB
–
–
VDDD ≥ 2.2 V at
–40 °C
VDDD ≥ 2.7V
VDDD ≤ 2.7V
–
µA
MΩ
–
VDDD ≥ 2.2 V at
–40 °C
–
Table 10. Comparator AC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
SID91
TRESP1
Response time, normal mode, 50 mV overdrive
–
38
110
SID258
TRESP2
Response time, low power mode, 50 mV overdrive
–
70
200
SID92
TRESP3
Response time, ultra-low power mode, 200 mV
overdrive
–
2.3
15
Document Number: 002-00123 Rev. *K
Units
ns
µs
Details/
Conditions
–
–
VDDD ≥ 2.2 V at
–40 °C
Page 16 of 37
PSoC® 4: PSoC 4000S Datasheet
CSD
Table 11. CSD and IDAC Specifications
SPEC ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
SYS.PER#3
VDD_RIPPLE
Max allowed ripple on power supply,
DC to 10 MHz
–
–
±50
mV
VDD > 2 V (with ripple),
25 °C TA, Sensitivity =
0.1 pF
SYS.PER#16
VDD_RIPPLE_1.8
Max allowed ripple on power supply,
DC to 10 MHz
–
–
±25
mV
VDD > 1.75V (with ripple),
25 °C TA, Parasitic Capacitance (CP) < 20 pF,
Sensitivity ≥ 0.4 pF
SID.CSD.BLK
ICSD
Maximum block current
–
–
4000
µA
Maximum block current for
both IDACs in dynamic
(switching) mode including
comparators, buffer, and
reference generator.
SID.CSD#15
VREF
Voltage reference for CSD and
Comparator
0.6
1.2
VDDA - 0.6
V
VDDA - 0.06 or 4.4,
whichever is lower
SID.CSD#15A
VREF_EXT
External Voltage reference for CSD
and Comparator
0.6
VDDA - 0.6
V
VDDA - 0.06 or 4.4,
whichever is lower
SID.CSD#16
IDAC1IDD
IDAC1 (7-bits) block current
–
–
1750
µA
SID.CSD#17
IDAC2IDD
IDAC2 (7-bits) block current
–
–
1750
µA
Voltage range of operation
1.71
–
5.5
V
1.8 V ±5% or 1.8 V to 5.5 V
Voltage compliance range of IDAC
0.6
–
VDDA –0.6
V
VDDA - 0.06 or 4.4,
whichever is lower
SID308
VCSD
SID308A
VCOMPIDAC
SID309
IDAC1DNL
DNL
–1
–
1
LSB
SID310
IDAC1INL
INL
–2
–
2
LSB
SID311
IDAC2DNL
DNL
–1
–
1
LSB
SID312
IDAC2INL
INL
–2
–
2
LSB
SID313
SNR
Ratio of counts of finger to noise.
Guaranteed by characterization
5
–
–
Ratio Capacitance range of 5 to
SID314
IDAC1CRT1
Output current of IDAC1 (7 bits) in
low range
4.2
–
5.4
µA
LSB = 37.5-nA typ.
SID314A
IDAC1CRT2
Output current of IDAC1(7 bits) in
medium range
34
–
41
µA
LSB = 300-nA typ.
SID314B
IDAC1CRT3
Output current of IDAC1(7 bits) in
high range
275
–
330
µA
LSB = 2.4-µA typ.
SID314C
IDAC1CRT12
Output current of IDAC1 (7 bits) in
low range, 2X mode
8
–
10.5
µA
LSB = 75-nA typ.
SID314D
IDAC1CRT22
Output current of IDAC1(7 bits) in
medium range, 2X mode
69
–
82
µA
LSB = 600-nA typ.
SID314E
IDAC1CRT32
Output current of IDAC1(7 bits) in
high range, 2X mode
540
–
660
µA
LSB = 4.8-µA typ.
SID315
IDAC2CRT1
Output current of IDAC2 (7 bits) in
low range
4.2
–
5.4
µA
LSB = 37.5-nA typ.
SID315A
IDAC2CRT2
Output current of IDAC2 (7 bits) in
medium range
34
–
41
µA
LSB = 300-nA typ.
SID315B
IDAC2CRT3
Output current of IDAC2 (7 bits) in
high range
275
–
330
µA
LSB = 2.4-µA typ.
SID315C
IDAC2CRT12
Output current of IDAC2 (7 bits) in
low range, 2X mode
8
–
10.5
µA
LSB = 75-nA typ.
SID315D
IDAC2CRT22
Output current of IDAC2(7 bits) in
medium range, 2X mode
69
–
82
µA
LSB = 600-nA typ.
Document Number: 002-00123 Rev. *K
INL is ±5.5 LSB for VDDA <
2V
INL is ±5.5 LSB for VDDA <
2V
35 pF, 0.1-pF sensitivity. All
use cases. VDDA > 2 V.
Page 17 of 37
PSoC® 4: PSoC 4000S Datasheet
Table 11. CSD and IDAC Specifications (continued)
SPEC ID#
Parameter
Description
Min
Typ
Max
Units
SID315E
IDAC2CRT32
Output current of IDAC2(7 bits) in
high range, 2X mode
SID315F
IDAC3CRT13
SID315G
Details / Conditions
540
–
660
µA
LSB = 4.8-µA typ.
Output current of IDAC in 8-bit mode
in low range
8
–
10.5
µA
LSB = 37.5-nA typ.
IDAC3CRT23
Output current of IDAC in 8-bit mode
in medium range
69
–
82
µA
LSB = 300-nA typ.
SID315H
IDAC3CRT33
Output current of IDAC in 8-bit mode
in high range
540
–
660
µA
LSB = 2.4-µA typ.
SID320
IDACOFFSET
All zeroes input
–
–
1
LSB
SID321
IDACGAIN
Full-scale error less offset
–
–
±10
%
Polarity set by Source or
Sink. Offset is 2 LSBs for
37.5 nA/LSB mode
SID322
IDACMISMATCH1 Mismatch between IDAC1 and
IDAC2 in Low mode
–
–
9.2
LSB
LSB = 37.5-nA typ.
SID322A
IDACMISMATCH2 Mismatch between IDAC1 and
IDAC2 in Medium mode
–
–
5.6
LSB
LSB = 300-nA typ.
SID322B
IDACMISMATCH3 Mismatch between IDAC1 and
IDAC2 in High mode
–
–
6.8
LSB
LSB = 2.4-µA typ.
SID323
IDACSET8
Settling time to 0.5 LSB for 8-bit IDAC
–
–
10
µs
Full-scale transition. No
external load.
SID324
IDACSET7
Settling time to 0.5 LSB for 7-bit IDAC
–
–
10
µs
Full-scale transition. No
external load.
SID325
CMOD
External modulator capacitor.
–
2.2
–
nF
5-V rating, X7R or NP0 cap.
Document Number: 002-00123 Rev. *K
Page 18 of 37
PSoC® 4: PSoC 4000S Datasheet
Table 12. 10-bit CapSense ADC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
bits
Auto-zeroing is required
every millisecond
SIDA94
A_RES
Resolution
–
–
10
SIDA95
A_CHNLS_S
Number of channels - single
ended
–
–
16
SIDA97
A-MONO
Monotonicity
–
–
–
Yes
SIDA98
A_GAINERR
Gain error
–
–
±2
%
In VREF (2.4 V) mode
with VDDA bypass capacitance of 10 µF
SIDA99
A_OFFSET
Input offset voltage
–
–
3
mV
In VREF (2.4 V) mode
with VDDA bypass capacitance of 10 µF
SIDA100
A_ISAR
Current consumption
–
–
0.25
mA
SIDA101
A_VINS
Input voltage range - single
ended
VSSA
–
VDDA
V
SIDA103
A_INRES
Input resistance
–
2.2
–
KΩ
SIDA104
A_INCAP
Input capacitance
–
20
–
pF
SIDA106
A_PSRR
Power supply rejection ratio
–
60
–
dB
SIDA107
A_TACQ
Sample acquisition time
–
1
–
µs
SIDA108
A_CONV8
Conversion time for 8-bit
resolution at conversion rate =
Fhclk/(2^(N+2)). Clock frequency
= 48 MHz.
–
–
21.3
µs
Does not include acquisition time. Equivalent to
44.8 ksps including
acquisition time.
SIDA108A
A_CONV10
Conversion time for 10-bit
resolution at conversion rate =
Fhclk/(2^(N+2)). Clock frequency
= 48 MHz.
–
–
85.3
µs
Does not include acquisition time. Equivalent to
11.6 ksps including
acquisition time.
SIDA109
A_SND
Signal-to-noise and Distortion
ratio (SINAD)
–
61
–
dB
With 10-Hz input sine
wave, external 2.4-V
reference, VREF (2.4 V)
mode
SIDA110
A_BW
Input bandwidth without aliasing
–
–
22.4
kHz
8-bit resolution
SIDA111
A_INL
Integral Non Linearity. 1 ksps
–
–
2
LSB
VREF = 2.4 V or greater
SIDA112
A_DNL
Differential Non Linearity. 1 ksps
–
–
1
LSB
Document Number: 002-00123 Rev. *K
Defined by AMUX Bus.
In VREF (2.4 V) mode
with VDDA bypass capacitance of 10 µF
Page 19 of 37
PSoC® 4: PSoC 4000S Datasheet
Digital Peripherals
Timer Counter Pulse-Width Modulator (TCPWM)
Table 13. TCPWM Specifications
Spec ID
SID.TCPWM.1
Parameter
ITCPWM1
Description
Block current consumption at 3 MHz
Min
–
Typ
–
Max
45
Units
Details/Conditions
All modes (TCPWM)
SID.TCPWM.2
ITCPWM2
Block current consumption at 12 MHz
–
–
155
μA
All modes (TCPWM)
SID.TCPWM.2A ITCPWM3
Block current consumption at 48 MHz
–
–
650
–
–
Fc
2/Fc
–
–
For all trigger events[6]
Minimum possible width
of Overflow, Underflow,
and CC (Counter equals
Compare value) outputs
SID.TCPWM.3
TCPWMFREQ
Operating frequency
SID.TCPWM.4
TPWMENEXT
Input trigger pulse width
SID.TCPWM.5
TPWMEXT
All modes (TCPWM)
MHz
Fc max = CLK_SYS
Maximum = 48 MHz
Output trigger pulse widths
2/Fc
–
–
SID.TCPWM.5A TCRES
Resolution of counter
1/Fc
–
–
SID.TCPWM.5B PWMRES
PWM resolution
1/Fc
–
–
Minimum pulse width of
PWM Output
SID.TCPWM.5C QRES
Quadrature inputs resolution
1/Fc
–
–
Minimum pulse width
between Quadrature
phase inputs
ns
Minimum time between
successive counts
Note
6. Trigger events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected.
Document Number: 002-00123 Rev. *K
Page 20 of 37
PSoC® 4: PSoC 4000S Datasheet
I2C
Table 14. Fixed I2C DC Specifications[7]
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
–
SID149
II2C1
Block current consumption at 100 kHz
–
–
50
SID150
II2C2
Block current consumption at 400 kHz
–
–
135
SID151
II2C3
Block current consumption at 1 Mbps
–
–
310
–
–
1.4
Min
Typ
Max
Units
Details/Conditions
–
–
1
Msps
–
Min
Typ
Max
Units
Details/Conditions
SID152
2
I C enabled in Deep Sleep mode
II2C4
µA
–
–
Table 15. Fixed I2C AC Specifications[7]
Spec ID
SID153
Parameter
Description
FI2C1
Bit rate
Table 16. SPI DC Specifications[7]
Spec ID
Parameter
Description
SID163
ISPI1
Block current consumption at 1 Mbps
–
–
360
–
SID164
ISPI2
Block current consumption at 4 Mbps
–
–
560
SID165
ISPI3
Block current consumption at 8 Mbps
–
–
600
Min
Typ
Max
Units
–
–
8
MHz
µA
–
–
Table 17. SPI AC Specifications[7]
Spec ID
SID166
Parameter
FSPI
Description
SPI operating frequency (Master; 6X
Oversampling)
Details/Conditions
Fixed SPI Master Mode AC Specifications
SID167
TDMO
MOSI Valid after SClock driving edge
–
–
15
SID168
TDSI
MISO Valid before SClock capturing
edge
20
–
–
SID169
THMO
Previous MOSI data hold time
0
–
–
–
ns
Full clock, late MISO
sampling
Referred to Slave
capturing edge
Fixed SPI Slave Mode AC Specifications
SID170
TDMI
MOSI Valid before Sclock Capturing
edge
40
–
–
SID171
TDSO
MISO Valid after Sclock driving edge
–
–
42 +
3*Tcpu
SID171A
TDSO_EXT
MISO Valid after Sclock driving edge in
Ext. Clk mode
–
–
48
–
SID172
THSO
Previous MISO data hold time
0
–
–
–
SID172A
TSSELSSCK SSEL Valid to first SCK Valid edge
–
–
100
–
ns
ns
TCPU = 1/FCPU
–
Note
7. Guaranteed by characterization.
Document Number: 002-00123 Rev. *K
Page 21 of 37
PSoC® 4: PSoC 4000S Datasheet
Table 18. UART DC Specifications[8]
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID160
IUART1
Block current consumption at 100 Kbps
–
–
55
µA
–
SID161
IUART2
Block current consumption at 1000 Kbps
–
–
312
µA
–
Min
Typ
Max
Units
Details/Conditions
–
–
1
Mbps
–
Typ
Max
Units
5
–
µA
500
5000
pF
20
–
mV
Table 19. UART AC Specifications[8]
Spec ID
SID162
Parameter
FUART
Description
Bit rate
Table 20. LCD Direct Drive DC Specifications[8]
Spec ID
Parameter
Description
Min
SID154
ILCDLOW
Operating current in low power mode
SID155
CLCDCAP
LCD capacitance per segment/common
driver
–
SID156
LCDOFFSET
Long-term segment offset
–
SID157
ILCDOP1
LCD system operating current Vbias = 5 V
SID158
ILCDOP2
LCD system operating current Vbias =
3.3 V
–
Details/Conditions
16 4 small segment
disp. at 50 Hz
–
–
32 4 segments. 50 Hz.
25 °C
2
–
2
–
Min
Typ
Max
Units
Details/Conditions
10
50
150
Hz
–
–
–
mA
32 4 segments. 50 Hz.
25 °C
Table 21. LCD Direct Drive AC Specifications[8]
Spec ID
SID159
Parameter
FLCD
Description
LCD frame rate
Note
8. Guaranteed by characterization.
Document Number: 002-00123 Rev. *K
Page 22 of 37
PSoC® 4: PSoC 4000S Datasheet
Memory
Table 22. Flash DC Specifications
Spec ID
SID173
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
1.71
–
5.5
V
–
Description
Min
Typ
Max
Units
Details/Conditions
Erase and program voltage
VPE
Table 23. Flash AC Specifications
Spec ID
Parameter
SID174
TROWWRITE[9]
Row (block) write time (erase and
program)
–
–
20
SID175
TROWERASE[9]
Row erase time
–
–
16
SID176
TROWPROGRAM[9] Row program time after erase
–
–
4
[9]
Row (block) = 128 bytes
ms
–
–
SID178
TBULKERASE
Bulk erase time (32 KB)
–
–
35
SID180[10]
TDEVPROG[9]
Total device program time
–
–
7
Seconds
–
SID181[10]
FEND
Flash endurance
100 K
–
–
Cycles
–
FRET
Flash retention. TA 55 °C, 100 K
P/E cycles
20
–
–
–
Flash retention. TA 85 °C, 10 K
P/E cycles
10
–
–
SID256
TWS48
Number of Wait states at 48 MHz
2
–
–
CPU execution from
Flash
SID257
TWS24
Number of Wait states at 24 MHz
1
–
–
CPU execution from
Flash
Min
Typ
Max
Units
1
–
67
V/ms
V
SID182[10]
SID182A[10]
–
–
Years
–
System Resources
Power-on Reset (POR)
Table 24. Power On Reset (PRES)
Spec ID
Parameter
Description
SID.CLK#6 SR_POWER_UP Power supply slew rate
Details/Conditions
At power-up
[10]
SID185
VRISEIPOR
Rising trip voltage
0.80
–
1.5
SID186[10]
VFALLIPOR
Falling trip voltage
0.70
–
1.4
Min
Typ
Max
Units
Details/Conditions
V
–
–
–
Table 25. Brown-out Detect (BOD) for VCCD
Spec ID
[10]
Parameter
Description
SID190
VFALLPPOR
BOD trip voltage in active and
sleep modes
1.48
–
1.62
SID192[10]
VFALLDPSLP
BOD trip voltage in Deep Sleep
1.11
–
1.5
–
Notes
9. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
10. Guaranteed by characterization.
Document Number: 002-00123 Rev. *K
Page 23 of 37
PSoC® 4: PSoC 4000S Datasheet
SWD Interface
Table 26. SWD Interface Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SWDCLK ≤ 1/3 CPU
clock frequency
SID213
F_SWDCLK1
3.3 V VDD 5.5 V
–
–
14
SID214
F_SWDCLK2
1.71 V VDD 3.3 V
–
–
7
SWDCLK ≤ 1/3 CPU
clock frequency
SID215[11]
T_SWDI_SETUP T = 1/f SWDCLK
0.25*T
–
–
–
SID216[11]
T_SWDI_HOLD
0.25*T
–
–
T_SWDO_VALID T = 1/f SWDCLK
–
–
0.5*T
SID217A[11] T_SWDO_HOLD T = 1/f SWDCLK
1
–
–
MHz
[11]
SID217
T = 1/f SWDCLK
ns
–
–
–
Internal Main Oscillator
Table 27. IMO DC Specifications
(Guaranteed by Design)
Min
Typ
Max
Units
Details/Conditions
SID218
Spec ID
IIMO1
Parameter
IMO operating current at 48 MHz
Description
–
–
250
µA
–
SID219
IIMO2
IMO operating current at 24 MHz
–
–
180
µA
–
Description
Min
Typ
Max
Units
Details/Conditions
–
±2
%
Table 28. IMO AC Specifications
Spec ID
Parameter
SID223
FIMOTOL1
Frequency variation at 24, 32, and
48 MHz (trimmed)
–
SID226
TSTARTIMO
IMO startup time
–
–
7
µs
–
SID228
TJITRMSIMO2
RMS jitter at 24 MHz
–
145
–
ps
–
Min
Typ
Max
Units
Details/Conditions
–
0.3
1.05
µA
–
Internal Low-Speed Oscillator
Table 29. ILO DC Specifications
(Guaranteed by Design)
Spec ID
[11]
SID231
Parameter
IILO1
Description
ILO operating current
Table 30. ILO AC Specifications
Min
Typ
Max
Units
Details/Conditions
SID234[11] TSTARTILO1
SID236[11] TILODUTY
Spec ID
Parameter
ILO startup time
–
–
2
ms
–
ILO duty cycle
40
50
60
%
–
SID237
ILO frequency range
20
40
80
kHz
–
FILOTRIM1
Description
Note
11. Guaranteed by characterization.
Document Number: 002-00123 Rev. *K
Page 24 of 37
PSoC® 4: PSoC 4000S Datasheet
Table 31. Watch Crystal Oscillator (WCO) Specifications
Min
Typ
Max
Units
SID398
Spec ID#
FWCO
Parameter
Crystal Frequency
Description
–
32.768
–
kHz
Details/Conditions
SID399
FTOL
Frequency tolerance
–
50
250
ppm
SID400
ESR
Equivalent series resistance
–
50
–
kΩ
SID401
PD
Drive Level
–
–
1
µW
SID402
TSTART
Startup time
–
–
500
ms
SID403
CL
Crystal Load Capacitance
6
–
12.5
pF
SID404
C0
Crystal Shunt Capacitance
–
1.35
–
pF
SID405
IWCO1
Operating Current (high power mode)
–
–
8
uA
SID406
IWCO2
Operating Current (low power mode)
–
–
1
uA
Min
Typ
Max
Units
Details/Conditions
With 20-ppm crystal
Table 32. External Clock Specifications
Spec ID
SID305[12]
Parameter
Description
ExtClkFreq
External clock input frequency
0
–
48
MHz
–
SID306[12] ExtClkDuty
Duty cycle; measured at VDD/2
45
–
55
%
–
Min
Typ
Max
Units
Details/Conditions
3
–
4
Periods
–
Min
Typ
Max
Units
Details/Conditions
–
–
1.6
ns
Table 33. Block Specs
Spec ID
SID262[12]
Parameter
TCLKSWITCH
Description
System clock source switching time
Table 34. Smart I/O Pass-through Time (Delay in Bypass Mode)
Spec ID#
SID252
Parameter
Description
PRG_BYPASS Max delay added by Smart I/O in
bypass mode
Note
12. Guaranteed by characterization.
Document Number: 002-00123 Rev. *K
Page 25 of 37
PSoC® 4: PSoC 4000S Datasheet
Ordering Information
The PSoC 4000S part numbers and features are listed in the following table.
Table 35. PSoC 4000S Ordering Information
4025
4045
LP Comparators
TCPWM Blocks
SCB Blocks
Smart I/Os
GPIO
WLCSP (0.35-mm pitch)
0
0
1
0
2
5
2
8
21
✔
2
0
0
1
0
2
5
2
8
19
CY8C4024LQI-S402
24
16
2
0
0
1
0
2
5
2
16
27
CY8C4024AXI-S402
24
16
2
0
0
1
0
2
5
2
16
27
CY8C4024LQI-S403
24
16
2
0
0
1
0
2
5
2
16
34
CY8C4024AZI-S403
24
16
2
0
0
1
0
2
5
2
16
36
CY8C4024FNI-S412
24
16
2
0
1
1
0
2
5
2
8
21
CY8C4024LQI-S411
24
16
2
0
1
1
0
2
5
2
8
19
CY8C4024LQI-S412
24
16
2
0
1
1
0
2
5
2
16
27
CY8C4024AXI-S412
24
16
2
0
1
1
0
2
5
2
16
27
CY8C4024LQI-S413
24
16
2
0
1
1
0
2
5
2
16
34
CY8C4024AZI-S413
24
16
2
0
1
1
0
2
5
2
16
36
CY8C4025FNI-S402
24
32
4
0
0
1
0
2
5
2
8
21
CY8C4025LQI-S401
24
32
4
0
0
1
0
2
5
2
8
19
CY8C4025LQI-S402
24
32
4
0
0
1
0
2
5
2
16
27
CY8C4025AXI-S402
24
32
4
0
0
1
0
2
5
2
16
27
CY8C4025AZI-S403
24
32
4
0
0
1
0
2
5
2
16
36
CY8C4025FNI-S412
24
32
4
0
1
1
0
2
5
2
8
21
CY8C4025LQI-S411
24
32
4
0
1
1
0
2
5
2
8
19
CY8C4025LQI-S412
24
32
4
0
1
1
0
2
5
2
16
27
CY8C4025AXI-S412
24
32
4
0
1
1
0
2
5
2
16
27
CY8C4025AZI-S413
24
32
4
0
1
1
0
2
5
2
16
36
CY8C4045FNI-S412
48
32
4
0
1
1
0
2
5
2
8
21
CY8C4045LQI-S411
48
32
4
0
1
1
0
2
5
2
8
19
CY8C4045LQI-S412
48
32
4
0
1
1
0
2
5
2
16
27
CY8C4045AXI-S412
48
32
4
0
1
1
0
2
5
2
16
27
CY8C4045AZI-S413
48
32
4
0
1
1
0
2
5
2
16
36
Document Number: 002-00123 Rev. *K
48-Pin TQFP
12-bit SAR ADC
2
16
40-Pin QFN
10-bit CSD ADC
16
24
32-pin TQFP
CapSense
24
32-Pin QFN
Opamp (CTBm)
CY8C4024FNI-S402
CY8C4024LQI-S401
MPN
24-Pin QFN
SRAM (KB)
4024
Flash (KB)
Category
Package
Max CPU Speed (MHz)
Features
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
✔
Page 26 of 37
PSoC® 4: PSoC 4000S Datasheet
The nomenclature used in the preceding table is based on the following part numbering convention:
Table 36. Nomenclature
Field
Description
CY8C
Cypress Prefix
Values
Meaning
4
Architecture
4
PSoC 4
A
Family
0
4000 Family
B
CPU Speed
2
24 MHz
4
48 MHz
4
16 KB
5
32 KB
6
64 KB
C
Flash Capacity
DE
F
Package Code
Temperature Range
S
Series Designator
XYZ
Attributes Code
7
128 KB
AX
TQFP (0.8-mm pitch)
AZ
TQFP (0.5-mm pitch)
LQ
QFN
PV
SSOP
FN
CSP
I
Industrial
S
PSoC 4 S-Series
M
PSoC 4 M-Series
L
PSoC 4 L-Series
BL
PSoC 4 BLE-Series
000-999
Code of feature set in the specific family
The following is an example of a part number:
Example
CY8C 4 A B C DE F – S XYZ
Cypress Prefix
Architecture
4: PSoC 4
1:
2:
4200
Family
0: 4100
4000 Family
Family within Architecture
CPU Speed
4: 48 MHz
5: 32 KB
Flash Capacity
AZ: TQFP
AX:
TQFP
Package Code
I: Industrial
Temperature Range
Silicon Family
Attributes Code
Document Number: 002-00123 Rev. *K
Page 27 of 37
PSoC® 4: PSoC 4000S Datasheet
Packaging
The PSoC 4000S will be offered in 48-pin TQFP, 40-pin QFN, 32-pin QFN, 24-pin QFN, 32-pin TQFP, and 25-ball WLCSP packages.
Package dimensions and Cypress drawing numbers are in the following table.
Table 37. Package List
Spec ID#
Package
Description
Package Dwg
BID20
48-pin TQFP
7 × 7 × 1.4 mm height with 0.5-mm pitch
51-85135
BID27
40-pin QFN
6 × 6 × 0.6 mm height with 0.5-mm pitch
001-80659
BID34A
32-pin QFN
5 × 5 × 0.6 mm height with 0.5-mm pitch
001-42168
BID34
24-pin QFN
4 × 4 × 0.6 mm height with 0.5-mm pitch
001-13937
BID34G
32-pin TQFP
7 × 7 × 1.4 mm height with 0.8-mm pitch
51-85088
BID34F
25-ball WLCSP
2.02 × 1.93 × 0.48 mm height with 0.35-mm pitch 002-09957
Table 38. Package Thermal Characteristics
Parameter
Description
Package
Min
Typ
Max
Units
TA
Operating ambient temperature
–40
25
85
°C
TJ
Operating junction temperature
–40
–
100
°C
TJA
Package θJA
48-pin TQFP
–
73.5
–
°C/W
TJC
Package θJC
48-pin TQFP
–
33.5
–
°C/W
TJA
Package θJA
40-pin QFN
–
17.8
–
°C/W
TJC
Package θJC
40-pin QFN
–
2.8
–
°C/W
TJA
Package θJA
32-pin QFN
–
20.8
–
°C/W
TJC
Package θJC
32-pin QFN
–
5.9
–
°C/W
TJA
Package θJA
24-pin QFN
–
21.7
–
°C/W
TJC
Package θJC
24-pin QFN
–
5.6
–
°C/W
TJA
Package θJA
32-pin TQFP
–
29.4
–
°C/W
TJC
Package θJC
32-pin TQFP
–
3.5
–
°C/W
TJA
Package θJA
25-ball WLCSP
–
54.6
–
°C/W
TJC
Package θJC
25-ball WLCSP
–
0.5
–
°C/W
Table 39. Solder Reflow Peak Temperature
Package
Maximum Peak
Temperature
Maximum Time at Peak Temperature
All
260 °C
30 seconds
Table 40. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-020
Package
MSL
All except WLCSP
MSL 3
25-ball WLCSP
MSL 1
Document Number: 002-00123 Rev. *K
Page 28 of 37
PSoC® 4: PSoC 4000S Datasheet
Package Diagrams
Figure 5. 48-pin TQFP Package Outline
51-85135 *C
Figure 6. 40-pin QFN Package Outline
001-80659 *A
Document Number: 002-00123 Rev. *K
Page 29 of 37
PSoC® 4: PSoC 4000S Datasheet
Figure 7. 32-pin QFN Package Outline
SEE NOTE 1
TOP VIEW
BOTTOM VIEW
SIDE VIEW
DIMENSIONS
A
A1
HATCH AREA IS SOLDERABLE EXPOSED PAD
MIN.
NOM.
MAX.
0.50
0.55
0.60
3. PACKAGE WEIGHT: 0.0388g
0.045
4. DIMENSIONS ARE IN MILLIMETERS
-
A2
0.020
2. BASED ON REF JEDEC # MO-248
0.15 BSC
D
4.90
5.00
5.10
D2
3.40
3.50
3.60
E
4.90
5.00
5.10
E2
3.40
3.50
3.60
L
0.30
0.40
0.50
b
0.18
0.25
0.30
e
NOTES:
1.
SYMBOL
0.50 TYP
001-42168 *F
Document Number: 002-00123 Rev. *K
Page 30 of 37
PSoC® 4: PSoC 4000S Datasheet
Figure 8. 24-pin QFN Package Outline
001-13937 *F
The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance.
If not connected to ground, it should be electrically floating and not connected to any other signal.
Document Number: 002-00123 Rev. *K
Page 31 of 37
PSoC® 4: PSoC 4000S Datasheet
Figure 9. 32-pin TQFP Package Outline
51-85088 *E
Figure 10. 25-Ball WLCSP Package Outline
002-09957 **
Document Number: 002-00123 Rev. *K
Page 32 of 37
PSoC® 4: PSoC 4000S Datasheet
Acronyms
Table 41. Acronyms Used in this Document
Acronym
Description
Table 41. Acronyms Used in this Document (continued)
Acronym
Description
ETM
embedded trace macrocell
FIR
finite impulse response, see also IIR
FPB
flash patch and breakpoint
FS
full-speed
GPIO
general-purpose input/output, applies to a PSoC
pin
arithmetic logic unit
HVI
high-voltage interrupt, see also LVI, LVD
analog multiplexer bus
IC
integrated circuit
API
application programming interface
IDAC
current DAC, see also DAC, VDAC
APSR
application program status register
IDE
integrated development environment
ARM®
advanced RISC machine, a CPU architecture
I
ATM
automatic thump mode
BW
bandwidth
CAN
Controller Area Network, a communications
protocol
abus
analog local bus
ADC
analog-to-digital converter
AG
analog global
AHB
AMBA (advanced microcontroller bus
architecture) high-performance bus, an ARM
data transfer bus
ALU
AMUXBUS
2C,
or IIC
Inter-Integrated Circuit, a communications
protocol
IIR
infinite impulse response, see also FIR
ILO
internal low-speed oscillator, see also IMO
IMO
internal main oscillator, see also ILO
integral nonlinearity, see also DNL
CMRR
common-mode rejection ratio
INL
CPU
central processing unit
I/O
input/output, see also GPIO, DIO, SIO, USBIO
CRC
cyclic redundancy check, an error-checking
protocol
IPOR
initial power-on reset
IPSR
interrupt program status register
DAC
digital-to-analog converter, see also IDAC, VDAC
IRQ
interrupt request
DFB
digital filter block
ITM
instrumentation trace macrocell
DIO
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
LCD
liquid crystal display
DMIPS
Dhrystone million instructions per second
LIN
Local Interconnect Network, a communications
protocol.
DMA
direct memory access, see also TD
LR
link register
DNL
differential nonlinearity, see also INL
LUT
lookup table
DNU
do not use
LVD
low-voltage detect, see also LVI
DR
port write data registers
LVI
low-voltage interrupt, see also HVI
DSI
digital system interconnect
LVTTL
low-voltage transistor-transistor logic
DWT
data watchpoint and trace
MAC
multiply-accumulate
ECC
error correcting code
MCU
microcontroller unit
ECO
external crystal oscillator
MISO
master-in slave-out
EEPROM
electrically erasable programmable read-only
memory
NC
no connect
EMI
electromagnetic interference
NMI
nonmaskable interrupt
EMIF
external memory interface
NRZ
non-return-to-zero
EOC
end of conversion
NVIC
nested vectored interrupt controller
EOF
end of frame
NVL
nonvolatile latch, see also WOL
EPSR
execution program status register
ESD
electrostatic discharge
Document Number: 002-00123 Rev. *K
opamp
operational amplifier
PAL
programmable array logic, see also PLD
Page 33 of 37
PSoC® 4: PSoC 4000S Datasheet
Table 41. Acronyms Used in this Document (continued)
Acronym
Description
Table 41. Acronyms Used in this Document (continued)
Acronym
Description
PC
program counter
SWV
single-wire viewer
PCB
printed circuit board
TD
transaction descriptor, see also DMA
PGA
programmable gain amplifier
THD
total harmonic distortion
PHUB
peripheral hub
TIA
transimpedance amplifier
PHY
physical layer
TRM
technical reference manual
PICU
port interrupt control unit
TTL
transistor-transistor logic
PLA
programmable logic array
TX
transmit
PLD
programmable logic device, see also PAL
UART
PLL
phase-locked loop
Universal Asynchronous Transmitter Receiver, a
communications protocol
PMDD
package material declaration data sheet
UDB
universal digital block
POR
power-on reset
PRES
precise power-on reset
PRS
pseudo random sequence
PS
port read data register
PSoC®
Programmable System-on-Chip™
PSRR
power supply rejection ratio
PWM
pulse-width modulator
RAM
random-access memory
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
RTL
register transfer language
RTR
remote transmission request
RX
receive
SAR
successive approximation register
SC/CT
switched capacitor/continuous time
SCL
I2C serial clock
SDA
I2C serial data
S/H
sample and hold
SINAD
signal to noise and distortion ratio
SIO
special input/output, GPIO with advanced
features. See GPIO.
SOC
start of conversion
SOF
start of frame
SPI
Serial Peripheral Interface, a communications
protocol
SR
slew rate
SRAM
static random access memory
SRES
software reset
SWD
serial wire debug, a test protocol
Document Number: 002-00123 Rev. *K
USB
Universal Serial Bus
USBIO
USB input/output, PSoC pins used to connect to
a USB port
VDAC
voltage DAC, see also DAC, IDAC
WDT
watchdog timer
WOL
write once latch, see also NVL
WRES
watchdog timer reset
XRES
external reset I/O pin
XTAL
crystal
Page 34 of 37
PSoC® 4: PSoC 4000S Datasheet
Document Conventions
Units of Measure
Table 42. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
dB
decibel
fF
femto farad
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohour
kHz
kilohertz
k
kilo ohm
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
M
mega-ohm
Msps
megasamples per second
µA
microampere
µF
microfarad
µH
microhenry
µs
microsecond
µV
microvolt
µW
microwatt
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
nV
nanovolt
ohm
pF
picofarad
ppm
parts per million
ps
picosecond
s
second
sps
samples per second
sqrtHz
square root of hertz
V
volt
Document Number: 002-00123 Rev. *K
Page 35 of 37
PSoC® 4: PSoC 4000S Datasheet
Document History Page
Description Title: PSoC® 4: PSoC 4000S Datasheet Programmable System-on-Chip (PSoC®)
Document Number: 002-00123
Revision
ECN
Orig. of
Change
Submission
Date
**
4883809
WKA
08/28/2015 New data sheet.
*A
4992376
WKA
10/30/2015 Updated Pinouts.
Added VDDD ≥ 2.2V at –40 °C under Conditions for specs SID247A, SID90,
SID92.
Updated Table 12.
Updated Ordering Information.
*B
5037826
SLAN
12/08/2015 Changed datasheet status to Preliminary
*C
5104369
WKA
01/27/2016 Added Errata.
Added 25 WLCSP package details.
Updated theta JA and JC values for all packages.
*D
5139206
WKA
02/16/2016 Updated copyright information at the end of the document.
*E
5173961
WKA
03/15/2016 Updated Pinouts.
Updated values for SID79, BID194. SID175, and SID176.
Updated CSD and IDAC Specifications.
Updated 10-bit CapSense ADC Specifications.
*F
5268662
WKA
05/12/2016 Updated Alternate Pin Functions.
Updated the following specs:
SID310, SID312, SID313, SID314, SID314C, SID314D, SID314E, SID315,
SID315C, SID315D, SID315E, SID322A, SID322B, SIDA109.
Removed Errata section.
Updated the Cypress logo and copyright information based on the template.
*G
5330930
WKA
07/27/2016 Changed status from Preliminary to Final.
Updated LCD Segment Drive.
Updated SID60 conditions.
Updated IDD specs.
Corrected package dimensions for WLCSP package and added WLCSP MSL
condition.
*H
5415365
WKA
09/14/2016 Added 40-pin QFN pin and package details.
Updated IDD spec values in DC Specifications.
Description of Change
*I
5561833
WKA
01/09/2017 Changed PRGIO references to Smart I/O.
*J
5704046
GNKK
04/26/2017 Updated the Cypress logo and copyright information.
*K
5969745
JIAO
11/17/2017 Updated Document Title to read as “PSoC® 4: PSoC 4000S Datasheet
Programmable System-on-Chip (PSoC®)”.
Added 32-pin TQFP Package related information in all instance across the
document.
Updated Ordering Information:
Updated part numbers.
Updated Packaging:
Updated Package Diagrams:
spec 001-42168 – Changed revision from *E to *F.
Added spec 51-85088 *E.
Document Number: 002-00123 Rev. *K
Page 36 of 37
PSoC® 4: PSoC 4000S Datasheet
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
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Products
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Interface
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Memory
cypress.com/iot
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cypress.com/psoc
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Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs | Training
| Components
Technical Support
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cypress.com/touch
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cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2015-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-00123 Rev. *K
Revised November 17, 2017
Page 37 of 37
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