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Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Programmable System-on-Chip (PSoC)
General Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
ARM® Cortex®-M0+ CPU while being AEC-Q100 compliant. It combines programmable and reconfigurable analog and digital blocks
with flexible automatic routing. The PSoC 4000S product family is a member of the PSoC 4 platform architecture. It is a combination
of a microcontroller with standard communication and timing peripherals, a capacitive touch-sensing system (CapSense) with
best-in-class performance, programmable general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC 4000S products will be upward compatible with members of the PSoC 4 platform for new applications and
design needs.
Features
■
Automotive Electronics Council (AEC) AEC-Q100 Qualified
32-bit MCU Subsystem
LCD Drive Capability
■
■
48-MHz ARM Cortex-M0+ CPU
■
Up to 32 KB of flash with Read Accelerator
■
Up to 4 KB of SRAM
LCD segment drive capability on GPIOs
Timing and Pulse-Width Modulation
Programmable Analog
■
Single-slope 10-bit ADC function provided by Capacitance
sensing block
■
Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
■
Two low-power comparators that operate in Deep Sleep
low-power mode
■
Five 16-bit timer/counter/pulse-width modulator (TCPWM)
blocks
■
Center-aligned, Edge, and Pseudo-random modes
■
Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
Up to 24 Programmable GPIO Pins
■
24-pin QFN and 28-pin SSOP packages
■
Any GPIO pin can be CapSense, analog, or digital
Programmable Digital
■
Drive modes, strengths, and slew rates are programmable
Programmable logic blocks allowing Boolean operations to be
performed on port inputs and outputs
PSoC Creator Design Environment
Low-Power 1.71-V to 5.5-V Operation
■
Deep Sleep mode with operational analog and 2.5 A digital
system current
■
Integrated Development Environment (IDE) provides
schematic design entry and build (with analog and digital
automatic routing)
■
Applications Programming Interface (API) component for all
fixed-function and programmable peripherals
Capacitive Sensing
■
Cypress CapSense Sigma-Delta (CSD) provides best-in-class
signal-to-noise ratio (SNR) (>5:1) and water tolerance
■
Cypress-supplied software component makes capacitive
sensing design easy
■
Automatic hardware tuning (SmartSense™)
Serial Communication
■
Industry-Standard Tool Compatibility
■
After schematic entry, development can be done with
ARM-based industry-standard development tools
Temperature Range
■
A-Grade: 40 °C to +85 °C
■
S-Grade: 40 °C to +105 °C
Two independent run-time reconfigurable Serial
Communication Blocks (SCBs) with re-configurable I2C, SPI,
or UART functionality
Cypress Semiconductor Corporation
Document Number: 002-18381 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 13, 2020
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Contents
Functional Definition ........................................................ 4
CPU and Memory Subsystem ..................................... 4
System Resources ...................................................... 4
Analog Blocks .............................................................. 5
Programmable Digital Blocks ....................................... 5
Fixed Function Digital .................................................. 5
GPIO ........................................................................... 6
Special Function Peripherals ....................................... 6
Pinouts .............................................................................. 7
Alternate Pin Functions ............................................... 8
Power ................................................................................. 9
Mode 1: 1.8 V to 5.5 V External Supply ...................... 9
Mode 2: 1.8 V ±5% External Supply ............................ 9
Development Support .................................................... 10
Documentation .......................................................... 10
Online ........................................................................ 10
Tools.......................................................................... 10
Electrical Specifications ................................................ 11
Absolute Maximum Ratings ...................................... 11
Document Number: 002-18381 Rev. *E
Device Level Specifications ....................................... 11
Analog Peripherals .................................................... 15
Digital Peripherals ..................................................... 18
Memory ..................................................................... 20
System Resources .................................................... 21
Ordering Information ...................................................... 23
Packaging ........................................................................ 25
Package Diagrams .................................................... 26
Acronyms ........................................................................ 28
Document Conventions ................................................. 30
Units of Measure ....................................................... 30
Revision History ............................................................. 31
Sales, Solutions, and Legal Information ...................... 32
Worldwide Sales and Design Support ....................... 32
Products .................................................................... 32
PSoC® Solutions ...................................................... 32
Cypress Developer Community ................................. 32
Technical Support ..................................................... 32
Page 2 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Figure 1. Block Diagram
CPU Subsystem
SWD/ TC
32- bit
48 MHz
System Resources
Lite
SRAM Controller
ROM Controller
WCO
2x LP Comparator
Peripheral Interconnect (MMIO)
PCLK
2x SCB-I2C/SPI/UART
Test
TestMode Entry
Digital DFT
Analog DFT
ROM
8 KB
Peripherals
5x TCPWM
Reset
Reset Control
XRES
Read Accelerator
SRAM
4 KB
System Interconnect ( Single Layer AHB)
IOSS GPIO (5x ports)
Clock
Clock Control
WDT
ILO
IMO
FLASH
32 KB
FAST MUL
NVIC, IRQMUX
AHB- Lite
Power
Sleep Control
WIC
POR
REF
PWRSYS
SPCIF
Cortex
M0+
CapSense
PSoC 4000S
Architecture
High Speed I/ O Matrix & 2 x Programmable I/O
Power Modes
Active/ Sleep
DeepSleep
24x GPIOs, LCD
I/O Subsystem
PSoC 4000S devices include extensive support for
programming, testing, debugging, and tracing both hardware
and firmware.
The ARM Serial-Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE provides fully integrated programming
and debug support for the PSoC 4000S devices. The SWD
interface is fully compatible with industry-standard third-party
tools. The PSoC 4000S family provides a level of security not
possible with multi-chip application solutions or with
microcontrollers. It has the following advantages:
■
Allows disabling of debug features
■
Robust flash protection
■
Allows customer-proprietary functionality to be implemented in
on-chip programmable blocks
Document Number: 002-18381 Rev. *E
The debug circuits are enabled by default and can be disabled
in firmware. If they are not enabled, the only way to re-enable
them is to erase the entire device, clear flash protection, and
reprogram the device with new firmware that enables debugging.
Thus firmware control of debugging cannot be over-ridden
without erasing the firmware thus providing security.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. All programming, debug, and test interfaces are
disabled when maximum device security is enabled. Therefore,
PSoC 4000S, with device security enabled, may not be returned
for failure analysis. This is a trade-off the PSoC 4000S allows the
customer to make.
Page 3 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Functional Definition
CPU and Memory Subsystem
CPU
The Cortex-M0+ CPU in the PSoC 4000S is part of the 32-bit
MCU subsystem, which is optimized for low-power operation
with extensive clock gating. Most instructions are 16 bits in length
and the CPU executes a subset of the Thumb-2 instruction set.
It includes a nested vectored interrupt controller (NVIC) block
with eight interrupt inputs and also includes a Wakeup Interrupt
Controller (WIC). The WIC can wake the processor from Deep
Sleep mode, allowing power to be switched off to the main
processor when the chip is in Deep Sleep mode.
The CPU also includes a debug interface, the serial wire debug
(SWD) interface, which is a two-wire form of JTAG. The debug
configuration used for PSoC 4000S has four breakpoint
(address) comparators and two watchpoint (data) comparators.
Flash
Clock System
The PSoC 4000S clock system is responsible for providing
clocks to all subsystems that require clocks and for switching
between different clock sources without glitching. In addition, the
clock system ensures that there are no metastable conditions.
The clock system for the PSoC 4000S consists of the internal
main oscillator (IMO), internal low-frequency oscillator (ILO), a
32 kHz Watch Crystal Oscillator (WCO) and provision for an
external clock. Clock dividers are provided to generate clocks for
peripherals on a fine-grained basis. Fractional dividers are also
provided to enable clocking of higher data rates for UARTs.
The HFCLK signal can be divided down to generate
synchronous clocks for the analog and digital peripherals. There
are eight clock dividers for the PSoC 4000S, two of those are
fractional dividers. The 16-bit capability allows flexible generation of fine-grained frequency values, and is fully supported in
PSoC Creator.
Figure 2. PSoC 4000S MCU Clocking Architecture
The PSoC 4000S device has a flash module with a flash
accelerator, tightly coupled to the CPU to improve average
access times from the flash block. The low-power flash block is
designed to deliver two wait-state (WS) access time at 48 MHz.
The flash accelerator delivers 85% of single-cycle SRAM access
performance on average.
IMO
Divide By
2,4,8
HFCLK
External Clock
ILO
LFCLK
SRAM
Four KB of SRAM are provided with zero wait-state access at
48 MHz.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
System Resources
HFCLK
SYSCLK
Prescaler
Integer
Dividers
Fractional
Dividers
6X 16-bit
2X 16.5-bit
Power System
IMO Clock Source
The power system is described in detail in the section Power on
page 9. It provides assurance that voltage levels are as required
for each respective mode and either delays mode entry (for
example, on power-on reset (POR)) until voltage levels are as
required for proper functionality, or generates resets (for
example, on brown-out detection). The PSoC 4000S operates
with a single external supply over the range of either 1.8 V ±5%
(externally regulated) or 1.8 to 5.5 V (internally regulated) and
has three different power modes, transitions between which are
managed by the power system. The PSoC 4000S provides
Active, Sleep, and Deep Sleep low-power modes.
The IMO is the primary source of internal clocking in the
PSoC 4000S. It is trimmed during testing to achieve the specified
accuracy.The IMO default frequency is 24 MHz and it can be
adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO tolerance
with Cypress-provided calibration settings is ±2%.
All subsystems are operational in Active mode. The CPU
subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep
mode, while all peripherals and interrupts are active with
instantaneous wake-up on a wake-up event. In Deep Sleep
mode, the high-speed clock and associated circuitry is switched
off; wake-up from this mode takes 35 µs. The opamps can
remain operational in Deep Sleep mode.
Document Number: 002-18381 Rev. *E
ILO Clock Source
The ILO is a very low power, nominally 40-kHz oscillator, which
is primarily used to generate clocks for the watchdog timer
(WDT) and peripheral operation in Deep Sleep mode. ILO-driven
counters can be calibrated to the IMO to improve accuracy.
Cypress provides a software component, which does the
calibration.
Watch Crystal Oscillator (WCO)
The PSoC 4000S clock subsystem also implements a
low-frequency (32-kHz watch crystal) oscillator that can be used
for precision timing applications.
Page 4 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Watchdog Timer
A watchdog timer is implemented in the clock block running from
the ILO; this allows watchdog operation during Deep Sleep and
generates a watchdog reset if not serviced before the set timeout
occurs. The watchdog reset is recorded in a Reset Cause
register, which is firmware readable.
Reset
The PSoC 4000S can be reset from a variety of sources
including a software reset. Reset events are asynchronous and
guarantee reversion to a known state. The reset cause is
recorded in a register, which is sticky through reset and allows
software to determine the cause of the reset. An XRES pin is
reserved for external reset by asserting it active low. The XRES
pin has an internal pull-up resistor that is always enabled.
Voltage Reference
The PSoC 4000S reference system generates all internally
required references. A 1.2-V voltage reference is provided for the
comparator. The IDACs are based on a ±5% reference.
Analog Blocks
Low-power Comparators (LPC)
The PSoC 4000S has a pair of low-power comparators, which
can also operate in Deep Sleep modes. This allows the analog
system blocks to be disabled while retaining the ability to monitor
external voltage levels during low-power modes. The
comparator outputs are normally synchronized to avoid
metastability unless operating in an asynchronous power mode
where the system wake-up circuit is activated by a comparator
switch event. The LPC outputs can be routed to pins.
Current DACs
The PSoC 4000S has two IDACs, which can drive any of the pins
on the chip. These IDACs have programmable current ranges.
Analog Multiplexed Buses
The PSoC 4000S has two concentric independent buses that go
around the periphery of the chip. These buses (called amux
buses) are connected to firmware-programmable analog
switches that allow the chip's internal resources (IDACs,
comparator) to connect to any pin on the I/O Ports.
Programmable Digital Blocks
The programmable I/O (Smart I/O) block is a fabric of switches
and LUTs that allows Boolean functions to be performed in
signals being routed to the pins of a GPIO port. The Smart I/O
can perform logical operations on input pins to the chip and on
signals going out as outputs.
Fixed Function Digital
Timer/Counter/PWM (TCPWM) Block
The TCPWM block consists of a 16-bit counter with
user-programmable period length. There is a capture register to
record the count value at the time of an event (which may be an
I/O event), a period register that is used to either stop or
auto-reload the counter when its count is equal to the period
register, and compare registers to generate compare value
Document Number: 002-18381 Rev. *E
signals that are used as PWM duty cycle outputs. The block also
provides true and complementary outputs with programmable
offset between them to allow use as dead-band programmable
complementary PWM outputs. It also has a Kill input to force
outputs to a predetermined state; for example, this is used in
motor drive systems when an over-current state is indicated and
the PWM driving the FETs needs to be shut off immediately with
no time for software intervention. There are five TCPWM blocks
in the PSoC 4000S.
Serial Communication Block (SCB)
The PSoC 4000S has two serial communication blocks, which
can be programmed to have SPI, I2C, or UART functionality.
I2C Mode: The hardware I2C block implements a full
multi-master and slave interface (it is capable of multi-master
arbitration). This block is capable of operating at speeds of up to
1 Mbps (Fast Mode Plus) and has flexible buffering options to
reduce interrupt overhead and latency for the CPU. It also
supports EZI2C that creates a mailbox address range in the
memory of the PSoC 4000S and effectively reduces I2C communication to reading from and writing to an array in memory. In
addition, the block supports an 8-deep FIFO for receive and
transmit which, by increasing the time given for the CPU to read
data, greatly reduces the need for clock stretching caused by the
CPU not having read data on time.
The I2C peripheral is compatible with the I2C Standard-mode and
Fast Mode Plus devices as defined in the NXP I2C-bus
specification and user manual (UM10204). The I2C bus I/O is
implemented with GPIO in open-drain modes.
The PSoC 4000S is not completely compliant with the I2C spec
in the following respect:
■
GPIO cells are not overvoltage tolerant and, therefore, cannot
be hot-swapped or powered up independently of the rest of the
I2C system.
UART Mode: This is a full-feature UART operating at up to
1 Mbps. It supports automotive single-wire interface (LIN),
infrared interface (IrDA), and SmartCard (ISO7816) protocols, all
of which are minor variants of the basic UART protocol. In
addition, it supports the 9-bit multiprocessor mode that allows
addressing of peripherals connected over common RX and TX
lines. Common UART functions such as parity error, break
detect, and frame error are supported. An 8-deep FIFO allows
much greater CPU service latencies to be tolerated.
SPI Mode: The SPI mode supports full Motorola SPI, TI SSP
(adds a start pulse used to synchronize SPI Codecs), and
National Microwire (half-duplex form of SPI). The SPI block can
use the FIFO.
LIN Slave Mode: The LIN Slave mode uses the SCB hardware
block and implements a full LIN slave interface. This LIN Slave
is compliant with LIN v1.3, v2.1/2.2, ISO 17987-6, and SAE
J2602-2 specification standards. It is certified by C&S GmbH
based on the standard protocol and data link layer conformance
tests. LIN slave can be operated at baud rates of up to ~20 Kbps
with a maximum of 40-meter cable length. PSoC Creator
software supports up to two LIN slave interfaces in the PSoC 4
device, providing built-in application programming interfaces
(APIs) based on the LIN specification standard.
Page 5 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
GPIO
Special Function Peripherals
The PSoC 4000S has up to 24 GPIOs. The GPIO block implements the following:
CapSense
■
■
Eight drive modes:
❐ Analog input mode (input and output buffers disabled)
❐ Input only
❐ Weak pull-up with strong pull-down
❐ Strong pull-up with weak pull-down
❐ Open drain with strong pull-down
❐ Open drain with strong pull-up
❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
Input threshold select (CMOS or LVTTL).
■
Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes
■
Selectable slew rates for dV/dt related noise control to improve
EMI
The pins are organized in logical entities called ports, which are
8-bit in width (less for Ports 2 and 3). During power-on and reset,
the blocks are forced to the disabled state so as not to crowbar
any inputs and/or cause excess turn-on current. A multiplexing
network known as a high-speed I/O matrix is used to multiplex
between various signals that may connect to an I/O pin.
Data output and pin state registers store, respectively, the values
to be driven on the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled and each
I/O port has an interrupt request (IRQ) and interrupt service
routine (ISR) vector associated with it (5 for PSoC 4000S).
Document Number: 002-18381 Rev. *E
CapSense is supported in the PSoC 4000S through a CapSense
Sigma-Delta (CSD) block that can be connected to any pins
through an analog multiplex bus via analog switches. CapSense
function can thus be provided on any available pin or group of
pins in a system under software control. A PSoC Creator
component is provided for the CapSense block to make it easy
for the user.
Shield voltage can be driven on another analog multiplex bus to
provide water-tolerance capability. Water tolerance is provided
by driving the shield electrode in phase with the sense electrode
to keep the shield capacitance from attenuating the sensed
input. Proximity sensing can also be implemented.
The CapSense block has two IDACs, which can be used for
general purposes if CapSense is not being used (both IDACs are
available in that case) or if CapSense is used without water
tolerance (one IDAC is available).
The CapSense block also provides a 10-bit Slope ADC function,
which can be used in conjunction with the CapSense function.
The CapSense block is an advanced, low-noise, programmable
block with programmable voltage references and current source
ranges for improved sensitivity and flexibility. It can also use an
external reference voltage. It has a full-wave CSD mode that
alternates sensing to VDDA and Ground to null out power-supply
related noise.
LCD Segment Drive
The PSoC 4000S has an LCD controller, which can drive up to
4 commons and 20 segments. It uses full digital methods to drive
the LCD segments requiring no generation of internal LCD
voltages. The two methods used are referred to as Digital
Correlation and PWM. Digital Correlation pertains to modulating
the frequency and drive levels of the common and segment
signals to generate the highest RMS voltage across a segment
to light it up or to keep the RMS signal to zero. This method is
good for STN displays but may result in reduced contrast with TN
(cheaper) displays. PWM pertains to driving the panel with PWM
signals to effectively use the capacitance of the panel to provide
the integration of the modulated pulse-width to generate the
desired LCD voltage. This method results in higher power
consumption but can result in better results when driving TN
displays. LCD operation is supported during Deep Sleep
refreshing a small display buffer (4 bits; 1 32-bit register per port).
Page 6 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Pinouts
Table 1 provides the pin list for PSoC 4000S for the 24-pin QFN and 28-pin SSOP packages. All port pins support GPIO.
Table 1. Automotive PSoC 4000S Pin List
24-QFN
28-SSOP
Pin
13
14
Name
P0.0
P0.1
15
16
17
P0.4
P0.5
P0.6
18
19
20
21
22
XRES
VCCD
VSSD
VDD
VSSA
23
24
P1.2
P1.3
1
2
3
P1.7
P2.0
P2.1
4
5
P2.6
P2.7
6
P3.0
7
8
9
10
11
12
P3.2
P3.3
P4.0
P4.1
P4.2
P4.3
Pin
19
20
21
22
Name
P0.0
P0.1
P0.2
P0.3
23
24
25
26
27
28
P0.6
P0.7
XRES
VCCD
VSS
VDD
1
2
3
4
5
6
P1.0
P1.1
P1.2
P1.3
P1.4
P1.7
7
8
9
10
P2.4
P2.5
P2.6
P2.7
11
12
13
14
15
16
17
18
P3.0
P3.1
P3.2
P3.3
P4.0
P4.1
P4.2
P4.3
Descriptions of the pin functions are as follows:
VDDD: Power supply for the digital section.
VDDA: Power supply for the analog section.
VSSD, VSSA: Ground pins for the digital and analog sections respectively.
VCCD: Regulated digital supply (1.8 V ±5%)
VDD: On some packages, VDDA and VDDD are shorted inside and brought out as a single power supply
VSS: On some packages, VSSA and VSSD are shorted inside and brought out as a single ground
Document Number: 002-18381 Rev. *E
Page 7 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Alternate Pin Functions
Each port pin can be assigned to one of multiple functions; it can, for instance, be an analog I/O, a digital peripheral function, an LCD
pin, or a CapSense pin. The pin assignments are shown in the following table.
Port/
Pin
Analog
P0.0
lpcomp.in_p[0]
tcpwm.tr_in[0]
scb[0].spi_select1:0
P0.1
lpcomp.in_n[0]
tcpwm.tr_in[1]
scb[0].spi_select2:0
P0.2
lpcomp.in_p[1]
P0.3
lpcomp.in_n[1]
Smart I/O
Alternate Function 1 Alternate Function 2 Alternate Function 3
Deep Sleep 1
Deep Sleep 2
scb[0].spi_select3:0
P0.4
wco.wco_in
scb[1].uart_rx:0
scb[1].i2c_scl:0
scb[1].spi_mosi:1
P0.5
wco.wco_out
scb[1].uart_tx:0
scb[1].i2c_sda:0
scb[1].spi_miso:1
P0.6
srss.ext_clk
P0.7
scb[1].uart_cts:0
scb[1].spi_clk:1
scb[1].uart_rts:0
scb[1].spi_select0:1
P1.0
tcpwm.line[2]:1
scb[0].uart_rx:1
scb[0].i2c_scl:0
scb[0].spi_mosi:1
P1.1
tcpwm.line_compl[2]:1
scb[0].uart_tx:1
scb[0].i2c_sda:0
scb[0].spi_miso:1
P1.2
tcpwm.line[3]:1
scb[0].uart_cts:1
tcpwm.tr_in[2]
scb[0].spi_clk:1
P1.3
tcpwm.line_compl[3]:1
scb[0].uart_rts:1
tcpwm.tr_in[3]
scb[0].spi_select0:1
P1.4
scb[0].spi_select1:1
P1.7
P2.0
prgio[0].io[0]
tcpwm.line[4]:0
csd.comp
tcpwm.tr_in[4]
scb[1].i2c_scl:1
tcpwm.tr_in[5]
scb[1].i2c_sda:1
scb[1].spi_mosi:2
P2.1
prgio[0].io[1]
tcpwm.line_compl[4]:0
P2.4
prgio[0].io[4]
tcpwm.line[0]:1
scb[1].spi_select1:1
P2.5
prgio[0].io[5]
tcpwm.line_compl[0]:1
scb[1].spi_select2:1
scb[1].spi_miso:2
P2.6
prgio[0].io[6]
tcpwm.line[1]:1
P2.7
prgio[0].io[7]
tcpwm.line_compl[1]:1
scb[1].spi_select3:1
P3.0
prgio[1].io[0]
tcpwm.line[0]:0
scb[1].uart_rx:1
scb[1].i2c_scl:2
scb[1].spi_mosi:0
P3.1
prgio[1].io[1]
tcpwm.line_compl[0]:0
scb[1].uart_tx:1
scb[1].i2c_sda:2
scb[1].spi_miso:0
P3.2
prgio[1].io[2]
tcpwm.line[1]:0
scb[1].uart_cts:1
cpuss.swd_data
scb[1].spi_clk:0
P3.3
prgio[1].io[3]
tcpwm.line_compl[1]:0
scb[1].uart_rts:1
P3.4
prgio[1].io[4]
tcpwm.line[2]:0
lpcomp.comp[0]:1
cpuss.swd_clk
tcpwm.tr_in[6]
scb[1].spi_select0:0
scb[1].spi_select1:0
P4.0
csd.vref_ext
scb[0].uart_rx:0
tcpwm.tr_in[10]
scb[0].i2c_scl:1
scb[0].spi_mosi:0
P4.1
csd.cshieldpads
scb[0].uart_tx:0
tcpwm.tr_in[11]
scb[0].i2c_sda:1
scb[0].spi_miso:0
P4.2
csd.cmodpad
scb[0].uart_cts:0
lpcomp.comp[0]:0
scb[0].spi_clk:0
P4.3
csd.csh_tank
scb[0].uart_rts:0
lpcomp.comp[1]:0
scb[0].spi_select0:0
Document Number: 002-18381 Rev. *E
Page 8 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Power
Mode 1: 1.8 V to 5.5 V External Supply
The following power system diagram shows the set of power
supply pins as implemented for the PSoC 4000S. The system
has one regulator in Active mode for the digital circuitry. There is
no analog regulator; the analog circuits run directly from the
VDDA input.
Figure 3. Power Supply Connections
VDD
VDDA
VSSA
VDDD
Analog
Domain
Mode 2: 1.8 V ±5% External Supply
In this mode, the PSoC 4000S is powered by an external power
supply that must be within the range of 1.71 to 1.89 V; note that
this range needs to include the power supply ripple too. In this
mode, the VDD and VCCD pins are shorted together and
bypassed.
Digital
Domain
VSSD
1.8 Volt
Regulator
In this mode, the PSoC 4000S is powered by an external power
supply that can be anywhere in the range of 1.8 to 5.5 V. This
range is also designed for battery-powered operation. For
example, the chip can be powered from a battery system that
starts at 3.5 V and works down to 1.8 V. In this mode, the internal
regulator of the PSoC 4000S supplies the internal logic and its
output is connected to the VCCD pin. The VCCD pin must be
bypassed to ground via an external capacitor (0.1 µF; X5R
ceramic or better) and must not be connected to anything else.
Bypass capacitors must be used from VDD to ground. The
typical practice for systems in this frequency range is to use a
capacitor in the 1-µF range, in parallel with a smaller capacitor
(0.1 µF, for example). Note that these are simply rules of thumb
and that, for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated to
design and obtain optimal bypassing.
VCCD
An example of a bypass scheme is shown in Figure 4.
There are two distinct modes of operation. In Mode 1, the supply
voltage range is 1.8 V to 5.5 V (unregulated externally; internal
regulator operational). In Mode 2, the supply range is1.8 V ±5%
(externally regulated; 1.71 to 1.89, internal regulator bypassed).
Figure 4. External Supply Range from 1.8 V to 5.5 V with Internal Regulator Active
Power supply bypass connections example
1.8V to 5.5V
PSoC 4000S
V DD
F
0.1F
V CCD
0.1F
V SS
Document Number: 002-18381 Rev. *E
Page 9 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Development Support
The PSoC 4000S family has a rich set of documentation,
development tools, and online resources to assist you during
your development process. Visit www.cypress.com/go/psoc4 to
find out more.
Documentation
A suite of documentation supports the PSoC 4000S family to
ensure that you can find answers to your questions quickly. This
section contains a list of some of the key documents.
Software User Guide: A step-by-step guide for using
PSoC Creator. The software user guide shows you how the
PSoC Creator build process works in detail, how to use source
control with PSoC Creator, and much more.
Component Datasheets: The flexibility of PSoC allows the
creation of new peripherals (components) long after the device
has gone into production. Component data sheets provide all of
the information needed to select and use a particular component,
including a functional description, API documentation, example
code, and AC/DC specifications.
Technical Reference Manual: The Technical Reference Manual
(TRM) contains all the technical detail you need to use a PSoC
device, including a complete description of all PSoC registers.
The TRM is available in the Documentation section at
www.cypress.com/psoc4.
Online
In addition to print documentation, the Cypress PSoC forums
connect you with fellow PSoC users and experts in PSoC from
around the world, 24 hours a day, 7 days a week.
Tools
With industry standard cores, programming, and debugging
interfaces, the PSoC 4000S family is part of a development tool
ecosystem. Visit us at www.cypress.com/go/psoccreator for the
latest information on the revolutionary, easy to use PSoC Creator
IDE, supported third party compilers, programmers, debuggers,
and development kits.
Application Notes: PSoC application notes discuss a particular
application of PSoC in depth; examples include brushless DC
motor control and on-chip filtering. Application notes often
include example projects in addition to the application note
document.
Document Number: 002-18381 Rev. *E
Page 10 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Electrical Specifications
Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings[1]
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
VDDD_ABS
Digital supply relative to VSS
–0.5
–
6
SID2
VCCD_ABS
Direct digital core voltage input relative
to VSS
–0.5
–
1.95
SID3
VGPIO_ABS
GPIO voltage
–0.5
–
VDD+0.5
–
SID4
IGPIO_ABS
Maximum current per GPIO
–25
–
25
–
SID5
IGPIO_injection
GPIO injection current, Max for VIH >
VDDD, and Min for VIL < VSS
–0.5
–
0.5
BID44
ESD_HBM
Electrostatic discharge human body
model
2200
–
–
SID1
–
V
mA
–
Current injected
per pin
–
V
BID45
ESD_CDM
Electrostatic discharge charged device
model
500
–
–
BID46
LU
Pin current for latch-up
–140
–
140
–
mA
–
Device Level Specifications
All specifications are valid for –40 °C TA 85 °C for A grade devices and –40 °C TA 105 °C for S grade devices, except where
noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.
Table 3. DC Specifications
Typical values measured at VDD = 3.3 V and 25 °C.
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
Internally
regulated supply
SID53
VDD
Power supply input voltage
1.8
–
5.5
SID255
VDD
Power supply input voltage (VCCD =
VDD= VDDA)
1.71
–
1.89
SID54
VCCD
Output voltage (for core logic)
–
1.8
–
SID55
CEFC
External regulator voltage bypass
–
0.1
–
SID56
CEXC
Power supply bypass capacitor
–
1
–
X5R ceramic or
better
Max is at 105 °C
and 5.5 V
V
Internally
unregulated
supply
–
µF
X5R ceramic or
better
Active Mode, VDD = 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25 °C.
SID10
IDD5
Execute from flash; CPU at 6 MHz
–
1.2
2.0
SID16
IDD8
Execute from flash; CPU at 24 MHz
–
2.4
4.0
SID19
IDD11
Execute from flash; CPU at 48 MHz
–
4.6
5.9
mA
Max is at 105 °C
and 5.5 V
Max is at 105 °C
and 5.5 V
Note
1. Usage above the absolute maximum conditions listed in Table 2 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended
periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 002-18381 Rev. *E
Page 11 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Table 3. DC Specifications (continued)
Typical values measured at VDD = 3.3 V and 25 °C.
Spec ID#
Parameter
Description
Min
Typ
Max
Units
mA
Details/
Conditions
Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on)
SID22
IDD17
I2C wakeup WDT, and Comparators on
–
1.1
1.6
SID25
IDD20
I2C wakeup, WDT, and Comparators on
–
1.4
1.9
6 MHz, Max is at
105 °C and 5.5 V
12 MHz, Max is at
105 °C and 5.5 V
Sleep Mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed)
SID28
IDD23
I2C wakeup, WDT, and Comparators on
–
0.7
0.9
mA
6 MHz, Max is at
105 °C
SID28A
IDD23A
I2C wakeup, WDT, and Comparators on
–
0.9
1.1
mA
12 MHz, Max is at
105 °C and 5.5 V
–
2.5
60
µA
Max is at 105 °C
and 3.6 V
–
2.5
60
µA
Max is at 105 °C
Deep Sleep Mode, VDD = 1.8 V to 3.6 V (Regulator on)
SID31
IDD26
I2C wakeup and WDT on
Deep Sleep Mode, VDD = 3.6 V to 5.5 V (Regulator on)
SID34
IDD29
I2C wakeup and WDT on
Deep Sleep Mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed)
SID37
IDD32
I2C wakeup and WDT on
–
2.5
60
µA
Max is at 105 °C
IDD_XR
Supply current while XRES asserted
–
2
5
mA
Max is at 105 °C
Min
Typ
Max
Units
DC
–
48
MHz
XRES Current
SID307
Table 4. AC Specifications
Spec ID#
SID48
SID49
[3]
SID50[3]
Parameter
Description
FCPU
CPU frequency
TSLEEP
Wakeup from Sleep mode
–
0
–
TDEEPSLEEP
Wakeup from Deep Sleep mode
–
35
–
Details/
Conditions
1.71 VDD 5.5
µs
Note
2. Guaranteed by characterization.
Document Number: 002-18381 Rev. *E
Page 12 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
GPIO
Table 5. GPIO DC Specifications
Spec ID#
SID57
Parameter
VIH
[3]
Description
Input voltage high threshold
Min
Typ
Max
Units
Details/Conditions
0.7 VDDD
–
–
CMOS Input
0.3
VDDD
CMOS Input
SID58
VIL
Input voltage low threshold
–
–
SID241
VIH[3]
LVTTL input, VDDD < 2.7 V
0.7 VDDD
–
–
–
SID242
VIL
LVTTL input, VDDD < 2.7 V
–
–
0.3
VDDD
–
SID243
VIH[3]
LVTTL input, VDDD 2.7 V
2.0
–
–
SID244
VIL
LVTTL input, VDDD 2.7 V
–
–
0.8
SID59
VOH
Output voltage high level
VDDD –0.6
–
–
IOH = 4 mA at 3 V VDDD
SID60
VOH
Output voltage high level
VDDD –0.5
–
–
IOH = 1 mA at 3 V VDDD
SID61
VOL
Output voltage low level
–
–
0.6
IOL = 4 mA at 1.8 V VDDD
SID62
VOL
Output voltage low level
–
–
0.6
IOL = 10 mA at 3 V VDDD
SID62A
VOL
Output voltage low level
–
–
0.4
IOL = 3 mA at 3 V VDDD
SID63
RPULLUP
Pull-up resistor
3.5
5.6
8.5
SID64
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
SID65
IIL
Input leakage current (absolute
value)
–
–
2
nA
SID66
CIN
Input capacitance
–
–
7
pF
SID67[4]
VHYSTTL
Input hysteresis LVTTL
25
40
–
SID68[4]
VHYSCMOS
Input hysteresis CMOS
0.05 × VDDD
–
–
200
–
–
SID68A
[4]
VHYSCMOS5V5 Input hysteresis CMOS
V
kΩ
–
–
–
–
25 °C, VDDD = 3.0 V
–
VDDD 2.7 V
mV
VDD < 4.5 V
VDD > 4.5 V
SID69[4]
IDIODE
Current through protection diode to
VDD/VSS
–
–
100
µA
–
SID69A[4]
ITOT_GPIO
Maximum total source or sink chip
current
–
–
200
mA
–
Table 6. GPIO AC Specifications
(Guaranteed by Characterization)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
3.3 V VDDD,
Cload = 25 pF
SID70
TRISEF
Rise time in fast strong mode
2
–
12
SID71
TFALLF
Fall time in fast strong mode
2
–
12
SID72
TRISES
Rise time in slow strong mode
10
–
60
–
3.3 V VDDD,
Cload = 25 pF
SID73
TFALLS
Fall time in slow strong mode
10
–
60
–
3.3 V VDDD,
Cload = 25 pF
ns
3.3 V VDDD,
Cload = 25 pF
Notes
3. VIH must not exceed VDDD + 0.2 V.
4. Guaranteed by characterization.
Document Number: 002-18381 Rev. *E
Page 13 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Table 6. GPIO AC Specifications
(Guaranteed by Characterization) (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID74
FGPIOUT1
GPIO FOUT; 3.3 V VDDD 5.5 V
Fast strong mode
–
–
33
90/10%, 25 pF load,
60/40 duty cycle
SID75
FGPIOUT2
GPIO FOUT; 1.71 VVDDD3.3 V
Fast strong mode
–
–
16.7
90/10%, 25 pF load,
60/40 duty cycle
SID76
FGPIOUT3
GPIO FOUT; 3.3 V VDDD 5.5 V
Slow strong mode
–
–
7
SID245
FGPIOUT4
GPIO FOUT; 1.71 V VDDD 3.3 V
Slow strong mode.
–
–
3.5
90/10%, 25 pF load,
60/40 duty cycle
SID246
FGPIOIN
GPIO input operating frequency;
1.71 V VDDD 5.5 V
–
–
48
90/10% VIO
Min
Typ
Max
MHz
90/10%, 25 pF load,
60/40 duty cycle
XRES
Table 7. XRES DC Specifications
Spec ID#
Parameter
Description
Units
Details/Conditions
SID77
VIH
Input voltage high threshold
0.7 × VDDD
–
–
SID78
VIL
Input voltage low threshold
–
–
0.3 VDDD
SID79
RPULLUP
Pull-up resistor
–
60
–
kΩ
–
SID80
CIN
Input capacitance
–
–
7
pF
–
SID81[5]
VHYSXRES
Input voltage hysteresis
–
100
–
mV
SID82
IDIODE
Current through protection
diode to VDD/VSS
–
–
100
µA
V
CMOS Input
Typical hysteresis is
200 mV for VDD > 4.5 V
Table 8. XRES AC Specifications
Min
Typ
Max
Units
Details/Conditions
SID83[5]
Spec ID#
TRESETWIDTH
Parameter
Reset pulse width
Description
1
–
–
µs
–
BID194[5]
TRESETWAKE
Wake-up time from reset
release
–
–
2.7
ms
–
Note
5. Guaranteed by characterization.
Document Number: 002-18381 Rev. *E
Page 14 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Analog Peripherals
Table 9. Comparator DC Specifications
Min
Typ
Max
SID84
Spec ID# Parameter
VOFFSET1
Input offset voltage, Factory trim
Description
–
–
±10
SID85
VOFFSET2
Input offset voltage, Custom trim
–
–
±4
SID86
VHYST
Hysteresis when enabled
–
10
35
–
SID87
VICM1
Input common mode voltage in normal mode
0
–
VDDD-0.1
Modes 1 and 2
SID247
VICM2
Input common mode voltage in low power mode
0
–
VDDD
SID247A VICM3
Input common mode voltage in ultra low power
mode
0
–
VDDD-1.15
SID88
CMRR
Common mode rejection ratio
50
–
–
SID88A
CMRR
Common mode rejection ratio
42
–
–
SID89
ICMP1
Block current, normal mode
–
–
400
SID248
ICMP2
Block current, low power mode
–
–
100
SID259
ICMP3
Block current in ultra low-power mode
–
6
28
SID90
ZCMP
DC Input impedance of comparator
35
–
–
Units
Details/Conditions
–
mV
V
dB
–
–
VDDD ≥ 2.2 V at –40
°C
VDDD ≥ 2.7V
VDDD ≤ 2.7V
–
µA
MΩ
–
VDDD ≥ 2.2 V at –40
°C
–
Table 10. Comparator AC Specifications
Min
Typ
Max
SID91
Spec ID# Parameter
TRESP1
Response time, normal mode, 50 mV overdrive
Description
–
38
110
SID258
TRESP2
Response time, low power mode, 50 mV overdrive
–
70
200
SID92
TRESP3
Response time, ultra-low power mode, 200 mV
overdrive
–
2.3
15
Document Number: 002-18381 Rev. *E
Units
ns
µs
Details/Conditions
–
–
VDDD ≥ 2.2 V at
–40 °C
Page 15 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
CSD
Table 11. CSD and IDAC Specifications
SPEC ID#
Parameter
Description
SYS.PER#3
VDD_RIPPLE
Max allowed ripple on power supply,
DC to 10 MHz
Min
Typ
–
–
SYS.PER#16
VDD_RIPPLE_1.8
Max allowed ripple on power supply,
DC to 10 MHz
–
–
Max
Units
Details / Conditions
±50
mV
VDD > 2 V (with ripple), 25 °C TA,
Sensitivity = 0.1 pF
±25
mV
VDD > 1.75V (with ripple), 25 °C
TA, Parasitic Capacitance (CP) <
20 pF, Sensitivity ≥ 0.4 pF
–
–
4000
µA
Maximum block current for both
IDACs in dynamic (switching)
mode including comparators,
buffer, and reference generator.
Voltage reference for CSD and
Comparator
0.6
1.2
VDDA - 0.6
V
VDDA - 0.06 or 4.4, whichever is
lower
VREF_EXT
External Voltage reference for CSD
and Comparator
0.6
VDDA - 0.6
V
VDDA - 0.06 or 4.4, whichever is
lower
SID.CSD#16
IDAC1IDD
IDAC1 (7-bits) block current
–
–
1750
µA
SID.CSD#17
IDAC2IDD
IDAC2 (7-bits) block current
–
–
1750
µA
SID308
VCSD
Voltage range of operation
1.71
–
5.5
V
1.8 V ±5% or 1.8 V to 5.5 V
SID308A
VCOMPIDAC
Voltage compliance range of IDAC
0.6
–
VDDA –0.6
V
VDDA - 0.06 or 4.4, whichever is
lower
SID309
IDAC1DNL
DNL
–1
–
1
LSB
SID310
IDAC1INL
INL
–2
–
2
LSB INL is ±5.5 LSB for VDDA < 2 V
SID.CSD.BLK
ICSD
Maximum block current
SID.CSD#15
VREF
SID.CSD#15A
SID311
IDAC2DNL
DNL
–1
–
1
LSB
SID312
IDAC2INL
INL
–2
–
2
LSB INL is ±5.5 LSB for VDDA < 2 V
SID313
SNR
Ratio of counts of finger to noise.
Guaranteed by characterization
5
–
–
Ratio 0.1-pF sensitivity. All use cases.
SID314
IDAC1CRT1
Output current of IDAC1 (7 bits) in
low range
4.2
–
5.4
µA
LSB = 37.5-nA typ.
SID314A
IDAC1CRT2
Output current of IDAC1(7 bits) in
medium range
34
–
41
µA
LSB = 300-nA typ.
SID314B
IDAC1CRT3
Output current of IDAC1(7 bits) in
high range
275
–
330
µA
LSB = 2.4-µA typ.
SID314C
IDAC1CRT12
Output current of IDAC1 (7 bits) in
low range, 2X mode
8
–
10.5
µA
LSB = 75-nA typ.
SID314D
IDAC1CRT22
Output current of IDAC1(7 bits) in
medium range, 2X mode
69
–
82
µA
LSB = 600-nA typ.
SID314E
IDAC1CRT32
Output current of IDAC1(7 bits) in
high range, 2X mode
540
–
660
µA
LSB = 4.8-µA typ.
SID315
IDAC2CRT1
Output current of IDAC2 (7 bits) in
low range
4.2
–
5.4
µA
LSB = 37.5-nA typ.
SID315A
IDAC2CRT2
Output current of IDAC2 (7 bits) in
medium range
34
–
41
µA
LSB = 300-nA typ.
SID315B
IDAC2CRT3
Output current of IDAC2 (7 bits) in
high range
275
–
330
µA
LSB = 2.4-µA typ.
SID315C
IDAC2CRT12
Output current of IDAC2 (7 bits) in
low range, 2X mode
8
–
10.5
µA
LSB = 75-nA typ.
SID315D
IDAC2CRT22
Output current of IDAC2(7 bits) in
medium range, 2X mode
69
–
82
µA
LSB = 600-nA typ.
SID315E
IDAC2CRT32
Output current of IDAC2(7 bits) in
high range, 2X mode
540
–
660
µA
LSB = 4.8-µA typ.
Document Number: 002-18381 Rev. *E
Capacitance range of 5 to 35 pF,
VDDA > 2 V.
Page 16 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Table 11. CSD and IDAC Specifications (continued)
SPEC ID#
Parameter
Description
Min
Typ
Max
Units
SID315F
IDAC3CRT13
Output current of IDAC in 8-bit mode
in low range
Details / Conditions
8
–
10.5
µA
LSB = 37.5-nA typ.
SID315G
IDAC3CRT23
Output current of IDAC in 8-bit mode
in medium range
69
–
82
µA
LSB = 300-nA typ.
SID315H
IDAC3CRT33
Output current of IDAC in 8-bit mode
in high range
540
–
660
µA
LSB = 2.4-µA typ.
SID320
IDACOFFSET
All zeroes input
–
–
1
SID321
IDACGAIN
Full-scale error less offset
–
–
±10
SID322
IDACMISMATCH1
Mismatch between IDAC1 and
IDAC2 in Low mode
–
–
9.2
LSB LSB = 37.5-nA typ.
SID322A
IDACMISMATCH2
Mismatch between IDAC1 and
IDAC2 in Medium mode
–
–
5.6
LSB LSB = 300-nA typ.
SID322B
IDACMISMATCH3
Mismatch between IDAC1 and
IDAC2 in High mode
–
–
6.8
LSB LSB = 2.4-µA typ.
SID323
IDACSET8
Settling time to 0.5 LSB for 8-bit IDAC
–
–
10
µs
Full-scale transition. No external
load.
SID324
IDACSET7
Settling time to 0.5 LSB for 7-bit IDAC
–
–
10
µs
Full-scale transition. No external
load.
SID325
CMOD
External modulator capacitor.
–
2.2
–
nF
5-V rating, X7R or NP0 cap.
Polarity set by Source or Sink.
LSB Offset is 2 LSBs for 37.5 nA/LSB
mode
%
Table 12. 10-bit CapSense ADC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
bits
Auto-zeroing is required
every millisecond
SIDA94
A_RES
Resolution
–
–
10
SIDA95
A_CHNLS_S
Number of channels - single
ended
–
–
16
SIDA97
A-MONO
Monotonicity
–
–
–
Yes
SIDA98
A_GAINERR
Gain error
–
–
±2
%
In VREF (2.4 V) mode
with VDDA bypass capacitance of 10 µF
SIDA99
A_OFFSET
Input offset voltage
–
–
3
mV
In VREF (2.4 V) mode
with VDDA bypass capacitance of 10 µF
SIDA100
A_ISAR
Current consumption
–
–
0.25
mA
SIDA101
A_VINS
Input voltage range - single
ended
VSSA
–
VDDA
V
SIDA103
A_INRES
Input resistance
–
2.2
–
KΩ
SIDA104
A_INCAP
Input capacitance
–
20
–
pF
SIDA106
A_PSRR
Power supply rejection ratio
–
60
–
dB
SIDA107
A_TACQ
Sample acquisition time
–
1
–
µs
A_CONV8
Conversion time for 8-bit
resolution at conversion rate =
Fhclk/(2^(N+2)). Clock frequency
= 48 MHz.
SIDA108
Document Number: 002-18381 Rev. *E
–
–
21.3
Defined by AMUX Bus.
µs
In VREF (2.4 V) mode
with VDDA bypass capacitance of 10 µF
Does not include acquisition time. Equivalent to
44.8 ksps including
acquisition time.
Page 17 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Table 12. 10-bit CapSense ADC Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
µs
Does not include acquisition time. Equivalent to
11.6 ksps including
acquisition time.
A_CONV10
Conversion time for 10-bit
resolution at conversion rate =
Fhclk/(2^(N+2)). Clock frequency
= 48 MHz.
SIDA109
A_SND
Signal-to-noise and Distortion
ratio (SINAD)
–
61
–
dB
With 10-Hz input sine
wave, external 2.4-V
reference, VREF (2.4 V)
mode
SIDA110
A_BW
Input bandwidth without aliasing
–
–
22.4
kHz
8-bit resolution
VREF = 2.4 V or greater
SIDA108A
–
–
85.3
SIDA111
A_INL
Integral Non Linearity. 1 ksps
–
–
2
LSB
SIDA112
A_DNL
Differential Non Linearity. 1 ksps
–
–
1
LSB
Digital Peripherals
Timer Counter Pulse-Width Modulator (TCPWM)
Table 13. TCPWM Specifications
Spec ID
SID.TCPWM.1
Parameter
ITCPWM1
Description
Block current consumption at 3 MHz
Min
–
Typ
–
Max
45
Units
SID.TCPWM.2
ITCPWM2
Block current consumption at 12 MHz
–
–
155
μA
SID.TCPWM.2A ITCPWM3
Block current consumption at 48 MHz
–
–
650
–
–
Fc
2/Fc
–
–
For all trigger events[6]
Minimum possible width of
Overflow, Underflow, and
CC (Counter equals
Compare value) outputs
SID.TCPWM.3
TCPWMFREQ
Operating frequency
SID.TCPWM.4
TPWMENEXT
Input trigger pulse width
SID.TCPWM.5
TPWMEXT
Details/Conditions
All modes (TCPWM)
All modes (TCPWM)
All modes (TCPWM)
MHz
Fc max = CLK_SYS
Maximum = 48 MHz
Output trigger pulse widths
2/Fc
–
–
SID.TCPWM.5A TCRES
Resolution of counter
1/Fc
–
–
SID.TCPWM.5B PWMRES
PWM resolution
1/Fc
–
–
Minimum pulse width of
PWM Output
SID.TCPWM.5C QRES
Quadrature inputs resolution
1/Fc
–
–
Minimum pulse width
between Quadrature phase
inputs
ns
Minimum time between
successive counts
I2C
Table 14. Fixed I2C DC Specifications[7]
Description
Min
Typ
Max
SID149
Spec ID
II2C1
Block current consumption at 100 kHz
–
–
50
SID150
II2C2
Block current consumption at 400 kHz
–
–
135
SID151
II2C3
Block current consumption at 1 Mbps
–
–
310
–
–
1.4
SID152
Parameter
II2C4
2
I C enabled in Deep Sleep mode
Units
Details/Conditions
–
µA
–
–
Note
6. Trigger events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected.
7. Guaranteed by characterization.
Document Number: 002-18381 Rev. *E
Page 18 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Table 15. Fixed I2C AC Specifications[8]
Spec ID
SID153
Parameter
Description
FI2C1
Bit rate
Min
Typ
Max
Units
Details/Conditions
–
–
1
Msps
–
Min
Typ
Max
Units
Details/Conditions
Table 16. SPI DC Specifications[8]
Spec ID
Parameter
Description
SID163
ISPI1
Block current consumption at 1 Mbps
–
–
360
–
SID164
ISPI2
Block current consumption at 4 Mbps
–
–
560
SID165
ISPI3
Block current consumption at 8 Mbps
–
–
600
Min
Typ
Max
Units
–
–
8
MHz
µA
–
–
Table 17. SPI AC Specifications[8]
Spec ID
SID166
Parameter
FSPI
Description
SPI operating frequency (Master; 6X
Oversampling)
Details/Conditions
Fixed SPI Master Mode AC Specifications
SID167
TDMO
MOSI Valid after SClock driving edge
–
–
15
SID168
TDSI
MISO Valid before SClock capturing
edge
20
–
–
SID169
THMO
Previous MOSI data hold time
0
–
–
–
ns
Full clock, late MISO
sampling
Referred to Slave
capturing edge
Fixed SPI Slave Mode AC Specifications
SID170
TDMI
MOSI Valid before Sclock Capturing
edge
40
–
–
SID171
TDSO
MISO Valid after Sclock driving edge
–
–
42 +
3*Tcpu
SID171A
TDSO_EXT
MISO Valid after Sclock driving edge in
Ext. Clk mode
–
–
48
–
SID172
THSO
Previous MISO data hold time
0
–
–
–
SID172A
TSSELSSCK SSEL Valid to first SCK Valid edge
–
–
100
Min
Typ
Max
Units
Details/Conditions
–
ns
TCPU = 1/FCPU
ns
–
Table 18. UART DC Specifications[8]
Spec ID
Parameter
Description
SID160
IUART1
Block current consumption at 100 Kbps
–
–
55
µA
–
SID161
IUART2
Block current consumption at 1000 Kbps
–
–
312
µA
–
Min
Typ
Max
Units
Details/Conditions
–
–
1
Mbps
–
Table 19. UART AC Specifications[8]
Spec ID
SID162
Parameter
FUART
Description
Bit rate
Note
8. Guaranteed by characterization.
Document Number: 002-18381 Rev. *E
Page 19 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Table 20. LCD Direct Drive DC Specifications[9]
Spec ID Parameter
Description
SID154
ILCDLOW
Operating current in low power mode
SID155
CLCDCAP
LCD capacitance per segment/common
driver
SID156
LCDOFFSET Long-term segment offset
SID157
ILCDOP1
LCD system operating current Vbias = 5 V
SID158
ILCDOP2
LCD system operating current Vbias = 3.3 V
Min
Typ
Max
Units
5
–
µA
500
5000
pF
20
–
mV
–
–
–
Details/Conditions
16 4 small segment
disp. at 50 Hz
–
–
32 4 segments. 50 Hz.
25 °C
2
–
2
–
Min
Typ
Max
Units
Details/Conditions
10
50
150
Hz
–
–
mA
–
32 4 segments. 50 Hz.
25 °C
Table 21. LCD Direct Drive AC Specifications[9]
Spec ID
SID159
Parameter
Description
LCD frame rate
FLCD
Memory
Table 22. Flash DC Specifications
Spec ID
SID173
Parameter
Description
Erase and program voltage
VPE
Min
Typ
Max
Units
Details/Conditions
1.71
–
5.5
V
–
Units
Details/Conditions
Table 23. Flash AC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
SID174
TROWWRITE[9]
Row (block) write time (erase and
program)
–
–
20
SID175
TROWERASE[9]
Row erase time
–
–
16
SID176
Row program time after erase
–
–
4
SID180[11]
TROWPROGRAM[9]
TBULKERASE[9]
TDEVPROG[9]
SID181[11]
FEND
SID178
SID182[11]
SID182A[11]
FRET
Row (block) = 128 bytes
ms
–
–
Bulk erase time (32 KB)
–
–
35
Total device program time
–
–
7
Seconds
–
100 K
–
–
Cycles
–
Flash retention. TA 55 °C, 100 K
P/E cycles
20
–
–
Flash retention. TA 85 °C, 10 K
P/E cycles
10
–
–
Flash endurance
–
–
Years
–
SID182B
FRETQ
Flash retention. TA 105 °C, 10 K
P/E cycles with no more than 3
years at TA 85 °C
10
–
–
Guaranteed by design
SID256
TWS48
Number of Wait states at 48 MHz
2
–
–
CPU execution from
Flash
Notes
9. Guaranteed by characterization.
10. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
11. Guaranteed by characterization.
Document Number: 002-18381 Rev. *E
Page 20 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Table 23. Flash AC Specifications
SID257
TWS24
Number of Wait states at 24 MHz
CPU execution from
Flash
1
–
–
Min
Typ
Max
Units
1
–
67
V/ms
System Resources
Power-on Reset (POR)
Table 24. Power On Reset (PRES)
Spec ID
Parameter
Description
SID.CLK#6 SR_POWER
Power supply slew rate
SID185[12]
VRISEIPOR
Rising trip voltage
0.80
–
1.5
[12]
VFALLIPOR
Falling trip voltage
0.70
–
1.4
Min
Typ
Max
SID186
Details/Conditions
On power-up and
power-down
–
V
–
Table 25. Brown-out Detect (BOD) for VCCD
Spec ID
Parameter
Description
SID190[12]
VFALLPPOR
BOD trip voltage in active and
sleep modes
1.48
–
1.62
SID192[12]
VFALLDPSLP
BOD trip voltage in Deep Sleep
1.11
–
1.5
Units
Details/Conditions
–
V
–
SWD Interface
Table 26. SWD Interface Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SWDCLK ≤ 1/3 CPU
clock frequency
SID213
F_SWDCLK1
3.3 V VDD 5.5 V
–
–
14
SID214
F_SWDCLK2
1.71 V VDD 3.3 V
–
–
7
SWDCLK ≤ 1/3 CPU
clock frequency
SID215[12]
T_SWDI_SETUP T = 1/f SWDCLK
0.25*T
–
–
–
SID216
T_SWDI_HOLD
0.25*T
–
–
SID217[12]
T_SWDO_VALID T = 1/f SWDCLK
–
–
0.5*T
SID217A[12] T_SWDO_HOLD T = 1/f SWDCLK
1
–
–
Min
Typ
Max
Units
Details/Conditions
MHz
[12]
T = 1/f SWDCLK
ns
–
–
–
Internal Main Oscillator
Table 27. IMO DC Specifications
(Guaranteed by Design)
Spec ID
Parameter
Description
SID218
IIMO1
IMO operating current at 48 MHz
–
–
250
µA
–
SID219
IIMO2
IMO operating current at 24 MHz
–
–
180
µA
–
Description
Min
Typ
Max
Units
Details/Conditions
Table 28. IMO AC Specifications
Spec ID
Parameter
SID223
FIMOTOL1
Frequency variation at 24, 32, and
48 MHz (trimmed)
–
–
±2
%
SID226
TSTARTIMO
IMO startup time
–
–
7
µs
–
SID228
TJITRMSIMO2
RMS jitter at 24 MHz
–
145
–
ps
–
Note
12. Guaranteed by characterization.
Document Number: 002-18381 Rev. *E
Page 21 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Internal Low-Speed Oscillator
Table 29. ILO DC Specifications
(Guaranteed by Design)
Spec ID
Parameter
Description
SID231[13] IILO1
ILO operating current
Min
Typ
Max
Units
Details/Conditions
–
0.3
1.05
µA
–
Min
Typ
Max
Units
Details/Conditions
Table 30. ILO AC Specifications
Spec ID
SID234[13]
Parameter
Description
TSTARTILO1
SID236[13] TILODUTY
SID237
FILOTRIM1
ILO startup time
–
–
2
ms
–
ILO duty cycle
40
50
60
%
–
ILO frequency range
20
40
80
kHz
–
Table 31. Watch Crystal Oscillator (WCO) Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
SID398
FWCO
Crystal Frequency
–
32.768
–
kHz
SID399
FTOL
Frequency tolerance
–
50
250
ppm
Details / Conditions
With 20-ppm crystal
SID400
ESR
Equivalent series resistance
–
50
–
kΩ
SID401
PD
Drive Level
–
–
1
µW
SID402
TSTART
Startup time
–
–
500
ms
SID403
CL
Crystal Load Capacitance
6
–
12.5
pF
SID404
C0
Crystal Shunt Capacitance
–
1.35
–
pF
SID405
IWCO1
Operating Current (high power mode)
–
–
8
uA
SID406
IWCO2
Operating Current (low power mode)
–
–
1
uA
Min
Typ
Max
Units
Details/Conditions
Table 32. External Clock Specifications
Spec ID
SID305[13]
Parameter
Description
ExtClkFreq
External clock input frequency
0
–
48
MHz
–
SID306[13] ExtClkDuty
Duty cycle; measured at VDD/2
45
–
55
%
–
Min
Typ
Max
Units
Details/Conditions
3
–
4
Periods
–
Min
Typ
Max
Units
Details / Conditions
–
–
1.6
ns
Table 33. Block Specs
Spec ID
Parameter
SID262[13] TCLKSWITCH
Description
System clock source switching time
Table 34. Smart I/O Pass-through Time (Delay in Bypass Mode)
Spec ID#
SID252
Parameter
Description
Max delay added by Smart I/O in
PRG_BYPASS
bypass mode
Note
13. Guaranteed by characterization.
Document Number: 002-18381 Rev. *E
Page 22 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Ordering Information
The Automotive PSoC 4000S part numbers and features are listed in Table 35.
Table 35. Automotive PSoC 4000S Ordering Information
TCPWM Blocks
SCB Blocks
GPIO
24-Pin QFN
28-Pin SSOP
–40 to +85 °C
–40 to +105 °C
4045
LP Comparators
4025
12-bit SAR ADC
4024
CSD
4045
Opamp (CTBm)
4025
SRAM (KB)
4024
Operating
Temperature
Flash (KB)
Category
Packages
Max CPU Speed (MHz)
Features
CY8C4024LQA-S411
24
16
2
0
1
0
2
5
2
19
✔
–
✔
–
CY8C4024PVA-S412
24
16
2
0
1
0
2
5
2
24
–
✔
✔
–
CY8C4025LQA-S411
24
32
4
0
1
0
2
5
2
19
✔
–
✔
–
CY8C4025PVA-S412
24
32
4
0
1
0
2
5
2
24
–
✔
✔
–
CY8C4045LQA-S411
48
32
4
0
1
0
2
5
2
19
✔
–
✔
–
CY8C4045PVA-S412
48
32
4
0
1
0
2
5
2
24
–
✔
✔
–
CY8C4024LQS-S411
24
16
2
0
1
0
2
5
2
19
✔
–
–
✔
CY8C4024PVS-S412
24
16
2
0
1
0
2
5
2
24
–
✔
–
✔
CY8C4025LQS-S411
24
32
4
0
1
0
2
5
2
19
✔
–
–
✔
CY8C4025PVS-S412
24
32
4
0
1
0
2
5
2
24
–
✔
–
✔
CY8C4045LQS-S411
48
32
4
0
1
0
2
5
2
19
✔
–
–
✔
CY8C4045PVS-S412
48
32
4
0
1
0
2
5
2
24
–
✔
–
✔
MPN
Document Number: 002-18381 Rev. *E
Page 23 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
The nomenclature used in the preceding table is based on the following part numbering convention:
Field
Description
CY8C
Cypress Prefix
Values
Meaning
4
Architecture
4
PSoC 4
A
Family
0
4000 Family
B
CPU Speed
2
24 MHz
4
48 MHz
4
16 KB
5
32 KB
6
64 KB
7
128 KB
LQ
QFN
C
Flash Capacity
DE
F
Package Code
Temperature Range
S
XYZ
Silicon Family
Attributes Code
PV
SSOP
I
Industrial
A
Automotive (AEC-Q100: –40 °C to +85 °C)
S
Automotive (AEC-Q100: –40 °C to +105 °C)
S
PSoC 4A-S1, PSoC 4A-S2
M
PSoC 4A-M
L
PSoC 4A-L
BL
PSoC 4A-BLE
000-999
Code of feature set in the specific family
The following is an example of a part number:
CY8C 4 A B C DE F – S XYZ T
Example
Cypress Prefix
Architecture
4 : PSoC 4
0 : 4000 Family
Family within Architecture
CPU Speed
4 : 48 MHz
5 : 32 KB
Flash Capacity
PV : SSOP
Package Code
A , S : Automotive
Temperature Range
Silicon Family
Attributes Code
T = Tape and Reel
Document Number: 002-18381 Rev. *E
Page 24 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Packaging
The Automotive PSoC 4000S will be offered in 24-QFN and 28-SSOP packages.
Table 36 provides the package dimensions and Cypress drawing numbers.
Table 36. Package List
Spec ID#
Package
BID34
24-pin QFN
BID28
28-pin SSOP
Description
Package Dwg
4 × 4 × 0.6 mm height, 2.75 × 2.75 mm EPAD (Sawn) 002-18982
210 Mils O28.21
51-85079
Table 37. Package Thermal Characteristics
Parameter
Description
Package
Conditions
Min
Typ
Max
TA
Operating Ambient temperature
TJ
Operating Junction temperature
TJA
Package θJA
TJC
Package θJC
24-pin QFN
–
5.6
–
°C/Watt
TJA
Package θJA
28-pin SSOP
–
66.58
–
°C/Watt
TJC
Package θJC
28-pin SSOP
–
46.28
–
°C/Watt
For A-grade devices
–40
25
85
For S-grade devices
–40
25
105
For A-grade devices
–40
–
100
For S-grade devices
–40
–
120
–
21.7
–
24-pin QFN
Units
°C
°C
°C/Watt
Table 38. Solder Reflow Peak Temperature
Package
Maximum Peak Temperature
Maximum Time at Peak Temperature
All
260 °C
30 seconds
Table 39. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-020
Package
MSL
All
MSL 3
Document Number: 002-18381 Rev. *E
Page 25 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Package Diagrams
Figure 5. 24-pin QFN Package Outline
002-18982 *A
The center pad on the QFN package should be connected to ground (VSS) for best mechanical, thermal, and electrical performance.
If not connected to ground, it should be electrically floating and not connected to any other signal.
Document Number: 002-18381 Rev. *E
Page 26 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Figure 6. 28-Pin SSOP Package Outline
51-85079 *G
Document Number: 002-18381 Rev. *E
Page 27 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Acronyms
Table 40. Acronyms Used in this Document
Acronym
Description
Table 40. Acronyms Used in this Document (continued)
Acronym
Description
ETM
embedded trace macrocell
FIR
finite impulse response, see also IIR
FPB
flash patch and breakpoint
FS
full-speed
GPIO
general-purpose input/output, applies to a PSoC
pin
arithmetic logic unit
HVI
high-voltage interrupt, see also LVI, LVD
analog multiplexer bus
IC
integrated circuit
API
application programming interface
IDAC
current DAC, see also DAC, VDAC
APSR
application program status register
IDE
integrated development environment
ARM®
advanced RISC machine, a CPU architecture
I2C, or IIC
ATM
automatic thump mode
Inter-Integrated Circuit, a communications
protocol
BW
bandwidth
IIR
infinite impulse response, see also FIR
Controller Area Network, a communications
protocol
ILO
internal low-speed oscillator, see also IMO
CAN
IMO
internal main oscillator, see also ILO
integral nonlinearity, see also DNL
abus
analog local bus
ADC
analog-to-digital converter
AG
analog global
AHB
AMBA (advanced microcontroller bus
architecture) high-performance bus, an ARM
data transfer bus
ALU
AMUXBUS
CMRR
common-mode rejection ratio
INL
CPU
central processing unit
I/O
input/output, see also GPIO, DIO, SIO, USBIO
CRC
cyclic redundancy check, an error-checking
protocol
IPOR
initial power-on reset
IPSR
interrupt program status register
DAC
digital-to-analog converter, see also IDAC, VDAC
IRQ
interrupt request
DFB
digital filter block
ITM
instrumentation trace macrocell
DIO
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
LCD
liquid crystal display
DMIPS
Dhrystone million instructions per second
LIN
Local Interconnect Network, a communications
protocol.
DMA
direct memory access, see also TD
LR
link register
DNL
differential nonlinearity, see also INL
LUT
lookup table
DNU
do not use
LVD
low-voltage detect, see also LVI
DR
port write data registers
LVI
low-voltage interrupt, see also HVI
DSI
digital system interconnect
LVTTL
low-voltage transistor-transistor logic
DWT
data watchpoint and trace
MAC
multiply-accumulate
ECC
error correcting code
MCU
microcontroller unit
ECO
external crystal oscillator
MISO
master-in slave-out
EEPROM
electrically erasable programmable read-only
memory
NC
no connect
EMI
electromagnetic interference
NMI
nonmaskable interrupt
EMIF
external memory interface
NRZ
non-return-to-zero
EOC
end of conversion
NVIC
nested vectored interrupt controller
EOF
end of frame
NVL
nonvolatile latch, see also WOL
EPSR
execution program status register
ESD
electrostatic discharge
Document Number: 002-18381 Rev. *E
opamp
operational amplifier
PAL
programmable array logic, see also PLD
Page 28 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Table 40. Acronyms Used in this Document (continued)
Acronym
Description
Table 40. Acronyms Used in this Document (continued)
Acronym
Description
PC
program counter
SWV
single-wire viewer
PCB
printed circuit board
TD
transaction descriptor, see also DMA
PGA
programmable gain amplifier
THD
total harmonic distortion
PHUB
peripheral hub
TIA
transimpedance amplifier
PHY
physical layer
TRM
technical reference manual
PICU
port interrupt control unit
TTL
transistor-transistor logic
PLA
programmable logic array
TX
transmit
UART
Universal Asynchronous Transmitter Receiver, a
communications protocol
UDB
universal digital block
PLD
programmable logic device, see also PAL
PLL
phase-locked loop
PMDD
package material declaration data sheet
POR
power-on reset
PRES
precise power-on reset
PRS
pseudo random sequence
PS
port read data register
PSoC®
Programmable System-on-Chip™
PSRR
power supply rejection ratio
PWM
pulse-width modulator
RAM
random-access memory
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
RTL
register transfer language
RTR
remote transmission request
RX
receive
SAR
successive approximation register
SC/CT
switched capacitor/continuous time
SCL
I2C serial clock
SDA
I2C serial data
S/H
sample and hold
SINAD
signal to noise and distortion ratio
SIO
special input/output, GPIO with advanced
features. See GPIO.
SOC
start of conversion
SOF
start of frame
SPI
Serial Peripheral Interface, a communications
protocol
SR
slew rate
SRAM
static random access memory
SRES
software reset
SWD
serial wire debug, a test protocol
Document Number: 002-18381 Rev. *E
USB
Universal Serial Bus
USBIO
USB input/output, PSoC pins used to connect to
a USB port
VDAC
voltage DAC, see also DAC, IDAC
WDT
watchdog timer
WOL
write once latch, see also NVL
WRES
watchdog timer reset
XRES
external reset I/O pin
XTAL
crystal
Page 29 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Document Conventions
Units of Measure
Table 41. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
dB
decibel
fF
femto farad
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohour
kHz
kilohertz
k
kilo ohm
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
M
mega-ohm
Msps
megasamples per second
µA
microampere
µF
microfarad
µH
microhenry
µs
microsecond
µV
microvolt
µW
microwatt
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
nV
nanovolt
ohm
pF
picofarad
ppm
parts per million
ps
picosecond
s
second
sps
samples per second
sqrtHz
square root of hertz
V
volt
Document Number: 002-18381 Rev. *E
Page 30 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Revision History
Description Title: Automotive PSoC® 4: PSoC 4000S Family Datasheet Programmable System-on-Chip (PSoC)
Document Number: 002-18381
Submission
Revision
ECN
Description of Change
Date
**
5585298 01/13/2017 New datasheet
*A
5651125
03/06/2017 Corrected 28-pin SSOP pin details in Table 1.
Updated General Description, Features, Timer/Counter/PWM (TCPWM)
Block, Ordering Information, and Packaging.
*B
5909901 10/05/2017
Updated Table 1.
Updated Sales, Solutions, and Legal Information.
*C
6078471 02/22/2018 Replaced Spec 002-18982 in Figure 5. 24-pin QFN Package Outline.
Updated Details/Conditions in DC Specifications.
*D
6212923 06/21/2018 Removed SID182B.
Updated 24-pin QFN package diagram.
Updated I2C mode speed to 1 Mbps (Fast Mode Plus).
Updated VDD and VSS pin notes in Pinouts.
Updated Power.
Updated SID.CLK#6 parameter.
*E
7023012
11/13/2020
Added SID182B
Added tape and reel to ordering code definition.
Refer to Product Information Notice #6965423.
Document Number: 002-18381 Rev. *E
Page 31 of 32
Automotive PSoC® 4: PSoC 4000S
Family Datasheet
Sales, Solutions, and Legal Information
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closest to you, visit us at Cypress Locations.
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Document Number: 002-18381 Rev. *E
Revised November 13, 2020
Page 32 of 32
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