Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
PSoC 4: PSoC 4100S Datasheet
Programmable System-on-Chip (PSoC)
General Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
Arm® Cortex™-M0+ CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing.
The PSoC 4100S product family is a member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard
communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, programmable
general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC 4100S products are
upward compatible with members of the PSoC 4 platform for new applications and design needs.
Features
32-bit MCU Subsystem
Timing and Pulse-Width Modulation
■
48-MHz Arm Cortex-M0+ CPU with single-cycle multiply
■
Up to 64 KB of flash with Read Accelerator
■
Up to 8 KB of SRAM
Programmable Analog
■
Two opamps with reconfigurable high-drive external and
high-bandwidth internal drive and Comparator modes and ADC
input buffering capability. Opamps can operate in Deep Sleep
low-power mode.
■
12-bit 1-Msps SAR ADC with differential and single-ended
modes, and Channel Sequencer with signal averaging
■
Single-slope 10-bit ADC function provided by a capacitance
sensing block
■
Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
■
Two low-power comparators that operate in Deep Sleep
low-power mode
Programmable Digital
■
Programmable logic blocks allowing Boolean operations to be
performed on port inputs and outputs
Low-Power 1.71-V to 5.5-V Operation
■
Deep Sleep mode with operational analog and 2.5-µA digital
system current
Capacitive Sensing
■
Five 16-bit timer/counter/pulse-width modulator (TCPWM)
blocks
■
Center-aligned, Edge, and Pseudo-random modes
■
Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
■
Quadrature decoder
Up to 36 Programmable GPIO Pins
■
48-pin TQFP, 44-pin TQFP, 40-pin QFN, 32-pin QFN, and
35-ball WLCSP packages
■
Any GPIO pin can be CapSense, analog, or digital
■
Drive modes, strengths, and slew rates are programmable
Clock Sources
■
32-kHz Watch Crystal Oscillator (WCO)
■
±2% Internal Main Oscillator (IMO)
■
32-kHz Internal Low-power Oscillator (ILO)
ModusToolbox™ Software
■
Comprehensive collection of multi-platform tools and software
libraries
■
Includes board support packages (BSPs), peripheral driver
library (PDL), and middleware such as CapSense
PSoC Creator Design Environment
■
Cypress CapSense Sigma-Delta (CSD) provides best-in-class
signal-to-noise ratio (SNR) (>5:1) and water tolerance
■
Integrated development environment (IDE) provides schematic
design entry and build, with analog and digital automatic routing
■
Cypress-supplied software component makes capacitive
sensing design easy
■
Application programming interface (API) Components for all
fixed-function and programmable peripherals
■
Automatic hardware tuning (SmartSense™)
Industry-Standard Tool Compatibility
LCD Drive Capability
■
■
LCD segment drive capability on GPIOs
After schematic entry, development can be done with
Arm-based industry-standard development tools
Serial Communication
■
Three independent run-time reconfigurable Serial
Communication Blocks (SCBs) with re-configurable I2C, SPI,
or UART functionality
Cypress Semiconductor Corporation
Document Number: 002-00122 Rev. *N
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 10, 2020
PSoC 4: PSoC 4100S Datasheet
Development Ecosystem
PSoC 4 MCU Resources
Cypress provides a wealth of data at www.cypress.com to help you select the right PSoC device and quickly and effectively integrate
it into your design. The following is an abbreviated, hyperlinked list of resources for PSoC 4 MCU:
■
Overview: PSoC Portfolio, PSoC Roadmap
■
Product Selectors: PSoC 4 MCU
■
Application Notes cover a broad range of topics, from basic
to advanced level, and include the following:
❐ AN79953: Getting Started With PSoC 4. This application note
has a convenient flow chart to help decide which IDE to use:
ModusToolbox™ Software or PSoC Creator.
❐ AN91184: PSoC 4 BLE - Designing BLE Applications
❐ AN88619: PSoC 4 Hardware Design Considerations
❐ AN73854: Introduction To Bootloaders
❐ AN89610: Arm Cortex Code Optimization
❐ AN86233: PSoC 4 MCU Power Reduction Techniques
❐ AN57821: Mixed Signal Circuit Board Layout
❐ AN85951: PSoC 4, PSoC 6 CapSense Design Guide
■
Code Examples demonstrate product features and usage, and
are also available on Cypress GitHub repositories.
■
Technical Reference Manuals (TRMs) provide detailed
descriptions of PSoC 4 MCU architecture and registers.
Document Number: 002-00122 Rev. *N
■
PSoC 4 MCU Programming Specification provides the information necessary to program PSoC 4 MCU nonvolatile
memory.
■
Development Tools
❐ ModusToolbox™ Software enables cross platform code
development with a robust suite of tools and software
libraries.
❐ PSoC Creator is a free Windows-based IDE. It enables
concurrent hardware and firmware design of PSoC 3, PSoC
4, PSoC 5LP, and PSoC 6 MCU based systems. Applications
are created using schematic capture and over 150
pre-verified, production-ready peripheral Components.
❐ CY8CKIT-041-41XX PSoC 4100S CapSense Pioneer Kit, is
an easy-to-use and inexpensive development platform. This
kit includes connectors for Arduino™ compatible shields.
❐ MiniProg4
and MiniProg3 all-in-one development
programmers and debuggers.
❐ PSoC 4 MCU CAD libraries provide footprint and schematic
support for common tools. IBIS models are also available.
■
Training Videos are available on a wide range of topics
including the PSoC 4 MCU 101 series.
■
Cypress Developer Community enables connection with
fellow PSoC developers around the world, 24 hours a day, 7
days a week, and hosts a dedicated PSoC 4 MCU Community.
Page 2 of 43
PSoC 4: PSoC 4100S Datasheet
ModusToolbox™ Software
ModusToolbox Software is Cypress' comprehensive collection of multi-platform tools and software libraries that enable an immersive
development experience for creating converged MCU and wireless systems. It is:
■
Comprehensive - it has the resources you need
■
Flexible - you can use the resources in your own workflow
■
Atomic - you can get just the resources you want
Cypress provides a large collection of code repositories on GitHub, including:
■
Board Support Packages (BSPs) aligned with Cypress kits
■
Low-level resources, including a peripheral driver library (PDL)
■
Middleware enabling industry-leading features such as CapSense
■
An extensive set of thoroughly tested code example applications
ModusToolbox Software is IDE-neutral and easily adaptable to your workflow and preferred development environment. It includes a
project creator, peripheral and library configurators, a library manager, as well as the optional Eclipse IDE for ModusToolbox, as
Figure 1 shows. For information on using Cypress tools, refer to the documentation delivered with ModusToolbox software, and
AN79953: Getting Started with PSoC 4.
Figure 1. ModusToolbox Software Tools
Document Number: 002-00122 Rev. *N
Page 3 of 43
PSoC 4: PSoC 4100S Datasheet
PSoC Creator
PSoC Creator is a free Windows-based IDE. It enables you to design hardware and firmware systems concurrently, based on PSoC
4 MCU. As Figure 2 shows, with PSoC Creator you can:
1. Explore the library of 200+ Components
2. Drag and drop Component icons to complete your hardware system design in the main design workspace
3. Configure Components using the Component configuration tools and the Component datasheets
4. Co-design your application firmware and hardware in the PSoC Creator IDE or build a project for a third-party IDE
5. Prototype your solution with the PSoC 4 Pioneer kits. If a design change is needed, PSoC Creator and Components enable you
to make changes on-the-fly without the need for hardware revisions.
Figure 2. PSoC Creator Schematic Entry and Components
Document Number: 002-00122 Rev. *N
Page 4 of 43
PSoC 4: PSoC 4100S Datasheet
Contents
Functional Definition ........................................................ 7
CPU and Memory Subsystem ..................................... 7
System Resources ...................................................... 7
Analog Blocks .............................................................. 8
Programmable Digital Blocks ...................................... 8
Fixed Function Digital .................................................. 8
GPIO ........................................................................... 9
Special Function Peripherals ....................................... 9
Pinouts ............................................................................ 10
Alternate Pin Functions ............................................. 12
Power ............................................................................... 14
Mode 1: 1.8 V to 5.5 V External Supply .................... 14
Mode 2: 1.8 V ±5% External Supply .......................... 14
Electrical Specifications ................................................ 15
Absolute Maximum Ratings ...................................... 15
Device Level Specifications ....................................... 15
Document Number: 002-00122 Rev. *N
Analog Peripherals .................................................... 19
Digital Peripherals ..................................................... 26
Memory ..................................................................... 28
System Resources .................................................... 28
Ordering Information ...................................................... 31
Packaging ........................................................................ 34
Package Diagrams .................................................... 35
Acronyms ........................................................................ 39
Document Conventions ................................................. 41
Units of Measure ....................................................... 41
Revision History ............................................................. 42
Sales, Solutions, and Legal Information ...................... 43
Worldwide Sales and Design Support ....................... 43
Products .................................................................... 43
PSoC® Solutions ...................................................... 43
Cypress Developer Community ................................. 43
Technical Support ..................................................... 43
Page 5 of 43
PSoC 4: PSoC 4100S Datasheet
Figure 3. Block Diagram
CPU Subsystem
SWD/TC
Cortex
M0+
32-bit
48 MHz
System Resources
Lite
SRAM Controller
ROM
8 KB
ROM Controller
Peripherals
SAR ADC
(12-bit)
x1
SARMUX
WCO
Programmable
Analog
2x LP Comparator
Peripheral Interconnect (MMIO)
PCLK
2x SCB-I2C/SPI/UART
Test
TestMode Entry
Digital DFT
Analog DFT
Read Accelerator
CapSense
Reset
Reset Control
XRES
SRAM
8 KB
System Interconnect (Single Layer AHB)
IOSS GPIO (5x ports)
Clock
Clock Control
WDT
ILO
IMO
Flash
64 KB
FAST MUL
NVIC, IRQMUX
AHB- Lite
Power
Sleep Control
WIC
POR
REF
PWRSYS
SPCIF
5x TCPWM
PSoC 4100S
Architecture
CTBm
2x Opamp x1
High Speed I/O Matrix, 2X Smart I/O Ports
Power Modes
Active/ Sleep
DeepSleep
36x GPIOs, LCD
I/O Subsystem
PSoC 4100S devices include extensive support for
programming, testing, debugging, and tracing both hardware
and firmware.
The Arm Serial-Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE provides fully integrated programming
and debug support for the PSoC 4100S devices. The SWD
interface is fully compatible with industry-standard third-party
tools. The PSoC 4100S provides a level of security not possible
with multi-chip application solutions or with microcontrollers.
The debug circuits are enabled by default and can be disabled
in firmware. If they are not enabled, the only way to re-enable
them is to erase the entire device, clear flash protection, and
reprogram the device with new firmware that enables debugging.
Thus firmware control of debugging cannot be over-ridden
without erasing the firmware thus providing security.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. All programming, debug, and test interfaces are
disabled when maximum device security is enabled. Therefore,
PSoC 4100S, with device security enabled, may not be returned
for failure analysis. This is a trade-off the PSoC 4100S allows the
customer to make.
It has the following advantages:
■
Allows disabling of debug features
■
Robust flash protection
■
Allows customer-proprietary functionality to be implemented in
on-chip programmable blocks
Document Number: 002-00122 Rev. *N
Page 6 of 43
PSoC 4: PSoC 4100S Datasheet
Functional Definition
CPU and Memory Subsystem
CPU
The Cortex-M0+ CPU in the PSoC 4100S is part of the 32-bit
MCU subsystem, which is optimized for low-power operation
with extensive clock gating. Most instructions are 16 bits in length
and the CPU executes a subset of the Thumb-2 instruction set.
It includes a nested vectored interrupt controller (NVIC) block
with eight interrupt inputs and also includes a Wakeup Interrupt
Controller (WIC). The WIC can wake the processor from Deep
Sleep mode, allowing power to be switched off to the main
processor when the chip is in Deep Sleep mode.
The clock system for the PSoC 4100S consists of the internal
main oscillator (IMO), internal low-frequency oscillator (ILO), a
32 kHz Watch Crystal Oscillator (WCO) and provision for an
external clock. Clock dividers are provided to generate clocks for
peripherals on a fine-grained basis. Fractional dividers are also
provided to enable clocking of higher data rates for UARTs.
Figure 4. PSoC 4100S MCU Clocking Architecture
IMO
External Clock
WCO
The CPU also includes a debug interface, the serial wire debug
(SWD) interface, which is a two-wire form of JTAG. The debug
configuration used for PSoC 4100S has four breakpoint
(address) comparators and two watchpoint (data) comparators.
Flash
The PSoC 4100S device has a flash module with a flash
accelerator, tightly coupled to the CPU to improve average
access times from the flash block. The low-power flash block is
designed to deliver two wait-state (WS) access time at 48 MHz.
The flash accelerator delivers 85% of single-cycle SRAM access
performance on average.
HFCLK
Divide By
2,4,8
LFCLK
ILO
WDC0
16-bits
WDC1
16-bits
WDC2
32-bits
WDT
Watchdog Counters (WDC)
Watchdog Timer (WDT)
HFCLK
Prescaler
Integer
Dividers
Fractional
Dividers
SYSCLK
6X 16-bit
3X 16.5-bit
SROM
The HFCLK signal can be divided down to generate
synchronous clocks for the analog and digital peripherals. There
are eight clock dividers for the PSoC 4100S; two of those are
fractional dividers. The 16-bit capability allows flexible
generation of fine-grained frequency values and is fully
supported in PSoC Creator
An 8 KB supervisory ROM that contains boot and configuration
routines is provided.
IMO Clock Source
SRAM
Eight KB of SRAM are provided with zero wait-state access at
48 MHz.
System Resources
Power System
The power system is described in detail in the section Power on
page 14. It provides assurance that voltage levels are as
required for each respective mode and either delays mode entry
(for example, on power-on reset (POR)) until voltage levels are
as required for proper functionality, or generates resets (for
example, on brown-out detection). The PSoC 4100S operates
with a single external supply over the range of either 1.8 V ±5%
(externally regulated) or 1.8 to 5.5 V (internally regulated) and
has three different power modes, transitions between which are
managed by the power system. The PSoC 4100S provides
Active, Sleep, and Deep Sleep low-power modes.
All subsystems are operational in Active mode. The CPU
subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep
mode, while all peripherals and interrupts are active with
instantaneous wake-up on a wake-up event. In Deep Sleep
mode, the high-speed clock and associated circuitry is switched
off; wake-up from this mode takes 35 µs. The opamps can
remain operational in Deep Sleep mode.
Clock System
The PSoC 4100S clock system is responsible for providing
clocks to all subsystems that require clocks and for switching
between different clock sources without glitching. In addition, the
clock system ensures that there are no metastable conditions.
Document Number: 002-00122 Rev. *N
The IMO is the primary source of internal clocking in the
PSoC 4100S. It is trimmed during testing to achieve the specified
accuracy.The IMO default frequency is 24 MHz and it can be
adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO tolerance
with Cypress-provided calibration settings is ±2%.
ILO Clock Source
The ILO is a very low power, nominally 40-kHz oscillator, which
is primarily used to generate clocks for the watchdog timer
(WDT) and peripheral operation in Deep Sleep mode. ILO-driven
counters can be calibrated to the IMO to improve accuracy.
Cypress provides a software component, which does the
calibration.
Watch Crystal Oscillator (WCO)
The PSoC 4100S clock subsystem also implements a
low-frequency (32-kHz watch crystal) oscillator that can be used
for precision timing applications. The WCO block allows locking
the IMO to the 32-kHz oscillator.
Watchdog Timer and Counters
A watchdog timer is implemented in the clock block running from
the ILO; this allows watchdog operation during Deep Sleep and
generates a watchdog reset if not serviced before the set timeout
occurs. The watchdog reset is recorded in a Reset Cause
register, which is firmware readable. The Watchdog counters can
be used to implement a Real-Time clock using the 32-kHz WCO.
Reset
Page 7 of 43
PSoC 4: PSoC 4100S Datasheet
The PSoC 4100S can be reset from a variety of sources
including a software reset. Reset events are asynchronous and
guarantee reversion to a known state. The reset cause is
recorded in a register, which is sticky through reset and allows
software to determine the cause of the reset. An XRES pin is
reserved for external reset by asserting it active low. The XRES
pin has an internal pull-up resistor that is always enabled.
Analog Blocks
12-bit SAR ADC
The 12-bit, 1-Msps SAR ADC can operate at a maximum clock
rate of 18 MHz and requires a minimum of 18 clocks at that
frequency to do a 12-bit conversion.
The Sample-and-Hold (S/H) aperture is programmable allowing
the gain bandwidth requirements of the amplifier driving the SAR
inputs, which determine its settling time, to be relaxed if required.
It is possible to provide an external bypass (through a fixed pin
location) for the internal reference amplifier.
The SAR is connected to a fixed set of pins through an 8-input
sequencer. The sequencer cycles through selected channels
autonomously (sequencer scan) with zero switching overhead
(that is, aggregate sampling bandwidth is equal to 1 Msps
whether it is for a single channel or distributed over several
channels). The sequencer switching is effected through a state
machine or through firmware driven switching. A feature
provided by the sequencer is buffering of each channel to reduce
CPU interrupt service requirements. To accommodate signals
with varying source impedance and frequency, it is possible to
have different sample times programmable for each channel.
Also, signal range specification through a pair of range registers
(low and high range values) is implemented with a corresponding
out-of-range interrupt if the digitized value exceeds the
programmed range; this allows fast detection of out-of-range
values without the necessity of having to wait for a sequencer
scan to be completed and the CPU to read the values and check
for out-of-range values in software.
The SAR is not available in Deep Sleep mode as it requires a
high-speed clock (up to 18 MHz). The SAR operating range is
1.71 V to 5.5 V.
Figure 5. SAR ADC
AHB System Bus and Programmable Logic
Interconnect
SAR Sequencer
vminus vplus
SARMUX
SARMUX Port
(Up to 16 inputs)
Sequencing
and Control
Data and
Status Flags
POS
SARADC
NEG
Reference
Selection
VDDA /2
VDDA
Inputs from other Ports
Document Number: 002-00122 Rev. *N
VREF
External
Reference and
Bypass
(optional )
Two Opamps (Continuous-Time Block; CTB)
The PSoC 4100S has two opamps with Comparator modes
which allow most common analog functions to be performed
on-chip eliminating external components; PGAs, Voltage
Buffers, Filters, Trans-Impedance Amplifiers, and other functions
can be realized, in some cases with external passives. saving
power, cost, and space. The on-chip opamps are designed with
enough bandwidth to drive the Sample-and-Hold circuit of the
ADC without requiring external buffering.
Low-power Comparators (LPC)
The PSoC 4100S has a pair of low-power comparators, which
can also operate in Deep Sleep modes. This allows the analog
system blocks to be disabled while retaining the ability to monitor
external voltage levels during low-power modes. The
comparator outputs are normally synchronized to avoid
metastability unless operating in an asynchronous power mode
where the system wake-up circuit is activated by a comparator
switch event. The LPC outputs can be routed to pins.
Current DACs
The PSoC 4100S has two IDACs, which can drive any of the pins
on the chip. These IDACs have programmable current ranges.
Analog Multiplexed Buses
The PSoC 4100S has two concentric independent buses that go
around the periphery of the chip. These buses (called amux
buses) are connected to firmware-programmable analog
switches that allow the chip's internal resources (IDACs,
comparator) to connect to any pin on the I/O Ports.
Programmable Digital Blocks
The Smart I/O block is a fabric of switches and LUTs that allows
Boolean functions to be performed in signals being routed to the
pins of a GPIO port. The Smart I/O can perform logical operations on input pins to the chip and on signals going out as
outputs.
Fixed Function Digital
Timer/Counter/PWM (TCPWM) Block
The TCPWM block consists of a 16-bit counter with
user-programmable period length. There is a capture register to
record the count value at the time of an event (which may be an
I/O event), a period register that is used to either stop or
auto-reload the counter when its count is equal to the period
register, and compare registers to generate compare value
signals that are used as PWM duty cycle outputs. The block also
provides true and complementary outputs with programmable
offset between them to allow use as dead-band programmable
complementary PWM outputs. It also has a Kill input to force
outputs to a predetermined state; for example, this is used in
motor drive systems when an over-current state is indicated and
the PWM driving the FETs needs to be shut off immediately with
no time for software intervention. There are five TCPWM blocks
in the PSoC 4100S.
Page 8 of 43
PSoC 4: PSoC 4100S Datasheet
Serial Communication Block (SCB)
The PSoC 4100S has three serial communication blocks, which
can be programmed to have SPI, I2C, or UART functionality.
I2C Mode: The hardware I2C block implements a full
multi-master and slave interface (it is capable of multi-master
arbitration). This block is capable of operating at speeds of up to
400 kbps (Fast Mode) and has flexible buffering options to
reduce interrupt overhead and latency for the CPU. It also
supports EZI2C that creates a mailbox address range in the
memory of the PSoC 4100S and effectively reduces I2C communication to reading from and writing to an array in memory. In
addition, the block supports an 8-deep FIFO for receive and
transmit which, by increasing the time given for the CPU to read
data, greatly reduces the need for clock stretching caused by the
CPU not having read data on time.
The I2C peripheral is compatible with the I2C Standard-mode and
Fast-mode devices as defined in the NXP I2C-bus specification
and user manual (UM10204). The I2C bus I/O is implemented
with GPIO in open-drain modes.
The PSoC 4100S is not completely compliant with the I2C spec
in the following respect:
■
GPIO cells are not overvoltage tolerant and, therefore, cannot
be hot-swapped or powered up independently of the rest of the
I2C system.
UART Mode: This is a full-feature UART operating at up to
1 Mbps. It supports automotive single-wire interface (LIN),
infrared interface (IrDA), and SmartCard (ISO7816) protocols, all
of which are minor variants of the basic UART protocol. In
addition, it supports the 9-bit multiprocessor mode that allows
addressing of peripherals connected over common RX and TX
lines. Common UART functions such as parity error, break
detect, and frame error are supported. An 8-deep FIFO allows
much greater CPU service latencies to be tolerated.
SPI Mode: The SPI mode supports full Motorola SPI, TI SSP
(adds a start pulse used to synchronize SPI Codecs), and
National Microwire (half-duplex form of SPI). The SPI block can
use the FIFO.
GPIO
The PSoC 4100S has up to 36 GPIOs. The GPIO block implements the following:
■ Eight drive modes:
❐ Analog input mode (input and output buffers disabled)
❐ Input only
❐ Weak pull-up with strong pull-down
❐ Strong pull-up with weak pull-down
❐ Open drain with strong pull-down
❐ Open drain with strong pull-up
❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
■ Input threshold select (CMOS or LVTTL).
■ Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes
■ Selectable slew rates for dV/dt related noise control to improve
EMI
Document Number: 002-00122 Rev. *N
The pins are organized in logical entities called ports, which are
8-bit in width (less for Ports 2 and 3). During power-on and reset,
the blocks are forced to the disable state so as not to crowbar
any inputs and/or cause excess turn-on current. A multiplexing
network known as a high-speed I/O matrix is used to multiplex
between various signals that may connect to an I/O pin.
Data output and pin state registers store, respectively, the values
to be driven on the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled and each
I/O port has an interrupt request (IRQ) and interrupt service
routine (ISR) vector associated with it (5 for PSoC 4100S).
Special Function Peripherals
CapSense
CapSense is supported in the PSoC 4100S through a CapSense
Sigma-Delta (CSD) block that can be connected to any pins
through an analog multiplex bus via analog switches. CapSense
function can thus be provided on any available pin or group of
pins in a system under software control. A PSoC Creator
component is provided for the CapSense block to make it easy
for the user.
Shield voltage can be driven on another analog multiplex bus to
provide water-tolerance capability. Water tolerance is provided
by driving the shield electrode in phase with the sense electrode
to keep the shield capacitance from attenuating the sensed
input. Proximity sensing can also be implemented.
The CapSense block has two IDACs, which can be used for
general purposes if CapSense is not being used (both IDACs are
available in that case) or if CapSense is used without water
tolerance (one IDAC is available).
The CapSense block also provides a 10-bit Slope ADC function
which can be used in conjunction with the CapSense function.
The CapSense block is an advanced, low-noise, programmable
block with programmable voltage references and current source
ranges for improved sensitivity and flexibility. It can also use an
external reference voltage. It has a full-wave CSD mode that
alternates sensing to VDDA and ground to null out power-supply
related noise.
LCD Segment Drive
The PSoC 4100S has an LCD controller, which can drive up to
4 commons and up to 32 segments. It uses full digital methods
to drive the LCD segments requiring no generation of internal
LCD voltages. The two methods used are referred to as Digital
Correlation and PWM. Digital Correlation pertains to modulating
the frequency and drive levels of the common and segment
signals to generate the highest RMS voltage across a segment
to light it up or to keep the RMS signal to zero. This method is
good for STN displays but may result in reduced contrast with TN
(cheaper) displays. PWM pertains to driving the panel with PWM
signals to effectively use the capacitance of the panel to provide
the integration of the modulated pulse-width to generate the
desired LCD voltage. This method results in higher power
consumption but can result in better results when driving TN
displays. LCD operation is supported during Deep Sleep
refreshing a small display buffer (4 bits; 1 32-bit register per port).
Page 9 of 43
PSoC 4: PSoC 4100S Datasheet
Pinouts
Table 1 provides the pin list for PSoC 4100S for the 48-pin TQFP, 44-pin TQFP, 40-pin QFN, 32-pin QFN, and 35-ball CSP packages.
All port pins support GPIO.
Table 1. Pin List
48-TQFP
Pin
Name
44-TQFP
Pin
Name
40-QFN
Pin
32-QFN
Name
Pin
35-CSP
Name
Pin
Name
28
P0.0
24
P0.0
22
P0.0
17
P0.0
C3
P0.0
29
P0.1
25
P0.1
23
P0.1
18
P0.1
A5
P0.1
30
P0.2
26
P0.2
24
P0.2
19
P0.2
A4
P0.2
31
P0.3
27
P0.3
25
P0.3
20
P0.3
A3
P0.3
32
P0.4
28
P0.4
26
P0.4
21
P0.4
B3
P0.4
33
P0.5
29
P0.5
27
P0.5
22
P0.5
A6
P0.5
34
P0.6
30
P0.6
28
P0.6
23
P0.6
B4
P0.6
35
P0.7
31
P0.7
29
P0.7
B5
P0.7
36
XRES
32
XRES
30
XRES
24
XRES
B6
XRES
37
VCCD
33
VCCD
31
VCCD
25
VCCD
A7
VCCD
38
VSSD
DN
VSSD
26
VSSD
B7
VSS
39
VDDD
32
VDDD
C7
VDD
40
41
34
VDDD
VDDA
35
VDDA
33
VDDA
27
VDD
C7
VDD
VSSA
36
VSSA
34
VSSA
28
VSSA
B7
VSS
42
P1.0
37
P1.0
35
P1.0
29
P1.0
C4
P1.0
43
P1.1
38
P1.1
36
P1.1
30
P1.1
C5
P1.1
44
P1.2
39
P1.2
37
P1.2
31
P1.2
C6
P1.2
45
P1.3
40
P1.3
38
P1.3
32
P1.3
D7
P1.3
46
P1.4
41
P1.4
39
P1.4
D4
P1.4
47
P1.5
42
P1.5
D5
P1.5
48
P1.6
43
P1.6
1
P1.7/VREF
44
P1.7/VREF
1
VSSD
40
P1.7/VREF
1
P1.7/VREF
D6
P1.6
E7
P1.7/VREF
2
P2.0
2
P2.0
1
P2.0
2
P2.0
3
P2.1
3
P2.1
2
P2.1
3
P2.1
4
P2.2
4
P2.2
3
P2.2
4
P2.2
D3
P2.2
5
P2.3
5
P2.3
4
P2.3
5
P2.3
E4
P2.3
6
P2.4
6
P2.4
5
P2.4
E5
P2.4
7
P2.5
7
P2.5
6
P2.5
6
P2.5
E6
P2.5
8
P2.6
8
P2.6
7
P2.6
7
P2.6
E3
P2.6
9
P2.7
9
P2.7
8
P2.7
8
P2.7
E2
P2.7
10
VSSD
10
VSSD
9
VSSD
12
P3.0
11
P3.0
10
P3.0
9
P3.0
E1
P3.0
13
P3.1
12
P3.1
11
P3.1
10
P3.1
D2
P3.1
14
P3.2
13
P3.2
12
P3.2
11
P3.2
D1
P3.2
16
P3.3
14
P3.3
13
P3.3
12
P3.3
C1
P3.3
Document Number: 002-00122 Rev. *N
Page 10 of 43
PSoC 4: PSoC 4100S Datasheet
Table 1. Pin List (continued)
48-TQFP
44-TQFP
40-QFN
32-QFN
Pin
Name
Pin
Name
Pin
Name
Pin
17
P3.4
15
P3.4
14
P3.4
18
P3.5
16
P3.5
15
P3.5
19
P3.6
17
P3.6
16
P3.6
20
P3.7
18
P3.7
17
P3.7
21
VDDD
19
VDDD
22
P4.0
20
P4.0
18
P4.0
13
23
P4.1
21
P4.1
19
P4.1
24
P4.2
22
P4.2
20
P4.2
25
P4.3
23
P4.3
21
P4.3
35-CSP
Name
Pin
Name
C2
P3.4
P4.0
B1
P4.0
14
P4.1
B2
P4.1
15
P4.2
A2
P4.2
16
P4.3
A1
P4.3
Note Pins 11, 15, 26, and 27 are No Connects (NC) on the 48-pin TQFP.
Descriptions of the Power pins are as follows:
VDDD: Power supply for the digital section.
VDDA: Power supply for the analog section.
VSSD, VSSA: Ground pins for the digital and analog sections respectively.
VCCD: Regulated digital supply (1.8 V ±5%)
VDD: Power supply to all sections of the chip
VSS: Ground for all sections of the chip
Document Number: 002-00122 Rev. *N
Page 11 of 43
PSoC 4: PSoC 4100S Datasheet
Alternate Pin Functions
Each Port pin has can be assigned to one of multiple functions; it can, for instance, be an analog I/O, a digital peripheral function, an LCD pin, or a CapSense pin. The pin
assignments are shown in Table 2.
Table 2. Alternate Pin Functions
Port/Pin
Analog
Smart I/O
Alternate Function 1
Alternate Function 2
Alternate Function 3
Deep Sleep 1
Deep Sleep 2
P0.0
lpcomp.in_p[0]
P0.1
lpcomp.in_n[0]
tcpwm.tr_in[0]
scb[2].i2c_scl:0
scb[0].spi_select1:0
tcpwm.tr_in[1]
scb[2].i2c_sda:0
scb[0].spi_select2:0
P0.2
lpcomp.in_p[1]
scb[0].spi_select3:0
P0.3
lpcomp.in_n[1]
scb[2].spi_select0
P0.4
wco.wco_in
scb[1].uart_rx:0
scb[2].uart_rx:0
scb[1].i2c_scl:0
scb[1].spi_mosi:1
P0.5
wco.wco_out
scb[1].uart_tx:0
scb[2].uart_tx:0
scb[1].i2c_sda:0
scb[1].spi_miso:1
scb[2].uart_tx:1
P0.6
srss.ext_clk
scb[1].uart_cts:0
P0.7
tcpwm.line[0]:2
scb[1].uart_rts:0
scb[1].spi_clk:1
scb[1].spi_select0:1
P1.0
ctb0_oa0+
tcpwm.line[2]:1
scb[0].uart_rx:1
scb[0].i2c_scl:0
scb[0].spi_mosi:1
P1.1
ctb0_oa0-
tcpwm.line_compl[2]:1
scb[0].uart_tx:1
scb[0].i2c_sda:0
scb[0].spi_miso:1
P1.2
ctb0_oa0_out
tcpwm.line[3]:1
scb[0].uart_cts:1
tcpwm.tr_in[2]
scb[2].i2c_scl:1
scb[0].spi_clk:1
P1.3
ctb0_oa1_out
tcpwm.line_compl[3]:1
scb[0].uart_rts:1
tcpwm.tr_in[3]
scb[2].i2c_sda:1
scb[0].spi_select0:1
P1.4
ctb0_oa1-
scb[0].spi_select1:1
P1.5
ctb0_oa1+
scb[0].spi_select2:1
P1.6
ctb0_oa0+
scb[0].spi_select3:1
P1.7
ctb0_oa1+
sar_ext_vref0
sar_ext_vref1
scb[2].spi_clk
P2.0
sarmux[0]
SmartIo[0].io[0]
P2.1
sarmux[1]
SmartIo[0].io[1] tcpwm.line_compl[4]:0
P2.2
sarmux[2]
SmartIo[0].io[2]
P2.3
sarmux[3]
SmartIo[0].io[3]
P2.4
sarmux[4]
SmartIo[0].io[4]
P2.5
sarmux[5]
SmartIo[0].io[5] tcpwm.line_compl[0]:1
scb[1].spi_select2:1
P2.6
sarmux[6]
SmartIo[0].io[6]
scb[1].spi_select3:1
P2.7
sarmux[7]
SmartIo[0].io[7] tcpwm.line_compl[1]:1
P3.0
SmartIo[1].io[0]
Document Number: 002-00122 Rev. *N
tcpwm.line[4]:0
csd.comp
tcpwm.tr_in[4]
scb[1].i2c_scl:1
scb[1].spi_mosi:2
tcpwm.tr_in[5]
scb[1].i2c_sda:1
scb[1].spi_miso:2
scb[1].spi_clk:2
scb[1].spi_select0:2
tcpwm.line[0]:1
scb[1].spi_select1:1
tcpwm.line[1]:1
tcpwm.line[0]:0
scb[1].uart_rx:1
lpcomp.comp[0]:1
scb[2].spi_mosi
scb[1].i2c_scl:2
scb[1].spi_mosi:0
Page 12 of 43
PSoC 4: PSoC 4100S Datasheet
Table 2. Alternate Pin Functions (continued)
Port/Pin
Deep Sleep 1
Deep Sleep 2
P3.1
Analog
SmartIo[1].io[1] tcpwm.line_compl[0]:0
Smart I/O
Alternate Function 1
scb[1].uart_tx:1
scb[1].i2c_sda:2
scb[1].spi_miso:0
P3.2
SmartIo[1].io[2]
scb[1].uart_cts:1
cpuss.swd_data
scb[1].spi_clk:0
P3.3
SmartIo[1].io[3] tcpwm.line_compl[1]:0
scb[1].uart_rts:1
cpuss.swd_clk
scb[1].spi_select0:0
tcpwm.line[1]:0
Alternate Function 2
tcpwm.line[2]:0
Alternate Function 3
P3.4
SmartIo[1].io[4]
P3.5
SmartIo[1].io[5] tcpwm.line_compl[2]:0
tcpwm.tr_in[6]
scb[1].spi_select1:0
scb[1].spi_select2:0
P3.6
SmartIo[1].io[6]
scb[1].spi_select3:0
P3.7
SmartIo[1].io[7] tcpwm.line_compl[3]:0
tcpwm.line[3]:0
lpcomp.comp[1]:1
scb[2].spi_miso
P4.0
csd.vref_ext
scb[0].uart_rx:0
scb[0].i2c_scl:1
scb[0].spi_mosi:0
P4.1
csd.cshieldpads
scb[0].uart_tx:0
scb[0].i2c_sda:1
scb[0].spi_miso:0
P4.2
csd.cmodpad
scb[0].uart_cts:0
lpcomp.comp[0]:0
scb[0].spi_clk:0
P4.3
csd.csh_tank
scb[0].uart_rts:0
lpcomp.comp[1]:0
scb[0].spi_select0:0
Document Number: 002-00122 Rev. *N
Page 13 of 43
PSoC 4: PSoC 4100S Datasheet
Power
Mode 1: 1.8 V to 5.5 V External Supply
The following power system diagram shows the set of power
supply pins as implemented for the PSoC 4100S. The system
has one regulator in Active mode for the digital circuitry. There is
no analog regulator; the analog circuits run directly from the VDD
input.
Figure 6. Power Supply Connections
VDDA
VDDD
VDDA
VSSA
Mode 2: 1.8 V ±5% External Supply
VDDD
Analog
Domain
In this mode, the PSoC 4100S is powered by an external power
supply that must be within the range of 1.71 to 1.89 V; note that
this range needs to include the power supply ripple too. In this
mode, the VDD and VCCD pins are shorted together and
bypassed. The internal regulator can be disabled in the firmware.
Digital
Domain
VSSD
1.8 Volt
Regulator
In this mode, the PSoC 4100S is powered by an external power
supply that can be anywhere in the range of 1.8 to 5.5 V. This
range is also designed for battery-powered operation. For
example, the chip can be powered from a battery system that
starts at 3.5 V and works down to 1.8 V. In this mode, the internal
regulator of the PSoC 4100S supplies the internal logic and its
output is connected to the VCCD pin. The VCCD pin must be
bypassed to ground via an external capacitor (0.1 µF; X5R
ceramic or better) and must not be connected to anything else.
Bypass capacitors must be used from VDDD to ground. The
typical practice for systems in this frequency range is to use a
capacitor in the 1-µF range, in parallel with a smaller capacitor
(0.1 µF, for example). Note that these are simply rules of thumb
and that, for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated to
design and obtain optimal bypassing.
VCCD
Figure 7 shows an example of a bypass scheme.
There are two distinct modes of operation. In Mode 1, the supply
voltage range is 1.8 V to 5.5 V (unregulated externally; internal
regulator operational). In Mode 2, the supply range is1.8 V ±5%
(externally regulated; 1.71 to 1.89, internal regulator bypassed).
Figure 7. External Supply Range from 1.8 V to 5.5 V with Internal Regulator Active
Power supply bypass connections example
1.8 V to 5.5 V
VDD
F
PSoC 4100S
1.8 V to 5.5 V
VDDA
F
0.1 F
0.1 F
VCCD
0.1 F
VSS
Document Number: 002-00122 Rev. *N
Page 14 of 43
PSoC 4: PSoC 4100S Datasheet
Electrical Specifications
Absolute Maximum Ratings
Table 3. Absolute Maximum Ratings[1]
Spec ID
Parameter
Description
Min
Typ
Max
VDDD_ABS
Digital supply relative to VSS
–0.5
–
6
SID2
VCCD_ABS
Direct digital core voltage input relative
to VSS
–0.5
–
1.95
SID3
VGPIO_ABS
GPIO voltage
–0.5
–
VDD+0.5
SID4
IGPIO_ABS
Maximum current per GPIO
–25
–
25
SID1
SID5
IGPIO_injection
GPIO injection current, Max for VIH >
VDDD, and Min for VIL < VSS
–0.5
–
0.5
BID44
ESD_HBM
Electrostatic discharge human body
model
2200
–
–
Unit
Details/Conditions
–
V
–
–
–
mA
Current injected per pin
–
V
BID45
ESD_CDM
Electrostatic discharge charged device
model
500
–
–
BID46
LU
Pin current for latch-up
–140
–
140
–
mA
–
Device Level Specifications
All specifications are valid for –40 °C TA 105 °C and TJ 125 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
Table 4. DC Specifications
Typical values measured at VDD = 3.3 V and 25 °C.
Spec ID
Parameter
Description
Min
Typ
Max
VDD
Power supply input voltage
1.8
–
5.5
SID255 VDD
Power supply input voltage
(VCCD = VDDD = VDDA)
1.71
–
1.89
SID54
VCCD
Output voltage (for core logic)
–
1.8
–
SID55
CEFC
External regulator voltage bypass
–
0.1
–
SID56
CEXC
Power supply bypass capacitor
–
1
–
SID53
Unit
Details/Conditions
Internally regulated
supply
V
Internally unregulated
supply
–
µF
X5R ceramic or better
mA
Max is at 85 °C and
5.5 V
Active Mode, VDD = 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25 °C.
SID10
IDD5
Execute from flash; CPU at 6 MHz
–
1.8
2.7
SID16
IDD8
Execute from flash; CPU at 24 MHz
–
3.0
4.75
SID19
IDD11
Execute from flash; CPU at 48 MHz
–
5.4
6.85
Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on)
SID22
IDD17
I2C wakeup WDT, and Comparators on
–
1.7
2.2
SID25
IDD20
I2C wakeup, WDT, and Comparators on.
–
2.2
2.5
mA
6 MHZ. Max is at 85 °C
and 5.5 V.
12 MHZ. Max is at 85
°C and 5.5 V.
Sleep Mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed)
Note
1. Usage above the absolute maximum conditions listed in Table 3 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended
periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 002-00122 Rev. *N
Page 15 of 43
PSoC 4: PSoC 4100S Datasheet
Table 4. DC Specifications (continued)
Typical values measured at VDD = 3.3 V and 25 °C.
Spec ID
SID28
Parameter
IDD23
Description
Min
Typ
Max
Unit
I2C wakeup, WDT, and Comparators on
–
0.7
0.9
I2C wakeup, WDT, and Comparators on
–
1
1.2
–
2.5
60
µA
Max is at 3.6 V and 85
°C.
–
2.5
60
µA
Max is at 5.5 V and 85
°C.
mA
SID28A IDD23A
Details/Conditions
6 MHZ. Max is at 85 °C
and 5.5 V.
12 MHZ. Max is at 85
°C and 5.5 V.
Deep Sleep Mode, VDD = 1.8 V to 3.6 V (Regulator on)
SID31
IDD26
I2C wakeup and WDT on
Deep Sleep Mode, VDD = 3.6 V to 5.5 V (Regulator on)
SID34
IDD29
I2C wakeup and WDT on
Deep Sleep Mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed)
SID37
IDD32
I2C wakeup and WDT on
–
2.5
65
µA
Max is at 1.89 V and 85
°C.
Supply current while XRES asserted
–
2
5
mA
–
Min
Typ
Max
Unit
Details/Conditions
MHz
XRES Current
SID307 IDD_XR
Table 5. AC Specifications
Spec ID
Parameter
Description
DC
–
48
SID49[2] TSLEEP
Wakeup from Sleep mode
–
0
–
SID50[2]
Wakeup from Deep Sleep mode
–
35
–
SID48
FCPU
TDEEPSLEEP
CPU frequency
µs
1.71 VDD 5.5
–
–
Note
2. Guaranteed by characterization.
Document Number: 002-00122 Rev. *N
Page 16 of 43
PSoC 4: PSoC 4100S Datasheet
GPIO
Table 6. GPIO DC Specifications
Spec ID
Parameter
Min
Typ
Max
Input voltage high threshold
0.7 VDDD
–
–
VIL
Input voltage low threshold
–
–
SID241
VIH[3]
LVTTL input, VDDD < 2.7 V
0.7 VDDD
0.3
VDDD
–
–
–
SID242
VIL
LVTTL input, VDDD < 2.7 V
–
–
0.3
VDDD
–
SID243
VIH[3]
LVTTL input, VDDD 2.7 V
2.0
–
–
SID244
VIL
LVTTL input, VDDD 2.7 V
–
–
0.8
SID59
VOH
Output voltage high level
VDDD –0.6
–
–
IOH = 4 mA, VDDD 3 V
SID60
VOH
Output voltage high level
VDDD –0.5
–
–
IOH = 1 mA at 1.8 V VDDD
SID61
VOL
Output voltage low level
–
–
0.6
IOL = 4 mA at 1.8 V VDDD
SID62
VOL
Output voltage low level
–
–
0.6
IOL = 10 mA, VDDD 3 V
SID62A
VOL
Output voltage low level
–
–
0.4
IOL = 3 mA, VDDD 3 V
SID63
RPULLUP
Pull-up resistor
3.5
5.6
8.5
SID64
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
SID65
IIL
Input leakage current
(absolute value)
–
–
2
nA
SID66
CIN
Input capacitance
–
–
7
pF
SID67[4]
VHYSTTL
Input hysteresis LVTTL
25
40
–
SID68[4]
VHYSCMOS
Input hysteresis CMOS
0.05 × VDDD
–
–
200
–
–
Current through protection diode to
VDD/VSS
–
–
100
µA
–
Maximum total source or sink chip
current
–
–
200
mA
–
SID57
VIH[3]
SID58
Description
SID68A[4] VHYSCMOS5V5 Input hysteresis CMOS
SID69[4]
IDIODE
SID69A[4] ITOT_GPIO
Unit
Details/Conditions
CMOS Input
–
V
–
–
k
–
25 °C, VDDD = 3.0 V
–
VDDD 2.7 V
mV
VDD < 4.5 V
Notes
3. VIH must not exceed VDDD + 0.2 V.
4. Guaranteed by characterization.
Document Number: 002-00122 Rev. *N
Page 17 of 43
PSoC 4: PSoC 4100S Datasheet
Table 7. GPIO AC Specifications
(Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ
Max
Unit
SID70
TRISEF
Rise time in fast strong mode
2
–
12
SID71
TFALLF
Fall time in fast strong mode
2
–
12
SID72
TRISES
Rise time in slow strong mode
10
–
60
–
SID73
TFALLS
Fall time in slow strong mode
10
–
60
–
SID74
FGPIOUT1
GPIO FOUT; 3.3 V VDDD 5.5 V
Fast strong mode
–
–
33
SID75
FGPIOUT2
GPIO FOUT; 1.71 VVDDD3.3 V
Fast strong mode
–
–
16.7
SID76
FGPIOUT3
GPIO FOUT; 3.3 V VDDD 5.5 V
Slow strong mode
–
–
7
SID245
FGPIOUT4
GPIO FOUT; 1.71 V VDDD 3.3 V
Slow strong mode.
–
–
3.5
SID246
FGPIOIN
GPIO input operating frequency;
1.71 V VDDD 5.5 V
–
–
48
Min
Typ
Max
ns
MHz
Details/Conditions
3.3 V VDDD,
Cload = 25 pF
90/10%, 25 pF load,
60/40 duty cycle
90/10% VIO
XRES
Table 8. XRES DC Specifications
Spec ID
Parameter
Description
Unit
Details/Conditions
SID77
VIH
Input voltage high threshold
0.7 × VDDD
–
–
SID78
VIL
Input voltage low threshold
–
–
0.3 VDDD
SID79
RPULLUP
Pull-up resistor
–
60
–
kΩ
–
SID80
CIN
Input capacitance
–
–
7
pF
–
SID81[5]
VHYSXRES
Input voltage hysteresis
–
100
–
mV
SID82
IDIODE
Current through protection diode to
VDD/VSS
–
–
100
µA
V
CMOS Input
Typical hysteresis is
200 mV for VDD > 4.5 V
–
Table 9. XRES AC Specifications
Min
Typ
Max
Unit
Details/Conditions
SID83[5]
Spec ID
TRESETWIDTH
Parameter
Reset pulse width
Description
1
–
–
µs
–
BID194[5]
TRESETWAKE
Wake-up time from reset release
–
–
2.7
ms
–
Note
5. Guaranteed by characterization.
Document Number: 002-00122 Rev. *N
Page 18 of 43
PSoC 4: PSoC 4100S Datasheet
Analog Peripherals
Table 10. CTBm Opamp Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
µA
–
IDD
Opamp block current, External
load
SID269
IDD_HI
power = hi
–
1100
1850
SID270
IDD_MED
power = med
–
550
950
SID271
IDD_LOW
power = lo
–
150
350
GBW
Load = 20 pF, 0.1 mA
VDDA = 2.7 V
SID272
GBW_HI
power = hi
6
–
–
SID273
GBW_MED
power = med
3
–
–
SID274
GBW_LO
power = lo
–
1
–
IOUT_MAX
VDDA = 2.7 V, 500 mV from rail
SID275
IOUT_MAX_HI
power = hi
10
–
–
SID276
IOUT_MAX_MID
power = mid
10
–
–
SID277
IOUT_MAX_LO
power = lo
–
5
–
IOUT
VDDA = 1.71 V, 500 mV from rail
SID278
IOUT_MAX_HI
power = hi
4
–
–
SID279
IOUT_MAX_MID
power = mid
4
–
–
SID280
IOUT_MAX_LO
power = lo
–
2
–
IDD_Int
Opamp block current Internal
Load
SID269_I
IDD_HI_Int
power = hi
–
1500
1700
–
SID270_I
IDD_MED_Int
power = med
–
700
900
–
IDD_LOW_Int
power = lo
–
–
–
–
GBW
VDDA = 2.7 V
–
–
–
–
GBW_HI_Int
power = hi
8
–
–
SID271_I
SID272_I
–
–
MHz
Input and output are
0.2 V to VDDA-0.2 V
mA
Output is 0.5 V
VDDA-0.5 V
mA
Output is 0.5 V
VDDA-0.5 V
µA
MHz
Output is 0.25 V to
VDDA-0.25 V
General opamp specs for both
internal and external modes
SID281
VIN
Charge-pump on, VDDA = 2.7 V
–0.05
–
VDDA-0.2
SID282
VCM
Charge-pump on, VDDA = 2.7 V
–0.05
–
VDDA-0.2
VOUT
VDDA = 2.7 V
SID283
VOUT_1
power = hi, Iload = 10 mA
0.5
–
VDDA -0.5
SID284
VOUT_2
power = hi, Iload = 1 mA
0.2
–
VDDA -0.2
SID285
VOUT_3
power = med, Iload = 1 mA
0.2
–
VDDA -0.2
SID286
VOUT_4
power = lo, Iload = 0.1 mA
0.2
–
VDDA -0.2
Document Number: 002-00122 Rev. *N
V
–
–
–
V
–
–
–
Page 19 of 43
PSoC 4: PSoC 4100S Datasheet
Table 10. CTBm Opamp Specifications (continued)
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
High mode, input 0 V
to VDDA-0.2 V
SID288
VOS_TR
Offset voltage, trimmed
–1.0
0.5
1.0
SID288A
VOS_TR
Offset voltage, trimmed
–
1
–
SID288B
VOS_TR
Offset voltage, trimmed
–
2
–
Low mode, input 0 V
to VDDA-0.2 V
SID290
VOS_DR_TR
Offset voltage drift, trimmed
–10
3
10
High mode
SID290A
VOS_DR_TR
Offset voltage drift, trimmed
–
10
–
SID290B
VOS_DR_TR
Offset voltage drift, trimmed
–
10
–
Low mode
SID291
CMRR
DC
70
80
–
Input is 0 V to
VDDA-0.2 V, Output is
0.2 V to VDDA-0.2 V
mV
µV/°C
dB
SID292
PSRR
SID294
Medium mode, input
0 V to VDDA-0.2 V
Medium mode
VDDD = 3.6 V,
high-power mode,
input is 0.2 V to
VDDA-0.2 V
At 1 kHz, 10-mV ripple
70
85
–
VN2
Input-referred, 1 kHz, power = hi
–
72
–
SID295
VN3
Input-referred, 10 kHz,
power = hi
–
28
–
SID296
VN4
Input-referred, 100 kHz,
power = hi
–
15
–
SID297
CLOAD
Stable up to max. load.
Performance specs at 50 pF.
–
–
125
pF
–
SID298
SLEW_RATE
Cload = 50 pF, Power = High,
VDDA = 2.7 V
6
–
–
V/µs
–
SID299
T_OP_WAKE
From disable to enable, no
external RC dominating
–
–
25
µs
–
SID299A
OL_GAIN
Open Loop Gain
–
90
–
dB
–
COMP_MODE
Comparator mode; 50 mV drive,
Trise=Tfall (approx.)
SID300
TPD1
Response time; power = hi
–
150
–
SID301
TPD2
Response time; power = med
–
500
–
SID302
TPD3
Response time; power = lo
–
2500
–
SID303
VHYST_OP
Hysteresis
–
10
–
mV
–
SID304
WUP_CTB
Wake-up time from Enabled to
Usable
–
–
25
µs
–
Deep Sleep
Mode
Mode 2 is lowest current range.
Mode 1 has higher GBW.
Noise
Document Number: 002-00122 Rev. *N
Input and output are at
nV/rtHz 0.2 V to V
DDA-0.2 V
ns
Input is 0.2 V to
VDDA-0.2 V
Page 20 of 43
PSoC 4: PSoC 4100S Datasheet
Table 10. CTBm Opamp Specifications (continued)
Spec ID
Parameter
Typ
Max
Mode 1, High current
–
1400
–
Mode 1, Medium current
–
700
–
IDD_LOW_M1
Mode 1, Low current
–
200
–
SID_DS_4
IDD_HI_M2
Mode 2, High current
–
120
–
SID_DS_5
IDD_MED_M2
Mode 2, Medium current
–
60
–
SID_DS_6
IDD_LOW_M2
Mode 2, Low current
–
15
–
SID_DS_7
GBW_HI_M1
Mode 1, High current
–
4
–
SID_DS_8
GBW_MED_M1
Mode 1, Medium current
–
2
–
SID_DS_9
GBW_LOW_M1
Mode 1, Low current
–
0.5
–
SID_DS_10 GBW_HI_M2
SID_DS_11 GBW_MED_M2
Mode 2, High current
–
0.5
–
Mode 2, Medium current
–
0.2
–
SID_DS_12 GBW_Low_M2
SID_DS_1
IDD_HI_M1
SID_DS_2
IDD_MED_M1
SID_DS_3
Description
Min
Mode 2, Low current
–
0.1
–
SID_DS_13 VOS_HI_M1
SID_DS_14 VOS_MED_M1
Mode 1, High current
–
5
–
Mode 1, Medium current
–
5
–
SID_DS_15 VOS_LOW_M1
SID_DS_16 VOS_HI_M2
Mode 1, Low current
–
5
–
Mode 2, High current
–
5
–
SID_DS_17 VOS_MED_M2
Mode 2, Medium current
–
5
–
SID_DS_18 VOS_LOW_M2
SID_DS_19 IOUT_HI_M1
Mode 2, Low current
–
5
–
Mode 1, High current
–
10
–
SID_DS_20 IOUT_MED_M1
Mode 1, Medium current
–
10
–
SID_DS_21 IOUT_LOW_M1
Unit
µA
Details/Conditions
25 °C
MHz
20-pF load, no DC
load 0.2 V to
VDDA-0.2 V
mV
With trim 25 °C, 0.2 V
to VDDA-0.2 V
Output is 0.5 V to
VDDA-0.5 V
Mode 1, Low current
–
4
–
SID_DS_22 IOUT_HI_M2
SID_DS_23 IOUT_MED_M2
Mode 2, High current
–
1
–
Mode 2, Medium current
–
1
–
–
SID_DS_24 IOUT_LOW_M2
Mode 2, Low current
–
0.5
–
–
Description
Min
Typ
Max
mA
–
Table 11. Comparator DC Specifications
Spec ID
Parameter
SID84
VOFFSET1
Input offset voltage, Factory trim
–
–
±10
SID85
VOFFSET2
Input offset voltage, Custom trim
–
–
±4
SID86
VHYST
Hysteresis when enabled
–
10
35
SID87
VICM1
Input common mode voltage in
normal mode
0
–
VDDD-0.1
SID247
VICM2
Input common mode voltage in
low power mode
0
–
VDDD
SID247A
VICM3
Input common mode voltage in
ultra low power mode
0
–
VDDD-1.15
SID88
CMRR
Common mode rejection ratio
50
–
–
SID88A
CMRR
Common mode rejection ratio
42
–
–
Document Number: 002-00122 Rev. *N
Unit
Details/Conditions
–
mV
–
–
Modes 1 and 2
V
–
VDDD ≥ 2.2 V at –40 °C
dB
VDDD ≥ 2.7V
Page 21 of 43
PSoC 4: PSoC 4100S Datasheet
Table 11. Comparator DC Specifications (continued)
Min
Typ
Max
SID89
Spec ID
ICMP1
Parameter
Block current, normal mode
Description
–
–
400
SID248
ICMP2
Block current, low power mode
–
–
100
SID259
ICMP3
Block current in ultra low-power
mode
–
–
6
SID90
ZCMP
DC Input impedance of
comparator
35
–
–
Description
Min
Typ
Max
Response time, normal mode, 50
mV overdrive
–
38
110
Unit
Details/Conditions
–
µA
–
VDDD ≥ 2.2 V at –40 °C
MΩ
–
Unit
Details/Conditions
Table 12. Comparator AC Specifications
Spec ID
SID91
Parameter
TRESP1
–
ns
SID258
TRESP2
Response time, low power mode,
50 mV overdrive
–
70
200
SID92
TRESP3
Response time, ultra-low power
mode, 200 mV overdrive
–
2.3
15
Min
Typ
Max
Unit
–5
±1
5
°C
Min
Typ
Max
Unit
Details/Conditions
bits
–
–
µs
VDDD ≥ 2.2 V at –40 °C
Table 13. Temperature Sensor Specifications
Spec ID
SID93
Parameter
TSENSACC
Description
Temperature sensor accuracy
Details/Conditions
–40 to +85 °C
Table 14. SAR Specifications
Spec ID
Parameter
Description
SAR ADC DC Specifications
SID94
A_RES
Resolution
–
–
12
SID95
A_CHNLS_S
Number of channels - single
ended
–
–
16
SID96
A-CHNKS_D
Number of channels - differential
–
–
4
–
Diff inputs use neighboring I/O
SID97
A-MONO
Monotonicity
–
–
–
SID98
A_GAINERR
Gain error
–
–
±0.1
%
Yes
SID99
A_OFFSET
Input offset voltage
–
–
2
mV
SID100
A_ISAR
Current consumption
–
–
1
mA
SID101
A_VINS
Input voltage range - single
ended
VSS
–
VDDA
SID102
A_VIND
Input voltage range - differential[
VSS
–
VDDA
SID103
A_INRES
Input resistance
–
–
2.2
kΩ
–
SID104
A_INCAP
Input capacitance
–
–
10
pF
–
SID260
VREFSAR
Trimmed internal reference to
SAR
1.188
1.2
1.212
V
–
V
With external reference.
Measured with 1-V
reference
–
–
–
SAR ADC AC Specifications
SID106
A_PSRR
Power supply rejection ratio
70
–
–
SID107
A_CMRR
Common mode rejection ratio
66
–
–
Document Number: 002-00122 Rev. *N
dB
–
Measured at 1 V
Page 22 of 43
PSoC 4: PSoC 4100S Datasheet
Table 14. SAR Specifications (continued)
Min
Typ
Max
Unit
Details/Conditions
SID108
Spec ID
A_SAMP
Parameter
Sample rate
Description
–
–
1
Msps
–
SID109
A_SNR
Signal-to-noise and distortion
ratio (SINAD)
65
–
–
dB
FIN = 10 kHz
SID110
A_BW
Input bandwidth without aliasing
–
–
A_samp/2
kHz
–
SID111
A_INL
Integral non linearity. VDD = 1.71
to 5.5, 1 Msps
–1.7
–
2
SID111A
A_INL
Integral non linearity. VDDD = 1.71
to 3.6, 1 Msps
–1.5
–
1.7
SID111B
A_INL
Integral non linearity. VDD = 1.71
to 5.5, 500 ksps
–1.5
–
1.7
VREF = 1 to VDD
VREF = 1.71 to VDD
VREF = 1 to VDD
LSB
SID112
A_DNL
Differential non linearity.
VDD = 1.71 to 5.5, 1 Msps
–1
–
2.2
SID112A
A_DNL
Differential non linearity. VDD =
1.71 to 3.6, 1 Msps
–1
–
2
SID112B
A_DNL
Differential non linearity. VDD =
1.71 to 5.5, 500 ksps
–1
–
2.2
SID113
A_THD
Total harmonic distortion
–
–
–65
dB
FSARINTREF
SAR operating speed without
external ref. bypass
–
–
100
ksps
Min
Typ
Max
Unit
SID261
VREF = 1 to VDD
VREF = 1.71 to VDD
VREF = 1 to VDD
Fin = 10 kHz
12-bit resolution
CSD
Table 15. CSD and IDAC Specifications
Spec ID
SYS.PER#3
Parameter
VDD_RIPPLE
Description
Max allowed ripple on power
supply, DC to 10 MHz
–
–
±50
±25
VDD > 1.75V (with ripple),
25 °C TA,
Parasitic Capacitance (CP)
< 20 pF,
Sensitivity ≥ 0.4 pF
Maximum block current for
both IDACs in dynamic
(switching) mode including
comparators, buffer, and
reference generator.
mV
SYS.PER#16
VDD_RIPPLE_1.8
Max allowed ripple on power
supply, DC to 10 MHz
SID.CSD.BLK ICSD
Maximum block current
SID.CSD#15
–
–
–
–
4000
Voltage reference for CSD and
Comparator
0.6
1.2
VDDA - 0.6
SID.CSD#15A VREF_EXT
External Voltage reference for
CSD and Comparator
0.6
SID.CSD#16
IDAC1IDD
IDAC1 (7-bits) block current
–
–
1750
SID.CSD#17
IDAC2IDD
IDAC2 (7-bits) block current
–
–
1750
SID308
VCSD
Voltage range of operation
1.71
–
5.5
VCOMPIDAC
Voltage compliance range of
IDAC
SID308A
VREF
Document Number: 002-00122 Rev. *N
µA
V
0.6
VDDA - 0.6
–
Details/Conditions
VDD > 2 V (with ripple),
25 °C TA,
Sensitivity = 0.1 pF
VDDA –0.6
µA
VDDA – 0.6 or 4.4,
whichever is lower
VDDA – 0.6 or 4.4,
whichever is lower
–
–
1.8 V ±5% or 1.8 V to 5.5 V
V
VDDA – 0.6 or 4.4,
whichever is lower
Page 23 of 43
PSoC 4: PSoC 4100S Datasheet
Table 15. CSD and IDAC Specifications (continued)
Min
Typ
Max
SID309
Spec ID
IDAC1DNL
Parameter
DNL
Description
–1
–
1
Unit
Details/Conditions
SID310
IDAC1INL
INL
–2
–
2
SID311
IDAC2DNL
DNL
–1
–
1
SID312
IDAC2INL
INL
–2
–
2
INL is ±5.5 LSB for
VDDA < 2 V
SID313
SNR
Ratio of counts of finger to
noise. Guaranteed by characterization
5
–
–
Capacitance range of 5 to
Ratio 35 pF, 0.1-pF sensitivity.
All use cases. VDDA > 2 V.
SID314
IDAC1CRT1
Output current of IDAC1
(7 bits) in low range
4.2
–
5.4
LSB = 37.5-nA typ.
SID314A
IDAC1CRT2
Output current of IDAC1
(7 bits) in medium range
34
–
41
SID314B
IDAC1CRT3
Output current of IDAC1
(7 bits) in high range
275
–
330
LSB = 2.4-µA typ.
SID314C
IDAC1CRT12
Output current of IDAC1
(7 bits) in low range, 2X mode
8
–
10.5
LSB = 75-nA typ.
SID314D
IDAC1CRT22
Output current of IDAC1(7 bits)
in medium range, 2X mode
69
–
82
LSB = 600-nA typ.
SID314E
IDAC1CRT32
Output current of IDAC1(7 bits)
in high range, 2X mode
540
–
660
LSB = 4.8-µA typ.
SID315
IDAC2CRT1
Output current of IDAC2
(7 bits) in low range
4.2
–
5.4
LSB = 37.5-nA typ.
SID315A
IDAC2CRT2
Output current of IDAC2
(7 bits) in medium range
34
–
41
LSB = 300-nA typ.
SID315B
IDAC2CRT3
Output current of IDAC2
(7 bits) in high range
275
–
330
–
LSB
µA
INL is ±5.5 LSB for
VDDA < 2 V
–
LSB = 300-nA typ.
LSB = 2.4-µA typ.
µA
SID315C
IDAC2CRT12
Output current of IDAC2
(7 bits) in low range, 2X mode
8
–
10.5
LSB = 75-nA typ.
SID315D
IDAC2CRT22
Output current of IDAC2(7 bits)
in medium range, 2X mode
69
–
82
LSB = 600-nA typ.
SID315E
IDAC2CRT32
Output current of IDAC2(7 bits)
in high range, 2X mode
540
–
660
LSB = 4.8-µA typ.
SID315F
IDAC3CRT13
Output current of IDAC in
8-bit mode in low range
8
–
10.5
LSB = 37.5-nA typ.
SID315G
IDAC3CRT23
Output current of IDAC in
8-bit mode in medium range
69
–
82
LSB = 300-nA typ.
SID315H
IDAC3CRT33
Output current of IDAC in
8-bit mode in high range
540
–
660
LSB = 2.4-µA typ.
SID320
IDACOFFSET
All zeroes input
–
–
1
LSB
Polarity set by Source or
Sink. Offset is 2 LSBs for
37.5 nA/LSB mode
SID321
IDACGAIN
Full-scale error less offset
–
–
±10
%
–
Document Number: 002-00122 Rev. *N
Page 24 of 43
PSoC 4: PSoC 4100S Datasheet
Table 15. CSD and IDAC Specifications (continued)
Spec ID
Parameter
Min
Typ
Max
SID322
Mismatch between IDAC1 and
IDACMISMATCH1
IDAC2 in Low mode
Description
Unit
Details/Conditions
–
–
9.2
SID322A
IDACMISMATCH2
Mismatch between IDAC1 and
IDAC2 in Medium mode
–
–
5.6
SID322B
IDACMISMATCH3
Mismatch between IDAC1 and
IDAC2 in High mode
–
–
6.8
LSB = 2.4-µA typ.
SID323
IDACSET8
Settling time to 0.5 LSB for
8-bit IDAC
–
–
10
Full-scale transition.
No external load.
SID324
IDACSET7
Settling time to 0.5 LSB for
7-bit IDAC
–
–
10
SID325
CMOD
External modulator capacitor.
–
2.2
–
nF
5-V rating, X7R or NP0
cap.
LSB = 37.5-nA typ.
LSB
µs
LSB = 300-nA typ.
Full-scale transition.
No external load.
Table 16. 10-bit CapSense ADC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
bits
Auto-zeroing is required
every millisecond
SIDA94
A_RES
Resolution
–
–
10
SIDA95
A_CHNLS_S
Number of channels - single
ended
–
–
16
SIDA97
A-MONO
Monotonicity
–
–
–
Yes
SIDA98
A_GAINERR
Gain error
–
–
±2
%
In VREF (2.4 V) mode with
VDDA bypass
capacitance of 10 µF
SIDA99
A_OFFSET
Input offset voltage
–
–
3
mV
In VREF (2.4 V) mode with
VDDA bypass
capacitance of 10 µF
SIDA100
A_ISAR
Current consumption
–
–
0.25
mA
–
SIDA101
A_VINS
Input voltage range - single
ended
VSSA
–
VDDA
V
–
SIDA103
A_INRES
Input resistance
–
2.2
–
KΩ
–
SIDA104
A_INCAP
Input capacitance
–
20
–
pF
–
SIDA106
A_PSRR
Power supply rejection ratio
–
60
–
dB
SIDA107
A_TACQ
Sample acquisition time
–
1
–
A_CONV8
Conversion time for 8-bit
resolution at conversion rate =
Fhclk/(2^(N+2)). Clock
frequency = 48 MHz.
–
SIDA108
–
µs
A_CONV10
Conversion time for 10-bit
resolution at conversion rate =
Fhclk/(2^(N+2)). Clock
frequency = 48 MHz.
–
–
85.3
SIDA109
A_SND
Signal-to-noise and Distortion
ratio (SINAD)
–
61
–
SIDA110
A_BW
Input bandwidth without aliasing
–
–
22.4
–
In VREF (2.4 V) mode with
VDDA bypass
capacitance of 10 µF
–
21.3
SIDA108A
Document Number: 002-00122 Rev. *N
Defined by AMUX Bus
Does not include acquisition time. Equivalent to
44.8 ksps including acquisition time.
Does not include acquisition time. Equivalent to
11.6 ksps including acquisition time.
dB
With 10-Hz input sine wave,
external 2.4-V reference,
VREF (2.4 V) mode
KHz 8-bit resolution
Page 25 of 43
PSoC 4: PSoC 4100S Datasheet
Table 16. 10-bit CapSense ADC Specifications (continued)
Min
Typ
Max
SIDA111
Spec ID
A_INL
Parameter
Integral Non Linearity. 1 ksps
Description
–
–
2
SIDA112
A_DNL
Differential Non Linearity. 1 ksps
–
–
1
Unit
LSB
Details/Conditions
VREF = 2.4 V or greater
–
Digital Peripherals
Timer Counter Pulse-Width Modulator (TCPWM)
Table 17. TCPWM Specifications
Spec ID
Parameter
SID.TCPWM.1
ITCPWM1
SID.TCPWM.2
ITCPWM2
SID.TCPWM.2A ITCPWM3
Description
Block current consumption at 3 MHz
Block current consumption at 12 MHz
Block current consumption at 48 MHz
Min
–
–
–
Typ
–
–
–
Max
45
155
650
Unit
Details/Conditions
μA
All modes (TCPWM)
–
–
Fc
MHz
Fc max = CLK_SYS
Maximum = 48 MHz
SID.TCPWM.3
TCPWMFREQ
Operating frequency
SID.TCPWM.4
TPWMENEXT
Input trigger pulse width
2/Fc
–
–
For all trigger events[6]
SID.TCPWM.5
TPWMEXT
Output trigger pulse widths
2/Fc
–
–
Minimum possible width
of Overflow, Underflow,
and CC (Counter equals
Compare value) outputs
SID.TCPWM.5A TCRES
Resolution of counter
1/Fc
–
–
SID.TCPWM.5B PWMRES
PWM resolution
1/Fc
–
–
Minimum pulse width of
PWM Output
SID.TCPWM.5C QRES
Quadrature inputs resolution
1/Fc
–
–
Minimum pulse width
between Quadrature
phase inputs
Description
Min
Typ
Max
ns
Minimum time between
successive counts
I2C
Table 18. Fixed I2C DC Specifications[7]
Spec ID
Parameter
Unit
Details/Conditions
–
SID149
II2C1
Block current consumption at 100 kHz
–
–
50
SID150
II2C2
Block current consumption at 400 kHz
–
–
135
SID151
II2C3
Block current consumption at 1 Mbps
–
–
310
II2C4
I2C
–
–
1.4
Min
Typ
Max
Unit
Details/Conditions
–
–
1
Msps
–
Unit
Details/Conditions
µA
–
SID152
enabled in Deep Sleep mode
µA
–
–
Table 19. Fixed I2C AC Specifications[7]
Spec ID
SID153
Parameter
FI2C1
Description
Bit rate
Table 20. SPI DC Specifications[7]
Spec ID
Parameter
Description
Min
Typ
Max
SID163
ISPI1
Block current consumption at 1 Mbps
–
–
360
SID164
ISPI2
Block current consumption at 4 Mbps
–
–
560
SID165
ISPI3
Block current consumption at 8 Mbps
–
–
600
–
–
Notes
6. Trigger events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected.
7. Guaranteed by characterization.
Document Number: 002-00122 Rev. *N
Page 26 of 43
PSoC 4: PSoC 4100S Datasheet
Table 21. SPI AC Specifications[8]
Spec ID
SID166
Parameter
FSPI
Description
Min
Typ
Max
SPI Operating frequency (Master; 6X
Oversampling)
–
–
8
Unit
Details/Conditions
MHz SID166
Fixed SPI Master Mode AC Specifications
SID167
TDMO
MOSI Valid after SClock driving edge
–
–
15
–
SID168
TDSI
MISO Valid before SClock capturing
edge
20
–
–
SID169
THMO
Previous MOSI data hold time
0
–
–
Referred to Slave capturing
edge
–
ns
Full clock, late MISO
sampling
Fixed SPI Slave Mode AC Specifications
SID170
TDMI
MOSI Valid before Sclock Capturing
edge
40
–
–
SID171
TDSO
MISO Valid after Sclock driving edge
–
–
42 +
3*Tcpu
SID171A
TDSO_EXT
MISO Valid after Sclock driving edge
in Ext. Clk mode
–
–
48
SID172
THSO
Previous MISO data hold time
0
–
–
–
SID172A
TSSELSSCK
SSEL Valid to first SCK Valid edge
100
–
–
–
TCPU = 1/FCPU
ns
–
Table 22. UART DC Specifications[8]
Spec ID
SID160
SID161
Parameter
IUART1
IUART2
Min
Typ
Max
Block current consumption at
100 Kbps
Description
Unit
Details/Conditions
–
–
55
Block current consumption at
1000 Kbps
–
–
312
Min
Typ
Max
Unit
Details/Conditions
–
–
1
Mbps
–
–
µA
–
Table 23. UART AC Specifications[8]
Spec ID
SID162
Parameter
FUART
Description
Bit rate
Table 24. LCD Direct Drive DC Specifications[8]
Spec ID
Parameter
Description
Min
SID154
ILCDLOW
Operating current in low power
mode
–
SID155
CLCDCAP
LCD capacitance per
segment/common driver
–
SID156
LCDOFFSET
Long-term segment offset
–
SID157
ILCDOP1
LCD system operating current
Vbias = 5 V
–
LCD system operating current
Vbias = 3.3 V
–
SID158
ILCDOP2
Typ
Max
Unit
Details/Conditions
5
–
µA
500
5000
pF
–
20
–
mV
–
2
–
16 4 small segment disp. at
50 Hz
32 4 segments. 50 Hz. 25 °C
mA
2
–
32 4 segments. 50 Hz. 25 °C
Note
8. Guaranteed by characterization.
Document Number: 002-00122 Rev. *N
Page 27 of 43
PSoC 4: PSoC 4100S Datasheet
Table 25. LCD Direct Drive AC Specifications[10]
Spec ID
SID159
Parameter
FLCD
Description
Min
Typ
Max
Unit
Details/Conditions
10
50
150
Hz
–
Min
Typ
Max
Unit
Details/Conditions
1.71
–
5.5
V
–
Description
Min
Typ
Max
Unit
Details/Conditions
LCD frame rate
Memory
Table 26. Flash DC Specifications
Spec ID
SID173
Parameter
VPE
Description
Erase and program voltage
Table 27. Flash AC Specifications
Spec ID
Parameter
SID174
TROWWRITE[9]
Row (block) write time (erase and
program)
–
–
20
SID175
TROWERASE[9]
Row erase time
–
–
16
SID176
Row program time after erase
–
–
4
SID180[10]
TROWPROGRAM[9]
TBULKERASE[9]
TDEVPROG[9]
SID181[10]
FEND
Flash endurance
SID182[10]
FRET
Row (block) = 128 bytes
ms
–
–
Bulk erase time (64 KB)
–
–
35
Total device program time
–
–
7
Seconds
–
100 K
–
–
Cycles
–
Flash retention. TA 55 °C, 100 K
P/E cycles
20
–
–
SID182A[10] –
Flash retention. TA 85 °C, 10 K
P/E cycles
10
–
–
SID182B
–
Flash retention. TA 105 °C, 10K
P/E cycles, three years at TA ≥
85 °C
10
–
20
SID256
TWS48
Number of Wait states at 48 MHz
2
–
–
SID257
TWS24
Number of Wait states at 24 MHz
1
–
–
Min
Typ
Max
SID178
–
–
Years
–
Years
–
CPU execution from
Flash
System Resources
Power-on Reset (POR)
Table 28. Power On Reset (PRES)
Spec ID
Parameter
Description
SID.CLK#6 SR_POWER_UP Power supply slew rate
1
–
67
SID185[10]
VRISEIPOR
Rising trip voltage
0.80
–
1.5
SID186[10]
VFALLIPOR
Falling trip voltage
0.70
–
1.4
Unit
V/ms
V
Details/Conditions
At power-up and
power-down
–
–
Notes
9. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations may be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
10. Guaranteed by characterization.
Document Number: 002-00122 Rev. *N
Page 28 of 43
PSoC 4: PSoC 4100S Datasheet
Table 29. Brown-out Detect (BOD) for VCCD
Spec ID
Parameter
Description
SID190[11]
VFALLPPOR
BOD trip voltage in active and
sleep modes
SID192[11]
VFALLDPSLP
BOD trip voltage in Deep Sleep
Min
Typ
Max
1.48
–
1.62
1.11
–
1.5
Unit
Details/Conditions
–
V
–
SWD Interface
Table 30. SWD Interface Specifications
Spec ID
SID213
Parameter
F_SWDCLK1
Description
3.3 V VDD 5.5 V
Min
Typ
Max
–
–
14
Unit
MHz
1.71 V VDD 3.3 V
–
–
7
T_SWDI_SETUP T = 1/f SWDCLK
0.25*T
–
–
T_SWDI_HOLD
0.25*T
–
–
T_SWDO_VALID T = 1/f SWDCLK
–
–
0.5*T
T_SWDO_HOLD T = 1/f SWDCLK
1
–
–
SID214
F_SWDCLK2
SID215[11]
SID216[11]
SID217[11]
SID217A[11]
T = 1/f SWDCLK
Details/Conditions
SWDCLK ≤ 1/3
CPU clock
frequency
SWDCLK ≤ 1/3
CPU clock
frequency
–
ns
–
–
–
Internal Main Oscillator
Table 31. IMO DC Specifications
(Guaranteed by Design)
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
SID218
IIMO1
IMO operating current at 48 MHz
–
–
250
SID219
IIMO2
IMO operating current at 24 MHz
–
–
180
Min
Typ
Max
Unit
Details/Conditions
–
–
±2
%
–
FIMOTOL1
Frequency variation at 24, 32, and
48 MHz (trimmed)
–
–
±2.5
%
At 105 °C, 44-TQFP
and 32-QFN
packages
SID226
TSTARTIMO
IMO startup time
–
–
7
µs
–
SID228
TJITRMSIMO2
RMS jitter at 24 MHz
–
145
–
ps
–
Min
Typ
Max
Unit
Details/Conditions
–
0.3
1.05
µA
–
µA
–
–
Table 32. IMO AC Specifications
Spec ID
Parameter
Description
SID223
SID223A
Internal Low-Speed Oscillator
Table 33. ILO DC Specifications
(Guaranteed by Design)
Spec ID
SID231[11]
Parameter
IILO1
Description
ILO operating current
Note
11. Guaranteed by characterization.
Document Number: 002-00122 Rev. *N
Page 29 of 43
PSoC 4: PSoC 4100S Datasheet
Table 34. ILO AC Specifications
Min
Typ
Max
Unit
Details/Conditions
SID234[12]
Spec ID
TSTARTILO1
Parameter
ILO startup time
Description
–
–
2
ms
–
SID236[12]
TILODUTY
ILO duty cycle
40
50
60
%
–
SID237
FILOTRIM1
ILO frequency range
20
40
80
kHz
–
Min
Typ
Max
Unit
Details/Conditions
Table 35. Watch Crystal Oscillator (WCO) Specifications
Spec ID
Parameter
Description
SID398
FWCO
Crystal Frequency
–
32.768
–
kHz
SID399
FTOL
Frequency tolerance
–
50
250
ppm
–
SID400
ESR
Equivalent series resistance
–
50
–
kΩ
–
SID401
PD
Drive Level
–
–
1
µW
–
SID402
TSTART
Startup time
–
–
500
ms
–
SID403
CL
Crystal Load Capacitance
6
–
12.5
pF
–
SID404
C0
Crystal Shunt Capacitance
–
1.35
–
SID405
IWCO1
Operating Current (high power mode)
–
–
8
SID406
IWCO2
Operating Current (low power mode)
–
–
1
With 20-ppm crystal
–
A
–
–
Table 36. External Clock Specifications
Min
Typ
Max
Unit
Details/Conditions
SID305[12] ExtClkFreq
Spec ID
Parameter
External clock input frequency
0
–
48
MHz
–
SID306[12]
Duty cycle; measured at VDD/2
45
–
55
%
–
Min
Typ
Max
Unit
Details/Conditions
3
–
4
Periods
–
Min
Typ
Max
Unit
Details/Conditions
–
–
1.6
ns
–
ExtClkDuty
Description
Table 37. Block Specs
Spec ID
Parameter
SID262[12] TCLKSWITCH
Description
System clock source switching time
Table 38. Smart I/O Pass-through Time (Delay in Bypass Mode)
Spec ID
SID252
Parameter
PRG_BYPASS
Description
Max delay added by Smart I/O in
bypass mode
Note
12. Guaranteed by characterization.
Document Number: 002-00122 Rev. *N
Page 30 of 43
PSoC 4: PSoC 4100S Datasheet
Ordering Information
The marketing part numbers for the PSoC 4100S family are listed in the following table.
4125
4126
4145
SCB Blocks
Smart I/Os
GPIO
35-WLCSP
(0.35mm pitch)
0
1
0
2
5
2
8
31
X
2
1
1
0
2
5
2
16
31
X
CY8C4124LQI-S412(T)
24
16
4
2
1
1
0
2
5
2
16
27
CY8C4124LQI-S413(T)
24
16
4
2
1
1
0
2
5
2
16
34
CY8C4124AZI-S413(T)
24
16
4
2
1
1
0
2
5
2
16
36
CY8C4124FNI-S433(T)
24
16
4
2
1
1
1
806 ksps
2
5
2
16
31
CY8C4124LQI-S432(T)
24
16
4
2
1
1
1
806 ksps
2
5
2
16
27
CY8C4124LQI-S433(T)
24
16
4
2
1
1
1
806 ksps
2
5
2
16
34
CY8C4124AZI-S433(T)
24
16
4
2
1
1
1
806 ksps
2
5
2
16
36
CY8C4125FNI-S423(T)
24
32
4
2
0
1
1
806 ksps
2
5
2
16
31
CY8C4125LQI-S422(T)
24
32
4
2
0
1
1
806 ksps
2
5
2
16
27
CY8C4125LQI-S423(T)
24
32
4
2
0
1
1
806 ksps
2
5
2
16
34
CY8C4125AZI-S423(T)
24
32
4
2
0
1
1
806 ksps
2
5
2
16
36
CY8C4125AXI-S423
24
32
4
2
0
1
1
806 ksps
2
5
2
16
36
Temperature
Range (°C)
TCPWM Blocks
2
4
44-TQFP
LP Comparators
4
16
48-TQFP
12-bit SAR
ADC
16
24
40-QFN
10-bit
CSD ADC
24
CY8C4124FNI-S413(T)
32-QFN
CSD
CY8C4124FNI-S403(T)
MPN
ADC Sample
Rate
SRAM (KB)
Opamp (CTBm)
4124
Flash (KB)
Category
Package
Max CPU
Speed (MHz)
Features
–40 to 85 °C
–40 to 85 °C
X
–40 to 85 °C
X
–40 to 85 °C
X
–40 to 85 °C
X
–40 to 85 °C
X
–40 to 85 °C
X
–40 to 85 °C
X
–40 to 85 °C
X
–40 to 85 °C
X
–40 to 85 °C
X
–40 to 85 °C
X
–40 to 85 °C
X
CY8C4125FNI-S413(T)
24
32
4
2
1
1
0
2
5
2
16
31
CY8C4125LQI-S412(T)
24
32
4
2
1
1
0
2
5
2
16
27
X
CY8C4125LQI-S413(T)
24
32
4
2
1
1
0
2
5
2
16
34
CY8C4125AZI-S413(T)
24
32
4
2
1
1
0
2
5
2
16
36
CY8C4125FNI-S433(T)
24
32
4
2
1
1
1
806 ksps
2
5
2
16
31
CY8C4125LQI-S432
24
32
4
2
1
1
1
806 ksps
2
5
2
16
27
X
X
–40 to 85 °C
–40 to 85 °C
X
–40 to 85 °C
X
–40 to 85 °C
X
–40 to 85 °C
X
–40 to 85 °C
–40 to 85 °C
CY8C4125LQQ-S432
24
32
4
2
1
1
1
806 ksps
2
5
2
16
27
CY8C4125LQI-S433
24
32
4
2
1
1
1
806 ksps
2
5
2
16
34
–40 to 105 °C
CY8C4125AZI-S433(T)
24
32
4
2
1
1
1
806 ksps
2
5
2
16
36
X
–40 to 85 °C
CY8C4125AZQ-S433
24
32
4
2
1
1
1
806 ksps
2
5
2
16
36
X
–40 to 105 °C
X
–40 to 85 °C
CY8C4125AXI-S433
24
32
4
2
1
1
1
806 ksps
2
5
2
16
36
CY8C4126AZI-S423(T)
24
64
8
2
0
1
1
806 ksps
2
5
3
16
36
X
X
–40 to 85 °C
CY8C4126AZQ-S423
24
64
8
2
0
1
1
806 ksps
2
5
3
16
36
X
–40 to 105 °C
CY8C4126AXI-S423
24
64
8
2
0
1
1
806 ksps
2
5
3
16
36
CY8C4126AZI-S433(T)
24
64
8
2
1
1
1
806 ksps
2
5
3
16
36
X
–40 to 85 °C
CY8C4126AZQ-S433
24
64
8
2
1
1
1
806 ksps
2
5
3
16
36
X
–40 to 105 °C
CY8C4126AXI-S433
24
64
8
2
1
1
1
806 ksps
2
5
3
16
36
X
–40 to 85 °C
CY8C4126AXQ-S433
24
64
8
2
1
1
1
806 ksps
2
5
3
16
36
X
–40 to 105 °C
X
–40 to 85 °C
–40 to 85 °C
CY8C4145AZI-S423(T)
48
32
4
2
0
1
1
1 Msps
2
5
2
16
36
X
–40 to 85 °C
CY8C4145AZQ-S433
48
32
4
2
1
1
1
1 Msps
2
5
2
16
36
X
–40 to 105 °C
CY8C4145AXI-S423
48
32
4
2
0
1
1
1 Msps
2
5
2
16
36
X
–40 to 85 °C
CY8C4145AXI-S433
48
32
4
2
1
1
1
1 Msps
2
5
2
16
36
X
–40 to 85 °C
CY8C4145AXQ-S433
48
32
4
2
1
1
1
1 Msps
2
5
2
16
36
X
–40 to 105 °C
Document Number: 002-00122 Rev. *N
Page 31 of 43
PSoC 4: PSoC 4100S Datasheet
4146
1
1 Msps
2
5
3
16
31
X
1
1
1 Msps
2
5
3
16
27
X
X
CY8C4146LQQ-S422(T)
48
64
8
2
0
1
1
1 Msps
2
5
3
16
27
CY8C4146LQI-S423(T)
48
64
8
2
0
1
1
1 Msps
2
5
3
16
34
Temperature
Range (°C)
GPIO
35-WLCSP
(0.35mm pitch)
1
0
44-TQFP
ADC Sample
Rate
0
2
48-TQFP
12-bit SAR
ADC
2
8
40-QFN
10-bit
CSD ADC
8
64
32-QFN
CSD
64
48
Smart I/Os
SRAM (KB)
Opamp (CTBm)
48
CY8C4146LQI-S422(T)
SCB Blocks
Flash (KB)
CY8C4146FNI-S423(T)
MPN
TCPWM Blocks
Max CPU
Speed (MHz)
Category
Package
LP Comparators
Features
–40 to 85 °C
–40 to 85 °C
–40 to 105 °C
X
–40 to 85 °C
CY8C4146AZI-S423(T)
48
64
8
2
0
1
1
1 Msps
2
5
3
16
36
X
–40 to 85 °C
CY8C4146AZQ-S423
48
64
8
2
0
1
1
1 Msps
2
5
3
16
36
X
–40 to 105 °C
CY8C4146AXI-S423
48
64
8
2
0
1
1
1 Msps
2
5
3
16
36
X
–40 to 85 °C
CY8C4146AXQ-S423
48
64
8
2
0
1
1
1 Msps
2
5
3
16
36
X
–40 to 105 °C
CY8C4146FNI-S433(T)
48
64
8
2
1
1
1
1 Msps
2
5
3
16
31
CY8C4146LQI-S432(T)
48
64
8
2
1
1
1
1 Msps
2
5
3
16
27
X
X
CY8C4146LQQ-S432(T)
48
64
8
2
1
1
1
1 Msps
2
5
3
16
27
CY8C4146LQI-S433(T)
48
64
8
2
1
1
1
1 Msps
2
5
3
16
34
X
–40 to 85 °C
–40 to 85 °C
–40 to 105 °C
X
–40 to 85 °C
CY8C4146AZI-S433(T)
48
64
8
2
1
1
1
1 Msps
2
5
3
16
36
X
–40 to 85 °C
CY8C4146AZQ-S433
48
64
8
2
1
1
1
1 Msps
2
5
3
16
36
X
–40 to 105 °C
CY8C4146AXI-S433
48
64
8
2
1
1
1
1 Msps
2
5
3
16
36
X
–40 to 85 °C
CY8C4146AXQ-S433
48
64
8
2
1
1
1
1 Msps
2
5
3
16
36
X
–40 to 105 °C
Document Number: 002-00122 Rev. *N
Page 32 of 43
PSoC 4: PSoC 4100S Datasheet
The nomenclature used in the preceding table is based on the following part numbering convention:
Field
CY8C
Description
Values
Meaning
Cypress Prefix
4
Architecture
4
PSoC 4
A
Family
1
4100 Family
B
CPU Speed
2
24 MHz
4
48 MHz
4
16 KB
5
32 KB
6
64 KB
7
128 KB
C
DE
F
S
Flash Capacity
Package Code
Temperature Range
Series Designator
XYZ
Attributes Code
T
Package Type
AX
TQFP (0.8mm pitch)
AZ
TQFP (0.5mm pitch)
LQ
QFN
PV
SSOP
FN
CSP
I
Industrial
Q
Extended Industrial
S
S-Series
M
M-Series
L
L-Series
000-999
Code of feature set in the specific family
Tray
T
Tape and Reel
The following is an example of a part number.
Example
CY8C
4
A
B
C
DE
F
– S
XYZ
T
Cypress Prefix
4: PSoC 4
1: 4100 Family
Architecture
Family within Architecture
4: 48 MHz
CPU Speed
5: 32 KB
Flash Capacity
AZ: TQFP
Package Code
I: Industrial
Temperature Range
Series Designator
Attributes Code
Package Type
Document Number: 002-00122 Rev. *N
Page 33 of 43
PSoC 4: PSoC 4100S Datasheet
Packaging
The PSoC 4100S is offered in 48-pin TQFP, 44-pin TQFP, 40-pin QFN, 32-pin QFN, and 35-ball WLCSP packages.
Table 39 provides the package dimensions and Cypress drawing numbers.
Table 39. Package List
Spec ID
Package
Description
Package Dwg
BID20
48-pin TQFP
7 × 7 × 1.4-mm height with 0.5-mm pitch
51-85135
BID20A
44-pin TQFP
10 × 10 × 1.6-mm height with 0.8-mm pitch
51-85064
BID27
40-pin QFN
6 × 6 × 0.6-mm height with 0.5-mm pitch
001-80659
BID34A
32-pin QFN
5 × 5 × 0.6-mm height with 0.5-mm pitch
001-42168
BID34D
35-ball WLCSP
2.6 × 2.1 × 0.48-mm height with 0.35-mm pitch
002-09958
Table 40. Package Thermal Characteristics
Parameter
Description
Package
Min
Typ
Max
Unit
Details/Conditions
TA
Operating ambient temperature
–
–40
25
105
TJ
Operating junction temperature
–
–40
–
125
–
TJA
Package θJA
48-pin TQFP
–
74.8
–
–
TJC
Package θJC
48-pin TQFP
–
35.7
–
–
TJA
Package θJA
44-pin TQFP
–
57.2
–
–
TJC
Package θJC
44-pin TQFP
–
17.5
–
–
TJA
Package θJA
40-pin QFN
–
17.8
–
TJC
Package θJC
40-pin QFN
–
2.8
–
TJA
Package θJA
32-pin QFN
–
19.9
–
–
TJC
Package θJC
32-pin QFN
–
4.3
–
–
TJA
Package θJA
35-ball WLCSP
–
43
–
–
TJC
Package θJC
35-ball WLCSP
–
0.3
–
–
°C
–
–
°C/Watt
–
Table 41. Solder Reflow Peak Temperature
Package
Maximum Peak Temperature
Maximum Time at Peak Temperature
All
260 °C
30 seconds
Table 42. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-020
Package
MSL
All except WLCSP
MSL 3
35-ball WLCSP
MSL 1
Document Number: 002-00122 Rev. *N
Page 34 of 43
PSoC 4: PSoC 4100S Datasheet
Package Diagrams
Figure 8. 48-pin TQFP Package Outline
51-85135 *C
Figure 9. 44-pin TQFP Package Outline
51-85064 *G
Document Number: 002-00122 Rev. *N
Page 35 of 43
PSoC 4: PSoC 4100S Datasheet
Figure 10. 40-pin QFN Package Outline
001-80659 *A
Document Number: 002-00122 Rev. *N
Page 36 of 43
PSoC 4: PSoC 4100S Datasheet
Figure 11. 32-pin QFN Package Outline
SEE NOTE 1
TOP VIEW
BOTTOM VIEW
SIDE VIEW
DIMENSIONS
A
A1
Document Number: 002-00122 Rev. *N
HATCH AREA IS SOLDERABLE EXPOSED PAD
MIN.
NOM.
MAX.
0.50
0.55
0.60
3. PACKAGE WEIGHT: 0.0388g
0.045
4. DIMENSIONS ARE IN MILLIMETERS
-
A2
0.020
2. BASED ON REF JEDEC # MO-248
0.15 BSC
D
4.90
5.00
5.10
D2
3.40
3.50
3.60
E
4.90
5.00
5.10
E2
3.40
3.50
3.60
L
0.30
0.40
0.50
b
0.18
0.25
0.30
e
NOTES:
1.
SYMBOL
001-42168 *F
0.50 TYP
Page 37 of 43
PSoC 4: PSoC 4100S Datasheet
Figure 12. 35-Ball WLCSP Package Outline
1
2
3
4
5
6
7
7
6
5
4
3
2
1
A
A
B
B
C
C
D
D
E
E
NOTES:
DIMENSIONS
SYMBOL
MIN.
NOM.
MAX.
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. JEDEC PUBLICATION 95; DESIGN GUIDE 4.18.
A
-
-
0.482
A1
0.141
0.157
0.173
D
2.557
2.582
2.607
E
2.072
2.097
2.122
D1
2.10 BSC
E1
1.40 BSC
MD
7
ME
5
N
35
b
0.19
0.22
0.25
eD
-
0.35
-
eE
-
0.35
-
SD
0
SE
0.02 BSC
Document Number: 002-00122 Rev. *N
002-09958 *D
Page 38 of 43
PSoC 4: PSoC 4100S Datasheet
Acronyms
Table 43. Acronyms Used in this Document
Acronym
Description
abus
analog local bus
ADC
analog-to-digital converter
AG
analog global
AHB
AMBA (advanced microcontroller bus
architecture) high-performance bus, an Arm data
transfer bus
Table 43. Acronyms Used in this Document (continued)
Acronym
Description
ESD
electrostatic discharge
ETM
embedded trace macrocell
FIR
finite impulse response, see also IIR
FPB
flash patch and breakpoint
FS
full-speed
GPIO
general-purpose input/output, applies to a PSoC
pin
ALU
arithmetic logic unit
AMUXBUS
analog multiplexer bus
HVI
high-voltage interrupt, see also LVI, LVD
API
application programming interface
IC
integrated circuit
APSR
application program status register
IDAC
current DAC, see also DAC, VDAC
Arm®
advanced RISC machine, a CPU architecture
IDE
integrated development environment
ATM
automatic thump mode
I2C, or IIC
BW
bandwidth
Inter-Integrated Circuit, a communications
protocol
Controller Area Network, a communications
protocol
IIR
infinite impulse response, see also FIR
CAN
ILO
internal low-speed oscillator, see also IMO
internal main oscillator, see also ILO
CMRR
common-mode rejection ratio
IMO
CPU
central processing unit
INL
integral nonlinearity, see also DNL
CRC
cyclic redundancy check, an error-checking
protocol
I/O
input/output, see also GPIO, DIO, SIO, USBIO
IPOR
initial power-on reset
DAC
digital-to-analog converter, see also IDAC,
VDAC
IPSR
interrupt program status register
DFB
digital filter block
IRQ
interrupt request
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
ITM
instrumentation trace macrocell
DIO
DMIPS
Dhrystone million instructions per second
DMA
direct memory access, see also TD
DNL
differential nonlinearity, see also INL
DNU
do not use
DR
port write data registers
DSI
digital system interconnect
DWT
data watchpoint and trace
ECC
error correcting code
ECO
external crystal oscillator
EEPROM
electrically erasable programmable read-only
memory
LCD
liquid crystal display
LIN
Local Interconnect Network, a communications
protocol.
LR
link register
LUT
lookup table
LVD
low-voltage detect, see also LVI
LVI
low-voltage interrupt, see also HVI
LVTTL
low-voltage transistor-transistor logic
MAC
multiply-accumulate
MCU
microcontroller unit
MISO
master-in slave-out
NC
no connect
nonmaskable interrupt
EMI
electromagnetic interference
NMI
EMIF
external memory interface
NRZ
non-return-to-zero
EOC
end of conversion
NVIC
nested vectored interrupt controller
EOF
end of frame
NVL
nonvolatile latch, see also WOL
execution program status register
opamp
operational amplifier
EPSR
Document Number: 002-00122 Rev. *N
Page 39 of 43
PSoC 4: PSoC 4100S Datasheet
Table 43. Acronyms Used in this Document (continued)
Acronym
Description
Table 43. Acronyms Used in this Document (continued)
Acronym
Description
PAL
programmable array logic, see also PLD
SWD
serial wire debug, a test protocol
PC
program counter
SWV
single-wire viewer
PCB
printed circuit board
TD
transaction descriptor, see also DMA
PGA
programmable gain amplifier
THD
total harmonic distortion
PHUB
peripheral hub
TIA
transimpedance amplifier
PHY
physical layer
TRM
technical reference manual
PICU
port interrupt control unit
TTL
transistor-transistor logic
PLA
programmable logic array
TX
transmit
PLD
programmable logic device, see also PAL
PLL
phase-locked loop
UART
Universal Asynchronous Transmitter Receiver, a
communications protocol
PMDD
package material declaration data sheet
POR
power-on reset
PRES
precise power-on reset
PRS
pseudo random sequence
PS
port read data register
PSoC®
Programmable System-on-Chip™
PSRR
power supply rejection ratio
PWM
pulse-width modulator
RAM
random-access memory
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
RTL
register transfer language
RTR
remote transmission request
RX
receive
SAR
successive approximation register
SC/CT
switched capacitor/continuous time
SCL
I2C serial clock
SDA
I2C serial data
S/H
sample and hold
SINAD
signal to noise and distortion ratio
SIO
special input/output, GPIO with advanced
features. See GPIO.
SOC
start of conversion
SOF
start of frame
SPI
Serial Peripheral Interface, a communications
protocol
SR
slew rate
SRAM
static random access memory
SRES
software reset
Document Number: 002-00122 Rev. *N
UDB
universal digital block
USB
Universal Serial Bus
USBIO
USB input/output, PSoC pins used to connect to
a USB port
VDAC
voltage DAC, see also DAC, IDAC
WDT
watchdog timer
WOL
write once latch, see also NVL
WRES
watchdog timer reset
XRES
external reset I/O pin
XTAL
crystal
Page 40 of 43
PSoC 4: PSoC 4100S Datasheet
Document Conventions
Units of Measure
Table 44. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
dB
decibel
fF
femto farad
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohour
kHz
kilohertz
k
kilo ohm
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
M
mega-ohm
Msps
megasamples per second
µA
microampere
µF
microfarad
µH
microhenry
µs
microsecond
µV
microvolt
µW
microwatt
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
nV
nanovolt
ohm
pF
picofarad
ppm
parts per million
ps
picosecond
s
second
sps
samples per second
sqrtHz
square root of hertz
V
volt
Document Number: 002-00122 Rev. *N
Page 41 of 43
PSoC 4: PSoC 4100S Datasheet
Revision History
Description Title: PSoC 4: PSoC 4100S Datasheet Programmable System-on-Chip (PSoC)
Document Number: 002-00122
Submission
Revision
ECN
Description of Change
Date
**
4883809
08/28/2015 New datasheet
Updated Pinouts.
Added VDDD ≥ 2.2V at –40 °C under Conditions for specs SID247A, SID90, SID92.
*A
4992376
10/30/2015
Updated Table 16.
Updated Ordering Information.
*B
5037826
12/08/2015 Changed datasheet status to Preliminary
Updated SCBs from 2 to 3.
Updated SRAM size to 8 KB.
*C
5060691
12/22/2015 Changed WLCSP package to 35-ball WLCSP.
Updated Pin List and Alternate Pin Functions.
Updated Ordering Information.
Added Errata.
Added 35 WLCSP package details.
*D
5139206
02/16/2016
Updated theta JA and JC values for all packages.
Updated copyright information at the end of the document.
Updated values for SID79, BID194. SID175, and SID176.
*E
5173961
03/15/2016 Updated CSD and IDAC Specifications.
Updated 10-bit CapSense ADC Specifications.
Updated CSD and IDAC Specifications.
*F
5330930
07/27/2016 Updated 10-bit CapSense ADC Specifications.
Removed errata.
*G
5473409
10/13/2016 Added 44 TQFP pin and package details.
Updated Figure 5.
Changed PRGIO references to Smart I/O.
*H
5561833
01/09/2017
Updated DC Specifications.
Updated Ordering Information.
Updated 35-ball WLCSP package diagram.
*I
5713158
04/26/2017
Updated the Cypress logo.
Updated Sales page.
Updated Features.
Updated Development Ecosystem.
*J
6069924
02/14/2018 Updated Ordering Information.
Updated Figure 3 and Figure 4.
Updated Figure 11 in Packaging (spec 001-42168 *E to *F).
Updated Table 2.
*K
6120525
04/03/2018 Updated Clock Diagram to show Watchdog details and clock divider information
Updated 32-bit MCU subsystem feature list.
Corrected typo in the block diagram.
Updated Watch Crystal Oscillator (WCO).
*L
6348123
10/30/2018 Corrected typos in CTBm Opamp Specifications.
Updated values for SID260.
Updated Conditions for SID.CSD#15, SID.CSD#15A, and SID308A.
Updated min and max values for SID172A.
Added extended industrial temperature range.
*M
6585507
07/05/2019
Added SID182B parameter.
Added ModusToolbox™ in Features.
Updated PSoC Creator.
Added ModusToolbox™ Software.
*N
7021633
11/10/2020
Updated Table 27: Updated SID182B.
Updated Table 32: Added SID223A.
Updated Ordering Information.
Document Number: 002-00122 Rev. *N
Page 42 of 43
PSoC 4: PSoC 4100S Datasheet
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Arm® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Community | Code Examples | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2015-2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries ("Cypress"). This document, including any software or
firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce
the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or
indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by
Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, "Security
Breach"). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the
responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. "High-Risk Device"
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. "Critical Component" means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-00122 Rev. *N
Revised November 10, 2020
Page 43 of 43
工商网监
湘ICP备2023018690号
