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Automotive PSoC® 4: PSoC 4100
Family Datasheet
®
Programmable System-on-Chip (PSoC )
Programmable System-on-Chip (PSoC®)
General Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of mixed-signal programmable embedded system
controllers with an ARM® Cortex™-M0 CPU, while being AEC-Q100 compliant. It combines programmable and re-configurable analog
and digital blocks with flexible automatic routing. The PSoC 4100 product family, based on this platform, is a combination of a
microcontroller with digital programmable logic, high-performance analog-to-digital conversion, opamp with Comparator mode, and
standard communication and timing peripherals. The PSoC 4100 products will be fully upward compatible with members of the PSoC 4
platform for new applications and design needs. The programmable analog and digital subsystems allow flexibility and in-field tuning
of the design.
Features
32-bit MCU Sub-system
Serial Communication
■
Automotive Electronics Council (AEC) AEC-Q100 qualified
■
24 MHz ARM Cortex-M0 CPU with single-cycle multiply
■
Up to 32 kB of flash with Read Accelerator
■
Up to 4 kB of SRAM
■
Two
independent
run-time
reconfigurable
serial
communication blocks (SCBs) with reconfigurable I2C, SPI,
UART, or LIN Slave 1.3, 2.1/2.2 functionality
Timing and Pulse-Width Modulation
Programmable Analog
■
One opamp with reconfigurable high-drive external and
high-bandwidth internal drive, Comparator mode, and ADC
input buffering capability
■
12-bit, 806 Ksps SAR ADC with differential and single-ended
modes and Channel Sequencer with signal averaging
■
Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
■
Two low-power comparators that operate in Deep Sleep
Low Power 1.71 V to 5.5 V operation
■
Four 16-bit Timer/Counter Pulse-Width Modulator (TCPWM)
blocks
■
Center-aligned, Edge, and Pseudo-random modes
■
Comparator-based triggering of Kill signals for motor drive and
other high reliability digital logic applications
Up to 24 Programmable GPIOs
■
28-pin SSOP package
■
Any GPIO pin can be CapSense, LCD, analog, or digital
■
Drive modes, strengths, and slew rates are programmable
■
20 nA Stop Mode with GPIO pin wakeup
Temperature Ranges:
■
Hibernate and Deep Sleep modes allow wakeup-time versus
power trade-offs
■
A Grade: –40 °C to +85 °C
■
S Grade: –40 °C to +105 °C
Capacitive Sensing
■
Cypress Capacitive Sigma-Delta (CSD) provides best-in-class
SNR (>5:1) and water tolerance
■
Cypress supplied software component makes capacitive
sensing design easy
■
Automatic hardware tuning (SmartSense™)
Segment LCD Drive
■
Integrated Development Environment provides schematic
design entry and build (with analog and digital automatic
routing)
■
Applications Programming Interface (API Component) for all
fixed-function and programmable peripherals
Industry Standard Tool Compatibility
■
LCD drive supported on all pins (common or segment)
■
Operates in Deep Sleep mode with 4 bits per pin memory
Cypress Semiconductor Corporation
Document Number: 001-93576 Rev. *F
PSoC Creator Design Environment
•
■
198 Champion Court
After schematic entry, development can be done with
ARM-based industry-standard development tools
•
San Jose, CA 95134-1709
•
408-943-2600
Revised May 26, 2017
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Contents
Block Diagram .................................................................. 3
Functional Description ..................................................... 3
Functional Overview ........................................................ 4
CPU and Memory Subsystem ..................................... 4
System Resources ...................................................... 4
Analog Blocks .............................................................. 5
Fixed Function Digital .................................................. 6
GPIO ........................................................................... 7
Special Function Peripherals ....................................... 7
Pinouts .............................................................................. 8
Power ............................................................................... 10
Unregulated External Supply ..................................... 10
Regulated External Supply ........................................ 10
Development Support .................................................... 11
Documentation .......................................................... 11
Online ........................................................................ 11
Tools .......................................................................... 11
Electrical Specifications ................................................ 12
Absolute Maximum Ratings ....................................... 12
Document Number: 001-93576 Rev. *F
Device-Level Specifications ...................................... 13
Analog Peripherals .................................................... 17
Digital Peripherals ..................................................... 21
Memory ..................................................................... 24
System Resources .................................................... 24
Ordering Information ...................................................... 28
Part Numbering Conventions .................................... 28
Packaging ........................................................................ 29
Acronyms ........................................................................ 31
Document Conventions ................................................. 33
Units of Measure ....................................................... 33
Document History Page ................................................. 34
Sales, Solutions, and Legal Information ...................... 37
Worldwide Sales and Design Support ....................... 37
Products .................................................................... 37
PSoC® Solutions ...................................................... 37
Cypress Developer Community ................................. 37
Technical Support ..................................................... 37
Page 2 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Block Diagram
CPU Subsystem
PSoC 4100
SW D
32-bit
AH B -Lite
C ortex
M0
24 M H z
FLASH
U p to 32 kB
SR AM
U p to 4 kB
ROM
4 kB
FAST M U L
N VIC , IR Q M X
R ead Accelerator
SR AM C ontroller
R O M C ontroller
System R esources
System Interconnect (Single Layer AHB)
Peripherals
Test
D FT Logic
D FT Analog
x1
SM X
CTBm
x1
1x O pAm p
2x LP Comparator
R eset
R eset C ontrol
XR ES
SAR AD C
(12-bit)
Capsense
IOSS GPIO (5x ports)
Program m able
Analog
LCD
C lock
C lock C ontrol
WDT
IM O
ILO
2x SCB-I2C/SPI/UART
Peripheral Interconnect (M M IO)
PC LK
4x TCPWM
Pow er
Sleep C ontrol
W IC
PO R
LVD
R EF
BO D
PW R SYS
N VLatches
Port Interface & D igital System Interconnect (D SI)
H igh Speed I/O M atrix
Pow er M odes
Active/Sleep
D eep Sleep
H ibernate
24x G PIO s
I/O Subsystem
Functional Description
PSoC 4100 devices include extensive support for programming,
testing, debugging, and tracing both hardware and firmware.
The ARM Serial_Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator Integrated Development Environment (IDE)
provides fully integrated programming and debug support for
PSoC 4100 devices. The SWD interface is fully compatible with
industry standard third party tools. With the ability to disable
debug features, with very robust flash protection, and by allowing
customer-proprietary functionality to be implemented in on-chip
Document Number: 001-93576 Rev. *F
programmable blocks, the PSoC 4100 family provides a level of
security not possible with multi-chip application solutions or with
microcontrollers.
The debug circuits are enabled by default and can only be
disabled in firmware. If not enabled, the only way to re-enable
them is to erase the entire device, clear flash protection, and
reprogram the device with new firmware that enables debugging.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. Because all programming, debug, and test
interfaces are disabled when maximum device security is
enabled, PSoC 4100 with device security enabled may not be
returned for failure analysis. This is a trade-off the PSoC 4100
allows the customer to make.
Page 3 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Functional Overview
System Resources
CPU and Memory Subsystem
Power System
CPU
The Cortex-M0 CPU in PSoC 4100 is part of the 32-bit MCU
subsystem, which is optimized for low power operation with
extensive clock gating. It mostly uses 16-bit instructions and
executes a subset of the Thumb-2 instruction set. This enables
fully compatible binary upward migration of the code to higher
performance processors such as the Cortex-M3 and M4, thus
enabling upward compatibility. The Cypress implementation
includes a hardware multiplier that provides a 32-bit result in one
cycle. It includes a nested vectored interrupt controller (NVIC)
block with 32 interrupt inputs and also includes a Wakeup
Interrupt Controller (WIC), which can wake the processor up
from Deep Sleep mode allowing power to be switched off to the
main processor when the chip is in Deep Sleep mode. The
Cortex-M0 CPU provides a Non-Maskable Interrupt input (NMI),
which is made available to the user when it is not in use for
system functions requested by the user.
The CPU also includes a debug interface, the Serial Wire Debug
(SWD) interface, which is a 2-wire form of JTAG; the debug
configuration used for PSoC 4100 has four break-point (address)
comparators and two watchpoint (data) comparators.
The power system is described in detail in the section Power on
page 10. It provides assurance that voltage levels are as
required for each respective mode and either delay mode entry
(on power-on reset (POR), for example) until voltage levels are
as required for proper function or generate resets (brown-out
detect (BOD)) or interrupts (low-voltage detect (LVD)). The
PSoC 4100 operates with a single external supply over the range
of 1.71 V to 5.5 V and has five different power modes, transitions
between which are managed by the power system. The
PSoC 4100 provides Sleep, Deep Sleep, Hibernate, and Stop
low-power modes.
Clock System
The PSoC 4100 clock system is responsible for providing clocks
to all subsystems that require clocks and for switching between
different clock sources without glitching. In addition, the clock
system ensures that no metastable conditions occur.
The clock system for the PSoC 4100 consists of two internal
oscillators, IMO and the ILO, and provision for an external clock.
Figure 1. PSoC 4100 MCU Clocking Architecture
IMO
HFCLK
Flash
PSoC 4100 has a flash module with a flash accelerator tightly
coupled to the CPU to improve average access times from the
flash block. The flash block is designed to deliver 0 wait-state
(WS) access time at 24 MHz. Part of the flash module can be
used to emulate EEPROM operation if required.
EXTCLK
ILO
LFCLK
The PSoC 4100 flash supports the following flash protection
modes at the memory sub-system level.
Open: No protection. Factory default mode that the product is
shipped in.
Protected: User may change from Open to Protected. This
mode disables debug interface accesses. The mode can be set
back to Open but only after completely erasing the flash.
Kill: User may change from Open to Kill. This mode disables all
debug accesses. The part cannot be erased externally, thus
obviating the possibility of partial erasure by power interruption
and potential malfunction and security leaks. This is an
irrecvocable mode.
In addition, row-level Read/Write protection is also supported to
prevent inadvertent Writes as well as selectively block Reads.
Flash Read/Write/Erase operations are always available for
internal code using system calls.
SRAM
SRAM memory is retained during Hibernate.
SROM
A supervisory ROM that contains boot and configuration routines
is provided.
Document Number: 001-93576 Rev. *F
HFCLK
Prescaler
SYSCLK
UDB
Dividers
UDBn
Analog
Divider
SAR clock
Peripheral
Dividers
PERXYZ_CLK
The HFCLK signal can be divided down (see PSoC 4100 MCU
Clocking Architecture) to generate synchronous clocks for the
analog and digital peripherals. There are a total of 12 clock
dividers for the PSoC 4100, each with 16-bit divide capability.
The analog clock leads the digital clocks to allow analog events
to occur before digital clock-related noise is generated. The
16-bit capability allows a lot of flexibility in generating
fine-grained frequency values and is fully supported in
PSoC Creator.
Page 4 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Analog Blocks
IMO Clock Source
The IMO is the primary source of internal clocking in the
PSoC 4100. It is trimmed during testing to achieve the specified
accuracy. Trim values are stored in nonvolatile latches (NVL).
Additional trim settings from flash can be used to compensate for
changes. The IMO default frequency is 24 MHz and it can be
adjusted between 3 MHz to 24 MHz in steps of 1 MHz. IMO
tolerance with Cypress-provided calibration settings is ±2%.
ILO Clock Source
The ILO is a very low power oscillator, which is primarily used to
generate clocks for peripheral operation in Deep Sleep mode.
ILO-driven counters can be calibrated to the IMO to improve
accuracy. Cypress provides a software component, which does
the calibration.
Watchdog Timer
A watchdog timer is implemented in the clock block running from
the ILO; this allows watchdog operation during Deep Sleep and
generates a watchdog reset if not serviced before the timeout
occurs. The watchdog reset is recorded in the Reset Cause
register.
Reset
PSoC 4100 can be reset from a variety of sources including a
software reset. Reset events are asynchronous and guarantee
reversion to a known state. The reset cause is recorded in a
register, which is sticky through reset and allows software to
determine the cause of the Reset. An XRES pin is reserved for
external reset to avoid complications with configuration and
multiple pin functions during power-on or reconfiguration. The
XRES pin has an internal pull-up resistor that is always enabled.
Voltage Reference
The PSoC 4100 reference system generates all internally
required references. A 1% voltage reference spec is provided for
the 12-bit ADC. To allow better signal-to-noise ratios (SNR) and
better absolute accuracy, it is possible to bypass the internal
reference using a GPIO pin or to use an external reference for
the SAR.
12-bit SAR ADC
The 12-bit 806 Ksps SAR ADC can operate at a maximum clock
rate of 14.5 MHz and requires a minimum of 18 clocks at that
frequency to do a 12-bit conversion.
The block functionality is augmented for the user by adding a
reference buffer to it (trimmable to ±1%) and by providing the
choice (for the PSoC 4100 case) of three internal voltage references: VDD, VDD/2, and VREF (nominally 1.024 V) as well as an
external reference through a GPIO pin. The Sample-and-Hold
(S/H) aperture is programmable allowing the gain bandwidth
requirements of the amplifier driving the SAR inputs, which
determine its settling time, to be relaxed if required. System
performance will be 65 dB for true 12-bit precision providing
appropriate references are used and system noise levels permit.
To improve performance in noisy conditions, it is possible to
provide an external bypass (through a fixed pin location) for the
internal reference amplifier.
The SAR is connected to a fixed set of pins through an 8-input
sequencer. The sequencer cycles through selected channels
autonomously (sequencer scan) and does so with zero switching
overhead (that is, aggregate sampling bandwidth is equal to
806 Ksps whether it is for a single channel or distributed over
several channels). The sequencer switching is effected through
a state machine or through firmware-driven switching. A feature
provided by the sequencer is buffering of each channel to reduce
CPU interrupt service requirements. To accommodate signals
with varying source impedance and frequency, it is possible to
have different sample times programmable for each channel.
Also, signal range specification through a pair of range registers
(low and high range values) is implemented with a corresponding
out-of-range interrupt if the digitized value exceeds the
programmed range; this allows fast detection of out-of-range
values without the necessity of having to wait for a sequencer
scan to be completed and the CPU to read the values and check
for out-of-range values in software.
The SAR is able to digitize the output of the on-board
temperature
sensor
for
calibration
and
other
temperature-dependent functions. The SAR is not available in
Deep Sleep and Hibernate modes as it requires a high-speed
clock (up to 18 MHz). The SAR operating range is 1.71 V to
5.5 V.
Figure 2. SAR ADC System Diagram
AHB System Bus and Programmable Logic
Interconnect
SAR Sequencer
vminus vplus
Data and
Status Flags
POS
SARADC
NEG
External
Reference
and
Bypass
(optional)
Reference
Selection
P7
Port 2 (8 inputs)
SARMUX
P0
Sequencing
and Control
VDD/2
VDDD
VREF
Inputs from other Ports
Document Number: 001-93576 Rev. *F
Page 5 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Opamp (CTBm Block)
PSoC 4100 has an opamp with Comparator mode, which allows
most common analog functions to be performed on-chip eliminating external components; PGAs, voltage buffers, filters,
trans-impedance amplifiers, and other functions can be realized
with external passives saving power, cost, and space. The
on-chip opamp is designed with enough bandwidth to drive the
S/H circuit of the ADC without requiring external buffering.
Temperature Sensor
PSoC 4100 has one on-chip temperature sensor This consists
of a diode, which is biased by a current source that can be
disabled to save power. The temperature sensor is connected to
the ADC, which digitizes the reading and produces a
temperature value using Cypress supplied software that includes
calibration and linearization.
I/O is implemented with GPIO in open-drain modes. The I2C bus
uses open-drain drivers for clock and data with pull-up resistors
on the bus for clock and data connected to all nodes. Required
Rise and Fall times for different I2C speeds are guaranteed by
using appropriate pull-up resistor values depending on VDD, Bus
Capacitance, and resistor tolerance. For detailed information on
how to calculate the optimum pull-up resistor value for your
design, please refer to the UM10204 I2C bus specification and
user manual, the newest revision is available at www.nxp.com.
The PSoC 4100 is not completely compliant with the I2C spec in
the following respects:
■
GPIO cells are not overvoltage tolerant and, therefore, cannot
be hot-swapped or powered up independently of the rest of the
I2C system.
■
Fast-mode Plus has an IOL specification of 20 mA at a VOL of
0.4 V. The GPIO cells can sink a maximum of 8 mA IOL with a
VOL maximum of 0.6 V.
■
Fast-mode and Fast-mode Plus specify minimum Fall times,
which are not met with the GPIO cell; Slow strong mode can
help meet this spec depending on the Bus Load.
Low-power Comparators
PSoC 4100 has a pair of low-power comparators, which can also
operate in the Deep Sleep and Hibernate modes. This allows the
analog system blocks to be disabled while retaining the ability to
monitor external voltage levels during low-power modes. The
comparator outputs are normally synchronized to avoid metastability unless operating in an asynchronous power mode
(Hibernate) where the system wake-up circuit is activated by a
comparator switch event.
Fixed Function Digital
Timer/Counter/PWM Block
The Timer/Counter/PWM block consists of four 16-bit counters
with user-programmable period length. There is a Capture
register to record the count value at the time of an event (which
may be an I/O event), a period register which is used to either
stop or auto-reload the counter when its count is equal to the
period register, and compare registers to generate compare
value signals which are used as PWM duty cycle outputs. The
block also provides true and complementary outputs with
programmable offset between them to allow use as deadband
programmable complementary PWM outputs. It also has a Kill
input to force outputs to a predetermined state; for example, this
is used in motor drive systems when an overcurrent state is
indicated and the PWMs driving the FETs need to be shut off
immediately with no time for software intervention.
Serial Communication Blocks (SCB)
PSoC 4100 has two SCBs, which can each implement an I2C,
UART, SPI, or LIN Slave interface.
I2C Mode: The hardware I2C block implements a full
multi-master and slave interface (it is capable of multimaster
arbitration). This block is capable of operating at speeds of up to
1 Mbps (Fast Mode Plus) and has flexible buffering options to
reduce interrupt overhead and latency for the CPU. The FIFO
mode is available in all channels and is very useful in the
absence of DMA.
The I2C peripheral is compatible with the I2C Standard-mode,
Fast-mode, and Fast-mode Plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus
Document Number: 001-93576 Rev. *F
■
■
When the SCB is an I2C Master, it interposes an IDLE state
between NACK and Repeated Start; the I2C spec defines Bus
free as following a Stop condition so other Active Masters do
not intervene but a Master that has just become activated may
start an Arbitration cycle.
When the SCB is in I2C Slave mode, and Address Match on
External Clock is enabled (EC_AM = 1) along with operation in
the internally clocked mode (EC_OP = 0), then its I2C address
must be even.
UART Mode: This is a full-feature UART operating at up to
1 Mbps. It supports automotive single-wire interface (LIN),
infrared interface (IrDA), and SmartCard (ISO7816) protocols, all
of which are minor variants of the basic UART protocol. In
addition, it supports the 9-bit multiprocessor mode that allows
addressing of peripherals connected over common RX and TX
lines. Common UART functions such as parity error, break
detect, and frame error are supported. An 8-deep FIFO allows
much greater CPU service latencies to be tolerated.
SPI Mode: The SPI mode supports full Motorola SPI, TI SSP
(essentially adds a start pulse used to synchronize SPI Codecs),
and National Microwire (half-duplex form of SPI). The SPI block
can use the FIFO and also supports an EzSPI mode in which
data interchange is reduced to reading and writing an array in
memory.
LIN Slave Mode: The LIN Slave mode uses the SCB hardware
block and implements a full LIN slave interface. This LIN slave is
compliant with LIN v1.3 and LIN v2.1/2.2 specification standards.
It is certified by C&S GmbH based on the standard protocol and
data link layer conformance tests. The LIN slave can be operated
at baud rates of up to ~20 Kbps with a maximum of 40-meter
cable length. PSoC Creator software supports up to two LIN
slave interfaces in the PSoC 4 device, providing built-in
application programming interfaces (APIs) based on the LIN
specification standard.
Page 6 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
GPIO
Special Function Peripherals
PSoC 4100 has 24 GPIOs. The GPIO block implements the
following:
LCD Segment Drive
■
Eight drive strength modes:
❐ Analog input mode (input and output buffers disabled)
❐ Input only
❐ Weak pull-up with strong pull-down
❐ Strong pull-up with weak pull-down
❐ Open drain with strong pull-down
❐ Open drain with strong pull-up
❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
The PSoC 4100 has an LCD controller which can drive up to four
commons and up to 32 segments. It uses full digital methods to
drive the LCD segments requiring no generation of internal LCD
voltages. The two methods used are referred to as digital
correlation and PWM.
Digital correlation pertains to modulating the frequency and
levels of the common and segment signals to generate the
highest RMS voltage across a segment to light it up or to keep
the RMS signal zero. This method is good for STN displays but
may result in reduced contrast with TN (cheaper) displays.
■
Input threshold select (CMOS or LVTTL).
■
Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes.
■
Hold mode for latching previous state (used for retaining I/O
state in Deep Sleep mode and Hibernate modes).
PWM pertains to driving the panel with PWM signals to
effectively use the capacitance of the panel to provide the
integration of the modulated pulse-width to generate the desired
LCD voltage. This method results in higher power consumption
but can result in better results when driving TN displays. LCD
operation is supported during Deep Sleep refreshing a small
display buffer (4 bits; 1 32-bit register per port).
■
Selectable slew rates for dV/dt related noise control to improve
EMI.
CapSense
The pins are organized in logical entities called ports, which are
8-bit in width. During power-on and reset, the blocks are forced
to the disable state so as not to crowbar any inputs and/or cause
excess turn-on current. A multiplexing network known as a
high-speed I/O matrix is used to multiplex between various
signals that may connect to an I/O pin. Pin locations for
fixed-function peripherals are also fixed to reduce internal
multiplexing complexity.
Data output and pin state registers store, respectively, the values
to be driven on the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled and each
I/O port has an interrupt request (IRQ) and interrupt service
routine (ISR) vector associated with it (5 for PSoC 4100).
Document Number: 001-93576 Rev. *F
CapSense is supported on all pins in the PSoC 4100 through a
CapSense Sigma-Delta (CSD) block that can be connected to
any pin through an analog mux bus that any GPIO pin can be
connected to via an Analog switch. CapSense function can thus
be provided on any pin or group of pins in a system under
software control. A component is provided for the CapSense
block to make it easy for the user.
Shield voltage can be driven on another Mux Bus to provide
water tolerance capability. Water tolerance is provided by driving
the shield electrode in phase with the sense electrode to keep
the shield capacitance from attenuating the sensed input.
The CapSense block has two IDACs which can be used for
general purposes if CapSense is not being used.(both IDACs are
available in that case) or if CapSense is used without water
tolerance (one IDAC is available).
Page 7 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Pinouts
The following is the pin-list for PSoC 4100. Port 2 comprises of the high-speed Analog inputs for the SAR Mux. P1.7 is the optional
external input and bypass for the SAR reference. Ports 3 and 4 contain the Digital Communication channels. All pins support CSD
CapSense and Analog Mux Bus connections.
Pins
28-SSOP
Name
Type
Pin
VSSD
Power
DN
P2.2
GPIO
5
P2.3
GPIO
6
P2.4
GPIO
P2.5
Name
Alternate Functions for Pins
Pin Description
Analog
Alt 1
Alt 2
Alt 3
Alt 4
–
–
–
–
–
–
Digital Ground
P2.2
sarmux.2
–
–
–
–
Port 2 Pin 2: gpio, lcd, csd, sarmux
P2.3
sarmux.3
–
–
–
–
Port 2 Pin 3: gpio, lcd, csd, sarmux
7
P2.4
sarmux.4
tcpwm0_p[1]
–
–
–
Port 2 Pin 4: gpio, lcd, csd, sarmux,
pwm
GPIO
8
P2.5
sarmux.5
tcpwm0_n[1]
–
–
–
Port 2 Pin 5: gpio, lcd, csd, sarmux,
pwm
P2.6
GPIO
9
P2.6
sarmux.6
tcpwm1_p[1]
–
–
–
Port 2 Pin 6: gpio, lcd, csd, sarmux,
pwm
P2.7
GPIO
10
P2.7
sarmux.7
tcpwm1_n[1]
–
–
–
Port 2 Pin 7: gpio, lcd, csd, sarmux,
pwm
P3.0
GPIO
11
P3.0
–
tcpwm0_p[0]
scb1_uart_rx[0]
scb1_i2c_scl[0]
scb1_spi_mosi[0]
Port 3 Pin 0: gpio, lcd, csd, pwm,
scb1
P3.1
GPIO
12
P3.1
–
tcpwm0_n[0]
scb1_uart_tx[0]
scb1_i2c_sda[0]
scb1_spi_miso[0]
Port 3 Pin 1: gpio, lcd, csd, pwm,
scb1
P3.2
GPIO
13
P3.2
–
tcpwm1_p[0]
–
swd_io
scb1_spi_clk[0]
Port 3 Pin 2: gpio, lcd, csd, pwm,
scb1, swd
P3.3
GPIO
14
P3.3
–
tcpwm1_n[0]
–
swd_clk
P4.0
GPIO
15
P4.0
–
–
scb0_uart_rx
scb0_i2c_scl
scb0_spi_mosi
Port 4 Pin 0: gpio, lcd, csd, scb0
P4.1
GPIO
16
P4.1
–
–
scb0_uart_tx
scb0_i2c_sda
scb0_spi_miso
Port 4 Pin 1: gpio, lcd, csd, scb0
P4.2
GPIO
17
P4.2
csd_c_mod
–
–
–
scb0_spi_clk
Port 4 Pin 2: gpio, lcd, csd, scb0
P4.3
GPIO
18
P4.3
csd_c_sh_tan
k
–
–
–
scb0_spi_ssel_0
Port 4 Pin 3: gpio, lcd, csd, scb0
P0.0
GPIO
19
P0.0
comp1_inp
–
–
–
scb0_spi_ssel_1
Port 0 Pin 0: gpio, lcd, csd, scb0,
comp
P0.1
GPIO
20
P0.1
comp1_inn
–
–
–
scb0_spi_ssel_2
Port 0 Pin 1: gpio, lcd, csd, scb0,
comp
P0.2
GPIO
21
P0.2
comp2_inp
–
–
–
scb0_spi_ssel_3
Port 0 Pin 2: gpio, lcd, csd, scb0,
comp
scb1_spi_ssel_0[0] Port 3 Pin 3: gpio, lcd, csd, pwm,
scb1, swd
P0.3
GPIO
22
P0.3
comp2_inn
–
–
–
–
Port 0 Pin 3: gpio, lcd, csd, comp
P0.6
GPIO
23
P0.6
–
ext_clk
–
–
scb1_spi_clk[1]
Port 0 Pin 6: gpio, lcd, csd, scb1,
ext_clk
P0.7
GPIO
24
P0.7
–
–
–
wakeup
scb1_spi_ssel_0[1] Port 0 Pin 7: gpio, lcd, csd, scb1,
wakeup
XRES
XRES
25
XRES
–
–
–
–
–
Chip reset, active low
VCCD
Power
26
VCCD
–
–
–
–
–
Regulated supply, connect to 1 µF
cap or 1.8 V
VDDD
Power
27
VDDD
–
–
–
–
–
Common power supply (Analog &
Digital) 1.8 V–5.5 V
VSSA
Power
28(DN)
VSS
–
–
–
–
–
Analog Ground
P1.0
GPIO
1
P1.0
ctb.oa0.inp
tcpwm2_p[1]
–
–
–
Port 1 Pin 0: gpio, lcd, csd, ctb, pwm
P1.1
GPIO
2
P1.1
ctb.oa0.inm
tcpwm2_n[1]
–
–
–
Port 1 Pin 1: gpio, lcd, csd, ctb, pwm
P1.2
GPIO
3
P1.2
ctb.oa0.out
tcpwm3_p[1]
–
–
–
Port 1 Pin 2: gpio, lcd, csd, ctb, pwm
P1.7
GPIO
4
P1.7
ctb.oa1.inp_a
lt ext_vref
–
–
–
–
Port 1 Pin 7: gpio, lcd, csd, ext_ref
Notes:
1. tcpwm_p and tcpwm_n refer to tcpwm non-inverted and inverted outputs respectively.
2. P3.2 and P3.3 are SWD pins after boot (reset).
Descriptions of the pin functions are as follows:
VDDD: Power supply for both analog and digital sections (where there is no VDDA pin).
Document Number: 001-93576 Rev. *F
Page 8 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
VDDA: Analog VDD pin where package pins allow; shorted to VDDD otherwise.
VSSA: Analog ground pin where package pins allow; shorted to VSS otherwise
VSS: Ground pin.
VCCD: Regulated Digital supply (1.8 V ±5%).
Port Pins can all be used as LCD Commons, LCD Segment drivers, or CSD sense and shield pins can be connected to AMUXBUS
A or B or can all be used as GPIO pins that can be driven by firmware or DSI signals.
The following package is supported: 28-pin SSOP.
Figure 3. 28-pin SSOP pinout
(GPIO)P1[0]
(GPIO)P1[1]
(GPIO)P1[2]
(GPIO)P1[7]
(GPIO)P2[2]
(GPIO)P2[3]
(GPIO)P2[4]
(GPIO)P2[5]
(GPIO)P2[6]
(GPIO)P2[7]
(GPIO)P3[0]
(GPIO)P3[1]
(GPIO)P3[2]
(GPIO)P3[3]
Document Number: 001-93576 Rev. *F
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSOP
(Top View)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VSS
VDDD
VCCD
XRES
(GPIO)P0[7]
(GPIO)P0[6]
(GPIO)P0[3]
(GPIO)P0[2]
(GPIO)P0[1]
(GPIO)P0[0]
(GPIO)P4[3]
(GPIO)P4[2]
(GPIO)P4[1]
(GPIO)P4[0]
Page 9 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Power
Table 1. Example of a bypass scheme
The following power system diagram shows the minimum set of
power supply pins as implemented for the PSoC 4100. The
system has one regulator in Active mode for the digital circuitry.
There is no analog regulator; the analog circuits run directly from
the VDDA input. There are separate regulators for the Deep Sleep
and Hibernate (lowered power supply and retention) modes.
There is a separate low-noise regulator for the bandgap. The
supply voltage range is 1.71 to 5.5 V with all functions and
circuits operating over that range.
Power Supply
Bypass Capacitors
VDDD–VSS
0.1 µF ceramic capacitor (C2) plus bulk
capacitor 1 to 10 µF (C1). Total
Capacitance may be greater than 10 µF.
VCCD–VSS
1 µF ceramic capacitor at the VCCD pin
(C3)
VREF–VSS
(optional)
The internal bandgap may be bypassed
with a 1 µF to 10 µF capacitor. Total capacitance may be greater than 10 µF.
Figure 4. PSoC 4 Power Supply
Figure 5. 28-Pin SSOP Example
Digital
Domain
VSS
0.1 µF C2
C1 1µF
VSS
VDDD
VDDD
1.8 Volt
Reg
VCCD
VSSD
The PSoC 4100 family allows two distinct modes of power supply
operation: Unregulated External Supply, and Regulated External
Supply modes.
Unregulated External Supply
In this mode, PSoC 4100 is powered by an External Power
Supply that can be anywhere in the range of 1.8 V to 5.5 V. This
range is also designed for battery-powered operation, for
instance, the chip can be powered from a battery system that
starts at 3.5 V and works down to 1.8 V. In this mode, the internal
regulator of the PSoC 4100 supplies the internal logic and the
VCCD output of the PSoC 4100 must be bypassed to ground via
an external Capacitor (in the range of 1 to 1.6 µF; X5R ceramic
or better).
(GPIO )P1[0]
(GPIO)P1[1]
(GPIO )P1[2]
( GPIO) P1[7]
( GPIO) P2[2]
(GPIO ) P2[3]
(GPIO ) P2[4]
(GPIO ) P2[5]
(GPIO) P2[6]
(GPIO) P2[7]
( GPIO) P3[0]
(GPIO )P3[1]
(GPIO )P3[2]
(GPIO )P3[3]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
SSOP
( Top View)
VSS 28
VDDD27
VCCD26
25
24
23
22
21
20
19
18
17
16
15
XRES
( GPIO) P0[7]
( GPIO) P0[6]
( GPIO) P0[3]
( GPIO) P0[2]
( GPIO) P0[1]
( GPIO) P0[0]
( GPIO) P4[3]
( GPIO)P4[2]
( GPIO)P4[1]
( GPIO)P4[0]
C3 1µF
VSS
Regulated External Supply
In this mode, the PSoC 4100 is powered by an external power
supply that must be within the range of 1.71 to 1.89 V (1.8 ± 5%);
note that this range needs to include power supply ripple too. In
this mode, VCCD, and VDDD pins are all shorted together and
bypassed. The internal regulator is disabled in firmware.
Bypass capacitors must be used from VDDD to ground, typical
practice for systems in this frequency range is to use a capacitor
in the 1-µF range in parallel with a smaller capacitor (0.1 µF for
example). Note that these are simply rules of thumb and that, for
critical applications, the PCB layout, lead inductance, and the
Bypass capacitor parasitic should be simulated to design and
obtain optimal bypassing.
An example of a bypass scheme for the 28-pin SSOP package
follows.
Document Number: 001-93576 Rev. *F
Page 10 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Development Support
The PSoC 4100 family has a rich set of documentation,
development tools, and online resources to assist you during
your development process. Visit www.cypress.com/go/psoc4 to
find out more.
Documentation
A suite of documentation supports the PSoC 4100 family to
ensure that you can find answers to your questions quickly. This
section contains a list of some of the key documents.
Software User Guide: A step-by-step guide for using PSoC
Creator. The software user guide shows you how the PSoC
Creator build process works in detail, how to use source control
with PSoC Creator, and much more.
Component Datasheets: The flexibility of PSoC allows the
creation of new peripherals (components) long after the device
has gone into production. Component data sheets provide all of
the information needed to select and use a particular component,
including a functional description, API documentation, example
code, and AC/DC specifications.
Technical Reference Manual: The Technical Reference Manual
(TRM) contains all the technical detail you need to use a PSoC
device, including a complete description of all PSoC registers.
The TRM is available in the Documentation section at
www.cypress.com/psoc4.
Online
In addition to print documentation, the Cypress PSoC forums
connect you with fellow PSoC users and experts in PSoC from
around the world, 24 hours a day, 7 days a week.
Tools
With industry standard cores, programming, and debugging
interfaces, the PSoC 4100 family is part of a development tool
ecosystem. Visit us at www.cypress.com/go/psoccreator for the
latest information on the revolutionary, easy to use PSoC Creator
IDE, supported third party compilers, programmers, debuggers,
and development kits.
Application Notes: PSoC application notes discuss a particular
application of PSoC in depth; examples include brushless DC
motor control and on-chip filtering. Application notes often
include example projects in addition to the application note
document.
Document Number: 001-93576 Rev. *F
Page 11 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Electrical Specifications
Absolute Maximum Ratings
Table 2. Absolute Maximum Ratings[1]
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID1
VDDD_ABS
Digital supply relative to VSSD
–0.5
–
6
V
Absolute max
SID2
VCCD_ABS
Direct digital core voltage input relative
to VSSD
–0.5
–
1.95
V
Absolute max
SID3
VGPIO_ABS
GPIO voltage
–0.5
–
VDD+0.5
V
Absolute max
SID4
IGPIO_ABS
Maximum current per GPIO
–25
–
25
mA
Absolute max
SID5
IGPIO_injection
GPIO injection current, Max for VIH >
VDDD, and Min for VIL < VSS
–0.5
–
0.5
mA
Absolute max, current
injected per pin
BID44
ESD_HBM
Electrostatic discharge human body
model
2200
–
–
V
BID45
ESD_CDM
Electrostatic discharge charged device
model
500
–
–
V
BID46
LU
Pin current for latch-up
–200
–
200
mA
Note
1. Usage above the absolute maximum conditions listed in Table 2 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 001-93576 Rev. *F
Page 12 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Device-Level Specifications
All specifications are valid for –40 °C ≤ TA ≤ 85 °C for A grade devices and -40 °C ≤ TA ≤ 105 °C for S grade devices, except where
noted. Specifications are valid for 1.71 V to 5.5 V, except where noted.
Table 3. DC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
1.8
–
5.5
V
With regulator enabled
Power supply input voltage unregulated 1.71
1.8
1.89
V
Internally unregulated
Supply
VCCD
Output voltage (for core logic)
–
1.8
–
V
SID55
CEFC
External regulator voltage bypass
1
1.3
1.6
µF
X5R ceramic or better
SID56
CEXC
Power supply decoupling capacitor
–
1
–
µF
X5R ceramic or better
SID53
VDD
Power supply input voltage
(VDDA = VDDD = VDD)
SID255
VDDD
SID54
Details/Conditions
Active Mode, VDD = 1.71 V to 5.5 V. Typical Values measured at VDD = 3.3 V.
SID9
IDD4
Execute from Flash;
CPU at 6 MHz
–
–
2.8
mA
SID10
IDD5
Execute from Flash;
CPU at 6 MHz
–
2.2
–
mA
SID12
IDD7
Execute from Flash;
CPU at 12 MHz
–
–
4.2
mA
SID13
IDD8
Execute from Flash;
CPU at 12 MHz
–
3.7
–
mA
T = 25 °C
SID16
IDD11
Execute from Flash;
CPU at 24 MHz
–
6.7
–
mA
T = 25 °C
SID17
IDD12
Execute from Flash;
CPU at 24 MHz
–
–
7.2
mA
T = 25 °C
Sleep Mode, VDD = 1.7 V to 5.5 V
SID25
IDD20
I2C wakeup, WDT,
and Comparators on. 6 MHz.
–
1.3
1.8
mA
VDD = 1.71 V to 5.5 V
SID25A
IDD20A
I2C wakeup, WDT,
and Comparators on. 12 MHz.
–
1.7
2.2
mA
VDD = 1.71 V to 5.5 V
Deep Sleep Mode, VDD = 1.8 V to 3.6 V (Regulator on)
SID31
SID32
IDD26
I2C wakeup and WDT on.
–
1.3
–
µA
T = 25 °C
IDD27
I2C
–
–
45
µA
T = 85 °C
–
1.5
15
µA
Typ. at 25 °C
Max at 85 °C
wakeup and WDT on.
Deep Sleep Mode, VDD = 3.6 V to 5.5 V
SID34
IDD29
I2C wakeup and WDT on
Deep Sleep Mode, VDD = 1.71 V to 1.89 V (Regulator bypassed)
SID37
IDD32
I2C wakeup and WDT on.
–
1.7
–
µA
T = 25 °C
SID38
IDD33
I2C wakeup and WDT on
–
–
60
µA
T = 85 °C
IDD28Q
I2C wakeup and WDT on. Regulator Off.
–
–
135
µA
VDD = 1.71 V to 1.89 V
SID34Q
IDD29Q
I2C
wakeup and WDT on.
–
–
180
µA
VDD = 1.8 V to 3.6 V
SID35Q
IDD30Q
I2C wakeup and WDT on.
–
–
140
µA
VDD = 3.6 V to 5.5 V
Deep Sleep Mode, +105 °C
SID33Q
Document Number: 001-93576 Rev. *F
Page 13 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Table 3. DC Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
Hibernate Mode, VDD = 1.8 V to 3.6 V (Regulator on)
SID40
IDD35
GPIO & Reset active
–
150
–
nA
T = 25 °C
SID41
IDD36
GPIO & Reset active
–
–
1000
nA
T = 85 °C
–
150
–
nA
T = 25 °C
Hibernate Mode, VDD = 3.6 V to 5.5 V
SID43
IDD38
GPIO & Reset active
Hibernate Mode, VDD = 1.71 V to 1.89 V (Regulator bypassed)
SID46
IDD41
GPIO & Reset active
–
150
–
nA
T = 25 °C
SID47
IDD42
GPIO & Reset active
–
–
1000
nA
T = 85 °C
Regulator Off
Hibernate Mode, +105 °C
SID42Q
IDD37Q
–
–
19.4
µA
VDD = 1.71 V to 1.89 V
SID43Q
IDD38Q
–
–
17
µA
VDD = 1.8 V to 3.6 V
SID44Q
IDD39Q
–
–
16
µA
VDD = 3.6 V to 5.5 V
Stop Mode current; VDD = 3.3 V
–
20
80
nA
Typ at 25 °C.
Max at 85 °C
Stop Mode current; VDD = 5.5 V
–
20
750
nA
Typ at 25 °C
Max at 85 °C
IDD43AQ
Stop Mode current; VDD = 3.6 V
–
–
5645
nA
IDD_XR
Supply current while XRES asserted
–
2
5
mA
Stop Mode
SID304
IDD43A
Stop Mode, +105 °C
SID304Q
XRES current
SID307
Document Number: 001-93576 Rev. *F
Page 14 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
GPIO
Table 4. GPIO DC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID57
VIH[2]
Input voltage high threshold
0.7 ×
VDDD
–
–
V
CMOS Input
SID58
VIL
Input voltage low threshold
–
–
0.3 ×
VDDD
V
CMOS Input
SID241
VIH[2]
LVTTL input, VDDD < 2.7 V
0.7×
VDDD
–
–
V
SID242
VIL
LVTTL input, VDDD < 2.7 V
–
–
0.3 ×
VDDD
V
SID243
VIH[2]
LVTTL input, VDDD ≥ 2.7 V
2.0
–
–
V
SID244
VIL
LVTTL input, VDDD ≥ 2.7 V
–
–
0.8
V
SID59
VOH
Output voltage high level
VDDD
–0.6
–
–
V
IOH = 4 mA at 3 V
VDDD
SID60
VOH
Output voltage high level
VDDD
–0.5
–
–
V
IOH = 1 mA at
1.8 V VDDD
SID61
VOL
Output voltage low level
–
–
0.6
V
IOL = 4 mA at
1.8 V VDDD
SID62
VOL
Output voltage low level
–
–
0.6
V
IOL = 8 mA at 3 V
VDDD
SID62A
VOL
Output voltage low level
–
–
0.4
V
IOL = 3 mA at 3 V
VDDD
SID63
RPULLUP
Pull-up resistor
3.5
5.6
8.5
kΩ
SID64
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
kΩ
SID65
IIL
Input leakage current (absolute value)
–
–
2
nA
SID65A
IIL_CTBM
Input leakage current (absolute value) for
CTBM pins
–
–
4
nA
SID66
CIN
Input capacitance
–
–
7
pF
SID67
VHYSTTL
Input hysteresis LVTTL
25
40
–
mV
VDDD ≥ 2.7 V.
Guaranteed by
characterization
SID68
VHYSCMOS
Input hysteresis CMOS
0.05 ×
VDDD
–
–
mV
Guaranteed by
characterization
SID69
IDIODE
Current through protection diode to
VDD/Vss
–
–
100
µA
Guaranteed by
characterization
SID69A
ITOT_GPIO
Maximum total source or sink chip current
–
–
200
mA
Guaranteed by
characterization
25 °C, VDDD =
3.0 V
Note
2. VIH must not exceed VDDD + 0.2 V.
Document Number: 001-93576 Rev. *F
Page 15 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Table 5. GPIO AC Specifications (Guaranteed by Characterization)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID70
TRISEF
Rise time in fast strong mode
2
–
12
ns
3.3-V VDDD,
Cload = 25 pF
SID71
TFALLF
Fall time in fast strong mode
2
–
12
ns
3.3-V VDDD,
Cload = 25 pF
SID72
TRISES
Rise time in slow strong mode
10
–
60
3.3-V VDDD,
Cload = 25 pF
SID73
TFALLS
Fall time in slow strong mode
10
–
60
3.3-V VDDD,
Cload = 25 pF
SID74
FGPIOUT1
GPIO Fout;3.3 V ≤ VDDD ≤ 5.5 V. Fast
strong mode.
–
–
24
MHz
90/10%, 25-pF
load, 60/40 duty
cycle
SID75
FGPIOUT2
GPIO Fout;1.7 V≤ VDDD≤ 3.3 V. Fast
strong mode.
–
–
16.7
MHz
90/10%, 25-pF
load, 60/40 duty
cycle
SID76
FGPIOUT3
GPIO Fout;3.3 V ≤ VDDD ≤ 5.5 V. Slow
strong mode.
–
–
7
MHz
90/10%, 25-pF
load, 60/40 duty
cycle
SID245
FGPIOUT4
GPIO Fout;1.7 V ≤ VDDD ≤ 3.3 V. Slow
strong mode.
–
–
3.5
MHz
90/10%, 25-pF
load, 60/40 duty
cycle
SID246
FGPIOIN
GPIO input operating frequency;
1.71 V ≤ VDDD ≤ 5.5 V
–
–
24
MHz
90/10% VIO
Min
Typ
Max
Units
XRES
Table 6. XRES DC Specifications
Spec ID#
Parameter
Description
Details/
Conditions
SID77
VIH
Input voltage high threshold
0.7 ×
VDDD
–
–
V
CMOS Input
SID78
VIL
Input voltage low threshold
–
–
0.3 ×
VDDD
V
CMOS Input
SID79
RPULLUP
Pull-up resistor
3.5
5.6
8.5
kΩ
SID80
CIN
Input capacitance
–
3
–
pF
SID81
VHYSXRES
Input voltage hysteresis
–
100
–
mV
Guaranteed by
characterization
SID82
IDIODE
Current through protection diode to
VDDD/VSS
–
–
100
µA
Guaranteed by
characterization
Min
Typ
Max
Units
1
–
–
µs
Table 7. XRES AC Specifications
Spec ID#
SID83
Parameter
TRESETWIDTH
Description
Reset pulse width
Document Number: 001-93576 Rev. *F
Details/
Conditions
Guaranteed by
characterization
Page 16 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Analog Peripherals
Opamp
Table 8. Opamp Specifications (Guaranteed by Characterization)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
IDD
Opamp block current. No load.
–
–
–
–
SID269
IDD_HI
Power = high
–
1100
1850
µA
SID270
IDD_MED
Power = medium
–
550
950
µA
SID271
IDD_LOW
Power = low
–
150
350
µA
GBW
Load = 20 pF, 0.1 mA. VDDA = 2.7 V
–
–
–
–
SID272
GBW_HI
Power = high
6
–
–
MHz
SID273
GBW_MED
Power = medium
4
–
–
MHz
SID274
GBW_LO
Power = low
–
1
–
MHz
IOUT_MAX
VDDA ≥ 2.7 V, 500 mV from rail
–
–
–
–
SID275
IOUT_MAX_HI
Power = high
10
–
–
mA
SID276
IOUT_MAX_MID
Power = medium
10
–
–
mA
SID277
IOUT_MAX_LO
Power = low
–
5
–
mA
IOUT
VDDA = 1.71 V, 500 mV from rail
–
–
–
–
SID278
IOUT_MAX_HI
Power = high
4
–
–
mA
SID279
IOUT_MAX_MID
Power = medium
4
–
–
mA
SID280
IOUT_MAX_LO
Power = low
–
2
–
mA
Details/
Conditions
SID281
VIN
Charge pump on, VDDA ≥ 2.7 V
–0.05
–
VDDA – 0.2
V
SID282
VCM
Charge pump on, VDDA ≥ 2.7 V
–0.05
–
VDDA – 0.2
V
VOUT
VDDA ≥ 2.7 V
SID283
VOUT_1
Power = high, Iload=10 mA
SID284
VOUT_2
Power = high, Iload=1 mA
0.2
SID285
VOUT_3
Power = medium, Iload=1 mA
0.2
SID286
VOUT_4
Power = low, Iload=0.1mA
0.2
–
VDDA – 0.2
V
SID288
VOS_TR
Offset voltage, trimmed
1
±0.5
1
mV
SID288A
VOS_TR
Offset voltage, trimmed
–
±1
–
mV
Medium mode
SID288B
VOS_TR
Offset voltage, trimmed
–
±2
–
mV
Low mode
SID290
VOS_DR_TR
Offset voltage drift, trimmed
–10
±3
10
µV/°C
High mode
TA < 85 °C.
SID290Q
VOS_DR_TR
Offset voltage drift, trimmed
–15
±3
15
μV/°C
High mode.
TA ≤ 105 °C
SID290A
VOS_DR_TR
Offset voltage drift, trimmed
–
±10
–
µV/°C
Medium mode
SID290B
VOS_DR_TR
Offset voltage drift, trimmed
–
±10
–
µV/°C
Low mode
–
–
–
0.5
–
VDDA – 0.5
V
–
VDDA – 0.2
V
–
VDDA – 0.2
V
High mode
SID291
CMRR
DC
70
80
–
dB
VDDD = 3.6 V
SID292
PSRR
At 1 kHz, 100 mV ripple
70
85
–
dB
VDDD = 3.6 V
–
–
–
–
SID293
VN1
Input referred, 1 Hz - 1GHz, power =
high
–
94
–
µVrms
SID294
VN2
Input referred, 1 kHz, power = high
–
72
–
nV/rtHz
SID295
VN3
Input referred, 10 kHz, power = high
–
28
–
nV/rtHz
SID296
VN4
Input referred, 100 kHz, power = high
–
15
–
nV/rtHz
Noise
Document Number: 001-93576 Rev. *F
Page 17 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Table 8. Opamp Specifications (Guaranteed by Characterization) (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
SID297
Cload
Stable up to maximum load. Performance specs at 50 pF.
–
–
125
pF
SID298
Slew_rate
Cload = 50 pF, Power = High, VDDA ≥
2.7 V
6
–
–
V/µs
SID299
T_op_wake
From disable to enable, no external RC
dominating
–
300
–
µs
Comp_mode
Comparator mode; 50 mV drive,
Trise = Tfall (approx.)
–
–
–
SID299A
OL_GAIN
Open Loop Gain
–
90
–
dB
SID300
TPD1
Response time; power = high
–
150
–
ns
SID301
TPD2
Response time; power = medium
–
400
–
ns
SID302
TPD3
Response time; power = low
–
2000
–
ns
SID303
Vhyst_op
Hysteresis
–
10
–
mV
Min
Typ
Max
Units
Details/
Conditions
Guaranteed by
design
Comparator
Table 9. Comparator DC Specifications
Spec ID#
Parameter
Description
Details/
Conditions
SID85
VOFFSET2
Input offset voltage, Common Mode
voltage range from 0 to VDD-1
–
–
±4
mV
SID85A
VOFFSET3
Input offset voltage. Ultra low-power
mode (VDDD ≥ 2.2 V for Temp < 0 °C,
VDDD ≥ 1.8 V for Temp > 0 °C)
–
±12
–
mV
SID86
VHYST
Hysteresis when enabled, Common
Mode voltage range from 0 to (VDD – 1).
–
10
35
mV
Guaranteed by
characterization
SID87
VICM1
Input common mode voltage in normal
mode
0
–
VDDD – 0.1
V
Modes 1 and 2
SID247
VICM2
Input common mode voltage in low
power mode (VDDD ≥ 2.2 V for Temp <
0 °C, VDDD ≥ 1.8 V for Temp > 0 °C)
0
–
VDDD
V
SID247A
VICM3
Input common mode voltage in ultra low
power mode
0
–
VDDD –
1.15
V
SID88
CMRR
Common mode rejection ratio
50
–
–
dB
VDDD ≥ 2.7 V.
Guaranteed by
characterization
SID88A
CMRR
Common mode rejection ratio
42
–
–
dB
VDDD < 2.7 V.
Guaranteed by
characterization
SID89
ICMP1
Block current, normal mode
–
–
400
µA
Guaranteed by
characterization
SID248
ICMP2
Block current, low power mode
–
–
100
µA
Guaranteed by
characterization
SID259
ICMP3
Block current, ultra low power mode
(VDDD ≥ 2.2 V for Temp < 0 °C, VDDD ≥
1.8 V for Temp > 0 °C)
–
6
28
µA
Guaranteed by
characterization
SID90
ZCMP
DC input impedance of comparator
35
–
–
MΩ
Guaranteed by
characterization
Document Number: 001-93576 Rev. *F
Page 18 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Table 10. Comparator AC Specifications
(Guaranteed by Characterization)
Min
Typ
Max
Units
SID91
Spec ID#
TRESP1
Parameter
Response time, normal mode
Description
–
–
110
ns
50 mV overdrive
Details/Conditions
SID258
TRESP2
Response time, low power mode
–
–
200
ns
50 mV overdrive
SID92
TRESP3
Response time, ultra low power mode
(VDDD ≥ 2.2 V for Temp < 0 °C,
VDDD ≥ 1.8 V for Temp > 0 °C)
–
–
15
µs
200 mV overdrive
Min
Typ
Max
Units
–5
±1
+5
°C
Min
Typ
Max
Units
bits
Temperature Sensor
Table 11. Temperature Sensor Specifications
Spec ID#
SID93
Parameter
TSENSACC
Description
Temperature sensor accuracy
Details/Conditions
–40 to +85 °C
SAR ADC
Table 12. SAR ADC DC Specifications
Spec ID#
Parameter
Description
Details/Conditions
SID94
A_RES
Resolution
–
–
12
SID95
A_CHNIS_S
Number of channels - single ended
–
–
8
8 full speed
SID96
A-CHNKS_D
Number of channels - differential
–
–
4
Diff inputs use
neighboring I/O
SID97
A-MONO
Monotonicity
–
–
–
Yes. Based on
characterization
SID98
A_GAINERR
Gain error
–
–
±0.1
%
With external
reference.
Guaranteed by
characterization
SID99
A_OFFSET
Input offset voltage
–
–
2
mV
Measured with 1-V
VREF. Guaranteed by
characterization
SID100
A_ISAR
Current consumption
–
–
1
mA
SID101
A_VINS
Input voltage range - single ended
VSS
–
VDDA
V
Based on device
characterization
SID102
A_VIND
Input voltage range - differential
VSS
–
VDDA
V
Based on device
characterization
SID103
A_INRES
Input resistance
–
–
2.2
KΩ
Based on device
characterization
SID104
A_INCAP
Input capacitance
–
–
10
pF
Based on device
characterization
Document Number: 001-93576 Rev. *F
Page 19 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Table 13. SAR ADC AC Specifications (Guaranteed by Characterization)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID106
A_PSRR
Power supply rejection ratio
70
–
–
dB
SID107
A_CMRR
Common mode rejection ratio
66
–
–
dB
SID108
A_SAMP_1
Sample rate with external reference
bypass cap
–
–
1
Msps
SID108A
A_SAMP_2
Sample rate with no bypass cap.
Reference = VDD
–
–
806
Ksps
SID108B
A_SAMP_3
Sample rate with no bypass cap. Internal
reference
–
–
100
Ksps
SID109
A_SNDR
Signal-to-noise and distortion ratio
(SINAD)
65
–
–
dB
SID111
A_INL
Integral non linearity
–1.7
–
+2
LSB
VDD = 1.71 to 5.5, 806
Ksps, Vref = 1 to 5.5.
–40 °C ≤ TA ≤ 85 °C
–1.9
–
+2
LSB
VDD = 1.71 to 5.5, 806
Ksps, Vref = 1 to 5.5.
–40 °C ≤ TA ≤ 105 °C
–1.5
–
+1.7
LSB
VDDD = 1.71 to 3.6,
806 Ksps, Vref = 1.71
to VDDD. –40 °C ≤ TA
≤ 85 °C
–1.9
–
+2
LSB
VDDD = 1.71 to 3.6,
806 Ksps, Vref = 1.71
to VDDD. –40 °C ≤ TA
≤ 105 °C
–1.5
–
+1.7
LSB
VDDD = 1.71 to 5.5,
500 Ksps, Vref = 1 to
5.5.
–1
–
+2.2
LSB
VDDD = 1.71 to 5.5,
806 Ksps, Vref = 1 to
5.5. –40 °C ≤ TA ≤
85 °C
–1
–
+2.3
LSB
VDDD = 1.71 to 5.5,
806 Ksps, Vref = 1 to
5.5. –40 °C ≤ TA ≤
105 °C
–1
–
+2
LSB
VDDD = 1.71 to 3.6,
806 Ksps, Vref = 1.71
to VDDD. –40 °C ≤ TA
≤ 85 °C
–1
–
+2.2
LSB
VDDD = 1.71 to 3.6,
806 Ksps, Vref = 1.71
to VDDD. –40 °C ≤ TA
≤ 105 °C
VDDD = 1.71 to 5.5,
500 Ksps, Vref = 1 to
5.5.
SID111A
A_INL
Integral non linearity
SID111B
A_INL
Integral non linearity
SID112
A_DNL
Differential non linearity
SID112A
A_DNL
Differential non linearity
SID112B
A_DNL
Differential non linearity
–1
–
+2.2
LSB
SID113
A_THD
Total harmonic distortion
–
–
–65
dB
Document Number: 001-93576 Rev. *F
Measured at 1 V
FIN = 10 kHz
FIN = 10 kHz.
Page 20 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
CSD
Table 14. CSD Block Specification
Spec ID#
Parameter
Description
CSD Specification
SID308
VCSD
Voltage range of operation
SID309
DNL for 8-bit resolution
IDAC1
Min
Typ
Max
Units
1.71
–
5.5
V
–1
–
1
LSB
SID310
IDAC1
INL for 8-bit resolution
–3
–
3
LSB
SID311
IDAC2
DNL for 7-bit resolution
–1
–
1
LSB
Details/
Conditions
SID312
IDAC2
INL for 7-bit resolution
–3
–
3
LSB
SID313
SNR
Ratio of counts of finger to noise. Guaranteed
by characterization
5
–
–
Ratio Capacitance range of 9 to
35 pF, 0.1 pF sensitivity
SID314
IDAC1_CRT1
Output current of Idac1 (8-bits) in High range
–
612
–
µA
SID314A
IDAC1_CRT2
Output current of Idac1(8-bits) in Low range
–
306
–
µA
SID315
IDAC2_CRT1
Output current of Idac2 (7-bits) in High range
–
304.8
–
µA
SID315A
IDAC2_CRT2
Output current of Idac2 (7-bits) in Low range
–
152.4
–
µA
Digital Peripherals
The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode.
Timer/Counter/PWM
Table 15. TCPWM Specifications
(Guaranteed by Characterization)
Spec ID
SID.TCPWM.1
Parameter
ITCPWM1
Description
Block current consumption at 3 MHz
Min
–
Typ
–
Max
45
SID.TCPWM.2
ITCPWM2
Block current consumption at 12 MHz
–
–
155
SID.TCPWM.2A ITCPWM3
Block current consumption at 48 MHz
–
–
650
–
–
Fc
SID.TCPWM.3
TCPWMFREQ Operating frequency
SID.TCPWM.4
TPWMENEXT Input Trigger Pulse Width for all
Trigger Events
2/Fc
–
–
SID.TCPWM.5
TPWMEXT
Output Trigger Pulse widths
2/Fc
–
–
SID.TCPWM.5A TCRES
Resolution of Counter
1/Fc
–
–
SID.TCPWM.5B PWMRES
PWM Resolution
1/Fc
–
–
SID.TCPWM.5C QRES
Quadrature inputs resolution
1/Fc
–
–
Document Number: 001-93576 Rev. *F
Units
Details/Conditions
µA All modes
(Timer/Counter/PWM)
µA All modes
(Timer/Counter/PWM)
µA All modes
(Timer/Counter/PWM)
MHz Fc max = Fcpu.
Maximum = 24 MHz
ns Trigger Events can be Stop,
Start, Reload, Count,
Capture, or Kill depending
on which mode of operation
is selected.
ns Minimum possible width of
Overflow, Underflow, and
CC (Counter equals
Compare value) trigger
outputs
ns Minimum time between
successive counts
ns Minimum pulse width of
PWM Output
ns Minimum pulse width
between Quadrature phase
inputs.
Page 21 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
I2C
Table 16. Fixed I2C DC Specifications (Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ
Max
Units
SID149
II2C1
Block current consumption at 100 kHz
–
–
50
µA
SID150
II2C2
Block current consumption at 400 kHz
–
–
135
µA
SID151
II2C3
Block current consumption at 1 Mbps
–
–
310
µA
SID152
II2C4
I2C enabled in Deep Sleep mode
–
–
1.4
µA
Min
Typ
Max
Units
–
–
1
Mbps
Details/Conditions
Table 17. Fixed I2C AC Specifications (Guaranteed by Characterization)
Spec ID
SID153
Parameter
FI2C1
Description
Bit rate
Details/Conditions
LCD Direct Drive
Table 18. LCD Direct Drive DC Specifications (Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID154
ILCDLOW
Operating current in low power mode
–
5
–
µA
16 × 4 small segment
disp. at 50 Hz
SID155
CLCDCAP
LCD capacitance per segment/common
driver
–
500
5000
pF
Guaranteed by Design
SID156
LCDOFFSET
Long-term segment offset
–
20
–
mV
SID157
ILCDOP1
PWM Mode current. 5-V bias.
24-MHz IMO. 25 °C
–
0.6
–
mA
32 × 4 segments.
50 Hz
SID158
ILCDOP2
PWM Mode current. 3.3-V bias.
24-MHz IMO. 25 °C
–
0.5
–
mA
32 × 4 segments.
50 Hz
Table 19. LCD Direct Drive AC Specifications (Guaranteed by Characterization)
Spec ID
SID159
Parameter
FLCD
Description
LCD frame rate
Min
Typ
Max
Units
10
50
150
Hz
Details/Conditions
Table 20. Fixed UART DC Specifications (Guaranteed by Characterization)
Min
Typ
Max
Units
SID160
Spec ID
IUART1
Parameter
Block current consumption at
100 Kbits/sec
Description
–
–
55
µA
SID161
IUART2
Block current consumption at
1000 Kbits/sec
–
–
312
µA
Details/Conditions
Table 21. Fixed UART AC Specifications (Guaranteed by Characterization)
Spec ID
SID162
Parameter
FUART
Document Number: 001-93576 Rev. *F
Description
Bit rate
Min
Typ
Max
Units
–
–
1
Mbps
Page 22 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
SPI Specifications
Table 22. Fixed SPI DC Specifications (Guaranteed by Characterization)
Spec ID
Parameter
Description
Min
Typ
Max
Units
SID163
ISPI1
Block current consumption at 1 Mbits/sec
–
–
360
µA
SID164
ISPI2
Block current consumption at 4 Mbits/sec
–
–
560
µA
SID165
ISPI3
Block current consumption at 8 Mbits/sec
–
–
600
µA
Min
Typ
Max
Units
–
–
4
MHz
Min
Typ
Max
Units
Table 23. Fixed SPI AC Specifications (Guaranteed by Characterization)
Spec ID
SID166
Parameter
FSPI
Description
SPI operating frequency (master; 6X
oversampling)
Table 24. Fixed SPI Master mode AC Specifications (Guaranteed by Characterization)
Spec ID
Parameter
Description
SID167
TDMO
MOSI valid after Sclock driving edge
–
–
15
ns
SID168
TDSI
MISO valid before Sclock capturing edge. Full
clock, late MISO Sampling used
20
–
–
ns
SID169
THMO
Previous MOSI data hold time with respect to
capturing edge at Slave
0
–
–
ns
Table 25. Fixed SPI Slave mode AC Specifications (Guaranteed by Characterization)
Min
Typ
Max
Units
SID170
Spec ID
TDMI
Parameter
MOSI valid before Sclock capturing edge
40
–
–
ns
SID171
TDSO
MISO valid after Sclock driving edge
–
–
42 + (3 ×
Tscbclk)
ns
SID171A
TDSO_ext
MISO valid after Sclock driving edge in Ext.
Clock mode
–
–
48
ns
SID172
THSO
Previous MISO data hold time
0
–
–
ns
SID172A
TSSELSCK
SSEL Valid to first SCK Valid edge
100
–
–
ns
Document Number: 001-93576 Rev. *F
Description
Page 23 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Memory
Table 26. Flash DC Specifications
Spec ID
SID173
Parameter
VPE
Description
Erase and program voltage
Min
Typ
Max
Units
1.71
–
5.5
V
Details/Conditions
Table 27. Flash AC Specifications
Spec ID
SID174
Parameter
[3]
TROWWRITE
Description
Min
Typ
Max
Units
Details/Conditions
Row (block) write time (erase and
program)
–
–
20
ms
Row (block) = 128 bytes. –40
°C ≤ TA ≤ 85 °C
–
–
26
ms
Row (block) = 128 bytes. –40
°C ≤ TA ≤ 105 °C
SID175
TROWERASE[3]
–
–
13
ms
SID176
TROWPROGRAM[3] Row program time after erase
–
–
7
ms
–40 °C ≤ TA ≤ 85 °C
–
–
13
ms
–40 °C ≤ TA ≤ 105 °C
SID178
TBULKERASE[3]
Bulk erase time (32 KB)
–
–
35
ms
SID180
TDEVPROG[3]
Total device program time
SID181
FEND
Flash endurance
SID182
FRET
SID182A
SID182B
FRETQ
Row erase time
–
–
7
seconds Guaranteed by characterization
100 K
–
–
cycles Guaranteed by characterization
Flash retention. TA ≤ 55 °C, 100 K
P/E cycles
20
–
–
years
Guaranteed by characterization
Flash retention. TA ≤ 85 °C, 10 K
P/E cycles
10
–
–
years
Guaranteed by characterization
Flash retention. TA ≤ 105 °C,
10K P/E cycles, < three years at
TA > 85 °C.
10
20
–
Min
Typ
Max
Units
Details/Conditions
Guaranteed by characterization.
System Resources
Power-on-Reset (POR) with Brown Out
Table 28. Imprecise Power On Reset (PRES)
Spec ID
Parameter
Description
SID185
VRISEIPOR
Rising trip voltage
0.80
–
1.45
V
Guaranteed by characterization
SID186
VFALLIPOR
Falling trip voltage
0.75
–
1.4
V
Guaranteed by characterization
SID187
VIPORHYST
Hysteresis
15
–
200
mV
Guaranteed by characterization
Min
Typ
Max
Units
Details/Conditions
Table 29. Precise Power On Reset (POR)
Spec ID
Parameter
Description
SID190
VFALLPPOR
BOD trip voltage in active and
sleep modes
1.64
–
–
V
Full functionality between 1.71 V
and BOD trip voltage is
guaranteed by characterization
SID192
VFALLDPSLP
BOD trip voltage in Deep Sleep
1.4
–
–
V
Guaranteed by characterization
BID55
Svdd
Maximum power supply ramp
rate
–
–
67
kV/sec
Note
3. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
Document Number: 001-93576 Rev. *F
Page 24 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Voltage Monitors
Table 30. Voltage Monitors DC Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID195
VLVI1
LVI_A/D_SEL[3:0] = 0000b
1.71
1.75
1.79
V
SID196
VLVI2
LVI_A/D_SEL[3:0] = 0001b
1.76
1.80
1.85
V
SID197
VLVI3
LVI_A/D_SEL[3:0] = 0010b
1.85
1.90
1.95
V
SID198
VLVI4
LVI_A/D_SEL[3:0] = 0011b
1.95
2.00
2.05
V
SID199
VLVI5
LVI_A/D_SEL[3:0] = 0100b
2.05
2.10
2.15
V
SID200
VLVI6
LVI_A/D_SEL[3:0] = 0101b
2.15
2.20
2.26
V
SID201
VLVI7
LVI_A/D_SEL[3:0] = 0110b
2.24
2.30
2.36
V
SID202
VLVI8
LVI_A/D_SEL[3:0] = 0111b
2.34
2.40
2.46
V
SID203
VLVI9
LVI_A/D_SEL[3:0] = 1000b
2.44
2.50
2.56
V
SID204
VLVI10
LVI_A/D_SEL[3:0] = 1001b
2.54
2.60
2.67
V
SID205
VLVI11
LVI_A/D_SEL[3:0] = 1010b
2.63
2.70
2.77
V
SID206
VLVI12
LVI_A/D_SEL[3:0] = 1011b
2.73
2.80
2.87
V
SID207
VLVI13
LVI_A/D_SEL[3:0] = 1100b
2.83
2.90
2.97
V
SID208
VLVI14
LVI_A/D_SEL[3:0] = 1101b
2.93
3.00
3.08
V
SID209
VLVI15
LVI_A/D_SEL[3:0] = 1110b
3.12
3.20
3.28
V
SID210
VLVI16
LVI_A/D_SEL[3:0] = 1111b
4.39
4.50
4.61
V
SID211
LVI_IDD
Block current
–
–
100
µA
Min
Typ
Max
Units
–
–
1
µs
Min
Typ
Max
Units
Details/Conditions
Guaranteed by
characterization
Table 31. Voltage Monitors AC Specifications
Spec ID
SID212
Parameter
TMONTRIP
Description
Voltage monitor trip time
Details/Conditions
Guaranteed by
characterization
SWD Interface
Table 32. SWD Interface Specifications
Spec ID
Parameter
Description
SID213
F_SWDCLK1
3.3 V ≤ VDD ≤ 5.5 V
–
–
14
MHz
SWDCLK ≤ 1/3 CPU
clock frequency
SID214
F_SWDCLK2
1.71 V ≤ VDD ≤ 3.3 V
–
–
7
MHz
SWDCLK ≤ 1/3 CPU
clock frequency
SID215
T_SWDI_SETUP T = 1/f SWDCLK
0.25*T
–
–
ns
Guaranteed by
characterization
SID216
T_SWDI_HOLD
0.25*T
–
–
ns
Guaranteed by
characterization
SID217
T_SWDO_VALID T = 1/f SWDCLK
–
–
0.5*T
ns
Guaranteed by
characterization
SID217A
T_SWDO_HOLD T = 1/f SWDCLK
1
–
–
ns
Guaranteed by
characterization
T = 1/f SWDCLK
Document Number: 001-93576 Rev. *F
Page 25 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Internal Main Oscillator
Table 33. IMO DC Specifications (Guaranteed by Design)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID219
IIMO2
IMO operating current at 24 MHz
–
–
325
µA
SID220
IIMO3
IMO operating current at 12 MHz
–
–
225
µA
SID221
IIMO4
IMO operating current at 6 MHz
–
–
180
µA
SID222
IIMO5
IMO operating current at 3 MHz
–
–
150
µA
Min
Typ
Max
Units
Details/Conditions
+3% if TA > 85 °C and
IMO frequency <
24 MHz
Table 34. IMO AC Specifications
Spec ID
Parameter
Description
SID223
FIMOTOL1
Frequency variation from 3 to
24 MHz
–
–
±2
%
SID226
TSTARTIMO
IMO startup time
–
–
12
µs
SID227
TJITRMSIMO1
RMS Jitter at 3 MHz
–
156
–
ps
SID228
TJITRMSIMO2
RMS Jitter at 24 MHz
–
145
–
ps
Internal Low-Speed Oscillator
Table 35. ILO DC Specifications (Guaranteed by Design)
Min
Typ
Max
Units
SID231
Spec ID
IILO1
Parameter
ILO operating current at 32 kHz
Description
–
0.3
1.05
µA
Guaranteed by
Characterization
Details/Conditions
SID233
IILOLEAK
ILO leakage current
–
2
15
nA
Guaranteed by
Design
Min
–
Typ
–
Max
2
Units
ms
Table 36. ILO AC Specifications
Spec ID
SID234
Parameter
TSTARTILO1
Description
ILO startup time
SID236
TILODUTY
ILO duty cycle
40
50
60
%
SID237
FILOTRIM1
32 kHz trimmed frequency
15
32
50
kHz
Min
Typ
Max
Units
Details/Conditions
Guaranteed by characterization
Guaranteed by characterization
Max. ILO frequency is
70 kHz if TA > 85 °C
Table 37. External Clock Specifications
Spec ID
Parameter
Description
Details/Conditions
SID305
ExtClkFreq
External Clock input Frequency
0
–
24
MHz
Guaranteed by
characterization
SID306
ExtClkDuty
Duty cycle; Measured at VDD/2
45
–
55
%
Guaranteed by
characterization
Document Number: 001-93576 Rev. *F
Page 26 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Table 38. Block Specs
Spec ID
Parameter
Description
Min
Typ
Max
SID257
TWS24*
Number of wait states at 24 MHz
0
–
–
SID260
VREFSAR
Trimmed internal reference to SAR
–1
–
+1
SID262
TCLKSWITCH
Clock switching from clk1 to clk2 in
clk1 periods
3
–
4
Units
Details/Conditions
CPU execution from
Flash. Guaranteed by
characterization
%
Percentage of Vbg
(1.024 V). Guaranteed
by characterization
Periods Guaranteed by design
* Tws24 is guaranteed by design.
Document Number: 001-93576 Rev. *F
Page 27 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Ordering Information
The PSoC 4100 part numbers and features are listed in the Table 39.
Table 39. PSoC 4100 Family Ordering Information
SRAM (KB)
UDB
Opamp (CTBm)
CapSense
Direct LCD Drive
LP Comparators
TCPWM Blocks
SCB Blocks
GPIO
28-SSOP
–40 to +85 °C
–40 to +105 °C
24
16
4
–
1
✔
✔ 806 Ksps 2
4
2
24
✔
✔
–
CY8C4125PVA-482Z
24
32
4
–
1
✔
✔ 806 Ksps 2
4
2
24
✔
✔
–
CY8C4124PVS-442Z
24
16
4
–
1
✔
✔ 806 Ksps 2
4
2
24
✔
–
✔
CY8C4125PVS-482Z
24
32
4
–
1
✔
✔ 806 Ksps 2
4
2
24
✔
–
✔
MPN
12-bit SAR ADC
Flash (KB)
Operating
Temperature
CY8C4124PVA-442Z
Family
4100
Package
Max CPU Speed (MHz)
Features
Part Numbering Conventions
PSoC 4 devices follow the part numbering convention described in the following table. All fields are single-character alphanumeric (0,
1, 2, …, 9, A,B, …, Z) unless stated otherwise.
The part numbers are of the form CY8C4ABCDEF-GHI where the fields are defined as follows.
Example
CY8C
4 A B C
DE
F - GH I
Z
Cypress Prefix
4 : PSoC 4
1 : 4100 Family
2 : 24 MHz
Architecture
Family within Architecture
Speed Grade
5 : 32 KB
Flash Capacity
PV : SSOP
Package Code
A: Automotive -40 to +85 °C
S: Automotive: -40 to +105 °C
Temperature Range
Attributes Set
Fab Location Change: Z
Document Number: 001-93576 Rev. *F
Page 28 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
The field values are listed in Table 40.
Table 40. Field Values
Field
CY8C
Description
Values
Meaning
Cypress Prefix
4
Architecture
4
PSoC 4
A
Family within architecture
1
4100 Family
2
4200 Family
B
CPU Speed
2
24 MHz
4
48 MHz
C
Flash Capacity
4
16 KB
5
32 KB
DE
Package Code
PV
SSOP
F
GHI
Z
Temperature Range
A/S
Attributes Code
Automotive
000-999
Code of feature set in specific family
Fab location change
Packaging
Table 41. Package Characteristics
Parameter
Description
Conditions
Min
Typ
Max
Units
TA
Operating ambient temperature
For A grade devices
–40
25.00
85
°C
TA
Operating ambient temperature
For S grade devices
–40
25.00
105
°C
TJ
Operating junction temperature
For A grade devices
–40
–
100
°C
TJ
Operating junction temperature
For S grade devices
–40
–
120
°C
TJA
Package θJA (28-pin SSOP)
–
66.58
–
°C/W
TJC
Package θJC (28-pin SSOP)
–
46.28
–
°C/W
Table 42. Solder Reflow Peak Temperature
Package
Maximum Peak Temperature
Maximum Time at Peak Temperature
28-pin SSOP
260 °C
30 seconds
Table 43. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
28-pin SSOP
MSL 3
PSoC4 CAB Libraries with Schematics Symbols and PCB Footprints are on the
http://www.cypress.com/cad-resources/psoc-4-cad-libraries?source=search&cat=technical_documents
Document Number: 001-93576 Rev. *F
Cypress
web
site
at
Page 29 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Figure 6. 28-pin SSOP (210 Mils) Package Outline
51-85079 *F
Document Number: 001-93576 Rev. *F
Page 30 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Acronyms
Table 44. Acronyms Used in this Document (continued)
Acronym
Table 44. Acronyms Used in this Document
Acronym
Description
abus
analog local bus
ADC
analog-to-digital converter
AG
analog global
AHB
AMBA (advanced microcontroller bus architecture) high-performance bus, an ARM data
transfer bus
ALU
arithmetic logic unit
AMUXBUS
API
Description
ETM
embedded trace macrocell
FIR
finite impulse response, see also IIR
FPB
flash patch and breakpoint
FS
full-speed
GPIO
general-purpose input/output, applies to a PSoC
pin
HVI
high-voltage interrupt, see also LVI, LVD
IC
integrated circuit
analog multiplexer bus
IDAC
current DAC, see also DAC, VDAC
application programming interface
IDE
integrated development environment
APSR
application program status register
2C,
ARM®
advanced RISC machine, a CPU architecture
ATM
automatic thump mode
BW
bandwidth
CAN
Controller Area Network, a communications
protocol
CMRR
I
or IIC
IIR
Inter-Integrated Circuit, a communications
protocol
infinite impulse response, see also FIR
ILO
internal low-speed oscillator, see also IMO
IMO
internal main oscillator, see also ILO
INL
integral nonlinearity, see also DNL
common-mode rejection ratio
I/O
input/output, see also GPIO, DIO, SIO, USBIO
CPU
central processing unit
IPOR
initial power-on reset
CRC
cyclic redundancy check, an error-checking
protocol
IPSR
interrupt program status register
DAC
digital-to-analog converter, see also IDAC, VDAC
IRQ
interrupt request
DFB
digital filter block
ITM
instrumentation trace macrocell
DIO
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
DMIPS
Dhrystone million instructions per second
DMA
direct memory access, see also TD
DNL
differential nonlinearity, see also INL
DNU
do not use
DR
port write data registers
DSI
digital system interconnect
DWT
data watchpoint and trace
ECC
error correcting code
ECO
external crystal oscillator
EEPROM
electrically erasable programmable read-only
memory
EMI
electromagnetic interference
EMIF
external memory interface
EOC
end of conversion
EOF
end of frame
EPSR
execution program status register
ESD
electrostatic discharge
Document Number: 001-93576 Rev. *F
LCD
liquid crystal display
LIN
Local Interconnect Network, a communications
protocol.
LR
link register
LUT
lookup table
LVD
low-voltage detect, see also LVI
LVI
low-voltage interrupt, see also HVI
LVTTL
low-voltage transistor-transistor logic
MAC
multiply-accumulate
MCU
microcontroller unit
MISO
master-in slave-out
NC
no connect
NMI
nonmaskable interrupt
NRZ
non-return-to-zero
NVIC
nested vectored interrupt controller
NVL
nonvolatile latch, see also WOL
opamp
operational amplifier
PAL
programmable array logic, see also PLD
PC
program counter
PCB
printed circuit board
Page 31 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Table 44. Acronyms Used in this Document (continued)
Acronym
Description
Table 44. Acronyms Used in this Document (continued)
Acronym
Description
PGA
programmable gain amplifier
THD
total harmonic distortion
PHUB
peripheral hub
TIA
transimpedance amplifier
PHY
physical layer
TRM
technical reference manual
PICU
port interrupt control unit
TTL
transistor-transistor logic
PLA
programmable logic array
TX
transmit
PLD
programmable logic device, see also PAL
UART
PLL
phase-locked loop
Universal Asynchronous Transmitter Receiver, a
communications protocol
PMDD
package material declaration data sheet
UDB
universal digital block
POR
power-on reset
USB
Universal Serial Bus
PRES
precise power-on reset
USBIO
PRS
pseudo random sequence
USB input/output, PSoC pins used to connect to
a USB port
PS
port read data register
VDAC
voltage DAC, see also DAC, IDAC
PSoC®
Programmable System-on-Chip™
WDT
watchdog timer
PSRR
power supply rejection ratio
PWM
pulse-width modulator
RAM
random-access memory
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
RTL
register transfer language
RTR
remote transmission request
RX
receive
SAR
successive approximation register
SC/CT
switched capacitor/continuous time
SCL
I2C serial clock
SDA
I2C serial data
S/H
sample and hold
SINAD
signal to noise and distortion ratio
SIO
special input/output, GPIO with advanced
features. See GPIO.
SOC
start of conversion
SOF
start of frame
SPI
Serial Peripheral Interface, a communications
protocol
SR
slew rate
SRAM
static random access memory
SRES
software reset
SWD
serial wire debug, a test protocol
SWV
single-wire viewer
TD
transaction descriptor, see also DMA
Document Number: 001-93576 Rev. *F
WOL
write once latch, see also NVL
WRES
watchdog timer reset
XRES
external reset I/O pin
XTAL
crystal
Page 32 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Document Conventions
Units of Measure
Table 45. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
dB
decibel
fF
femto farad
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohour
kHz
kilohertz
kΩ
kilo ohm
Ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
MΩ
mega-ohm
Msps
megasamples per second
µA
microampere
µF
microfarad
µH
microhenry
µs
microsecond
µV
microvolt
µW
microwatt
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
nV
nanovolt
Ω
ohm
pF
picofarad
ppm
parts per million
ps
picosecond
s
second
sps
samples per second
sqrtHz
square root of hertz
V
volt
Document Number: 001-93576 Rev. *F
Page 33 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Document History Page
Document Title: Automotive PSoC® 4: PSoC 4100 Family Datasheet Programmable System-on-Chip (PSoC®)
Document Number: 001-93576
Revision
ECN
Orig. of
Change
Submission
Date
*B
5071385
THOR /
KIKU
01/21/2016
Changed status from Preliminary to Final.
*C
5117912
MVRE
01/31/2016
Updated Features:
Updated Programmable Analog:
Replaced “Two opamps” with “One opamp”.
Updated Block Diagram:
Replaced “2x” with “1x”.
Updated Functional Overview:
Updated Analog Blocks:
Updated Opamp (CTBm Block):
Replaced “Two opamps” with “Opamp” in heading.
Updated description.
Updated Power:
Updated Unregulated External Supply:
Updated Table 1:
Updated details in “Bypass Capacitors” column corresponding to “VDDD–VSS”
and “VCCD–VSS” power supplies.
*D
5331416
MVRE
07/04/2016
Updated Functional Overview:
Updated CPU and Memory Subsystem:
Updated Flash:
Updated description.
Updated Fixed Function Digital:
Updated Serial Communication Blocks (SCB):
Updated description.
Updated Pinouts:
Updated description.
Updated Figure 3.
Updated Power:
Added Figure 4.
Updated Unregulated External Supply:
Updated Table 1:
Updated details in “Bypass Capacitors” column corresponding to “VDDD–VSS”
and “VREF–VSS (optional)” Power Supply.
Document Number: 001-93576 Rev. *F
Description of Change
Page 34 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Document History Page (continued)
Document Title: Automotive PSoC® 4: PSoC 4100 Family Datasheet Programmable System-on-Chip (PSoC®)
Document Number: 001-93576
Revision
ECN
Orig. of
Change
Submission
Date
Description of Change
*D (cont.)
5331416
MVRE
07/04/2016
Updated Electrical Specifications:
Updated Device-Level Specifications:
Updated Table 3:
Updated entire table.
Updated Analog Peripherals:
Updated Opamp:
Updated Table 8:
Updated values in “Typ” and “Max” columns for IDD_HI, IDD_MED, IDD_LOW
parameters.
Updated details in “Details/Conditions” column corresponding to “SID290”
Spec ID and “VOS_DR_TR” parameter.
Added SID290Q Spec ID corresponding to VOS_DR_TR parameter and its
details.
Added SID299A Spec ID corresponding to OL_GAIN parameter and its details.
Updated Comparator:
Updated Table 9:
Updated details in “Description”, “Min”, “Typ”, “Max” columns corresponding to
“ICMP1”, “ICMP2” and “ICMP3” parameters.
Updated Table 10:
Updated details in “Description”, “Min”, “Typ”, “Max” columns corresponding to
“TRESP1”, “TRESP2” and “TRESP3” parameters.
Updated Digital Peripherals:
Removed “Timer”.
Removed “Counter”.
Removed “Pulse Width Modulation (PWM)”.
Added Timer/Counter/PWM.
Updated I2C:
Updated Table 16:
Changed maximum value of II2C1 parameter from 10.5 μA to 50 μA.
Updated LCD Direct Drive:
Updated Table 20:
Changed maximum value of IUART1 parameter from 9 μA to 55 μA.
Updated SPI Specifications:
Updated Table 25:
Replaced “FCPU” with “Tscbclk” in “Max” column corresponding to TDSO
parameter.
Updated Memory:
Updated Table 27:
Added FRETQ parameter and its details.
Document Number: 001-93576 Rev. *F
Page 35 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Document History Page (continued)
Document Title: Automotive PSoC® 4: PSoC 4100 Family Datasheet Programmable System-on-Chip (PSoC®)
Document Number: 001-93576
Revision
ECN
Orig. of
Change
Submission
Date
*D (cont.)
5331416
MVRE
07/04/2016
Updated Electrical Specifications:
Updated System Resources:
Updated Power-on-Reset (POR) with Brown Out:
Updated Table 29:
Updated details in “Details/Conditions” column corresponding to VFALLPPOR
parameter.
Added Svdd parameter and its details.
Updated Internal Main Oscillator:
Updated Table 34:
Updated details in “Details/Conditions” column corresponding to FIMOTOL1
parameter.
Updated Internal Low-Speed Oscillator:
Updated Table 36:
Updated details in “Details/Conditions” column corresponding to FILOTRIM1
parameter.
Updated Packaging:
Updated description.
Updated to new template.
Completing Sunset Review.
*E
5675099
SNPR
03/28/2017
Updated Ordering Information:
Updated part numbers.
Updated to new template.
*F
5751084
SNPR
05/26/2017
No technical updates.
Completing Sunset Review.
Document Number: 001-93576 Rev. *F
Description of Change
Page 36 of 37
Automotive PSoC® 4: PSoC 4100
Family Datasheet
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
ARM® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Forums | WICED IOT Forums | Projects | Video | Blogs | Training
| Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2014-2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document,
including any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries
worldwide. Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other
intellectual property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress
hereby grants you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to
modify and reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users
(either directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as
provided by Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation
of the Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. To the extent
permitted by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any
product or circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is
the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. Cypress products
are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of weapons, weapons systems, nuclear installations, life-support devices or
systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or hazardous substances management, or other uses where the failure of the
device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any component of a device or system whose failure to perform can be reasonably
expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim,
damage, or other liability arising from or related to all Unintended Uses of Cypress products. You shall indemnify and hold Cypress harmless from and against all claims, costs, damages, and other
liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in the United
States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 001-93576 Rev. *F
Revised May 26, 2017
Page 37 of 37
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