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to offer the product to new and existing customers as part of the Infineon product
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Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
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Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Programmable System-on-Chip (PSoC)
General Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
Arm® Cortex™-M0+ CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing.
PSoC 4100S Plus 256KB is a member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard
communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, programmable
general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC 4100S Plus 256KB
products are upward compatible with members of the PSoC 4 platform for new applications and design needs.
Features
32-bit MCU Subsystem
Timing and Pulse-Width Modulation
■
48-MHz Arm Cortex-M0+ CPU with single-cycle multiply
■
Up to 256 KB of flash with Read Accelerator
■
■
■
Eight 16-bit timer/counter/pulse-width modulator (TCPWM)
blocks
Up to 32 KB of SRAM
■
Center-aligned, Edge, and Pseudo-random modes
8-channel DMA engine
■
Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
■
Quadrature decoder
Programmable Analog
■
Two opamps with reconfigurable high-drive external and
high-bandwidth internal drive and Comparator modes and ADC
input buffering capability. Opamps can operate in Deep Sleep
low-power mode.
■
12-bit 1-Msps SAR ADC with differential and single-ended
modes, and Channel Sequencer with signal averaging
■
Single-slope 10-bit ADC function provided by a capacitance
sensing block
■
Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
■
Two low-power comparators that operate in Deep Sleep
low-power mode
Clock Sources
■
4 to 33 MHz external crystal oscillator (ECO)
■
PLL to generate 48-MHz frequency
■
32-kHz Watch Crystal Oscillator (WCO)
■
±2% Internal Main Oscillator (IMO)
■
40-kHz Internal Low-power Oscillator (ILO)
Up to 54 Programmable GPIO Pins
■
48-pin TQFP (0.5-mm pitch), and 64-pin TQFP normal
(0.8 mm) and Fine Pitch (0.5 mm) packages
■
Any GPIO pin can be CapSense, analog, or digital
■
Drive modes, strengths, and slew rates are programmable
Programmable Digital
■
Programmable logic blocks allowing Boolean operations to be
performed on port inputs and outputs
ModusToolbox™ Software
Low-Power 1.71-V to 5.5-V Operation
■
Deep Sleep mode with operational analog and 2.5-µA digital
system current
Capacitive Sensing
■
Cypress CapSense Sigma-Delta (CSD) provides best-in-class
signal-to-noise ratio (SNR) (>5:1) and water tolerance
■
Cypress-supplied software component makes capacitive
sensing design easy
■
Automatic hardware tuning (SmartSense™)
LCD Drive Capability
■
Comprehensive collection of multi-platform tools and software
libraries
■
Includes board support packages (BSPs), peripheral driver
library (PDL), and middleware such as CapSense
PSoC Creator Design Environment
■
Integrated development environment (IDE) provides schematic
design entry and build, with analog and digital automatic routing
■
Application programming interface (API) Components for all
fixed-function and programmable peripherals
Industry-Standard Tool Compatibility
LCD segment drive capability on GPIOs
Serial Communication
■
■
■
Five
independent
run-time
reconfigurable
Serial
Communication Blocks (SCBs) with re-configurable I2C, SPI,
or UART functionality
Cypress Semiconductor Corporation
Document Number: 002-26566 Rev. *C
•
198 Champion Court
After schematic entry, development can be done with
Arm-based industry-standard development tools
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 10, 2020
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Development Ecosystem
PSoC 4 MCU Resources
Cypress provides a wealth of data at www.cypress.com to help you select the right PSoC device and quickly and effectively integrate
it into your design. The following is an abbreviated, hyperlinked list of resources for PSoC 4 MCU:
■
Overview: PSoC Portfolio, PSoC Roadmap
■
Product Selectors: PSoC 4 MCU
■
Application Notes cover a broad range of topics, from basic
to advanced level, and include the following:
❐ AN79953: Getting Started With PSoC 4. This application note
has a convenient flow chart to help decide which IDE to use:
ModusToolbox™ Software or PSoC Creator.
❐ AN91184: PSoC 4 BLE - Designing BLE Applications
❐ AN88619: PSoC 4 Hardware Design Considerations
❐ AN73854: Introduction To Bootloaders
❐ AN89610: Arm Cortex Code Optimization
❐ AN86233: PSoC 4 MCU Power Reduction Techniques
❐ AN57821: Mixed Signal Circuit Board Layout
❐ AN85951: PSoC 4, PSoC 6 CapSense Design Guide
■
Code Examples demonstrate product features and usage, and
are also available on Cypress GitHub repositories.
■
Technical Reference Manuals (TRMs) provide detailed
descriptions of PSoC 4 MCU architecture and registers.
Document Number: 002-26566 Rev. *C
■
PSoC 4 MCU Programming Specification provides the
information necessary to program PSoC 4 MCU nonvolatile
memory.
■
Development Tools
❐ ModusToolbox™ Software enables cross platform code
development with a robust suite of tools and software
libraries.
❐ PSoC Creator is a free Windows-based IDE. It enables
concurrent hardware and firmware design of PSoC 3, PSoC
4, PSoC 5LP, and PSoC 6 MCU based systems. Applications
are created using schematic capture and over 150
pre-verified, production-ready peripheral Components.
❐ CY8CKIT-149 PSoC 4100S Plus Prototyping Kit, is a
low-cost and easy-to-use evaluation platform. This kit
provides easy access to all the device I/Os in a
breadboard-compatible format.
❐ MiniProg4
and MiniProg3 all-in-one development
programmers and debuggers.
❐ PSoC 4 MCU CAD libraries provide footprint and schematic
support for common tools. IBIS models are also available.
■
Training Videos are available on a wide range of topics
including the PSoC 4 MCU 101 series.
■
Cypress Developer Community enables connection with
fellow PSoC developers around the world, 24 hours a day, 7
days a week, and hosts a dedicated PSoC 4 MCU Community.
Page 2 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
ModusToolbox™ Software
ModusToolbox Software is Cypress' comprehensive collection of multi-platform tools and software libraries that enable an immersive
development experience for creating converged MCU and wireless systems. It is:
■
Comprehensive - it has the resources you need
■
Flexible - you can use the resources in your own workflow
■
Atomic - you can get just the resources you want
Cypress provides a large collection of code repositories on GitHub, including:
■
Board Support Packages (BSPs) aligned with Cypress kits
■
Low-level resources, including a peripheral driver library (PDL)
■
Middleware enabling industry-leading features such as CapSense
■
An extensive set of thoroughly tested code example applications
ModusToolbox Software is IDE-neutral and easily adaptable to your workflow and preferred development environment. It includes a
project creator, peripheral and library configurators, a library manager, as well as the optional Eclipse IDE for ModusToolbox, as
Figure 1 shows. For information on using Cypress tools, refer to the documentation delivered with ModusToolbox software, and
AN79953: Getting Started with PSoC 4.
Figure 1. ModusToolbox Software Tools
Document Number: 002-26566 Rev. *C
Page 3 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
PSoC Creator
PSoC Creator is a free Windows-based IDE. It enables you to design hardware and firmware systems concurrently, based on PSoC
4 MCU. As Figure 2 shows, with PSoC Creator you can:
1. Explore the library of 200+ Components
2. Drag and drop Component icons to complete your hardware system design in the main design workspace
3. Configure Components using the Component configuration tools and the Component datasheets
4. Co-design your application firmware and hardware in the PSoC Creator IDE or build a project for a third-party IDE
5. Prototype your solution with the PSoC 4 Pioneer kits. If a design change is needed, PSoC Creator and Components enable you
to make changes on-the-fly without the need for hardware revisions.
Figure 2. PSoC Creator Schematic Entry and Components
Document Number: 002-26566 Rev. *C
Page 4 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Contents
Functional Definition ........................................................ 7
CPU and Memory Subsystem ..................................... 7
System Resources ...................................................... 7
Analog Blocks .............................................................. 8
Programmable Digital Blocks ...................................... 9
Fixed Function Digital Blocks ...................................... 9
GPIO ........................................................................... 9
Special Function Peripherals ..................................... 10
Pinouts ............................................................................ 11
Alternate Pin Functions ............................................. 14
Power ............................................................................... 16
Mode 1: 1.8 V to 5.5 V External Supply .................... 16
Mode 2: 1.8 V ±5% External Supply .......................... 16
Electrical Specifications ................................................ 17
Absolute Maximum Ratings ...................................... 17
Device Level Specifications ....................................... 17
Document Number: 002-26566 Rev. *C
Analog Peripherals .................................................... 21
Digital Peripherals ..................................................... 29
Memory ..................................................................... 31
System Resources .................................................... 31
Ordering Information ...................................................... 35
Packaging ........................................................................ 37
Package Diagrams .................................................... 38
Acronyms ........................................................................ 40
Document Conventions ................................................. 42
Units of Measure ....................................................... 42
Revision History ............................................................. 43
Sales, Solutions, and Legal Information ...................... 44
Worldwide Sales and Design Support ....................... 44
Products .................................................................... 44
PSoC® Solutions ...................................................... 44
Cypress Developer Community ................................. 44
Technical Support ..................................................... 44
Page 5 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Figure 3. Block Diagram
CPU Subsystem
32-bit
AHB-Lite
SWD/TC, MTB
SPCIF
Cortex
M0+
48 MHz
FLASH
256 KB
SRAM
32 KB
ROM
8 KB
DataWire/
DMA
FAST MUL
NVIC, IRQMUX, MPU
Read Accelerator
SRAM Controller
ROM Controller
Initiator/MMIO
System Resources
Lite
System Interconnect (Single Layer AHB)
SARMUX
LCD
2x LP Comparator
x1
WCO
SAR ADC
(12-bit)
5x SCB-I2C/SPI/UART
Test
TestMode Entry
Digital DFT
Analog DFT
Programmable
Analog
IOSS GPIO (8x ports)
Reset
Reset Control
XRES
EXCO (w/PLL)
Clock
Clock Control
WDT
ILO
IMO
Peripheral Interconnect (MMIO)
PCLK
CapSense
Power
Sleep Control
WIC
POR
REF
PWRSYS
8x TCPWM
PSoC 4100S Plus
256KB
CTBm
x1
2x OpAmp
High Speed I/O Matrix & 2 Ports Smart I/O
Power Modes
Active/Sleep
DeepSleep
54x GPIOs
IO Subsystem
This device includes extensive support for programming, testing,
debugging, and tracing both hardware and firmware.
The Arm Serial-Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE provides fully integrated programming
and debug support for this device. The SWD interface is fully
compatible with industry-standard third-party tools. This device
provides a level of security not possible with multi-chip
application solutions or with microcontrollers. It has the following
advantages:
■
Allows disabling of debug features
■
Robust flash protection
■
Allows customer-proprietary functionality to be implemented in
on-chip programmable blocks
Document Number: 002-26566 Rev. *C
The debug circuits are enabled by default and can be disabled
in firmware. If they are not enabled, the only way to re-enable
them is to erase the entire device, clear flash protection, and
reprogram the device with new firmware that enables debugging.
Thus firmware control of debugging cannot be over-ridden
without erasing the firmware thus providing security.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. All programming, debug, and test interfaces are
disabled when maximum device security is enabled. Therefore,
this device, with device security enabled, may not be returned for
failure analysis. This is a trade-off it allows the customer to make.
Page 6 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Functional Definition
CPU and Memory Subsystem
CPU
The Cortex-M0+ CPU in PSoC 4100S Plus 256KB is part of the
32-bit MCU subsystem, which is optimized for low-power
operation with extensive clock gating. Most instructions are 16
bits in length and the CPU executes a subset of the Thumb-2
instruction set. It includes a nested vectored interrupt controller
(NVIC) block with eight interrupt inputs and also includes a
Wakeup Interrupt Controller (WIC). The WIC can wake the
processor from Deep Sleep mode, allowing power to be switched
off to the main processor when the chip is in Deep Sleep mode.
The CPU subsystem includes an 8-channel DMA engine and
also includes a debug interface, the serial wire debug (SWD)
interface, which is a two-wire form of JTAG. The debug configuration used for PSoC 4100S Plus 256KB has four breakpoint
(address) comparators and two watchpoint (data) comparators.
Flash
The PSoC 4100S Plus 256KB device has a 256 KB flash module
with a flash accelerator, tightly coupled to the CPU to improve
average access times from the flash block. The low-power flash
block is designed to deliver two wait-state (WS) access time at
48 MHz. The flash accelerator delivers 85% of single-cycle
SRAM access performance on average.
SRAM
32 KB of SRAM are provided with zero wait-state access at
48 MHz.
SROM
An 8-KB supervisory ROM that contains boot and configuration
routines is provided.
System Resources
Power System
The power system is described in detail in the section Power. It
provides assurance that voltage levels are as required for each
respective mode and either delays mode entry (for example, on
power-on reset (POR)) until voltage levels are as required for
proper functionality, or generates resets (for example, on
brown-out detection). operates with a single external supply
over the range of either 1.8 V ±5% (externally regulated) or 1.8
to 5.5 V (internally regulated) and has three different power
modes, transitions between which are managed by the power
system. PSoC 4100S Plus 256KB provides Active, Sleep, and
Deep Sleep low-power modes.
All subsystems are operational in Active mode. The CPU
subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep
mode, while all peripherals and interrupts are active with
instantaneous wake-up on a wake-up event. In Deep Sleep
mode, the high-speed clock and associated circuitry is switched
off; wake-up from this mode takes 35 µs. The opamps can
remain operational in Deep Sleep mode.
Document Number: 002-26566 Rev. *C
Clock System
The PSoC 4100S Plus 256KB clock system is responsible for
providing clocks to all subsystems that require clocks and for
switching between different clock sources without glitching. In
addition, the clock system ensures that there are no metastable
conditions.
The clock system for the PSoC 4100S Plus 256KB consists of
the IMO, ILO, a 32-kHz Watch Crystal Oscillator (WCO), MHz
ECO and PLL, and provision for an external clock. The WCO
block allows locking the IMO to the 32-kHz oscillator.
Figure 4. MCU Clocking Architecture
IMO
Divide By
2,4,8
clk_hf
clk_ext
PLL
ECO
ILO
clk_lf
WCO
clk_hf
Prescaler
clk_sys
Peripheral
Dividers
Peripheral Clocks
Analog
Divider
SAR Clock
The HFCLK signal can be divided down as shown to generate
synchronous clocks for the Analog and Digital peripherals. There
are 18 clock dividers for the PSoC 4100S Plus 256KB (six with
fractional divide capability, twelve with integer divide only). There
are 12 16-bit dividers allowing a lot of flexibility in generating
fine-grained frequencies.
In addition, there are five 16-bit fractional dividers and one 24-bit
fractional divider.
IMO Clock Source
The IMO is the primary source of internal clocking in the PSoC
4100S Plus 256KB. It is trimmed during testing to achieve the
specified accuracy.The IMO default frequency is 24 MHz and it
can be adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO
tolerance with Cypress-provided calibration settings is ±2% over
the entire voltage and temperature range.
ILO Clock Source
The ILO is a very low power, nominally 40-kHz oscillator, which
is primarily used to generate clocks for the watchdog timer
(WDT) and peripheral operation in Deep Sleep mode. ILO-driven
counters can be calibrated to the IMO to improve accuracy.
Cypress provides a software component, which does the
calibration.
Page 7 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Watch Crystal Oscillator (WCO)
The PSoC 4100S Plus 256KB clock subsystem also implements
a low-frequency (32-kHz watch crystal) oscillator that can be
used for precision timing applications. The WCO block allows
locking the IMO to the 32 kHz oscillator.
The SAR is not available in Deep Sleep mode as it requires a
high-speed clock (up to 18 MHz). The SAR operating range is
1.71 V to 5.5 V.
Figure 5. SAR ADC
AHB System Bus and Programmable Logic
Interconnect
External Crystal Oscillators (ECO)
SAR Sequencer
The PSoC 4100S Plus 256KB also implements a 4 to 33 MHz
crystal oscillator.
Reset
vminus vplus
SARMUX
A watchdog timer is implemented in the clock block running from
the ILO; this allows watchdog operation during Deep Sleep and
generates a watchdog reset if not serviced before the set timeout
occurs. The watchdog reset is recorded in a Reset Cause
register, which is firmware readable. The Watchdog counters can
be used to implement a Real-Time clock using the 32-kHz WCO.
SARMUX Port
(Up to 16 inputs)
Watchdog Timer and Counters
Sequencing
and Control
Data and
Status Flags
POS
SARADC
NEG
Reference
Selection
VDDA /2
VDDA
External
Reference and
Bypass
(optional)
VREF
Inputs from other Ports
Opamps (Continuous-Time Block; CTB)
PSoC 4100S Plus 256KB can be reset from a variety of sources
including a software reset. Reset events are asynchronous and
guarantee reversion to a known state. The reset cause is
recorded in a register, which is sticky through reset and allows
software to determine the cause of the reset. An XRES pin is
reserved for external reset by asserting it active low. The XRES
pin has an internal pull-up resistor that is always enabled.
PSoC 4100S Plus 256KB has two opamps with Comparator
modes which allow most common analog functions to be
performed on-chip eliminating external components; PGAs,
Voltage Buffers, Filters, Trans-Impedance Amplifiers, and other
functions can be realized, in some cases with external passives.
saving power, cost, and space. The on-chip opamps are
designed with enough bandwidth to drive the Sample-and-Hold
circuit of the ADC without requiring external buffering.
Analog Blocks
Low-power Comparators (LPC)
12-bit SAR ADC
The 12-bit, 1-Msps SAR ADC can operate at a maximum clock
rate of 18 MHz and requires a minimum of 18 clocks to do a 12-bit
conversion.
The Sample-and-Hold (S/H) aperture is programmable allowing
the gain bandwidth requirements of the amplifier driving the SAR
inputs, which determine its settling time, to be relaxed if required.
It is possible to provide an external bypass (through a fixed pin
location) for the internal reference amplifier.
The SAR is connected to a fixed set of pins through an 8-input
sequencer. The sequencer cycles through selected channels
autonomously (sequencer scan) with zero switching overhead
(that is, aggregate sampling bandwidth is equal to 1 Msps
whether it is for a single channel or distributed over several
channels). The sequencer switching is effected through a state
machine or through firmware driven switching. A feature
provided by the sequencer is buffering of each channel to reduce
CPU interrupt service requirements. To accommodate signals
with varying source impedance and frequency, it is possible to
have different sample times programmable for each channel.
Also, signal range specification through a pair of range registers
(low and high range values) is implemented with a corresponding
out-of-range interrupt if the digitized value exceeds the
programmed range; this allows fast detection of out-of-range
values without the necessity of having to wait for a sequencer
scan to be completed and the CPU to read the values and check
for out-of-range values in software.
Document Number: 002-26566 Rev. *C
PSoC 4100S Plus 256KB has a pair of low-power comparators,
which can also operate in low power modes. This allows the
analog system blocks to be disabled while retaining the ability to
monitor external voltage levels during low-power modes. The
comparator outputs are normally synchronized to avoid
metastability unless operating in an asynchronous power mode
where the system wake-up circuit is activated by a comparator
switch event. The LPC outputs can be routed to pins.
Current DACs
PSoC 4100S Plus 256KB has two 7-bit IDACs, which can drive
any of the pins on the chip. These IDACs have programmable
current ranges.
Analog Multiplexed Buses
PSoC 4100S Plus 256KB has two concentric independent buses
that go around the periphery of the chip. These buses (called
amux buses) are connected to firmware-programmable analog
switches that allow the chip's internal resources (IDACs,
comparator) to connect to any pin on the I/O Ports.
Page 8 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Programmable Digital Blocks
Smart I/O Block
The Smart I/O block is a fabric of switches and LUTs that allows
Boolean functions to be performed in signals being routed to the
pins of a GPIO port. The Smart I/O can perform logical operations on input pins to the chip and on signals going out as
outputs. There are two Smart I/O blocks in the PSoC 4100S Plus
256KB.
Fixed Function Digital Blocks
Timer/Counter/PWM (TCPWM) Block
The TCPWM block consists of a 16-bit counter with
user-programmable period length. There is a capture register to
record the count value at the time of an event (which may be an
I/O event), a period register that is used to either stop or
auto-reload the counter when its count is equal to the period
register, and compare registers to generate compare value
signals that are used as PWM duty cycle outputs. The block also
provides true and complementary outputs with programmable
offset between them to allow use as dead-band programmable
complementary PWM outputs. It also has a Kill input to force
outputs to a predetermined state; for example, this is used in
motor drive systems when an over-current state is indicated and
the PWM driving the FETs needs to be shut off immediately with
no time for software intervention. Each block also incorporates a
Quadrature decoder. There are eight TCPWM blocks in PSoC
4100S Plus 256KB.
Serial Communication Block (SCB)
PSoC 4100S Plus 256KB has five serial communication blocks,
which can be programmed to have SPI, I2C, or UART functionality.
I2C Mode: The hardware I2C block implements a full
multi-master and slave interface (it is capable of multi-master
arbitration). This block is capable of operating at speeds of up to
400 kbps (Fast Mode) and has flexible buffering options to
reduce interrupt overhead and latency for the CPU. It also
supports EZI2C that creates a mailbox address range in the
memory of PSoC 4100S Plus 256KB and effectively reduces I2C
communication to reading from and writing to an array in
memory. In addition, the block supports an 8-deep FIFO for
receive and transmit which, by increasing the time given for the
CPU to read data, greatly reduces the need for clock stretching
caused by the CPU not having read data on time.
UART Mode: This is a full-feature UART operating at up to
1 Mbps. It supports automotive single-wire interface (LIN),
infrared interface (IrDA), and SmartCard (ISO7816) protocols, all
of which are minor variants of the basic UART protocol. In
addition, it supports the 9-bit multiprocessor mode that allows
addressing of peripherals connected over common RX and TX
lines. Common UART functions such as parity error, break
detect, and frame error are supported. An 8-deep FIFO allows
much greater CPU service latencies to be tolerated.
SPI Mode: The SPI mode supports full Motorola SPI, TI SSP
(adds a start pulse used to synchronize SPI Codecs), and
National Microwire (half-duplex form of SPI). The SPI block can
use the FIFO.
GPIO
PSoC 4100S Plus 256KB has up to 54 GPIOs. The GPIO block
implements the following:
■ Eight drive modes:
❐ Analog input mode (input and output buffers disabled)
❐ Input only
❐ Weak pull-up with strong pull-down
❐ Strong pull-up with weak pull-down
❐ Open drain with strong pull-down
❐ Open drain with strong pull-up
❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
■ Input threshold select (CMOS or LVTTL).
■ Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes
■ Selectable slew rates for dV/dt related noise control to improve
EMI
The pins are organized in logical entities called ports, which are
8-bit in width (less for Ports 5 and 6). During power-on and reset,
the blocks are forced to the disable state so as not to crowbar
any inputs and/or cause excess turn-on current. A multiplexing
network known as a high-speed I/O matrix is used to multiplex
between various signals that may connect to an I/O pin.
Data output and pin state registers store, respectively, the values
to be driven on the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled and each
I/O port has an interrupt request (IRQ) and interrupt service
routine (ISR) vector associated with it.
The I2C peripheral is compatible with the I2C Standard-mode and
Fast-mode devices as defined in the NXP I2C-bus specification
and user manual (UM10204). The I2C bus I/O is implemented
with GPIO in open-drain modes.
PSoC 4100S Plus 256KB is not completely compliant with the
I2C spec in the following respect:
■
GPIO cells are not overvoltage tolerant and, therefore, cannot
be hot-swapped or powered up independently of the rest of the
I2C system.
Document Number: 002-26566 Rev. *C
Page 9 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Special Function Peripherals
CapSense
CapSense is supported in the PSoC 4100S Plus 256KB through
a CapSense Sigma-Delta (CSD) block that can be connected to
any pins through an analog multiplex bus via analog switches.
CapSense function can thus be provided on any available pin or
group of pins in a system under software control. A PSoC
Creator component is provided for the CapSense block to make
it easy for the user.
Shield voltage can be driven on another analog multiplex bus to
provide water-tolerance capability. Water tolerance is provided
by driving the shield electrode in phase with the sense electrode
to keep the shield capacitance from attenuating the sensed
input. Proximity sensing can also be implemented.
The CapSense block has two IDACs, which can be used for
general purposes if CapSense is not being used (both IDACs are
available in that case) or if CapSense is used without water
tolerance (one IDAC is available).
LCD Segment Drive
PSoC 4100S Plus 256KB has an LCD controller, which can drive
up to 4 commons and up to 50 segments. Any pin can be either
a common or a segment pin. It uses full digital methods to drive
the LCD segments requiring no generation of internal LCD
voltages. The two methods used are referred to as Digital
Correlation and PWM. Digital Correlation pertains to modulating
the frequency and drive levels of the common and segment
signals to generate the highest RMS voltage across a segment
to light it up or to keep the RMS signal to zero. This method is
good for STN displays but may result in reduced contrast with TN
(cheaper) displays. PWM pertains to driving the panel with PWM
signals to effectively use the capacitance of the panel to provide
the integration of the modulated pulse-width to generate the
desired LCD voltage. This method results in higher power
consumption but can result in better results when driving TN
displays.
The CapSense block also provides a 10-bit Slope ADC function
which can be used in conjunction with the CapSense function.
The CapSense block is an advanced, low-noise, programmable
block with programmable voltage references and current source
ranges for improved sensitivity and flexibility. It can also use an
external reference voltage. It has a full-wave CSD mode that
alternates sensing to VDDA and ground to null out power-supply
related noise.
Document Number: 002-26566 Rev. *C
Page 10 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Pinouts
The following table provides the pin list for PSoC 4100S Plus 256KB for the 48-pin TQFP and 64-pin TQFP Normal and Fine Pitch
packages.
64-TQFP
48-TQFP
Pin
Name
Pin
Name
39
P0.0
28
P0.0
40
P0.1
29
P0.1
41
P0.2
30
P0.2
42
P0.3
31
P0.3
43
P0.4
32
P0.4
44
P0.5
33
P0.5
45
P0.6
34
P0.6
46
P0.7
35
P0.7
47
XRES
36
XRES
48
VCCD
37
VCCD
49
VSSD
38
VSSD
50
VDDD
39
VDDD
51
P5.0
52
P5.1
53
P5.2
54
P5.3
55
P5.5
56
VDDA
40
VDDA
57
VSSA
41
VSSA
58
P1.0
42
P1.0
59
P1.1
43
P1.1
60
P1.2
44
P1.2
61
P1.3
45
P1.3
62
P1.4
46
P1.4
63
P1.5
47
P1.5
64
P1.6
48
P1.6
1
P1.7
1
P1.7
Note
1. DNC = Do Not Connect. No connection should be made to this pin.
Document Number: 002-26566 Rev. *C
Page 11 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
64-TQFP
48-TQFP
Pin
Name
Pin
Name
2
P2.0
2
P2.0
3
P2.1
3
P2.1
4
P2.2
4
P2.2
5
P2.3
5
P2.3
6
P2.4
6
P2.4
7
P2.5
7
P2.5
8
P2.6
8
P2.6
9
P2.7
9
P2.7
10
VSSD
10
VSSD
11
*DNC[1]
11
*DNC[1]
15
*DNC[1]
12
P6.0
13
P6.1
14
P6.2
15
P6.4
16
P6.5
17
VSSD
18
P3.0
12
P3.0
19
P3.1
13
P3.1
20
P3.2
14
P3.2
21
P3.3
16
P3.3
22
P3.4
17
P3.4
23
P3.5
18
P3.5
24
P3.6
19
P3.6
25
P3.7
20
P3.7
26
VDDD
21
VDDD
27
P4.0
22
P4.0
28
P4.1
23
P4.1
29
P4.2
24
P4.2
Note
1. DNC = Do Not Connect. No connection should be made to this pin.
Document Number: 002-26566 Rev. *C
Page 12 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
64-TQFP
48-TQFP
Pin
Name
Pin
Name
30
P4.3
25
P4.3
31
P4.4
32
P4.5
33
P4.6
34
P4.7
35
P5.6
36
P5.7
37
P7.0
26
P7.0
38
P7.1
27
P7.1
Note
1. DNC = Do Not Connect. No connection should be made to this pin.
Descriptions of the Power pins are as follows:
VDDD: Power supply for the digital section.
VDDA: Power supply for the analog section.
VSSD, VSSA: Ground pins for the digital and analog sections respectively.
VCCD: Regulated digital supply (1.8 V ±5%)
GPIOs by package:
Number
64-TQFP
48-TQFP
54
38
Document Number: 002-26566 Rev. *C
Page 13 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Alternate Pin Functions
Each Port pin has can be assigned to one of multiple functions; it can, for example, be an analog I/O, a digital peripheral function, an LCD pin, or a CapSense pin. The pin
assignments are shown in the following table.
Port/Pin
P0.0
Analog
lpcomp.in_p[0]
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P5.0
P5.1
P5.2
P5.3
lpcomp.in_n[0]
lpcomp.in_p[1]
lpcomp.in_n[1]
wco.wco_in
wco.wco_out
exco.eco_in
exco.eco_out
P5.4
P5.5
P1.0
Smart I/O
ACT #0
ext_clk:0
tcpwm.line[0]:3
tcpwm.line[4]:2
tcpwm.line_compl[4]:2
tcpwm.line[5]:2
tcpwm.line_compl[5]:2
ACT #1
tcpwm.tr_in[0]
ACT #3
scb[2].uart_cts:0
DS #2
scb[2].i2c_scl:0
DS #3
scb[0].spi_select1:0
tcpwm.tr_in[1]
scb[2].uart_rts:0
scb[2].i2c_sda:0
scb[1].uart_rx:0
scb[1].uart_tx:0
scb[1].uart_cts:0
scb[1].uart_rts:0
scb[2].uart_rx:0
scb[2].uart_tx:0
scb[2].uart_tx:1
scb[1].i2c_scl:0
scb[1].i2c_sda:0
scb[2].uart_rx:1
scb[2].uart_tx:2
scb[2].uart_cts:1
scb[2].uart_rts:1
scb[2].i2c_scl:1
scb[2].i2c_sda:1
lpcomp.comp[0]:2
lpcomp.comp[1]:0
scb[0].spi_select2:0
scb[0].spi_select3:0
scb[2].spi_select0:1
scb[1].spi_mosi:1
scb[1].spi_miso:1
scb[1].spi_clk:1
scb[1].spi_select0:1
scb[2].spi_mosi:0
scb[2].spi_miso:0
scb[2].spi_clk:0
scb[2].spi_select0:0
ctb0_oa0+
tcpwm.line[6]:2
tcpwm.line_compl[6]:2
tcpwm.line[2]:1
scb[0].uart_rx:1
scb[0].i2c_scl:0
scb[2].spi_select1:0
scb[2].spi_select2:0
scb[0].spi_mosi:1
P1.1
ctb0_oa0-
tcpwm.line_compl[2]:1
scb[0].uart_tx:1
scb[0].i2c_sda:0
scb[0].spi_miso:1
P1.2
ctb0_oa0_out
tcpwm.line[3]:1
scb[0].uart_cts:1
tcpwm.tr_in[2]
scb[2].i2c_scl:2
scb[0].spi_clk:1
P1.3
ctb0_oa1_out
tcpwm.line_compl[3]:1
scb[0].uart_rts:1
tcpwm.tr_in[3]
scb[2].i2c_sda:2
scb[0].spi_select0:1
P1.4
P1.5
P1.6
P1.7
ctb0_oa1ctb0_oa1+
ctb0_oa0+
ctb0_oa1+
sar_ext_vref0
sar_ext_vref1
tcpwm.line[6]:1
tcpwm.line_compl[6]:1
tcpwm.line[7]:1
tcpwm.line_compl[7]:1
scb[3].i2c_scl:0
scb[3].i2c_sda:0
scb[0].spi_select1:1
scb[0].spi_select2:1
scb[0].spi_select3:1
scb[2].spi_clk:1
P2.0
P2.1
P2.2
P2.3
sarmux[0]
sarmux[1]
sarmux[2]
sarmux[3]
scb[1].i2c_scl:1
scb[1].i2c_sda:1
scb[1].spi_mosi:2
scb[1].spi_miso:2
scb[1].spi_clk:2
scb[1].spi_select0:2
SmartIo[0].io[0]
SmartIo[0].io[1]
SmartIo[0].io[2]
SmartIo[0].io[3]
Document Number: 002-26566 Rev. *C
tcpwm.line[4]:0
tcpwm.line_compl[4]:0
tcpwm.line[5]:1
tcpwm.line_compl[5]:1
csd.comp
tcpwm.tr_in[4]
tcpwm.tr_in[5]
Page 14 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Port/Pin
P2.4
P2.5
P2.6
Analog
sarmux[4]
sarmux[5]
sarmux[6]
Smart I/O
SmartIo[0].io[4]
SmartIo[0].io[5]
SmartIo[0].io[6]
ACT #0
tcpwm.line[0]:1
tcpwm.line_compl[0]:1
tcpwm.line[1]:1
ACT #1
scb[3].uart_rx:1
scb[3].uart_tx:1
scb[3].uart_cts:1
P2.7
sarmux[7]
SmartIo[0].io[7]
tcpwm.line_compl[1]:1
SmartIo[1].io[0]
SmartIo[1].io[1]
SmartIo[1].io[2]
SmartIo[1].io[3]
SmartIo[1].io[4]
SmartIo[1].io[5]
SmartIo[1].io[6]
SmartIo[1].io[7]
tcpwm.line[4]:1
tcpwm.line_compl[4]:1
tcpwm.line[5]:0
tcpwm.line_compl[5]:0
tcpwm.line[6]:0
tcpwm.line_compl[6]:0
tcpwm.line[0]:0
tcpwm.line_compl[0]:0
tcpwm.line[1]:0
tcpwm.line_compl[1]:0
tcpwm.line[2]:0
tcpwm.line_compl[2]:0
tcpwm.line[3]:0
tcpwm.line_compl[3]:0
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P5.6
P5.7
P7.0
P7.1
P7.2
csd.vref_ext
csd.cshield
csd.cmod
csd.csh_tank
Document Number: 002-26566 Rev. *C
DS #2
DS #3
scb[1].spi_select1:1
scb[1].spi_select2:1
scb[1].spi_select3:1
scb[3].uart_rts:1
lpcomp.comp[0]:0
scb[2].spi_mosi:1
scb[3].uart_rx:0
scb[3].uart_tx:0
scb[3].uart_cts:0
scb[3].uart_rts:0
scb[3].i2c_scl:1
scb[3].i2c_sda:1
scb[3].spi_mosi:0
scb[3].spi_miso:0
scb[3].spi_clk:0
scb[3].spi_select0:0
scb[3].spi_select1:0
scb[3].spi_select2:0
scb[1].spi_mosi:0
scb[1].spi_miso:0
scb[1].spi_clk:0
scb[1].spi_select0:0
scb[1].spi_select1:0
scb[1].spi_select2:0
scb[1].spi_select3:0
scb[2].spi_miso:1
scb[0].spi_mosi:0
scb[0].spi_miso:0
scb[0].spi_clk:0
scb[0].spi_select0:0
scb[0].spi_select1:2
scb[0].spi_select2:2
scb[0].spi_select3:2
scb[4].i2c_scl
scb[4].i2c_sda
scb[1].i2c_scl:2
scb[1].i2c_sda:2
cpuss.swd_data
cpuss.swd_clk
scb[1].uart_rx:1
scb[1].uart_tx:1
scb[1].uart_cts:1
scb[1].uart_rts:1
tcpwm.tr_in[6]
scb[0].uart_rx:0
scb[0].uart_tx:0
scb[0].uart_cts:0
scb[0].uart_rts:0
scb[4].uart_rx
scb[4].uart_tx
scb[4].uart_cts
scb[4].uart_rts
tcpwm.line[7]:0
tcpwm.line_compl[7]:0
tcpwm.line[0]:2
tcpwm.line_compl[0]:2
tcpwm.line[1]:2
ACT #3
scb[3].uart_rx:2
scb[3].uart_tx:2
scb[3].uart_cts:2
scb[4].spi_select3
lpcomp.comp[1]:1
scb[0].i2c_scl:1
scb[0].i2c_sda:1
lpcomp.comp[0]:1
lpcomp.comp[1]:2
scb[4].spi_mosi
scb[4].spi_miso
scb[4].spi_clk
scb[4].spi_select0
scb[4].spi_select1
scb[4].spi_select2
scb[3].i2c_scl:2
scb[3].i2c_sda:2
scb[2].spi_select3:0
scb[3].spi_mosi:1
scb[3].spi_miso:1
scb[3].spi_clk:1
Page 15 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Power
Mode 1: 1.8 V to 5.5 V External Supply
The following power system diagram shows the set of power
supply pins as implemented for PSoC 4100S Plus 256KB. The
system has one regulator in Active mode for the digital circuitry.
There is no analog regulator; the analog circuits run directly from
the VDDA input.
Figure 6. Power Supply Connections
VDDA
VDDD
VDDA
VSSA
Mode 2: 1.8 V ±5% External Supply
VDDD
Analog
Domain
In this mode, PSoC 4100S Plus 256KB is powered by an external
power supply that must be within the range of 1.71 to 1.89 V; note
that this range needs to include the power supply ripple too. In
this mode, the VDD and VCCD pins are shorted together and
bypassed. The internal regulator can be disabled in the firmware.
Digital
Domain
VSSD
1.8 Volt
Regulator
In this mode, PSoC 4100S Plus 256KB is powered by an external
power supply that can be anywhere in the range of 1.8 to 5.5 V.
This range is also designed for battery-powered operation. For
example, the chip can be powered from a battery system that
starts at 3.5 V and works down to 1.8 V. In this mode, the internal
regulator of PSoC 4100S Plus 256KB supplies the internal logic
and its output is connected to the VCCD pin. The VCCD pin must
be bypassed to ground via an external capacitor (0.1 µF; X5R
ceramic or better) and must not be connected to anything else.
Bypass capacitors must be used from VDDD to ground. The
typical practice for systems in this frequency range is to use a
capacitor in the 1-µF range, in parallel with a smaller capacitor
(0.1 µF, for example). Note that these are simply rules of thumb
and that, for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated to
design and obtain optimal bypassing.
VCCD
There are two distinct modes of operation. In Mode 1, the supply
voltage range is 1.8 V to 5.5 V (unregulated externally; internal
regulator operational). In Mode 2, the supply range is1.8 V ±5%
(externally regulated; 1.71 to 1.89, internal regulator bypassed).
An example of a bypass scheme is shown in the following
diagram.
Figure 7. External Supply Range from 1.8 V to 5.5 V with Internal Regulator Active
Power supply bypass connections example
1.8 V to 5.5 V
1.8 V to 5.5 V
VDDD
1 µF
VDDA
1 µF
0.1 µF
0.1 µF
VCCD
PSoC 4100S Plus
256KB
0.1 µF
VSS
Document Number: 002-26566 Rev. *C
Page 16 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Electrical Specifications
Absolute Maximum Ratings
Table 1. Absolute Maximum Ratings[2]
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
VDDD_ABS
Digital supply relative to VSS
–0.5
–
6
V
SID2
VCCD_ABS
Direct digital core voltage input relative
to VSS
–0.5
–
1.95
V
SID3
VGPIO_ABS
GPIO voltage
–0.5
–
VDD+0.5
V
–
SID4
IGPIO_ABS
Maximum current per GPIO
–25
–
25
mA
–
SID5
IGPIO_injection
GPIO injection current, Max for VIH >
VDDD, and Min for VIL < VSS
–0.5
–
0.5
mA
Current injected
per pin
BID44
ESD_HBM
Electrostatic discharge human body
model
2200
–
–
V
BID45
ESD_CDM
Electrostatic discharge charged device
model
500
–
–
V
BID46
LU
Pin current for latch-up
–140
–
140
mA
SID1
–
–
–
–
–
Device Level Specifications
All specifications are valid for –40 °C TA 105 °C and TJ 125 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
Table 2. DC Specifications
Typical values measured at VDD = 3.3 V and 25 °C.
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID53
VDD
Power supply input voltage
1.8
–
5.5
V
Internally
regulated supply
SID255
VDD
Power supply input voltage
(VCCD = VDDD = VDDA)
1.71
–
1.89
V
Internally
unregulated
supply
SID54
VCCD
Output voltage (for core logic)
–
1.8
–
V
–
SID55
CEFC
External regulator voltage bypass
–
0.1
–
µF
X5R ceramic or
better
SID56
CEXC
Power supply bypass capacitor
–
1
–
µF
X5R ceramic or
better
Active Mode, VDD = 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25 °C.
SID10
IDD5
Execute from flash; CPU at 6 MHz
–
1.8
2.4
mA
–
SID16
IDD8
Execute from flash; CPU at 24 MHz
–
3.0
4.6
mA
–
SID19
IDD11
Execute from flash; CPU at 48 MHz
–
5.4
7.1
mA
–
–
1.1
2.1
mA
6 MHZ
–
1.5
2.8
mA
12 MHZ
Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on)
SID22
SID25
IDD17
IDD20
I2C wakeup WDT, and Comparators on
2
I C wakeup, WDT, and Comparators on
Note
2. Usage above the absolute maximum conditions listed in Table 1 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended
periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 002-26566 Rev. *C
Page 17 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Table 2. DC Specifications (continued)
Typical values measured at VDD = 3.3 V and 25 °C.
Spec ID#
Parameter
Description
Details/
Conditions
Min
Typ
Max
Units
–
1.1
2.1
mA
6 MHZ
–
1.5
2.8
mA
12 MHZ
Sleep Mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed)
SID28
SID28A
IDD23
IDD23A
I2C wakeup, WDT, and Comparators on
2
I C wakeup, WDT, and Comparators on
Deep Sleep Mode, VDD = 1.8 V to 3.6 V (Regulator on)
SID30
IDD25
I2C wakeup and WDT on; T = –40 °C to
60 °C
–
2.5
40
µA
T = –40 °C to
60 °C
SID31
IDD26
I2C wakeup and WDT on
–
2.5
125
µA
Max is at 3.6 V
and 85 °C
2.5
40
µA
T = –40 °C to
60 °C
2.5
125
µA
Max is at 5.5 V
and 85 °C
2.5
60
µA
T = –40 °C to
60 °C
Deep Sleep Mode, VDD = 3.6 V to 5.5 V (Regulator on)
SID33
IDD28
I2C wakeup and WDT on; T = –40 °C to
60 °C
–
SID34
IDD29
I2C wakeup and WDT on
–
Deep Sleep Mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed)
SID36
IDD31
I2C wakeup and WDT on; T = –40 °C to
60 °C
–
SID37
IDD32
I2C wakeup and WDT on
–
2.5
180
µA
Max is at 1.89 V
and 85 °C
IDD_XR
Supply current while XRES asserted
–
2
5
mA
–
Min
Typ
Max
Units
DC
–
48
MHz
XRES Current
SID307
Table 3. AC Specifications
Spec ID#
Parameter
Description
Details/
Conditions
1.71 VDD 5.5
FCPU
CPU frequency
[3]
TSLEEP
Wakeup from Sleep mode
–
0
–
µs
–
[3]
TDEEPSLEEP
Wakeup from Deep Sleep mode
–
35
–
µs
–
SID48
SID49
SID50
Note
3. Guaranteed by characterization.
Document Number: 002-26566 Rev. *C
Page 18 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
GPIO
Table 4. GPIO DC Specifications
Spec ID#
SID57
Parameter
VIH
[4]
Description
Input voltage high threshold
Min
Typ
Max
Units
0.7 VDDD
Details/Conditions
–
–
V
CMOS Input
0.3
VDDD
V
CMOS Input
–
SID58
VIL
Input voltage low threshold
–
–
SID241
VIH[4]
LVTTL input, VDDD < 2.7 V
0.7 VDDD
–
–
V
SID242
VIL
LVTTL input, VDDD < 2.7 V
–
–
0.3
VDDD
V
SID243
VIH[4]
LVTTL input, VDDD 2.7 V
2.0
–
–
V
–
SID244
VIL
LVTTL input, VDDD 2.7 V
–
–
0.8
V
–
SID59
VOH
Output voltage high level
VDDD –0.6
–
–
V
IOH = 4 mA at 3 V VDDD
SID60
VOH
Output voltage high level
VDDD –0.5
–
–
V
IOH = 1 mA at 1.8 V
VDDD
SID61
VOL
Output voltage low level
–
–
0.6
V
IOL = 4 mA at 1.8 V VDDD
SID62
VOL
Output voltage low level
–
–
0.6
V
IOL = 10 mA at 3 V VDDD
SID62A
VOL
Output voltage low level
–
–
0.4
V
IOL = 3 mA at 3 V VDDD
SID63
RPULLUP
Pull-up resistor
3.5
5.6
8.5
kΩ
–
SID64
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
kΩ
–
SID65
IIL
Input leakage current (absolute
value)
–
–
2
nA
25 °C, VDDD = 3.0 V
SID66
–
CIN
Input capacitance
–
–
7
pF
–
[5]
VHYSTTL
Input hysteresis LVTTL
25
40
–
mV
VDDD 2.7 V
[5]
Input hysteresis CMOS
0.05 × VDDD
–
–
mV
VDD < 4.5 V
200
–
–
mV
VDD > 4.5 V
–
SID67
SID68
VHYSCMOS
SID68A[5]
VHYSCMOS5V5 Input hysteresis CMOS
SID69[5]
IDIODE
Current through protection diode to
VDD/VSS
–
–
100
µA
SID69A[5]
ITOT_GPIO
Maximum total source or sink chip
current
–
–
200
mA
–
Notes
4. VIH must not exceed VDDD + 0.2 V.
5. Guaranteed by characterization.
Document Number: 002-26566 Rev. *C
Page 19 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Table 5. GPIO AC Specifications
(Guaranteed by Characterization)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID70
TRISEF
Rise time in fast strong mode
2
–
12
ns
3.3 V VDDD,
Cload = 25 pF
SID71
TFALLF
Fall time in fast strong mode
2
–
12
ns
3.3 V VDDD,
Cload = 25 pF
SID72
TRISES
Rise time in slow strong mode
10
–
60
ns
3.3 V VDDD,
Cload = 25 pF
SID73
TFALLS
Fall time in slow strong mode
10
–
60
ns
3.3 V VDDD,
Cload = 25 pF
SID74
FGPIOUT1
GPIO FOUT; 3.3 V VDDD 5.5 V
Fast strong mode
–
–
33
MHz
90/10%, 25 pF load,
60/40 duty cycle
SID75
FGPIOUT2
GPIO FOUT; 1.71 VVDDD3.3 V
Fast strong mode
–
–
16.7
MHz
90/10%, 25 pF load,
60/40 duty cycle
SID76
FGPIOUT3
GPIO FOUT; 3.3 V VDDD 5.5 V
Slow strong mode
–
–
7
MHz
90/10%, 25 pF load,
60/40 duty cycle
SID245
FGPIOUT4
GPIO FOUT; 1.71 V VDDD 3.3 V
Slow strong mode.
–
–
3.5
MHz
90/10%, 25 pF load,
60/40 duty cycle
SID246
FGPIOIN
GPIO input operating frequency;
1.71 V VDDD 5.5 V
–
–
48
MHz
90/10% VIO
XRES
Table 6. XRES DC Specifications
Min
Typ
Max
Units
SID77
Spec ID#
VIH
Parameter
Input voltage high threshold
Description
0.7 × VDDD
–
–
V
SID78
VIL
Input voltage low threshold
–
–
0.3 VDDD
V
SID79
RPULLUP
Pull-up resistor
–
60
–
kΩ
SID80
CIN
Input capacitance
–
–
7
pF
–
Typical hysteresis is
200 mV for VDD > 4.5 V
SID81[6]
VHYSXRES
Input voltage hysteresis
–
100
–
mV
SID82
IDIODE
Current through protection diode
to VDD/VSS
–
–
100
µA
Details/Conditions
CMOS Input
–
–
Table 7. XRES AC Specifications
Min
Typ
Max
Units
SID83[6]
Spec ID#
TRESETWIDTH
Parameter
Reset pulse width
Description
1
–
–
µs
–
Details/Conditions
BID194[6]
TRESETWAKE
Wake-up time from reset release
–
–
2.7
ms
–
Note
6. Guaranteed by characterization.
Document Number: 002-26566 Rev. *C
Page 20 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Analog Peripherals
CTBm Opamp
Table 8. CTBm Opamp Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
IDD
Opamp block current, External load
SID269
IDD_HI
power=hi
–
1100
1900
µA
–
SID270
IDD_MED
power=med
–
550
1020
µA
–
SID271
IDD_LOW
power=lo
–
150
370
µA
–
GBW
Load = 50 pF, 0.1 mA
VDDA = 2.7 V
SID272
GBW_HI
power=hi
6
–
–
MHz
Input and output are
0.2 V to VDDA-0.2 V
SID273
GBW_MED
power=med
3
–
–
MHz
Input and output are
0.2 V to VDDA-0.2 V
SID274
GBW_LO
power=lo
–
1
–
MHz
Input and output are
0.2 V to VDDA-0.2 V
IOUT_MAX
VDDA = 2.7 V, 500 mV from rail
SID275
IOUT_MAX_HI
power=hi
10
–
–
mA
Output is 0.5 V to VDDA
-0.5 V
SID276
IOUT_MAX_MID
power=mid
10
–
–
mA
Output is 0.5 V to VDDA
-0.5 V
SID277
IOUT_MAX_LO
power=lo
–
5
–
mA
Output is 0.5 V to VDDA
-0.5 V
IOUT
VDDA = 1.71 V, 500 mV from rail
SID278
IOUT_MAX_HI
power=hi
4
–
–
mA
Output is 0.5 V to VDDA
-0.5 V
SID279
IOUT_MAX_MID
power=mid
4
–
–
mA
Output is 0.5 V to
VDDA-0.5 V
SID280
IOUT_MAX_LO
power=lo
–
2
–
mA
Output is 0.5 V to
VDDA-0.5 V
IDD_Int
Opamp block current Internal Load
SID269_I
IDD_HI_Int
power=hi
–
1500
1700
µA
–
SID270_I
IDD_MED_Int
power=med
–
700
980
µA
–
IDD_LOW_Int
power=lo
–
–
405
µA
–
GBW
VDDA = 2.7 V
–
–
–
GBW_HI_Int
power=hi
8
–
–
MHz
SID271_I
SID272_I
–
Output is 0.25 V to
VDDA-0.25 V
General opamp specs for both
internal and external modes
SID281
VIN
Charge-pump on, VDDA = 2.7 V
–0.05
–
VDDA-0.2
V
–
SID282
VCM
Charge-pump on, VDDA = 2.7 V
–0.05
–
VDDA-0.2
V
–
VOUT
VDDA = 2.7 V
VOUT_1
power=hi, Iload=10 mA
0.5
–
VDDA
-0.5
V
–
SID283
Document Number: 002-26566 Rev. *C
Page 21 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Table 8. CTBm Opamp Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID284
VOUT_2
power=hi, Iload=1 mA
0.2
–
VDDA
-0.2
V
–
SID285
VOUT_3
power=med, Iload=1 mA
0.2
–
VDDA
-0.2
V
–
SID286
VOUT_4
power=lo, Iload=0.1 mA
0.2
–
VDDA
-0.2
V
–
SID288
VOS_TR
Offset voltage, trimmed
–1.0
0.5
1.0
mV
High mode, input 0 V to
VDDA-0.2 V
SID288A
VOS_TR
Offset voltage, trimmed
–
1
–
mV
Medium mode, input
0 V to VDDA-0.2 V
SID288B
VOS_TR
Offset voltage, trimmed
–
2
–
mV
Low mode, input 0 V to
VDDA-0.2 V
SID290
VOS_DR_TR
Offset voltage drift, trimmed
–10
3
10
µV/°C
High mode
SID290A
VOS_DR_TR
Offset voltage drift, trimmed
–
10
–
µV/°C
Medium mode
SID290B
VOS_DR_TR
Offset voltage drift, trimmed
–
10
–
µV/°C
Low mode
dB
Input is 0 V to
VDDA-0.2 V, Output is
0.2 V to VDDA-0.2 V
dB
VDDD = 3.6 V,
high-power mode, input
is 0.2 V to VDDA-0.2 V
SID291
CMRR
DC
70
80
–
SID292
PSRR
At 1 kHz, 10-mV ripple
70
85
–
Noise
SID294
VN2
Input-referred, 1 kHz, power = Hi
–
72
–
Input and output are at
nV/rtHz 0.2 V to V
DDA-0.2 V
SID295
VN3
Input-referred, 10 kHz, power = Hi
–
28
–
Input and output are at
nV/rtHz 0.2 V to V
DDA-0.2 V
SID296
VN4
Input-referred, 100 kHz, power = Hi
–
15
–
Input and output are at
nV/rtHz 0.2 V to V
DDA-0.2 V
SID297
CLOAD
Stable up to max. load.
Performance specs at 50 pF.
–
–
125
pF
–
SID298
SLEW_RATE
Cload = 50 pF, Power = High,
VDDA = 2.7 V
4
–
–
V/µs
–
SID299
T_OP_WAKE
From disable to enable, no external
RC dominating
–
–
25
µs
–
SID299A
OL_GAIN
Open Loop Gain
–
90
–
dB
–
COMP_MODE
Comparator mode; 50 mV drive,
Trise=Tfall (approx.)
SID300
TPD1
Response time; power=hi
–
150
–
ns
Input is 0.2 V to
VDDA-0.2 V
SID301
TPD2
Response time; power=med
–
500
–
ns
Input is 0.2 V to
VDDA-0.2 V
SID302
TPD3
Response time; power=lo
–
2500
–
ns
Input is 0.2 V to
VDDA-0.2 V
Document Number: 002-26566 Rev. *C
Page 22 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Table 8. CTBm Opamp Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID303
VHYST_OP
Hysteresis
–
10
–
mV
–
SID304
WUP_CTB
Wake-up time from Enabled to
Usable
–
–
25
µs
–
Deep Sleep
Mode
Mode 2 is lowest current range.
Mode 1 has higher GBW.
SID_DS_1
IDD_HI_M1
Mode 1, High current
–
1400
–
µA
25 °C
SID_DS_2
IDD_MED_M1
Mode 1, Medium current
–
700
–
µA
25 °C
SID_DS_3
IDD_LOW_M1
Mode 1, Low current
–
200
–
µA
25 °C
120
–
µA
25 °C
SID_DS_4
IDD_HI_M2
Mode 2, High current
–
SID_DS_5
IDD_MED_M2
Mode 2, Medium current
–
60
–
µA
25 °C
SID_DS_6
IDD_LOW_M2
Mode 2, Low current
–
15
–
µA
25 °C
SID_DS_7
GBW_HI_M1
Mode 1, High current
–
4
–
MHz
20-pF load, no DC load
0.2 V to VDDA-0.2 V
SID_DS_8
GBW_MED_M1
Mode 1, Medium current
–
2
–
MHz
20-pF load, no DC load
0.2 V to VDDA-0.2 V
SID_DS_9
GBW_LOW_M1
Mode 1, Low current
–
0.5
–
MHz
20-pF load, no DC load
0.2 V to VDDA-0.2 V
SID_DS_10 GBW_HI_M2
Mode 2, High current
–
0.5
–
MHz
20-pF load, no DC load
0.2 V to VDDA-0.2 V
SID_DS_11 GBW_MED_M2
Mode 2, Medium current
–
0.2
–
MHz
20-pF load, no DC load
0.2 V to VDDA-0.2 V
SID_DS_12 GBW_Low_M2
Mode 2, Low current
–
0.1
–
MHz
20-pF load, no DC load
0.2 V to VDDA-0.2 V
SID_DS_13 VOS_HI_M1
Mode 1, High current
–
5
–
mV
With trim 25 °C, 0.2 V to
VDDA-0.2 V
SID_DS_14 VOS_MED_M1
Mode 1, Medium current
–
5
–
mV
With trim 25 °C, 0.2 V to
VDDA-0.2 V
SID_DS_15 VOS_LOW_M1
Mode 1, Low current
–
5
–
mV
With trim 25 °C, 0.2 V to
VDDA-0.2 V
SID_DS_16 VOS_HI_M2
Mode 2, High current
–
5
–
mV
With trim 25 °C, 0.2V to
VDDA-0.2 V
SID_DS_17 VOS_MED_M2
Mode 2, Medium current
–
5
–
mV
With trim 25 °C, 0.2 V to
VDDA-0.2 V
SID_DS_18 VOS_LOW_M2
Mode 2, Low current
–
5
–
mV
With trim 25 °C, 0.2 V to
VDDA-0.2 V
SID_DS_19 IOUT_HI_M1
Mode 1, High current
–
10
–
mA
Output is 0.5 V to
VDDA-0.5 V
SID_DS_20 IOUT_MED_M1
Mode 1, Medium current
–
10
–
mA
Output is 0.5 V to
VDDA-0.5 V
SID_DS_21 IOUT_LOW_M1
Mode 1, Low current
–
4
–
mA
Output is 0.5 V to
VDDA-0.5 V
SID_DS_22 IOUT_HI_M2
Mode 2, High current
–
1
–
mA
Document Number: 002-26566 Rev. *C
Page 23 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Table 8. CTBm Opamp Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
SID_DS_23 IOUT_MED_M2
Mode 2, Medium current
–
1
–
mA
SID_DS_24 IOUT_LOW_M2
Mode 2, Low current
–
0.5
–
mA
Details/Conditions
Comparator
Table 9. Comparator DC Specifications
Max
Units
SID84
Spec ID#
VOFFSET1
Parameter
Input offset voltage, Factory trim
Description
Min Typ
–
–
±10
mV
–
Details/Conditions
SID85
VOFFSET2
Input offset voltage, Custom trim
–
–
±4
mV
–
SID86
VHYST
Hysteresis when enabled
–
10
35
mV
–
SID87
VICM1
Input common mode voltage in normal
mode
0
–
VDDD-0.1
V
SID247
VICM2
Input common mode voltage in low
power mode
0
–
VDDD
V
SID247A
VICM3
Input common mode voltage in ultra
low power mode
0
–
VDDD-1.15
V
VDDD ≥ 2.2 V at –40 °C
SID88
CMRR
Common mode rejection ratio
50
–
–
dB
VDDD ≥ 2.7V
SID88A
CMRR
Common mode rejection ratio
42
–
–
dB
VDDD ≤ 2.7V
SID89
ICMP1
Block current, normal mode
–
–
400
µA
–
SID248
ICMP2
Block current, low power mode
–
–
100
µA
–
SID259
ICMP3
Block current in ultra low-power mode
–
–
6
µA
VDDD ≥ 2.2 V at –40 °C
SID90
ZCMP
DC Input impedance of comparator
35
–
–
MΩ
–
Modes 1 and 2
–
Table 10. Comparator AC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
SID91
TRESP1
Response time, normal mode, 50 mV
overdrive
–
38
110
ns
SID258
TRESP2
Response time, low power mode, 50 mV
overdrive
–
70
200
ns
SID92
TRESP3
Response time, ultra-low power mode,
200 mV overdrive
–
2.3
15
µs
Details/Conditions
–
–
VDDD ≥ 2.2 V at –40 °C
Note
7. Guaranteed by characterization.
Document Number: 002-26566 Rev. *C
Page 24 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Temperature Sensor
Table 11. Temperature Sensor Specifications
Spec ID#
SID93
Parameter
Description
TSENSACC
Temperature sensor accuracy
Min
Typ
Max
Units
–5
±1
5
°C
Details/
Conditions
–40 to +85 °C
SAR ADC
Table 12. SAR ADC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
bits
Details/
Conditions
SAR ADC DC Specifications
SID94
A_RES
Resolution
–
–
12
SID95
A_CHNLS_S
Number of channels - single ended
–
–
16
–
SID96
A-CHNKS_D
Number of channels - differential
–
–
4
Diff inputs use
neighboring I/O
SID97
A-MONO
Monotonicity
SID98
A_GAINERR
Gain error
–
–
±0.125
%
SID99
A_OFFSET
Input offset voltage
–
–
±2.3
mV
Measured with
1-V reference
SID100
A_ISAR
Current consumption
–
–
1
mA
–
Yes
–
–
With external
reference
SID101
A_VINS
Input voltage range - single ended
VSS
–
VDDA
V
–
SID102
A_VIND
Input voltage range - differential
VSS
–
VDDA
V
–
SID103
A_INRES
Input resistance
–
–
2.2
KΩ
–
SID104
A_INCAP
Input capacitance
–
–
10
pF
–
SID260
VREFSAR
Trimmed internal reference to SAR
1.188
1.2
1.212
V
–
SAR ADC AC Specifications
SID106
A_PSRR
Power supply rejection ratio
70
–
–
dB
–
SID107
A_CMRR
Common mode rejection ratio
66
–
–
dB
Measured at 1 V
SID108
A_SAMP
Sample rate
–
–
1
SID109
A_SNR
Signal-to-noise and distortion ratio (SINAD)
64
–
–
SID110
A_BW
Input bandwidth without aliasing
–
–
A_samp/2
kHz
–
SID111
A_INL
Integral non linearity
–3
–
3
LSB
–
–
Msps –
dB
SID112
A_DNL
Differential non linearity
–1
–
3
LSB
SID113
A_THD
Total harmonic distortion
–
–
–62
dB
SID261
FSARINTREF SAR operating speed without external reference
bypass
–
–
100
ksps
Document Number: 002-26566 Rev. *C
FIN = 10 kHz
Fin = 10 kHz
12-bit resolution
Page 25 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
CSD and IDAC
Table 13. CSD and IDAC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
SYS.PER#3
VDD_RIPPLE
Max allowed ripple on
power supply, DC to 10
MHz
–
–
±50
mV
VDD > 2 V (with ripple), 25 °C
TA, Sensitivity = 0.1 pF
SYS.PER#16
VDD_RIPPLE_1.8 Max allowed ripple on
power supply, DC to 10
MHz
–
–
±25
mV
VDD > 1.75V (with ripple),
25 °C TA, Parasitic Capacitance (CP) < 20 pF,
Sensitivity ≥ 0.4 pF
–
–
4000
µA
Maximum block current for
both IDACs in dynamic
(switching) mode including
comparators, buffer, and
reference generator
0.6
1.2
VDDA - 0.6
V
VDDA – 0.6 or 4.4, whichever
is lower
SID.CSD.BLK ICSD
Maximum block current
SID.CSD#15
VREF
Voltage reference for CSD
and Comparator
SID.CSD#16
IDAC1IDD
IDAC1 (7-bits) block
current
–
–
1750
µA
–
SID.CSD#17
IDAC2IDD
IDAC2 (7-bits) block
current
–
–
1750
µA
–
SID308
VCSD
Voltage range of operation
1.71
–
5.5
V
1.8 V ±5% or 1.8 V to 5.5 V
SID308A
VCOMPIDAC
Voltage compliance range
of IDAC
0.6
–
VDDA –0.6
V
VDDA – 0.6 or 4.4, whichever
is lower
SID309
IDAC1DNL
IDAC1DNL
–1
–
1
LSB
–
SID310
IDAC1INL
IDAC1INL
–2
–
2
LSB
INL is ±5.5 LSB for
VDDA < 2 V
SID311
IDAC2DNL
IDAC2DNL
–1
–
1
LSB
–
SID312
IDAC2INL
IDAC2INL
–2
–
2
LSB
INL is ±5.5 LSB for
VDDA < 2 V
SID313
SNR
Ratio of counts of finger to
noise. Guaranteed by
characterization
5
–
–
Ratio Capacitance range of 5 to
35 pF, 0.1-pF sensitivity.
All use cases. VDDA > 2 V.
SID314
IDAC1CRT1
Output current of IDAC1
(7 bits) in low range
4.2
–
5.4
µA
LSB = 37.5-nA typ.
SID314A
IDAC1CRT2
Output current of IDAC1
(7 bits) in medium range
34
–
41
µA
LSB = 300-nA typ.
SID314B
IDAC1CRT3
Output current of IDAC1
(7 bits) in high range
275
–
330
µA
LSB = 2.4-µA typ.
SID314C
IDAC1CRT12
Output current of IDAC1
(7 bits) in low range, 2X
mode
8
–
10.5
µA
LSB = 75-nA typ.
SID314D
IDAC1CRT22
Output current of IDAC1
(7 bits) in medium range,
2X mode
69
–
82
µA
LSB = 600-nA typ.
SID314E
IDAC1CRT32
Output current of IDAC1
(7 bits) in high range, 2X
mode
540
–
660
µA
LSB = 4.8-µA typ.
SID315
IDAC2CRT1
Output current of IDAC2
(7 bits) in low range
4.2
–
5.4
µA
LSB = 37.5-nA typ.
SID315A
IDAC2CRT2
Output current of IDAC2
(7 bits) in medium range
34
–
41
µA
LSB = 300-nA typ.
Document Number: 002-26566 Rev. *C
Page 26 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Table 13. CSD and IDAC Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details / Conditions
SID315B
IDAC2CRT3
Output current of IDAC2
(7 bits) in high range
275
–
330
µA
LSB = 2.4-µA typ.
SID315C
IDAC2CRT12
Output current of IDAC2
(7 bits) in low range, 2X
mode
8
–
10.5
µA
LSB = 75-nA typ.
SID315D
IDAC2CRT22
Output current of IDAC2
(7 bits) in medium range,
2X mode
69
–
82
µA
LSB = 600-nA typ.
SID315E
IDAC2CRT32
Output current of IDAC2
(7 bits) in high range, 2X
mode
540
–
660
µA
LSB = 4.8-µA typ.
SID315F
IDAC3CRT13
Output current of IDAC in
8-bit mode in low range
8
–
10.5
µA
LSB = 37.5-nA typ.
SID315G
IDAC3CRT23
Output current of IDAC in
8-bit mode in medium
range
69
–
82
µA
LSB = 300-nA typ.
SID315H
IDAC3CRT33
Output current of IDAC in
8-bit mode in high range
540
–
660
µA
LSB = 2.4-µA typ.
SID320
IDACOFFSET
All zeroes input
–
–
1
LSB
SID321
IDACGAIN
Full-scale error less offset
–
–
±10
%
SID322
IDACMISMATCH1 Mismatch between IDAC1
and IDAC2 in Low range
–
–
9.2
LSB
LSB = 37.5-nA typ.
SID322A
IDACMISMATCH2 Mismatch between IDAC1
and IDAC2 in Medium
range
–
–
5.6
LSB
LSB = 300-nA typ.
SID322B
IDACMISMATCH3 Mismatch between IDAC1
and IDAC2 in High range
–
–
6.8
LSB
LSB = 2.4-µA typ.
SID323
IDACSET8
Settling time to 0.5 LSB for
8-bit IDAC
–
–
5
µs
Full-scale transition.
No external load.
SID324
IDACSET7
Settling time to 0.5 LSB for
7-bit IDAC
–
–
5
µs
Full-scale transition.
No external load.
SID325
CMOD
External modulator
capacitor.
–
2.2
–
nF
5-V rating, X7R or NP0 cap
Document Number: 002-26566 Rev. *C
Polarity set by Source or
Sink. Offset is 2 LSBs for
37.5 nA/LSB mode
–
Page 27 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
10-bit CapSense ADC
Table 14. 10-bit CapSense ADC Specifications
Spec ID#
SIDA94
Parameter
A_RES
Description
Min
Typ
Max
Resolution
–
–
10
–
–
16
Units
Details/Conditions
bits Auto-zeroing is required
every millisecond
SIDA95
A_CHNLS_S
Number of channels - single ended
SIDA97
A-MONO
Monotonicity
SIDA98
A_GAINERR
Gain error
–
–
±3
SIDA99
A_OFFSET
Input offset voltage
–
–
±18
mV In VREF (2.4 V) mode with
VDDA bypass
capacitance of 10 µF
mA –
SIDA100
A_ISAR
Current consumption
SIDA101
A_VINS
Input voltage range - single ended
Defined by AMUX Bus
Yes
–
%
–
–
0.25
VSSA
–
VDDA
V
In VREF (2.4 V) mode with
VDDA bypass
capacitance of 10 µF
–
SIDA103
A_INRES
Input resistance
–
2.2
–
KΩ
–
SIDA104
A_INCAP
Input capacitance
–
20
–
pF
–
SIDA106
A_PSRR
Power supply rejection ratio
–
60
–
dB
In VREF (2.4 V) mode with
VDDA bypass capacitance of 10 µF
SIDA107
A_TACQ
Sample acquisition time
–
1
–
µs
–
SIDA108
A_CONV8
Conversion time for 8-bit resolution at
conversion rate = Fhclk/(2^(N+2)).
Clock frequency = 48 MHz.
–
–
21.3
µs
Does not include acquisition time. Equivalent to
44.8 ksps including
acquisition time.
SIDA108A
A_CONV10
Conversion time for 10-bit resolution at
conversion rate = Fhclk/(2^(N+2)).
Clock frequency = 48 MHz.
–
–
85.3
µs
Does not include acquisition time. Equivalent to
11.6 ksps including
acquisition time.
SIDA109
A_SND
Signal-to-noise and Distortion ratio
(SINAD)
–
59
–
dB
With 10-Hz input sine
wave, internal reference,
VREF (2.4 V) mode
SIDA110
A_BW
Input bandwidth without aliasing
–
–
22.4
SIDA111
A_INL
Integral Non Linearity. 1 ksps
–
–
2
LSB VREF = 2.4 V or greater
SIDA112
A_DNL
Differential Non Linearity. 1 ksps
–
–
1
LSB –
Document Number: 002-26566 Rev. *C
KHz 8-bit resolution
Page 28 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Digital Peripherals
Timer Counter Pulse-Width Modulator (TCPWM)
Table 15. TCPWM Specifications
Spec ID#
SID.TCPWM.1
Parameter
ITCPWM1
Description
Block current consumption at 3 MHz
Min
–
Typ
–
Max
45
Units
Details/Conditions
μA All modes (TCPWM)
SID.TCPWM.2
ITCPWM2
Block current consumption at 12 MHz
–
–
155
μA
All modes (TCPWM)
SID.TCPWM.2A ITCPWM3
Block current consumption at 48 MHz
–
–
650
μA
All modes (TCPWM)
–
–
Fc
MHz
Fc max = CLK_SYS
Maximum = 48 MHz
SID.TCPWM.3
TCPWMFREQ
Operating frequency
SID.TCPWM.4
TPWMENEXT
Input trigger pulse width
2/Fc
–
–
ns
For all trigger events[8]
SID.TCPWM.5
TPWMEXT
Output trigger pulse widths
2/Fc
–
–
ns
Minimum possible width
of Overflow, Underflow,
and CC (Counter equals
Compare value) outputs
SID.TCPWM.5A TCRES
Resolution of counter
1/Fc
–
–
ns
Minimum time between
successive counts
SID.TCPWM.5B PWMRES
PWM resolution
1/Fc
–
–
ns
Minimum pulse width of
PWM Output
SID.TCPWM.5C QRES
Quadrature inputs resolution
1/Fc
–
–
ns
Minimum pulse width
between Quadrature
phase inputs
Description
Min
Typ
Max
Units
II2C1
Block current consumption at 100 kHz
–
–
50
µA
–
I2C
Table 16. Fixed I2C DC Specifications[8]
Spec ID#
SID149
Parameter
Details/Conditions
SID150
II2C2
Block current consumption at 400 kHz
–
–
135
µA
–
SID151
II2C3
Block current consumption at 1 Mbps
–
–
310
µA
–
SID152
II2C4
Block current in Deep Sleep mode
–
1
–
µA
–
Units
Table 17. Fixed I2C AC Specifications[8]
Spec ID#
SID153
Parameter
Description
Bit rate
FI2C1
Min
Typ
Max
–
–
1
Details/Conditions
Msps –
SPI
Table 18. SPI DC Specifications[8]
Description
Min
Typ
Max
Units
SID163
Spec ID#
ISPI1
Parameter
Block current consumption at 1 Mbps
–
–
360
µA
–
Details/Conditions
SID164
ISPI2
Block current consumption at 4 Mbps
–
–
560
µA
–
SID165
ISPI3
Block current consumption at 8 Mbps
–
–
600
µA
–
Note
8. Guaranteed by characterization.
Document Number: 002-26566 Rev. *C
Page 29 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Table 19. SPI AC Specifications[9]
Spec ID#
SID166
Parameter
FSPI
Description
Min
Typ
Max
Units
SPI Operating frequency (Master; 6X
Oversampling)
–
–
8
MHz
Details/Conditions
–
Fixed SPI Master Mode AC Specifications
SID167
TDMO
MOSI Valid after SClock driving edge
–
–
15
ns
–
SID168
TDSI
MISO Valid before SClock capturing
edge
20
–
–
ns
Full clock, late MISO
sampling
SID169
THMO
Previous MOSI data hold time
0
–
–
ns
Referred to Slave capturing
edge
Fixed SPI Slave Mode AC Specifications
–
SID170
TDMI
MOSI Valid before Sclock Capturing
edge
40
–
–
ns
SID171
TDSO
MISO Valid after Sclock driving edge
–
–
42 +
3*Tcpu
ns
SID171A
TDSO_EXT
MISO Valid after Sclock driving edge
in Ext. Clk mode
–
–
48
ns
SID172
THSO
Previous MISO data hold time
0
–
–
ns
–
SID172A
TSSELSSCK
SSEL Valid to first SCK Valid edge
100
–
–
ns
–
Min
Typ
Max
Units
TCPU = 1/FCPU
–
UART
Table 20. UART DC Specifications[9]
Spec ID#
Parameter
Description
SID160
IUART1
Block current consumption at
100 Kbps
–
–
55
µA
SID161
IUART2
Block current consumption at
1000 Kbps
–
–
312
µA
Min
Typ
Max
Units
–
–
1
Min
Typ
Details/Conditions
–
–
Table 21. UART AC Specifications[9]
Spec ID#
SID162
Parameter
FUART
Description
Bit rate
Details/Conditions
Mbps –
LCD Direct Drive
Table 22. LCD Direct Drive DC Specifications[9]
Spec ID#
Parameter
Description
SID155
CLCDCAP
LCD capacitance per
segment/common driver
SID156
LCDOFFSET
Long-term segment offset
–
SID157
ILCDOP1
LCD system operating current Vbias
=5V
–
SID158
ILCDOP2
LCD system operating current Vbias
= 3.3 V
–
–
Max
Units
Details/Conditions
–
500
5000
pF
20
–
mV
–
2
–
mA
32 4 segments at 50 Hz
25 °C
2
–
mA
32 4 segments at 50 Hz
25 °C
Note
9. Guaranteed by characterization.
Document Number: 002-26566 Rev. *C
Page 30 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Table 23. LCD Direct Drive AC Specifications[10]
Spec ID#
SID159
Parameter
Description
LCD frame rate
FLCD
Min
Typ
Max
Units
10
50
150
Hz
Details/Conditions
–
Memory
Table 24. Flash DC Specifications
Spec ID#
SID173
Parameter
VPE
Description
Min
Typ
Max
Units
1.71
–
5.5
V
Description
Min
Typ
Max
Units
Details/Conditions
Erase and program voltage
Details/Conditions
–
Table 25. Flash AC Specifications
Spec ID#
Parameter
SID174
TROWWRITE[11]
Row (block) write time (erase and
program)
–
–
20
ms
Row (block) = 256 bytes
SID175
TROWERASE[11]
Row erase time
–
–
16
ms
–
SID176
Row program time after erase
–
–
4
ms
–
Bulk erase time (256 KB)
–
–
35
ms
–
SID180[10]
TROWPROGRAM[11]
TBULKERASE[11]
TDEVPROG[11]
Total device program time
–
–
7
SID181[10]
FEND
Flash endurance
100 K
–
–
Cycles
–
SID182[10]
FRET
Flash retention. TA 55 °C, 100 K
P/E cycles
20
–
–
Years
–
SID182A[10] –
Flash retention. TA 85 °C, 10 K
P/E cycles
10
–
–
Years
–
SID182B
–
Flash retention. TA 105 °C, 10K
P/E cycles, three years at TA ≥
85 °C
10
–
20
Years
–
SID256
TWS48
Number of Wait states at 48 MHz
2
–
–
CPU execution from
Flash
SID257
TWS24
Number of Wait states at 24 MHz
1
–
–
CPU execution from
Flash
Min
Typ
Max
Units
1
–
67
V/ms
SID178
Seconds –
System Resources
Power-on Reset (POR)
Table 26. Power On Reset (PRES)
Spec ID#
Parameter
Description
SID.CLK#6 SR_POWER_UP Power supply slew rate
Details/Conditions
At power-up and
power-down
SID185[10]
VRISEIPOR
Rising trip voltage
0.80
–
1.5
V
–
[10]
VFALLIPOR
Falling trip voltage
0.70
–
1.4
V
–
SID186
Notes
10. Guaranteed by characterization.
11. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations may be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
Document Number: 002-26566 Rev. *C
Page 31 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Table 27. Brown-out Detect (BOD) for VCCD
Spec ID#
[12]
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID190
VFALLPPOR
BOD trip voltage in active and
sleep modes
1.48
–
1.62
V
–
SID192[12]
VFALLDPSLP
BOD trip voltage in Deep Sleep
1.11
–
1.5
V
–
Min
Typ
Max
Units
Details/Conditions
SWD Interface
Table 28. SWD Interface Specifications
Spec ID#
Parameter
Description
SID213
F_SWDCLK1
3.3 V VDD 5.5 V
–
–
14
MHz
SWDCLK ≤ 1/3 CPU
clock frequency
SID214
F_SWDCLK2
1.71 V VDD 3.3 V
–
–
7
MHz
SWDCLK ≤ 1/3 CPU
clock frequency
SID215[13]
T_SWDI_SETUP T = 1/f SWDCLK
0.25*T
–
–
ns
–
SID216
[13]
T_SWDI_HOLD
0.25*T
–
–
ns
–
SID217
[13]
T_SWDO_VALID T = 1/f SWDCLK
–
–
0.5*T
ns
–
T_SWDO_HOLD T = 1/f SWDCLK
1
–
–
ns
–
Min
Typ
Max
Units
SID217A
[13]
T = 1/f SWDCLK
Internal Main Oscillator
Table 29. IMO DC Specifications
(Guaranteed by Design)
Spec ID#
Parameter
Description
Details/Conditions
SID218
IIMO1
IMO operating current at 48 MHz
–
–
250
µA
–
SID219
IIMO2
IMO operating current at 24 MHz
–
–
180
µA
–
Min
Typ
Max
Units
Table 30. IMO AC Specifications
Spec ID#
Parameter
Description
SID223
Details/Conditions
–
–
±2
%
–
FIMOTOL1
Frequency variation at 24, 32, and
48 MHz (trimmed)
–
–
±2.5
%
At 105 °C, 44-TQFP
and 32-QFN
packages
SID226
TSTARTIMO
IMO startup time
–
–
7
µs
–
SID228
TJITRMSIMO2
RMS jitter at 24 MHz
–
145
–
ps
–
Min
Typ
Max
Units
–
0.3
1.05
µA
SID223A
Internal Low-Speed Oscillator
Table 31. ILO DC Specifications
(Guaranteed by Design)
Spec ID#
SID231
Parameter
IILO1
Description
ILO operating current
Details/Conditions
–
Notes
12. Guaranteed by characterization.
13. Guaranteed by design.
Document Number: 002-26566 Rev. *C
Page 32 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Table 32. ILO AC Specifications
Min
Typ
Max
Units
SID234[14] TSTARTILO1
SID236[14] TILODUTY
Spec ID#
Parameter
ILO startup time
Description
–
–
2
ms
–
ILO duty cycle
40
50
60
%
–
SID237
ILO frequency range
20
40
80
kHz
–
FILOTRIM1
Details/Conditions
Watch Crystal Oscillator (WCO)
Table 33. WCO Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID398
FWCO
Crystal frequency
–
32.768
–
kHz
–
SID399
FTOL
Frequency tolerance
–
50
250
ppm
With 20-ppm crystal
SID400
ESR
Equivalent series resistance
–
50
–
kΩ
–
SID401
PD
Drive Level
–
–
1
µW
–
SID402
TSTART
Startup time
–
–
500
ms
–
SID403
CL
Crystal Load Capacitance
6
–
12.5
pF
–
SID404
C0
Crystal Shunt Capacitance
–
1.35
–
pF
–
SID405
IWCO1
Operating Current (high power mode)
–
–
8
µA
–
Min
Typ
Max
Units
External Clock
Table 34. External Clock Specifications
Spec ID#
[15]
Parameter
Description
Details/Conditions
ExtClkFreq
External clock input frequency
0
–
48
MHz
–
SID306[15] ExtClkDuty
Duty cycle; measured at VDD/2
45
–
55
%
–
Min
Typ
Max
SID305
External Crystal Oscillator and PLL
Table 35. External Crystal Oscillator (ECO) Specifications
Spec ID#
Parameter
Description
Units
Details/Conditions
–
SID316[15]
IECO1
Block current
–
–
1.5
mA
[15]
FECO
Crystal frequency range
4
–
33
MHz –
SID317
Notes
14. Guaranteed by design.
15. Guaranteed by characterization.
Document Number: 002-26566 Rev. *C
Page 33 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Table 36. PLL Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SID410
IDD_PLL_48
In = 3 MHz, Out = 48 MHz
–
530
610
µA
–
SID411
IDD_PLL_24
In = 3 MHz, Out = 24 MHz
–
300
405
µA
–
SID412
Fpllin
PLL input frequency
1
–
48
MHz
–
SID413
Fpllint
PLL intermediate frequency;
prescaler out
1
–
3
MHz
–
SID414
Fpllvco
VCO output frequency before
post-divide
22.5
–
104
MHz
–
SID415
Divvco
VCO Output post-divider range; PLL
output frequency is Fpplvco/Divvco
1
–
8
SID416
Plllocktime
Lock time at startup
–
–
250
µs
–
SID417
Jperiod_1
Period jitter for VCO ≥ 67 MHz
–
–
150
ps
Guaranteed by design
SID416A
Jperiod_2
Period jitter for VCO ≤ 67 MHz
–
–
200
ps
Guaranteed by design
Min
Typ
Max
3
–
4
Min
Typ
Max
Units
–
–
1.6
ns
–
System Clock
Table 37. System Clock Spec
Spec ID#
Parameter
SID262[16] TCLKSWITCH
Description
System clock source switching time
Units
Details/Conditions
Periods –
Smart I/O
Table 38. Smart I/O Pass-through Time (Delay in Bypass Mode)
Spec ID#
SID252
Parameter
Description
PRG_BYPASS Max delay added by Smart I/O in
bypass mode
Details / Conditions
–
Note
16. Guaranteed by characterization.
Document Number: 002-26566 Rev. *C
Page 34 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Ordering Information
4148
CSD
10-bit CSD ADC
12-bit SAR ADC
SAR ADC Sample Rate
LP Comparators
TCPWM Blocks
SCB Blocks
ECO / PLL
Smart IOs
GPIO
48-TQFP
64-TQFP (0.5mm pitch)
64-TQFP (0.8mm pitch)
Temp Range (oC)
24 256 32
2
-
1
1
806 Ksps
2
8
4
X
16
38
X
-
-
-40 to 85
CY8C4128AZI-S445
24 256 32
2
-
1
1
806 Ksps
2
8
5
X
16
54
-
X
-
-40 to 85
CY8C4128AXI-S445
24 256 32
2
-
1
1
806 Ksps
2
8
5
X
16
54
-
-
X
-40 to 85
CY8C4128AZI-S453
24 256 32
2
1
1
1
806 Ksps
2
8
4
X
16
38
X
-
-
-40 to 85
CY8C4128AZI-S455
24 256 32
2
1
1
1
806 Ksps
2
8
5
X
16
54
-
X
-
-40 to 85
CY8C4128AXI-S455
24 256 32
2
1
1
1
806 Ksps
2
8
5
X
16
54
-
-
X
-40 to 85
CY8C4148AZI-S443
48 256 32
2
1
1
1 Msps
2
8
4
X
16
38
X
X
Flash (KB)
Op-amp (CTBm)
Max CPU Speed (MHz)
Packages
SRAM (KB)
4128
Features
CY8C4128AZI-S443
MPN
Category
The marketing part numbers for the PSoC 4100S Plus 256KB devices are listed in the following table.
-40 to 85
CY8C4148AZQ-S443
48 256 32
2
1
1
1 Msps
2
8
4
X
16
38
CY8C4148AZI-S445
48 256 32
2
1
1
1 Msps
2
8
5
X
16
54
X
-40 to 105
-40 to 85
CY8C4148AZQ-S445
48 256 32
2
1
1
1 Msps
2
8
5
X
16
54
X
-40 to 105
CY8C4148AXI-S445
48 256 32
2
1
1
1 Msps
2
8
5
X
16
54
CY8C4148AXQ-S445
48 256 32
2
1
1
1 Msps
2
8
5
X
16
54
CY8C4148AZI-S453
48 256 32
2
1
1
1
1 Msps
2
8
4
X
16
38
X
-40 to 85
CY8C4148AZQ-S453
48 256 32
2
1
1
1
1 Msps
2
8
4
X
16
38
X
-40 to 105
CY8C4148AZI-S455
48 256 32
2
1
1
1
1 Msps
2
8
5
X
16
54
X
X
X
-40 to 85
X -40 to 105
-40 to 85
CY8C4148AZQ-S455
48 256 32
2
1
1
1
1 Msps
2
8
5
X
16
54
CY8C4148AXI-S455
48 256 32
2
1
1
1
1 Msps
2
8
5
X
16
54
X
CY8C4148AXQ-S455
48 256 32
2
1
1
1
1 Msps
2
8
5
X
16
54
X -40 to 105
Document Number: 002-26566 Rev. *C
-40 to 105
-40 to 85
Page 35 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
The nomenclature used in the preceding table is based on the following part numbering convention:
Field
Description
CY8C
Cypress Prefix
Values
Meaning
4
Architecture
4
PSoC 4
A
Family
1
4100 Family
B
CPU Speed
2
24 MHz
4
48 MHz
4
16 KB
5
32 KB
6
64 KB
7
128 KB
AX
TQFP (0.8-mm pitch)
C
Flash Capacity
DE
Package Code
AZ
TQFP (0.5-mm pitch)
LQ
QFN
PV
SSOP
FN
CSP
Industrial
Extended Industrial
F
Temperature Range
I
Q
S
Series Designator
S
PSoC 4 S-Series
M
PSoC 4 M-Series
XYZ
Attributes Code
L
PSoC 4 L-Series
BL
PSoC 4 BLE-Series
000-999
Code of feature set in the specific family
The following is an example of a part number:
CY8C 4 A B C DE F – S XYZ
Example
Cypress Prefix
Architecture
4 : PSoC 4
1: 4100 Family
Family within Architecture
CPU Speed
4 : 48 MHz
5 : 32 KB
Flash Capacity
AZ/AX: TQFP
Package Code
I : Industrial
Temperature Range
Series Designator
Attributes Code
Document Number: 002-26566 Rev. *C
Page 36 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Packaging
The PSoC 4100S Plus 256KB is offered in 48-pin TQFP, 64-pin TQFP Normal pitch, and 64-pin TQFP Fine Pitch packages.
Package dimensions and Cypress drawing numbers are in the following table.
Table 39. Package List
Spec ID#
Package
Description
Package Dwg
BID20
64-pin TQFP
14 × 14 × 1.4-mm height with 0.8-mm pitch
51-85046
BID27
64-pin TQFP
10 × 10 × 1.6-mm height with 0.5-mm pitch
51-85051
BID70
48-pin TQFP
7 × 7 × 1.4-mm height with 0.5-mm pitch
51-85135
Table 40. Package Thermal Characteristics
Package
Min
Typ
Max
Units
TA
Parameter
Operating ambient temperature
Description
–
–40
25
105
°C
TJ
Operating junction temperature
–
–40
–
125
°C
TJA
Package θJA
64-pin TQFP (0.5-mm pitch)
–
46
–
°C/Watt
TJC
Package θJC
64-pin TQFP (0.5-mm pitch)
–
10
–
°C/Watt
TJA
Package θJA
64-pin TQFP (0.8-mm pitch)
–
36.8
–
°C/Watt
TJC
Package θJC
64-pin TQFP (0.8-mm pitch)
–
9.4
–
°C/Watt
TJA
Package θJA
48-pin TQFP (0.5-mm pitch)
–
39.4
–
°C/Watt
TJC
Package θJC
48-pin TQFP (0.5-mm pitch)
–
9.3
–
°C/Watt
Table 41. Solder Reflow Peak Temperature
Package
Maximum Peak
Temperature
Maximum Time at Peak Temperature
All
260 °C
30 seconds
Table 42. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-020
Package
MSL
All
MSL 3
Document Number: 002-26566 Rev. *C
Page 37 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Package Diagrams
Figure 8. 64-pin TQFP Package (0.8-mm Pitch) Outline
ș1
ș
ș2
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
A
1.60
A1
0.05
A2
1.35 1.40 1.45
0.15
D
15.75 16.00 16.25
D1
13.95 14.00 14.05
E
15.75 16.00 16.25
E1
13.95 14.00 14.05
R1
0.08
0.20
R2
0.08
0.20
ș
0°
7°
ș1
0°
ș2
11°
c
12°
b
0.30 0.35 0.40
0.45 0.60 0.75
L2
L3
e
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
13°
0.20
L
L1
NOTE:
1.00 REF
0.25 BSC
0.20
0.80 TYP
51-85046 *H
Document Number: 002-26566 Rev. *C
Page 38 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Figure 9. 64-pin TQFP Package (0.5-mm Pitch) Outline
51-85051 *D
Figure 10. 48-Pin 7 × 7 × 1.4 mm TQFP Package Outline
51-85135 *C
Document Number: 002-26566 Rev. *C
Page 39 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Acronyms
Table 43. Acronyms Used in this Document
Acronym
Description
abus
analog local bus
ADC
analog-to-digital converter
AG
analog global
AHB
AMBA (advanced microcontroller bus
architecture) high-performance bus, an Arm data
transfer bus
Table 43. Acronyms Used in this Document (continued)
Acronym
Description
ESD
electrostatic discharge
ETM
embedded trace macrocell
FIR
finite impulse response, see also IIR
FPB
flash patch and breakpoint
FS
full-speed
GPIO
general-purpose input/output, applies to a PSoC
pin
ALU
arithmetic logic unit
AMUXBUS
analog multiplexer bus
HVI
high-voltage interrupt, see also LVI, LVD
API
application programming interface
IC
integrated circuit
APSR
application program status register
IDAC
current DAC, see also DAC, VDAC
Arm®
advanced RISC machine, a CPU architecture
IDE
integrated development environment
ATM
automatic thump mode
BW
bandwidth
CAN
Controller Area Network, a communications
protocol
I2C,
or IIC
Inter-Integrated Circuit, a communications
protocol
IIR
infinite impulse response, see also FIR
ILO
internal low-speed oscillator, see also IMO
internal main oscillator, see also ILO
CMRR
common-mode rejection ratio
IMO
CPU
central processing unit
INL
integral nonlinearity, see also DNL
CRC
cyclic redundancy check, an error-checking
protocol
I/O
input/output, see also GPIO, DIO, SIO, USBIO
IPOR
initial power-on reset
DAC
digital-to-analog converter, see also IDAC,
VDAC
IPSR
interrupt program status register
DFB
digital filter block
IRQ
interrupt request
DIO
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
ITM
instrumentation trace macrocell
LCD
liquid crystal display
LIN
Local Interconnect Network, a communications
protocol.
LR
link register
LUT
lookup table
LVD
low-voltage detect, see also LVI
LVI
low-voltage interrupt, see also HVI
LVTTL
low-voltage transistor-transistor logic
MAC
multiply-accumulate
MCU
microcontroller unit
MISO
master-in slave-out
NC
no connect
nonmaskable interrupt
DMIPS
Dhrystone million instructions per second
DMA
direct memory access, see also TD
DNL
differential nonlinearity, see also INL
DNU
do not use
DR
port write data registers
DSI
digital system interconnect
DWT
data watchpoint and trace
ECC
error correcting code
ECO
external crystal oscillator
EEPROM
electrically erasable programmable read-only
memory
EMI
electromagnetic interference
NMI
EMIF
external memory interface
NRZ
non-return-to-zero
EOC
end of conversion
NVIC
nested vectored interrupt controller
EOF
end of frame
NVL
nonvolatile latch, see also WOL
execution program status register
opamp
operational amplifier
EPSR
Document Number: 002-26566 Rev. *C
Page 40 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Table 43. Acronyms Used in this Document (continued)
Acronym
Description
Table 43. Acronyms Used in this Document (continued)
Acronym
Description
PAL
programmable array logic, see also PLD
SWD
serial wire debug, a test protocol
PC
program counter
SWV
single-wire viewer
PCB
printed circuit board
TD
transaction descriptor, see also DMA
PGA
programmable gain amplifier
THD
total harmonic distortion
PHUB
peripheral hub
TIA
transimpedance amplifier
PHY
physical layer
TRM
technical reference manual
PICU
port interrupt control unit
TTL
transistor-transistor logic
PLA
programmable logic array
TX
transmit
PLD
programmable logic device, see also PAL
UART
PLL
phase-locked loop
Universal Asynchronous Transmitter Receiver, a
communications protocol
PMDD
package material declaration data sheet
UDB
universal digital block
POR
power-on reset
USB
Universal Serial Bus
PRES
precise power-on reset
USBIO
PRS
pseudo random sequence
USB input/output, PSoC pins used to connect to
a USB port
PS
port read data register
VDAC
voltage DAC, see also DAC, IDAC
PSoC®
Programmable System-on-Chip™
WDT
watchdog timer
PSRR
power supply rejection ratio
WOL
write once latch, see also NVL
PWM
pulse-width modulator
WRES
watchdog timer reset
RAM
random-access memory
XRES
external reset I/O pin
RISC
reduced-instruction-set computing
XTAL
crystal
RMS
root-mean-square
RTC
real-time clock
RTL
register transfer language
RTR
remote transmission request
RX
receive
SAR
successive approximation register
SC/CT
switched capacitor/continuous time
SCL
I2C serial clock
SDA
I2C serial data
S/H
sample and hold
SINAD
signal to noise and distortion ratio
SIO
special input/output, GPIO with advanced
features. See GPIO.
SOC
start of conversion
SOF
start of frame
SPI
Serial Peripheral Interface, a communications
protocol
SR
slew rate
SRAM
static random access memory
SRES
software reset
Document Number: 002-26566 Rev. *C
Page 41 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Document Conventions
Units of Measure
Table 44. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
dB
decibel
fF
femto farad
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohour
kHz
kilohertz
k
kilo ohm
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
M
mega-ohm
Msps
megasamples per second
µA
microampere
µF
microfarad
µH
microhenry
µs
microsecond
µV
microvolt
µW
microwatt
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
nV
nanovolt
ohm
pF
picofarad
ppm
parts per million
ps
picosecond
s
second
sps
samples per second
sqrtHz
square root of hertz
V
volt
Document Number: 002-26566 Rev. *C
Page 42 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Revision History
Description Title: PSoC 4: PSoC 4100S Plus 256KB Datasheet Programmable System-on-Chip (PSoC)
Document Number: 002-26566
Submission
Revision
ECN
Description of Change
Date
*B
6828229
03/18/2020 Release to web.
Added ModusToolbox™ in Features.
Updated Development Ecosystem.
Added ModusToolbox™ Software.
*C
7021633
11/10/2020
Updated Table 25: Updated SID182B.
Updated Table 30: Added SID223A.
Updated Ordering Information.
Document Number: 002-26566 Rev. *C
Page 43 of 44
PSoC 4: PSoC 4100S Plus 256KB Datasheet
Sales, Solutions, and Legal Information
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closest to you, visit us at Cypress Locations.
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© Cypress Semiconductor Corporation, 2019-2020 This document is the property of Cypress Semiconductor Corporation and its subsidiaries ("Cypress"). This document, including any software or
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Document Number: 002-26566 Rev. *C
Revised November 10, 2020
Page 44 of 44
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