Please note that Cypress is an Infineon Technologies Company.
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The fact that Infineon offers the following product as part of the Infineon product
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Infineon continues to support existing part numbers. Please continue to use the
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www.infineon.com
PSoC 4: PSoC 4100PS Datasheet
Programmable System-on-Chip (PSoC)
General Description
Cypress' PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers
with an Arm® Cortex™-M0+ CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic
routing. PSoC 4100PS is a member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard
communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, programmable
general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity.
Features
Programmable Analog Blocks
Low-Power Operation
■
Two dedicated analog-to-digital converters (ADC) including a
12-bit SAR ADC and a 10-bit single-slope ADC
■
Four opamps, two low-power comparators, and a flexible
38-channel analog mux to create custom Analog Front Ends
(AFE)
■
1.71-V to 5.5-V operation
■
Deep-Sleep mode with operational analog and 2.5-µA digital
system current
■
Watch Crystal Oscillator (WCO)
■
Two 13-bit Voltage DACs
Programmable GPIO Pins
■
Two 7-bit Current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
■
Up to 38 GPIOs that can be used for analog, digital, CapSense,
or LCD functions with programmable drive modes, strength and
slew rates
■
Includes eight Smart I/Os to implement pin-level Boolean
operations on input and output signals
■
48-pin QFN, 48-pin TQFP, 28-pin SSOP, and 45-ball WLCSP
packages
CapSense® Capacitive Sensing
■
Cypress's fourth-generation CapSense Sigma-Delta (CSD)
providing best-in-class signal-to-noise ratio (SNR) and water
tolerance
■
Cypress-supplied software component makes capacitive
sensing design easy
PSoC Creator Design Environment
■
Automatic hardware tuning (SmartSense™)
■
Integrated Design Environment (IDE) provides
schematic-capture design entry and build (with automatic
routing of analog and digital signals) and concurrent firmware
development with an Arm-SWD debugger
■
GUI-based configurable PSoC Components with fully
engineered embedded initialization, calibration and correction
algorithms
Application Programming Interfaces (API) for all fixed-function
and programmable peripherals
Segment LCD Drive
■
LCD drive supported on all pins (common or segment)
■
Operates in Deep-Sleep mode with four bits per pin memory
Programmable Digital Peripherals
■
Three independent serial communication blocks (SCBs) that
are run-time configurable as I2C, SPI or UART
■
■
Eight 16-bit timer/counter/pulse-width modulator (TCPWM)
blocks with center-aligned, edge, and pseudo-random modes
Industry-Standard Tool Compatibility
■
32-bit Signal Processing Engine
■
Arm Cortex-M0+ CPU up to 48 MHz
■
Up to 32 KB of flash with read accelerator
■
Up to 4 KB of SRAM
■
Eight-channel descriptor-based DMA controller
Cypress Semiconductor Corporation
Document Number: 002-22097 Rev. *E
•
198 Champion Court
After schematic-capture, firmware development can be done
with Arm-based industry-standard development tools
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 17, 2020
PSoC 4: PSoC 4100PS Datasheet
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP. Following is an abbreviated list for PSoC 4:
■
Overview: PSoC Portfolio, PSoC Roadmap
■
Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP
In addition, PSoC Creator includes a device selection tool.
■
Application notes: Cypress offers a large number of PSoC
application notes covering a broad range of topics, from basic
to advanced level. Recommended application notes for getting
started with PSoC 4 are:
❐ AN79953: Getting Started With PSoC 4
❐ AN88619: PSoC 4 Hardware Design Considerations
❐ AN86439: Using PSoC 4 GPIO Pins
❐ AN57821: Mixed Signal Circuit Board Layout
❐ AN81623: Digital Design Best Practices
❐ AN73854: Introduction To Bootloaders
❐ AN89610: Arm Cortex Code Optimization
®
❐ AN85951: PSoC 4 and PSoC Analog Coprocessor
CapSense® Design Guide
■
■
Software User Guide:
❐ A step-by-step guide for using PSoC Creator. The software
user guide shows you how the PSoC Creator build process
works in detail, how to use source control with PSoC Creator,
and much more.
■
Component Datasheets:
❐ The flexibility of PSoC allows the creation of new peripherals
(components) long after the device has gone into production.
Component datasheets provide all the information needed to
select and use a particular component, including a functional
description, API documentation, example code, and AC/DC
specifications.
■
Online:
❐ In addition to print documentation, the Cypress PSoC forums
connect you with fellow PSoC users and experts in PSoC
from around the world, 24 hours a day, 7 days a week.
Technical Reference Manual (TRM) is in two documents:
❐ Architecture TRM details each PSoC 4 functional block.
❐ Registers TRM describes each of the PSoC 4 registers.
Development Kits:
®
❐ CY8CKIT-147 PSoC 4100PS Prototyping Kit enables you
to evaluate and develop with PSoC 4100PS devices at a low
cost.
The MiniProg3 device provides an interface for flash
programming and debug.
■
Document Number: 002-22097 Rev. *E
Page 2 of 45
PSoC 4: PSoC 4100PS Datasheet
PSoC Creator
PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100
pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can:
1. Drag and drop component icons to build your hardware
system design in the main design workspace
2. Codesign your application firmware with the PSoC hardware,
using the PSoC Creator IDE C compiler
3. Configure components using the configuration tools
4. Explore the library of 100+ components
5. Review component datasheets
Figure 1. Multiple-Sensor Example Project in PSoC Creator
1
2
3
4
5
Document Number: 002-22097 Rev. *E
Page 3 of 45
PSoC 4: PSoC 4100PS Datasheet
Contents
Functional Definition ........................................................ 6
CPU and Memory Subsystem ..................................... 6
System Resources ...................................................... 6
Analog Blocks .............................................................. 7
Fixed Function Digital .................................................. 8
GPIO ........................................................................... 8
Special Function Peripherals ....................................... 9
WLCSP Package Bootloader ...................................... 9
Pinouts ............................................................................ 10
Alternate Pin Functions ............................................. 12
Power ............................................................................... 14
Mode 1: 1.8 V to 5.5 V External Supply .................... 14
Development Support .................................................... 15
Documentation .......................................................... 15
Online ........................................................................ 15
Tools .......................................................................... 15
Electrical Specifications ................................................ 16
Absolute Maximum Ratings ...................................... 16
Document Number: 002-22097 Rev. *E
Device Level Specifications ....................................... 16
Analog Peripherals .................................................... 20
Digital Peripherals ..................................................... 30
Memory ..................................................................... 32
System Resources .................................................... 33
Ordering Information ...................................................... 35
Packaging ........................................................................ 37
Package Diagrams .................................................... 38
Acronyms ........................................................................ 41
Document Conventions ................................................. 43
Units of Measure ....................................................... 43
Revision History ............................................................. 44
Sales, Solutions, and Legal Information ...................... 45
Worldwide Sales and Design Support ....................... 45
Products .................................................................... 45
PSoC® Solutions ...................................................... 45
Cypress Developer Community ................................. 45
Technical Support ..................................................... 45
Page 4 of 45
PSoC 4: PSoC 4100PS Datasheet
Figure 2. Block Diagram
CPU
CPU
Subsystem
Subsystem
32- bit
AHB -Lite
SWD/ TC
SPCIF
Cortex
M0+
48 MHz
FLASH
32 KB
SRAM
4 KB
Read Accelerator
SRAM Controller
FAST MUL
NVIC, IRQMX
System Resources
Lite
Initiator / MMIO
x1
SARMUX
x2
CTB
2 x Opamp
WCO
VDAC
(13-bit)
2x LP Comparator
SAR ADC
( 12- bit)
8x TCPWM
Programmable
Analog
3x SCB-I2C/SPI/UART
Peripheral Interconnect (MMIO)
PCLK
I OSS GPIO (6x ports)
Test
DFT Logic
DFT Analog
ROM Controller
DataWire /
DMA
Peripherals
Clock
Clock Control
WDT
IMO
ILO
Reset
Reset Control
XRES
ROM
8 KB
System Interconnect (Multi Layer AHB)
Power
Sleep Control
WIC
POR
REF
PWRSYS
CapSense
PSoC 4100 PS
Architecture
x2
High Speed I /O Matrix , Smart I/O
Power Modes
Active/ Sleep
Deep Sleep
38 x GPIO, LCD
I/ O Subsystem
PSoC 4100PS devices include extensive support for
programming, testing, debugging, and tracing both hardware
and firmware.
The Arm Serial-Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE provides fully integrated programming
and debug support for the PSoC 4100PS devices. The SWD
interface is fully compatible with industry-standard third-party
tools. The PSoC 4100PS family provides a level of security not
possible with multi-chip application solutions or with
microcontrollers. It has the following advantages:
■
Allows disabling of debug features
■
Robust flash protection
■
Allows customer-proprietary functionality to be implemented in
on-chip programmable blocks
Document Number: 002-22097 Rev. *E
The debug circuits are enabled by default and can be disabled
in firmware. If they are not enabled, the only way to re-enable
them is to erase the entire device, clear flash protection, and
reprogram the device with new firmware that enables debugging.
Thus firmware control of debugging cannot be over-ridden
without erasing the firmware thus providing security.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. All programming, debug, and test interfaces are
disabled when maximum device security is enabled. Therefore,
PSoC 4100PS, with device security enabled, may not be
returned for failure analysis. This is a trade-off the PSoC 4100PS
allows the customer to make.
Page 5 of 45
PSoC 4: PSoC 4100PS Datasheet
Functional Definition
CPU and Memory Subsystem
CPU
The Cortex-M0+ CPU in the PSoC 4100PS is part of the 32-bit
MCU subsystem, which is optimized for low-power operation
with extensive clock gating. Most instructions are 16 bits in length
and the CPU executes a subset of the Thumb-2 instruction set.
It includes a nested vectored interrupt controller (NVIC) block
with eight interrupt inputs and also includes a Wakeup Interrupt
Controller (WIC). The WIC can wake the processor from Deep
Sleep mode, allowing power to be switched off to the main
processor when the chip is in Deep Sleep mode.
The CPU also includes a debug interface, the serial wire debug
(SWD) interface, which is a two-wire form of JTAG. The debug
configuration used for PSoC 4100PS has four breakpoint
(address) comparators and two watchpoint (data) comparators.
instantaneous wake-up on a wake-up event. In Deep Sleep
mode, the high-speed clock and associated circuitry is switched
off; wake-up from this mode takes 35 µs. The opamps can
remain operational in Deep Sleep mode.
Clock System
The PSoC 4100PS clock system is responsible for providing
clocks to all subsystems that require clocks and for switching
between different clock sources without glitching. In addition, the
clock system ensures that there are no metastable conditions.
The clock system for the PSoC 4100PS consists of the internal
main oscillator (IMO), internal low-frequency oscillator (ILO), a
32 kHz Watch Crystal Oscillator (WCO) and provision for an
external clock. Clock dividers are provided to generate clocks for
peripherals on a fine-grained basis. Fractional dividers are also
provided to enable clocking of higher data rates for UARTs.
Figure 3. PSoC 4100PS MCU Clocking Architecture
IM O
DMA/DataWire
The DMA engine will be capable of doing independent data
transfers anywhere within the memory map via a user-programmable descriptor chain. The DataWire capability is used to effect
single-element transfers from one location in memory to another.
There are eight DMA channels with a range of selectable trigger
sources.
E xterna l C lock
WCO
SRAM
Four KB of SRAM are provided with zero wait-state access at
48 MHz.
SROM
Eight KB of SROM are provided that contain boot and configuration routines.
System Resources
Power System
The power system is described in detail in the section Power on
page 14. It provides an assurance that voltage levels are as
required for each respective mode and either delays mode entry
(for example, on power-on reset (POR) until voltage levels are
as required for proper functionality, or generates resets (for
example, on brown-out detection). PSoC 4100PS operates with
a single external supply over the range of either 1.8 V ±5%
(externally regulated) or 1.8 to 5.5 V (internally regulated) and
has three different power modes, transitions between which are
managed by the power system. PSoC 4100PS provides Active,
Sleep, and Deep Sleep low-power modes.
All subsystems are operational in Active mode. The CPU
subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep
mode, while all peripherals and interrupts are active with
Document Number: 002-22097 Rev. *E
W DC0
16-bits
L F C LK
W DC1
16-bits
IL O
W DC2
32-bits
W DT
Flash
The PSoC 4100PS device has a flash module with a flash
accelerator, tightly coupled to the CPU to improve average
access times from the flash block. The low-power flash block is
designed to deliver two wait-state (WS) access time at 48 MHz.
The flash accelerator delivers 85% of single-cycle SRAM access
performance on average.
H F C LK
D ivide B y
2,4,8
W atchdog C ounters (W D C )
W atchdog T im er (W D T )
P re sca le r
S Y S C LK
H F C LK
Inte g er
D ivide rs
F ractio na l
D ivide rs
7 X 16-b it
3 X 16.5-bit, 1X 24.5 b it
The HFCLK signal can be divided down to generate
synchronous clocks for the analog and digital peripherals. There
are 11 clock dividers for PSoC 4100PS as shown in the diagram
above.. The 16-bit capability allows flexible generation of
fine-grained frequency values (there is one 24-bit divider for
large divide ratios), and is fully supported in PSoC Creator.
IMO Clock Source
The IMO is the primary source of internal clocking in
PSoC 4100PS. It is trimmed during testing to achieve the
specified accuracy.The IMO default frequency is 24 MHz and it
can be adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO
tolerance with Cypress-provided calibration settings is ±2%.
ILO Clock Source
The ILO is a very low power, nominally 40-kHz oscillator, which
is primarily used to generate clocks for the watchdog timer
(WDT) and peripheral operation in Deep Sleep mode. ILO-driven
counters can be calibrated to the IMO to improve accuracy.
Cypress provides a software component, which does the
calibration.
Page 6 of 45
PSoC 4: PSoC 4100PS Datasheet
Watch Crystal Oscillator (WCO)
Analog Blocks
The PSoC 4100PS clock subsystem also implements a
low-frequency (32-kHz watch crystal) oscillator that can be used
for Watchdog timing applications.
12-bit SAR ADC
Watchdog Timer
The 12-bit, 1-Msps SAR ADC can operate at a maximum clock
rate of 18 MHz and requires a minimum of 18 clocks at that
frequency to do a 12-bit conversion.
A watchdog timer is implemented in the clock block running from
the ILO; this allows watchdog operation during Deep Sleep and
generates a watchdog reset if not serviced before the set timeout
occurs. The watchdog reset is recorded in a Reset Cause
register, which is firmware readable.
The Sample-and-Hold (S/H) aperture is programmable allowing
the gain bandwidth requirements of the amplifier driving the SAR
inputs, which determine its settling time, to be relaxed if required.
It is possible to provide an external bypass (through a fixed pin
location) for the internal reference amplifier.
Reset
PSoC 4100PS can be reset from a variety of sources including
a software reset. Reset events are asynchronous and guarantee
reversion to a known state. The reset cause is recorded in a
register, which is sticky through reset and allows software to
determine the cause of the reset. An XRES pin is reserved for
external reset by asserting it active low. The XRES pin has an
internal pull-up resistor that is always enabled.
Voltage Reference
The PSoC 4100PS reference system generates all internally
required references. A 1.2-V voltage reference is provided for the
comparator. The IDACs are based on a ±5% reference.
The SAR is connected to a fixed set of pins through an 8-input
sequencer. The sequencer cycles through selected channels
autonomously (sequencer scan) with zero switching overhead
(that is, aggregate sampling bandwidth is equal to 1 Msps
whether it is for a single channel or distributed over several
channels). The sequencer switching is effected through a state
machine or through firmware driven switching. A feature
provided by the sequencer is buffering of each channel to reduce
CPU interrupt service requirements. To accommodate signals
with varying source impedance and frequency, it is possible to
have different sample times programmable for each channel.
Also, signal range specification through a pair of range registers
(low and high range values) is implemented with a corresponding
out-of-range interrupt if the digitized value exceeds the
programmed range; this allows fast detection of out-of-range
values without the necessity of having to wait for a sequencer
scan to be completed and the CPU to read the values and check
for out-of-range values in software.
The SAR is not available in Deep Sleep mode as it requires a
high-speed clock (up to 18 MHz). The SAR operating range is
1.71 V to 5.5 V.
Figure 4. SAR ADC
AHB System Bus and Programmable Logic
Interconnect
SAR Sequencer
vminus vplus
Data and
Status Flags
POS
SARADC
NEG
P7
SARMUX Port
(8 inputs)
SARMUX
P0
Sequencing
and Control
External
Reference
and
Bypass
(optional )
Reference
Selection
VDDA/2
VDDA
VREF
Inputs from other Ports
Four Opamps (Continuous-Time Block; CTB)
VDAC (13 bits)
PSoC 4100PS has four opamps with Comparator modes which
allow most common analog functions to be performed on-chip
eliminating external components; PGAs, Voltage Buffers, Filters,
Trans-Impedance Amplifiers, and other functions can be
realized, in some cases with external passives, saving power,
cost, and space. The on-chip opamps are designed with enough
bandwidth to drive the Sample-and-Hold circuit of the ADC
without requiring external buffering.
The PSoC 4100PS has two 13-bit resolution Voltage DACs.
Document Number: 002-22097 Rev. *E
Low-power Comparators (LPC)
PSoC 4100PS has a pair of low-power comparators, which can
also operate in Deep Sleep modes. This allows the analog
system blocks to be disabled while retaining the ability to monitor
external voltage levels during low-power modes. The
comparator outputs are normally synchronized to avoid
metastability unless operating in an asynchronous power mode
where the system wake-up circuit is activated by a comparator
switch event. The LPC outputs can be routed to pins.
Page 7 of 45
PSoC 4: PSoC 4100PS Datasheet
Current DACs
PSoC 4100PS has two IDACs, which can drive any of the pins
on the chip. These IDACs have programmable current ranges.
■
GPIO cells are not overvoltage tolerant and, therefore, cannot
be hot-swapped or powered up independently of the rest of the
I2C system.
Temperature Sensor
UART Mode: This is a full-feature UART operating at up to
1 Mbps. It supports automotive single-wire interface (LIN),
infrared interface (IrDA), and SmartCard (ISO7816) protocols, all
of which are minor variants of the basic UART protocol. In
addition, it supports the 9-bit multiprocessor mode that allows
addressing of peripherals connected over common RX and TX
lines. Common UART functions such as parity error, break
detect, and frame error are supported. An 8-deep FIFO allows
much greater CPU service latencies to be tolerated.
There is an on-chip temperature sensor which is calibrated
during production to achieve ±1% typical (±5% maximum)
deviation from accuracy. The SAR ADC is used to measure the
temperature.
SPI Mode: The SPI mode supports full Motorola SPI, TI SSP
(adds a start pulse used to synchronize SPI Codecs), and
National Microwire (half-duplex form of SPI). The SPI block can
use the FIFO.
Fixed Function Digital
GPIO
Analog Multiplexed Buses
PSoC 4100PS has two concentric independent buses that go
around the periphery of the chip. These buses (called amux
buses) are connected to firmware-programmable analog
switches that allow the chip's internal resources (IDACs,
comparator) to connect to any pin on the I/O Ports.
Timer/Counter/PWM (TCPWM) Block
The TCPWM block consists of a 16-bit counter with
user-programmable period length. There is a capture register to
record the count value at the time of an event (which may be an
I/O event), a period register that is used to either stop or
auto-reload the counter when its count is equal to the period
register, and compare registers to generate compare value
signals that are used as PWM duty cycle outputs. The block also
provides true and complementary outputs with programmable
offset between them to allow use as dead-band programmable
complementary PWM outputs. It also has a Kill input to force
outputs to a predetermined state; for example, this is used in
motor drive systems when an over-current state is indicated and
the PWM driving the FETs needs to be shut off immediately with
no time for software intervention. There are eight TCPWM blocks
in PSoC 4100PS.
Serial Communication Block (SCB)
PSoC 4100PS has three serial communication blocks, which can
be programmed to have SPI, I2C, or UART functionality.
I2C Mode: The hardware I2C block implements a full
multi-master and slave interface (it is capable of multi-master
arbitration). This block is capable of operating at speeds of up to
1 Mbps (Fast Mode Plus) and has flexible buffering options to
reduce interrupt overhead and latency for the CPU. It also
supports EZI2C that creates a mailbox address range in the
memory of PSoC 4100PS and effectively reduces I2C communication to reading from and writing to an array in memory. In
addition, the block supports an 8-deep FIFO for receive and
transmit which, by increasing the time given for the CPU to read
data, greatly reduces the need for clock stretching caused by the
CPU not having read data on time.
PSoC 4100PS has up to 38 GPIOs. The GPIO block implements
the following:
■ Eight drive modes:
❐ Analog input mode (input and output buffers disabled)
❐ Input only
❐ Weak pull-up with strong pull-down
❐ Strong pull-up with weak pull-down
❐ Open drain with strong pull-down
❐ Open drain with strong pull-up
❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
■ Input threshold select (CMOS or LVTTL)
■ Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes
■ Selectable slew rates for dV/dt related noise control to improve
EMI.
The pins are organized in logical entities called ports, which are
8-bit in width (less for Ports 2 and 3). During power-on and reset,
the blocks are forced to the disable state so as not to crowbar
any inputs and/or cause excess turn-on current. A multiplexing
network known as a high-speed I/O matrix is used to multiplex
between various signals that may connect to an I/O pin.
Data output and pin state registers store, respectively, the values
to be driven on the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled; each I/O
port has an interrupt request (IRQ) and interrupt service routine
(ISR) vector associated with it (4 for PSoC 4100PS). The Smart
I/O block is a fabric of switches and LUTs that allows Boolean
functions to be performed on signals being routed to the pins of
a GPIO port. The Smart I/O block can perform logical operations
on input pins to the chip and on signals going out as outputs.
The I2C peripheral is compatible with the I2C Standard-mode and
Fast-mode devices as defined in the NXP I2C-bus specification
and user manual (UM10204). The I2C bus I/O is implemented
with GPIO in open-drain modes.
PSoC 4100PS is not completely compliant with the I2C spec in
the following respect:
Document Number: 002-22097 Rev. *E
Page 8 of 45
PSoC 4: PSoC 4100PS Datasheet
Special Function Peripherals
CapSense
CapSense is supported in PSoC 4100PS through a CSD block
that can be connected to any pins through an analog mux bus
via an analog switch. CapSense function can thus be provided
on any available pin or group of pins in a system under software
control. A PSoC Creator component is provided for the
CapSense block to make it easy for the user.
Shield voltage can be driven on another mux bus to provide
water-tolerance capability. Water tolerance is provided by driving
the shield electrode in phase with the sense electrode to keep
the shield capacitance from attenuating the sensed input.
Proximity sensing can also be implemented.
The CapSense block has two IDACs, which can be used for
general purposes if CapSense is not being used (both IDACs are
available in that case) or if CapSense is used without water
tolerance (one IDAC is available). The CapSense block also
provides a 10-bit Slope ADC function, which can be used in
conjunction with the CapSense function.
The CapSense block is an advanced, low-noise, programmable
block with programmable voltage references and current source
ranges for improved sensitivity and flexibility. It can also use an
external reference voltage. It has a full-wave CSD mode that
alternates sensing to VDDA and ground to null out power-supply
related noise
Document Number: 002-22097 Rev. *E
WLCSP Package Bootloader
The WLCSP package is supplied with an I2C bootloader installed
in flash. The bootloader is compatible with PSoC Creator
bootloader project files.
Page 9 of 45
PSoC 4: PSoC 4100PS Datasheet
Pinouts
The following table provides the pin list for PSoC 4100PS for the 48-QFN, 48-TQFP, 45-WLCSP, and 28-SSOP packages. All port
pins support GPIO.
Packages
48-QFN
48-TQFP
28-SSOP
45-CSP
Pin
Name
Pin
Name
Pin
Name
Pin
Name
28
P0.0
28
P0.0
21
P0.0
D3
P0.0
29
P0.1
29
P0.1
22
P0.1
E2
P0.1
30
P0.2
30
P0.2
23
P0.2
D2
P0.2
31
P0.3
31
P0.3
C3
P0.3
32
P0.4
32
P0.4
D1
P0.4
33
P0.5
33
P0.5
E1
P0.5
34
P0.6
34
P0.6
C2
P0.6
35
P0.7
35
P0.7
36
XRES
36
XRES
37
P4.0
37
38
P4.1
38
39
P5.0
39
P5.0
40
P5.1
40
P5.1
41
P5.2
41
P5.2
26
42
P5.3
42
P5.3
27
43
VDDA
43
VDDA
28
44
VSSA
44
VSSA
45
VCCD
45
VCCD
B2
P0.7
B3
XRES
P4.0
A1
P4.0
P4.1
B1
P4.1
24
25
1
XRES
P5.0
B4
P5.0
C1
P5.1
P5.2
A2
P5.2
P5.3
A3
P5.3
VDDA
J2
VDDA
J3
VSSA
A4
VCCD
B5
VDDD
A5
VSSD
VCCD
46
VSSD
46
VSSD
2
VSSD
47
VDDD
47
VDDD
3
VDDD
48
P1.0
48
P1.0
4
P1.0
C5
P1.0
1
P1.1
1
P1.1
5
P1.1
C4
P1.1
2
P1.2
2
P1.2
6
P1.2
D5
P1.2
3
P1.3
3
P1.3
7
P1.3
D4
P1.3
4
P1.4
4
P1.4
E3
P1.4
5
P1.5
5
P1.5
E4
P1.5
6
P1.6
6
P1.6
7
P1.7
7
P1.7
G3
P1.7
8
VDDA
8
VDDA
8
VDDA
E5
VDDA
9
VSSA
9
VSSA
9
VSSA
F5
VSSA
10
P2.0
10
P2.0
10
P2.0
F4
P2.0
11
P2.1
11
P2.1
11
P2.1
F3
P2.1
12
P2.2
12
P2.2
12
P2.2
G4
P2.2
13
P2.3
13
P2.3
13
P2.3
G5
P2.3
14
P2.4
14
P2.4
H5
P2.4
15
P2.5
15
P2.5
J4
P2.5
16
P2.6
16
P2.6
H4
P2.6
Document Number: 002-22097 Rev. *E
Page 10 of 45
PSoC 4: PSoC 4100PS Datasheet
Packages
48-QFN
48-TQFP
28-SSOP
45-CSP
Pin
Name
Pin
Name
Pin
Name
Pin
Name
17
P2.7/VREF
17
P2.7/VREF
14
P2.7/VREF
J5
P2.7/VREF
18
VSSA
18
VSSA
J3
VSSA
19
VDDA
19
VDDA
20
P3.0
20
P3.0
21
P3.1
21
P3.1
16
22
P3.2
22
P3.2
17
23
P3.3
23
P3.3
18
24
P3.4
24
P3.4
25
P3.5
25
P3.5
26
P3.6
26
P3.6
19
P3.6
27
P3.7
27
P3.7
20
P3.7
15
VDDA
J2
VDDA
H2
P3.0
P3.1
F2
P3.1
P3.2
J1
P3.2
P3.3
H3
P3.3
F1
P3.4
G2
P3.5
G1
P3.6
H1
P3.7
Descriptions of the Power pins are as follows:
VDDD: Power supply for the digital section.
VDDA: Power supply for the analog section.
VSS: Ground pin.
VCCD: Regulated digital supply (1.8 V ±5%)
The 48-pin packages have 38 I/O pins. The 45 CSP and the 28 SSOP have 37 and 20 I/O pins respectively.
Document Number: 002-22097 Rev. *E
Page 11 of 45
PSoC 4: PSoC 4100PS Datasheet
Alternate Pin Functions
Each Port pin has can be assigned to one of multiple functions; it can, for example, be an Analog I/O, a Digital Peripheral function, or a CapSense or LCD pin. The pin
assignments are shown in the following table.
Port/Pin
Analog
SmartIO
Active
ACT #0
ACT #1
DeepSleep
ACT #2
ACT #3
DS #0
DS #1
P0.0
SmartIO[0].io[0]
tcpwm.line[4]:1
tcpwm.tr_in[0]
cpuss.swd_data:0
scb[0].spi_select1:0
P0.1
SmartIO[0].io[1]
tcpwm.line_compl[4]:1
tcpwm.tr_in[1]
cpuss.swd_clk:0
scb[0].spi_select2:0
P0.2
SmartIO[0].io[2]
tcpwm.line[5]:1
P0.3
SmartIO[0].io[3]
tcpwm.line_compl[5]:1
srss.ext_clk
scb[0].spi_select3:0
P0.4
SmartIO[0].io[4]
tcpwm.line[6]:1
scb[1].uart_rx:0
scb[1].i2c_scl:0
scb[1].spi_mosi:0
P0.5
SmartIO[0].io[5]
tcpwm.line_compl[6]:1
scb[1].uart_tx:0
scb[1].i2c_sda:0
scb[1].spi_miso:0
P0.6
SmartIO[0].io[6]
scb[1].uart_cts:0
lpcomp.comp[0]:0
scb[1].spi_clk:0
P0.7
SmartIO[0].io[7]
scb[1].uart_rts:0
lpcomp.comp[1]:0
scb[1].spi_select0:0
P4.0
wco_in
tcpwm.line[0]:2
scb[2].uart_rx:1
tcpwm.tr_in[5]
scb[2].i2c_scl:1
scb[2].spi_mosi:1
P4.1
wco_out
tcpwm.line_compl[0]:2
scb[2].uart_tx:1
tcpwm.tr_in[6]
scb[2].i2c_sda:1
scb[2].spi_miso:1
P5.0
csd.cshieldpads
tcpwm.line[7]:1
scb[0].uart_rx:1
scb[0].i2c_scl:1
scb[0].spi_mosi:1
P5.1
csd.vref_ext
tcpwm.line_compl[7]:1
scb[0].uart_tx:1
scb[0].i2c_sda:1
scb[0].spi_miso:1
P5.2
csd.dsi_cmod
tcpwm.line[6]:2
scb[0].uart_cts:1
P5.3
csd.dsi_csh_tank
tcpwm.line_compl[6]:2
scb[0].uart_rts:1
P1.0
ctb_pads[8]
lpcomp.in_p[1]
tcpwm.line[0]:1
scb[1].uart_rx:1
scb[1].i2c_scl:1
scb[1].spi_mosi:1
P1.1
ctb_pads[9]
lpcomp.in_n[1]
tcpwm.line_compl[0]:1
scb[1].uart_tx:1
scb[1].i2c_sda:1
scb[1].spi_miso:1
P1.2
ctb_pads[10]
ctb_oa0_out_10x[1]
tcpwm.line[1]:1
scb[1].uart_cts:1
scb[1].spi_clk:1
P1.3
ctb_pads[11]
ctb_oa1_out_10x[1]
tcpwm.line_compl[1]:1
scb[1].uart_rts:1
scb[1].spi_select0:1
P1.4
ctb_pads[12]
tcpwm.line[2]:1
scb[1].spi_select1:0
P1.5
ctb_pads[13]
tcpwm.line_compl[2]:1
scb[1].spi_select2:0
P1.6
ctb_pads[14]
tcpwm.line[3]:1
scb[1].spi_select3:0
P1.7
ctb_pads[15]
tcpwm.line_compl[3]:1
P2.0
ctb_pads[0]
tcpwm.line[4]:0
Document Number: 002-22097 Rev. *E
scb[2].uart_rx:0
tr_sar_out
scb[0].spi_clk:1
scb[0].spi_select0:1
scb[2].i2c_scl:0
scb[2].spi_mosi:0
Page 12 of 45
PSoC 4: PSoC 4100PS Datasheet
Port/Pin
Analog
P2.1
SmartIO
Active
DeepSleep
ACT #0
ACT #1
ctb_pads[1]
tcpwm.line_compl[4]:0
scb[2].uart_tx:0
P2.2
ctb_pads[2]
ctb_oa0_out_10x[0]
tcpwm.line[5]:0
scb[2].uart_cts:0
scb[2].spi_clk:0
P2.3
ctb_pads[3]
ctb_oa1_out_10x[0]
tcpwm.line_compl[5]:0
scb[2].uart_rts:0
scb[2].spi_select0:0
P2.4
ctb_pads[4]
tcpwm.line[0]:0
scb[2].spi_select1:0
P2.5
ctb_pads[5]
tcpwm.line_compl[0]:0
scb[2].spi_select2:0
P2.6
ctb_pads[6]
tcpwm.line[1]:0
scb[2].spi_select3:0
ctb_pads[7]
tcpwm.line_compl[1]:0
P2.7
ACT #2
ACT #3
DS #0
DS #1
scb[2].i2c_sda:0
scb[2].spi_miso:0
sar_ext_vref0
sar_ext_vref1
P3.0
sarmux[0]
tcpwm.line[2]:0
scb[0].uart_rx:0
scb[0].i2c_scl:0
scb[0].spi_mosi:0
P3.1
sarmux[1]
tcpwm.line_compl[2]:0
scb[0].uart_tx:0
scb[0].i2c_sda:0
scb[0].spi_miso:0
P3.2
sarmux[2]
lpcomp.in_p[0]
tcpwm.line[3]:0
scb[0].uart_cts:0
scb[0].spi_clk:0
P3.3
sarmux[3]
lpcomp.in_n[0]
tcpwm.line_compl[3]:0
scb[0].uart_rts:0
scb[0].spi_select0:0
P3.4
sarmux[4]
tcpwm.line[6]:0
tcpwm.tr_in[2]
P3.5
sarmux[5]
tcpwm.line_compl[6]:0
tcpwm.tr_in[3]
csd.comp
scb[0].spi_select2:1
P3.6
sarmux[6]
tcpwm.line[7]:0
scb[2].uart_rx:2
tcpwm.tr_in[4]
scb[2].i2c_scl:2
scb[2].spi_mosi:2
P3.7
sarmux[7]
tcpwm.line_compl[7]:0
scb[2].uart_tx:2
scb[2].i2c_sda:2
scb[2].spi_miso:2
scb[0].spi_select1:1
Refer to the Technical Reference Manual (TRM) for CTB connection details. The VDAC outputs are buffered through the CTB outputs; any VDAC output may be routed to
any CTB output.
Document Number: 002-22097 Rev. *E
Page 13 of 45
PSoC 4: PSoC 4100PS Datasheet
Power
The following power system diagram shows the set of power
supply pins as implemented for the PSoC 4100PS. The system
has one regulator in Active mode for the digital circuitry. There is
no analog regulator; the analog circuits run directly from the
VDDA input.
Note that VDDD and VDDA must be shorted together on the
PCB.
Figure 5. Power Supply Connections
VDDA
VDDA
Digital
Domain
Analog
Domain
In this mode, the PSoC 4100PS is powered by an external power
supply that can be anywhere in the range of 1.8 to 5.5 V. This
range is also designed for battery-powered operation. For
example, the chip can be powered from a battery system that
starts at 3.5 V and works down to 1.8 V. In this mode, the internal
regulator of the PSoC 4100PS supplies the internal logic and its
output is connected to the VCCD pin. The VCCD pin must be
bypassed to ground via an external capacitor (0.1 µF; X5R
ceramic or better) and must not be connected to anything else.
In this mode, the PSoC 4100PS is powered by an external power
supply that must be within the range of 1.71 to 1.89 V; note that
this range needs to include the power supply ripple too. In this
mode, the VDDD and VCCD pins are shorted together and
bypassed.
VCCD
1.8 Volt
Reg
Mode 1: 1.8 V to 5.5 V External Supply
Mode 2: 1.8 V ±5% External Supply
VSSA
VDDD
VDDD
There are two distinct modes of operation. In Mode 1, the supply
voltage range is 1.8 V to 5.5 V (unregulated externally; internal
regulator operational). In Mode 2, the supply range is1.8 V ±5%
(externally regulated; 1.71 to 1.89, internal regulator bypassed).
Bypass capacitors must be used from VDDD and VDDA to ground.
The typical practice for systems in this frequency range is to use
a capacitor in the 1-µF range, in parallel with a smaller capacitor
(0.1 µF, for example). Note that these are simply rules of thumb
and that, for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated to
design and obtain optimal bypassing.
VSSD
Figure 6 shows an example of a bypass scheme.
Figure 6. External Supply Range from 1.8 V to 5.5 V with Internal Regulator Active
Power supply bypass connections example
1. 8 V to 5.5 V
1. 8 V to 5.5 V
VDDD
1 µF
VDDA
1 µF
0. 1 µF
0. 1 µF
VCCD
0. 1 µF
PSoC CY8C4Axx
VSS
Document Number: 002-22097 Rev. *E
Page 14 of 45
PSoC 4: PSoC 4100PS Datasheet
Development Support
The PSoC 4100PS family has a rich set of documentation,
development tools, and online resources to assist you during
your development process. Visit www.cypress.com/psoc4 to find
out more.
Documentation
A suite of documentation supports the PSoC 4100PS family to
ensure that you can find answers to your questions quickly. This
section contains a list of some of the key documents.
Software User Guide: A step-by-step guide for using PSoC
Creator. The software user guide shows you how the PSoC
Creator build process works in detail, how to use source control
with PSoC Creator, and much more.
Component Datasheets: The flexibility of PSoC allows the
creation of new peripherals (components) long after the device
has gone into production. Component data sheets provide all of
the information needed to select and use a particular component,
including a functional description, API documentation, example
code, and AC/DC specifications.
Technical Reference Manual: The Technical Reference Manual
(TRM) contains all the technical detail you need to use a PSoC
device, including a complete description of all PSoC registers.
The TRM is available in the Documentation section at
www.cypress.com/psoc4.
Online
In addition to print documentation, the Cypress PSoC forums
connect you with fellow PSoC users and experts in PSoC from
around the world, 24 hours a day, 7 days a week.
Tools
With industry standard cores, programming, and debugging
interfaces, the PSoC 4100PS family is part of a development tool
ecosystem. Visit us at www.cypress.com/psoccreator for the
latest information on the revolutionary, easy to use PSoC Creator
IDE, supported third party compilers, programmers, debuggers,
and development kits.
Application Notes: PSoC application notes discuss a particular
application of PSoC in depth; examples include brushless DC
motor control and on-chip filtering. Application notes often
include example projects in addition to the application note
document.
Document Number: 002-22097 Rev. *E
Page 15 of 45
PSoC 4: PSoC 4100PS Datasheet
Electrical Specifications
Absolute Maximum Ratings
Table 1. Absolute Maximum Ratings[1]
Spec ID#
Parameter
Description
Min
Typ
Max
SID1
VDD_ABS
Digital or Analog supply relative to VSS
–0.5
–
6
SID2
VCCD_ABS
Direct digital core voltage input relative
to VSS
–0.5
–
1.95
SID3
VGPIO_ABS
GPIO voltage
–0.5
–
VDD+0.5
SID4
IGPIO_ABS
Maximum current per GPIO
–25
–
25
SID5
IGPIO_injection
GPIO injection current, Max for VIH >
VDDD, and Min for VIL < VSS
–0.5
–
0.5
BID44
ESD_HBM
Electrostatic discharge human body
model
2200
–
–
Details/
Conditions
Unit
VDDD, VDDA,
Absolute Max
V
–
–
–
mA
Current injected
per pin
–
V
BID45
ESD_CDM
Electrostatic discharge charged device
model
500
–
–
BID46
LU
Pin current for latch-up
–140
–
140
–
mA
–
Device Level Specifications
All specifications are valid for –40 °C TA 105 °C and TJ 125 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
Table 2. DC Specifications
Typical values measured at VDD = 3.3 V and 25 °C.
Spec ID#
Parameter
Description
Min
Typ
Max
SID53
VDD
Power supply input voltage
1.8
–
5.5
SID255
VDD
Power supply input voltage
(VCCD = VDD)
1.71
–
1.89
SID54
VDDIO
VDDIO domain supply
1.71
–
VDD
SID55
CEFC
External regulator voltage bypass
–
0.1
–
With regulator
enabled
V
CEXC
Power supply bypass capacitor
–
1
Internally
unregulated supply
–
µF
SID56
Details/
Conditions
Unit
X5R ceramic or
better
–
X5R ceramic or
better
–
Active Mode, VDD = 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25 °C.
SID10
IDD5
Execute from flash; CPU at 6 MHz
–
2
–
SID16
IDD8
Execute from flash; CPU at 24 MHz
–
5.6
–
SID19
IDD11
Execute from flash; CPU at 48 MHz
–
10.4
–
mA
–
–
Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on)
SID22
SID25
IDD17
I2C wakeup WDT, and Comparators on.
–
1.1
–
IDD20
I2C wakeup, WDT, and Comparators on.
–
3.1
–
mA
6 MHz
12 MHz
Note
1. Usage above the absolute maximum conditions listed in Table 1 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended
periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 002-22097 Rev. *E
Page 16 of 45
PSoC 4: PSoC 4100PS Datasheet
Table 2. DC Specifications (continued)
Typical values measured at VDD = 3.3 V and 25 °C.
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details/
Conditions
Sleep Mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed)
SID28
IDD23
I2C wakeup, WDT, and Comparators on.
–
1.1
–
mA
6 MHz
SID28A
IDD23A
I2C wakeup, WDT, and Comparators on.
–
3.1
–
mA
12 MHz
–
2.5
–
µA
–
–
2.5
–
µA
–
Deep Sleep Mode, VDD = 1.8 V to 3.6 V (Regulator on)
SID31
IDD26
I2C wakeup and WDT on
Deep Sleep Mode, VDD = 3.6 V to 5.5 V (Regulator on)
SID34
IDD29
I2C wakeup and WDT on
Deep Sleep Mode, VDD = 1.71 V to 1.89 V (Regulator bypassed)
SID37
IDD32
I2C wakeup and WDT on
–
2.5
–
µA
–
IDD_XR
Supply current while XRES asserted
–
115
300
µA
–
XRES Current
SID307
Table 3. AC Specifications
Spec ID#
SID48
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
DC
–
48
MHz
1.71 VDD 5.5
FCPU
CPU frequency
SID49
TSLEEP
Wakeup from Sleep mode
–
0
–
SID50[2]
TDEEPSLEEP
Wakeup from Deep Sleep mode
–
35
–
[2]
µs
–
–
Note
2. Guaranteed by characterization.
Document Number: 002-22097 Rev. *E
Page 17 of 45
PSoC 4: PSoC 4100PS Datasheet
GPIO
Table 4. GPIO DC Specifications
Spec ID#
Parameter
[3]
Description
Min
Typ
Max
Unit
Details/Conditions
Input voltage high threshold
0.7 VDDD
–
–
CMOS Input
CMOS Input
SID57
VIH
SID58
VIL
Input voltage low threshold
–
–
SID241
VIH[3]
LVTTL input, VDDD < 2.7 V
0.7 VDDD
0.3
VDDD
–
–
–
SID242
VIL
LVTTL input, VDDD < 2.7 V
–
–
0.3
VDDD
–
SID243
VIH[3]
LVTTL input, VDDD 2.7 V
2.0
–
–
SID244
VIL
LVTTL input, VDDD 2.7 V
–
–
0.8
V
–
–
SID59
VOH
Output voltage high level
VDDD –0.6
–
–
IOH = 4 mA at 3 V VDDD
SID60
VOH
Output voltage high level
VDDD –0.5
–
–
IOH = 1 mA at 1.8 V VDDD
SID61
VOL
Output voltage low level
–
–
0.6
IOL = 4 mA at 1.8 V VDDD
SID62
VOL
Output voltage low level
–
–
0.6
IOL = 10 mA at 3 V VDDD
SID62A
VOL
Output voltage low level
–
–
0.4
IOL = 3 mA at 3 V VDDD
SID63
RPULLUP
Pull-up resistor
3.5
5.6
8.5
–
SID64
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
SID65
IIL
Input leakage current (absolute
value)
–
2
–
nA
SID66
pF
CIN
Input capacitance
–
3
7
[4]
VHYSTTL
Input hysteresis LVTTL
15
40
–
[4]
Input hysteresis CMOS
0.05 × VDDD
–
–
200
–
–
SID67
kΩ
–
–
–
VDDD 2.7 V
SID68
VHYSCMOS
SID68A[4]
VHYSCMOS5V5 Input hysteresis CMOS
SID69[4]
IDIODE
Current through protection diode to
VDD/VSS
–
–
100
µA
SID69A[4]
ITOT_GPIO
Maximum total source or sink chip
current
–
–
85
mA
mV
VDD < 4.5 V
VDD > 4.5 V
–
–
Notes
3. VIH must not exceed VDDD + 0.2 V.
4. Guaranteed by characterization.
Document Number: 002-22097 Rev. *E
Page 18 of 45
PSoC 4: PSoC 4100PS Datasheet
Table 5. GPIO AC Specifications
(Guaranteed by Characterization)
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
3.3 V VDDD,
Cload = 25 pF
SID70
TRISEF
Rise time in fast strong mode
2
–
12
SID71
TFALLF
Fall time in fast strong mode
2
–
12
SID72
TRISES
Rise time in slow strong mode
10
–
60
ns
3.3 V VDDD,
Cload = 25 pF
SID73
TFALLS
Fall time in slow strong mode
10
–
60
ns
3.3 V VDDD,
Cload = 25 pF
SID74
FGPIOUT1
GPIO FOUT; 3.3 V VDDD 5.5 V
Fast strong mode
–
–
16
90/10%, 25-pF load,
60/40 duty cycle
SID75
FGPIOUT2
GPIO FOUT; 1.71 VVDDD3.3 V
Fast strong mode
–
–
16
90/10%, 25-pF load,
60/40 duty cycle
SID76
FGPIOUT3
GPIO FOUT; 3.3 V VDDD 5.5 V
Slow strong mode
–
–
7
SID245
FGPIOUT4
GPIO FOUT; 1.71 V VDDD 3.3 V
Slow strong mode.
–
–
3.5
90/10%, 25-pF load,
60/40 duty cycle
SID246
FGPIOIN
GPIO input operating frequency;
1.71 V VDDD 5.5 V
–
–
48
90/10% VIO
Min
Typ
Max
ns
3.3 V VDDD,
Cload = 25 pF
90/10%, 25-pF load,
60/40 duty cycle
MHz
XRES
Table 6. XRES DC Specifications
Spec ID#
Parameter
Description
SID77
VIH
Input voltage high threshold
0.7 × VDDD
–
–
SID78
VIL
Input voltage low threshold
–
–
0.3 VDDD
SID79
RPULLUP
Pull-up resistor
–
60
SID80
CIN
Input capacitance
–
SID81[5]
VHYSXRES
Input voltage hysteresis
–
Unit
Details/Conditions
V
CMOS Input
–
kΩ
–
3
7
pF
–
0.05
VDD
–
mV
Typical hysteresis is
200 mV for VDD > 4.5 V
Table 7. XRES AC Specifications
Spec ID#
Parameter
SID83[5]
TRESETWIDTH
BID194[5]
TRESETWAKE
Description
Min
Typ
Max
Unit
Reset pulse width
1
–
–
µs
Wake-up time from reset
release
–
–
2.5
ms
Details/Conditions
–
–
Note
5. Guaranteed by characterization.
Document Number: 002-22097 Rev. *E
Page 19 of 45
PSoC 4: PSoC 4100PS Datasheet
Analog Peripherals
Table 8. CTB Opamp Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
power=hi
–
1100
2070
IDD_MED
power=med
–
550
950
IDD_LOW
power=lo
–
150
350
GBW
Load = 20 pF, 0.1 mA
VDDA = 2.7 V
SID272
GBW_HI
power=hi
6
–
–
SID273
GBW_MED
power=med
3
–
–
SID274
GBW_LO
power=lo
–
1
–
Input and output are
0.2 V to VDDA-0.2 V
IOUT_MAX
VDDA = 2.7 V, 500 mV from rail
SID275
IOUT_MAX_HI
power=hi
10
–
–
Output is 0.5 V
VDDA-0.5 V
SID276
IOUT_MAX_MID
power=mid
10
–
–
SID277
IOUT_MAX_LO
power=lo
–
5
–
Output is 0.5 V
VDDA-0.5 V
IOUT
VDDA = 1.71 V, 500 mV from rail
SID278
IOUT_MAX_HI
power=hi
4
–
–
Output is 0.5 V
VDDA-0.5 V
SID279
IOUT_MAX_MID
power=mid
4
–
–
SID280
IOUT_MAX_LO
power=lo
–
2
–
IDD_Int
Opamp block current Internal Load
SID269_I
IDD_HI_Int
power=hi
–
1500
2300
SID270_I
IDD_MED_Int
power=med
–
700
1200
GBW
VDDA = 2.7 V
GBW_HI_Int
power=hi
8
–
–
IDD
Opamp block current, No load
SID269
IDD_HI
SID270
SID271
SID272_I
Unit
Details/Conditions
–
µA
–
–
Input and output are
0.2 V to VDDA-0.2 V
MHz
mA
mA
Input and output are
0.2 V to VDDA-0.2 V
Output is 0.5 V
VDDA-0.5 V
Output is 0.5 V
VDDA-0.5 V
Output is 0.5 V
VDDA-0.5 V
–
µA
MHz
–
Output is 0.25 V to
VDDA-0.25 V
General opamp specs for both internal and external modes
SID281
SID282
VIN
VCM
Charge-pump on,
VDDA = 2.7 V
Charge-pump on, VDDA = 2.7 V
Document Number: 002-22097 Rev. *E
–0.05
–
VDDA-0.2
-0.05
–
VDDA-0.2
–
V
–
Page 20 of 45
PSoC 4: PSoC 4100PS Datasheet
Table 8. CTB Opamp Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
SID283
VOUT_1
power=hi, Iload=10 mA
0.5
–
VDDA
-0.5
VDD = 2.7 V
SID284
VOUT_2
power=hi, Iload=1 mA
0.2
–
VDDA
-0.2
VDDA = 2.7 V
SID285
VOUT_3
power=med, Iload=1 mA
0.2
–
VDDA
-0.2
SID286
VOUT_4
power=lo, Iload=0.1 mA
0.2
–
VDDA
-0.2
SID288
VOS_TR
Offset voltage, trimmed
–1.0
0.5
1.0
SID288A
VOS_TR
Offset voltage, trimmed
–
1
–
SID288B
VOS_TR
Offset voltage, trimmed
–
2
–
SID290
VOS_DR_TR
Offset voltage drift, trimmed
-10
3
10
SID290A
VOS_DR_TR
Offset voltage drift, trimmed
–
10
–
SID290B
VOS_DR_TR
Offset voltage drift, trimmed
–
10
–
SID291
SID291A
CMRR
CMRR2
DC
DC
70
60
80
70
V
VDDA = 2.7 V
High mode, input 0 V
to VDDA-0.2 V
mV
Medium mode, input
0 V to VDDA-0.2 V
Low mode, input 0 V
to VDDA-0.2 V
µV/C
µV/C
High mode
Medium mode
Low mode
Input is 0 V to
VDDA-0.2 V, Output is
0.2 V to VDDA-0.2 V,
VDDA ≥ 2.7 V
–
–
VDDA = 2.7 V
dB
Input is 0 V to
VDDA-0.2 V, Output is
0.2 V to VDDA-0.2 V.
1.71 V VDDA < 2.7 V
SID292
PSRR
At 1 kHz, 10-mV ripple
70
85
–
VDDD = 3.6 V,
high-power mode,
input is 0.2 V to
VDDA-0.2 V
Input and output are
at 0.2 V to VDDA-0.2 V
Noise
SID294
VN2
Input-referred, 1 kHz, power=Hi
–
72
–
SID295
VN3
Input-referred, 10 kHz, power=Hi
–
28
–
SID296
VN4
Input-referred, 100 kHz, power=Hi
–
15
–
SID297
CLOAD
Stable up to max. load. Performance
specs at 50 pF.
–
–
125
pF
SID298
SLEW_RATE
CLOAD = 50 pF, Power = High, VDDA
= 2.7 V
6
–
–
V/µs
SID299
T_OP_WAKE
From disable to enable, no external
RC dominating
–
–
25
µs
Document Number: 002-22097 Rev. *E
nV/
rtHz
Input and output are
at 0.2 V to VDDA-0.2 V
Input and output are
at 0.2 V to VDDA-0.2 V
–
–
–
Page 21 of 45
PSoC 4: PSoC 4100PS Datasheet
Table 8. CTB Opamp Specifications (continued)
Spec ID#
SID299A
Parameter
Description
Min
–
Typ
90
Max
–
Unit
dB
Details/Conditions
–
OL_GAIN
Open Loop Gain
COMP_MODE
Comparator mode; 50-mV drive, Trise=Tfall (approx)
SID300
TPD1
Response time; power=hi
–
150
175
SID301
TPD2
Response time; power=med
–
500
–
SID302
TPD3
Response time; power=lo
–
2500
–
SID303
VHYST_OP
Hysteresis
–
10
–
mV
SID304
WUP_CTB
Wake-up time from Enabled to
Usable
–
–
25
µs
Opamp Deep
Sleep Mode
Mode 2 is lowest current range. Mode 1 has higher GBW.
SID_DS_1
IDD_HI_M1
Mode 1, High current
–
1400
–
SID_DS_2
IDD_MED_M1
Mode 1, Medium current
–
700
–
SID_DS_3
IDD_LOW_M1
Mode 1, Low current
–
200
–
–
SID_DS_4
IDD_HI_M2
Mode 2, High current
–
120
–
–
SID_DS_5
IDD_MED_M2
Mode 2, Medium current
–
60
–
SID_DS_6
IDD_LOW_M2
Mode 2, Low current
–
15
–
–
SID_DS_7
GBW_HI_M1
Mode 1, High current
–
4
–
20-pF load, no DC
load
0.2 V to VDDA-0.2 V
SID_DS_8
GBW_MED_M1
Mode 1, Medium current
–
2
–
20-pF load, no DC
load 0.2 V to
VDDA-0.2 V
SID_DS_9
GBW_LOW_M1
Mode 1, Low current
–
0.5
–
20-pF load, no DC
load 0.2 V to
VDDA-0.2 V
Input is 0.2 V to
VDDA-0.2 V
ns
Input is 0.2 V to
VDDA-0.2 V
Input is 0.2 V to
VDDA-0.2 V
–
–
–
µA
µA
MHz
–
–
SID_DS_10 GBW_HI_M2
Mode 2, High current
–
0.5
–
20-pF load, no DC
load 0.2 V to
VDDA-0.2 V
SID_DS_11 GBW_MED_M2
Mode 2, Medium current
–
0.2
–
20-pF load, no DC
load 0.2 V to
VDDAA-0.2 V
SID_DS_12 GBW_Low_M2
Mode 2, Low current
–
0.1
–
20-pF load, no DC
load 0.2 V to
VDDA-0.2 V
Document Number: 002-22097 Rev. *E
Page 22 of 45
PSoC 4: PSoC 4100PS Datasheet
Table 8. CTB Opamp Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
SID_DS_13 VOS_HI_M1
Mode 1, High current
–
5
–
With trim 25 °C, 0.2 V
to VDDA-1.5 V
SID_DS_14 VOS_MED_M1
Mode 1, Medium current
–
5
–
With trim 25 °C, 0.2 V
to VDDA-1.5 V
SID_DS_15 VOS_LOW_M1
Mode 1, Low current
–
5
–
With trim 25 °C, 0.2 V
to VDDA-1.5 V
SID_DS_16 VOS_HI_M2
Mode 2, High current
–
5
–
With trim 25 °C, 0.2V
to VDDA-1.5 V
SID_DS_17 VOS_MED_M2
Mode 2, Medium current
–
5
–
With trim 25 °C, 0.2 V
to VDDA-1.5 V
SID_DS_18 VOS_LOW_M2
Mode 2, Low current
–
5
–
With trim 25 °C, 0.2 V
to VDDA-1.5 V
SID_DS_19 IOUT_HI_M1
Mode 1, High current
–
10
–
Output is 0.5 V to
VDDA-0.5 V
SID_DS_20 IOUT_MED_M1
Mode 1, Medium current
–
10
–
Output is 0.5 V to
VDDA-0.5 V
SID_DS_21 IOUT_LOW_M1
Mode 1, Low current
–
4
–
SID_DS_22 IOUT_HI_M2
Mode 2, High current
–
1
–
–
SID_DS_23 IOU_MED_M2
Mode 2, Medium current
–
1
–
–
SID_DS_24 IOU_LOW_M2
Mode 2, Low current
–
0.5
–
–
Min
Typ
Max
mV
mA
Output is 0.5 V to
VDDA-0.5 V
Table 9. PGA Specifications
Spec ID#
PGA Gain
Values
Parameter
–
SID_PGA_1 PGA_ERR_1
SID_PGA_2 PGA_ERR_2
SID_PGA_3 PGA_ERR_3
SID_PGA_4 PGA_ERR_4
Description
Unit
Details/Conditions
Gain Values are 2,4,16, and 32.
2
–
32
–
–
Gain Error for Low range; Gain = 2
–
1
–
%
–
Gain Error for Medium range; Gain = 2
–
–
1.5
%
–
Gain Error for High range; Gain = 2
–
–
1.5
%
–
Gain Error for Low range; Gain = 4
–
1
–
%
–
Gain Error for Medium range; Gain = 4
–
–
1.5
%
–
Gain Error for High range; Gain = 4
–
–
1.5
%
–
Gain Error for Low range; Gain = 16
–
3
–
%
–
Gain Error for Medium range;
Gain = 16
–
3
–
%
Gain Error for High range; Gain = 16
–
3
–
%
–
–
Gain Error for Low range; Gain = 32
–
5
–
%
Gain Error for Medium range;
Gain = 32
–
5
–
%
Gain Error for High range; Gain = 32
–
5
–
%
Document Number: 002-22097 Rev. *E
–
–
–
Page 23 of 45
PSoC 4: PSoC 4100PS Datasheet
Table 10. Voltage DAC Specifications
(VDAC specs are valid from –20 to 85 °C)
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
13-bit DAC
SID_DAC_1
INL_VDAC1
Integral non linearity (INL)
–6
–
5
SID_DAC_2
DNL_VDAC1
Differential non linearity (DNL)
–1
–
4
LSB
–
–
Valid output range is 200
LSBs from rails. Full
settling bandwidth to
within 200 mV of rail.
0.2
–
VDDA-0.2
V
Zero scale error (output with all
zeroes input)
–
20
–
mV
GE_VDAC1
Full scale error less offset
–
0.3
2
%
SID_DAC_6
IDD_VDAC1
Block current
–
1.8
–
mA
–
SID_DAC_7
PSRR_VDAC1 Power supply rejection ratio
–
50
–
dB
2.7 V < VDDA 5.5 V
SID_DAC_8
WUP_VDAC1
Wake-up time from Enabled to
Usable
–
–
32
µs
2.7 V < VDDA 5.5 V
SID_DAC_8A WUP_VDAC2
Wake-up time from Enabled to
Usable
–
–
72
µs
VDDA 2.7 V
SID_DAC_9
TS_VDAC1
Settling time for DAC
–
–
2
µs
500 ksps operation,
VDDA ≥ 2.7 V
SID_DAC_9A TS_VDAC2
Settling time for DAC
–
–
10
µs
100 ksps operation,
VDDA 2.7 V
SID_DAC_3
VOUT_VDAC1 Output voltage range
SID_DAC_4
ZSE_VDAC1
SID_DAC_5
Zero scale is at analog
ground
VDDA ≥ 2.7 V,
VREF = VDDA/2
Note
6. Guaranteed by characterization.
Document Number: 002-22097 Rev. *E
Page 24 of 45
PSoC 4: PSoC 4100PS Datasheet
Table 11. Comparator DC Specifications
Min
Typ
Max
SID84
Spec ID#
VOFFSET1
Parameter
Input offset voltage, Factory trim
Description
–
–
±10
SID85
VOFFSET2
Input offset voltage, Custom trim
–
–
±4
SID86
VHYST
Hysteresis when enabled
–
10
35
SID87
VICM1
Input common mode voltage in normal
mode
0
–
VDDD-0.1
SID247
VICM2
Input common mode voltage in low
power mode
0
–
VDDD
SID247A
VICM3
Input common mode voltage in ultra
low power mode
0
–
VDDD-1.15
SID88
CMRR
Common mode rejection ratio
50
–
–
SID88A
CMRR
Common mode rejection ratio
42
–
–
SID89
ICMP1
Block current, normal mode
–
–
400
SID248
ICMP2
Block current, low power mode
–
–
100
SID259
ICMP3
Block current in ultra low-power mode
–
–
28
SID90
ZCMP
DC Input impedance of comparator
35
–
–
Unit Details/Conditions
–
mV
–
–
Modes 1 and 2
V
dB
–
VDDD ≥ 2.2 V for
Temp < 0 °C, VDDD
≥ 1.8 V for Temp >
0 °C
VDDD ≥ 2.7V
VDDD ≤ 2.7V
–
–
µA
VDDD ≥ 2.2 V for
Temp < 0 °C, VDDD
≥ 1.8 V for Temp >
0 °C
MΩ
–
Table 12. Comparator AC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
–
38
110
Unit
Details/Conditions
SID91
TRESP1
Response time, normal mode, 50 mV
overdrive
SID258
TRESP2
Response time, low power mode, 50 mV
overdrive
–
70
200
SID92
TRESP3
Response time, ultra-low power mode,
200 mV overdrive
–
2.3
15
µs
VDDD ≥ 2.2 V for
Temp < 0 °C, VDDD
≥ 1.8 V for Temp >
0 °C
Details/Conditions
All VDD
ns
–
Table 13. Temperature Sensor Specifications
Spec ID#
SID93
Parameter
TSENSACC
Description
Temperature sensor accuracy
Document Number: 002-22097 Rev. *E
Min
Typ
Max
Unit
–5
±1
5
°C
–40 to +85 °C
Page 25 of 45
PSoC 4: PSoC 4100PS Datasheet
Table 14. SAR Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
bits
–
SAR ADC DC Specifications
SID94
A_RES
Resolution
–
–
12
SID95
A_CHNLS_S
Number of channels - single ended
–
–
8
8 full speed.
SID96
A-CHNKS_D
Number of channels - differential
–
–
4
–
SID97
A-MONO
Monotonicity
–
–
–
Yes.
SID98
A_GAINERR
Gain error
–
–
±0.1
%
With external
reference.
SID99
A_OFFSET
Input offset voltage
–
–
2
mV
Measured with 1-V
reference
SID100
A_ISAR
Current consumption
–
–
1
mA
–
SID101
A_VINS
Input voltage range - single ended
VSS
–
VDDA
V
–
SID102
A_VIND
Input voltage range - differential[
VSS
–
VDDA
V
–
SID103
A_INRES
Input resistance
–
–
2.2
KΩ
–
SID104
A_INCAP
Input capacitance
–
–
10
pF
–
SID260
VREFSAR
Trimmed internal reference to SAR
–
–
TBD
V
–
Power supply rejection ratio
70
–
–
dB
–
dB
Measured at 1 V
SAR ADC AC Specifications
SID106
A_PSRR
SID107
A_CMRR
Common mode rejection ratio
66
–
–
SID108
A_SAMP
Sample rate
–
–
1
SID109
A_SNR
Signal-to-noise and distortion ratio
(SINAD)
65
–
–
dB
FIN = 10 kHz
SID110
A_BW
Input bandwidth without aliasing
–
–
A_samp/2
kHz
–
SID111
A_INL
Integral non linearity. VDD = 1.71 to 5.5,
–1.7
1 Msps
–
2
LSB
VREF = 1 to VDD
SID111A
A_INL
Integral non linearity. VDDD = 1.71 to 3.6,
–1.5
1 Msps
–
1.7
LSB
VREF = 1.71 to VDD
SID111B
A_INL
Integral non linearity. VDD = 1.71 to 5.5,
–1.5
500 ksps
–
1.7
LSB
VREF = 1 to VDD
SID112
A_DNL
Differential non linearity. VDD = 1.71 to
5.5, 1 Msps
–1
–
2.2
LSB
VREF = 1 to VDD
SID112A
A_DNL
Differential non linearity. VDD = 1.71 to
3.6, 1 Msps
–1
–
2
LSB
VREF = 1.71 to VDD
SID112B
A_DNL
Differential non linearity. VDD = 1.71 to
5.5, 500 ksps
–1
–
2.2
LSB
VREF = 1 to VDD
SID113
A_THD
Total harmonic distortion
–
–
–65
dB
FSARINTREF
SAR operating speed without external
ref. bypass
–
–
100
ksps
SID261
Document Number: 002-22097 Rev. *E
Msps –
FIN = 10 kHz
12-bit resolution
Page 26 of 45
PSoC 4: PSoC 4100PS Datasheet
Table 15. CapSense and IDAC Specifications[7]
Spec ID#
SYS.PER#3
SYS.PER#16
Parameter
VDD_RIPPLE
VDD_RIPPLE_1.8
Description
Max allowed ripple on power supply,
DC to 10 MHz
Max allowed ripple on power supply,
DC to 10 MHz
Min
–
–
Typ
–
–
Max
Unit
Details/Conditions
mV
VDD > 2 V (with
ripple), 25 °C TA,
Sensitivity = 0.1pF
±25
mV
VDD > 1.75 V (with
ripple), 25 °C TA,
Parasitic Capacitance (CP) < 20 pF,
Sensitivity ≥ 0.4 pF
4000
µA
–
VDDA 0.6
V
VDDA - 0.6 or 4.4,
whichever is lower
VDDA 0.6
V
VDDA - 0.6 or 4.4,
whichever is lower
±50
SID.CSD.BLK ICSD
Maximum block current
SID.CSD#15
Voltage reference for CSD and
Comparator
0.6
SID.CSD#15A VREF_EXT
External Voltage reference for CSD and
Comparator
0.6
SID.CSD#16
IDAC1IDD
IDAC1 (7 bits) block current
–
–
1750
µA
–
SID.CSD#17
IDAC2IDD
IDAC2 (7 bits) block current
–
–
1750
µA
–
SID308
VCSD
Voltage range of operation
1.71
–
5.5
V
1.8 V ±5% or 1.8 V
to 5.5 V
SID308A
VCOMPIDAC
Voltage compliance range of IDAC
0.6
–
VDDA –
0.6
V
VDDA –0.6 or 4.4,
whichever is lower
SID309
IDAC1DNL
DNL
–1
–
1
LSB
–
SID310
IDAC1INL
INL
–3
–
3
LSB
–
SID311
IDAC2DNL
DNL
–1
–
1.0
LSB
–
SID312
IDAC2INL
INL
–3
–
3
LSB
–
–
Capacitance range
of 5 to 200 pF,
Ratio 0.1 pF sensitivity. All
use cases. VDDA >
2 V.
VREF
1.2
SID313
SNR
Ratio of counts of finger to noise.
Guaranteed by characterization
5.0
SID314
IDAC7_SRC1
Maximum Source current of 7-bit IDAC
in low range
4.2
5.4
µA
LSB = 37.5 nA typ.
SID314A
IDAC7_SRC2
Maximum Source current of 7-bit IDAC
in medium range
34
41
µA
LSB = 300 nA typ.
SID314B
IDAC7_SRC3
Maximum Source current of 7-bit IDAC
in high range
275
330
µA
LSB = 2.4 µA typ.
SID314C
IDAC7_SRC4
Maximum Source current of 7-bit IDAC
in low range, 2X mode
8
10.5
µA
LSB = 37.5 nA typ.
2X output stage
SID314D
IDAC7_SRC5
Maximum Source current of 7-bit IDAC
in medium range, 2X mode
69
82
µA
LSB = 300 nA typ.
2X output stage
SID314E
IDAC7_SRC6
Maximum Source current of 7-bit IDAC
in high range, 2X mode
540
660
µA
LSB = 2.4 µA typ.2X
output stage
SID315
IDAC7_SINK_1
Maximum Sink current of 7-bit IDAC in
low range
4.2
5.7
µA
LSB = 37.5 nA typ.
SID315A
IDAC7_SINK_2
Maximum Sink current of 7-bit IDAC in
medium range
34
44
µA
LSB = 300 nA typ.
SID315B
IDAC7_SINK_3
Maximum Sink current of 7-bit IDAC in
high range
260
340
µA
LSB = 2.4 µA typ.
–
Note
7. For optimal CapSense performance, Ports 0, 4, and 5 must be used for large DC loads.
Document Number: 002-22097 Rev. *E
Page 27 of 45
PSoC 4: PSoC 4100PS Datasheet
Table 15. CapSense and IDAC Specifications[7] (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
11.5
µA
LSB = 37.5 nA typ.
2X output stage
SID315C
IDAC7_SINK_4
Maximum Sink current of 7-bit IDAC in
low range, 2X mode
SID315D
IDAC7_SINK_5
Maximum Sink current of 7-bit IDAC in
medium range, 2X mode
68
86
µA
LSB = 300 nA typ.
2X output stage
SID315E
IDAC7_SINK_6
Maximum Sink current of 7-bit IDAC in
high range, 2X mode
540
700
µA
LSB = 2.4 µA typ.2X
output stage
SID315F
IDAC8_SRC_1
Maximum Source current of 8-bit IDAC
in low range
8.4
10.8
µA
LSB = 37.5 nA typ.
SID315G
IDAC8_SRC_2
Maximum Source current of 8-bit IDAC
in medium range
68
82
µA
LSB = 300 nA typ.
SID315H
IDAC8_SRC_3
Maximum Source current of 8-bit IDAC
in high range
550
680
µA
LSB = 2.4 µA typ.
SID315J
IDAC8_SINK_1
Maximum Sink current of 8-bit IDAC in
low range
8.4
11.4
µA
LSB = 37.5 nA typ.
SID315K
IDAC8_SINK_2
Maximum Sink current of 8-bit IDAC in
medium range
68
88
µA
LSB = 300 nA typ.
SID315L
IDAC8_SINK_3
Maximum Sink current of 8-bit IDAC in
high range
540
670
µA
LSB = 2.4 µA typ.
SID320
IDACOFFSET1
All zeroes input; Medium and High
range
–
–
1
LSB
Polarity set by
Source or Sink
SID320A
IDACOFFSET2
All zeroes input; Low range
–
–
2
LSB
Polarity set by
Source or Sink
SID321
IDACGAIN
Full-scale error less offset
–
–
±20
%
SID322
IDACMISMATCH1
Mismatch between IDAC1 and IDAC2
in Low mode
–
–
9.2
LSB
LSB = 37.5 nA typ.
SID322A
IDACMISMATCH2
Mismatch between IDAC1 and IDAC2
in Medium mode
–
–
6
LSB
LSB = 300 nA typ.
SID322B
IDACMISMATCH3
Mismatch between IDAC1 and IDAC2
in High mode
–
–
6.8
LSB
LSB = 2.4 µA typ.
SID323
IDACSET8
Settling time to 0.5 LSB for 8-bit IDAC
–
–
10
µs
Full-scale transition.
No external load.
SID324
IDACSET7
Settling time to 0.5 LSB for 7-bit IDAC
–
–
10
µs
Full-scale transition.
No external load.
SID325
CMOD
External modulator capacitor.
–
2.2
–
nF
5-V rating, X7R or
NP0 cap.
Document Number: 002-22097 Rev. *E
8
Page 28 of 45
PSoC 4: PSoC 4100PS Datasheet
Table 16. 10-bit CapSense ADC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
–
10
bits
Details/Conditions
SIDA94
A_RES
Resolution
–
SID95
A_CHNLS_S
Number of channels - single-ended
–
–
16
SIDA97
A-MONO
Monotonicity
–
–
–
Yes
SIDA98
A_GAINERR
Gain error
–
–
TBD
%
SIDA99
A_OFFSET
Input offset voltage
–
–
TBD
mV
Measured with 1-V reference
SIDA100
A_ISAR
Current consumption
–
–
TBD
mA
–
SIDA101
A_VINS
Input voltage range - single-ended
VSSA
–
VDDA
V
–
SIDA103
A_INRES
Input resistance
–
2.2
–
KΩ
–
Input capacitance
–
20
–
TBD
–
–
pF
–
dB
–
SIDA104
A_INCAP
8 full speed.
Diff inputs use neighboring I/O
Yes
With external reference.
SIDA106
A_PSRR
Power supply rejection ratio
SIDA107
A_TACQ
Sample acquisition time
–
1
–
µs
–
SIDA108
A_CONV8
Conversion time for 8-bit resolution at
conversion rate = Fhclk/(2^(N+2)).
Clock frequency = 48 MHz.
–
–
21.3
µs
Does not include acquisition
time. Equivalent to 44.8 ksps
including acquisition time.
SIDA108A
A_CONV10
Conversion time for 10-bit resolution
at conversion rate = Fhclk/(2^(N+2)).
Clock frequency = 48 MHz.
–
–
85.3
µs
Does not include acquisition
time. Equivalent to 11.6 ksps
including acquisition time.
SIDA109
A_SND
Signal-to-noise and distortion ratio
(SINAD)
TBD
–
–
dB
SIDA110
A_BW
Input bandwidth without aliasing
–
–
22.4
kHz
8-bit resolution
SIDA111
A_INL
Integral non linearity. VDD = 1.71 to
5.5, 1 ksps
–
–
2
LSB
VREF = 2.4 V or greater
SIDA112
A_DNL
Differential non linearity. VDD = 1.71
to 5.5, 1 ksps
–
–
1
LSB
Document Number: 002-22097 Rev. *E
–
–
Page 29 of 45
PSoC 4: PSoC 4100PS Datasheet
Digital Peripherals
Timer Counter Pulse-Width Modulator (TCPWM)
Table 17. TCPWM Specifications
Spec ID#
SID.TCPWM.1
Parameter
ITCPWM1
Description
Block current consumption at 3 MHz
Min
–
Typ
–
Max
45
Unit
SID.TCPWM.2
ITCPWM2
Block current consumption at 12 MHz
–
–
155
μA
All modes (TCPWM)
SID.TCPWM.2A ITCPWM3
Block current consumption at 48 MHz
–
–
650
All modes (TCPWM)
MHz
Fc max = CLK_SYS
Maximum = 48 MHz
SID.TCPWM.3
TCPWMFREQ
Operating frequency
SID.TCPWM.4
TPWMENEXT
Input trigger pulse width
SID.TCPWM.5
TPWMEXT
Details/Conditions
All modes (TCPWM)
–
–
Fc
2/Fc
–
–
For all trigger events[8]
Minimum possible
width of Overflow,
Underflow, and CC
(Counter equals
Compare value)
outputs
Output trigger pulse widths
2/Fc
–
–
SID.TCPWM.5A TCRES
Resolution of counter
1/Fc
–
–
SID.TCPWM.5B PWMRES
PWM resolution
1/Fc
–
–
Minimum pulse width
of PWM Output
SID.TCPWM.5C QRES
Quadrature inputs resolution
1/Fc
–
–
Minimum pulse width
between Quadrature
phase inputs
ns
Minimum time
between successive
counts
I2C
Table 18. Fixed I2C DC Specifications[9]
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
SID149
II2C1
Block current consumption at 100 kHz
–
–
50
–
SID150
II2C2
Block current consumption at 400 kHz
–
–
135
SID151
II2C3
Block current consumption at 1 Mbps
–
–
310
–
SID152
II2C4
I2C enabled in Deep Sleep mode
–
–
1.4
–
µA
–
Table 19. Fixed I2C AC Specifications[9]
Spec ID#
SID153
Parameter
FI2C1
Description
Bit rate
Min
Typ
Max
–
–
1
Min
Typ
Max
Unit
Details/Conditions
Msps –
Table 20. SPI DC Specifications[10]
Spec ID#
Parameter
Description
SID163
ISPI1
Block current consumption at
1 Mbits/sec
–
–
360
SID164
ISPI2
Block current consumption at
4 Mbits/sec
–
–
560
SID165
ISPI3
Block current consumption at
8 Mbits/sec
–
–
600
Unit
Details/Conditions
–
µA
–
–
Note
8. Trigger events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected.
9. Guaranteed by characterization.
Document Number: 002-22097 Rev. *E
Page 30 of 45
PSoC 4: PSoC 4100PS Datasheet
Table 21. SPI AC Specifications[10]
Spec ID#
SID166
Parameter
FSPI
Description
Min
Typ
Max
SPI Operating frequency (Master; 6X
Oversampling)
Unit
Details/Conditions
–
–
8
MHz SID166
–
Fixed SPI Master Mode AC Specifications
SID167
TDMO
MOSI Valid after SClock driving edge
–
–
15
SID168
TDSI
MISO Valid before SClock capturing
edge
20
–
–
SID169
THMO
Previous MOSI data hold time
0
–
–
ns
Full clock, late MISO
sampling
Referred to Slave capturing
edge
Fixed SPI Slave Mode AC Specifications
–
SID170
TDMI
MOSI Valid before Sclock Capturing
edge
40
–
–
SID171
TDSO
MISO Valid after Sclock driving edge
–
–
42 +
3*Tscb
SID171A
TDSO_EXT
MISO Valid after Sclock driving edge
in Ext. Clk mode
–
–
48
SID172
THSO
Previous MISO data hold time
0
–
–
Min
Typ
Max
Unit
ns
Tscb = SCB clock
–
–
Table 22. UART DC Specifications[10]
Spec ID#
Parameter
Description
SID160
IUART1
Block current consumption at
100 Kbits/sec
–
–
55
µA
SID161
IUART2
Block current consumption at
1000 Kbits/sec
–
–
312
µA
Min
Typ
Max
–
–
1
Details/Conditions
–
–
Table 23. UART AC Specifications[10]
Spec ID#
SID162
Parameter
FUART
Description
Bit rate
Unit
Details/Conditions
Mbps –
Table 24. LCD Direct Drive DC Specifications[10]
Spec ID#
Parameter
Description
Min
–
SID154
ILCDLOW
Operating current in low power
mode
SID155
CLCDCAP
LCD capacitance per
segment/common driver
–
SID156
LCDOFFSET
Long-term segment offset
–
ILCDOP1
LCD system operating current
Vbias = 5 V
–
LCD system operating current
Vbias = 3.3 V
–
SID157
SID158
ILCDOP2
Typ
Max
Unit
Details/Conditions
5
–
µA
16 4 small segment disp. at Hz
500
5000
pF
20
–
mV
2
–
–
–
32 4 segments. 50 Hz. 25 °C
mA
2
–
32 4 segments. 50 Hz. 25 °C
4 segments. 50 Hz. 25 °C.
Note
10. Guaranteed by characterization.
Document Number: 002-22097 Rev. *E
Page 31 of 45
PSoC 4: PSoC 4100PS Datasheet
Table 25. LCD Direct Drive AC Specifications[10]
Spec ID#
SID159
Parameter
FLCD
Description
LCD frame rate
Min
Typ
Max
Unit
10
50
150
Hz
Min
Typ
Max
Unit
1.71
–
5.5
V
Unit
Details/Conditions
–
Memory
Table 26. Flash DC Specifications
Spec ID#
SID173
Parameter
VPE
Description
Erase and program voltage
Details/Conditions
–
Table 27. Flash AC Specifications
Spec ID#
Description
Min
Typ
Max
SID174
TROWWRITE[11]
Row (block) write time (erase and
program)
–
–
20
SID175
TROWERASE[11]
Row erase time
–
–
13
SID176
Row program time after erase
–
–
7
–
Bulk erase time (16 KB)
–
–
15
–
SID180
TROWPROGRAM[11]
TBULKERASE[11]
TDEVPROG[11]
Seconds –
SID181[12]
FEND
Flash endurance
SID182[12]
FRET
SID178
[12]
Parameter
Total device program time
Details/Conditions
Row (block) = 64 bytes
ms
–
–
–
7.5
100 K
–
–
Flash retention. TA 55 °C, 100 K
P/E cycles
20
–
–
SID182A[12] –
Flash retention. TA 85 °C, 10 K
P/E cycles
10
–
–
SID182B[12] FRETQ
Flash retention. TA 105 °C, 10 K
P/E cycles; three years at TA
85 °C
10
–
–
Guaranteed by
characterization
SID256
TWS48
Number of Wait states at 48 MHz
2
–
–
CPU execution from
Flash
SID257
TWS24
Number of Wait states at 24 MHz
1
–
–
CPU execution from
Flash
Cycles
–
–
Years
–
Notes
11. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
12. Guaranteed by characterization.
Document Number: 002-22097 Rev. *E
Page 32 of 45
PSoC 4: PSoC 4100PS Datasheet
System Resources
Power-on Reset (POR)
Table 28. Power On Reset (PRES)
Spec ID#
Parameter
Description
SID.CLK#6 SR_POWER_UP Power supply slew rate
Min
Typ
Max
Unit
1
–
67
V/ms
SID185[13]
VRISEIPOR
Rising trip voltage
0.80
–
1.5
[13]
VFALLIPOR
Falling trip voltage
0.70
–
1.4
SID186
V
Details/Conditions
At power-up and
power-down.
–
–
Table 29. Brown-out Detect (BOD) for VCCD
Spec ID
Parameter
Description
Min
Typ
Max
1.48
–
1.62
1.1
–
1.5
Min
Typ
Max
SID190[13]
VFALLPPOR
BOD trip voltage in active and sleep
modes
SID192[13]
VFALLDPSLP
BOD trip voltage in Deep Sleep
Unit
V
Details/Conditions
–
–
SWD Interface
Table 30. SWD Interface Specifications
Spec ID#
Parameter
Description
Unit
Details/Conditions
SWDCLK ≤ 1/3 CPU
clock frequency
SID213
F_SWDCLK1
3.3 V VDD 5.5 V
–
–
14
SID214
F_SWDCLK2
1.71 V VDD 3.3 V
–
–
7
SID215[13]
T_SWDI_SETUP T = 1/f SWDCLK
0.25*T
–
–
–
SID216[13]
T_SWDI_HOLD
0.25*T
–
–
–
SID217[13]
T_SWDO_VALID T = 1/f SWDCLK
–
–
0.5*T
T_SWDO_HOLD T = 1/f SWDCLK
1
–
–
Min
Typ
Max
Unit
MHz
[13]
SID217A
T = 1/f SWDCLK
ns
SWDCLK ≤ 1/3 CPU
clock frequency
–
–
Internal Main Oscillator
Table 31. IMO DC Specifications
(Guaranteed by Design)
Spec ID#
Parameter
Description
Details/Conditions
SID218
IIMO1
IMO operating current at 48 MHz
–
–
250
µA
–
SID219
IIMO2
IMO operating current at 24 MHz
–
–
180
µA
–
Min
Typ
Max
Unit
Details/Conditions
Table 32. IMO AC Specifications
Spec ID
Parameter
Description
SID223
FIMOTOL1
Frequency range from 24 to
48 MHz (4-MHz increments)
–2
–
+2
%
2 V VDD 5.5 V, and
–25 °C TA 85 °C
SID226
TSTARTIMO
IMO startup time
–
–
7
µs
–
SID228
TJITRMSIMO2
RMS jitter at 24 MHz
–
145
–
ps
–
Note
13. Guaranteed by characterization.
Document Number: 002-22097 Rev. *E
Page 33 of 45
PSoC 4: PSoC 4100PS Datasheet
Internal Low-Speed Oscillator
Table 33. ILO DC Specifications
(Guaranteed by Design)
Spec ID
[14]
SID231
Parameter
Description
IILO1
Min
Typ
Max
Unit
–
0.3
1.05
µA
ILO operating current
Details/Conditions
–
Table 34. ILO AC Specifications
Min
Typ
Max
Unit
SID234[14] TSTARTILO1
Spec ID
Parameter
ILO startup time
Description
–
–
2
ms
–
SID236[14] TILODUTY
ILO duty cycle
40
50
60
%
–
SID237
ILO frequency range
20
40
80
kHz
–
FILOTRIM1
Details/Conditions
Table 35. Watch Crystal Oscillator (WCO) Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
SID398
FWCO
Crystal Frequency
–
32.768
–
kHz
–
SID399
FTOL
Frequency tolerance
–
50
250
ppm
With 20-ppm crystal
SID400
ESR
Equivalent series resistance
–
50
–
kΩ
–
SID401
PD
Drive Level
–
–
1
µW
–
SID402
TSTART
Startup time
–
–
500
ms
–
SID403
CL
Crystal Load Capacitance
6
–
12.5
pF
–
SID404
C0
Crystal Shunt Capacitance
–
1.35
–
pF
–
SID405
IWCO1
Operating Current (high power mode)
–
–
8
µA
–
Min
Typ
Max
Unit
Table 36. External Clock Specifications
Spec ID
SID305[14]
Parameter
Description
Details/Conditions
ExtClkFreq
External clock input frequency
0
–
48
MHz
–
SID306[14] ExtClkDuty
Duty cycle; measured at VDD/2
45
–
55
%
–
Min
Typ
Max
Unit
3
–
4
Table 37. Block Specs
Spec ID
[14]
SID262
Parameter
TCLKSWITCH
Description
System clock source switching time
Details/Conditions
Periods –
Table 38. PRGIO Pass-through Time (Delay in Bypass Mode)
Spec ID
SID252
Parameter
Description
Min
Typ
Max
Unit
PRG_BYPASS
Max. delay added by PRGIO in bypass
mode
–
–
1.6
ns
Details/Conditions
–
Note
14. Guaranteed by characterization.
Document Number: 002-22097 Rev. *E
Page 34 of 45
PSoC 4: PSoC 4100PS Datasheet
Max CPU Speed (MHz)
DMA
Flash (KB)
SRAM (KB)
13-bit VDAC
Opamp (CTB)
CapSense
10-bit CSD ADC
Direct LCD Drive
RTC
12-bit SAR ADC
LP Comparators
TCPWM Blocks
SCB Blocks
Smart IOs
GPIO
28-SSOP
45-WLCSP
48-TQFP
48-QFN
Package
CY8C4125PVI-PS421
24
✔
32
4
2
4
–
✔
✔
✔
806
ksps
2
8
2
8
20
✔
–
–
–
CY8C4125FNI-PS423
24
✔
32
4
2
4
–
✔
✔
✔
806
ksps
2
8
2
8
37
–
✔
–
–
CY8C4125AZI-PS423
24
✔
32
4
2
4
–
✔
✔
✔
806
ksps
2
8
2
8
38
–
–
✔
–
2
8
2
8
38
–
–
–
✔
MPN
Category
Features
4125
CY8C4125LQI-PS423
24
✔
32
4
2
4
–
✔
✔
✔
806
ksps
CY8C4145PVI-PS421
48
✔
32
4
2
4
–
✔
✔
✔
1000
ksps
2
8
2
8
20
✔
–
–
–
CY8C4145FNI-PS423
48
✔
32
4
2
4
–
✔
✔
✔
1000
ksps
2
8
2
8
37
–
✔
–
–
CY8C4145FNQ-PS423
48
✔
32
4
2
4
–
✔
✔
✔
1000
ksps
2
8
2
8
37
–
✔
–
–
CY8C4145AZI-PS423
48
✔
32
4
2
4
–
✔
✔
✔
1000
ksps
2
8
2
8
38
–
–
✔
–
CY8C4145LQI-PS423
48
✔
32
4
2
4
–
✔
✔
✔
1000
ksps
2
8
2
8
38
–
–
–
✔
2
8
3
8
20
✔
–
–
–
4145
CY8C4145PVI-PS431
48
✔
32
4
2
4
✔
✔
✔
✔
1000
ksps
CY8C4145FNI-PS433
48
✔
32
4
2
4
✔
✔
✔
✔
1000
ksps
2
8
3
8
37
–
✔
–
–
CY8C4145FNQ-PS433
48
✔
32
4
2
4
✔
✔
✔
✔
1000
ksps
2
8
3
8
37
–
✔
–
–
CY8C4145AZI-PS433
48
✔
32
4
2
4
✔
✔
✔
✔
1000
ksps
2
8
3
8
38
–
–
✔
–
✔
1000
ksps
2
8
3
8
38
–
–
–
✔
CY8C4145LQI-PS433
48
✔
Document Number: 002-22097 Rev. *E
32
4
2
4
✔
✔
✔
Temperature Range (°C)
Ordering Information
–40 to
85
–40 to
105
–40 to
85
–40 to
105
–40 to
85
Page 35 of 45
PSoC 4: PSoC 4100PS Datasheet
The nomenclature used in the preceding table is based on the following part numbering convention:
Field
Description
Values
Meaning
CY8C
Cypress Prefix
4
Architecture
4
Arm Cortex-M0+ CPU
A
Family
1
4100PS Family
2
24 MHz
B
Maximum frequency
C
Flash Memory Capacity
DE
S
Package Code
Series Designator
F
Temperature Range
XYZ
Attributes Code
4
48 MHz
5
32 KB
AZ
TQFP (0.5mm pitch)
LQ
QFN
PV
SSOP
FN
CSP
PS
S-Series
I
Industrial
Q
Extended Industrial
000-999
Code of feature set in the specific family
The following is an example of a part number:
CY 8 C 4 A B C DE F – S XYZ
Example
Cypress Prefix
Architecture
4 : PSoC 4
1 : 4100 Family
Family within Architecture
CPU Speed
4 : 48 MHz
5 : 32 KB
Flash Capacity
AZ : TQFP
Package Code
I : Industrial
Temperature Range
Series Designator
Attributes Code
Document Number: 002-22097 Rev. *E
Page 36 of 45
PSoC 4: PSoC 4100PS Datasheet
Packaging
Spec ID#
Package
Description
Package DWG #
BID20
48-pin TQFP
7 × 7 × 1.4 mm height with 0.5-mm pitch
51-85135
BID27
48-pin QFN
6 × 6 × 0.6 mm height with 0.4-mm pitch
001-57280
BID34
45-ball WLCSP
1.986 × 3.691 × 0.482-mm height with 0.38-mm pitch
002-24003
BID34A
28-pin SSOP
5.3 × 10.2 × 0.65-mm pitch
51-85079
Table 39. Package Thermal Characteristics
Parameter
Description
Package
Min
Typ
Max
Unit
TA
Operating Ambient temperature
–
–40
25
105
°C
TJ
Operating junction temperature
–
–40
–
125
°C
TJA
Package θJA
48-pin TQFP
–
71
–
°C/Watt
TJC
Package θJC
48-pin TQFP
–
34.3
–
°C/Watt
TJA
Package θJA
48-pin QFN
–
18
–
°C/Watt
TJC
Package θJC
48-pin QFN
–
4.5
–
°C/Watt
TJA
Package θJA
45-Ball WLCSP
–
37.2
–
°C/Watt
TJC
Package θJC
45-Ball WLCSP
–
0.31
–
°C/Watt
TJA
Package θJA
28-pin SSOP
–
60
–
°C/Watt
TJC
Package θJC
28-pin SSOP
–
25
–
°C/Watt
Table 40. Solder Reflow Peak Temperature
Package
Maximum Peak
Temperature
Maximum Time at Peak Temperature
All
260 °C
30 seconds
Table 41. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-020
Package
MSL
All
MSL 3
Document Number: 002-22097 Rev. *E
Page 37 of 45
PSoC 4: PSoC 4100PS Datasheet
Package Diagrams
Figure 7. 48-pin TQFP Package Outline
51-85135 *C
Figure 8. 48-Pin QFN Package Outline
001-57280 *E
Document Number: 002-22097 Rev. *E
Page 38 of 45
PSoC 4: PSoC 4100PS Datasheet
Figure 9. 45-Ball WLCSP Dimensions
6
7
5
4
3
2
1
A
B
C
D
E
F
G
H
J
5
NOTES:
DIMENSIONS
SYMBOL
1. ALL DIMENSIONS ARE IN MILLIMETERS.
MIN
NOM
MAX
A
-
-
0.482
A1
0.141
-
-
D
1.986 BSC
E
3.691 BSC
D1
1.52 BSC
E1
3.04 BSC
E2
0.263 BSC
E3
0.388 BSC
MD
5
ME
9
N
45
Øb
0.19
eD
eE
0.22
0.38 BSC
0.38 BSC
SD
0.00 BSC
SE
0.063 BSC
2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
5. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
6. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" = 0.
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
0.25
7. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK,
METALIZED MARK, INDENTATION OR OTHER MEANS.
8. "+" INDICATES THE THEORETICAL CENTER OF DEPOPULATED SOLDER
BALLS.
9. JEDEC SPECIFICATION NO. REF. : N/A.
002-24003 **
CYPRESS
Company Confidential
Document Number: 002-22097 Rev. *E
Page 39 of 45
PSoC 4: PSoC 4100PS Datasheet
Figure 10. 28-Pin SSOP Package Outline
51-85079 *G
Document Number: 002-22097 Rev. *E
Page 40 of 45
PSoC 4: PSoC 4100PS Datasheet
Acronyms
Table 42. Acronyms used in this Document
Acronym
Description
abus
analog local bus
ADC
analog-to-digital converter
AG
analog global
AHB
AMBA (advanced microcontroller bus
architecture) high-performance bus, an Arm data
transfer bus
Table 42. Acronyms used in this Document (continued)
Acronym
Description
ESD
electrostatic discharge
ETM
embedded trace macrocell
FIR
finite impulse response, see also IIR
FPB
flash patch and breakpoint
FS
full-speed
GPIO
general-purpose input/output, applies to a PSoC
pin
ALU
arithmetic logic unit
AMUXBUS
analog multiplexer bus
HVI
high-voltage interrupt, see also LVI, LVD
API
application programming interface
IC
integrated circuit
APSR
application program status register
IDAC
current DAC, see also DAC, VDAC
Arm®
advanced RISC machine, a CPU architecture
IDE
integrated development environment
ATM
automatic thump mode
I
BW
bandwidth
CAN
Controller Area Network, a communications
protocol
2C,
or IIC
IIR
Inter-Integrated Circuit, a communications
protocol
infinite impulse response, see also FIR
ILO
internal low-speed oscillator, see also IMO
internal main oscillator, see also ILO
CMRR
common-mode rejection ratio
IMO
CPU
central processing unit
INL
integral nonlinearity, see also DNL
CRC
cyclic redundancy check, an error-checking
protocol
I/O
input/output, see also GPIO, DIO, SIO, USBIO
IPOR
initial power-on reset
DAC
digital-to-analog converter, see also IDAC,
VDAC
IPSR
interrupt program status register
DFB
digital filter block
IRQ
interrupt request
DIO
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
ITM
instrumentation trace macrocell
DMIPS
Dhrystone million instructions per second
DMA
direct memory access, see also TD
DNL
differential nonlinearity, see also INL
DNU
do not use
DR
port write data registers
DSI
digital system interconnect
DWT
data watchpoint and trace
ECC
error correcting code
ECO
external crystal oscillator
EEPROM
electrically erasable programmable read-only
memory
LCD
liquid crystal display
LIN
Local Interconnect Network, a communications
protocol.
LR
link register
LUT
lookup table
LVD
low-voltage detect, see also LVI
LVI
low-voltage interrupt, see also HVI
LVTTL
low-voltage transistor-transistor logic
MAC
multiply-accumulate
MCU
microcontroller unit
MISO
master-in slave-out
NC
no connect
nonmaskable interrupt
EMI
electromagnetic interference
NMI
EMIF
external memory interface
NRZ
non-return-to-zero
EOC
end of conversion
NVIC
nested vectored interrupt controller
EOF
end of frame
NVL
nonvolatile latch, see also WOL
execution program status register
opamp
operational amplifier
EPSR
Document Number: 002-22097 Rev. *E
Page 41 of 45
PSoC 4: PSoC 4100PS Datasheet
Table 42. Acronyms used in this Document (continued)
Acronym
Description
Table 42. Acronyms used in this Document (continued)
Acronym
Description
PAL
programmable array logic, see also PLD
SWD
serial wire debug, a test protocol
PC
program counter
SWV
single-wire viewer
PCB
printed circuit board
TD
transaction descriptor, see also DMA
PGA
programmable gain amplifier
THD
total harmonic distortion
PHUB
peripheral hub
TIA
transimpedance amplifier
PHY
physical layer
TRM
technical reference manual
PICU
port interrupt control unit
TTL
transistor-transistor logic
PLA
programmable logic array
TX
transmit
PLD
programmable logic device, see also PAL
UART
PLL
phase-locked loop
Universal Asynchronous Transmitter Receiver, a
communications protocol
PMDD
package material declaration data sheet
POR
power-on reset
PRES
precise power-on reset
PRS
pseudo random sequence
PS
port read data register
PSoC®
Programmable System-on-Chip™
PSRR
power supply rejection ratio
PWM
pulse-width modulator
RAM
random-access memory
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
RTL
register transfer language
RTR
remote transmission request
RX
receive
SAR
successive approximation register
SC/CT
switched capacitor/continuous time
SCL
I2C serial clock
SDA
I2C serial data
S/H
sample and hold
SINAD
signal to noise and distortion ratio
SIO
special input/output, GPIO with advanced
features. See GPIO.
SOC
start of conversion
SOF
start of frame
SPI
Serial Peripheral Interface, a communications
protocol
SR
slew rate
SRAM
static random access memory
SRES
software reset
Document Number: 002-22097 Rev. *E
UDB
universal digital block
USB
Universal Serial Bus
USBIO
USB input/output, PSoC pins used to connect to
a USB port
VDAC
voltage DAC, see also DAC, IDAC
WDT
watchdog timer
WOL
write once latch, see also NVL
WRES
watchdog timer reset
XRES
external reset I/O pin
XTAL
crystal
Page 42 of 45
PSoC 4: PSoC 4100PS Datasheet
Document Conventions
Units of Measure
Table 43. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
dB
decibel
fF
femto farad
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohour
kHz
kilohertz
k
kilo ohm
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
M
mega-ohm
Msps
megasamples per second
µA
microampere
µF
microfarad
µH
microhenry
µs
microsecond
µV
microvolt
µW
microwatt
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
nV
nanovolt
ohm
pF
picofarad
ppm
parts per million
ps
picosecond
s
second
sps
samples per second
sqrtHz
square root of hertz
V
volt
Document Number: 002-22097 Rev. *E
Page 43 of 45
PSoC 4: PSoC 4100PS Datasheet
Revision History
Description Title: PSoC 4: PSoC 4100PS Datasheet Programmable System-on-Chip (PSoC)
Document Number: 002-22097
Submission
Revision
ECN
Description of Change
Date
**
6049408
01/30/2018 New spec
Updated number of VDACs to 2.
*A
6155846
04/27/2018
Updated Voltage DAC Specifications.
*B
6164274
05/03/2018 Corrected typo in Ordering Information.
Updated Table 2, Table 6, Table 8, Table 10, Table 27, and Table 36.
*C
6318827
09/25/2018
Updated 45-ball WLCSP package drawing.
Updated Device Level Specifications and Ordering Information.
*D
6740728
12/06/2019 Updated Table 27 and Table 39.
Updated Sales page and Copyright information.
Updated Conditions for SR_POWER_UP in Table 28.
*E
7047124
12/17/2020 Updated Figure 10 (spec 51-85079 *F to *G) in Packaging.
Updated Sales, Solutions, and Legal Information.
Document Number: 002-22097 Rev. *E
Page 44 of 45
PSoC 4: PSoC 4100PS Datasheet
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2018-2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries ("Cypress"). This document, including any software or
firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce
the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or
indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by
Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, "Security
Breach"). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
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responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. "High-Risk Device"
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. "Critical Component" means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-22097 Rev. *E
Revised December 17, 2020
Page 45 of 45
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