CY8C41xx
PSoC™ 4 MCU: PS oC™ 4100S
Based on Arm® Cortex®-M0+ CPU
General description
PSoC™ 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system
controllers with an Arm® Cortex®-M0+ CPU. It combines programmable and reconfigurable analog and digital
blocks with flexible automatic routing. The PSoC™ 4100S product family is a member of the PSoC™ 4 platform
architecture. It is a combination of a microcontroller with standard communication and timing peripherals, a
capacitive touch-sensing system (CAPSENSE™) with best-in-class performance, programmable general-purpose
continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC™ 4100S products
are upward compatible with members of the PSoC™ 4 platform for new applications and design needs.
Features
• 32-bit MCU subsystem
- 48-MHz Arm® Cortex®-M0+ CPU with single-cycle multiply
- Up to 64 KB of flash with read accelerator
- Up to 8 KB of SRAM
• Programmable analog
- Two opamps with reconfigurable high-drive external and high-bandwidth internal drive and Comparator
modes and ADC input buffering capability. Opamps can operate in deep sleep low-power mode.
- 12-bit 1-Msps SAR ADC with differential and single-ended modes, and channel sequencer with signal averaging
- Single-slope 10-bit ADC function provided by a capacitance sensing block
- Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
- Two low-power comparators that operate in Deep Sleep low-power mode
• Programmable digital
- Programmable logic blocks allowing boolean operations to be performed on port inputs and outputs
• Low-power 1.71-V to 5.5-V operation
- Deep Sleep mode with operational analog and 2.5-µA digital system current
• Capacitive sensing
- Capacitive sigma-delta provides best-in-class signal-to-noise ratio (SNR) (>5:1) and water tolerance
- Infineon-supplied software component makes capacitive sensing design easy
- Automatic hardware tuning (SmartSense)
• LCD drive capability
- LCD segment drive capability on GPIOs
• Serial communication
- Three independent run-time reconfigurable Serial Communication Blocks (SCBs) with re-configurable I2C,
SPI, or UART functionality
• Timing and pulse-width modulation
- Five 16-bit Timer/Counter/Pulse-width Modulator (TCPWM) blocks
- Center-aligned, edge, and pseudo-random modes
- Comparator-based triggering of kill signals for motor drive and other high-reliability digital logic applications
- Quadrature decoder
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Features
• Up to 36 programmable GPIO pins
- 48-pin TQFP, 44-pin TQFP, 40-pin QFN, 32-pin QFN, and 35-ball WLCSP packages
- Any GPIO pin can be CAPSENSE™, analog, or digital
- Drive modes, strengths, and slew rates are programmable
• Clock sources
- 32-kHz watch crystal oscillator (WCO)
- ±2% internal main oscillator (IMO)
- 32-kHz internal low-power oscillator (ILO)
• ModusToolbox™ software
- Comprehensive collection of multi-platform tools and software libraries
- Includes board support packages (BSPs), peripheral driver library (PDL), and middleware such as CAPSENSE™
• PSoC™ Creator design environment
- Integrated development environment (IDE) provides schematic design entry and build, with analog and digital
automatic routing
- Application programming interface (API) components for all fixed-function and programmable peripherals
• Industry-standard tool compatibility
- After schematic entry, development can be done with Arm®-based industry-standard development tools
Datasheet
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Table of contents
Table of contents
General description ...........................................................................................................................1
Features ...........................................................................................................................................1
Table of contents ...............................................................................................................................3
1 Development ecosystem .................................................................................................................4
1.1 PSoC™ 4 MCU resources .........................................................................................................................................4
1.2 ModusToolbox™ software ......................................................................................................................................5
1.3 PSoC™ Creator ........................................................................................................................................................6
Block diagram...................................................................................................................................7
2 Functional definition.......................................................................................................................9
2.1 CPU and memory subsystem .................................................................................................................................9
2.2 System resources....................................................................................................................................................9
2.3 Analog blocks ........................................................................................................................................................11
2.4 Programmable digital blocks ...............................................................................................................................12
2.5 Fixed function digital ............................................................................................................................................12
2.6 GPIO.......................................................................................................................................................................13
2.7 Special function peripherals ................................................................................................................................14
3 Pinouts ........................................................................................................................................15
3.1 Alternate pin functions .........................................................................................................................................17
4 Power ..........................................................................................................................................19
4.1 Mode 1: 1.8 V to 5.5 V external supply ..................................................................................................................19
4.2 Mode 2: 1.8 V ± 5% external supply ......................................................................................................................20
5 Electrical specifications.................................................................................................................21
5.1 Absolute maximum ratings ..................................................................................................................................21
5.2 Device level specifications....................................................................................................................................22
5.3 Analog peripherals................................................................................................................................................27
5.4 Digital peripherals.................................................................................................................................................37
5.5 Memory..................................................................................................................................................................41
5.6 System resources..................................................................................................................................................42
6 Ordering information ....................................................................................................................46
7 Packaging ....................................................................................................................................49
7.1 Package diagrams.................................................................................................................................................50
8 Acronyms .....................................................................................................................................54
9 Document conventions..................................................................................................................58
9.1 Units of measure ...................................................................................................................................................58
Revision history ..............................................................................................................................59
Datasheet
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Development ecosystem
1
Development ecosystem
1.1
PSoC™ 4 MCU resources
Infineon provides a wealth of data at www.cypress.com to help you select the right PSoC™ device and quickly
and effectively integrate it into your design. The following is an abbreviated, hyperlinked list of resources for
PSoC™ 4 MCU:
• Overview: PSoC™ Portfolio, PSoC™ Roadmap
• Product selectors: PSoC™ 4 MCU
• Application notes cover a broad range of topics, from basic to advanced level, and include the following:
- AN79953: Getting Started With PSoC™ 4. This application note has a convenient flow chart to help decide
which IDE to use: ModusToolbox™ software or PSoC™ Creator.
- AN91184: PSoC™ 4 BLE - Designing BLE applications
- AN88619: PSoC™ 4 hardware design considerations
- AN73854: Introduction to bootloaders
- AN89610: Arm® Cortex® code optimization
- AN86233: PSoC™ 4 MCU power reduction techniques
- AN57821: Mixed signal circuit board layout
- AN85951: PSoC™ 4, PSoC™ 6 CAPSENSE™ design guide
• Code examples demonstrate product features and usage, and are also available on Infineon GitHub
repositories.
• Technical Reference Manuals (TRMs) provide detailed descriptions of PSoC™ 4 MCU architecture and registers.
• PSoC 4 MCU programming specification provides the information necessary to program PSoC™ 4 MCU
non-volatile memory.
• Development tools
- ModusToolbox™ software enables cross platform code development with a robust suite of tools and software
libraries.
- PSoC™ Creator is a free Windows-based IDE. It enables concurrent hardware and firmware design of PSoC™
3, PSoC™ 4, PSoC™ 5LP, and PSoC™ 6 MCU based systems. Applications are created using schematic capture
and over 150 pre-verified, production-ready peripheral components.
- CY8CKIT-041-41XX PSoC™ 4100S CAPSENSE™ pioneer kit, is an easy-to-use and inexpensive development
platform. This kit includes connectors for Arduino™ compatible shields.
- MiniProg4 and MiniProg3 all-in-one development programmers and debuggers.
- PSoC™ 4 MCU CAD libraries provide footprint and schematic support for common tools. IBIS models are also
available.
• Training Videos are available on a wide range of topics including the PSoC™ 4 MCU 101 series.
• Infineon developer community enables connection with fellow PSoC™ developers around the world, 24 hours
a day, 7 days a week, and hosts a dedicated PSoC™ 4 MCU community.
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Based on Arm® Cortex®-M0+ CPU
Development ecosystem
1.2
ModusToolbox™ software
ModusToolbox™ software is Infineon’ comprehensive collection of multi-platform tools and software libraries
that enable an immersive development experience for creating converged MCU and wireless systems. It is:
• Comprehensive - it has the resources you need
• Flexible - you can use the resources in your own workflow
• Atomic - you can get just the resources you want
Infineon provides a large collection of code repositories on GitHub, including:
• Board support packages (BSPs) aligned with Infineon kits
• Low-level resources, including a peripheral driver library (PDL)
• Middleware enabling industry-leading features such as CAPSENSE™
• An extensive set of thoroughly tested code example applications
ModusToolbox™ software is IDE-neutral and easily adaptable to your workflow and preferred development
environment. It includes a project creator, peripheral and library configurators, a library manager, as well as the
optional Eclipse IDE for ModusToolbox™, as Figure 1 shows. For information on using Infineon tools, refer to the
documentation delivered with ModusToolbox™ software, and AN79953: Getting Started with PSoC™ 4.
Figure 1
Datasheet
ModusToolbox™ software tools
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Development ecosystem
1.3
PSoC™ Creator
PSoC™ Creator is a free Windows-based IDE. It enables you to design hardware and firmware systems
concurrently, based on PSoC™ 4 MCU. As Figure 2 shows, with PSoC™ Creator you can:
1. Explore the library of 200+ components
2. Drag and drop component icons to complete your hardware system design in the main design workspace
3. Configure components using the component configuration tools and the component datasheets
4. Co-design your application firmware and hardware in the PSoC™ Creator IDE or build a project for a third-party
IDE
5. Prototype your solution with the PSoC™ 4 pioneer kits. If a design change is needed, PSoC™ Creator and
components enable you to make changes on-the-fly without the need for hardware revisions.
Figure 2
Datasheet
PSoC™ Creator schematic entry and components
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Block diagram
Block diagram
SWD/TC
SPCIF
Cortex® M0+
48 MHz
FLASH
64 KB
SRAM
16 KB
ROM
8 KB
FAST MUL
NVIC, IRQMUX
Read Accelerator
SRAM Controller
ROM Controller
AHB-Lite
System Resources
Lite
x1
SARMUX
TRNG
SAR ADC
( 12-bit)
WCO
Programmable
Analog
2x LP Comparator
Test
TestMode Entry
Digital DFT
Analog DFT
Peripheral Interconnect (MMIO)
PCLK
2x S C B-I2 C/S PI/UA R T
Reset
Reset Control
XRES
Peripherals
IO S S G PIO (5x ports)
Clock
Clock Control
WDT
ILO
IMO
System Interconnect (Single Layer AHB)
CO(wPLL)
Power
Sleep Control
WIC
POR
REF
PWRSYS
CAPSENSE ™ (v2)
32-bit
CPU Subsystem
5x T C P W M
PSoC™ 4100S
Architecture
CTBm
2 x Opamp
High Speed I/O Matrix, 2X Smart I/O Ports
Power Modes
Active/Sleep
DeepSleep
36x GPIOs, LCD
I/O Subsystem
PSoC™ 4100S devices include extensive support for programming, testing, debugging, and tracing both hardware
and firmware.
The Arm® serial-wire debug (SWD) interface supports all programming and debug features of the device.
Complete debug-on-chip functionality enables full-device debugging in the final system using the standard
production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the
standard programming connections are required to fully support debug.
The PSoC™ Creator IDE provides fully integrated programming and debug support for the PSoC™ 4100S devices.
The SWD interface is fully compatible with industry-standard third-party tools. The PSoC™ 4100S provides a level
of security not possible with multi-chip application solutions or with microcontrollers.
It has the following advantages:
• Allows disabling of debug features
• Robust flash protection
• Allows customer-proprietary functionality to be implemented in on-chip programmable blocks
Datasheet
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Block diagram
The debug circuits are enabled by default and can be disabled in firmware. If they are not enabled, the only way
to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new
firmware that enables debugging. Thus firmware control of debugging cannot be over-ridden without erasing the
firmware thus providing security.
Additionally, all device interfaces can be permanently disabled (device security) for applications concerned
about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and
interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when
maximum device security is enabled. Therefore, PSoC™ 4100S, with device security enabled, may not be returned
for failure analysis. This is a trade-off the PSoC™ 4100S allows the customer to make.
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Functional definition
2
Functional definition
2.1
CPU and memory subsystem
2.1.1
CPU
The Cortex®-M0+ CPU in the PSoC™ 4100S is part of the 32-bit MCU subsystem, which is optimized for low-power
operation with extensive clock gating. Most instructions are 16 bits in length and the CPU executes a subset of
the thumb-2 instruction set. It includes a nested vectored interrupt controller (NVIC) block with eight interrupt
inputs and also includes a wakeup interrupt controller (WIC). The WIC can wake the processor from Deep Sleep
mode, allowing power to be switched off to the main processor when the chip is in Deep Sleep mode.
The CPU also includes a debug interface, the serial wire debug (SWD) interface, which is a two-wire form of JTAG.
The debug configuration used for PSoC™ 4100S has four breakpoint (address) comparators and two watchpoint
(data) comparators.
2.1.2
Flash
The PSoC™ 4100S device has a flash module with a flash accelerator, tightly coupled to the CPU to improve
average access times from the flash block. The low-power flash block is designed to deliver two wait-state (WS)
access time at 48 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average.
2.1.3
SRAM
Eight KB of SRAM are provided with zero wait-state access at 48 MHz.
2.1.4
SROM
An 8 KB supervisory ROM that contains boot and configuration routines is provided.
2.2
System resources
2.2.1
Power system
The power system is described in detail in the section “Power” on page 19. It provides assurance that voltage
levels are as required for each respective mode and either delays mode entry (for example, on power-on reset
(POR)) until voltage levels are as required for proper functionality, or generates resets (for example, on brown-out
detection). The PSoC™ 4100S operates with a single external supply over the range of either 1.8 V ± 5% (externally
regulated) or 1.8 to 5.5 V (internally regulated) and has three different power modes, transitions between which
are managed by the power system. The PSoC™ 4100S provides Active, Sleep, and Deep Sleep low-power modes.
All subsystems are operational in Active mode. The CPU subsystem (CPU, flash, and SRAM) is clock-gated off in
Sleep mode, while all peripherals and interrupts are active with instantaneous wake-up on a wake-up event. In
Deep Sleep mode, the high-speed clock and associated circuitry is switched off; wake-up from this mode takes
35 µs. The opamps can remain operational in Deep Sleep mode.
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Based on Arm® Cortex®-M0+ CPU
Functional definition
2.2.2
Clock system
The PSoC™ 4100S clock system is responsible for providing clocks to all subsystems that require clocks and for
switching between different clock sources without glitching. In addition, the clock system ensures that there are
no metastable conditions.
The clock system for the PSoC™ 4100S consists of the internal main oscillator (IMO), internal low-frequency
oscillator (ILO), a 32 kHz watch crystal oscillator (WCO) and provision for an external clock. Clock dividers are
provided to generate clocks for peripherals on a fine-grained basis. Fractional dividers are also provided to
enable clocking of higher data rates for UARTs.
External Clock
HFCLK
IMO
WCO
Divide By
2,4,8
WDC0
16-bits
LFCLK
WDC1
16-bits
ILO
WDC2
32-bits
WDT
Watchdog Counters (WDC)
Watchdog Timer (WDT)
Prescaler
SYSCLK
HFCLK
Integer
Dividers
Fractional
Dividers
Figure 3
6X 16-bit
3X 16.5-bit
PSoC™ 4100S MCU clocking architecture
The HFCLK signal can be divided down to generate synchronous clocks for the analog and digital peripherals.
There are eight clock dividers for the PSoC™ 4100S; two of those are fractional dividers. The 16-bit capability
allows flexible generation of fine-grained frequency values and is fully supported in PSoC™ Creator.
2.2.3
IMO clock source
The IMO is the primary source of internal clocking in the PSoC™ 4100S. It is trimmed during testing to achieve the
specified accuracy.The IMO default frequency is 24 MHz and it can be adjusted from 24 to 48 MHz in steps of
4 MHz. The IMO tolerance with Infineon provided calibration settings is ±2%.
2.2.4
ILO clock source
The ILO is a very low power, nominally 40-kHz oscillator, which is primarily used to generate clocks for the
watchdog timer (WDT) and peripheral operation in Deep Sleep mode. ILO-driven counters can be calibrated to
the IMO to improve accuracy. Infineon provides a software component, which does the calibration.
2.2.5
Watch Crystal Oscillator (WCO)
The PSoC™ 4100S clock subsystem also implements a low-frequency (32-kHz watch crystal) oscillator that can
be used for precision timing applications. The WCO block allows locking the IMO to the 32-kHz oscillator.
2.2.6
Watchdog timer and counters
A watchdog timer is implemented in the clock block running from the ILO; this allows watchdog operation during
Deep Sleep and generates a watchdog reset if not serviced before the set timeout occurs. The watchdog reset is
recorded in a Reset Cause Register, which is firmware readable. The watchdog counters can be used to
implement a real-time clock using the 32-kHz WCO.
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Functional definition
2.2.7
Reset
The PSoC™ 4100S can be reset from a variety of sources including a software reset. Reset events are asynchronous
and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky through reset
and allows software to determine the cause of the reset. An XRES pin is reserved for external reset by asserting it
active low. The XRES pin has an internal pull-up resistor that is always enabled.
2.3
Analog blocks
2.3.1
12-bit SAR ADC
The 12-bit, 1-Msps SAR ADC can operate at a maximum clock rate of 18 MHz and requires a minimum of 18 clocks
at that frequency to do a 12-bit conversion.
The sample-and-hold (S/H) aperture is programmable allowing the gain bandwidth requirements of the amplifier
driving the SAR inputs, which determine its settling time, to be relaxed if required. It is possible to provide an
external bypass (through a fixed pin location) for the internal reference amplifier.
The SAR is connected to a fixed set of pins through an 8-input sequencer. The sequencer cycles through selected
channels autonomously (sequencer scan) with zero switching overhead (that is, aggregate sampling bandwidth
is equal to 1 Msps whether it is for a single channel or distributed over several channels). The sequencer switching
is effected through a state machine or through firmware driven switching. A feature provided by the sequencer
is buffering of each channel to reduce CPU interrupt service requirements. To accommodate signals with varying
source impedance and frequency, it is possible to have different sample times programmable for each channel.
Also, signal range specification through a pair of range registers (low and high range values) is implemented with
a corresponding out-of-range interrupt if the digitized value exceeds the programmed range; this allows fast
detection of out-of-range values without the necessity of having to wait for a sequencer scan to be completed
and the CPU to read the values and check for out-of-range values in software.
The SAR is not available in Deep Sleep mode as it requires a high-speed clock (up to 18 MHz). The SAR operating
range is 1.71 V to 5.5 V.
AHB System Bus and Programmable Logic
Interconnect
SAR Sequencer
vminus vplus
S A R MU X
S A R MU X Port
(Up to 16 inputs)
Sequencing
and Control
Data and
Status Flags
POS
SARADC
NEG
Reference
Selection
VDDA /2
VDDA
External
Reference and
Bypass
(optional)
VREF
Inputs from other Ports
Figure 4
Datasheet
SAR ADC
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Based on Arm® Cortex®-M0+ CPU
Functional definition
2.3.2
Two opamps (continuous-time block; CTB)
The PSoC™ 4100S has two opamps with Comparator modes which allow most common analog functions to be
performed on-chip eliminating external components; PGAs, Voltage Buffers, Filters, Trans-Impedance Amplifiers,
and other functions can be realized, in some cases with external passives. saving power, cost, and space. The
on-chip opamps are designed with enough bandwidth to drive the Sample-and-Hold circuit of the ADC without
requiring external buffering.
2.3.3
Low-power comparators (LPC)
The PSoC™ 4100S has a pair of low-power comparators, which can also operate in Deep Sleep modes. This allows
the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during
low-power modes. The comparator outputs are normally synchronized to avoid metastability unless operating
in an asynchronous power mode where the system wake-up circuit is activated by a comparator switch event.
The LPC outputs can be routed to pins.
2.3.4
Current DACs
The PSoC™ 4100S has two IDACs, which can drive any of the pins on the chip. These IDACs have programmable
current ranges.
2.3.5
Analog multiplexed buses
The PSoC™ 4100S has two concentric independent buses that go around the periphery of the chip. These buses
(called amux buses) are connected to firmware-programmable analog switches that allow the chip’s internal
resources (IDACs, comparator) to connect to any pin on the I/O ports.
2.4
Programmable digital blocks
The smart I/O block is a fabric of switches and LUTs that allows boolean functions to be performed in signals
being routed to the pins of a GPIO port. The Smart I/O can perform logical operations on input pins to the chip
and on signals going out as outputs.
2.5
Fixed function digital
2.5.1
Timer/Counter/PWM (TCPWM) block
The TCPWM block consists of a 16-bit counter with user-programmable period length. There is a capture register
to record the count value at the time of an event (which may be an I/O event), a period register that is used to
either stop or auto-reload the counter when its count is equal to the period register, and compare registers to
generate compare value signals that are used as PWM duty cycle outputs. The block also provides true and
complementary outputs with programmable offset between them to allow use as dead-band programmable
complementary PWM outputs. It also has a kill input to force outputs to a predetermined state; for example, this
is used in motor drive systems when an over-current state is indicated and the PWM driving the FETs needs to be
shut off immediately with no time for software intervention. There are five TCPWM blocks in the PSoC™ 4100S.
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Based on Arm® Cortex®-M0+ CPU
Functional definition
2.5.2
Serial Communication Block (SCB)
The PSoC™ 4100S has three serial communication blocks, which can be programmed to have SPI, I2C, or UART
functionality.
I2C Mode: The hardware I2C block implements a full multi-master and slave interface (it is capable of
multi-master arbitration). This block is capable of operating at speeds of up to 400 kbps (Fast Mode) and has
flexible buffering options to reduce interrupt overhead and latency for the CPU. It also supports EZI2C that
creates a mailbox address range in the memory of the PSoC™ 4100S and effectively reduces I2C communication
to reading from and writing to an array in memory. In addition, the block supports an 8-deep FIFO for receive and
transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock
stretching caused by the CPU not having read data on time.
The I2C peripheral is compatible with the I2C Standard-mode and Fast-mode devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain
modes.
The PSoC™ 4100S is not completely compliant with the I2C spec in the following respect:
• GPIO cells are not over-voltage tolerant and, therefore, cannot be hot-swapped or powered up independently
of the rest of the I2C system.
UART Mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface
(LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic
UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals
connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame
error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated.
SPI Mode: The SPI mode supports full Motorola SPI, TI SSP (adds a start pulse used to synchronize SPI Codecs),
and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO.
2.6
GPIO
The PSoC™ 4100S has up to 36 GPIOs. The GPIO block implements the following:
• Eight drive modes:
- Analog input mode (input and output buffers disabled)
- Input only
- Weak pull-up with strong pull-down
- Strong pull-up with weak pull-down
- Open drain with strong pull-down
- Open drain with strong pull-up
- Strong pull-up with strong pull-down
- Weak pull-up with weak pull-down
• Input threshold select (CMOS or LVTTL).
• Individual control of input and output buffer enabling/disabling in addition to the drive strength modes
• Selectable slew rates for dV/dt related noise control to improve EMI
The pins are organized in logical entities called ports, which are 8-bit in width (less for ports 2 and 3). During
power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess
turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various
signals that may connect to an I/O pin.
Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the
pins themselves.
Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt
service routine (ISR) vector associated with it (5 for PSoC™ 4100S).
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Functional definition
2.7
Special function peripherals
2.7.1
CAPSENSE™
CAPSENSE™ is supported in the PSoC™ 4100S through a CAPSENSE™ Sigma-Delta (CSD) block that can be
connected to any pins through an analog multiplex bus via analog switches. CAPSENSE™ function can thus be
provided on any available pin or group of pins in a system under software control. A PSoC™ Creator component
is provided for the CAPSENSE™ block to make it easy for the user.
Shield voltage can be driven on another analog multiplex bus to provide water-tolerance capability. Water
tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield
capacitance from attenuating the sensed input. Proximity sensing can also be implemented.
The CAPSENSE™ block has two IDACs, which can be used for general purposes if CAPSENSE™ is not being used
(both IDACs are available in that case) or if CAPSENSE™ is used without water tolerance (one IDAC is available).
The CAPSENSE™ block also provides a 10-bit slope ADC function which can be used in conjunction with the
CAPSENSE™ function.
The CAPSENSE™ block is an advanced, low-noise, programmable block with programmable voltage references
and current source ranges for improved sensitivity and flexibility. It can also use an external reference voltage. It
has a full-wave CSD mode that alternates sensing to VDDA and ground to null out power-supply related noise.
2.7.2
LCD segment drive
The PSoC™ 4100S has an LCD controller, which can drive up to 4 commons and up to 32 segments. It uses full
digital methods to drive the LCD segments requiring no generation of internal LCD voltages. The two methods
used are referred to as digital correlation and PWM. Digital correlation pertains to modulating the frequency and
drive levels of the common and segment signals to generate the highest RMS voltage across a segment to light it
up or to keep the RMS signal to zero. This method is good for STN displays but may result in reduced contrast
with TN (cheaper) displays. PWM pertains to driving the panel with PWM signals to effectively use the capacitance
of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This
method results in higher power consumption but can result in better results when driving TN displays. LCD
operation is supported during Deep Sleep refreshing a small display buffer (4 bits; 1 32-bit register per port).
Datasheet
14
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Pinouts
3
Pinouts
Table 1 provides the pin list for PSoC™ 4100S for the 48-pin TQFP, 44-pin TQFP, 40-pin QFN, 32-pin QFN, and
35-ball CSP packages. All port pins support GPIO.
Table 1
Pin list
48-pin TQFP
44-pin TQFP
40-pin QFN
32-pin QFN
35-ball CSP
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
28
P0.0
24
P0.0
22
P0.0
17
P0.0
C3
P0.0
29
P0.1
25
P0.1
23
P0.1
18
P0.1
A5
P0.1
30
P0.2
26
P0.2
24
P0.2
19
P0.2
A4
P0.2
31
P0.3
27
P0.3
25
P0.3
20
P0.3
A3
P0.3
32
P0.4
28
P0.4
26
P0.4
21
P0.4
B3
P0.4
33
P0.5
29
P0.5
27
P0.5
22
P0.5
A6
P0.5
34
P0.6
30
P0.6
28
P0.6
23
P0.6
B4
P0.6
35
P0.7
31
P0.7
29
P0.7
B5
P0.7
36
XRES
32
XRES
30
XRES
24
XRES
B6
XRES
37
VCCD
33
VCCD
31
VCCD
25
VCCD
A7
VCCD
38
VSSD
DN
VSSD
26
VSSD
B7
VSS
39
VDDD
34
VDDD
32
VDDD
C7
VDD
40
VDDA
35
VDDA
33
VDDA
27
VDD
C7
VDD
41
VSSA
36
VSSA
34
VSSA
28
VSSA
B7
VSS
42
P1.0
37
P1.0
35
P1.0
29
P1.0
C4
P1.0
43
P1.1
38
P1.1
36
P1.1
30
P1.1
C5
P1.1
44
P1.2
39
P1.2
37
P1.2
31
P1.2
C6
P1.2
45
P1.3
40
P1.3
38
P1.3
32
P1.3
D7
P1.3
46
P1.4
41
P1.4
39
P1.4
D4
P1.4
47
P1.5
42
P1.5
D5
P1.5
48
P1.6
43
P1.6
D6
P1.6
1
P1.7/VREF
44
P1.7/VREF
E7
P1.7/VREF
1
VSSD
40
P1.7/VREF
1
P1.7/VREF
2
P2.0
2
P2.0
1
P2.0
2
P2.0
3
P2.1
3
P2.1
2
P2.1
3
P2.1
4
P2.2
4
P2.2
3
P2.2
4
P2.2
D3
P2.2
5
P2.3
5
P2.3
4
P2.3
5
P2.3
E4
P2.3
6
P2.4
6
P2.4
5
P2.4
E5
P2.4
7
P2.5
7
P2.5
6
P2.5
6
P2.5
E6
P2.5
8
P2.6
8
P2.6
7
P2.6
7
P2.6
E3
P2.6
9
P2.7
9
P2.7
8
P2.7
8
P2.7
E2
P2.7
10
VSSD
10
VSSD
9
VSSD
12
P3.0
11
P3.0
10
P3.0
9
P3.0
E1
P3.0
13
P3.1
12
P3.1
11
P3.1
10
P3.1
D2
P3.1
Datasheet
15
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Pinouts
Table 1
Pin list (continued)
48-pin TQFP
44-pin TQFP
40-pin QFN
32-pin QFN
35-ball CSP
Pin
Name
Pin
Name
Pin
Name
Pin
Name
Pin
Name
14
P3.2
13
P3.2
12
P3.2
11
P3.2
D1
P3.2
16
P3.3
14
P3.3
13
P3.3
12
P3.3
C1
P3.3
17
P3.4
15
P3.4
14
P3.4
C2
P3.4
18
P3.5
16
P3.5
15
P3.5
19
P3.6
17
P3.6
16
P3.6
20
P3.7
18
P3.7
17
P3.7
21
VDDD
19
VDDD
22
P4.0
20
P4.0
18
P4.0
13
P4.0
B1
P4.0
23
P4.1
21
P4.1
19
P4.1
14
P4.1
B2
P4.1
24
P4.2
22
P4.2
20
P4.2
15
P4.2
A2
P4.2
25
P4.3
23
P4.3
21
P4.3
16
P4.3
A1
P4.3
Note Pins 11, 15, 26, and 27 are No Connects (NC) on the 48-pin TQFP.
Descriptions of the power pins are as follows:
VDDD: Power supply for the digital section.
VDDA: Power supply for the analog section.
VSSD, VSSA: Ground pins for the digital and analog sections respectively.
VCCD: Regulated digital supply (1.8 V ± 5%)
VDD: Power supply to all sections of the chip
VSS: Ground for all sections of the chip
Datasheet
16
002-00122 Rev. *O
2022-07-28
Table 2
Alternate pin functions
Smart I/O
Alternate function 1
Deep Sleep 1
Deep Sleep 2
tcpwm.tr_in[0]
scb[2].i2c_scl:0
scb[0].spi_select1:0
tcpwm.tr_in[1]
scb[2].i2c_sda:0
scb[0].spi_select2:0
Port/Pin
Analog
Alternate function 2 Alternate function 3
P0.0
lpcomp.in_p[0]
P0.1
lpcomp.in_n[0]
P0.2
lpcomp.in_p[1]
scb[0].spi_select3:0
P0.3
lpcomp.in_n[1]
scb[2].spi_select0
P0.4
wco.wco_in
scb[1].uart_rx:0
scb[2].uart_rx:0
scb[1].i2c_scl:0
scb[1].spi_mosi:1
P0.5
wco.wco_out
scb[1].uart_tx:0
scb[2].uart_tx:0
scb[1].i2c_sda:0
scb[1].spi_miso:1
scb[2].uart_tx:1
P0.6
srss.ext_clk
scb[1].uart_cts:0
P0.7
tcpwm.line[0]:2
scb[1].uart_rts:0
scb[1].spi_clk:1
scb[1].spi_select0:1
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P1.0
ctb0_oa0+
tcpwm.line[2]:1
scb[0].uart_rx:1
scb[0].i2c_scl:0
scb[0].spi_mosi:1
P1.1
ctb0_oa0–
tcpwm.line_compl[2]:1
scb[0].uart_tx:1
scb[0].i2c_sda:0
scb[0].spi_miso:1
P1.2
ctb0_oa0_out
tcpwm.line[3]:1
scb[0].uart_cts:1
tcpwm.tr_in[2]
scb[2].i2c_scl:1
scb[0].spi_clk:1
P1.3
ctb0_oa1_out
tcpwm.line_compl[3]:1
scb[0].uart_rts:1
tcpwm.tr_in[3]
scb[2].i2c_sda:1
scb[0].spi_select0:1
P1.4
ctb0_oa1–
scb[0].spi_select1:1
P1.5
ctb0_oa1+
scb[0].spi_select2:1
P1.6
ctb0_oa0+
scb[0].spi_select3:1
P1.7
ctb0_oa1+
sar_ext_vref0
sar_ext_vref1
scb[2].spi_clk
P2.0
sarmux[0]
SmartIo[0].io[0]
tcpwm.line[4]:0
P2.1
sarmux[1]
SmartIo[0].io[1]
tcpwm.line_compl[4]:0
P2.2
sarmux[2]
SmartIo[0].io[2]
scb[1].spi_clk:2
P2.3
sarmux[3]
SmartIo[0].io[3]
scb[1].spi_select0:2
P2.4
sarmux[4]
SmartIo[0].io[4]
tcpwm.line[0]:1
scb[1].spi_select1:1
P2.5
sarmux[5]
SmartIo[0].io[5]
tcpwm.line_compl[0]:1
scb[1].spi_select2:1
P2.6
sarmux[6]
SmartIo[0].io[6]
tcpwm.line[1]:1
scb[1].spi_select3:1
csd.comp
tcpwm.tr_in[4]
scb[1].i2c_scl:1
scb[1].spi_mosi:2
tcpwm.tr_in[5]
scb[1].i2c_sda:1
scb[1].spi_miso:2
PSoC™ 4 MCU: PSoC™ 4100S
Each port pin has can be assigned to one of multiple functions; it can, for instance, be an analog I/O, a digital peripheral function, an LCD pin, or a
CAPSENSE™ pin. The pin assignments are shown in Table 2.
Based on Arm® Cortex®-M0+ CPU
Alternate pin functions
Pinouts
Datasheet
3.1
Deep Sleep 2
lpcomp.comp[0]:1
scb[2].spi_mosi
scb[1].uart_rx:1
scb[1].i2c_scl:2
scb[1].spi_mosi:0
tcpwm.line_compl[0]:0
scb[1].uart_tx:1
scb[1].i2c_sda:2
scb[1].spi_miso:0
SmartIo[1].io[2]
tcpwm.line[1]:0
scb[1].uart_cts:1
cpuss.swd_data
scb[1].spi_clk:0
P3.3
SmartIo[1].io[3]
tcpwm.line_compl[1]:0
scb[1].uart_rts:1
cpuss.swd_clk
scb[1].spi_select0:0
P3.4
SmartIo[1].io[4]
tcpwm.line[2]:0
P3.5
SmartIo[1].io[5]
tcpwm.line_compl[2]:0
scb[1].spi_select2:0
P3.6
SmartIo[1].io[6]
tcpwm.line[3]:0
scb[1].spi_select3:0
P3.7
SmartIo[1].io[7]
tcpwm.line_compl[3]:0
Analog
Smart I/O
Alternate function 1
P2.7
sarmux[7]
SmartIo[0].io[7]
tcpwm.line_compl[1]:1
P3.0
SmartIo[1].io[0]
tcpwm.line[0]:0
P3.1
SmartIo[1].io[1]
P3.2
Alternate function 2 Alternate function 3
scb[1].spi_select1:0
tcpwm.tr_in[6]
lpcomp.comp[1]:1
scb[2].spi_miso
18
P4.0
csd.vref_ext
scb[0].uart_rx:0
scb[0].i2c_scl:1
scb[0].spi_mosi:0
P4.1
csd.cshieldpads
scb[0].uart_tx:0
scb[0].i2c_sda:1
scb[0].spi_miso:0
P4.2
csd.cmodpad
scb[0].uart_cts:0
lpcomp.comp[0]:0
scb[0].spi_clk:0
P4.3
csd.csh_tank
scb[0].uart_rts:0
lpcomp.comp[1]:0
scb[0].spi_select0:0
PSoC™ 4 MCU: PSoC™ 4100S
Deep Sleep 1
Port/Pin
Based on Arm® Cortex®-M0+ CPU
Alternate pin functions (continued)
Pinouts
Datasheet
Table 2
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Power
4
Power
The following power system diagram shows the set of power supply pins as implemented for the PSoC™ 4100S.
The system has one regulator in Active mode for the digital circuitry. There is no analog regulator; the analog
circuits run directly from the VDD input.
VDDA
VDDD
VDDA
VSSA
VDDD
Analog
Domain
Digital
Domain
VSSD
1.8 Volt
Regulator
Figure 5
VCCD
Power supply connections
There are two distinct modes of operation. In Mode 1, the supply voltage range is 1.8 V to 5.5 V (unregulated
externally; internal regulator operational). In Mode 2, the supply range is 1.8 V ± 5% (externally regulated; 1.71 V
to 1.89 V, internal regulator bypassed).
4.1
Mode 1: 1.8 V to 5.5 V external supply
In this mode, the PSoC™ 4100S is powered by an external power supply that can be anywhere in the range of
1.8 V to 5.5 V. This range is also designed for battery-powered operation. For example, the chip can be powered
from a battery system that starts at 3.5 V and works down to 1.8 V. In this mode, the internal regulator of the
PSoC™ 4100S supplies the internal logic and its output is connected to the VCCD pin. The VCCD pin must be
bypassed to ground via an external capacitor (0.1 µF; X5R ceramic or better) and must not be connected to
anything else.
Datasheet
19
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Power
4.2
Mode 2: 1.8 V ± 5% external supply
In this mode, the PSoC™ 4100S is powered by an external power supply that must be within the range of 1.71 V to
1.89 V; note that this range needs to include the power supply ripple too. In this mode, the VDD and VCCD pins
are shorted together and bypassed. The internal regulator can be disabled in the firmware.
Bypass capacitors must be used from VDDD to ground. The typical practice for systems in this frequency range is
to use a capacitor in the 1-µF range, in parallel with a smaller capacitor (0.1 µF, for example). Note that these are
simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass
capacitor parasitic should be simulated to design and obtain optimal bypassing.
Figure 6 shows an example of a bypass scheme.
Power supply bypass connections example
1.8 V to 5.5 V
VDD
1 mF
PSoCTM 4100S
1.8 V to 5.5 V
VDDA
1 mF
0.1 mF
0.1 mF
VCCD
0.1 mF
VSS
Figure 6
Datasheet
External supply range from 1.8 V to 5.5 V with internal regulator active
20
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5
Electrical specifications
5.1
Absolute maximum ratings
Table 3
Absolute maximum ratings[1]
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/conditions
SID1
VDDD_ABS
Digital supply relative to VSS
–0.5
–
6
SID2
VCCD_ABS
Direct digital core voltage
input relative to VSS
–0.5
–
1.95
SID3
VGPIO_ABS
GPIO voltage
–0.5
–
VDD + 0.5
–
SID4
IGPIO_ABS
Maximum current per GPIO
–25
–
25
–
SID5
GPIO injection current,
IGPIO_injection Max for VIH > VDDD, and
Min for VIL < VSS
–0.5
–
0.5
BID44
ESD_HBM
Electrostatic discharge
human body model
2200
–
–
BID45
ESD_CDM
Electrostatic discharge
charged device model
500
–
–
BID46
LU
Pin current for latch-up
–140
–
140
–
V
mA
–
Current injected per pin
–
V
–
mA –
Note
1. Usage above the absolute maximum conditions listed in Table 3 may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150°C in
compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions but
above normal operating conditions, the device may not operate to specification.
Datasheet
21
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2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.2
Device level specifications
All specifications are valid for –40°C TA 105°C and TJ 125°C, except where noted. Specifications are valid for
1.71 V to 5.5 V, except where noted.
Table 4
DC specifications
Typical values measured at VDD = 3.3 V and 25 °C.
Spec ID
Parameter
Description
Min
Typ
Max
SID53
VDD
Power supply input voltage
1.8
–
5.5
SID255
VDD
Power supply input voltage
(VCCD = VDDD = VDDA)
1.71
–
1.89
SID54
VCCD
Output voltage (for core
logic)
–
1.8
–
SID55
CEFC
External regulator voltage
bypass
–
0.1
–
SID56
CEXC
Power supply bypass
capacitor
–
1
–
Unit
Details/conditions
Internally regulated
supply
V
Internally unregulated
supply
–
µF
X5R ceramic or better
Active Mode, VDD = 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25°C.
SID10
IDD5
Execute from flash;
CPU at 6 MHz
–
1.8
2.7
SID16
IDD8
Execute from flash;
CPU at 24 MHz
–
3.0
4.75
SID19
IDD11
Execute from flash;
CPU at 48 MHz
–
5.4
6.85
1.7
2.2
mA Max is at 85°C and 5.5 V
Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on)
SID22
SID25
IDD17
I2C wakeup WDT, and
comparators on
–
IDD20
I2C wakeup, WDT, and
comparators on.
–
mA
6 MHz. Max is at 85°C
and 5.5 V.
2.2
2.5
12 MHz. Max is at 85°C
and 5.5 V.
6 MHz. Max is at 85°C
and 5.5 V.
Sleep Mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed)
SID28
IDD23
I2C wakeup, WDT, and
comparators on
–
0.7
0.9
SID28A
IDD23A
I2C wakeup, WDT, and
comparators on
–
1
1.2
–
2.5
60
µA
Max is at 3.6 V and 85°C.
–
2.5
60
µA
Max is at 5.5 V and 85°C.
Max is at 1.89 V and
85°C.
mA
12 MHz. Max is at 85°C
and 5.5 V.
Deep Sleep Mode, VDD = 1.8 V to 3.6 V (Regulator on)
SID31
IDD26
I2C wakeup and WDT on
Deep Sleep Mode, VDD = 3.6 V to 5.5 V (Regulator on)
SID34
IDD29
I2C wakeup and WDT on
Deep Sleep Mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed)
SID37
IDD32
I2C wakeup and WDT on
–
2.5
65
µA
Supply current while XRES
asserted
–
2
5
mA –
XRES Current
SID307
Datasheet
IDD_XR
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 5
Spec ID
SID48
SID49[2]
AC specifications
Parameter
Description
Min
Typ
Max
DC
–
48
FCPU
CPU frequency
TSLEEP
Wakeup from Sleep mode
–
0
–
Wakeup from Deep Sleep
mode
–
35
–
SID50[2] TDEEPSLEEP
Unit
Details/conditions
MHz 1.71 VDD 5.5
–
µs
–
Note
2. Guaranteed by characterization.
Datasheet
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.2.1
GPIO
Table 6
GPIO DC specifications
Spec ID
Parameter
Description
Min
Typ
Max
–
Unit
Details/conditions
VIH[3]
Input voltage high
threshold
0.7 VDDD
–
SID58
VIL
Input voltage low
threshold
–
–
0.3 VDDD
SID241
VIH[3]
LVTTL input,
VDDD < 2.7 V
0.7 VDDD
–
–
–
SID242
VIL
LVTTL input,
VDDD < 2.7 V
–
–
0.3 VDDD
–
SID243
VIH[3]
LVTTL input,
VDDD 2.7 V
2.0
–
–
–
SID244
VIL
LVTTL input,
VDDD 2.7 V
–
–
0.8
SID59
VOH
Output voltage high
level
VDDD – 0.6
–
–
IOH = 4 mA, VDDD 3 V
SID60
VOH
Output voltage high
level
VDDD – 0.5
–
–
IOH = 1 mA at 1.8 V VDDD
SID61
VOL
Output voltage low
level
–
–
0.6
IOL = 4 mA at 1.8 V VDDD
SID62
VOL
Output voltage low
level
–
–
0.6
IOL = 10 mA, VDDD 3 V
SID62A
VOL
Output voltage low
level
–
–
0.4
IOL = 3 mA, VDDD 3 V
SID63
RPULLUP
Pull-up resistor
3.5
5.6
8.5
SID64
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
SID65
IIL
Input leakage current
(absolute value)
–
–
2
nA
25°C, VDDD = 3.0 V
SID66
pF
–
SID57
CMOS Input
V
k
–
–
–
CIN
Input capacitance
–
–
7
SID67[4]
VHYSTTL
Input hysteresis LVTTL
25
40
–
SID68[4]
VHYSCMOS
Input hysteresis CMOS
0.05 ×
VDDD
–
–
200
–
–
Current through
protection diode to
VDD/VSS
–
–
100
µA
Maximum total source
or sink chip current
–
–
200
mA –
SID68A[4] VHYSCMOS5V5 Input hysteresis CMOS
SID69[4]
IDIODE
SID69A[4] ITOT_GPIO
VDDD 2.7 V
mV
VDD < 4.5 V
–
Notes
3. VIH must not exceed VDDD + 0.2 V.
4. Guaranteed by characterization.
Datasheet
24
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 7
GPIO AC specifications
(Guaranteed by characterization)
Spec ID
Parameter
Description
Min
Typ
Max
Unit
SID70
TRISEF
Rise time in fast strong
mode
2
–
12
SID71
TFALLF
Fall time in fast strong mode
2
–
12
SID72
TRISES
Rise time in slow strong
mode
10
–
60
–
SID73
TFALLS
Fall time in slow strong
mode
10
–
60
–
SID74
FGPIOUT1
GPIO FOUT;
3.3 V VDDD 5.5 V
Fast strong mode
–
–
33
SID75
FGPIOUT2
GPIO FOUT;
1.71 VVDDD3.3 V
Fast strong mode
–
–
16.7
SID76
FGPIOUT3
GPIO FOUT;
3.3 V VDDD 5.5 V
Slow strong mode
–
–
7
SID245
FGPIOUT4
GPIO FOUT;
1.71 V VDDD 3.3 V
Slow strong mode.
–
–
3.5
SID246
FGPIOIN
GPIO input operating
frequency;
1.71 V VDDD 5.5 V
–
–
48
Datasheet
Details/conditions
ns
3.3 V VDDD,
Cload = 25 pF
90/10%, 25 pF load,
60/40 duty cycle
25
MHz
90/10% VIO
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.2.2
XRES
Table 8
XRES DC specifications
Spec ID
Parameter
Description
Min
Typ
Max
Unit Details/conditions
SID77
VIH
Input voltage high threshold 0.7 × VDDD
–
–
SID78
VIL
Input voltage low threshold
–
–
0.3 × VDDD
SID79
RPULLUP
Pull-up resistor
–
60
–
kΩ –
SID80
CIN
Input capacitance
–
–
7
pF
SID81[5] VHYSXRES
Input voltage hysteresis
–
100
–
Typical hysteresis
mV is 200 mV for
VDD > 4.5 V
SID82
Current through protection
diode to VDD/VSS
–
–
100
Min
Typ
Max
Unit
1
–
–
µs
–
–
2.7
Table 9
Spec ID
SID83[5]
IDIODE
V
CMOS Input
–
µA –
XRES AC specifications
Parameter
Description
TRESETWIDTH Reset pulse width
BID194[5] TRESETWAKE
Wake-up time from reset
release
Details/conditions
–
ms –
Note
5. Guaranteed by characterization.
Datasheet
26
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.3
Analog peripherals
5.3.1
CTBm Opamp
Table 10
CTBm Opamp specifications
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/conditions
IDD
Opamp block current,
external load
SID269
IDD_HI
Power = High
–
1100
1850
SID270
IDD_MED
Power = Medium
–
550
950
SID271
IDD_LOW
Power = Low
–
150
350
GBW
Load = 20 pF, 0.1 mA
VDDA = 2.7 V
SID272
GBW_HI
Power = High
6
–
–
SID273
GBW_MED
Power = Medium
3
–
–
SID274
GBW_LO
Power = Low
–
1
–
IOUT_MAX
VDDA = 2.7 V,
500 mV from rail
SID275
IOUT_MAX_HI
Power = High
10
–
–
SID276
IOUT_MAX_MID
Power = Medium
10
–
–
SID277
IOUT_MAX_LO
Power = Low
–
5
–
IOUT
VDDA = 1.71 V,
500 mV from rail
SID278
IOUT_MAX_HI
Power = High
4
–
–
SID279
IOUT_MAX_MID
Power = Medium
4
–
–
SID280
IOUT_MAX_LO
Power = Low
–
2
–
IDD_Int
Opamp block current,
internal load
SID269_I
IDD_HI_Int
Power = High
–
1500
1700
SID270_I
IDD_MED_Int
Power = Medium
–
700
900
IDD_LOW_Int
Power = Low
–
–
–
–
GBW
VDDA = 2.7 V
–
–
–
–
GBW_HI_Int
Power = High
8
–
–
–
VDDA – 0.2
SID271_I
SID272_I
–
µA
–
–
MHz
Input and output
are 0.2 V to
VDDA – 0.2 V
mA
Output is 0.5 V to
VDDA – 0.5 V
mA
Output is 0.5 V to
VDDA – 0.5 V
–
µA
MHz
–
Output is 0.25 V to
VDDA – 0.25 V
General opamp specs
for both internal and
external modes
SID281
SID282
Datasheet
VIN
Charge-pump on,
VDDA = 2.7 V
–0.05
VCM
Charge-pump on,
VDDA = 2.7 V
–0.05
–
V
27
–
VDDA – 0.2
–
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 10
Spec ID
CTBm Opamp specifications (continued)
Parameter
Description
Min
Typ
Max
Unit
Details/conditions
VOUT
VDDA = 2.7 V
SID283
VOUT_1
Power = High,
Iload = 10 mA
0.5
–
VDDA – 0.5
–
SID284
VOUT_2
Power = High,
Iload = 1 mA
0.2
–
VDDA – 0.2
–
SID285
VOUT_3
Power = Medium,
Iload = 1 mA
0.2
–
VDDA – 0.2
–
SID286
VOUT_4
Power = Low,
Iload = 0.1 mA
0.2
–
VDDA – 0.2
–
SID288
VOS_TR
Offset voltage,
trimmed
–1.0
0.5
1.0
SID288A
VOS_TR
Offset voltage,
trimmed
–
1
–
SID288B
VOS_TR
Offset voltage,
trimmed
–
2
–
Low mode, input
0 V to VDDA – 0.2 V
SID290
VOS_DR_TR
Offset voltage drift,
trimmed
–10
3
10
High mode
SID290A
VOS_DR_TR
Offset voltage drift,
trimmed
–
10
–
SID290B
VOS_DR_TR
Offset voltage drift,
trimmed
–
10
–
SID291
CMRR
V
DC
70
80
High mode, input
0 V to VDDA – 0.2 V
mV
µV/°C
PSRR
Input is 0 V to
VDDA – 0.2 V,
–
At 1 kHz, 10-mV ripple
70
85
–
Medium mode
Low mode
dB
SID292
Medium mode,
input 0 V to
VDDA – 0.2 V
Output is 0.2 V to
VDDA – 0.2 V
VDDD = 3.6 V,
high-power mode,
input is 0.2 V to
VDDA – 0.2 V
Noise
SID294
VN2
Input-referred, 1 kHz,
Power = High
–
72
–
SID295
VN3
Input-referred, 10 kHz,
Power = High
–
28
–
VN4
Input-referred,
100 kHz,
Power = High
–
15
–
SID296
Datasheet
28
Input and output
nV/rtHz are at 0.2 V to
VDDA – 0.2 V
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 10
Spec ID
CTBm Opamp specifications (continued)
Parameter
Description
Min
Typ
Max
Unit
Details/conditions
CLOAD
Stable up to max.
load. Performance
specs at 50 pF.
–
–
125
pF
–
SLEW_RATE
Cload = 50 pF,
Power = High,
VDDA = 2.7 V
6
–
–
V/µs
–
SID299
T_OP_WAKE
From disable to
enable, no external RC
dominating
–
–
25
µs
–
SID299A
OL_GAIN
Open Loop Gain
–
90
–
dB
–
COMP_MODE
Comparator mode;
50 mV drive,
Trise = Tfall (approx.)
SID300
TPD1
Response time;
Power = High
–
150
–
SID301
TPD2
Response time;
Power = Medium
–
500
–
ns
Input is 0.2 V to
VDDA – 0.2 V
SID302
TPD3
Response time;
Power = Low
–
2500
–
SID303
VHYST_OP
Hysteresis
–
10
–
mV
–
SID304
WUP_CTB
Wake-up time from
Enabled to Usable
–
–
25
µs
–
Deep Sleep
Mode
Mode 2 is lowest
current range.
Mode 1 has higher
GBW.
SID_DS_1
IDD_HI_M1
Mode 1, high current
–
1400
–
SID_DS_2
IDD_MED_M1
Mode 1,
medium current
–
700
–
SID_DS_3
IDD_LOW_M1
Mode 1, low current
–
200
–
SID_DS_4
IDD_HI_M2
Mode 2, high current
–
120
–
µA
25°C
SID_DS_5
IDD_MED_M2
Mode 2,
medium current
–
60
–
SID_DS_6
IDD_LOW_M2
Mode 2, low current
–
15
–
SID297
SID298
Datasheet
29
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 10
Spec ID
CTBm Opamp specifications (continued)
Parameter
Description
Min
Typ
Max
Unit
Details/conditions
MHz
20-pF load, no DC
load 0.2 V to
VDDA – 0.2 V
mV
With trim 25°C,
0.2 V to VDDA – 0.2 V
SID_DS_7
GBW_HI_M1
Mode 1, high current
–
4
–
SID_DS_8
GBW_MED_M1
Mode 1,
medium current
–
2
–
SID_DS_9
GBW_LOW_M1
Mode 1, low current
–
0.5
–
SID_DS_10
GBW_HI_M2
Mode 2, high current
–
0.5
–
SID_DS_11
GBW_MED_M2
Mode 2,
medium current
–
0.2
–
SID_DS_12
GBW_Low_M2
Mode 2, low current
–
0.1
–
SID_DS_13
VOS_HI_M1
Mode 1, high current
–
5
–
SID_DS_14
VOS_MED_M1
Mode 1,
medium current
–
5
–
SID_DS_15
VOS_LOW_M1
Mode 1, low current
–
5
–
SID_DS_16
VOS_HI_M2
Mode 2, high current
–
5
–
SID_DS_17
VOS_MED_M2
Mode 2,
medium current
–
5
–
SID_DS_18
VOS_LOW_M2
Mode 2, low current
–
5
–
SID_DS_19
IOUT_HI_M1
Mode 1, high current
–
10
–
SID_DS_20
IOUT_MED_M1
Mode 1,
medium current
–
10
–
SID_DS_21
IOUT_LOW_M1
Mode 1, low current
–
4
–
SID_DS_22
IOUT_HI_M2
Mode 2, high current
–
1
–
SID_DS_23
IOUT_MED_M2
Mode 2,
medium current
–
1
–
–
SID_DS_24
IOUT_LOW_M2
Mode 2, low current
–
0.5
–
–
Datasheet
30
Output is 0.5 V to
VDDA – 0.5 V
mA
–
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.3.2
Comparator
Table 11
Comparator DC specifications
Spec ID
Parameter
Description
Min Typ
Max
SID84
VOFFSET1
Input offset voltage,
factory trim
–
–
±10
SID85
VOFFSET2
Input offset voltage,
custom trim
–
–
±4
SID86
VHYST
Hysteresis when enabled
–
10
35
SID87
VICM1
Input common mode
voltage in normal mode
0
–
VDDD – 0.1
SID247
VICM2
Input common mode
voltage in low power mode
0
–
VDDD
SID247A
VICM3
Input common mode
voltage in ultra low power
mode
0
–
VDDD – 1.15
SID88
CMRR
Common mode rejection
ratio
50
–
–
SID88A
CMRR
Common mode rejection
ratio
42
–
–
SID89
ICMP1
Block current, normal mode
–
–
400
SID248
ICMP2
Block current,
low power mode
–
–
100
SID259
ICMP3
Block current in ultra
low-power mode
–
–
6
SID90
ZCMP
DC Input impedance of
comparator
35
–
–
Table 12
Spec ID
Unit
–
mV
Modes 1 and 2
V
dB VDDD ≥ 2.7 V
–
µA
MΩ –
Comparator AC specifications
Parameter
Description
Min
Typ
Max
38
110
Unit
SID258
TRESP2
Response time, low power
mode, 50 mV overdrive
–
70
200
SID92
TRESP3
Response time, ultra-low
power mode, 200 mV
overdrive
–
2.3
15
µs
Min
Typ
Max
Unit
–5
±1
5
°C
5.3.3
Temperature Sensor
Table 13
Temperature sensor specifications
Datasheet
–
VDDD ≥ 2.2 V at –40°C
–
SID93
–
VDDD ≥ 2.2 V at –40°C
Response time, normal
mode, 50 mV overdrive
Spec ID
–
–
TRESP1
SID91
Details/conditions
Parameter
TSENSACC
Description
Temperature sensor
accuracy
31
Details/conditions
–
ns
–
VDDD ≥ 2.2 V at –40°C
Details/conditions
–40°C to +85°C
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.3.4
SAR
Table 14
SAR specifications
Spec ID
Parameter
Description
Min
Typ
Max
Unit Details/conditions
SAR ADC DC specifications
SID94
A_RES
Resolution
–
–
12
bits
–
SID95
A_CHNLS_S
Number of channels - single
ended
–
–
16
–
SID96
A-CHNKS_D
Number of channels differential
–
–
4
Diff inputs use
neighboring I/O
SID97
A-MONO
Monotonicity
–
–
–
Yes
SID98
A_GAINERR
Gain error
–
–
±0.1
%
With external
reference.
SID99
A_OFFSET
Input offset voltage
–
–
2
mV
Measured with 1-V
reference
SID100
A_ISAR
Current consumption
–
–
1
mA
–
SID101
A_VINS
Input voltage range - single
ended
VSS
–
VDDA
VSS
–
VDDA
–
V
SID102
A_VIND
Input voltage range differential
SID103
A_INRES
Input resistance
–
–
2.2
kΩ
–
SID104
A_INCAP
Input capacitance
–
–
10
pF
–
SID260
VREFSAR
Trimmed internal reference
to SAR
1.188
1.2
1.212
V
–
70
–
–
–
SAR ADC AC specifications
SID106
A_PSRR
Power supply rejection ratio
–
dB
SID107
A_CMRR
Common mode rejection
ratio
66
–
–
SID108
A_SAMP
Sample rate
–
–
1
SID109
A_SNR
Signal-to-noise and
distortion ratio (SINAD)
65
–
–
SID110
A_BW
Input bandwidth without
aliasing
–
–
A_samp/2
SID111
A_INL
Integral non linearity.
VDD = 1.71 V to 5.5 V, 1 Msps
–1.7
–
2
SID111A
A_INL
Integral non linearity.
VDDD = 1.71 V to 3.6 V, 1 Msps
–1.5
–
1.7
VREF = 1.71 V to VDD
SID111B
A_INL
Integral non linearity.
VDD = 1.71 V to 5.5 V, 500 ksps
–1.5
–
1.7
VREF = 1 V to VDD
SID112
A_DNL
Differential non linearity.
VDD = 1.71 V to 5.5 V, 1 Msps
–1
–
2.2
SID112A
A_DNL
Differential non linearity.
VDD = 1.71 V to 3.6 V, 1 Msps
–1
–
2
SID112B
A_DNL
Differential non linearity.
VDD = 1.71 V to 5.5 V, 500 ksps
–1
–
2.2
Datasheet
32
Measured at 1 V
Msps –
dB
FIN = 10 kHz
kHz –
VREF = 1 V to VDD
LSB
VREF = 1 V to VDD
VREF = 1.71 V to VDD
VREF = 1 V to VDD
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 14
SAR specifications (continued)
Spec ID
Parameter
Description
SID113
A_THD
Total harmonic distortion
SID261
SAR operating speed
FSARINTREF without external reference
bypass
5.3.5
CSD and IDAC
Table 15
CSD and IDAC specifications
Spec ID
SYS.PER#3
SYS.PER#16
Parameter
VDD_RIPPLE
Description
Max allowed ripple on
power supply,
DC to 10 MHz
Max allowed ripple on
VDD_RIPPLE_1.8 power supply,
DC to 10 MHz
SID.CSD.BLK
ICSD
Maximum block
current
SID.CSD#15
VREF
SID.CSD#15A
SID.CSD#16
Min
–
Typ
–
Max
–
–
100
ksps 12-bit resolution
Max
Unit Details/conditions
Min Typ
–
–
–65
Unit Details/conditions
dB
VDD > 2 V (with
ripple), 25°C TA,
Sensitivity = 0.1 pF
±50
±25
VDD > 1.75V (with
ripple), 25°C TA,
Parasitic
capacitance (CP) <
20 pF,
Sensitivity ≥ 0.4 pF
Maximum block
current for both
IDACs in dynamic
(switching) mode
including
comparators,
buffer, and
reference
generator.
mV
–
–
Fin = 10 kHz
–
–
4000
Voltage reference for
CSD and comparator
0.6
1.2
VDDA – 0.6
VREF_EXT
External voltage
reference for CSD and
comparator
0.6
–
VDDA – 0.6
IDAC1IDD
IDAC1 (7-bits) block
current
–
–
1750
–
–
1750
µA
VDDA – 0.6 or 4.4,
whichever is lower
V
VDDA – 0.6 or 4.4,
whichever is lower
–
µA
SID.CSD#17
IDAC2IDD
IDAC2 (7-bits) block
current
SID308
VCSD
Voltage range of
operation
1.71
–
5.5
SID308A
VCOMPIDAC
Voltage compliance
range of IDAC
0.6
–
VDDA – 0.6
SID309
IDAC1DNL
DNL
–1
–
1
–
SID310
IDAC1INL
INL
–2
–
2
INL is ±5.5 LSB for
VDDA < 2 V
SID311
IDAC2DNL
DNL
–1
–
1
SID312
IDAC2INL
INL
–2
–
2
Datasheet
33
–
V
LSB
1.8 V ± 5% or 1.8 V
to 5.5 V
VDDA – 0.6 or 4.4,
whichever is lower
–
INL is ±5.5 LSB for
VDDA < 2 V
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 15
Spec ID
CSD and IDAC specifications (continued)
Parameter
Description
SID313
SNR
Ratio of counts of
finger to noise.
Guaranteed by
characterization
SID314
IDAC1CRT1
SID314A
Min Typ
Max
Unit Details/conditions
Capacitance range
of 5 to 35 pF, 0.1-pF
Ratio
sensitivity. All use
cases. VDDA > 2 V.
5
–
–
Output current of
IDAC1 (7 bits) in low
range
4.2
–
5.4
LSB = 37.5-nA typ.
IDAC1CRT2
Output current of
IDAC1 (7 bits) in
medium range
34
–
41
LSB = 300-nA typ.
SID314B
IDAC1CRT3
Output current of
IDAC1 (7 bits) in high
range
275
–
330
LSB = 2.4-µA typ.
SID314C
IDAC1CRT12
Output current of
IDAC1 (7 bits) in low
range, 2X mode
8
–
10.5
LSB = 75-nA typ.
SID314D
IDAC1CRT22
Output current of
IDAC1 (7 bits) in
medium range, 2X
mode
69
–
82
LSB = 600-nA typ.
SID314E
IDAC1CRT32
Output current of
IDAC1 (7 bits) in high
range, 2X mode
540
–
660
LSB = 4.8-µA typ.
SID315
IDAC2CRT1
Output current of
IDAC2 (7 bits) in low
range
4.2
–
5.4
LSB = 37.5-nA typ.
SID315A
IDAC2CRT2
Output current of
IDAC2 (7 bits) in
medium range
34
–
41
LSB = 300-nA typ.
SID315B
IDAC2CRT3
Output current of
IDAC2 (7 bits) in high
range
275
–
330
LSB = 2.4-µA typ.
SID315C
IDAC2CRT12
Output current of
IDAC2 (7 bits) in low
range, 2X mode
8
–
10.5
LSB = 75-nA typ.
SID315D
IDAC2CRT22
Output current of
IDAC2 (7 bits) in
medium range, 2X
mode
69
–
82
LSB = 600-nA typ.
SID315E
IDAC2CRT32
Output current of
IDAC2 (7 bits) in high
range, 2X mode
540
–
660
LSB = 4.8-µA typ.
SID315F
IDAC3CRT13
Output current of IDAC
in 8-bit mode in low
range
8
–
10.5
LSB = 37.5-nA typ.
SID315G
IDAC3CRT23
Output current of IDAC
in 8-bit mode in
medium range
69
–
82
LSB = 300-nA typ.
Datasheet
34
µA
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 15
Spec ID
SID315H
CSD and IDAC specifications (continued)
Parameter
IDAC3CRT33
Description
Min Typ
Output current of IDAC
in 8-bit mode in high
540
range
–
Max
660
Unit Details/conditions
µA
LSB = 2.4-µA typ.
Polarity set by
Source or Sink.
LSB
Offset is 2 LSBs for
37.5 nA/LSB mode
SID320
IDACOFFSET
All zeroes input
–
–
1
SID321
IDACGAIN
Full-scale error less
offset
–
–
±10
SID322
Mismatch between
IDACMISMATCH1 IDAC1 and IDAC2 in
Low mode
–
–
9.2
LSB = 37.5-nA typ.
SID322A
Mismatch between
IDACMISMATCH2 IDAC1 and IDAC2 in
Medium mode
–
–
5.6
LSB LSB = 300-nA typ.
SID322B
Mismatch between
IDACMISMATCH3 IDAC1 and IDAC2 in
High mode
–
–
6.8
LSB = 2.4-µA typ.
SID323
IDACSET8
Settling time to 0.5 LSB
for 8-bit IDAC
–
–
10
Full-scale
transition.
No external load.
SID324
IDACSET7
Settling time to 0.5 LSB
for 7-bit IDAC
–
–
10
SID325
CMOD
External modulator
capacitor.
–
2.2
–
%
µs
Datasheet
35
nF
–
Full-scale
transition.
No external load.
5-V rating, X7R or
NP0 cap.
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.3.6
10-bit CapSense ADC
Table 16
10-bit CAPSENSE™ ADC specifications
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/conditions
bits
Auto-zeroing is required
every millisecond
SIDA94
A_RES
Resolution
–
–
10
SIDA95
A_CHNLS_S
Number of channels - single
ended
–
–
16
SIDA97
A-MONO
Monotonicity
–
–
–
Yes –
SIDA98
A_GAINERR
Gain error
–
–
±2
%
SIDA99
A_OFFSET
Input offset voltage
–
–
3
In VREF (2.4 V) mode with
mV VDDA bypass
capacitance of 10 µF
SIDA100
A_ISAR
Current consumption
–
–
0.25
SIDA101
A_VINS
Input voltage range - single
ended
VSSA
–
VDDA
SIDA103
A_INRES
Input resistance
–
2.2
–
KΩ –
SIDA104
A_INCAP
Input capacitance
–
20
–
pF
SIDA106
A_PSRR
Power supply rejection ratio
–
60
–
In VREF (2.4 V) mode with
dB VDDA bypass
capacitance of 10 µF
SIDA107
A_TACQ
Sample acquisition time
–
1
–
A_CONV8
Conversion time for 8-bit
resolution at conversion
rate = Fhclk/(2^(N+2)). Clock
frequency = 48 MHz.
SIDA108
–
–
SIDA109
A_SND
Signal-to-noise and
Distortion ratio (SINAD)
–
61
–
SIDA110
A_BW
Input bandwidth without
aliasing
–
–
22.4
SIDA111
A_INL
Integral Non Linearity.
1 ksps
–
–
2
A_DNL
Differential Non Linearity.
1 ksps
–
SIDA112
Datasheet
36
V
–
–
85.3
1
–
Does not include
acquisition time.
Equivalent to 44.8 ksps
including acquisition
time.
Does not include
acquisition time.
Equivalent to 11.6 ksps
including acquisition
time.
With 10-Hz input sine
wave, external 2.4-V
dB
reference, VREF (2.4 V)
mode
KHz 8-bit resolution
LSB
–
–
–
µs
A_CONV10
In VREF (2.4 V) mode with
VDDA bypass
capacitance of 10 µF
mA –
21.3
Conversion time for 10-bit
resolution at conversion
rate = Fhclk/(2^(N+2)). Clock
frequency = 48 MHz.
SIDA108A
Defined by AMUX Bus
VREF = 2.4 V or greater
–
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.4
5.4.1
Digital peripherals
Timer Counter Pulse-width Modulator (TCPWM)
Table 17
TCPWM specifications
Spec ID
Parameter
SID.TCPWM.1
ITCPWM1
SID.TCPWM.2
ITCPWM2
SID.TCPWM.2A ITCPWM3
Description
Block current
consumption at 3 MHz
Block current
consumption at 12 MHz
Block current
consumption at 48 MHz
Min
Typ
Max Unit
Details/conditions
–
–
45
–
–
155
–
–
650
–
–
Fc
2/Fc
–
–
For all trigger events[6]
Minimum possible width of
Overflow, Underflow, and CC
(Counter equals Compare
value) outputs
µA All modes (TCPWM)
Fc max = CLK_SYS
Maximum = 48 MHz
SID.TCPWM.3
TCPWMFREQ Operating frequency
SID.TCPWM.4
TPWMENEXT
Input trigger pulse
width
TPWMEXT
Output trigger pulse
widths
2/Fc
–
–
SID.TCPWM.5A TCRES
Resolution of counter
1/Fc
–
–
ns Minimum time between
successive counts
SID.TCPWM.5B PWMRES
PWM resolution
1/Fc
–
–
Minimum pulse width of
PWM Output
SID.TCPWM.5C QRES
Quadrature inputs
resolution
1/Fc
–
–
Minimum pulse width
between Quadrature phase
inputs
SID.TCPWM.5
MHz
Note
6. Trigger events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected.
Datasheet
37
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.4.2
I2C
Table 18
Fixed I2C DC specifications[7]
Spec ID
Parameter
Description
Min
Typ
Max
SID149
II2C1
Block current consumption
at 100 kHz
–
–
50
SID150
II2C2
Block current consumption
at 400 kHz
–
–
135
SID151
II2C3
Block current consumption
at 1 Mbps
–
–
310
SID152
II2C4
I2C enabled in Deep Sleep
mode
–
–
1.4
Table 19
Fixed I2C AC specifications[7]
Spec ID
SID153
Parameter
FI2C1
Description
Bit rate
Min
Typ
Max
–
–
1
Unit Details/conditions
–
–
µA
–
–
Unit Details/conditions
Msps –
Note
7. Guaranteed by characterization.
Datasheet
38
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.4.3
SPI
Table 20
SPI DC specifications[8]
Spec ID
Parameter
Description
Min
Typ
Max
SID163
ISPI1
Block current
consumption at 1 Mbps
–
–
360
SID164
ISPI2
Block current
consumption at 4 Mbps
–
–
560
SID165
ISPI3
Block current
consumption at 8 Mbps
–
–
600
Table 21
SPI AC specifications[8]
Spec ID
SID166
Parameter
FSPI
Unit Details/conditions
–
µA
–
–
Description
Min
Typ
Max
Unit Details/conditions
SPI operating frequency
(Master; 6X
oversampling)
–
–
8
MHz SID166
–
Fixed SPI Master Mode AC specifications
SID167
TDMO
MOSI valid after SClock
driving edge
–
–
15
SID168
TDSI
MISO valid before
SClock capturing edge
20
–
–
SID169
THMO
Previous MOSI data
hold time
0
–
–
Referred to Slave
capturing edge
–
ns
Full clock, late
MISO sampling
Fixed SPI Slave Mode AC specifications
SID170
TDMI
MOSI valid before
Sclock capturing edge
40
–
–
SID171
TDSO
MISO valid after Sclock
driving edge
–
–
42 + (3 × Tcpu)
SID171A
TDSO_EXT
MISO valid after Sclock
driving edge in External
Clock mode
–
–
48
SID172
THSO
Previous MISO data
hold time
0
–
–
–
SID172A
TSSELSSCK
SSEL valid to first SCK
valid edge
100
–
–
–
TCPU = 1/FCPU
ns
–
Note
8. Guaranteed by characterization.
Datasheet
39
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.4.4
UART
Table 22
UART DC specifications[9]
Spec ID
SID160
SID161
Parameter
Description
Min
Typ
Max
IUART1
Block current consumption
at 100 Kbps
–
–
55
IUART2
Block current consumption
at 1000 Kbps
–
SID162
–
µA
Parameter
FUART
Description
Bit rate
5.4.5
LCD
Table 24
LCD direct drive DC specifications[9]
Spec ID
Details/conditions
–
312
–
UART AC specifications[9]
Table 23
Spec ID
Unit
Parameter
Description
Min
Typ
Max
–
–
1
Unit Details/conditions
Mbps –
Min
Typ
Max
Unit
Details/conditions
SID154
ILCDLOW
Operating current in low
power mode
–
5
–
µA
16 × 4 small segment
disp. at 50 Hz
SID155
CLCDCAP
LCD capacitance per
segment/common driver
–
500
5000
pF
–
SID156
LCDOFFSET
Long-term segment offset
–
20
–
SID157
ILCDOP1
LCD system operating
current Vbias = 5 V
–
2
–
ILCDOP2
LCD system operating
current Vbias = 3.3 V
–
2
–
Min
Typ
Max
Unit
10
50
150
Hz
SID158
SID159
mA
32 × 4 segments. 50 Hz.
25°C
32 × 4 segments. 50 Hz.
25°C
LCD direct drive AC specifications[9]
Table 25
Spec ID
mV –
Parameter
FLCD
Description
LCD frame rate
Details/conditions
–
Note
9. Guaranteed by characterization.
Datasheet
40
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.5
Memory
5.5.1
Flash
Table 26
Flash DC specifications
Spec ID
SID173
Parameter
VPE
Table 27
Description
Min
Typ
Max
Unit
Erase and program voltage
1.71
–
5.5
V
Details/conditions
–
Flash AC specifications
Spec ID
Parameter
Description
Min
Typ
Max
Unit
Details/conditions
SID174
TROWWRITE[10]
Row (block) write
time (erase and
program)
–
–
20
SID175
TROWERASE[10]
Row erase time
–
–
16
SID176
TROWPROGRAM[10]
Row program time
after erase
–
–
4
–
SID178
TBULKERASE[10]
Bulk erase time
(64 KB)
–
–
35
–
SID180[11]
TDEVPROG[10]
Total device
program time
–
–
7
Seconds –
SID181[11]
FEND
Flash endurance
100 K
–
–
SID182[11]
FRET
Flash retention.
TA 55 °C,
100 K P/E cycles
20
–
–
–
Flash retention.
TA 85 °C,
10 K P/E cycles
10
–
–
SID182B
–
Flash retention.
TA 105 °C,
10K P/E cycles,
three years at
TA ≥ 85 °C
10
–
20
SID256
TWS48
Number of Wait
states at 48 MHz
2
–
–
TWS24
Number of Wait
states at 24 MHz
1
–
–
SID182A[11]
SID257
Row (block) = 128 bytes
ms
Cycles
–
–
–
Years
–
Years
–
CPU execution from
flash
Notes
10.It can take as much as 20 milliseconds to write to flash. During this time the device should not be Reset, or Flash operations may be
interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and
privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated.
11.Guaranteed by characterization.
Datasheet
41
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.6
System resources
5.6.1
Power-on reset (POR)
Table 28
Power-on reset (POR)
Spec ID
Parameter
Description
SID.CLK#6 SR_POWER_UP Power supply slew rate
Min
Typ
Max
Unit
1
–
67
V/ms
SID185[12] VRISEIPOR
Rising trip voltage
0.80
–
1.5
VFALLIPOR
Falling trip voltage
0.70
–
1.4
Min
Typ
Max
–
1.62
SID186[12]
Table 29
Spec ID
SID190[12]
SID192[12]
Parameter
Description
–
V
–
Unit
Details/conditions
VFALLPPOR
BOD trip voltage in active
and sleep modes
1.48
VFALLDPSLP
BOD trip voltage in Deep
Sleep
1.11
–
Min
Typ
Max
3.3 V VDD 5.5 V
–
–
14
–
–
7
SWDCLK ≤ 1/3 CPU
clock frequency
–
SWD interface
Table 30
SWD interface specifications
SID213
At power-up and
power-down
Brown-out detect (BOD) for VCCD
5.6.2
Spec ID
Details/conditions
Parameter
F_SWDCLK1
Description
–
V
1.5
–
Unit Details/conditions
MHz
SID214
F_SWDCLK2
1.71 V VDD 3.3 V
SID215[12]
T_SWDI_SETUP
T = 1/f SWDCLK
0.25 × T
–
–
SID216[12]
T_SWDI_HOLD
T = 1/f SWDCLK
0.25 × T
–
–
SID217[12]
T_SWDO_VALID
T = 1/f SWDCLK
–
–
0.5 × T
SID217A[12]
T_SWDO_HOLD
T = 1/f SWDCLK
1
–
–
ns
SWDCLK ≤ 1/3 CPU
clock frequency
–
–
–
Note
12.Guaranteed by characterization.
Datasheet
42
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.6.3
IMO
Table 31
IMO DC specifications
(Guaranteed by design)
Spec ID
SID218
SID219
Parameter
Description
Typ
Max
–
250
IIMO1
IMO operating current at
48 MHz
–
IIMO2
IMO operating current at
24 MHz
–
Table 32
Spec ID
Unit Details/conditions
–
µA
–
180
–
IMO AC specifications
Parameter
Description
Min
SID223
–
SID223A[13]
SID223B[13]
Min
–
FIMOTOL1
Frequency
variation at 24, 32,
and 48 MHz
(trimmed)
SID223C[13]
–
–
SID223D[13]
Typ
–
–
–
–
Max
±2.0
±2.5
±2.0
±1.5
Unit
Details/conditions
%
At –40°C to 85°C,
for industrial
temperature range and
original extended
industrial range parts
%
At –40°C to 105°C,
for all extended
industrial temperature
range parts
%
At –30°C to 105°C,
for enhanced IMO
extended industrial
temperature range
parts
%
At –20°C to 105°C,
for enhanced IMO
extended industrial
temperature range
parts
–
–
±1.25
%
At 0°C to 85°C,
for enhanced IMO
extended industrial
temperature range
parts
SID226
TSTARTIMO
IMO startup time
–
–
7
µs
–
SID228
TJITRMSIMO2
RMS jitter at 24 MHz
–
145
–
ps
–
Note
13.The enhanced IMO extended temperature range parts replace the original extended industrial temperature range parts. For details
on how to identify enhanced IMO extended temperature range parts, please visit the Infineon knowledge base article: Title (TBD).
Datasheet
43
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.6.4
ILO
Table 33
ILO DC specifications
(Guaranteed by design)
Spec ID
[14]
SID231
Parameter
IILO1
Table 34
Spec ID
[14]
SID234
Description
ILO operating current
Min
Typ
Max
Unit
–
0.3
1.05
µA
Min
Typ
Max
Unit
Details/conditions
–
ILO AC specifications
Parameter
Description
Details/conditions
TSTARTILO1
ILO startup time
–
–
2
ms
–
SID236
TILODUTY
ILO duty cycle
40
50
60
%
–
SID237
FILOTRIM1
ILO frequency range
20
40
80
kHz
–
[14]
5.6.5
WCO
Table 35
WCO specifications
Spec ID
Parameter
Description
Min
Typ
Max
Unit Details/conditions
SID398
FWCO
Crystal frequency
–
32.768
–
SID399
FTOL
Frequency tolerance
–
50
250
ppm
SID400
ESR
Equivalent series resistance
–
50
–
kΩ
–
SID401
PD
Drive level
–
–
1
µW
–
SID402
TSTART
Startup time
–
–
500
ms
–
SID403
CL
Crystal load capacitance
6
–
12.5
SID404
C0
Crystal shunt capacitance
–
1.35
–
SID405
IWCO1
Operating current (high
power mode)
–
–
8
IWCO2
Operating current (low
power mode)
–
SID406
5.6.6
External clock
Table 36
External clock specifications
Spec ID
Parameter
kHz –
With 20-ppm
crystal
–
pF
–
–
A
Description
–
1
–
Min
Typ
Max
Unit
Details/conditions
SID305[14] ExtClkFreq
External clock input
frequency
0
–
48
MHz
–
SID306[14] ExtClkDuty
Duty cycle; measured at
VDD/2
45
–
55
%
–
Note
14.Guaranteed by characterization.
Datasheet
44
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.6.7
Block
Table 37
Block specs
Spec ID
Parameter
SID262[15] TCLKSWITCH
Description
System clock source
switching time
Min
Typ
Max
3
–
4
5.6.8
Smart I/O
Table 38
Smart I/O pass-through time (Delay in Bypass Mode)
Spec ID
SID252
Parameter
PRG_BYPASS
Description
Max delay added by Smart
I/O in Bypass Mode
Unit
Details/conditions
Periods –
Min
Typ
Max
Unit
–
–
1.6
ns
Details/conditions
–
Note
15.Guaranteed by characterization.
Datasheet
45
002-00122 Rev. *O
2022-07-28
PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Ordering information
6
Ordering information
The marketing part numbers for the PSoC™ 4100S family are listed in the following table.
Ordering information
4124
4125
4126
4145
Datasheet
35-ball WLCSP
(0.35mm pitch)
32-pin QFN
40-pin QFN
48-pin TQFP
44-pin TQFP
0
GPIO
1
Smart I/Os
0
SCB Blocks
2
TCPWM Blocks
12-bit SAR ADC
4
LP Comparators
10-bit CSD ADC
16
Package
ADC Sample Rate
CSD
24
Opamp (CTBm)
CY8C4124FNI-S403(T)
Flash (KB)
MPN
SRAM (KB)
Category
Max CPU speed (MHz)
Features
2
5
2
8
31
X
–
–
–
–
Temperature
Range (°C)
Table 39
–40°C to 85°C
CY8C4124FNI-S413(T)
24
16
4
2
1
1
0
2
5
2
16
31
X
–
–
–
–
–40°C to 85°C
CY8C4124LQI-S412(T)
24
16
4
2
1
1
0
2
5
2
16
27
–
X
–
–
–
–40°C to 85°C
CY8C4124LQI-S413(T)
24
16
4
2
1
1
0
2
5
2
16
34
–
–
X
–
–40°C to 85°C
CY8C4124AZI-S413(T)
24
16
4
2
1
1
0
2
5
2
16
36
–
–
–
X
–
–40°C to 85°C
CY8C4124FNI-S433(T)
24
16
4
2
1
1
1
2
5
2
16
31
X
–
–
–
–
–40°C to 85°C
–40°C to 105°C
806 ksps
CY8C4124FNQ-S433(T)
24
16
4
2
1
1
1
806 ksps
2
5
2
16
31
X
–
–
–
–
CY8C4124LQI-S432(T)
24
16
4
2
1
1
1
806 ksps
2
5
2
16
27
–
X
–
–
–
–40°C to 85°C
CY8C4124LQI-S433(T)
24
16
4
2
1
1
1
806 ksps
2
5
2
16
34
–
–
X
–
–
–40°C to 85°C
CY8C4124AZI-S433(T)
24
16
4
2
1
1
1
806 ksps
2
5
2
16
36
–
–
–
X
–
–40°C to 85°C
CY8C4125FNI-S423(T)
24
32
4
2
0
1
1
806 ksps
2
5
2
16
31
X
–
–
–
–
–40°C to 85°C
CY8C4125LQI-S422(T)
24
32
4
2
0
1
1
806 ksps
2
5
2
16
27
–
X
–
–
–
–40°C to 85°C
CY8C4125LQI-S423(T)
24
32
4
2
0
1
1
806 ksps
2
5
2
16
34
–
–
X
–
–
–40°C to 85°C
X
CY8C4125AZI-S423(T)
24
32
4
2
0
1
1
806 ksps
2
5
2
16
36
–
–
–
CY8C4125AXI-S423
24
32
4
2
0
1
1
806 ksps
2
5
2
16
36
–
–
–
–
–40°C to 85°C
X
–40°C to 85°C
CY8C4125FNI-S413(T)
24
32
4
2
1
1
0
2
5
2
16
31
X
–
–
–
–
–40°C to 85°C
CY8C4125LQI-S412(T)
24
32
4
2
1
1
0
2
5
2
16
27
–
X
–
–
–
–40°C to 85°C
CY8C4125LQI-S413(T)
24
32
4
2
1
1
0
2
5
2
16
34
–
–
X
–
–
–40°C to 85°C
CY8C4125AZI-S413(T)
24
32
4
2
1
1
0
2
5
2
16
36
–
–
–
X
–
–40°C to 85°C
CY8C4125FNI-S433(T)
24
32
4
2
1
1
1
2
5
2
16
31
X
–
–
–
–
–40°C to 85°C
–40°C to 105°C
806 ksps
CY8C4125FNQ-S433(T)
24
32
4
2
1
1
1
806 ksps
2
5
2
16
31
X
–
–
–
–
CY8C4125LQI-S432
24
32
4
2
1
1
1
806 ksps
2
5
2
16
27
–
X
–
–
–
–40°C to 85°C
CY8C4125LQQ-S432
24
32
4
2
1
1
1
806 ksps
2
5
2
16
27
–
X
–
–
–
–40°C to 105°C
CY8C4125LQI-S433
24
32
4
2
1
1
1
806 ksps
2
5
2
16
34
–
–
X
–
–
–40°C to 85°C
CY8C4125AZI-S433(T)
24
32
4
2
1
1
1
806 ksps
2
5
2
16
36
–
–
–
X
–
–40°C to 85°C
CY8C4125AZQ-S433
24
32
4
2
1
1
1
806 ksps
2
5
2
16
36
–
–
–
X
–
–40°C to 105°C
CY8C4125AXI-S433
24
32
4
2
1
1
1
806 ksps
2
5
2
16
36
–
–
–
–
X
–40°C to 85°C
CY8C4126AZI-S423(T)
24
64
8
2
0
1
1
806 ksps
2
5
3
16
36
–
–
–
X
–
–40°C to 85°C
CY8C4126AZQ-S423
24
64
8
2
0
1
1
806 ksps
2
5
3
16
36
–
–
–
X
–
–40°C to 105°C
–40°C to 85°C
CY8C4126AXI-S423
24
64
8
2
0
1
1
806 ksps
2
5
3
16
36
–
–
–
–
X
CY8C4126AZI-S433(T)
24
64
8
2
1
1
1
806 ksps
2
5
3
16
36
–
–
–
X
–
–40°C to 85°C
CY8C4126AZQ-S433
24
64
8
2
1
1
1
806 ksps
2
5
3
16
36
–
–
–
X
–
–40°C to 105°C
CY8C4126AXI-S433
24
64
8
2
1
1
1
806 ksps
2
5
3
16
36
–
–
–
–
X
–40°C to 85°C
–40°C to 105°C
CY8C4126AXQ-S433
24
64
8
2
1
1
1
806 ksps
2
5
3
16
36
–
–
–
–
X
CY8C4145AZI-S423(T)
48
32
4
2
0
1
1
1 Msps
2
5
2
16
36
–
–
–
X
–
–40°C to 85°C
CY8C4145AZQ-S433
48
32
4
2
1
1
1
1 Msps
2
5
2
16
36
–
–
–
X
–
–40°C to 105°C
CY8C4145AXI-S423
48
32
4
2
0
1
1
1 Msps
2
5
2
16
36
–
–
–
–
X
–40°C to 85°C
CY8C4145AXI-S433
48
32
4
2
1
1
1
1 Msps
2
5
2
16
36
–
–
–
–
X
–40°C to 85°C
CY8C4145AXQ-S433
48
32
4
2
1
1
1
1 Msps
2
5
2
16
36
–
–
–
–
X
–40°C to 105°C
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Ordering information
Ordering information (continued)
4146
Datasheet
5
3
16
31
X
–
–
–
–
–40°C to 85°C
2
5
3
16
27
–
X
–
–
–
–40°C to 85°C
Temperature
Range (°C)
2
1 Msps
44-pin TQFP
35-ball WLCSP
(0.35mm pitch)
1 Msps
48-pin TQFP
GPIO
1
1
32-pin QFN
Smart I/Os
1
1
SCB Blocks
0
0
TCPWM Blocks
2
2
LP Comparators
ADC Sample Rate
8
8
10-bit CSD ADC
64
64
CSD
48
48
Opamp (CTBm)
CY8C4146FNI-S423(T)
Flash (KB)
12-bit SAR ADC
Package
CY8C4146LQI-S422(T)
MPN
SRAM (KB)
Category
Max CPU speed (MHz)
Features
40-pin QFN
Table 39
CY8C4146LQQ-S422(T)
48
64
8
2
0
1
1
1 Msps
2
5
3
16
27
–
X
–
–
–
–40°C to 105°C
CY8C4146LQI-S423(T)
48
64
8
2
0
1
1
1 Msps
2
5
3
16
34
–
–
X
–
–
–40°C to 85°C
CY8C4146AZI-S423(T)
48
64
8
2
0
1
1
1 Msps
2
5
3
16
36
–
–
–
X
–
–40°C to 85°C
CY8C4146AZQ-S423
48
64
8
2
0
1
1
1 Msps
2
5
3
16
36
–
–
–
X
–
–40°C to 105°C
CY8C4146AXI-S423
48
64
8
2
0
1
1
1 Msps
2
5
3
16
36
–
–
–
–
X
–40°C to 85°C
CY8C4146AXQ-S423
48
64
8
2
0
1
1
1 Msps
2
5
3
16
36
–
–
–
–
X
–40°C to 105°C
CY8C4146FNI-S433(T)
48
64
8
2
1
1
1
1 Msps
2
5
3
16
31
X
–
–
–
–
–40°C to 85°C
CY8C4146FNQ-S433(T)
48
64
8
2
1
1
1
1 Msps
2
5
3
16
31
X
–
–
–
–
–40°C to 105°C
CY8C4146LQI-S432(T)
48
64
8
2
1
1
1
1 Msps
2
5
3
16
27
–
X
–
–
–
–40°C to 85°C
CY8C4146LQQ-S432(T)
48
64
8
2
1
1
1
1 Msps
2
5
3
16
27
–
X
–
–
–
–40°C to 105°C
CY8C4146LQI-S433(T)
48
64
8
2
1
1
1
1 Msps
2
5
3
16
34
–
–
X
–
–
–40°C to 85°C
CY8C4146AZI-S433(T)
48
64
8
2
1
1
1
1 Msps
2
5
3
16
36
–
–
–
X
–
–40°C to 85°C
CY8C4146AZQ-S433
48
64
8
2
1
1
1
1 Msps
2
5
3
16
36
–
–
–
X
–
–40°C to 105°C
CY8C4146AXI-S433
48
64
8
2
1
1
1
1 Msps
2
5
3
16
36
–
–
–
–
X
–40°C to 85°C
CY8C4146AXQ-S433
48
64
8
2
1
1
1
1 Msps
2
5
3
16
36
–
–
–
–
X
–40°C to 105°C
47
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Based on Arm® Cortex®-M0+ CPU
Ordering information
The nomenclature used in the preceding table is based on the following part numbering convention:
Field
CY8C
Description
Values
Meaning
Prefix
4
Architecture
4
PSoC™ 4
A
Family
1
4100 Family
B
CPU speed
2
24 MHz
4
48 MHz
4
16 KB
5
32 KB
6
64 KB
7
128 KB
AX
TQFP (0.8 mm pitch)
AZ
TQFP (0.5 mm pitch)
LQ
QFN
PV
SSOP
FN
CSP
C
Flash capacity
DE
Package code
F
Temperature range
S
Series designator
XYZ
T
Attributes code
I
Industrial
Q
Extended Industrial
S
S-Series
M
M-Series
L
L-Series
000-999
Code of feature set in the specific family
Tray
Package type
T
Tape and Reel
The following is an example of a part number.
Example
CY8C 4 A B C DE F – S XYZ T
Cypress prefix
4: PSoCTM 4
1: 4100 Family
4: 48 MHz
Architecture
Family within Architecture
CPU speed
5: 32 KB
Flash capacity
AX: TQFP
Package code
I: Industrial
Temperature range
Series designator
Attributes code
Package type
Datasheet
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Based on Arm® Cortex®-M0+ CPU
Packaging
7
Packaging
The PSoC™ 4100S is offered in 48-pin TQFP, 44-pin TQFP, 40-pin QFN, 32-pin QFN, and 35-ball WLCSP packages.
Table 40 provides the package dimensions and Infineon drawing numbers.
Table 40
Package list
Spec ID
Package
Description
Package drawing
BID20
48-pin TQFP
7 × 7 × 1.4-mm height with 0.5-mm pitch
51-85135
BID20A
44-pin TQFP
10 × 10 × 1.6-mm height with 0.8-mm pitch
51-85064
BID27
40-pin QFN
6 × 6 × 0.6-mm height with 0.5-mm pitch
001-80659
BID34A
32-pin QFN
5 × 5 × 0.6-mm height with 0.5-mm pitch
001-42168
BID34D
35-ball WLCSP
2.6 × 2.1 × 0.48-mm height with 0.35-mm pitch
002-09958
Table 41
Package thermal characteristics
Parameter
Description
Package
Min
Typ
Max
Unit
Details/conditions
TA
Operating ambient
temperature
–
–40
25
105
TJ
Operating junction
temperature
–
–40
–
125
–
TJA
Package θJA
48-pin TQFP
–
74.8
–
–
TJC
Package θJC
48-pin TQFP
–
35.7
–
–
TJA
Package θJA
44-pin TQFP
–
57.2
–
–
TJC
Package θJC
44-pin TQFP
–
17.5
–
–
TJA
Package θJA
40-pin QFN
–
17.8
–
–
TJC
Package θJC
40-pin QFN
–
2.8
–
TJA
Package θJA
32-pin QFN
–
19.9
–
TJC
Package θJC
32-pin QFN
–
4.3
–
–
TJA
Package θJA
35-ball
WLCSP
–
43
–
–
TJC
Package θJC
35-ball
WLCSP
–
0.3
–
–
Table 42
Solder reflow peak temperature
–
°C
°C/W
–
–
Package
Maximum peak temperature
Maximum time at peak temperature
All
260 °C
30 seconds
Table 43
Datasheet
Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-020
Package
MSL
All except WLCSP
MSL 3
35-ball WLCSP
MSL 1
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Packaging
7.1
Package diagrams
51-85135 *C
Figure 7
48-pin TQFP (7 × 7 × 1.4 mm) package outline, 51-85135
51-85064 *G
Figure 8
Datasheet
44-pin TQFP (10 × 10 × 1.4 mm) package outline, 51-85064
50
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Packaging
001-80659 *A
Figure 9
Datasheet
40-pin QFN ((6 × 6 × 0.6 mm) 4.6 × 4.6 mm E-Pad (Sawn)) package outline, 001-80659
51
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Packaging
SEE NOTE 1
TOP VIEW
BOTTOM VIEW
SIDE VIEW
DIMENSIONS
NOTES:
1.
SYMBOL
MIN.
NOM.
MAX.
HATCH AREA IS SOLDERABLE EXPOSED PAD
2. BASED ON REF JEDEC # MO-248
A
0.50
0.55
0.60
3. PACKAGE WEIGHT: 0.0388g
A1
-
0.020
0.045
4. DIMENSIONS ARE IN MILLIMETERS
A2
0.15 BSC
D
4.90
5.00
5.10
D2
3.40
3.50
3.60
E
4.90
5.00
5.10
E2
3.40
3.50
3.60
L
0.30
0.40
0.50
b
0.18
0.25
0.30
e
0.50 TYP
001-42168 *F
Figure 10
Datasheet
32-pin QFN ((5.0 × 5.0 × 0.55 mm) 3.5 × 3.5 mm E-Pad (Sawn)) package outline, 001-42168
52
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Packaging
1
2
3
4
5
6
7
6
7
5
4
3
2
1
A
A
B
B
C
C
D
D
E
E
NOTES:
DIMENSIONS
SYMBOL
MIN.
NOM.
MAX.
A
-
-
0.482
A1
0.141
0.157
0.173
D
2.557
2.582
2.607
E
2.072
2.097
2.122
1. ALL DIMENSIONS ARE IN MILLIMETERS.
2. JEDEC PUBLICATION 95; DESIGN GUIDE 4.18.
D1
2.10 BSC
E1
1.40 BSC
MD
7
ME
5
N
35
b
0.19
0.22
0.25
eD
-
0.35
-
eE
-
0.35
-
SD
0
SE
0.02 BSC
002-09958 *D
Figure 11
Datasheet
35-ball WLCSP (2.582 × 2.097 × 0.482 mm) package outline, 002-09958
53
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Acronyms
8
Acronyms
Table 44
Acronyms used in this document
Acronym
Description
abus
analog local bus
ADC
analog-to-digital converter
AG
analog global
AHB
AMBA (advanced microcontroller bus architecture) high-performance bus, an Arm® data
transfer bus
ALU
arithmetic logic unit
AMUXBUS
analog multiplexer bus
API
application programming interface
APSR
application program status register
Arm®
advanced RISC machine, a CPU architecture
ATM
automatic thump mode
BW
bandwidth
CAN
Controller Area Network, a communications protocol
CMRR
common-mode rejection ratio
CPU
central processing unit
CRC
cyclic redundancy check, an error-checking protocol
DAC
digital-to-analog converter, see also IDAC, VDAC
DFB
digital filter block
DIO
digital input/output, GPIO with only digital capabilities, no analog. See GPIO.
DMIPS
Dhrystone million instructions per second
DMA
direct memory access, see also TD
DNL
differential nonlinearity, see also INL
DNU
do not use
DR
port write data registers
DSI
digital system interconnect
DWT
data watchpoint and trace
ECC
error correcting code
ECO
external crystal oscillator
EEPROM
electrically erasable programmable read-only memory
EMI
electromagnetic interference
EMIF
external memory interface
EOC
end of conversion
EOF
end of frame
EPSR
execution program status register
ESD
electrostatic discharge
ETM
embedded trace macrocell
FIR
finite impulse response, see also IIR
Datasheet
54
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Acronyms
Table 44
Acronyms used in this document (continued)
Acronym
Description
FPB
flash patch and breakpoint
FS
full-speed
GPIO
general-purpose input/output, applies to a PSoC pin
HVI
high-voltage interrupt, see also LVI, LVD
IC
integrated circuit
IDAC
current DAC, see also DAC, VDAC
IDE
integrated development environment
I2C, or IIC
Inter-Integrated Circuit, a communications protocol
IIR
infinite impulse response, see also FIR
ILO
internal low-speed oscillator, see also IMO
IMO
internal main oscillator, see also ILO
INL
integral nonlinearity, see also DNL
I/O
input/output, see also GPIO, DIO, SIO, USBIO
IPOR
initial power-on reset
IPSR
interrupt program status register
IRQ
interrupt request
ITM
instrumentation trace macrocell
LCD
liquid crystal display
LIN
Local Interconnect Network, a communications protocol.
LR
link register
LUT
lookup table
LVD
low-voltage detect, see also LVI
LVI
low-voltage interrupt, see also HVI
LVTTL
low-voltage transistor-transistor logic
MAC
multiply-accumulate
MCU
microcontroller unit
MISO
master-in slave-out
NC
no connect
NMI
nonmaskable interrupt
NRZ
non-return-to-zero
NVIC
nested vectored interrupt controller
NVL
nonvolatile latch, see also WOL
opamp
operational amplifier
PAL
programmable array logic, see also PLD
PC
program counter
PCB
printed circuit board
PGA
programmable gain amplifier
PHUB
peripheral hub
PHY
physical layer
PICU
port interrupt control unit
Datasheet
55
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Acronyms
Table 44
Acronyms used in this document (continued)
Acronym
Description
PLA
programmable logic array
PLD
programmable logic device, see also PAL
PLL
phase-locked loop
PMDD
package material declaration data sheet
POR
power-on reset
PRES
precise power-on reset
PRS
pseudo random sequence
PS
port read data register
PSoC™
Programmable System-on-Chip™
PSRR
power supply rejection ratio
PWM
pulse-width modulator
RAM
random-access memory
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
RTL
register transfer language
RTR
remote transmission request
RX
receive
SAR
successive approximation register
SC/CT
switched capacitor/continuous time
SCL
I2C serial clock
SDA
I2C serial data
S/H
sample and hold
SINAD
signal to noise and distortion ratio
SIO
special input/output, GPIO with advanced features. See GPIO.
SOC
start of conversion
SOF
start of frame
SPI
Serial Peripheral Interface, a communications protocol
SR
slew rate
SRAM
static random access memory
SRES
software reset
SWD
serial wire debug, a test protocol
SWV
single-wire viewer
TD
transaction descriptor, see also DMA
THD
total harmonic distortion
TIA
transimpedance amplifier
TRM
technical reference manual
TTL
transistor-transistor logic
TX
transmit
UART
Universal Asynchronous Transmitter Receiver, a communications protocol
Datasheet
56
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Acronyms
Table 44
Acronyms used in this document (continued)
Acronym
Description
UDB
universal digital block
USB
Universal Serial Bus
USBIO
USB input/output, PSoC pins used to connect to a USB port
VDAC
voltage DAC, see also DAC, IDAC
WDT
watchdog timer
WOL
write once latch, see also NVL
WRES
watchdog timer reset
XRES
external reset I/O pin
XTAL
crystal
Datasheet
57
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Document conventions
9
Document conventions
9.1
Units of measure
Table 45
Units of measure
Symbol
Unit of measure
°C
degrees Celsius
dB
decibel
fF
femto farad
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohour
kHz
kilohertz
k
kilo ohm
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
M
mega-ohm
Msps
megasamples per second
µA
microampere
µF
microfarad
µH
microhenry
µs
microsecond
µV
microvolt
µW
microwatt
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
nV
nanovolt
ohm
pF
picofarad
ppm
parts per million
ps
picosecond
s
second
sps
samples per second
sqrtHz
square root of hertz
V
volt
Datasheet
58
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Revision history
Revision histor y
Document
version
Date
**
2015-08-28
New datasheet.
*A
2015-10-30
Updated Pinouts:
Updated Table 1.
Updated Electrical specifications:
Updated Analog peripherals:
Updated Comparator:
Updated Table 11.
Updated Table 12.
Updated 10-bit CapSense ADC:
Updated Table 16.
Updated Ordering information:
Updated part numbers.
Completing Sunset Review.
*B
2015-12-08
Changed status from Advance to Preliminary.
2015-12-22
Updated Features:
Updated description under “32-bit MCU Subsystem” and “Serial
Communication”.
Updated Pinouts:
Updated Table 1.
Updated Table 2.
Updated Ordering information:
No change in part numbers.
Replaced “36 WLCSP (0.35 mm pitch)” with “35-WLCSP”.
Updated Packaging:
Replaced “36-ball WLCSP package” with “35-ball WLCSP package” in all
instances.
Completing Sunset Review.
2016-02-16
Updated Packaging:
Updated Table 41.
Replaced TBD with 002-09958 *A.
Added Errata.
Updated to new template.
Completing Sunset Review.
2016-03-15
Updated Electrical specifications:
Updated Device level specifications:
Updated XRES:
Updated Table 8.
Updated Table 9.
Updated Analog peripherals:
Updated CSD and IDAC:
Updated Table 15.
Updated 10-bit CapSense ADC:
Updated Table 16.
Updated Memory:
Updated Flash:
Updated Table 27.
Completing Sunset Review.
*C
*D
*E
Datasheet
Description of changes
59
002-00122 Rev. *O
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Revision history
Document
version
Date
Description of changes
2016-07-27
Updated Electrical specifications:
Updated Analog peripherals:
Updated CSD and IDAC:
Updated Table 15.
Updated 10-bit CapSense ADC:
Updated Table 16.
Removed Errata.
Completing Sunset Review.
2016-10-13
Added 44-pin TQFP package related information related information in all
instances across the document.
Updated Packaging:
Added 51-85064 *G.
*H
2017-01-09
Updated Functional definition:
Updated Analog blocks:
Updated 12-bit SAR ADC:
Updated Figure 4.
Updated Programmable digital blocks:
Updated description.
Updated Pinouts:
Updated description.
Updated Electrical specifications:
Updated Device level specifications:
Updated Table 4.
Updated Ordering information:
Updated part numbers.
Completing Sunset Review.
*I
2017-04-26
Updated Packaging:
spec 002-09958 – Changed revision from *C to *D.
Updated to new template.
2018-02-14
Updated Features:
Updated description under “Timing and Pulse-Width Modulation”.
Added “Clock Sources”.
Updated Development ecosystem:
Updated description.
Updated Block diagram.
Updated Functional definition:
Updated System resources:
Updated Clock system:
Updated Figure 3.
Updated Pinouts:
Updated Table 2.
Updated Ordering information:
Updated part numbers.
Updated Packaging:
spec 001-42168 – Changed revision from *E to *F.
Updated to new template.
*F
*G
*J
Datasheet
60
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PSoC™ 4 MCU: PSoC™ 4100S
Based on Arm® Cortex®-M0+ CPU
Revision history
Document
version
*K
*L
*M
*N
*O
Datasheet
Date
Description of changes
2018-04-03
Updated Functional definition:
Updated System resources:
Updated Clock system:
Updated Figure 3.
Updated Watchdog timer and counters:
Replaced “Watchdog Timer” with “Watchdog timer and counters” in
heading.
Updated description.
2018-10-30
Updated Features:
Updated description under “32-bit MCU Subsystem”.
Updated Block diagram (Corrected typo).
Updated Functional definition:
Updated System resources:
Updated Watch Crystal Oscillator (WCO):
Updated description.
Updated Electrical specifications:
Updated Analog peripherals:
Updated CTBm Opamp:
Updated Table 10.
Updated SAR:
Updated Table 14.
Updated CSD and IDAC:
Updated Table 15.
Updated Digital peripherals:
Updated SPI:
Updated Table 21.
Completing Sunset Review.
2019-07-05
Added extended industrial temperature range related information in all
instances across the document.
Updated Electrical specifications:
Updated Memory:
Updated Flash:
Updated Table 27.
Updated Ordering information:
Updated part numbers.
2020-11-10
Updated Features:
Added “ModusToolbox™ software”.
Updated Development ecosystem:
Added ModusToolbox™ software.
Updated PSoC™ Creator:
Updated description.
Updated Table 27: Updated SID182B.
Updated Table 32: Added SID223A.
Updated Ordering information:
Updated part numbers.
Completing Sunset Review.
2022-07-28
Updated Table 32: Updated spec SID223 and SID223A. Added specs
SID223B through SID223D.
Updated Ordering information:
Updated part numbers.
Migrated to Infineon template.
61
002-00122 Rev. *O
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Please read the Important Notice and Warnings at the end of this document
Trademarks
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Edition 2022-07-28
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2022 Infineon Technologies AG.
All Rights Reserved.
Do you have a question about this
document?
Go to www.infineon.com/support
Document reference
002-00122 Rev. *O
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