CY8C41xx
PSoC™ 4 MCU: PS oC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
General description
PSoC™ 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system
controllers with an Arm® Cortex®-M0+ CPU. It combines programmable and reconfigurable analog and digital
blocks with flexible automatic routing. PSoC™ 4100S Plus is a member of the PSoC™ 4 platform architecture. It is
a combination of a microcontroller with standard communication and timing peripherals, a capacitive
touch-sensing system (CAPSENSE™) with best-in-class performance, programmable general-purpose
continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC™ 4100S Plus
products are upward compatible with members of the PSoC™ 4 platform for new applications and design needs.
Features
• 32-bit MCU subsystem
- 48-MHz Arm® Cortex®-M0+ CPU with single-cycle multiply
- Up to 128 KB of flash with read accelerator
- Up to 16 KB of SRAM
- 8-channel DMA engine
• Programmable analog
- Two opamps with reconfigurable high-drive external and high-bandwidth internal drive and comparator
modes and ADC input buffering capability. Opamps can operate in Deep Sleep low-power mode.
- 12-bit 1-Msps SAR ADC with differential and single-ended modes, and Channel Sequencer with signal averaging
- Single-slope 10-bit ADC function provided by a capacitance sensing block
- Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin
- Two low-power comparators that operate in Deep Sleep low-power mode
• Programmable digital
- Programmable logic blocks allowing Boolean operations to be performed on port inputs and outputs
• Low-power 1.71-V to 5.5-V operation
- Deep Sleep mode with operational analog and 2.5-µA digital system current
• Capacitive sensing
- Capacitive sigma-delta (CSD) provides best-in-class signal-to-noise ratio (SNR) (>5:1) and water tolerance
- Infineon-supplied software component makes capacitive sensing design easy
- Automatic hardware tuning (SmartSense)
• LCD drive capability
- LCD segment drive capability on GPIOs
• Serial communication
- Five independent run-time reconfigurable Serial Communication Blocks (SCBs) with re-configurable I2C, SPI,
or UART functionality
• Timing and pulse-width modulation
- Eight 16-bit Timer, Counter, Pulse-Width Modulator (TCPWM) blocks
- Center-aligned, edge, and pseudo-random modes
- Comparator-based triggering of kill signals for motor drive and other high-reliability digital logic applications
- Quadrature decoder
Datasheet
www.infineon.com
Please read the Important Notice and Warnings at the end of this document
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PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Features
• Clock sources
- 4 to 33 MHz External Crystal Oscillator (ECO)
- PLL to generate 48-MHz frequency
- 32-kHz Watch Crystal Oscillator (WCO)
- ±2% Internal Main Oscillator (IMO)
- 32-kHz Internal Low-power Oscillator (ILO)
• True random number generator (TRNG)
- TRNG generates truly random number for secure key generation for Cryptography applications
• CAN block
- CAN 2.0B block with support for Time-Triggered CAN (TTCAN)
• Up to 54 programmable GPIO pins
- 44-pin TQFP (0.8-mm pitch), 48-pin TQFP (0.5-mm pitch), and 64-pin TQFP normal (0.8 mm) and fine pitch
(0.5 mm) packages
- Any GPIO pin can be CAPSENSE™, analog, or digital
- Drive modes, strengths, and slew rates are programmable
• ModusToolbox™ software
- Comprehensive collection of multi-platform tools and software libraries
- Includes board support packages (BSPs), peripheral driver library (PDL), and middleware such as CAPSENSE™
• PSoC™ Creator design environment
- Integrated development environment (IDE) provides schematic design entry and build, with analog and digital
automatic routing
- Application programming interface (API) Components for all fixed-function and programmable peripherals
• Industry-standard tool compatibility
- After schematic entry, development can be done with Arm®-based industry-standard development tools
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PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Table of contents
Table of contents
General description ...........................................................................................................................1
Features ...........................................................................................................................................1
Table of contents ...............................................................................................................................3
1 Development ecosystem .................................................................................................................4
1.1 PSoC™ 4 MCU resources .........................................................................................................................................4
1.2 ModusToolbox™ software ......................................................................................................................................5
1.3 PSoC™ Creator ........................................................................................................................................................6
Block diagram...................................................................................................................................7
2 Functional definition.......................................................................................................................8
2.1 CPU and memory subsystem .................................................................................................................................8
2.2 System resources....................................................................................................................................................8
2.3 Analog blocks ........................................................................................................................................................10
2.4 Programmable digital blocks ...............................................................................................................................11
2.5 Fixed function digital blocks ................................................................................................................................11
2.6 GPIO.......................................................................................................................................................................12
2.7 Special function peripherals ................................................................................................................................12
3 Pinouts ........................................................................................................................................14
3.1 Alternate pin functions .........................................................................................................................................17
4 Power ..........................................................................................................................................20
4.1 Mode 1: 1.8 V to 5.5 V external supply ..................................................................................................................20
4.2 Mode 2: 1.8 V ±5% external supply.......................................................................................................................20
5 Electrical specifications.................................................................................................................22
5.1 Absolute maximum ratings .................................................................................................................................22
5.2 Device level specifications....................................................................................................................................22
5.3 Analog peripherals................................................................................................................................................26
5.4 Digital peripherals.................................................................................................................................................35
5.5 Memory..................................................................................................................................................................37
5.6 System resources..................................................................................................................................................38
6 Ordering information ....................................................................................................................42
7 Packaging ....................................................................................................................................45
7.1 Package diagrams.................................................................................................................................................46
8 Acronyms .....................................................................................................................................49
9 Document conventions..................................................................................................................53
9.1 Units of measure ...................................................................................................................................................53
Revision history ..............................................................................................................................54
Datasheet
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PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Development ecosystem
1
Development ecosystem
1.1
PSoC™ 4 MCU resources
Infineon provides a wealth of data at www.Infineon.com to help you select the right PSoC™ device and quickly
and effectively integrate it into your design. The following is an abbreviated, hyperlinked list of resources for
PSoC™ 4 MCU:
• Overview: PSoC™ portfolio, PSoC™ roadmap
• Product selectors: PSoC™ 4 MCU
• Application notes cover a broad range of topics, from basic to advanced level, and include the following:
- AN79953: Getting started With PSoC™ 4. This application note has a convenient flow chart to help decide
which IDE to use: ModusToolbox™ software or PSoC™ Creator.
- AN91184: PSoC™ 4 Bluetooth® LE - Designing Bluetooth® LE applications
- AN88619: PSoC™ 4 hardware design considerations
- AN73854: Introduction to bootloaders
- AN89610: Arm® Cortex® code optimization
- AN86233: PSoC™ 4 MCU low-power modes and reduction techniques
- AN57821: PSoC™ 3, PSoC™ 4, and PSoC™ 5LP mixed-signal circuit board layout considerations
- AN85951: PSoC™ 4 and PSoC™ 6 CAPSENSE™ design guide
• Code examples demonstrate product features and usage, and are also available on Infineon GitHub repositories.
• Technical reference manuals (TRMs) provide detailed descriptions of PSoC™ 4 MCU architecture and registers.
• PSoC™ 4 MCU programming specification provides the information necessary to program PSoC™ 4 MCU
nonvolatile memory.
• Development tools
- ModusToolbox™ software enables cross platform code development with a robust suite of tools and software
libraries.
- PSoC™ Creator is a free Windows-based IDE. It enables concurrent hardware and firmware design of PSoC™ 3,
PSoC™ 4, PSoC™ 5LP, and PSoC™ 6 MCU based systems. Applications are created using schematic capture and
over 150 pre-verified, production-ready peripheral Components.
- CY8CKIT-149 PSoC™ 4100S Plus prototyping kit, is a low-cost and easy-to-use evaluation platform. This kit
provides easy access to all the device I/Os in a breadboard-compatible format.
- MiniProg4 and MiniProg3 all-in-one development programmers and debuggers.
- PSoC™ 4 MCU CAD libraries provide footprint and schematic support for common tools. IBIS models are also
available.
• Training videos are available on a wide range of topics including the PSoC™ 4 MCU 101 series.
• Infineon developer community enables connection with fellow PSoC™ developers around the world, 24 hours
a day, 7 days a week, and hosts a dedicated PSoC™ 4 MCU community.
Datasheet
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Based on Arm® Cortex®-M0+ CPU
Development ecosystem
1.2
ModusToolbox™ software
ModusToolbox™ software is Infineon' comprehensive collection of multi-platform tools and software libraries
that enable an immersive development experience for creating converged MCU and wireless systems. It is:
• Comprehensive - it has the resources you need
• Flexible - you can use the resources in your own workflow
• Atomic - you can get just the resources you want
Infineon provides a large collection of code repositories on GitHub, including:
• Board Support Packages (BSPs) aligned with Infineon kits
• Low-level resources, including a peripheral driver library (PDL)
• Middleware enabling industry-leading features such as CAPSENSE™
• An extensive set of thoroughly tested code example applications
ModusToolbox™ Software is IDE-neutral and easily adaptable to your workflow and preferred development
environment. It includes a project creator, peripheral and library configurators, a library manager, as well as the
optional Eclipse IDE for ModusToolbox™, as Figure 1 shows. For information on using Infineon tools, refer to the
documentation delivered with ModusToolbox™ software, and AN79953 -Getting started with PSoC™ 4.
Figure 1
Datasheet
ModusToolbox™ software tools
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Based on Arm® Cortex®-M0+ CPU
Development ecosystem
1.3
PSoC™ Creator
PSoC™ Creator is a free Windows-based IDE. It enables you to design hardware and firmware systems concurrently, based on PSoC™ 4 MCU. As Figure 2 shows, with PSoC™ Creator you can:
1. Explore the library of 200+ Components
2. Drag and drop Component icons to complete your hardware system design in the main design workspace
3. Configure Components using the Component configuration tools and the Component datasheets
4. Co-design your application firmware and hardware in the PSoC™ Creator IDE or build a project for a third-party
IDE
5. Prototype your solution with the PSoC™ 4 Pioneer kits. If a design change is needed, PSoC™ Creator and
Components enable you to make changes on-the-fly without the need for hardware revisions.
Figure 2
Datasheet
PSoC™ Creator schematic entry and Components
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PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Block diagram
Block diagram
SPCIF
Cortex® M0+
48 MHz
FLASH
128 KB
SRAM
16 KB
ROM
8 KB
DataWire/
DMA
FAST MUL
NVIC, IRQMUX, MPU
Read Accelerator
SRAM Controller
ROM Controller
Initiator / MMIO
System Resources
Lite
Test
TestMode Entry
Digital DFT
Analog DFT
x1
SARMUX
TRNG
C AN
SAR ADC
( 12-bit)
LCD
Programmable
Analog
WCO
Peripheral Interconnect (MMIO)
PCLK
2x LP Comparator
Reset
Reset Control
XRES
Peripherals
IO S S G PIO (8x ports)
Clock
Clock Control
WDT
ILO
IMO
System Interconnect (Single Layer AHB)
ECO(wPLL)
Power
Sleep Control
WIC
POR
REF
PWRSYS
5x S C B-I2 C/S PI/UA R T
AHB- Lite
SWD/TC, MTB
CAPSENSE ™ (v2)
32-bit
CPU Subsystem
8x T C P W M
PSoC™ 4100S
Plus
CTBm
2 x Opamp
High Speed I / O Matrix & Smart I/O
Power Modes
Active/Sleep
DeepSleep
Up to 54 x GPIOs
I/O Subsystem
PSoC™ 4100S Plus devices include extensive support for programming, testing, debugging, and tracing both
hardware and firmware.
The Arm® serial-wire debug (SWD) interface supports all programming and debug features of the device.
Complete debug-on-chip functionality enables full-device debugging in the final system using the standard
production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the
standard programming connections are required to fully support debug.
The PSoC™ Creator IDE provides fully integrated programming and debug support for the PSoC™ 4100S Plus
devices. The SWD interface is fully compatible with industry-standard third-party tools. PSoC™ 4100S Plus
provides a level of security not possible with multi-chip application solutions or with microcontrollers. It has the
following advantages:
• Allows disabling of debug features
• Robust flash protection
• Allows customer-proprietary functionality to be implemented in on-chip programmable blocks
The debug circuits are enabled by default and can be disabled in firmware. If they are not enabled, the only way
to re-enable them is to erase the entire device, clear flash protection, and reprogram the device with new
firmware that enables debugging. Thus firmware control of debugging cannot be over-ridden without erasing the
firmware thus providing security.
Additionally, all device interfaces can be permanently disabled (device security) for applications concerned
about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and
interrupting flash programming sequences. All programming, debug, and test interfaces are disabled when
maximum device security is enabled. Therefore, PSoC™ 4100S Plus, with device security enabled, may not be
returned for failure analysis. This is a trade-off the PSoC™ 4100S Plus allows the customer to make.
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PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Functional definition
2
Functional definition
2.1
CPU and memory subsystem
2.1.1
CPU
The Cortex®-M0+ CPU in the PSoC™ 4100S Plus is part of the 32-bit MCU subsystem, which is optimized for
low-power operation with extensive clock gating. Most instructions are 16 bits in length and the CPU executes a
subset of the Thumb-2 instruction set. It includes a nested vectored interrupt controller (NVIC) block with eight
interrupt inputs and also includes a wakeup interrupt controller (WIC). The WIC can wake the processor from
Deep Sleep mode, allowing power to be switched off to the main processor when the chip is in Deep Sleep mode.
The CPU subsystem includes an 8-channel DMA engine and also includes a debug interface, the serial wire debug
(SWD) interface, which is a two-wire form of JTAG. The debug configuration used for PSoC™ 4100S Plus has four
breakpoint (address) comparators and two watchpoint (data) comparators.
2.1.2
Flash
The PSoC™ 4100S Plus device has a flash module with a flash accelerator, tightly coupled to the CPU to improve
average access times from the flash block. The low-power flash block is designed to deliver two wait-state (WS)
access time at 48 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average.
2.1.3
SRAM
16 KB of SRAM are provided with zero wait-state access at 48 MHz.
2.1.4
SROM
An 8-KB supervisory ROM that contains boot and configuration routines is provided.
2.2
System resources
2.2.1
Power system
The power system is described in detail in the section Power. It provides assurance that voltage levels are as
required for each respective mode and either delays mode entry (for example, on power-on reset (POR)) until
voltage levels are as required for proper functionality, or generates resets (for example, on brown-out detection).
PSoC™ 4100S Plus operates with a single external supply over the range of either 1.8 V ±5% (externally regulated)
or 1.8 to 5.5 V (internally regulated) and has three different power modes, transitions between which are
managed by the power system. PSoC™ 4100S Plus provides Active, Sleep, and Deep Sleep low-power modes.
All subsystems are operational in Active mode. The CPU subsystem (CPU, flash, and SRAM) is clock-gated off in
Sleep mode, while all peripherals and interrupts are active with instantaneous wake-up on a wake-up event. In
Deep Sleep mode, the high-speed clock and associated circuitry is switched off; wake-up from this mode takes
35 µs. The opamps can remain operational in Deep Sleep mode.
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Based on Arm® Cortex®-M0+ CPU
Functional definition
2.2.2
Clock system
The PSoC™ 4100S Plus clock system is responsible for providing clocks to all subsystems that require clocks and
for switching between different clock sources without glitching. In addition, the clock system ensures that there
are no metastable conditions.
The clock system for the PSoC™ 4100S Plus consists of the IMO, ILO, a 32-kHz Watch Crystal Oscillator (WCO), MHz
ECO and PLL, and provision for an external clock. The WCO block allows locking the IMO to the 32-kHz oscillator.
External Clock
HFCLK
IMO
Divide By
2,4,8
PLL
ECO
WCO
WDC0
16-bits
LFCLK
WDC1
16-bits
ILO
WDC2
32-bits
WDT
Watchdog Counters (WDC)
Watchdog Timer (WDT)
Prescaler
SYSCLK
HFCLK
Integer
Dividers
Fractional
Dividers
Figure 3
12X 16-bit
5X 16.5-bit, 1X 24.5 bit
PSoC™ 4100S Plus MCU clocking architecture
The HFCLK signal can be divided down as shown to generate synchronous clocks for the analog and digital
peripherals. There are 18 clock dividers for the PSoC™ 4100S Plus (six with fractional divide capability, twelve with
integer divide only). The twelve 16-bit integer divide capability allows a lot of flexibility in generating fine-grained
frequency. In addition, there are five 16-bit fractional dividers and one 24-bit fractional divider.
2.2.3
IMO clock source
The IMO is the primary source of internal clocking in the PSoC™ 4100S Plus. It is trimmed during testing to achieve
the specified accuracy.The IMO default frequency is 24 MHz and it can be adjusted from 24 to 48 MHz in steps of
4 MHz. The IMO tolerance with Infineon-provided calibration settings is ±2% over the entire voltage and
temperature range.
2.2.4
ILO clock source
The ILO is a very low power, nominally 40-kHz oscillator, which is primarily used to generate clocks for the
watchdog timer (WDT) and peripheral operation in Deep Sleep mode. ILO-driven counters can be calibrated to
the IMO to improve accuracy. Infineon provides a software component, which does the calibration.
2.2.5
Watch Crystal Oscillator (WCO)
The PSoC™ 4100S Plus clock subsystem also implements a low-frequency (32-kHz watch crystal) oscillator that
can be used for precision timing applications.
2.2.6
External Crystal Oscillators (ECO)
The PSoC™ 4100S Plus also implements a 4 to 33 MHz crystal oscillator.
2.2.7
Watchdog timer and counters
A watchdog timer is implemented in the clock block running from the ILO; this allows watchdog operation during
Deep Sleep and generates a watchdog reset if not serviced before the set timeout occurs. The watchdog reset is
recorded in a Reset Cause register, which is firmware readable. The watchdog counters can be used to implement
a Real-Time clock using the 32-kHz WCO.
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Based on Arm® Cortex®-M0+ CPU
Functional definition
2.2.8
Reset
PSoC™ 4100S Plus can be reset from a variety of sources including a software reset. Reset events are
asynchronous and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky
through reset and allows software to determine the cause of the reset. An XRES pin is reserved for external reset
by asserting it active low. The XRES pin has an internal pull-up resistor that is always enabled.
2.3
Analog blocks
2.3.1
12-bit SAR ADC
The 12-bit, 1-Msps SAR ADC can operate at a maximum clock rate of 18 MHz and requires a minimum of 18 clocks
at that frequency to do a 12-bit conversion.
The Sample-and-Hold (S/H) aperture is programmable allowing the gain bandwidth requirements of the
amplifier driving the SAR inputs, which determine its settling time, to be relaxed if required. It is possible to
provide an external bypass (through a fixed pin location) for the internal reference amplifier.
The SAR is connected to a fixed set of pins through an 8-input sequencer. The sequencer cycles through selected
channels autonomously (sequencer scan) with zero switching overhead (that is, aggregate sampling bandwidth
is equal to 1 Msps whether it is for a single channel or distributed over several channels). The sequencer switching
is effected through a state machine or through firmware driven switching. A feature provided by the sequencer
is buffering of each channel to reduce CPU interrupt service requirements. To accommodate signals with varying
source impedance and frequency, it is possible to have different sample times programmable for each channel.
Also, signal range specification through a pair of range registers (low and high range values) is implemented with
a corresponding out-of-range interrupt if the digitized value exceeds the programmed range; this allows fast
detection of out-of-range values without the necessity of having to wait for a sequencer scan to be completed
and the CPU to read the values and check for out-of-range values in software.
The SAR is not available in Deep Sleep mode as it requires a high-speed clock (up to 18 MHz). The SAR operating
range is 1.71 V to 5.5 V.
AHB System Bus and Programmable Logic
Interconnect
SAR Sequencer
vminus vplus
S A R MU X
S A R MU X Port
(Up to 16 inputs)
Sequencing
and Control
Data and
Status Flags
POS
SARADC
NEG
Reference
Selection
VDDA /2
VDDA
External
Reference and
Bypass
(optional)
VREF
Inputs from other Ports
Figure 4
SAR ADC
2.3.2
Two opamps (Continuous-time block; CTB)
PSoC™ 4100S Plus has two opamps with Comparator modes which allow most common analog functions to be
performed on-chip eliminating external components; PGAs, Voltage Buffers, Filters, Trans-Impedance Amplifiers,
and other functions can be realized, in some cases with external passives. saving power, cost, and space. The
on-chip opamps are designed with enough bandwidth to drive the Sample-and-Hold circuit of the ADC without
requiring external buffering.
2.3.3
Low-power comparators (LPC)
PSoC™ 4100S Plus has a pair of low-power comparators, which can also operate in Deep Sleep modes. This allows
the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during
low-power modes. The comparator outputs are normally synchronized to avoid metastability unless operating
in an asynchronous power mode where the system wake-up circuit is activated by a comparator switch event.
The LPC outputs can be routed to pins.
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Functional definition
2.3.4
Current DACs
PSoC™ 4100S Plus has two IDACs, which can drive any of the pins on the chip. These IDACs have programmable
current ranges.
2.3.5
Analog multiplexed buses
PSoC™ 4100S Plus has two concentric independent buses that go around the periphery of the chip. These buses
(called amux buses) are connected to firmware-programmable analog switches that allow the chip's internal
resources (IDACs, comparator) to connect to any pin on the I/O ports.
2.4
Programmable digital blocks
2.4.1
Smart I/O block
The Smart I/O block is a fabric of switches and LUTs that allows Boolean functions to be performed in signals
being routed to the pins of a GPIO port. The Smart I/O can perform logical operations on input pins to the chip
and on signals going out as outputs.
2.5
Fixed function digital blocks
2.5.1
Timer, Counter, Pulse-Width Modulator (TCPWM) block
The TCPWM block consists of a 16-bit counter with user-programmable period length. There is a capture register
to record the count value at the time of an event (which may be an I/O event), a period register that is used to
either stop or auto-reload the counter when its count is equal to the period register, and compare registers to
generate compare value signals that are used as PWM duty cycle outputs. The block also provides true and
complementary outputs with programmable offset between them to allow use as dead-band programmable
complementary PWM outputs. It also has a Kill input to force outputs to a predetermined state; for example, this
is used in motor drive systems when an over-current state is indicated and the PWM driving the FETs needs to be
shut off immediately with no time for software intervention. Each block also incorporates a Quadrature decoder.
There are eight TCPWM blocks in PSoC™ 4100S Plus.
2.5.2
Serial Communication Block (SCB)
PSoC™ 4100S Plus has five serial communication blocks, which can be programmed to have SPI, I2C, or UART
functionality.
I2C mode: The hardware I2C block implements a full multi-master and slave interface (it is capable of
multi-master arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and has
flexible buffering options to reduce interrupt overhead and latency for the CPU. It also supports EZI2C that
creates a mailbox address range in the memory of PSoC™ 4100S Plus and effectively reduces I2C communication
to reading from and writing to an array in memory. In addition, the block supports an 8-deep FIFO for receive and
transmit which, by increasing the time given for the CPU to read data, greatly reduces the need for clock
stretching caused by the CPU not having read data on time.
The I2C peripheral is compatible with the I2C Standard-mode and Fast-mode devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain
modes.
PSoC™ 4100S Plus is not completely compliant with the I2C spec in the following respect:
GPIO cells are not overvoltage tolerant and, therefore, cannot be hot-swapped or powered up independently of
the rest of the I2C system.
UART mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface
(LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic
UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals
connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame
error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated.
SPI mode: The SPI mode supports full Motorola SPI, TI SSP (adds a start pulse used to synchronize SPI Codecs),
and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO.
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Based on Arm® Cortex®-M0+ CPU
Functional definition
2.5.3
CAN
There is a CAN 2.0B block with support for TT-CAN.
2.6
GPIO
PSoC™ 4100S Plus has up to 54 GPIOs. The GPIO block implements the following:
• Eight drive modes:
- Analog input mode (input and output buffers disabled)
- Input only
- Weak pull-up with strong pull-down
- Strong pull-up with weak pull-down
- Open drain with strong pull-down
- Open drain with strong pull-up
- Strong pull-up with strong pull-down
- Weak pull-up with weak pull-down
• Input threshold select (CMOS or LVTTL).
• Individual control of input and output buffer enabling/disabling in addition to the drive strength modes
• Selectable slew rates for dV/dt related noise control to improve EMI
The pins are organized in logical entities called ports, which are 8-bit in width (less for Ports 5 and 6). During
power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess
turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various
signals that may connect to an I/O pin.
Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the
pins themselves. Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request
(IRQ) and interrupt service routine (ISR) vector associated with it.
2.7
Special function peripherals
2.7.1
CAPSENSE™
CAPSENSE™ is supported in the PSoC™ 4100S Plus through a capacitive sigma-delta (CSD) block that can be
connected to any pins through an analog multiplex bus via analog switches. CAPSENSE™ function can thus be
provided on any available pin or group of pins in a system under software control. A PSoC™ Creator component
is provided for the CAPSENSE™ block to make it easy for the user.
Shield voltage can be driven on another analog multiplex bus to provide water-tolerance capability. Water
tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from attenuating the sensed input. Proximity sensing can also be implemented.
The CAPSENSE™ block has two IDACs, which can be used for general purposes if CAPSENSE™ is not being used
(both IDACs are available in that case) or if CAPSENSE™ is used without water tolerance (one IDAC is available).
The CAPSENSE™ block also provides a 10-bit Slope ADC function which can be used in conjunction with the
CAPSENSE™ function. The CAPSENSE™ block is an advanced, low-noise, programmable block with programmable voltage references and current source ranges for improved sensitivity and flexibility. It can also use an
external reference voltage. It has a full-wave CSD mode that alternates sensing to VDDA and ground to null out
power-supply related noise.
2.7.2
LCD segment drive
PSoC™ 4100S Plus has an LCD controller, which can drive up to 8 commons and up to 30 segments. It uses full
digital methods to drive the LCD segments requiring no generation of internal LCD voltages. The two methods
used are referred to as Digital Correlation and PWM. Digital Correlation pertains to modulating the frequency and
drive levels of the common and segment signals to generate the highest RMS voltage across a segment to light it
up or to keep the RMS signal to zero. This method is good for STN displays but may result in reduced contrast
with TN (cheaper) displays. PWM pertains to driving the panel with PWM signals to effectively use the capacitance
of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This
method results in higher power consumption but can result in better results when driving TN displays.
Datasheet
12
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PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Pinouts
3
Pinouts
The following table provides the pin list for PSoC™ 4100S Plus for the 44-pin TQFP, 48-pin TQFP, and 64-pin TQFP
normal and fine pitch packages.
Table 1
Pinout
64-TQFP
44-TQFP
48-TQFP
Pin
Name
Pin
Name
Pin
Name
39
P0.0
24
P0.0
28
P0.0
40
P0.1
25
P0.1
29
P0.1
41
P0.2
26
P0.2
30
P0.2
42
P0.3
27
P0.3
31
P0.3
43
P0.4
28
P0.4
32
P0.4
44
P0.5
29
P0.5
33
P0.5
45
P0.6
30
P0.6
34
P0.6
46
P0.7
31
P0.7
35
P0.7
47
XRES
32
XRES
36
XRES
48
VCCD
33
VCCD
37
VCCD
34
VDDD
49
VSSD
38
VSSD
50
VDDD
39
VDDD
51
P5.0
52
P5.1
53
P5.2
54
P5.3
55
P5.5
56
VDDA
35
VDDA
40
VDDA
57
VSSA
36
VSSA
41
VSSA
58
P1.0
37
P1.0
42
P1.0
59
P1.1
38
P1.1
43
P1.1
60
P1.2
39
P1.2
44
P1.2
61
P1.3
40
P1.3
45
P1.3
62
P1.4
41
P1.4
46
P1.4
63
P1.5
42
P1.5
47
P1.5
64
P1.6
43
P1.6
48
P1.6
1
P1.7
44
P1.7
1
P1.7
1
VSSD
2
P2.0
2
P2.0
2
P2.0
3
P2.1
3
P2.1
3
P2.1
4
P2.2
4
P2.2
4
P2.2
5
P2.3
5
P2.3
5
P2.3
6
P2.4
6
P2.4
6
P2.4
7
P2.5
7
P2.5
7
P2.5
Datasheet
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PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Pinouts
Table 1
Pinout (continued)
64-TQFP
44-TQFP
48-TQFP
Pin
Name
Pin
Name
Pin
Name
8
P2.6
8
P2.6
8
P2.6
9
P2.7
9
P2.7
9
P2.7
10
VSSD
11
NC
12
P6.0
10
P6.0
13
P6.1
14
P6.2
15
P6.4
16
P6.5
17
VSSD
10
VSSD
11
NC
18
P3.0
11
P3.0
12
P3.0
19
P3.1
12
P3.1
13
P3.1
20
P3.2
13
P3.2
14
P3.2
15
NC
21
P3.3
14
P3.3
16
P3.3
22
P3.4
15
P3.4
17
P3.4
23
P3.5
16
P3.5
18
P3.5
24
P3.6
17
P3.6
19
P3.6
25
P3.7
18
P3.7
20
P3.7
26
VDDD
19
VDDD
21
VDDD
27
P4.0
20
P4.0
22
P4.0
28
P4.1
21
P4.1
23
P4.1
29
P4.2
22
P4.2
24
P4.2
30
P4.3
23
P4.3
25
P4.3
31
P4.4
32
P4.5
33
P4.6
34
P4.7
35
P5.6
36
P5.7
37
P7.0
26
P7.0
38
P7.1
27
P7.1
Datasheet
14
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PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Pinouts
Descriptions of the power pins are as follows:
VDDD: Power supply for the digital section.
VDDA: Power supply for the analog section.
VSSD, VSSA: Ground pins for the digital and analog sections respectively.
VCCD: Regulated digital supply (1.8 V ±5%)
VDD: Power supply to all sections of the chip
VSS: Ground for all sections of the chip
GPIOs by package:
Number
Datasheet
64 TQFP
44 TQFP
48 TQFP
54
37
38
15
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Table 2
Alternate pin functions
Port/pin
Analog
P0.0
Smart I/O
ACT #0
ACT #1
ACT #3
DS #2
DS #3
lpcomp.in_p[0]
tcpwm.tr_in[0]
scb[2].uart_cts:0
scb[2].i2c_scl:0
scb[0].spi_select1:0
P0.1
lpcomp.in_n[0]
tcpwm.tr_in[1]
scb[2].uart_rts:0
scb[2].i2c_sda:0
scb[0].spi_select2:0
P0.2
lpcomp.in_p[1]
scb[0].spi_select3:0
P0.3
lpcomp.in_n[1]
scb[2].spi_select0:1
P0.4
wco.wco_in
scb[1].uart_rx:0
scb[2].uart_rx:0
scb[1].i2c_scl:0
scb[1].spi_mosi:1
P0.5
wco.wco_out
scb[1].uart_tx:0
scb[2].uart_tx:0
scb[1].i2c_sda:0
scb[1].spi_miso:1
P0.6
exco.eco_in
srss.ext_clk:0
scb[1].uart_cts:
0
scb[2].uart_tx:1
P0.7
exco.eco_out
tcpwm.line[0]:3
scb[1].uart_rts:
0
scb[1].spi_clk:1
scb[1].spi_select0:1
16
P5.0
tcpwm.line[4]:2
scb[2].uart_rx:1
scb[2].i2c_scl:1
scb[2].spi_mosi:0
P5.1
tcpwm.line_compl[4]:2
scb[2].uart_tx:2
scb[2].i2c_sda:1
scb[2].spi_miso:0
P5.2
tcpwm.line[5]:2
scb[2].uart_cts:1
lpcomp.comp[0]:2
scb[2].spi_clk:0
P5.3
tcpwm.line_compl[5]:2
scb[2].uart_rts:1
lpcomp.comp[1]:0
scb[2].spi_select0:0
P5.4
tcpwm.line[6]:2
scb[2].spi_select1:0
P5.5
tcpwm.line_compl[6]:2
scb[2].spi_select2:0
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P1.0
ctb0_oa0+
SmartIo[2].io[0]
tcpwm.line[2]:1
scb[0].uart_rx:1
scb[0].i2c_scl:0
scb[0].spi_mosi:1
P1.1
ctb0_oa0-
SmartIo[2].io[1]
tcpwm.line_compl[2]:1
scb[0].uart_tx:1
scb[0].i2c_sda:0
scb[0].spi_miso:1
P1.2
ctb0_oa0_out
SmartIo[2].io[2]
tcpwm.line[3]:1
scb[0].uart_cts:
1
tcpwm.tr_in[2]
scb[2].i2c_scl:2
scb[0].spi_clk:1
P1.3
ctb0_oa1_out
SmartIo[2].io[3]
tcpwm.line_compl[3]:1
scb[0].uart_rts:
1
tcpwm.tr_in[3]
scb[2].i2c_sda:2
scb[0].spi_select0:1
P1.4
ctb0_oa1-
SmartIo[2].io[4]
tcpwm.line[6]:1
scb[3].i2c_scl:0
scb[0].spi_select1:1
PSoC™ 4 MCU: PSoC™ 4100S Plus
Each Port pin has can be assigned to one of multiple functions; it can, for example, be an analog I/O, a digital peripheral function, an LCD pin, or a
CAPSENSE™ pin. The pin assignments are shown in the following table.
Based on Arm® Cortex®-M0+ CPU
Alternate pin functions
Pinouts
Datasheet
3.1
Smart I/O
ACT #0
ACT #1
P1.5
ctb0_oa1+
SmartIo[2].io[5]
tcpwm.line_compl[6]:1
P1.6
ctb0_oa0+
SmartIo[2].io[6]
tcpwm.line[7]:1
scb[0].spi_select3:1
P1.7
ctb0_oa1+
sar_ext_vref0
sar_ext_vref1
SmartIo[2].io[7]
tcpwm.line_compl[7]:1
scb[2].spi_clk:1
P2.0
sarmux[0]
SmartIo[0].io[0]
tcpwm.line[4]:0
P2.1
sarmux[1]
SmartIo[0].io[1]
tcpwm.line_compl[4]:0
P2.2
sarmux[2]
SmartIo[0].io[2]
tcpwm.line[5]:1
scb[1].spi_clk:2
P2.3
sarmux[3]
SmartIo[0].io[3]
tcpwm.line_compl[5]:1
scb[1].spi_select0:2
P2.4
sarmux[4]
SmartIo[0].io[4]
tcpwm.line[0]:1
scb[3].uart_rx:1
scb[1].spi_select1:1
P2.5
sarmux[5]
SmartIo[0].io[5]
tcpwm.line_compl[0]:1
scb[3].uart_tx:1
scb[1].spi_select2:1
P2.6
sarmux[6]
SmartIo[0].io[6]
tcpwm.line[1]:1
scb[3].uart_cts:
1
scb[1].spi_select3:1
P2.7
sarmux[7]
SmartIo[0].io[7]
tcpwm.line_compl[1]:1
scb[3].uart_rts:
1
P6.0
tcpwm.line[4]:1
scb[3].uart_rx:0
P6.1
tcpwm.line_compl[4]:1
P6.2
csd.comp
ACT #3
DS #2
DS #3
scb[3].i2c_sda:0
scb[0].spi_select2:1
tcpwm.tr_in[4]
scb[1].i2c_scl:1
scb[1].spi_mosi:2
tcpwm.tr_in[5]
scb[1].i2c_sda:1
scb[1].spi_miso:2
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lpcomp.comp[0]:0
scb[2].spi_mosi:1
can.can_tx_enb_n:0
scb[3].i2c_scl:1
scb[3].spi_mosi:0
scb[3].uart_tx:0
can.can_rx:0
scb[3].i2c_sda:1
scb[3].spi_miso:0
tcpwm.line[5]:0
scb[3].uart_cts:
0
can.can_tx:0
P6.3
tcpwm.line_compl[5]:0
scb[3].uart_rts:
0
P6.4
tcpwm.line[6]:0
scb[4].i2c_scl
scb[3].spi_select1:0
P6.5
tcpwm.line_compl[6]:0
scb[4].i2c_sda
scb[3].spi_select2:0
scb[1].i2c_scl:2
scb[1].spi_mosi:0
P3.0
SmartIo[1].io[0]
tcpwm.line[0]:0
scb[1].uart_rx:1
scb[3].spi_clk:0
scb[3].spi_select0:0
PSoC™ 4 MCU: PSoC™ 4100S Plus
Analog
17
Port/pin
Based on Arm® Cortex®-M0+ CPU
Alternate pin functions (continued)
Pinouts
Datasheet
Table 2
Smart I/O
ACT #0
ACT #1
P3.1
SmartIo[1].io[1]
tcpwm.line_compl[0]:0
P3.2
SmartIo[1].io[2]
P3.3
ACT #3
DS #2
DS #3
scb[1].uart_tx:1
scb[1].i2c_sda:2
scb[1].spi_miso:0
tcpwm.line[1]:0
scb[1].uart_cts:
1
cpuss.swd_data
scb[1].spi_clk:0
SmartIo[1].io[3]
tcpwm.line_compl[1]:0
scb[1].uart_rts:
1
cpuss.swd_clk
scb[1].spi_select0:0
P3.4
SmartIo[1].io[4]
tcpwm.line[2]:0
P3.5
SmartIo[1].io[5]
tcpwm.line_compl[2]:0
P3.6
SmartIo[1].io[6]
tcpwm.line[3]:0
scb[4].spi_select3
scb[1].spi_select3:0
P3.7
SmartIo[1].io[7]
tcpwm.line_compl[3]:0
lpcomp.comp[1]:1
scb[2].spi_miso:1
tcpwm.tr_in[6]
scb[1].spi_select1:0
scb[1].spi_select2:0
18
P4.0
csd.vref_ext
scb[0].uart_rx:0
can.can_rx:1
scb[0].i2c_scl:1
scb[0].spi_mosi:0
P4.1
csd.cshield
scb[0].uart_tx:0
can.can_tx:1
scb[0].i2c_sda:1
scb[0].spi_miso:0
P4.2
csd.cmod
scb[0].uart_cts:
0
can.can_tx_enb_n:1
lpcomp.comp[0]:1
scb[0].spi_clk:0
P4.3
csd.csh_tank
scb[0].uart_rts:
0
lpcomp.comp[1]:2
scb[0].spi_select0:0
P4.4
scb[4].uart_rx
scb[4].spi_mosi
scb[0].spi_select1:2
P4.5
scb[4].uart_tx
scb[4].spi_miso
scb[0].spi_select2:2
P4.6
scb[4].uart_cts
scb[4].spi_clk
scb[0].spi_select3:2
P4.7
scb[4].uart_rts
scb[4].spi_select0
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P5.6
tcpwm.line[7]:0
scb[4].spi_select1
scb[2].spi_select3:0
P5.7
tcpwm.line_compl[7]:0
scb[4].spi_select2
P7.0
tcpwm.line[0]:2
scb[3].uart_rx:2
scb[3].i2c_scl:2
scb[3].spi_mosi:1
P7.1
tcpwm.line_compl[0]:2
scb[3].uart_tx:2
scb[3].i2c_sda:2
scb[3].spi_miso:1
P7.2
tcpwm.line[1]:2
scb[3].uart_cts:
2
scb[3].spi_clk:1
PSoC™ 4 MCU: PSoC™ 4100S Plus
Analog
Based on Arm® Cortex®-M0+ CPU
Port/pin
Alternate pin functions (continued)
Pinouts
Datasheet
Table 2
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Power
4
Power
The following power system diagram shows the set of power supply pins as implemented for the
PSoC™ 4100S Plus. The system has one regulator in Active mode for the digital circuitry. There is no analog
regulator; the analog circuits run directly from the VDD input.
VDDA
VDDD
VDDA
VSSA
VDDD
Analog
Domain
Digital
Domain
1.8 Volt
Regulator
Figure 5
VSSD
VCCD
Power supply connections
There are two distinct modes of operation. In Mode 1, the supply voltage range is 1.8 V to 5.5 V (unregulated
externally; internal regulator operational). In Mode 2, the supply range is1.8 V ±5% (externally regulated; 1.71 to
1.89, internal regulator bypassed).
4.1
Mode 1: 1.8 V to 5.5 V external supply
In this mode, PSoC™ 4100S Plus is powered by an external power supply that can be anywhere in the range of 1.8
to 5.5 V. This range is also designed for battery-powered operation. For example, the chip can be powered from
a battery system that starts at 3.5 V and works down to 1.8 V. In this mode, the internal regulator of PSoC™ 4100S
Plus supplies the internal logic and its output is connected to the VCCD pin. The VCCD pin must be bypassed to
ground via an external capacitor (0.1 µF; X5R ceramic or better) and must not be connected to anything else.
4.2
Mode 2: 1.8 V ±5% external supply
In this mode, PSoC™ 4100S Plus is powered by an external power supply that must be within the range of 1.71 to
1.89 V; note that this range needs to include the power supply ripple too. In this mode, the VDD and VCCD pins
are shorted together and bypassed. The internal regulator can be disabled in the firmware.
Bypass capacitors must be used from VDDD to ground. The typical practice for systems in this frequency range is
to use a capacitor in the 1-µF range, in parallel with a smaller capacitor (0.1 µF, for example). Note that these are
simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the bypass
capacitor parasitic should be simulated to design and obtain optimal bypassing.
An example of a bypass scheme is shown in the following diagram.
Datasheet
19
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PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Power
Power supply bypass connections example
1.8 V to 5.5 V
1.8 V to 5.5 V
VDDA
VDDD
1 µF
1 µF
0.1 µF
0.1 µF
VCCD
PSoC™ 4100S Plus
0.1 µF
VSS
Figure 6
Datasheet
External supply range from 1.8 V to 5.5 V with internal regulator active
20
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PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5
Electrical specifications
5.1
Absolute maximum ratings
Table 3
Absolute maximum ratings[1]
Spec ID#
Parameter
Description
Min
Typ
Max
Units Details/conditions
SID1
VDDD_ABS
Digital supply relative to VSS
–0.5
–
6
SID2
VCCD_ABS
Direct digital core voltage input
relative to VSS
–0.5
–
1.95
SID3
VGPIO_ABS
GPIO voltage
–0.5
–
VDD+0.5
–
SID4
IGPIO_ABS
Maximum current per GPIO
–25
–
25
–
SID5
IGPIO_injection
GPIO injection current, Max for VIH
–0.5
> VDDD, and Min for VIL < VSS
–
0.5
BID44
ESD_HBM
Electrostatic discharge human
body model
2200
–
–
BID45
ESD_CDM
Electrostatic discharge charged
device model
500
–
–
BID46
LU
Pin current for latch-up
–140
–
140
5.2
–
V
mA
–
Current injected per
pin
–
V
–
mA
–
Device level specifications
All specifications are valid for –40°C TA 105°C and TJ 125°C, except where noted. Specifications are valid for
1.71 V to 5.5 V, except where noted.
Table 4
DC specifications
Typical values measured at VDD = 3.3 V and 25°C.
Spec ID#
Parameter
Description
Min
Typ
Max
Units Details/conditions
Internally regulated
supply
SID53
VDD
Power supply input voltage
1.8
–
5.5
SID255
VDD
Power supply input voltage (VCCD
= VDDD = VDDA)
1.71
–
1.89
SID54
VCCD
Output voltage (for core logic)
–
1.8
–
SID55
CEFC
External regulator voltage (VCCD)
bypass
–
0.1
–
CEXC
Power supply bypass capacitor
–
SID56
V
–
µF
1
Internally
unregulated supply
–
X5R ceramic or
better
X5R ceramic or
better
Active mode, VDD = 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25°C.
SID10
IDD5
Execute from flash; CPU at 6 MHz
–
1.8
2.4
SID16
IDD8
Execute from flash; CPU at 24 MHz
–
3.0
4.6
SID19
IDD11
Execute from flash; CPU at 48 MHz
–
5.4
7.1
mA
Note
1. Usage above the absolute maximum conditions listed in Table 3 may cause permanent damage to the device. Exposure to absolute
maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150°C in
compliance with JEDEC Standard JESD22-A103, high temperature storage life. When used below Absolute Maximum conditions but
above normal operating conditions, the device may not operate to specification.
Datasheet
21
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Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 4
DC specifications (continued)
Typical values measured at VDD = 3.3 V and 25°C.
Spec ID#
Parameter
Description
Min
Typ
Max
Units Details/conditions
Sleep mode, VDDD = 1.8 V to 5.5 V (Regulator on)
SID22
IDD17
I2C wakeup WDT, and
Comparators on
–
1.1
1.8
SID25
IDD20
I2C wakeup, WDT, and
Comparators on
–
1.5
2.1
mA
6 MHZ
12 MHZ
Sleep mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed)
SID28
IDD23
I2C wakeup, WDT, and
Comparators on
–
1.1
1.8
mA
6 MHZ
SID28A
IDD23A
I2C wakeup, WDT, and
Comparators on
–
1.5
2.1
mA
12 MHZ
Deep Sleep mode, VDD = 1.8 V to 3.6 V (Regulator on)
SID30
IDD25
I2C wakeup and WDT on; T = –40°C
to 60°C
–
2.5
40
µA
T = –40°C to 60°C
SID31
IDD26
I2C wakeup and WDT on
–
2.5
125
µA
Max is at 3.6 V and
85°C
2.5
40
µA
T = –40°C to 60°C
2.5
125
µA
Max is at 5.5 V and
85°C
µA
T = –40°C to 60°C
Deep Sleep mode, VDD = 3.6 V to 5.5 V (Regulator on)
SID33
IDD28
I2C wakeup and WDT on; T = –40°C
to 60°C
–
SID34
IDD29
I2C wakeup and WDT on
–
Deep Sleep mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed)
SID36
IDD31
I2C wakeup and WDT on; T = –40°C
to 60°C
–
SID37
IDD32
I2C wakeup and WDT on
Supply current while XRES
asserted
2.5
60
–
2.5
180
µA
Max is at 1.89 V and
85°C
–
2
5
mA
–
Min
Typ
Max
DC
–
48
XRES current
SID307
Table 5
IDD_XR
AC specifications
Spec ID# Parameter
SID48
SID49[2]
SID50[2]
Description
FCPU
CPU frequency
TSLEEP
Wakeup from Sleep mode
–
0
–
TDEEPSLEEP
Wakeup from Deep Sleep mode
–
35
–
Units Details/conditions
MHz 1.71 VDD 5.5
µs
Note
2. Guaranteed by characterization.
Datasheet
22
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.2.1
GPIO
Table 6
GPIO DC Specifications
Spec ID# Parameter
[3]
Description
Min
Typ
Max
Units Details/conditions
Input voltage high threshold 0.7 VDDD
–
–
CMOS Input
–
–
0.3
VDDD
CMOS Input
SID57
VIH
SID58
VIL
Input voltage low threshold
SID241
VIH[3]
LVTTL input, VDDD < 2.7 V
0.7 VDDD
–
–
–
SID242
VIL
LVTTL input, VDDD < 2.7 V
–
–
–
SID243
VIH[3]
0.3
VDDD
LVTTL input, VDDD 2.7 V
2.0
–
–
–
SID244
VIL
LVTTL input, VDDD 2.7 V
–
–
0.8
SID59
VOH
Output voltage high level
VDDD –0.6
–
–
SID60
VOH
Output voltage high level
VDDD –0.5
–
–
IOH = 1 mA at 1.8 V
VDDD
SID61
VOL
Output voltage low level
–
–
0.6
IOL = 4 mA at 1.8 V
VDDD
SID62
VOL
Output voltage low level
–
–
0.6
IOL = 10 mA at 3 V
VDDD
SID62A
VOL
Output voltage low level
–
–
0.4
IOL = 3 mA at 3 V VDDD
SID63
RPULLUP
Pull-up resistor
3.5
5.6
8.5
SID64
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
SID65
IIL
Input leakage current
(absolute value)
–
–
2
nA
SID66
CIN
Input capacitance
–
–
7
pF
SID67
VHYSTTL
Input hysteresis LVTTL
25
40
–
SID68[4]
VHYSCMOS
Input hysteresis CMOS
0.05 ×
VDDD
–
–
200
–
–
Current through protection
diode to VDD/VSS
–
–
100
µA
–
Maximum total source or
sink chip current
–
–
200
mA
–
[4]
SID68A[4] VHYSCMOS5V5 Input hysteresis CMOS
SID69[4]
IDIODE
SID69A[4] ITOT_GPIO
V
kΩ
–
IOH = 4 mA at 3 V
VDDD
–
–
25°C, VDDD = 3.0 V
–
VDDD 2.7 V
mV
VDD < 4.5 V
VDD > 4.5 V
Notes
3. VIH must not exceed VDDD + 0.2 V.
4. Guaranteed by characterization.
Datasheet
23
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 7
GPIO AC specifications
(Guaranteed by characterization)
Spec ID# Parameter
SID70
Description
Min
Typ
Max
2
–
12
Units
Details/Conditions
3.3 V VDDD,
Cload = 25 pF
TRISEF
Rise time in fast strong mode
SID71
TFALLF
Fall time in fast strong mode
2
–
12
SID72
TRISES
Rise time in slow strong mode
10
–
60
–
3.3 V VDDD,
Cload = 25 pF
SID73
TFALLS
Fall time in slow strong mode
10
–
60
–
3.3 V VDDD,
Cload = 25 pF
SID74
FGPIOUT1
GPIO FOUT; 3.3 V VDDD 5.5 V
Fast strong mode
–
–
33
90/10%, 25 pF load,
60/40 duty cycle
SID75
FGPIOUT2
GPIO FOUT; 1.71 VVDDD3.3 V
Fast strong mode
–
–
16.7
90/10%, 25 pF load,
60/40 duty cycle
SID76
FGPIOUT3
GPIO FOUT; 3.3 V VDDD 5.5 V
Slow strong mode
–
–
7
SID245
FGPIOUT4
GPIO FOUT; 1.71 V VDDD 3.3 V
Slow strong mode.
–
–
3.5
90/10%, 25 pF load,
60/40 duty cycle
SID246
FGPIOIN
GPIO input operating
frequency;
1.71 V VDDD 5.5 V
–
–
48
90/10% VIO
Min
Typ
Max
ns
5.2.2
XRES
Table 8
XRES DC specifications
Spec ID# Parameter
Description
MHz
Units
3.3 V VDDD,
Cload = 25 pF
90/10%, 25 pF load,
60/40 duty cycle
Details/conditions
SID77
VIH
Input voltage high threshold
0.7 ×
VDDD
–
–
SID78
VIL
Input voltage low threshold
–
–
0.3
VDDD
SID79
RPULLUP
Pull-up resistor
–
60
–
kΩ
–
SID80
CIN
Input capacitance
–
–
7
pF
–
SID81[5]
VHYSXRES
Input voltage hysteresis
–
100
–
mV
SID82
IDIODE
Current through protection
diode to VDD/VSS
–
–
100
µA
Min
Typ
Max
Units
Details/conditions
1
–
–
µs
–
–
–
2.7
ms
–
Table 9
CMOS Input
Typical hysteresis is
200 mV for VDD > 4.5 V
XRES AC specifications
Spec ID# Parameter
SID83[5]
V
Description
TRESETWIDTH Reset pulse width
BID194[5] TRESETWAKE
Wake-up time from reset
release
Note
5. Guaranteed by characterization.
Datasheet
24
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.3
Analog peripherals
5.3.1
CTBm opamp
Table 10
CTBm opamp specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/conditions
µA
–
IDD
Opamp block current,
External load
SID269
IDD_HI
power = hi
–
1100 1850
SID270
IDD_MED
power = med
–
550
950
–
SID271
IDD_LOW
power = lo
–
150
350
–
GBW
Load = 20 pF, 0.1 mA
VDDA = 2.7 V
SID272
GBW_HI
power = hi
6
–
–
SID273
GBW_MED
power = med
3
–
–
Input and output are
0.2 V to VDDA-0.2 V
SID274
GBW_LO
power = lo
–
1
–
Input and output are
0.2 V to VDDA-0.2 V
IOUT_MAX
VDDA = 2.7 V, 500 mV from rail
SID275
IOUT_MAX_HI
power = hi
10
–
–
SID276
IOUT_MAX_MID
power = med
10
–
–
Output is 0.5 V to
VDDA -0.5 V
SID277
IOUT_MAX_LO
power = lo
–
5
–
Output is 0.5 V to
VDDA -0.5 V
IOUT
VDDA = 1.71 V, 500 mV from rail
SID278
IOUT_MAX_HI
power = hi
4
–
–
SID279
IOUT_MAX_MID
power = med
4
–
–
Output is 0.5 V to
VDDA-0.5 V
SID280
IOUT_MAX_LO
power = lo
–
2
–
Output is 0.5 V to
VDDA-0.5 V
IDD_Int
Opamp block current Internal
Load
SID269_I
IDD_HI_Int
power = hi
–
1500 1700
SID270_I
IDD_MED_Int
power = med
–
700
900
–
SID271_I
IDD_LOW_Int
power = lo
–
–
–
–
GBW
VDDA = 2.7 V
–
–
–
–
GBW_HI_Int
power = hi
8
–
–
MHz
V
SID272_I
MHz
mA
mA
µA
Input and output are
0.2 V to VDDA-0.2 V
Output is 0.5 V to
VDDA -0.5 V
Output is 0.5 V to
VDDA -0.5 V
–
Output is 0.25 V to
VDDA-0.25 V
General opamp specs for both
internal and external modes
SID281
VIN
Charge-pump on, VDDA = 2.7 V –0.05
–
VDDA0.2
SID282
VCM
Charge-pump on, VDDA = 2.7 V –0.05
–
VDDA0.2
Datasheet
25
–
–
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 10
Spec ID#
CTBm opamp specifications (continued)
Parameter
Description
Min
Typ
Max
Units
V
Details/conditions
VOUT
VDDA = 2.7 V
SID283
VOUT_1
power=hi, Iload=10 mA
0.5
–
VDDA
-0.5
SID284
VOUT_2
power=hi, Iload=1 mA
0.2
–
VDDA
-0.2
–
SID285
VOUT_3
power=med, Iload=1 mA
0.2
–
VDDA
-0.2
–
SID286
VOUT_4
power=lo, Iload=0.1 mA
0.2
–
VDDA
-0.2
–
SID288
VOS_TR
Offset voltage, trimmed
–1.0
0.5
1.0
SID288A
VOS_TR
Offset voltage, trimmed
–
1
–
Medium mode, input
0 V to VDDA-0.2 V
SID288B
VOS_TR
Offset voltage, trimmed
–
2
–
Low mode, input 0 V
to VDDA-0.2 V
SID290
VOS_DR_TR
Offset voltage drift, trimmed
–10
3
10
µV/°C
High mode
SID290A
VOS_DR_TR
Offset voltage drift, trimmed
–
10
–
µV/°C
Medium mode
SID290B
VOS_DR_TR
Offset voltage drift, trimmed
–
10
–
SID291
CMRR
DC
70
80
–
SID292
PSRR
At 1 kHz, 10-mV ripple
70
85
–
mV
–
High mode, input 0 V
to VDDA-0.2 V
Low mode
dB
Input is 0 V to
VDDA-0.2 V, Output is
0.2 V to VDDA-0.2 V
VDDD = 3.6 V,
high-power mode,
input is 0.2 V to
VDDA-0.2 V
Noise
SID294
VN2
Input-referred, 1 kHz, power =
Hi
–
72
–
nV/rtHz Input and output are
at 0.2 V to VDDA-0.2 V
SID295
VN3
Input-referred, 10 kHz, power
= Hi
–
28
–
Input and output are
at 0.2 V to VDDA-0.2 V
SID296
VN4
Input-referred, 100 kHz,
power = Hi
–
15
–
Input and output are
at 0.2 V to VDDA-0.2 V
SID297
CLOAD
Stable up to max. load. Performance specs at 50 pF.
–
–
125
pF
–
SID298
SLEW_RATE
Cload = 50 pF, Power = High,
VDDA = 2.7 V
6
–
–
V/µs
–
SID299
T_OP_WAKE
From disable to enable, no
external RC dominating
–
–
25
µs
–
SID299A
OL_GAIN
Open Loop Gain
–
90
–
dB
COMP_MODE Comparator mode; 50 mV
drive, Trise=Tfall (approx.)
Datasheet
26
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 10
Spec ID#
CTBm opamp specifications (continued)
Parameter
Description
Min
Typ
Max
Units
ns
Details/conditions
SID300
TPD1
Response time; power = hi
–
150
–
SID301
TPD2
Response time; power = med
–
500
–
Input is 0.2 V to
VDDA-0.2 V
SID302
TPD3
Response time; power = lo
–
2500
–
Input is 0.2 V to
VDDA-0.2 V
SID303
VHYST_OP
Hysteresis
–
10
–
mV
–
SID304
WUP_CTB
Wake-up time from Enabled
to Usable
–
–
25
µs
–
Deep Sleep
mode
Mode 2 is lowest current
range. Mode 1 has higher
GBW.
SID_DS_1
IDD_HI_M1
Mode 1, High current
–
1400
–
µA
25°C
SID_DS_2
IDD_MED_M1
Mode 1, Medium current
–
700
–
25°C
SID_DS_3
IDD_LOW_M1
Mode 1, Low current
–
200
–
25°C
SID_DS_4
IDD_HI_M2
Mode 2, High current
–
120
–
25°C
SID_DS_5
IDD_MED_M2
Mode 2, Medium current
–
60
–
25°C
SID_DS_6
IDD_LOW_M2
Mode 2, Low current
–
15
–
25°C
SID_DS_7
GBW_HI_M1
Mode 1, High current
–
4
–
SID_DS_8
GBW_MED_M1
Mode 1, Medium current
–
2
–
20-pF load, no DC
load 0.2 V to
VDDA-0.2 V
SID_DS_9
GBW_LOW_M1
Mode 1, Low current
–
0.5
–
20-pF load, no DC
load 0.2 V to
VDDA-0.2 V
SID_DS_10 GBW_HI_M2
Mode 2, High current
–
0.5
–
20-pF load, no DC
load 0.2 V to
VDDA-0.2 V
SID_DS_11 GBW_MED_M2
Mode 2, Medium current
–
0.2
–
20-pF load, no DC
load 0.2 V to
VDDA-0.2 V
SID_DS_12 GBW_Low_M2
Mode 2, Low current
–
0.1
–
20-pF load, no DC
load 0.2 V to
VDDA-0.2 V
Datasheet
27
MHz
Input is 0.2 V to
VDDA-0.2 V
20-pF load, no DC
load 0.2 V to
VDDA-0.2 V
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 10
Spec ID#
CTBm opamp specifications (continued)
Parameter
Description
Min
Typ
Max
Units
Details/conditions
mV
With trim 25°C, 0.2 V
to VDDA-0.2 V
SID_DS_13 VOS_HI_M1
Mode 1, High current
–
5
–
SID_DS_14 VOS_MED_M1
Mode 1, Medium current
–
5
–
With trim 25°C, 0.2 V
to VDDA-0.2 V
SID_DS_15 VOS_LOW_M1
Mode 1, Low current
–
5
–
With trim 25°C, 0.2 V
to VDDA-0.2 V
SID_DS_16 VOS_HI_M2
Mode 2, High current
–
5
–
With trim 25°C, 0.2V
to VDDA-0.2 V
SID_DS_17 VOS_MED_M2
Mode 2, Medium current
–
5
–
With trim 25°C, 0.2 V
to VDDA-0.2 V
SID_DS_18 VOS_LOW_M2
Mode 2, Low current
–
5
–
With trim 25°C, 0.2 V
to VDDA-0.2 V
SID_DS_19 IOUT_HI_M1
Mode 1, High current
–
10
–
SID_DS_20 IOUT_MED_M1
Mode 1, Medium current
–
10
–
Output is 0.5 V to
VDDA-0.5 V
SID_DS_21 IOUT_LOW_M1
Mode 1, Low current
–
4
–
Output is 0.5 V to
VDDA-0.5 V
SID_DS_22 IOUT_HI_M2
Mode 2, High current
–
1
–
SID_DS_23 IOUT_MED_M2
Mode 2, Medium current
–
1
–
SID_DS_24 IOUT_LOW_M2
Mode 2, Low current
–
0.5
–
Datasheet
28
mA
Output is 0.5 V to
VDDA-0.5 V
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.3.2
Comparator
Table 11
Comparator DC specifications
Spec ID# Parameter
Description
Min Typ
Input offset voltage, Factory trim –
–
SID84
VOFFSET1
Max
±10
Units
mV
SID85
VOFFSET2
Input offset voltage, Custom trim
–
–
±4
SID86
VHYST
Hysteresis when enabled
–
10
35
SID87
VICM1
Input common mode voltage in
normal mode
0
–
VDDD-0.1
SID247
VICM2
Input common mode voltage in
low power mode
0
–
VDDD
SID247A VICM3
Input common mode voltage in
ultra low power mode
0
–
VDDD-1.15
SID88
CMRR
Common mode rejection ratio
50
–
–
SID88A
CMRR
Common mode rejection ratio
42
–
–
SID89
ICMP1
Block current, normal mode
–
–
400
SID248
ICMP2
Block current, low power mode
–
–
100
SID259
ICMP3
Block current in ultra low-power
mode
–
–
6
SID90
ZCMP
DC Input impedance of
comparator
35
–
–
MΩ
Max
Units
Table 12
TRESP1
Description
Min Typ
Response time, normal mode, 50
– 38
mV overdrive
SID258
TRESP2
Response time, low power mode,
50 mV overdrive
SID92
TRESP3
Response time, ultra-low power
mode, 200 mV overdrive
5.3.3
Temperature sensor
Table 13
Temperature sensor specifications
Spec ID# Parameter
SID93
Modes 1 and 2
V
VDDD ≥ 2.2 V at –40°C
dB
VDDD ≥ 2.7V
VDDD ≤ 2.7V
µA
VDDD ≥ 2.2 V at –40°C
Comparator AC specifications
Spec ID# Parameter
SID91
Details/conditions
TSENSACC
Description
110
ns
–
70
200
–
2.3
15
µs
VDDD ≥ 2.2 V at –40°C
Max
Units
Details/conditions
5
°C
Min Typ
Temperature sensor accuracy
Details/conditions
–5
±1
–40 to +85°C
Note
6. Guaranteed by characterization.
Datasheet
29
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.3.4
SAR ADC
Table 14
SAR ADC specifications
Spec ID# Parameter
Description
Min
Typ
Max
Units
–
–
12
bits
Details/
conditions
SAR ADC DC specifications
SID94
A_RES
Resolution
SID95
A_CHNLS_S Number of channels - single ended
–
–
16
SID96
A-CHNKS_D Number of channels - differential
–
–
4
Diff inputs use
neighboring I/O
SID97
A-MONO
Monotonicity
–
–
–
Yes
SID98
A_GAINERR
Gain error
–
–
±0.1
%
With external
reference
SID99
A_OFFSET
Input offset voltage
–
–
2
mV
Measured with
1-V reference
SID100
A_ISAR
Current consumption
–
–
1
mA
SID101
A_VINS
Input voltage range - single ended
VSS
–
VDDA
V
SID102
A_VIND
Input voltage range - differential
VSS
–
VDDA
V
SID103
A_INRES
Input resistance
–
–
2.2
KΩ
SID104
A_INCAP
Input capacitance
–
–
10
pF
SID260
VREFSAR
Trimmed internal reference to SAR
1.188
1.2
1.212
V
SAR ADC AC specifications
SID106
A_PSRR
Power supply rejection ratio
70
–
–
dB
SID107
A_CMRR
Common mode rejection ratio
66
–
–
dB
SID108
A_SAMP
Sample rate
–
–
1
Msps
SID109
A_SNR
Signal-to-noise and distortion ratio
(SINAD)
65
–
–
dB
SID110
A_BW
Input bandwidth without aliasing
–
–
A_samp/2
kHz
SID111
A_INL
Integral non linearity. VDD = 1.71 to
5.5, 1 Msps
–1.7
–
2
LSB
VREF = 1 to VDD
SID111A A_INL
Integral non linearity. VDDD = 1.71 to
3.6, 1 Msps
–1.5
–
1.7
LSB
VREF = 1.71 to
VDD
SID111B A_INL
Integral non linearity. VDD = 1.71 to
5.5, 500 ksps
–1.5
–
1.7
LSB
VREF = 1 to VDD
SID112
A_DNL
Differential non linearity. VDD = 1.71
to 5.5, 1 Msps
–1
–
2.2
LSB
VREF = 1 to VDD
SID112A A_DNL
Differential non linearity. VDD = 1.71
to 3.6, 1 Msps
–1
–
2
LSB
VREF = 1.71 to
VDD
SID112B A_DNL
Differential non linearity. VDD = 1.71
to 5.5, 500 ksps
–1
–
2.2
LSB
VREF = 1 to VDD
SID113
A_THD
Total harmonic distortion
–
–
–65
dB
Fin = 10 kHz
SID261
FSARINTREF SAR operating speed without
external reference bypass
–
–
100
Datasheet
30
Measured at 1 V
FIN = 10 kHz
ksps 12-bit
resolution
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.3.5
CSD and IDAC
Table 15
CSD and IDAC specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/conditions
SYS.PER#3
VDD_RIPPLE
Max allowed ripple on
power supply, DC to
10 MHz
–
–
±50
mV
VDD > 2 V (with ripple),
25°C TA, Sensitivity =
0.1 pF
SYS.PER#16
VDD_RIPPLE_1.8
Max allowed ripple on
power supply, DC to
10 MHz
–
–
±25
mV
VDD > 1.75 V (with
ripple), 25°C TA,
Parasitic Capacitance
(CP) < 20 pF,
Sensitivity ≥ 0.4 pF
SID.CSD.BLK
ICSD
Maximum block current
–
–
4000
µA
Maximum block
current for both IDACs
in dynamic
(switching) mode
including comparators, buffer, and
reference generator
SID.CSD#15
VREF
Voltage reference for CSD
and comparator
0.6
1.2
VDDA 0.6
V
VDDA – 0.6 or 4.4,
whichever is lower
SID.CSD#15A VREF_EXT
External voltage reference
for CSD and comparator
0.6
VDDA 0.6
V
VDDA – 0.6 or 4.4,
whichever is lower
SID.CSD#16
IDAC1IDD
IDAC1 (7-bits) block
current
–
–
1750
µA
SID.CSD#17
IDAC2IDD
IDAC2 (7-bits) block
current
–
–
1750
µA
SID308
VCSD
Voltage range of operation 1.71
–
5.5
V
1.8 V ±5% or 1.8 V to
5.5 V
SID308A
VCOMPIDAC
Voltage compliance range
of IDAC
0.6
–
VDDA –
0.6
V
VDDA – 0.6 or 4.4,
whichever is lower
SID309
IDAC1DNL
DNL
–1
–
1
LSB
SID310
IDAC1INL
INL
–2
–
2
LSB
SID311
IDAC2DNL
DNL
–1
–
1
LSB
SID312
IDAC2INL
INL
–2
–
2
LSB
SID313
SNR
Ratio of counts of finger to
noise. Guaranteed by
characterization
5
–
–
Ratio Capacitance range of
5 to 35 pF, 0.1-pF
sensitivity. All use
cases. VDDA > 2 V.
SID314
IDAC1CRT1
Output current of IDAC1 (7
bits) in low range
4.2
–
5.4
µA
LSB = 37.5-nA typ
SID314A
IDAC1CRT2
Output current of IDAC1(7
bits) in medium range
34
–
41
µA
LSB = 300-nA typ
SID314B
IDAC1CRT3
Output current of IDAC1(7
bits) in high range
275
–
330
µA
LSB = 2.4-µA typ
SID314C
IDAC1CRT12
Output current of IDAC1 (7
bits) in low range, 2X mode
8
–
10.5
µA
LSB = 75-nA typ
Datasheet
31
INL is ±5.5 LSB for
VDDA < 2 V
INL is ±5.5 LSB for
VDDA < 2 V
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 15
Spec ID#
CSD and IDAC specifications (continued)
Parameter
Description
Min
Typ
Max
Units
Details/conditions
SID314D
IDAC1CRT22
Output current of IDAC1(7
bits) in medium range, 2X
mode
69
–
82
µA
LSB = 600-nA typ.
SID314E
IDAC1CRT32
Output current of IDAC1(7
bits) in high range, 2X
mode
540
–
660
µA
LSB = 4.8-µA typ
SID315
IDAC2CRT1
Output current of IDAC2 (7
bits) in low range
4.2
–
5.4
µA
LSB = 37.5-nA typ
SID315A
IDAC2CRT2
Output current of IDAC2 (7
bits) in medium range
34
–
41
µA
LSB = 300-nA typ
SID315B
IDAC2CRT3
Output current of IDAC2 (7
bits) in high range
275
–
330
µA
LSB = 2.4-µA typ
SID315C
IDAC2CRT12
Output current of IDAC2 (7
bits) in low range, 2X mode
8
–
10.5
µA
LSB = 75-nA typ
SID315D
IDAC2CRT22
Output current of IDAC2(7
bits) in medium range, 2X
mode
69
–
82
µA
LSB = 600-nA typ
SID315E
IDAC2CRT32
Output current of IDAC2(7
bits) in high range, 2X
mode
540
–
660
µA
LSB = 4.8-µA typ
SID315F
IDAC3CRT13
Output current of IDAC in
8-bit mode in low range
8
–
10.5
µA
LSB = 37.5-nA typ
SID315G
IDAC3CRT23
Output current of IDAC in
8-bit mode in medium
range
69
–
82
µA
LSB = 300-nA typ
SID315H
IDAC3CRT33
Output current of IDAC in
8-bit mode in high range
540
–
660
µA
LSB = 2.4-µA typ
SID320
IDACOFFSET
All zeroes input
–
–
1
LSB
Polarity set by Source
or Sink. Offset is 2
LSBs for 37.5 nA/LSB
mode
SID321
IDACGAIN
Full-scale error less offset
–
–
±10
%
SID322
IDACMISMATCH1
Mismatch between IDAC1
and IDAC2 in Low mode
–
–
9.2
LSB
LSB = 37.5-nA typ
SID322A
IDACMISMATCH2
Mismatch between IDAC1
and IDAC2 in Medium
mode
–
–
5.6
LSB
LSB = 300-nA typ
SID322B
IDACMISMATCH3
Mismatch between IDAC1
and IDAC2 in High mode
–
–
6.8
LSB
LSB = 2.4-µA typ
SID323
IDACSET8
Settling time to 0.5 LSB for
8-bit IDAC
–
–
5
µs
Full-scale transition.
No external load
SID324
IDACSET7
Settling time to 0.5 LSB for
7-bit IDAC
–
–
5
µs
Full-scale transition.
No external load
SID325
CMOD
External modulator
capacitor.
–
2.2
–
nF
5-V rating, X7R or NP0
cap
Datasheet
32
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.3.6
10-bit CAPSENSE™ ADC
Table 16
10-bit CAPSENSE™ ADC Specifications
Spec ID#
Parameter
Description
Min Typ Max Units
Details/conditions
SIDA94
A_RES
Resolution
–
–
10
SIDA95
A_CHNLS_S
Number of channels - single
ended
–
–
16
SIDA97
A-MONO
Monotonicity
–
–
–
Yes
SIDA98
A_GAINERR
Gain error
–
–
±3
%
In VREF (2.4 V) mode with
VDDA bypass capacitance
of 10 µF
SIDA99
A_OFFSET
Input offset voltage
–
–
±18
mV
In VREF (2.4 V) mode with
VDDA bypass capacitance
of 10 µF
SIDA100
A_ISAR
Current consumption
–
–
0.25
mA
SIDA101
A_VINS
Input voltage range - single
ended
VSSA
–
VDDA
V
SIDA103
A_INRES
Input resistance
–
2.2
–
KΩ
SIDA104
A_INCAP
Input capacitance
–
20
–
pF
SIDA106
A_PSRR
Power supply rejection ratio
–
60
–
dB
SIDA107
A_TACQ
Sample acquisition time
–
1
–
µs
SIDA108
A_CONV8
Conversion time for 8-bit
resolution at conversion rate
= Fhclk/(2^(N+2)). Clock
frequency = 48 MHz.
–
–
21.3
µs
Does not include acquisition time. Equivalent to
44.8 ksps including acquisition time.
SIDA108A
A_CONV10
Conversion time for 10-bit
resolution at conversion rate
= Fhclk/(2^(N+2)). Clock
frequency = 48 MHz.
–
–
85.3
µs
Does not include acquisition time. Equivalent to
11.6 ksps including acquisition time.
SIDA109
A_SND
Signal-to-noise and
distortion ratio (SINAD)
–
61
–
dB
With 10-Hz input sine
wave, external 2.4-V
reference, VREF (2.4 V)
mode
SIDA110
A_BW
Input bandwidth without
aliasing
–
–
22.4
SIDA111
A_INL
Integral non linearity. 1 ksps
–
–
2
LSB VREF = 2.4 V or greater
SIDA112
A_DNL
Differential non linearity.
1 ksps
–
–
1
LSB
Datasheet
33
bits Auto-zeroing is required
every millisecond
Defined by AMUX bus
In VREF (2.4 V) mode with
VDDA bypass capacitance
of 10 µF
KHz 8-bit resolution
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.4
5.4.1
Digital peripherals
Timer, Counter, Pulse-Width Modulator (TCPWM)
Table 17
TCPWM specifications
Spec ID
Parameter
SID.TCPWM.1
ITCPWM1
SID.TCPWM.2
ITCPWM2
SID.TCPWM.2A ITCPWM3
Description
Block current
consumption at 3 MHz
Block current
consumption at 12 MHz
Block current
consumption at 48 MHz
SID.TCPWM.3
TCPWMFREQ Operating frequency
SID.TCPWM.4
TPWMENEXT Input trigger pulse width
Min
Typ
Max
Units
–
–
45
–
–
155
–
–
650
All modes (TCPWM)
–
–
Fc
MHz Fc max = CLK_SYS
Maximum = 48 MHz
2/Fc
–
–
For all trigger events[7]
Minimum possible width
of Overflow, Underflow,
and CC (Counter equals
Compare value) outputs
μA
Details/conditions
All modes (TCPWM)
All modes (TCPWM)
Output trigger pulse
widths
2/Fc
–
–
SID.TCPWM.5A TCRES
Resolution of counter
1/Fc
–
–
SID.TCPWM.5B PWMRES
PWM resolution
1/Fc
–
–
Minimum pulse width of
PWM Output
SID.TCPWM.5C QRES
Quadrature inputs
resolution
1/Fc
–
–
Minimum pulse width
between Quadrature
phase inputs
Description
Min
Typ
Max
SID.TCPWM.5
TPWMEXT
5.4.2
I2C
Table 18
Fixed I2C DC specifications[7]
Spec ID
Parameter
ns
Units
Minimum time between
successive counts
Details/conditions
SID149
II2C1
Block current
consumption at 100 kHz
–
–
50
–
SID150
II2C2
Block current
consumption at 400 kHz
–
–
135
–
SID151
II2C3
Block current
consumption at 1 Mbps
–
–
310
SID152
II2C4
I2C enabled in Deep
Sleep mode
–
1
–
Min
Typ
Max
Units
–
–
1
Msps
Table 19
Spec ID
SID153
µA
–
Fixed I2C AC specifications[7]
Parameter
FI2C1
Description
Bit rate
Details/conditions
–
Note
7. Guaranteed by characterization.
Datasheet
34
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.4.3
SPI
Table 20
SPI DC specifications[8]
Spec ID
Parameter
Description
Min
Typ
Max
SID163
ISPI1
Block current consumption at
1 Mbps
–
–
360
SID164
ISPI2
Block current consumption at
4 Mbps
–
–
560
SID165
ISPI3
Block current consumption at
8 Mbps
–
–
600
Min
Typ
Max
–
–
8
Table 21
–
µA
–
–
SPI AC Specifications[8]
Spec ID Parameter
SID166
Units Details/conditions
FSPI
Description
SPI operating frequency (Master;
6X oversampling)
Units Details/conditions
MHz
Fixed SPI Master mode AC specifications
SID167
TDMO
MOSI valid after SClock driving
edge
–
–
15
SID168
TDSI
MISO valid before SClock
capturing edge
20
–
–
SID169
THMO
Previous MOSI data hold time
0
–
–
–
ns
Full clock, late MISO
sampling
Referred to slave
capturing edge
Fixed SPI Slave mode AC specifications
SID170
TDMI
MOSI valid before Sclock capturing
edge
40
–
–
SID171
TDSO
MISO valid after Sclock driving
edge
–
–
42 +
3*Tcpu
SID171A TDSO_EXT
MISO valid after Sclock driving
edge in Ext. Clk mode
–
–
48
–
SID172
Previous MISO data hold time
0
–
–
–
100
–
–
Min
Typ
Max
THSO
SID172A TSSELSSCK SSEL valid to first SCK Valid edge
5.4.4
UART
Table 22
UART DC specifications[8]
Spec ID Parameter
Description
–
ns
ns
TCPU = 1/FCPU
–
Units Details/conditions
SID160
IUART1
Block current consumption at
100 Kbps
–
–
55
µA
–
SID161
IUART2
Block current consumption at
1000 Kbps
–
–
312
µA
–
Min
Typ
Max
–
–
1
Table 23
UART AC Specifications[8]
Spec ID Parameter
SID162
FUART
Description
Bit rate
Units Details/conditions
Mbps
–
Note
8. Guaranteed by characterization.
Datasheet
35
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.4.5
LCD direct drive
Table 24
LCD direct drive DC specifications[9]
Spec ID
Parameter
Description
Min
SID154
ILCDLOW
Operating current in low
power mode
–
SID155
CLCDCAP
LCD capacitance per
segment/common driver
–
SID156
LCDOFFSET
Long-term segment offset
–
SID157
ILCDOP1
LCD system operating
current Vbias = 5 V
–
ILCDOP2
LCD system operating
current Vbias = 3.3 V
–
SID158
Spec ID
Units
Details/conditions
5
–
µA
16 4 small segment
disp. at 50 Hz
500
5000
pF
–
20
–
mV
–
2
–
mA
32 4 segments at
50 Hz 25°C
32 4 segments at
50 Hz 25°C
2
–
Parameter
Min
Typ
Max
Units
Details/conditions
FLCD
10
50
150
Hz
–
Description
Min
Typ
Max
Units
Details/conditions
Erase and program voltage
1.71
–
5.5
V
–
Min
Typ
Max
Units
Details/conditions
Description
LCD frame rate
5.5
Memory
Table 26
Flash DC specifications
Spec ID
SID173
Max
LCD Direct Drive AC specifications[9]
Table 25
SID159
Typ
Parameter
VPE
Table 27
Flash AC specifications
Spec ID
Parameter
Description
SID174
TROWWRITE[10]
Row (block) write time
(erase and program)
–
–
20
SID175
TROWERASE[10]
Row erase time
–
–
16
SID176
TROWPROGRAM[10]
Row program time after
erase
–
–
4
–
SID178
TBULKERASE[10]
Bulk erase time (64 KB)
–
–
35
–
TDEVPROG
Total device program time
–
–
7
Seconds
–
100 K
–
–
Cycles
–
–
–
[9]
SID180
[9]
[10]
SID181
FEND
Flash endurance
SID182[9]
FRET
Flash retention. TA 55°C,
100 K P/E cycles
20
SID182A[9] –
Flash retention. TA 85°C,
10 K P/E cycles
10
–
–
SID182B
Flash retention. TA 105°C,
10K P/E cycles, three
years at TA ≥ 85°C
10
–
20
–
Row (block) =
256 bytes
ms
–
–
Years
–
Years
–
Notes
9. Guaranteed by characterization.
10.It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations may be
interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and
privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated.
Datasheet
36
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 27
Spec ID
Flash AC specifications (continued)
Parameter
Description
Min
Typ
Max
Units
Details/conditions
SID256
TWS48
Number of Wait states at
48 MHz
2
–
–
CPU execution from
Flash
SID257
TWS24
Number of Wait states at
24 MHz
1
–
–
CPU execution from
Flash
Min
Typ
Max
Units
Details/conditions
1
–
67
V/ms
At power-up and
power-down
V
5.6
System resources
5.6.1
Power-on reset (POR)
Table 28
Power-on reset (PRES)
Spec ID
Parameter
Description
SID.CLK#6 SR_POWER_UP
Power supply slew rate
SID185[11] VRISEIPOR
Rising trip voltage
0.80
–
1.5
VFALLIPOR
Falling trip voltage
0.70
–
1.4
Description
Min
Typ
Max
Units
Details/conditions
BOD trip voltage in active
and sleep modes
1.48
–
1.62
V
–
BOD trip voltage in Deep
Sleep
1.11
–
1.5
Min
Typ
Max
3.3 V VDD 5.5 V
–
–
14
1.71 V VDD 3.3 V
–
–
7
SID186[11]
Table 29
Spec ID
SID190[11]
Parameter
VFALLPPOR
5.6.2
SWD interface
Table 30
SWD interface specifications
SID213
–
Brown-out detect (BOD) for VCCD
SID192[11] VFALLDPSLP
Spec ID
–
Parameter
F_SWDCLK1
Description
–
Units
MHz
Details/conditions
SWDCLK ≤ 1/3 CPU
clock frequency
SWDCLK ≤ 1/3 CPU
clock frequency
SID214
F_SWDCLK2
SID215[12]
T_SWDI_SETUP T = 1/f SWDCLK
0.25*
T
–
–
SID216[12]
T_SWDI_HOLD T = 1/f SWDCLK
0.25*
T
–
–
SID217[12]
T_SWDO_VALID T = 1/f SWDCLK
–
–
0.5*T
–
SID217A[12]
T_SWDO_HOLD T = 1/f SWDCLK
1
–
–
–
–
ns
–
Notes
11.Guaranteed by characterization.
12.Guaranteed by design.
Datasheet
37
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.6.3
Internal Main Oscillator
Table 31
IMO DC specifications
(Guaranteed by design)
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/conditions
SID218
IIMO1
IMO operating current at
48 MHz
–
–
250
µA
–
SID219
IIMO2
IMO operating current at
24 MHz
–
–
180
µA
–
Min
Typ
Max
Units
Details/conditions
Table 32
Spec ID
IMO AC specifications
Parameter
Description
SID223[14]
–
–
±2.0
%
At –40°C to 85°C, for industrial temperature range
and original extended
industrial range parts
SID223A[13, 14]
–
–
±2.5
%
At –40°C to 105°C, for all
extended industrial
temperature range parts
%
At –30°C to 105°C, for
enhanced IMO extended
industrial temperature
range parts
SID223B[13, 14] FIMOTOL1
Frequency variation at
24, 32, and 48 MHz
(trimmed)
–
–
±2.0
SID223C[13, 14]
–
–
±1.5
%
At –20°C to 105°C, for
enhanced IMO extended
industrial temperature
range parts
SID223D[13, 14]
–
–
±1.25
%
At 0°C to 85°C, for enhanced
IMO extended industrial
temperature range parts
–
–
7
µs
–
–
145
–
ps
–
SID226
TSTARTIMO
SID228
TJITRMSIMO2 RMS jitter at 24 MHz
IMO startup time
Notes
13.The enhanced IMO extended temperature range parts replace the original extended industrial temperature range parts. For details
on how to identify enhanced IMO extended temperature range parts, please refer to KBA235887.
14.Evaluated by characterization. Does not take into account soldering or board-level effects.
Datasheet
38
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
5.6.4
Internal Low-Speed Oscillator
Table 33
ILO DC specifications
(Guaranteed by design)
Spec ID
SID231
Table 34
Spec ID
[15]
SID234
SID236[15]
SID237
Parameter
IILO1
Description
ILO operating current
Min
Typ
Max
Units
Details/conditions
–
0.3
1.05
µA
–
Min
Typ
Max
Units
Details/conditions
ILO AC specifications
Parameter
Description
TSTARTILO1
ILO startup time
–
–
2
ms
–
TILODUTY
ILO duty cycle
40
50
60
%
–
FILOTRIM1
ILO frequency range
20
40
80
kHz
–
5.6.5
Watch Crystal Oscillator (WCO)
Table 35
WCO specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units Details/conditions
SID398
FWCO
Crystal frequency
–
32.76
8
–
SID399
FTOL
Frequency tolerance
–
50
250
SID400
ESR
Equivalent series resistance
–
50
–
kΩ
SID401
PD
Drive level
–
–
1
µW
SID402
TSTART
Startup time
–
–
500
ms
SID403
CL
Crystal load capacitance
6
–
12.5
pF
SID404
C0
Crystal shunt capacitance
–
1.35
–
pF
SID405
IWCO1
Operating current (high
power mode)
–
–
8
µA
Min
Typ
Max
Units
5.6.6
External clock
Table 36
External clock specifications
Spec ID
Parameter
Description
kHz
ppm With 20-ppm crystal
Details/conditions
SID305[15]
ExtClkFreq
External clock input
frequency
0
–
48
MHz
SID306[15]
ExtClkDuty
Duty cycle; measured at VDD/2
45
–
55
%
–
Min
Typ
Max
Units
Details/conditions
5.6.7
External Crystal Oscillator and PLL
Table 37
External Crystal Oscillator (ECO) specifications
Spec ID
Parameter
Description
SID316[16]
IECO1
External clock input
frequency
–
–
1.5
mA
SID317[16]
FECO
Crystal frequency range
4
–
33
MHz
–
–
–
Note
15.Guaranteed by design.
16.Guaranteed by characterization.
Datasheet
39
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Electrical specifications
Table 38
Spec ID
PLL specifications
Parameter
Description
Min
Typ
Max
Units
Details/conditions
SID410
IDD_PLL_48
In = 3 MHz, Out = 48 MHz
–
530
610
µA
–
SID411
IDD_PLL_24
In = 3 MHz, Out = 24 MHz
–
300
405
µA
–
SID412
Fpllin
PLL input frequency
1
–
48
MHz
–
SID413
Fpllint
PLL intermediate frequency;
prescaler out
1
–
3
MHz
–
SID414
Fpllvco
VCO output frequency
before post-divide
22.5
–
104
MHz
–
SID415
Divvco
VCO Output post-divider
range; PLL output frequency
is Fpplvco/Divvco
1
–
8
SID416
Plllocktime
Lock time at startup
–
–
250
µs
SID417
Jperiod_1
Period jitter for VCO ≥ 67
MHz
–
–
150
ps
Guaranteed by
design
SID416A
Jperiod_2
Period jitter for VCO ≤ 67
MHz
–
–
200
ps
Guaranteed by
design
Min
3
Typ
–
Max
4
Units
Periods
Details/conditions
5.6.8
System clock
Table 39
System clock specification
Spec ID
SID262[16]
Parameter
TCLKSWITCH
Description
System clock source
switching time
5.6.9
Smart I/Os
Table 40
Smart I/O pass-through time (Delay in bypass mode)
Spec ID
SID252
Parameter
Description
PRG_BYPASS Max delay added by Smart
I/O in bypass mode
5.6.10
CAN
Table 41
CAN specifications
Spec ID
Parameter
–
–
Min
–
Typ
–
Max
1.6
Units
ns
Details/conditions
Description
Min
Typ
Max
Units
Details/Conditions
–
SID420
IDD_CAN
Block current consumption
–
–
200
µA
SID421
CAN_bits
CAN Bit rate
–
–
1
Mbps
Datasheet
–
40
–
Min 8-MHZ clock
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Ordering information
6
Ordering information
The marketing part numbers for the PSoC™ 4100S Plus devices are listed in the following table.
ECO
CAN controller
Smart I/Os
GPIO
44-TQFP (0.8-mm pitch)
64-TQFP (0.5-mm pitch)
64-TQFP (0.8-mm pitch)
8
4
✔
0
24
37
✔
–
–
–
–40 to 85
8
5
✔
0
24
54
–
–
✔
–
–40 to 85
4146
4127
4147
MPN
TCPWM blocks
2
2
LP comparators
806 ksps
806 ksps
SAR ADC sample rate
1
1
12-bit SAR ADC
1
1
10-bit CSD ADC
0
0
CSD
2
2
Opamp (CTBm)
8
8
SRAM (KB)
64
64
Flash (KB)
24
24
Max CPU speed (MHz)
CY8C4126AXI-S443
CY8C4126AZI-S445
Category
4126
Packages
SCB blocks
Features
Temperature range (°C)
Ordering information
48-TQFP (0.5-mm pitch)
Table 42
CY8C4126AXI-S445
24
64
8
2
0
1
1
806 ksps
2
8
5
✔
0
24
54
–
–
–
✔
–40 to 85
CY8C4126AZI-S455
24
64
8
2
1
1
1
806 ksps
2
8
5
✔
0
24
54
–
–
✔
–
–40 to 85
CY8C4126AXI-S455
24
64
8
2
1
1
1
806 ksps
2
8
5
✔
0
24
54
–
–
–
✔
–40 to 85
–40 to 85
CY8C4146AXI-S443
48
64
8
2
0
1
1
1 Msps
2
8
4
✔
0
24
37
✔
–
–
–
CY8C4146AZI-S443
48
64
8
2
0
1
1
1 Msps
2
8
4
✔
0
24
38
–
✔
–
–
–40 to 85
CY8C4146AZI-S445
48
64
8
2
0
1
1
1 Msps
2
8
5
✔
0
24
54
–
–
✔
–
–40 to 85
CY8C4146AZQ-S445
48
64
8
2
0
1
1
1 Msps
2
8
5
✔
0
24
54
–
–
✔
–
–40 to 105
CY8C4146AXI-S445
48
64
8
2
0
1
1
1 Msps
2
8
5
✔
0
24
54
–
–
–
✔
–40 to 85
–40 to 85
CY8C4146AXI-S453
48
64
8
2
1
1
1
1 Msps
2
8
4
✔
0
24
37
✔
–
–
–
CY8C4146AZI-S453
48
64
8
2
1
1
1
1 Msps
2
8
4
✔
0
24
38
–
✔
–
–
–40 to 85
CY8C4146AZI-S455
48
64
8
2
1
1
1
1 Msps
2
8
5
✔
0
24
54
–
–
✔
–
–40 to 85
CY8C4146AZQ-S455
48
64
8
2
1
1
1
1 Msps
2
8
5
✔
0
24
54
–
–
✔
–
–40 to 105
CY8C4146AXI-S455
48
64
8
2
1
1
1
1 Msps
2
8
5
✔
0
24
54
–
–
–
✔
–40 to 85
CY8C4146AZI-S463
48
64
8
2
0
1
1
1 Msps
2
8
4
✔
1
24
38
–
✔
–
–
–40 to 85
CY8C4127AXI-S443
24
128
16
2
0
1
1
806 ksps
2
8
4
✔
0
24
37
✔
–
–
–
–40 to 85
CY8C4127AZI-S443
24
128
16
2
0
1
1
806 ksps
2
8
4
✔
0
24
38
–
✔
–
–
–40 to 85
CY8C4127AZI-S445
24
128
16
2
0
1
1
806 ksps
2
8
5
✔
0
24
54
–
–
✔
–
–40 to 85
CY8C4127AZQ-S445
24
128
16
2
0
1
1
806 ksps
2
8
5
✔
0
24
54
–
–
✔
–
–40 to 105
CY8C4127AXI-S445
24
128
16
2
0
1
1
806 ksps
2
8
5
✔
0
24
54
–
–
–
✔
–40 to 85
CY8C4127AXI-S453
24
128
16
2
1
1
1
806 ksps
2
8
4
✔
0
24
37
✔
–
–
–
–40 to 85
CY8C4127AZI-S453
24
128
16
2
1
1
1
806 ksps
2
8
4
✔
0
24
38
–
✔
–
–
–40 to 85
CY8C4127AZI-S455
24
128
16
2
1
1
1
806 ksps
2
8
5
✔
0
24
54
–
–
✔
–
–40 to 85
CY8C4127AZQ-S455
24
128
16
2
1
1
1
806 ksps
2
8
5
✔
0
24
54
–
–
✔
–
–40 to 105
CY8C4127AXI-S455
24
128
16
2
1
1
1
806 ksps
2
8
5
✔
0
24
54
–
–
–
✔
–40 to 85
CY8C4147AXI-S443
48
128
16
2
0
1
1
1 Msps
2
8
4
✔
0
24
37
✔
–
–
–
–40 to 85
CY8C4147AZI-S443
48
128
16
2
0
1
1
1 Msps
2
8
4
✔
0
24
38
–
✔
–
–
–40 to 85
CY8C4147AZI-S445
48
128
16
2
0
1
1
1 Msps
2
8
5
✔
0
24
54
–
–
✔
–
–40 to 85
CY8C4147AZQ-S445
48
128
16
2
0
1
1
1 Msps
2
8
5
✔
0
24
54
–
–
✔
–
–40 to 105
CY8C4147AXI-S445
48
128
16
2
0
1
1
1 Msps
2
8
5
✔
0
24
54
–
–
–
✔
–40 to 85
CY8C4147AXI-S453
48
128
16
2
1
1
1
1 Msps
2
8
4
✔
0
24
37
✔
–
–
–
–40 to 85
CY8C4147AZI-S453
48
128
16
2
1
1
1
1 Msps
2
8
4
✔
0
24
38
–
✔
–
–
–40 to 85
CY8C4147AZQ-S453
48
128
16
2
1
1
1
1 Msps
2
8
4
✔
0
24
38
–
✔
–
–
–40 to 105
CY8C4147AZI-S455
48
128
16
2
1
1
1
1 Msps
2
8
5
✔
0
24
54
–
–
✔
–
–40 to 85
CY8C4147AZQ-S455
48
128
16
2
1
1
1
1 Msps
2
8
5
✔
0
24
54
–
–
✔
–
–40 to 105
CY8C4147AXI-S455
48
128
16
2
1
1
1
1 Msps
2
8
5
✔
0
24
54
–
–
–
✔
–40 to 85
CY8C4147AZI-S463
48
128
16
2
0
1
1
1 Msps
2
8
4
✔
1
24
38
–
✔
–
–
–40 to 85
Datasheet
41
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Ordering information
Ordering information (continued)
Opamp (CTBm)
CSD
10-bit CSD ADC
12-bit SAR ADC
SAR ADC sample rate
LP comparators
TCPWM blocks
SCB blocks
ECO
CAN controller
Smart I/Os
GPIO
44-TQFP (0.8-mm pitch)
48-TQFP (0.5-mm pitch)
128
16
2
0
1
1
1 Msps
2
8
5
✔
1
24
54
–
–
CY8C4147AZQ-S465
48
128
16
2
0
1
1
1 Msps
2
8
5
✔
1
24
54
–
–
CY8C4147AXI-S465
48
128
16
2
0
1
1
1 Msps
2
8
5
✔
1
24
54
–
–
CY8C4147AZI-S475
48
128
16
2
1
1
1
1 Msps
2
8
5
✔
1
24
54
–
CY8C4147AZQ-S475
48
128
16
2
1
1
1
1 Msps
2
8
5
✔
1
24
54
CY8C4147AXI-S475
48
128
16
2
1
1
1
1 Msps
2
8
5
✔
1
24
54
42
MPN
64-TQFP (0.8-mm pitch)
SRAM (KB)
48
Datasheet
64-TQFP (0.5-mm pitch)
Flash (KB)
CY8C4147AZI-S465
Category
4147
Packages
Max CPU speed (MHz)
Features
Temperature range (°C)
Table 42
✔
–
–40 to 85
✔
–
–40 to 105
–
✔
–40 to 85
–
✔
–
–40 to 85
–
–
✔
–
–40 to 105
–
–
–
✔
-40 to 85
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Ordering information
The nomenclature used in the preceding table is based on the following part numbering convention:
Field
Description
Values
Meaning
CY8C
Infineon prefix
4
Architecture
4
PSoC™ 4 MCU
A
Family
1
4100 family
B
CPU speed
2
24 MHz
4
48 MHz
4
16 KB
5
32 KB
6
64 KB
7
128 KB
AX
TQFP (0.8-mm pitch)
AZ
TQFP (0.5-mm pitch)
LQ
QFN
PV
SSOP
FN
I
Q
S
CSP
Industrial
Extended Industrial
PSoC™ 4 S-series
M
PSoC™ 4 M-series
L
PSoC™ 4 L-series
BL
PSoC™ 4 Bluetooth® LE-series
000-999
Code of feature set in the specific family
C
DE
Flash capacity
Package code
F
Temperature range
S
Series designator
XYZ
Attributes code
The following is an example of a part number:
Example
4 : PSoC™ 4 MCU
1 : 4100 family
4 : 48 MHz
CY 8 C 4 A B C DE F – S XYZ
Infineon prefix
Architecture
Family within architecture
CPU speed
5 : 32 KB
Flash capacity
AZ/AX : TQFP
Package code
I : Industrial
Temperature range
Series designator
Attributes code
Datasheet
43
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Packaging
7
Packaging
The PSoC™ 4100S Plus is offered in 44-pin TQFP, 48-pin TQFP, 64-pin TQFP Normal pitch, and 64-pin TQFP fine
pitch packages.
Table 43 provides the package dimensions and Infineon drawing numbers.
Table 43
Package list
Spec ID#
Package
BID20
64-pin TQFP
14 × 14 × 1.4-mm height with 0.8-mm pitch
51-85046
BID27
64-pin TQFP
10 × 10 × 1.6-mm height with 0.5-mm pitch
51-85051
BID34A
44-pin TQFP
10 × 10 × 1.4-mm height with 0.8-mm pitch
51-85064
BID70
48-pin TQFP
7 × 7 × 1.4-mm height with 0.5-mm pitch
51-85135
Table 44
Description
Package dwg
Package thermal characteristics
Parameter
Description
Package
Min
Typ
Max
Units
TA
Operating ambient temperature
–
–40
25
105
°C
TJ
Operating junction temperature
–
–40
–
125
°C
TJA
Package θJA
44-pin TQFP
–
55.6
–
°C/Watt
TJC
Package θJC
44-pin TQFP
–
14.4
–
°C/Watt
TJA
Package θJA
64-pin TQFP (0.5-mm pitch)
–
46
–
°C/Watt
TJC
Package θJC
64-pin TQFP (0.5-mm pitch)
–
10
–
°C/Watt
TJA
Package θJA
64-pin TQFP (0.8-mm pitch)
–
36.8
–
°C/Watt
TJC
Package θJC
64-pin TQFP (0.8-mm pitch)
–
9.4
–
°C/Watt
TJA
Package θJA
48-pin TQFP (0.5-mm pitch)
–
39.4
–
°C/Watt
TJC
Package θJC
48-pin TQFP (0.5-mm pitch)
–
9.3
–
°C/Watt
Table 45
Solder reflow peak temperature
Package
Maximum peak temperature
Maximum time at peak temperature
All
260°C
30 seconds
Table 46
Datasheet
Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-020
Package
MSL
All
MSL 3
44
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Packaging
7.1
Package diagrams
ș1
ș
ș2
SYMBOL
DIMENSIONS
A
0.05
A2
1.35 1.40 1.45
D
15.75 16.00 16.25
13.95 14.00 14.05
E
15.75 16.00 16.25
E1
13.95 14.00 14.05
R1
0.08
0.20
R2
0.08
0.20
ș
0°
7°
ș1
0°
ș2
11°
b
0.30 0.35 0.40
L
0.45 0.60 0.75
L3
e
Datasheet
13°
12°
0.20
c
Figure 7
0.15
D1
L2
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
1.60
A1
L1
NOTE:
MIN. NOM. MAX.
1.00 REF
0.25 BSC
0.20
0.80 TYP
51-85046 *H
64-pin TQFP package (0.8-mm pitch) outline
45
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Packaging
51-85051 *D
Figure 8
64-pin TQFP package (0.5-mm pitch) outline
51-85064 *G
Figure 9
Datasheet
44-pin TQFP package outline
46
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Packaging
51-85135 *C
Figure 10
Datasheet
48-pin 7 × 7 × 1.4 mm TQFP package outline
47
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Acronyms
8
Acronyms
Table 47
Acronyms used in this document
Acronym
Description
abus
analog local bus
ADC
analog-to-digital converter
AG
analog global
AHB
AMBA (advanced microcontroller bus architecture) high-performance bus, an Arm® data transfer
bus
ALU
arithmetic logic unit
AMUXBUS
analog multiplexer bus
API
application programming interface
APSR
application program status register
Arm®
advanced RISC machine, a CPU architecture
ATM
automatic thump mode
BW
bandwidth
CAN
Controller Area Network, a communications protocol
CMRR
common-mode rejection ratio
CPU
central processing unit
CRC
cyclic redundancy check, an error-checking protocol
DAC
digital-to-analog converter, see also IDAC, VDAC
DFB
digital filter block
DIO
digital input/output, GPIO with only digital capabilities, no analog. See GPIO.
DMIPS
Dhrystone million instructions per second
DMA
direct memory access, see also TD
DNL
differential nonlinearity, see also INL
DNU
do not use
DR
port write data registers
DSI
digital system interconnect
DWT
data watchpoint and trace
ECC
error correcting code
ECO
external crystal oscillator
EEPROM
electrically erasable programmable read-only memory
EMI
electromagnetic interference
EMIF
external memory interface
EOC
end of conversion
EOF
end of frame
EPSR
execution program status register
ESD
electrostatic discharge
ETM
embedded trace macrocell
FIR
finite impulse response, see also IIR
FPB
flash patch and breakpoint
Datasheet
48
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Acronyms
Table 47
Acronyms used in this document (continued)
Acronym
Description
FS
full-speed
GPIO
general-purpose input/output, applies to a PSoC™ pin
HVI
high-voltage interrupt, see also LVI, LVD
IC
integrated circuit
IDAC
current DAC, see also DAC, VDAC
IDE
integrated development environment
I2C, or IIC
Inter-Integrated Circuit, a communications protocol
IIR
infinite impulse response, see also FIR
ILO
internal low-speed oscillator, see also IMO
IMO
internal main oscillator, see also ILO
INL
integral nonlinearity, see also DNL
I/O
input/output, see also GPIO, DIO, SIO, USBIO
IPOR
initial power-on reset
IPSR
interrupt program status register
IRQ
interrupt request
ITM
instrumentation trace macrocell
LCD
liquid crystal display
LIN
Local Interconnect Network, a communications protocol.
LR
link register
LUT
lookup table
LVD
low-voltage detect, see also LVI
LVI
low-voltage interrupt, see also HVI
LVTTL
low-voltage transistor-transistor logic
MAC
multiply-accumulate
MCU
microcontroller unit
MISO
master-in slave-out
NC
no connect
NMI
nonmaskable interrupt
NRZ
non-return-to-zero
NVIC
nested vectored interrupt controller
NVL
nonvolatile latch, see also WOL
opamp
operational amplifier
PAL
programmable array logic, see also PLD
PC
program counter
PCB
printed circuit board
PGA
programmable gain amplifier
PHUB
peripheral hub
PHY
physical layer
PICU
port interrupt control unit
PLA
programmable logic array
Datasheet
49
002-19966 Rev. *K
2023-01-24
PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Acronyms
Table 47
Acronyms used in this document (continued)
Acronym
Description
PLD
programmable logic device, see also PAL
PLL
phase-locked loop
PMDD
package material declaration data sheet
POR
power-on reset
PRES
precise power-on reset
PRS
pseudo random sequence
PS
port read data register
PSoC™
programmable system on chip
PSRR
power supply rejection ratio
PWM
pulse-width modulator
RAM
random-access memory
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
RTL
register transfer language
RTR
remote transmission request
RX
receive
SAR
successive approximation register
SC/CT
switched capacitor/continuous time
SCL
I2C serial clock
SDA
I2C serial data
S/H
sample and hold
SINAD
signal to noise and distortion ratio
SIO
special input/output, GPIO with advanced features. See GPIO.
SOC
start of conversion
SOF
start of frame
SPI
Serial Peripheral Interface, a communications protocol
SR
slew rate
SRAM
static random access memory
SRES
software reset
SWD
serial wire debug, a test protocol
SWV
single-wire viewer
TD
transaction descriptor, see also DMA
THD
total harmonic distortion
TIA
transimpedance amplifier
TRM
technical reference manual
TTL
transistor-transistor logic
TX
transmit
UART
Universal Asynchronous Transmitter Receiver, a communications protocol
UDB
universal digital block
Datasheet
50
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PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Acronyms
Table 47
Acronyms used in this document (continued)
Acronym
Description
USB
Universal Serial Bus
USBIO
USB input/output, PSoC™ pins used to connect to a USB port
VDAC
voltage DAC, see also DAC, IDAC
WDT
watchdog timer
WOL
write once latch, see also NVL
WRES
watchdog timer reset
XRES
external reset I/O pin
XTAL
crystal
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PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Document conventions
9
Document conventions
9.1
Units of measure
Table 48
Units of measure
Symbol
Unit of measure
°C
degrees Celsius
dB
decibel
fF
femto farad
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohour
kHz
kilohertz
k
kilo ohm
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
M
mega-ohm
Msps
megasamples per second
µA
microampere
µF
microfarad
µH
microhenry
µs
microsecond
µV
microvolt
µW
microwatt
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
nV
nanovolt
ohm
pF
picofarad
ppm
parts per million
ps
picosecond
s
second
sps
samples per second
sqrtHz
square root of hertz
V
volt
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PSoC™ 4 MCU: PSoC™ 4100S Plus
Based on Arm® Cortex®-M0+ CPU
Revision history
Revision histor y
Document
version
Date of release
Description of changes
*E
2017-12-15
New release
*F
2018-02-13
Updated Pinouts and DC specifications.
*G
2018-05-09
Updated Clock Diagram to show Watchdog details and clock divider information.
Removed preliminary statement in Pinouts.
2018-09-14
Updated 32-bit MCU subsystem feature list.
Added 48-pin TQFP pin and package details.
Updated Watch Crystal Oscillator (WCO).
Corrected typos in CTBm opamp specifications.
Updated values for SID260.
Updated Conditions for SID.CSD#15, SID.CSD#15A, and SID308A.
Updated min and max values for SID172A.
Added extended temperature range.
2019-06-28
Updated the title for AN85951.
Updated Serial Communication Block (SCB).
Updated LCD segment drive.
Updated description for SID55.
2020-11-10
Added ModusToolbox™ in Features.
Updated Development ecosystem.
Added ModusToolbox™ software.
Updated Table 27: Updated SID182B.
Updated Table 32: Added SID223A.
Updated Ordering information.
2023-01-24
Migrated to Infineon template.
Updated Table 32: Updated spec SID223 and SID223A. Added specs SID223B
through SID223D.
Updated Ordering information.
Updated the footnotes in IMO AC specifications
*H
*I
*J
*K
Datasheet
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Please read the Important Notice and Warnings at the end of this document
Trademarks
All referenced product or service names and trademarks are the property of their respective owners.
Edition 2023-01-24
Published by
Infineon Technologies AG
81726 Munich, Germany
© 2023 Infineon Technologies AG.
All Rights Reserved.
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document?
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Document reference
002-19966 Rev. *K
IMPORTANT NOTICE
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