PSoC® 4: PSoC 4100S Plus
Datasheet
PRELIMINARY
Programmable System-on-Chip (PSoC)
General Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
ARM® Cortex™-M0+ CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing.
PSoC 4100S Plus is a member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard communication and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, programmable
general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC 4100S Plus products
will be upward compatible with members of the PSoC 4 platform for new applications and design needs.
Features
32-bit MCU Subsystem
Timing and Pulse-Width Modulation
■
48-MHz ARM Cortex-M0+ CPU
■
Up to 128 KB of flash with Read Accelerator
■
■
■
Eight 16-bit timer/counter/pulse-width modulator (TCPWM)
blocks
Up to 16 KB of SRAM
■
Center-aligned, Edge, and Pseudo-random modes
8-channel DMA engine
■
Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
■
Quadrature decoder
Programmable Analog
■
Two opamps with reconfigurable high-drive external and
high-bandwidth internal drive and Comparator modes and ADC
input buffering capability. Opamps can operate in Deep Sleep
low-power mode.
■
12-bit 1-Msps SAR ADC with differential and single-ended
modes, and Channel Sequencer with signal averaging
■
Single-slope 10-bit ADC function provided by a capacitance
sensing block
■
Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
■
Two low-power comparators that operate in Deep Sleep
low-power mode
Clock Sources
■
4 to 33 MHz external crystal oscillator (ECO)
■
PLL to generate 48-MHz frequency
■
32-kHz Watch Crystal Oscillator (WCO)
■
±2% Internal Main Oscillator (IMO)
■
32-kHz Internal Low-power Oscillator (ILO)
True Random Number Generator (TRNG)
■
Programmable Digital
■
Programmable logic blocks allowing Boolean operations to be
performed on port inputs and outputs
Low-Power 1.71-V to 5.5-V Operation
■
Deep Sleep mode with operational analog and 2.5-A digital
system current
Capacitive Sensing
■
Cypress CapSense Sigma-Delta (CSD) provides best-in-class
signal-to-noise ratio (SNR) (>5:1) and water tolerance
■
Cypress-supplied software component makes capacitive
sensing design easy
■
Automatic hardware tuning (SmartSense™)
LCD Drive Capability
■
LCD segment drive capability on GPIOs
Serial Communication
■
CAN Block
■
CAN 2.0B block with support for Time-Triggered CAN (TTCAN)
Up to 54 Programmable GPIO Pins
■
44-pin TQFP (0.8-mm pitch) and 64-pin TQFP normal (0.8 mm)
and Fine Pitch (0.5 mm) packages
■
Any GPIO pin can be CapSense, analog, or digital
■
Drive modes, strengths, and slew rates are programmable
PSoC Creator Design Environment
■
Integrated Development Environment (IDE) provides
schematic design entry and build (with analog and digital
automatic routing)
■
Applications Programming Interface (API) component for all
fixed-function and programmable peripherals
Industry-Standard Tool Compatibility
Five independent run-time reconfigurable Serial
Communication Blocks (SCBs) with re-configurable I2C, SPI,
or UART functionality
Cypress Semiconductor Corporation
Document Number: 002-19966 Rev. *E
TRNG generates truly random number for secure key generation for Cryptography applications
•
■
198 Champion Court
After schematic entry, development can be done with
ARM-based industry-standard development tools
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 15, 2017
PRELIMINARY
PSoC® 4: PSoC 4100S Plus
Datasheet
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP. Following is an abbreviated list for PSoC 4:
■
Overview: PSoC Portfolio, PSoC Roadmap
■
Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP
In addition, PSoC Creator includes a device selection tool.
■
Application notes: Cypress offers a large number of PSoC
application notes covering a broad range of topics, from basic
to advanced level. Recommended application notes for getting
started with PSoC 4 are:
❐ AN79953: Getting Started With PSoC 4
❐ AN88619: PSoC 4 Hardware Design Considerations
❐ AN86439: Using PSoC 4 GPIO Pins
❐ AN57821: Mixed Signal Circuit Board Layout
❐ AN81623: Digital Design Best Practices
❐ AN73854: Introduction To Bootloaders
❐ AN89610: ARM Cortex Code Optimization
®
❐ AN85951: PSoC 4 and PSoC Analog Coprocessor
CapSense® Design Guide
■
Technical Reference Manual (TRM) is in two documents:
❐ Architecture TRM details each PSoC 4 functional block.
❐ Registers TRM describes each of the PSoC 4 registers.
■
Development Kits:
❐ CY8CKIT-041-41XX PSoC 4100S CapSense Pioneer Kit, is
an easy-to-use and inexpensive development platform. This
kit includes connectors for Arduino™ compatible shields.
❐ CY8CKIT-149 PSoC® 4100S Plus Prototyping Kit enables
you to evaluate and develop with Cypress' fourth-generation,
low-power CapSense solution using the PSoC 4100S Plus
devices.
Document Number: 002-19966 Rev. *E
The MiniProg3 device provides an interface for flash
programming and debug.
■
Software User Guide:
❐ A step-by-step guide for using PSoC Creator. The software
user guide shows you how the PSoC Creator build process
works in detail, how to use source control with PSoC Creator,
and much more.
■
Component Datasheets:
❐ The flexibility of PSoC allows the creation of new peripherals
(components) long after the device has gone into production.
Component datasheets provide all the information needed to
select and use a particular component, including a functional
description, API documentation, example code, and AC/DC
specifications.
■
Online:
❐ In addition to print documentation, the Cypress PSoC forums
connect you with fellow PSoC users and experts in PSoC
from around the world, 24 hours a day, 7 days a week.
Page 2 of 42
PRELIMINARY
PSoC® 4: PSoC 4100S Plus
Datasheet
PSoC Creator
PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100
pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can:
1. Drag and drop component icons to build your hardware
system design in the main design workspace
2. Codesign your application firmware with the PSoC hardware,
using the PSoC Creator IDE C compiler
3. Configure components using the configuration tools
4. Explore the library of 100+ components
5. Review component datasheets
Figure 1. Multiple-Sensor Example Project in PSoC Creator
1
2
3
4
5
Document Number: 002-19966 Rev. *E
Page 3 of 42
PRELIMINARY
PSoC® 4: PSoC 4100S Plus
Datasheet
Contents
Functional Definition........................................................ 6
CPU and Memory Subsystem ..................................... 6
System Resources ...................................................... 6
Analog Blocks.............................................................. 7
Programmable Digital Blocks ...................................... 8
Fixed Function Digital Blocks ...................................... 8
GPIO ........................................................................... 8
Special Function Peripherals....................................... 9
Pinouts ............................................................................ 10
Alternate Pin Functions ............................................. 12
Power............................................................................... 14
Mode 1: 1.8 V to 5.5 V External Supply .................... 14
Mode 2: 1.8 V ±5% External Supply.......................... 14
Electrical Specifications ................................................ 15
Absolute Maximum Ratings....................................... 15
Device Level Specifications....................................... 15
Analog Peripherals .................................................... 19
Digital Peripherals ..................................................... 26
Memory ..................................................................... 29
System Resources .................................................... 29
Document Number: 002-19966 Rev. *E
Ordering Information...................................................... 33
Packaging........................................................................ 35
Package Diagrams .................................................... 36
Acronyms ........................................................................ 38
Document Conventions ................................................. 40
Units of Measure ....................................................... 40
Revision History ............................................................. 41
Sales, Solutions, and Legal Information ...................... 42
Worldwide Sales and Design Support....................... 42
Products .................................................................... 42
PSoC® Solutions ...................................................... 42
Cypress Developer Community................................. 42
Technical Support ..................................................... 42
Page 4 of 42
PSoC® 4: PSoC 4100S Plus
Datasheet
PRELIMINARY
Figure 2. Block Diagram
CPU Subsystem
SWD/TC, MTB
SPCIF
Cortex
M0+
48 MHz
FLASH
128 KB
32-bit
FAST MUL
NVIC, IRQMUX, MPU
System Resources
Lite
Initiator / MMIO
x1
SARMUX
TRNG
CAN
SAR ADC
(12-bit)
LCD
Programmable
Analog
WCO
Peripheral Interconnect ( MMIO)
PCLK
2x LP Comparator
Test
TestMode Entry
Digital DFT
Analog DFT
ROM Controller
5x SCB-I2C/SPI/UART
Reset
Reset Control
XRES
SRAM Controller
Peripherals
IOSS GPIO (8x ports)
Clock
Clock Control
WDT
ILO
IMO
DataWire/
DMA
System Interconnect (Single Layer AHB)
ECO (w/PLL)
Power
Sleep Control
WIC
POR
REF
PWRSYS
Read Accelerator
ROM
8 KB
CapSense(v2)
AHB- Lite
SRAM
16 KB
8x TCPWM
PSoC 4100S
Plus
CTBm
2 x Opamp
High Speed I /O Matrix & Smart I/O
Power Modes
Active / Sleep
DeepSleep
Up to 54 x GPIOs
I/ O Subsystem
PSoC 4100S Plus devices include extensive support for
programming, testing, debugging, and tracing both hardware
and firmware.
The ARM Serial-Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE provides fully integrated programming
and debug support for the PSoC 4100S Plus devices. The SWD
interface is fully compatible with industry-standard third-party
tools. PSoC 4100S Plus provides a level of security not possible
with multi-chip application solutions or with microcontrollers. It
has the following advantages:
■
Allows disabling of debug features
■
Robust flash protection
■
Allows customer-proprietary functionality to be implemented in
on-chip programmable blocks
Document Number: 002-19966 Rev. *E
The debug circuits are enabled by default and can be disabled
in firmware. If they are not enabled, the only way to re-enable
them is to erase the entire device, clear flash protection, and
reprogram the device with new firmware that enables debugging.
Thus firmware control of debugging cannot be over-ridden
without erasing the firmware thus providing security.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. All programming, debug, and test interfaces are
disabled when maximum device security is enabled. Therefore,
PSoC 4100S Plus, with device security enabled, may not be
returned for failure analysis. This is a trade-off the PSoC 4100S
Plus allows the customer to make.
Page 5 of 42
PSoC® 4: PSoC 4100S Plus
Datasheet
PRELIMINARY
Functional Definition
CPU and Memory Subsystem
CPU
The Cortex-M0+ CPU in the PSoC 4100S Plus is part of the
32-bit MCU subsystem, which is optimized for low-power
operation with extensive clock gating. Most instructions are 16
bits in length and the CPU executes a subset of the Thumb-2
instruction set. It includes a nested vectored interrupt controller
(NVIC) block with eight interrupt inputs and also includes a
Wakeup Interrupt Controller (WIC). The WIC can wake the
processor from Deep Sleep mode, allowing power to be switched
off to the main processor when the chip is in Deep Sleep mode.
The CPU subsystem includes an 8-channel DMA engine and
also includes a debug interface, the serial wire debug (SWD)
interface, which is a two-wire form of JTAG. The debug configuration used for PSoC 4100S Plus has four breakpoint (address)
comparators and two watchpoint (data) comparators.
off; wake-up from this mode takes 35 µs. The opamps can
remain operational in Deep Sleep mode.
Clock System
The PSoC 4100S Plus clock system is responsible for providing
clocks to all subsystems that require clocks and for switching
between different clock sources without glitching. In addition, the
clock system ensures that there are no metastable conditions.
The clock system for the PSoC 4100S Plus consists of the IMO,
ILO, a 32-kHz Watch Crystal Oscillator (WCO), MHz ECO and
PLL, and provision for an external clock. The WCO block allows
locking the IMO to the 32-kHz oscillator.
Figure 3. PSoC 4100S Plus MCU Clocking Architecture
clk_e xt
IM O
D ivide B y
2 ,4 ,8
PLL
ECO
Flash
The PSoC 4100S Plus device has a flash module with a flash
accelerator, tightly coupled to the CPU to improve average
access times from the flash block. The low-power flash block is
designed to deliver two wait-state (WS) access time at 48 MHz.
The flash accelerator delivers 85% of single-cycle SRAM access
performance on average.
SRAM
16 KB of SRAM are provided with zero wait-state access at
48 MHz.
SROM
An 8-KB supervisory ROM that contains boot and configuration
routines is provided.
System Resources
Power System
The power system is described in detail in the section Power. It
provides assurance that voltage levels are as required for each
respective mode and either delays mode entry (for example, on
power-on reset (POR)) until voltage levels are as required for
proper functionality, or generates resets (for example, on
brown-out detection). PSoC 4100S Plus operates with a single
external supply over the range of either 1.8 V ±5% (externally
regulated) or 1.8 to 5.5 V (internally regulated) and has three
different power modes, transitions between which are managed
by the power system. PSoC 4100S Plus provides Active, Sleep,
and Deep Sleep low-power modes.
All subsystems are operational in Active mode. The CPU
subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep
mode, while all peripherals and interrupts are active with
instantaneous wake-up on a wake-up event. In Deep Sleep
mode, the high-speed clock and associated circuitry is switched
Document Number: 002-19966 Rev. *E
IL O
clk_ lf
WCO
clk_ h f
P re sca le r
P e rip h e ra l
D ivid e rs
A n a lo g
D ivid e r
clk_ sys
P e rip h e ra l C lo cks
S A R C lo ck
The HFCLK signal can be divided down as shown to generate
synchronous clocks for the Analog and Digital peripherals. There
are 18 clock dividers for the PSoC 4100S Plus (six with fractional
divide capability, twelve with integer divide only). The twelve
16-bit integer divide capability allows a lot of flexibility in
generating fine-grained frequency. In addition, there are five
16-bit fractional dividers and one 24-bit fractional divider.
IMO Clock Source
The IMO is the primary source of internal clocking in the
PSoC 4100S Plus. It is trimmed during testing to achieve the
specified accuracy.The IMO default frequency is 24 MHz and it
can be adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO
tolerance with Cypress-provided calibration settings is ±2% over
the entire voltage and temperature range.
ILO Clock Source
The ILO is a very low power, nominally 40-kHz oscillator, which
is primarily used to generate clocks for the watchdog timer
(WDT) and peripheral operation in Deep Sleep mode. ILO-driven
counters can be calibrated to the IMO to improve accuracy.
Cypress provides a software component, which does the
calibration.
Page 6 of 42
PSoC® 4: PSoC 4100S Plus
Datasheet
PRELIMINARY
Watch Crystal Oscillator (WCO)
The PSoC 4100S Plus clock subsystem also implements a
low-frequency (32-kHz watch crystal) oscillator that can be used
for precision timing applications.
External Crystal Oscillators (ECO)
The PSoC 4100S Plus also implements a 4 to 33 MHz crystal
oscillator.
scan to be completed and the CPU to read the values and check
for out-of-range values in software.
The SAR is not available in Deep Sleep mode as it requires a
high-speed clock (up to 18 MHz). The SAR operating range is
1.71 V to 5.5 V.
Figure 4. SAR ADC
AHB System Bus and Programmable Logic
Interconnect
Watchdog Timer
vminus vplus
SARMUX
SARMUX Port
(Up to 16 inputs)
A watchdog timer is implemented in the clock block running from
the ILO; this allows watchdog operation during Deep Sleep and
generates a watchdog reset if not serviced before the set timeout
occurs. The watchdog reset is recorded in a Reset Cause
register, which is firmware readable.
SAR Sequencer
Sequencing
and Control
Data and
Status Flags
POS
SARADC
NEG
Reference
Selection
Reset
PSoC 4100S Plus can be reset from a variety of sources
including a software reset. Reset events are asynchronous and
guarantee reversion to a known state. The reset cause is
recorded in a register, which is sticky through reset and allows
software to determine the cause of the reset. An XRES pin is
reserved for external reset by asserting it active low. The XRES
pin has an internal pull-up resistor that is always enabled.
Analog Blocks
12-bit SAR ADC
The 12-bit, 1-Msps SAR ADC can operate at a maximum clock
rate of 18 MHz and requires a minimum of 18 clocks at that
frequency to do a 12-bit conversion.
The Sample-and-Hold (S/H) aperture is programmable allowing
the gain bandwidth requirements of the amplifier driving the SAR
inputs, which determine its settling time, to be relaxed if required.
It is possible to provide an external bypass (through a fixed pin
location) for the internal reference amplifier.
The SAR is connected to a fixed set of pins through an 8-input
sequencer. The sequencer cycles through selected channels
autonomously (sequencer scan) with zero switching overhead
(that is, aggregate sampling bandwidth is equal to 1 Msps
whether it is for a single channel or distributed over several
channels). The sequencer switching is effected through a state
machine or through firmware driven switching. A feature
provided by the sequencer is buffering of each channel to reduce
CPU interrupt service requirements. To accommodate signals
with varying source impedance and frequency, it is possible to
have different sample times programmable for each channel.
Also, signal range specification through a pair of range registers
(low and high range values) is implemented with a corresponding
out-of-range interrupt if the digitized value exceeds the
programmed range; this allows fast detection of out-of-range
values without the necessity of having to wait for a sequencer
Document Number: 002-19966 Rev. *E
VDDA /2
VDDA
External
Reference and
Bypass
(optional)
VREF
Inputs from other Ports
Two Opamps (Continuous-Time Block; CTB)
PSoC 4100S Plus has two opamps with Comparator modes
which allow most common analog functions to be performed
on-chip eliminating external components; PGAs, Voltage
Buffers, Filters, Trans-Impedance Amplifiers, and other functions
can be realized, in some cases with external passives. saving
power, cost, and space. The on-chip opamps are designed with
enough bandwidth to drive the Sample-and-Hold circuit of the
ADC without requiring external buffering.
Low-power Comparators (LPC)
PSoC 4100S Plus has a pair of low-power comparators, which
can also operate in Deep Sleep modes. This allows the analog
system blocks to be disabled while retaining the ability to monitor
external voltage levels during low-power modes. The
comparator outputs are normally synchronized to avoid
metastability unless operating in an asynchronous power mode
where the system wake-up circuit is activated by a comparator
switch event. The LPC outputs can be routed to pins.
Current DACs
PSoC 4100S Plus has two IDACs, which can drive any of the
pins on the chip. These IDACs have programmable current
ranges.
Analog Multiplexed Buses
PSoC 4100S Plus has two concentric independent buses that go
around the periphery of the chip. These buses (called amux
buses) are connected to firmware-programmable analog
switches that allow the chip's internal resources (IDACs,
comparator) to connect to any pin on the I/O Ports.
Page 7 of 42
PRELIMINARY
Programmable Digital Blocks
Smart I/O Block
The Smart I/O block is a fabric of switches and LUTs that allows
Boolean functions to be performed in signals being routed to the
pins of a GPIO port. The Smart I/O can perform logical operations on input pins to the chip and on signals going out as
outputs.
Fixed Function Digital Blocks
Timer/Counter/PWM (TCPWM) Block
The TCPWM block consists of a 16-bit counter with
user-programmable period length. There is a capture register to
record the count value at the time of an event (which may be an
I/O event), a period register that is used to either stop or
auto-reload the counter when its count is equal to the period
register, and compare registers to generate compare value
signals that are used as PWM duty cycle outputs. The block also
provides true and complementary outputs with programmable
offset between them to allow use as dead-band programmable
complementary PWM outputs. It also has a Kill input to force
outputs to a predetermined state; for example, this is used in
motor drive systems when an over-current state is indicated and
the PWM driving the FETs needs to be shut off immediately with
no time for software intervention. Each block also incorporates a
Quadrature decoder. There are eight TCPWM blocks in
PSoC 4100S Plus.
Serial Communication Block (SCB)
PSoC 4100S Plus has five serial communication blocks, which
can be programmed to have SPI, I2C, or UART functionality.
I2C Mode: The hardware I2C block implements a full
multi-master and slave interface (it is capable of multi-master
arbitration). This block is capable of operating at speeds of up to
400 kbps (Fast Mode) and has flexible buffering options to
reduce interrupt overhead and latency for the CPU. It also
supports EZI2C that creates a mailbox address range in the
memory of PSoC 4100S Plus and effectively reduces I2C
communication to reading from and writing to an array in
memory. In addition, the block supports an 8-deep FIFO for
receive and transmit which, by increasing the time given for the
CPU to read data, greatly reduces the need for clock stretching
caused by the CPU not having read data on time.
The I2C peripheral is compatible with the I2C Standard-mode and
Fast-mode devices as defined in the NXP I2C-bus specification
and user manual (UM10204). The I2C bus I/O is implemented
with GPIO in open-drain modes.
PSoC® 4: PSoC 4100S Plus
Datasheet
UART Mode: This is a full-feature UART operating at up to
1 Mbps. It supports automotive single-wire interface (LIN),
infrared interface (IrDA), and SmartCard (ISO7816) protocols, all
of which are minor variants of the basic UART protocol. In
addition, it supports the 9-bit multiprocessor mode that allows
addressing of peripherals connected over common RX and TX
lines. Common UART functions such as parity error, break
detect, and frame error are supported. An 8-deep FIFO allows
much greater CPU service latencies to be tolerated.
SPI Mode: The SPI mode supports full Motorola SPI, TI SSP
(adds a start pulse used to synchronize SPI Codecs), and
National Microwire (half-duplex form of SPI). The SPI block can
use the FIFO.
CAN
There is a CAN 2.0B block with support for TT-CAN.
GPIO
PSoC 4100S Plus has up to 54 GPIOs. The GPIO block implements the following:
■ Eight drive modes:
❐ Analog input mode (input and output buffers disabled)
❐ Input only
❐ Weak pull-up with strong pull-down
❐ Strong pull-up with weak pull-down
❐ Open drain with strong pull-down
❐ Open drain with strong pull-up
❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
■ Input threshold select (CMOS or LVTTL).
■ Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes
■ Selectable slew rates for dV/dt related noise control to improve
EMI
The pins are organized in logical entities called ports, which are
8-bit in width (less for Ports 5 and 6). During power-on and reset,
the blocks are forced to the disable state so as not to crowbar
any inputs and/or cause excess turn-on current. A multiplexing
network known as a high-speed I/O matrix is used to multiplex
between various signals that may connect to an I/O pin.
Data output and pin state registers store, respectively, the values
to be driven on the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled and each
I/O port has an interrupt request (IRQ) and interrupt service
routine (ISR) vector associated with it.
PSoC 4100S Plus is not completely compliant with the I2C spec
in the following respect:
■
GPIO cells are not overvoltage tolerant and, therefore, cannot
be hot-swapped or powered up independently of the rest of the
I2C system.
Document Number: 002-19966 Rev. *E
Page 8 of 42
PRELIMINARY
Special Function Peripherals
CapSense
CapSense is supported in the PSoC 4100S Plus through a
CapSense Sigma-Delta (CSD) block that can be connected to
any pins through an analog multiplex bus via analog switches.
CapSense function can thus be provided on any available pin or
group of pins in a system under software control. A PSoC
Creator component is provided for the CapSense block to make
it easy for the user.
Shield voltage can be driven on another analog multiplex bus to
provide water-tolerance capability. Water tolerance is provided
by driving the shield electrode in phase with the sense electrode
to keep the shield capacitance from attenuating the sensed
input. Proximity sensing can also be implemented.
The CapSense block has two IDACs, which can be used for
general purposes if CapSense is not being used (both IDACs are
available in that case) or if CapSense is used without water
tolerance (one IDAC is available).
PSoC® 4: PSoC 4100S Plus
Datasheet
LCD Segment Drive
PSoC 4100S Plus has an LCD controller, which can drive up to
4 commons and up to 50 segments. It uses full digital methods
to drive the LCD segments requiring no generation of internal
LCD voltages. The two methods used are referred to as Digital
Correlation and PWM. Digital Correlation pertains to modulating
the frequency and drive levels of the common and segment
signals to generate the highest RMS voltage across a segment
to light it up or to keep the RMS signal to zero. This method is
good for STN displays but may result in reduced contrast with TN
(cheaper) displays. PWM pertains to driving the panel with PWM
signals to effectively use the capacitance of the panel to provide
the integration of the modulated pulse-width to generate the
desired LCD voltage. This method results in higher power
consumption but can result in better results when driving TN
displays. LCD operation is supported during Deep Sleep
refreshing a small display buffer (4 bits; one 32-bit register per
port).
The CapSense block also provides a 10-bit Slope ADC function
which can be used in conjunction with the CapSense function.
The CapSense block is an advanced, low-noise, programmable
block with programmable voltage references and current source
ranges for improved sensitivity and flexibility. It can also use an
external reference voltage. It has a full-wave CSD mode that
alternates sensing to VDDA and ground to null out power-supply
related noise.
Document Number: 002-19966 Rev. *E
Page 9 of 42
PRELIMINARY
PSoC® 4: PSoC 4100S Plus
Datasheet
Pinouts
The following table provides the pin list for PSoC 4100S Plus for the 44-pin TQFP and 64-pin TQFP Normal and Fine Pitch packages.
64-TQFP
44-TQFP
Pin
Name
Pin
Name
39
P0.0
24
P0.0
40
P0.1
25
P0.1
41
P0.2
26
P0.2
42
P0.3
27
P0.3
43
P0.4
28
P0.4
44
P0.5
29
P0.5
45
P0.6
30
P0.6
46
P0.7
31
P0.7
47
XRES
32
XRES
48
VCCD
33
VCCD
49
VSSD
50
VDDD
34
VDDD
51
P5.0
52
P5.1
53
P5.2
54
P5.3
55
P5.5
56
VDDA
35
VDDA
57
VSSA
36
VSSA
58
P1.0
37
P1.0
59
P1.1
38
P1.1
60
P1.2
39
P1.2
61
P1.3
40
P1.3
62
P1.4
41
P1.4
63
P1.5
42
P1.5
64
P1.6
43
P1.6
1
P1.7
44
P1.7
1
VSSD
2
P2.0
2
P2.0
3
P2.1
3
P2.1
4
P2.2
4
P2.2
5
P2.3
5
P2.3
6
P2.4
6
P2.4
7
P2.5
7
P2.5
8
P2.6
8
P2.6
9
P2.7
9
P2.7
10
VSSD
10
VSSD
11
No Connect (NC)
12
P6.0
13
P6.1
Document Number: 002-19966 Rev. *E
Page 10 of 42
PRELIMINARY
64-TQFP
Pin
Name
14
P6.2
15
P6.4
16
P6.5
17
VSSD
17
VSSD
18
19
PSoC® 4: PSoC 4100S Plus
Datasheet
44-TQFP
Pin
Name
P3.0
11
P3.0
P3.1
12
P3.1
20
P3.2
13
P3.2
21
P3.3
14
P3.3
22
P3.4
15
P3.4
23
P3.5
16
P3.5
24
P3.6
17
P3.6
25
P3.7
18
P3.7
26
VDDD
19
VDDD
27
P4.0
20
P4.0
28
P4.1
21
P4.1
29
P4.2
22
P4.2
30
P4.3
23
P4.3
31
P4.4
32
P4.5
33
P4.6
34
P4.7
35
P5.6
36
P5.7
37
P7.0
38
P7.1
Descriptions of the Power pins are as follows:
VDDD: Power supply for the digital section.
VDDA: Power supply for the analog section.
VSSD, VSSA: Ground pins for the digital and analog sections respectively.
VCCD: Regulated digital supply (1.8 V ±5%)
VDD: Power supply to all sections of the chip
VSS: Ground for all sections of the chip
GPIOs by package:
Number
64 TQFP
44 TQFP
54
36
Document Number: 002-19966 Rev. *E
Page 11 of 42
PSoC® 4: PSoC 4100S Plus Datasheet
PRELIMINARY
Alternate Pin Functions
Each Port pin has can be assigned to one of multiple functions; it can, for example, be an analog I/O, a digital peripheral function, an LCD pin, or a CapSense pin. The pin
assignments are shown in the following table. Note that this is preliminary and subject to change.
Port/Pin
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P5.0
P5.1
P5.2
P5.3
Analog
lpcomp.in_p[0]
lpcomp.in_n[0]
lpcomp.in_p[1]
lpcomp.in_n[1]
wco.wco_in
wco.wco_out
exco.eco_in
exco.eco_out
Smart I/O
ACT #0
srss.ext_clk:0
tcpwm.line[0]:3
tcpwm.line[4]:2
tcpwm.line_compl[4]:2
tcpwm.line[5]:2
tcpwm.line_compl[5]:2
ACT #1
tcpwm.tr_in[0]
tcpwm.tr_in[1]
ACT #3
scb[2].uart_cts:0
scb[2].uart_rts:0
DS #2
scb[2].i2c_scl:0
scb[2].i2c_sda:0
scb[1].uart_rx:0
scb[1].uart_tx:0
scb[1].uart_cts:0
scb[1].uart_rts:0
scb[2].uart_rx:0
scb[2].uart_tx:0
scb[2].uart_tx:1
scb[1].i2c_scl:0
scb[1].i2c_sda:0
scb[2].uart_rx:1
scb[2].uart_tx:2
scb[2].uart_cts:1
scb[2].uart_rts:1
scb[2].i2c_scl:1
scb[2].i2c_sda:1
lpcomp.comp[0]:2
lpcomp.comp[1]:0
DS #3
scb[0].spi_select1:0
scb[0].spi_select2:0
scb[0].spi_select3:0
scb[2].spi_select0:1
scb[1].spi_mosi:1
scb[1].spi_miso:1
scb[1].spi_clk:1
scb[1].spi_select0:1
scb[2].spi_mosi:0
scb[2].spi_miso:0
scb[2].spi_clk:0
scb[2].spi_select0:0
scb[0].i2c_scl:0
scb[2].spi_select1:0
scb[2].spi_select2:0
scb[0].spi_mosi:1
scb[0].i2c_sda:0
scb[0].spi_miso:1
P5.4
P5.5
P1.0
ctb0_oa0+
SmartIo[2].io[0]
tcpwm.line[6]:2
tcpwm.line_compl[6]:2
tcpwm.line[2]:1
scb[0].uart_rx:1
P1.1
ctb0_oa0-
SmartIo[2].io[1]
tcpwm.line_compl[2]:1 scb[0].uart_tx:1
P1.2
ctb0_oa0_out
SmartIo[2].io[2]
P1.3
ctb0_oa1_out
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
scb[0].uart_cts:1
tcpwm.tr_in[2]
scb[2].i2c_scl:2
scb[0].spi_clk:1
SmartIo[2].io[3]
tcpwm.line_compl[3]:1 scb[0].uart_rts:1
tcpwm.tr_in[3]
scb[2].i2c_sda:2
scb[0].spi_select0:1
ctb0_oa1ctb0_oa1+
ctb0_oa0+
ctb0_oa1+
sar_ext_vref0
sar_ext_vref1
SmartIo[2].io[4]
SmartIo[2].io[5]
SmartIo[2].io[6]
SmartIo[2].io[7]
tcpwm.line[6]:1
tcpwm.line_compl[6]:1
tcpwm.line[7]:1
tcpwm.line_compl[7]:1
scb[3].i2c_scl:0
scb[3].i2c_sda:0
scb[0].spi_select1:1
scb[0].spi_select2:1
scb[0].spi_select3:1
scb[2].spi_clk:1
sarmux[0]
sarmux[1]
sarmux[2]
sarmux[3]
SmartIo[0].io[0]
SmartIo[0].io[1]
SmartIo[0].io[2]
SmartIo[0].io[3]
tcpwm.line[4]:0
tcpwm.line_compl[4]:0
tcpwm.line[5]:1
tcpwm.line_compl[5]:1
scb[1].i2c_scl:1
scb[1].i2c_sda:1
scb[1].spi_mosi:2
scb[1].spi_miso:2
scb[1].spi_clk:2
scb[1].spi_select0:2
Document Number: 002-19966 Rev. *E
tcpwm.line[3]:1
csd.comp
tcpwm.tr_in[4]
tcpwm.tr_in[5]
Page 12 of 42
PSoC® 4: PSoC 4100S Plus Datasheet
PRELIMINARY
Port/Pin
P2.4
P2.5
P2.6
Analog
sarmux[4]
sarmux[5]
sarmux[6]
Smart I/O
SmartIo[0].io[4]
SmartIo[0].io[5]
SmartIo[0].io[6]
ACT #0
ACT #1
tcpwm.line[0]:1
scb[3].uart_rx:1
tcpwm.line_compl[0]:1 scb[3].uart_tx:1
tcpwm.line[1]:1
scb[3].uart_cts:1
P2.7
sarmux[7]
SmartIo[0].io[7]
tcpwm.line_compl[1]:1 scb[3].uart_rts:1
SmartIo[1].io[0]
SmartIo[1].io[1]
SmartIo[1].io[2]
SmartIo[1].io[3]
SmartIo[1].io[4]
SmartIo[1].io[5]
SmartIo[1].io[6]
SmartIo[1].io[7]
tcpwm.line[4]:1
tcpwm.line_compl[4]:1
tcpwm.line[5]:0
tcpwm.line_compl[5]:0
tcpwm.line[6]:0
tcpwm.line_compl[6]:0
tcpwm.line[0]:0
tcpwm.line_compl[0]:0
tcpwm.line[1]:0
tcpwm.line_compl[1]:0
tcpwm.line[2]:0
tcpwm.line_compl[2]:0
tcpwm.line[3]:0
tcpwm.line_compl[3]:0
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P3.6
P3.7
P4.0
P4.1
P4.2
P4.3
P4.4
P4.5
P4.6
P4.7
P5.6
P5.7
P7.0
P7.1
P7.2
csd.vref_ext
csd.cshield
csd.cmod
csd.csh_tank
Document Number: 002-19966 Rev. *E
ACT #3
scb[3].uart_rx:0 can.can_tx_enb_n:0
scb[3].uart_tx:0
can.can_rx:0
scb[3].uart_cts:0
can.can_tx:0
scb[3].uart_rts:0
DS #2
DS #3
scb[1].spi_select1:1
scb[1].spi_select2:1
scb[1].spi_select3:1
lpcomp.comp[0]:0
scb[2].spi_mosi:1
scb[3].i2c_scl:1
scb[3].i2c_sda:1
scb[3].spi_mosi:0
scb[3].spi_miso:0
scb[3].spi_clk:0
scb[3].spi_select0:0
scb[3].spi_select1:0
scb[3].spi_select2:0
scb[1].spi_mosi:0
scb[1].spi_miso:0
scb[1].spi_clk:0
scb[1].spi_select0:0
scb[1].spi_select1:0
scb[1].spi_select2:0
scb[1].spi_select3:0
scb[2].spi_miso:1
scb[0].spi_mosi:0
scb[0].spi_miso:0
scb[0].spi_clk:0
scb[0].spi_select0:0
scb[0].spi_select1:2
scb[0].spi_select2:2
scb[0].spi_select3:2
scb[4].i2c_scl
scb[4].i2c_sda
scb[1].i2c_scl:2
scb[1].i2c_sda:2
cpuss.swd_data
cpuss.swd_clk
scb[1].uart_rx:1
scb[1].uart_tx:1
scb[1].uart_cts:1
scb[1].uart_rts:1
tcpwm.tr_in[6]
scb[0].uart_rx:0
can.can_rx:1
scb[0].uart_tx:0
can.can_tx:1
scb[0].uart_cts:0 can.can_tx_enb_n:1
scb[0].uart_rts:0
scb[4].uart_rx
scb[4].uart_tx
scb[4].uart_cts
scb[4].uart_rts
tcpwm.line[7]:0
tcpwm.line_compl[7]:0
tcpwm.line[0]:2
scb[3].uart_rx:2
tcpwm.line_compl[0]:2 scb[3].uart_tx:2
tcpwm.line[1]:2
scb[3].uart_cts:2
scb[4].spi_select3
lpcomp.comp[1]:1
scb[0].i2c_scl:1
scb[0].i2c_sda:1
lpcomp.comp[0]:1
lpcomp.comp[1]:2
scb[4].spi_mosi
scb[4].spi_miso
scb[4].spi_clk
scb[4].spi_select0
scb[4].spi_select1
scb[4].spi_select2
scb[3].i2c_scl:2
scb[3].i2c_sda:2
scb[2].spi_select3:0
scb[3].spi_mosi:1
scb[3].spi_miso:1
scb[3].spi_clk:1
Page 13 of 42
PSoC® 4: PSoC 4100S Plus
Datasheet
PRELIMINARY
Power
Mode 1: 1.8 V to 5.5 V External Supply
The following power system diagram shows the set of power
supply pins as implemented for the PSoC 4100S Plus. The
system has one regulator in Active mode for the digital circuitry.
There is no analog regulator; the analog circuits run directly from
the VDD input.
Figure 5. Power Supply Connections
VDDA
VDDD
VDDA
VSSA
Analog
Domain
VDDD
Mode 2: 1.8 V ±5% External Supply
VSSD
In this mode, PSoC 4100S Plus is powered by an external power
supply that must be within the range of 1.71 to 1.89 V; note that
this range needs to include the power supply ripple too. In this
mode, the VDD and VCCD pins are shorted together and
bypassed. The internal regulator can be disabled in the firmware.
Digital
Domain
Bypass capacitors must be used from VDDD to ground. The
typical practice for systems in this frequency range is to use a
capacitor in the 1-µF range, in parallel with a smaller capacitor
(0.1 µF, for example). Note that these are simply rules of thumb
and that, for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated to
design and obtain optimal bypassing.
VCCD
1.8 Volt
Regulator
In this mode, PSoC 4100S Plus is powered by an external power
supply that can be anywhere in the range of 1.8 to 5.5 V. This
range is also designed for battery-powered operation. For
example, the chip can be powered from a battery system that
starts at 3.5 V and works down to 1.8 V. In this mode, the internal
regulator of PSoC 4100S Plus supplies the internal logic and its
output is connected to the VCCD pin. The VCCD pin must be
bypassed to ground via an external capacitor (0.1 µF; X5R
ceramic or better) and must not be connected to anything else.
There are two distinct modes of operation. In Mode 1, the supply
voltage range is 1.8 V to 5.5 V (unregulated externally; internal
regulator operational). In Mode 2, the supply range is1.8 V ±5%
(externally regulated; 1.71 to 1.89, internal regulator bypassed).
An example of a bypass scheme is shown in the following
diagram.
Figure 6. External Supply Range from 1.8 V to 5.5 V with Internal Regulator Active
Power supply bypass connections example
1.8 V to 5.5 V
1.8 V to 5.5 V
VDDD
µF
1 F
VDDA
1 F
µF
0.1 F
µF
0.1 F
VCCD
µF
0.1 F
PSoC 4100S Plus
VSS
Document Number: 002-19966 Rev. *E
Page 14 of 42
PSoC® 4: PSoC 4100S Plus
Datasheet
PRELIMINARY
Electrical Specifications
Absolute Maximum Ratings
Table 1. Absolute Maximum Ratings[1]
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
VDDD_ABS
Digital supply relative to VSS
–0.5
–
6
SID2
VCCD_ABS
Direct digital core voltage input relative
to VSS
–0.5
–
1.95
SID3
VGPIO_ABS
GPIO voltage
–0.5
–
VDD+0.5
–
SID4
IGPIO_ABS
Maximum current per GPIO
–25
–
25
–
SID5
IGPIO_injection
GPIO injection current, Max for VIH >
VDDD, and Min for VIL < VSS
–0.5
–
0.5
BID44
ESD_HBM
Electrostatic discharge human body
model
2200
–
–
SID1
–
V
mA
–
Current injected
per pin
–
V
BID45
ESD_CDM
Electrostatic discharge charged device
model
500
–
–
BID46
LU
Pin current for latch-up
–140
–
140
–
mA
–
Device Level Specifications
All specifications are valid for –40 °C TA 85 °C and TJ 100 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
Table 2. DC Specifications
Typical values measured at VDD = 3.3 V and 25 °C.
Spec ID#
Parameter
Description
Min
Typ
Max
SID53
VDD
Power supply input voltage
1.8
–
5.5
SID255
VDD
Power supply input voltage (VCCD =
VDDD = VDDA)
1.71
–
1.89
SID54
VCCD
Output voltage (for core logic)
–
1.8
–
SID55
CEFC
External regulator voltage bypass
–
0.1
–
SID56
CEXC
Power supply bypass capacitor
–
1
–
Units
Details/
Conditions
Internally
regulated supply
V
Internally
unregulated
supply
–
µF
X5R ceramic or
better
X5R ceramic or
better
Active Mode, VDD = 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25 °C.
SID10
IDD5
Execute from flash; CPU at 6 MHz
–
1.8
2.7
SID16
IDD8
Execute from flash; CPU at 24 MHz
–
3.0
4.75
SID19
IDD11
Execute from flash; CPU at 48 MHz
–
5.4
6.85
Max is at 85 °C
and 5.5 V
mA
Max is at 85 °C
and 5.5 V
Max is at 85 °C
and 5.5 V
Note
1. Usage above the absolute maximum conditions listed in Table 1 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended
periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 002-19966 Rev. *E
Page 15 of 42
PSoC® 4: PSoC 4100S Plus
Datasheet
PRELIMINARY
Table 2. DC Specifications (continued)
Typical values measured at VDD = 3.3 V and 25 °C.
Spec ID#
Parameter
Description
Min
Typ
Max
Units
mA
Details/
Conditions
Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on)
SID22
IDD17
I2C wakeup WDT, and Comparators on
–
1.1
1.8
SID25
IDD20
I2C wakeup, WDT, and Comparators on
–
1.5
2.1
6 MHZ. Max is at
85 °C and 5.5 V
12 MHZ. Max is at
85 °C and 5.5 V
Sleep Mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed)
SID28
IDD23
I2C wakeup, WDT, and Comparators on
–
1.1
1.8
mA
6 MHZ. Max is at
85 °C and 1.89 V
SID28A
IDD23A
I2C wakeup, WDT, and Comparators on
–
1.5
2.1
mA
12 MHZ. Max is at
85 °C and 1.89 V
Deep Sleep Mode, VDD = 1.8 V to 3.6 V (Regulator on)
SID30
IDD25
I2C wakeup and WDT on; T = –40 °C to
60 °C
–
2.5
40
µA
T = –40 °C to
60 °C
SID31
IDD26
I2C wakeup and WDT on
–
2.5
125
µA
Max is at 3.6 V
and 85 °C
2.5
40
µA
T = –40 °C to
60 °C
2.5
125
µA
Max is at 5.5 V
and 85 °C
2.5
60
µA
T = –40 °C to
60 °C
Max is at 1.89 V
and 85 °C
Deep Sleep Mode, VDD = 3.6 V to 5.5 V (Regulator on)
SID33
IDD28
I2C wakeup and WDT on; T = –40 °C to
60 °C
–
SID34
IDD29
I2C wakeup and WDT on
–
Deep Sleep Mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed)
SID36
IDD31
I2C wakeup and WDT on; T = –40 °C to
60 °C
–
SID37
IDD32
I2C wakeup and WDT on
–
2.5
180
µA
IDD_XR
Supply current while XRES asserted
–
2
5
mA
Min
Typ
Max
Units
DC
–
48
MHz
XRES Current
SID307
–
Table 3. AC Specifications
Spec ID#
Parameter
Description
SID48
FCPU
CPU frequency
SID49[2]
TSLEEP
Wakeup from Sleep mode
–
0
–
SID50[2]
TDEEPSLEEP
Wakeup from Deep Sleep mode
–
35
–
Details/
Conditions
1.71 VDD 5.5
µs
Note
2. Guaranteed by characterization.
Document Number: 002-19966 Rev. *E
Page 16 of 42
PSoC® 4: PSoC 4100S Plus
Datasheet
PRELIMINARY
GPIO
Table 4. GPIO DC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID57
VIH[3]
Input voltage high threshold
0.7 VDDD
–
–
CMOS Input
SID58
VIL
Input voltage low threshold
–
–
CMOS Input
SID241
VIH[3]
LVTTL input, VDDD < 2.7 V
0.7 VDDD
0.3
VDDD
–
–
–
SID242
VIL
LVTTL input, VDDD < 2.7 V
–
–
0.3
VDDD
–
SID243
VIH[3]
LVTTL input, VDDD 2.7 V
2.0
–
–
–
SID244
VIL
LVTTL input, VDDD 2.7 V
–
–
0.8
SID59
VOH
Output voltage high level
VDDD –0.6
–
–
IOH = 4 mA at 3 V VDDD
SID60
VOH
Output voltage high level
VDDD –0.5
–
–
IOH = 1 mA at 1.8 V
VDDD
SID61
VOL
Output voltage low level
–
–
0.6
IOL = 4 mA at 1.8 V
VDDD
SID62
VOL
Output voltage low level
–
–
0.6
IOL = 10 mA at 3 V VDDD
SID62A
VOL
Output voltage low level
–
–
0.4
IOL = 3 mA at 3 V VDDD
SID63
RPULLUP
Pull-up resistor
3.5
5.6
8.5
SID64
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
SID65
IIL
Input leakage current (absolute
value)
–
–
2
nA
SID66
CIN
Input capacitance
–
–
7
pF
–
SID67[4]
VHYSTTL
Input hysteresis LVTTL
25
40
–
SID68[4]
VHYSCMOS
Input hysteresis CMOS
0.05 × VDDD
–
–
mV
VDD < 4.5 V
SID68A[4]
VHYSCMOS5V5 Input hysteresis CMOS
200
–
–
SID69[4]
IDIODE
Current through protection diode to
VDD/VSS
–
–
100
µA
–
SID69A[4]
ITOT_GPIO
Maximum total source or sink chip
current
–
–
200
mA
–
V
kΩ
–
–
–
25 °C, VDDD = 3.0 V
VDDD 2.7 V
VDD > 4.5 V
Table 5. GPIO AC Specifications
(Guaranteed by Characterization)
Spec ID#
Parameter
Description
Min
Typ
Max
SID70
TRISEF
Rise time in fast strong mode
2
–
12
SID71
TFALLF
Fall time in fast strong mode
2
–
12
SID72
TRISES
Rise time in slow strong mode
10
–
60
Units
ns
–
Details/
Conditions
3.3 V VDDD, Cload =
25 pF
3.3 V VDDD, Cload =
25 pF
3.3 V VDDD, Cload =
25 pF
Notes
3. VIH must not exceed VDDD + 0.2 V.
4. Guaranteed by characterization.
Document Number: 002-19966 Rev. *E
Page 17 of 42
PSoC® 4: PSoC 4100S Plus
Datasheet
PRELIMINARY
Table 5. GPIO AC Specifications (continued)
(Guaranteed by Characterization)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
–
Details/
Conditions
3.3 V VDDD, Cload =
25 pF
SID73
TFALLS
Fall time in slow strong mode
10
–
60
SID74
FGPIOUT1
GPIO FOUT; 3.3 V VDDD 5.5 V
Fast strong mode
–
–
33
90/10%, 25 pF load,
60/40 duty cycle
SID75
FGPIOUT2
GPIO FOUT; 1.71 VVDDD3.3 V
Fast strong mode
–
–
16.7
90/10%, 25 pF load,
60/40 duty cycle
SID76
FGPIOUT3
GPIO FOUT; 3.3 V VDDD 5.5 V
Slow strong mode
–
–
7
SID245
FGPIOUT4
GPIO FOUT; 1.71 V VDDD 3.3 V
Slow strong mode.
–
–
3.5
90/10%, 25 pF load,
60/40 duty cycle
SID246
FGPIOIN
GPIO input operating frequency;
1.71 V VDDD 5.5 V
–
–
48
90/10% VIO
MHz
90/10%, 25 pF load,
60/40 duty cycle
XRES
Table 6. XRES DC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
SID77
VIH
Input voltage high threshold
0.7 × VDDD
–
–
SID78
VIL
Input voltage low threshold
–
–
0.3 VDDD
SID79
RPULLUP
Pull-up resistor
–
60
SID80
CIN
Input capacitance
–
SID81[5]
VHYSXRES
Input voltage hysteresis
SID82
IDIODE
Current through protection diode
to VDD/VSS
Details/
Conditions
V
CMOS Input
–
kΩ
–
–
7
pF
–
–
100
–
mV
Typical hysteresis is
200 mV for VDD > 4.5 V
–
–
100
µA
Table 7. XRES AC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID83[5]
TRESETWIDTH
Reset pulse width
1
–
–
µs
–
BID194[5]
TRESETWAKE
Wake-up time from reset release
–
–
2.7
ms
–
Note
5. Guaranteed by characterization.
Document Number: 002-19966 Rev. *E
Page 18 of 42
PSoC® 4: PSoC 4100S Plus
Datasheet
PRELIMINARY
Analog Peripherals
CTBm Opamp
Table 8. CTBm Opamp Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
IDD
Opamp block current, External load
SID269
IDD_HI
power=hi
–
1100
1850
SID270
IDD_MED
power=med
–
550
950
SID271
IDD_LOW
power=lo
–
150
350
GBW
Load = 20 pF, 0.1 mA
VDDA = 2.7 V
SID272
GBW_HI
power=hi
6
–
–
SID273
GBW_MED
power=med
3
–
–
SID274
GBW_LO
power=lo
–
1
–
Input and output are
0.2 V to VDDA-0.2 V
IOUT_MAX
VDDA = 2.7 V, 500 mV from rail
SID275
IOUT_MAX_HI
power=hi
10
–
–
Output is 0.5 V to VDDA
-0.5 V
SID276
IOUT_MAX_MID
power=mid
10
–
–
SID277
IOUT_MAX_LO
power=lo
–
5
–
Output is 0.5 V to VDDA
-0.5 V
IOUT
VDDA = 1.71 V, 500 mV from rail
SID278
IOUT_MAX_HI
power=hi
4
–
–
Output is 0.5 V to VDDA
-0.5 V
SID279
IOUT_MAX_MID
power=mid
4
–
–
SID280
IOUT_MAX_LO
power=lo
–
2
–
IDD_Int
Opamp block current Internal Load
SID269_I
IDD_HI_Int
power=hi
–
1500
1700
SID270_I
IDD_MED_Int
power=med
–
700
900
IDD_LOW_Int
power=lo
–
–
–
–
GBW
VDDA = 2.7 V
–
–
–
–
GBW_HI_Int
power=hi
8
–
–
SID271_I
SID272_I
–
µA
–
–
Input and output are
0.2 V to VDDA-0.2 V
MHz
mA
mA
Input and output are
0.2 V to VDDA-0.2 V
Output is 0.5 V to VDDA
-0.5 V
Output is 0.5 V to
VDDA-0.5 V
Output is 0.5 V to
VDDA-0.5 V
–
µA
MHz
–
Output is 0.25 V to
VDDA-0.25 V
General opamp specs for both
internal and external modes
SID281
VIN
Charge-pump on, VDDA = 2.7 V
–0.05
–
VDDA-0
.2
SID282
VCM
Charge-pump on, VDDA = 2.7 V
–0.05
–
VDDA-0
.2
VOUT
VDDA = 2.7 V
Document Number: 002-19966 Rev. *E
–
V
–
Page 19 of 42
PSoC® 4: PSoC 4100S Plus
Datasheet
PRELIMINARY
Table 8. CTBm Opamp Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Details/
Conditions
Units
SID283
VOUT_1
power=hi, Iload=10 mA
0.5
–
VDDA
-0.5
–
SID284
VOUT_2
power=hi, Iload=1 mA
0.2
–
VDDA
-0.2
–
SID285
VOUT_3
power=med, Iload=1 mA
0.2
–
VDDA
-0.2
SID286
VOUT_4
power=lo, Iload=0.1 mA
0.2
–
VDDA
-0.2
–
SID288
VOS_TR
Offset voltage, trimmed
–1.0
0.5
1.0
High mode, input 0 V to
VDDA-0.2 V
SID288A
VOS_TR
Offset voltage, trimmed
–
1
–
SID288B
VOS_TR
Offset voltage, trimmed
–
2
–
SID290
VOS_DR_TR
Offset voltage drift, trimmed
–10
3
10
SID290A
VOS_DR_TR
Offset voltage drift, trimmed
–
10
–
SID290B
VOS_DR_TR
Offset voltage drift, trimmed
–
10
–
SID291
CMRR
DC
70
80
–
V
–
mV
Medium mode, input
0 V to VDDA-0.2 V
Low mode, input 0 V to
VDDA-0.2 V
µV/°C
µV/°C
dB
High mode
Medium mode
Low mode
Input is 0 V to
VDDA-0.2 V, Output is
0.2 V to VDDA-0.2 V
VDDD = 3.6 V,
high-power mode, input
is 0.2 V to VDDA-0.2 V
3
At 1 kHz, 10-mV ripple
70
85
–
VN2
Input-referred, 1 kHz, power=Hi
–
72
–
SID295
VN3
Input-referred, 10 kHz, power=Hi
–
28
–
Input and output are at
nV/rtHz 0.2 V to VDDA-0.2 V
SID296
VN4
Input-referred, 100 kHz, power=Hi
–
15
–
Input and output are at
0.2 V to VDDA-0.2 V
SID297
CLOAD
Stable up to max. load. Performance
specs at 50 pF.
–
–
125
pF
–
SID298
SLEW_RATE
Cload = 50 pF, Power = High, VDDA
= 2.7 V
6
–
–
V/µs
–
SID299
T_OP_WAKE
From disable to enable, no external
RC dominating
–
–
25
µs
–
SID299A
OL_GAIN
Open Loop Gain
–
90
–
dB
COMP_MODE
Comparator mode; 50 mV drive,
Trise=Tfall (approx.)
SID292
PSRR
SID294
Noise
Document Number: 002-19966 Rev. *E
Page 20 of 42
PSoC® 4: PSoC 4100S Plus
Datasheet
PRELIMINARY
Table 8. CTBm Opamp Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Details/
Conditions
Units
Input is 0.2 V to
VDDA-0.2 V
SID300
TPD1
Response time; power=hi
–
150
–
SID301
TPD2
Response time; power=med
–
500
–
SID302
TPD3
Response time; power=lo
–
2500
–
SID303
VHYST_OP
Hysteresis
–
10
–
mV
–
SID304
WUP_CTB
Wake-up time from Enabled to
Usable
–
–
25
µs
–
Deep Sleep
Mode
Mode 2 is lowest current range.
Mode 1 has higher GBW.
SID_DS_1
IDD_HI_M1
Mode 1, High current
–
1400
–
25 °C
SID_DS_2
IDD_MED_M1
Mode 1, Medium current
–
700
–
25 °C
200
–
ns
Input is 0.2 V to
VDDA-0.2 V
Input is 0.2 V to
VDDA-0.2 V
SID_DS_3
IDD_LOW_M1
Mode 1, Low current
–
SID_DS_4
IDD_HI_M2
Mode 2, High current
–
120
–
SID_DS_5
IDD_MED_M2
Mode 2, Medium current
–
60
–
25 °C
SID_DS_6
IDD_LOW_M2
Mode 2, Low current
–
15
–
25 °C
SID_DS_7
GBW_HI_M1
Mode 1, High current
–
4
–
20-pF load, no DC load
0.2 V to VDDA-0.2 V
SID_DS_8
GBW_MED_M1
Mode 1, Medium current
–
2
–
20-pF load, no DC load
0.2 V to VDDA-0.2 V
SID_DS_9
GBW_LOW_M1
Mode 1, Low current
–
0.5
–
20-pF load, no DC load
0.2 V to VDDA-0.2 V
SID_DS_10 GBW_HI_M2
Mode 2, High current
–
0.5
–
20-pF load, no DC load
0.2 V to VDDA-0.2 V
SID_DS_11 GBW_MED_M2
Mode 2, Medium current
–
0.2
–
20-pF load, no DC load
0.2 V to VDDA-0.2 V
SID_DS_12 GBW_Low_M2
Mode 2, Low current
–
0.1
–
20-pF load, no DC load
0.2 V to VDDA-0.2 V
SID_DS_13 VOS_HI_M1
Mode 1, High current
–
5
–
With trim 25 °C, 0.2 V to
VDDA-0.2 V
SID_DS_14 VOS_MED_M1
Mode 1, Medium current
–
5
–
With trim 25 °C, 0.2 V to
VDDA-0.2 V
SID_DS_15 VOS_LOW_M2
Mode 1, Low current
–
5
–
With trim 25 °C, 0.2 V to
VDDA-0.2 V
SID_DS_16 VOS_HI_M2
Mode 2, High current
–
5
–
With trim 25 °C, 0.2V to
VDDA-0.2 V
SID_DS_17 VOS_MED_M2
Mode 2, Medium current
–
5
–
With trim 25 °C, 0.2 V to
VDDA-0.2 V
SID_DS_18 VOS_LOW_M2
Mode 2, Low current
–
5
–
With trim 25 °C, 0.2 V to
VDDA-0.2 V
µA
MHz
mV
Document Number: 002-19966 Rev. *E
25 °C
25 °C
Page 21 of 42
PSoC® 4: PSoC 4100S Plus
Datasheet
PRELIMINARY
Table 8. CTBm Opamp Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
Details/
Conditions
SID_DS_19 IOUT_HI_M1
Mode 1, High current
–
10
–
Output is 0.5 V to
VDDA-0.5 V
SID_DS_20 IOUT_MED_M1
Mode 1, Medium current
–
10
–
Output is 0.5 V to
VDDA-0.5 V
SID_DS_21 IOUT_LOW_M1
Mode 1, Low current
–
4
–
SID_DS_22 IOUT_HI_M2
Mode 2, High current
–
1
–
SID_DS_23 IOU_MED_M2
Mode 2, Medium current
–
1
–
SID_DS_24 IOU_LOW_M2
Mode 2, Low current
–
0.5
–
mA
Output is 0.5 V to
VDDA-0.5 V
Comparator
Table 9. Comparator DC Specifications
Spec ID#
Parameter
Description
Min Typ
Max
Units
SID84
VOFFSET1
Input offset voltage, Factory trim
–
–
±10
SID85
VOFFSET2
Input offset voltage, Custom trim
–
–
±4
SID86
VHYST
Hysteresis when enabled
–
10
35
SID87
VICM1
Input common mode voltage in normal
mode
0
–
VDDD-0.1
SID247
VICM2
Input common mode voltage in low
power mode
0
–
VDDD
SID247A
VICM3
Input common mode voltage in ultra
low power mode
0
–
VDDD-1.15
SID88
CMRR
Common mode rejection ratio
50
–
–
SID88A
CMRR
Common mode rejection ratio
42
–
–
SID89
ICMP1
Block current, normal mode
–
–
400
SID248
ICMP2
Block current, low power mode
–
–
100
SID259
ICMP3
Block current in ultra low-power mode
–
–
6
SID90
ZCMP
DC Input impedance of comparator
35
–
–
MΩ
Units
Details/
Conditions
mV
Modes 1 and 2
V
VDDD ≥ 2.2 V at –40 °C
dB
VDDD ≥ 2.7V
VDDD ≤ 2.7V
µA
VDDD ≥ 2.2 V at –40 °C
Table 10. Comparator AC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
SID91
TRESP1
Response time, normal mode, 50 mV
overdrive
–
38
110
SID258
TRESP2
Response time, low power mode, 50 mV
overdrive
–
70
200
SID92
TRESP3
Response time, ultra-low power mode,
200 mV overdrive
–
2.3
15
Details/
Conditions
ns
µs
VDDD ≥ 2.2 V at –40 °C
Note
6. Guaranteed by characterization.
Document Number: 002-19966 Rev. *E
Page 22 of 42
PSoC® 4: PSoC 4100S Plus
Datasheet
PRELIMINARY
Temperature Sensor
Table 11. Temperature Sensor Specifications
Spec ID#
SID93
Parameter
Description
TSENSACC
Temperature sensor accuracy
Min
Typ
Max
Units
–5
±1
5
°C
Details /
Conditions
–40 to +85 °C
SAR ADC
Table 12. SAR ADC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Units
bits
Details/
Conditions
SAR ADC DC Specifications
SID94
A_RES
Resolution
–
–
12
SID95
A_CHNLS_S
Number of channels - single ended
–
–
16
SID96
A-CHNKS_D
Number of channels - differential
–
–
4
SID97
A-MONO
Monotonicity
–
–
–
SID98
A_GAINERR
Gain error
–
–
±0.1
%
With external
reference
SID99
A_OFFSET
Input offset voltage
–
–
2
mV
Measured with
1-V reference
SID100
A_ISAR
Current consumption
–
–
1
mA
SID101
A_VINS
Input voltage range - single ended
VSS
–
VDDA
V
SID102
A_VIND
Input voltage range - differential
VSS
–
VDDA
V
Diff inputs use
neighboring I/O
Yes
SID103
A_INRES
Input resistance
–
–
2.2
KΩ
SID104
A_INCAP
Input capacitance
–
–
10
pF
SID260
VREFSAR
Trimmed internal reference to SAR
–
–
TBD
V
SAR ADC AC Specifications
SID106
A_PSRR
Power supply rejection ratio
70
–
–
dB
SID107
A_CMRR
Common mode rejection ratio
66
–
–
dB
SID108
A_SAMP
Sample rate
–
–
1
Msps
SID109
A_SNR
Signal-to-noise and distortion ratio (SINAD)
65
–
–
dB
–
Measured at 1 V
FIN = 10 kHz
SID110
A_BW
Input bandwidth without aliasing
–
A_samp/2
kHz
SID111
A_INL
Integral non linearity. VDD = 1.71 to 5.5, 1 Msps –1.7
–
2
LSB
VREF = 1 to VDD
SID111A
A_INL
Integral non linearity. VDDD = 1.71 to 3.6, 1 Msps –1.5
–
1.7
LSB
VREF = 1.71 to
VDD
SID111B
A_INL
Integral non linearity. VDD = 1.71 to 5.5, 500 ksps –1.5
–
1.7
LSB
VREF = 1 to VDD
SID112
A_DNL
Differential non linearity. VDD = 1.71 to 5.5,
1 Msps
–1
2.2
LSB
VREF = 1 to VDD
SID112A
A_DNL
Differential non linearity. VDD = 1.71 to 3.6,
1 Msps
–1
2
LSB
VREF = 1.71 to
VDD
SID112B
A_DNL
Differential non linearity. VDD = 1.71 to 5.5,
500 ksps
–1
2.2
LSB
VREF = 1 to VDD
SID113
A_THD
Total harmonic distortion
–
–
–65
dB
SID261
FSARINTREF SAR operating speed without external reference
bypass
–
–
100
ksps
Document Number: 002-19966 Rev. *E
–
–
–
Fin = 10 kHz
12-bit resolution
Page 23 of 42
PSoC® 4: PSoC 4100S Plus
Datasheet
PRELIMINARY
CSD and IDAC
Table 13. CSD and IDAC Specifications
Description
Min
Typ
Max
Units
SYS.PER#3
SPEC ID#
VDD_RIPPLE
Parameter
Max allowed ripple on power supply,
DC to 10 MHz
–
–
±50
mV
VDD > 2 V (with ripple),
25 °C TA, Sensitivity =
0.1 pF
SYS.PER#16
VDD_RIPPLE_1.8
Max allowed ripple on power supply,
DC to 10 MHz
–
–
±25
mV
VDD > 1.75V (with ripple),
25 °C TA, Parasitic Capacitance (CP) < 20 pF,
Sensitivity ≥ 0.4 pF
SID.CSD.BLK
ICSD
Maximum block current
–
–
4000
µA
Maximum block current for
both IDACs in dynamic
(switching) mode including
comparators, buffer, and
reference generator
SID.CSD#15
VREF
Voltage reference for CSD and
Comparator
0.6
1.2
VDDA - 0.6
V
VDDA - 0.06 or 4.4,
whichever is lower
SID.CSD#15A
VREF_EXT
External Voltage reference for CSD
and Comparator
0.6
VDDA - 0.6
V
VDDA - 0.06 or 4.4,
whichever is lower
SID.CSD#16
IDAC1IDD
IDAC1 (7-bits) block current
–
–
1750
µA
SID.CSD#17
IDAC2IDD
IDAC2 (7-bits) block current
–
–
1750
µA
SID308
VCSD
Voltage range of operation
1.71
–
5.5
V
1.8 V ±5% or 1.8 V to 5.5 V
SID308A
VCOMPIDAC
Voltage compliance range of IDAC
0.6
–
VDDA –0.6
V
VDDA - 0.06 or 4.4,
whichever is lower
SID309
IDAC1DNL
DNL
–1
–
1
LSB
SID310
IDAC1INL
INL
–2
–
2
LSB
SID311
IDAC2DNL
DNL
–1
–
1
LSB
SID312
IDAC2INL
INL
–2
–
2
LSB
SID313
SNR
Ratio of counts of finger to noise.
Guaranteed by characterization
5
–
–
Ratio Capacitance range of 5 to
SID314
IDAC1CRT1
Output current of IDAC1 (7 bits) in
low range
4.2
–
5.4
µA
LSB = 37.5-nA typ
SID314A
IDAC1CRT2
Output current of IDAC1(7 bits) in
medium range
34
–
41
µA
LSB = 300-nA typ
SID314B
IDAC1CRT3
Output current of IDAC1(7 bits) in
high range
275
–
330
µA
LSB = 2.4-µA typ
SID314C
IDAC1CRT12
Output current of IDAC1 (7 bits) in
low range, 2X mode
8
–
10.5
µA
LSB = 75-nA typ
SID314D
IDAC1CRT22
Output current of IDAC1(7 bits) in
medium range, 2X mode
69
–
82
µA
LSB = 600-nA typ.
SID314E
IDAC1CRT32
Output current of IDAC1(7 bits) in
high range, 2X mode
540
–
660
µA
LSB = 4.8-µA typ
SID315
IDAC2CRT1
Output current of IDAC2 (7 bits) in
low range
4.2
–
5.4
µA
LSB = 37.5-nA typ
SID315A
IDAC2CRT2
Output current of IDAC2 (7 bits) in
medium range
34
–
41
µA
LSB = 300-nA typ
SID315B
IDAC2CRT3
Output current of IDAC2 (7 bits) in
high range
275
–
330
µA
LSB = 2.4-µA typ
SID315C
IDAC2CRT12
Output current of IDAC2 (7 bits) in
low range, 2X mode
8
–
10.5
µA
LSB = 75-nA typ
SID315D
IDAC2CRT22
Output current of IDAC2(7 bits) in
medium range, 2X mode
69
–
82
µA
LSB = 600-nA typ
SID315E
IDAC2CRT32
Output current of IDAC2(7 bits) in
high range, 2X mode
540
–
660
µA
LSB = 4.8-µA typ
SID315F
IDAC3CRT13
Output current of IDAC in 8-bit mode
in low range
8
–
10.5
µA
LSB = 37.5-nA typ
Document Number: 002-19966 Rev. *E
Details / Conditions
INL is ±5.5 LSB for VDDA <
2V
INL is ±5.5 LSB for VDDA <
2V
35 pF, 0.1-pF sensitivity. All
use cases. VDDA > 2 V.
Page 24 of 42
PSoC® 4: PSoC 4100S Plus
Datasheet
PRELIMINARY
Table 13. CSD and IDAC Specifications (continued)
Description
Min
Typ
Max
Units
SID315G
SPEC ID#
IDAC3CRT23
Parameter
Output current of IDAC in 8-bit mode
in medium range
69
–
82
µA
LSB = 300-nA typ
Details / Conditions
SID315H
IDAC3CRT33
Output current of IDAC in 8-bit mode
in high range
540
–
660
µA
LSB = 2.4-µA typ
SID320
IDACOFFSET
All zeroes input
–
–
1
LSB
SID321
IDACGAIN
Full-scale error less offset
–
–
±10
%
SID322
IDACMISMATCH1
Mismatch between IDAC1 and
IDAC2 in Low mode
–
–
9.2
LSB
LSB = 37.5-nA typ
SID322A
IDACMISMATCH2
Mismatch between IDAC1 and
IDAC2 in Medium mode
–
–
5.6
LSB
LSB = 300-nA typ
SID322B
IDACMISMATCH3
Mismatch between IDAC1 and
IDAC2 in High mode
–
–
6.8
LSB
LSB = 2.4-µA typ
SID323
IDACSET8
Settling time to 0.5 LSB for 8-bit IDAC
–
–
5
µs
Full-scale transition. No
external load
SID324
IDACSET7
Settling time to 0.5 LSB for 7-bit IDAC
–
–
5
µs
Full-scale transition. No
external load
SID325
CMOD
External modulator capacitor.
–
2.2
–
nF
5-V rating, X7R or NP0 cap
Polarity set by Source or
Sink. Offset is 2 LSBs for
37.5 nA/LSB mode
10-bit CapSense ADC
Table 14. 10-bit CapSense ADC Specifications
Spec ID#
SIDA94
Parameter
A_RES
Description
Resolution
Min
Typ
Max
–
–
10
Details/
Conditions
bits Auto-zeroing is required
every millisecond
Units
SIDA95
A_CHNLS_S
Number of channels - single ended
–
–
16
SIDA97
A-MONO
Monotonicity
–
–
–
Yes
SIDA98
A_GAINERR
Gain error
–
–
±3
%
SIDA99
A_OFFSET
Input offset voltage
–
–
±18
mV In VREF (2.4 V) mode
with VDDA bypass
capacitance of 10 µF
SIDA100
A_ISAR
Current consumption
SIDA101
A_VINS
Input voltage range - single ended
Defined by AMUX Bus
–
–
0.25
mA
VSSA
–
VDDA
V
In VREF (2.4 V) mode
with VDDA bypass
capacitance of 10 µF
SIDA103
A_INRES
Input resistance
–
2.2
–
KΩ
SIDA104
A_INCAP
Input capacitance
–
20
–
pF
SIDA106
A_PSRR
Power supply rejection ratio
–
60
–
dB
SIDA107
A_TACQ
Sample acquisition time
–
1
–
µs
SIDA108
A_CONV8
Conversion time for 8-bit resolution at
conversion rate = Fhclk/(2^(N+2)).
Clock frequency = 48 MHz.
–
–
21.3
µs
Does not include acquisition time. Equivalent to
44.8 ksps including
acquisition time.
SIDA108A
A_CONV10
Conversion time for 10-bit resolution at
conversion rate = Fhclk/(2^(N+2)).
Clock frequency = 48 MHz.
–
–
85.3
µs
Does not include acquisition time. Equivalent to
11.6 ksps including
acquisition time.
Document Number: 002-19966 Rev. *E
In VREF (2.4 V) mode
with VDDA bypass
capacitance of 10 µF
Page 25 of 42
PSoC® 4: PSoC 4100S Plus
Datasheet
PRELIMINARY
Table 14. 10-bit CapSense ADC Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Units
dB
Details/
Conditions
With 10-Hz input sine
wave, external 2.4-V
reference, VREF (2.4 V)
mode
SIDA109
A_SND
Signal-to-noise and Distortion ratio
(SINAD)
–
61
–
SIDA110
A_BW
Input bandwidth without aliasing
–
–
22.4
SIDA111
A_INL
Integral Non Linearity. 1 ksps
–
–
2
LSB VREF = 2.4 V or greater
SIDA112
A_DNL
Differential Non Linearity. 1 ksps
–
–
1
LSB
KHz 8-bit resolution
Digital Peripherals
Timer Counter Pulse-Width Modulator (TCPWM)
Table 15. TCPWM Specifications
Spec ID
SID.TCPWM.1
Parameter
ITCPWM1
Description
Block current consumption at 3 MHz
Min
–
Typ
–
Max
45
Units
Details/Conditions
All modes (TCPWM)
SID.TCPWM.2
ITCPWM2
Block current consumption at 12 MHz
–
–
155
μA
All modes (TCPWM)
SID.TCPWM.2A ITCPWM3
Block current consumption at 48 MHz
–
–
650
–
–
Fc
2/Fc
–
–
For all trigger events[7]
Minimum possible width
of Overflow, Underflow,
and CC (Counter equals
Compare value) outputs
SID.TCPWM.3
TCPWMFREQ
Operating frequency
SID.TCPWM.4
TPWMENEXT
Input trigger pulse width
SID.TCPWM.5
TPWMEXT
All modes (TCPWM)
MHz
Fc max = CLK_SYS
Maximum = 48 MHz
Output trigger pulse widths
2/Fc
–
–
SID.TCPWM.5A TCRES
Resolution of counter
1/Fc
–
–
SID.TCPWM.5B PWMRES
PWM resolution
1/Fc
–
–
Minimum pulse width of
PWM Output
SID.TCPWM.5C QRES
Quadrature inputs resolution
1/Fc
–
–
Minimum pulse width
between Quadrature
phase inputs
Description
Min
Typ
Max
ns
Minimum time between
successive counts
I2C
Table 16. Fixed I2C DC Specifications[7]
Spec ID
Parameter
SID149
II2C1
Block current consumption at 100 kHz
–
–
50
SID150
II2C2
Block current consumption at 400 kHz
–
–
135
SID151
II2C3
Block current consumption at 1 Mbps
–
–
310
II2C4
I2C
–
1
–
SID152
enabled in Deep Sleep mode
Units
Details/Conditions
–
µA
–
–
Table 17. Fixed I2C AC Specifications[7]
Spec ID
SID153
Parameter
FI2C1
Description
Bit rate
Min
Typ
Max
Units
Details/Conditions
–
–
1
Msps
–
Note
7. Guaranteed by characterization.
Document Number: 002-19966 Rev. *E
Page 26 of 42
PSoC® 4: PSoC 4100S Plus
Datasheet
PRELIMINARY
SPI
Table 18. SPI DC Specifications[8]
Spec ID
Parameter
Description
Min
Typ
Max
Units
SID163
ISPI1
Block current consumption at 1 Mbps
–
–
360
SID164
ISPI2
Block current consumption at 4 Mbps
–
–
560
SID165
ISPI3
Block current consumption at 8 Mbps
–
–
600
Description
Min
Typ
Max
Units
SPI Operating frequency (Master; 6X
Oversampling)
–
–
8
MHz
–
–
15
Details/Conditions
–
µA
–
–
Table 19. SPI AC Specifications[8]
Spec ID
SID166
Parameter
FSPI
Details/Conditions
Fixed SPI Master Mode AC Specifications
SID167
TDMO
MOSI Valid after SClock driving edge
SID168
TDSI
MISO Valid before SClock capturing
edge
–
20
–
–
SID169
THMO
Previous MOSI data hold time
0
–
–
Referred to Slave capturing
edge
–
ns
Full clock, late MISO
sampling
Fixed SPI Slave Mode AC Specifications
SID170
TDMI
MOSI Valid before Sclock Capturing
edge
40
–
–
SID171
TDSO
MISO Valid after Sclock driving edge
–
–
42 +
3*Tcpu
SID171A
TDSO_EXT
MISO Valid after Sclock driving edge
in Ext. Clk mode
–
–
48
–
SID172
THSO
Previous MISO data hold time
0
–
–
–
SID172A
TSSELSSCK
SSEL Valid to first SCK Valid edge
–
–
100
ns
–
Min
Typ
Max
Units
Details/Conditions
ns
TCPU = 1/FCPU
UART
Table 20. UART DC Specifications[8]
Spec ID
Parameter
Description
SID160
IUART1
Block current consumption at
100 Kbps
–
–
55
µA
–
SID161
IUART2
Block current consumption at
1000 Kbps
–
–
312
µA
–
Min
Typ
Max
Units
Details/Conditions
–
–
1
Mbps
–
Table 21. UART AC Specifications[8]
Spec ID
SID162
Parameter
FUART
Description
Bit rate
Note
8. Guaranteed by characterization.
Document Number: 002-19966 Rev. *E
Page 27 of 42
PSoC® 4: PSoC 4100S Plus
Datasheet
PRELIMINARY
LCD Direct Drive
Table 22. LCD Direct Drive DC Specifications[9]
Spec ID
Parameter
Description
Min
SID154
ILCDLOW
Operating current in low power mode
SID155
CLCDCAP
LCD capacitance per
segment/common driver
–
SID156
LCDOFFSET
Long-term segment offset
–
SID157
ILCDOP1
LCD system operating current Vbias
=5V
–
ILCDOP2
LCD system operating current Vbias
= 3.3 V
–
SID158
–
Typ
Max
Units
Details/Conditions
5
–
µA
16 4 small segment disp.
at 50 Hz
500
5000
pF
–
20
–
mV
–
2
–
mA
32 4 segments at 50 Hz
25 °C
32 4 segments at 50 Hz
25 °C
2
–
Min
Typ
Max
Units
Details/Conditions
10
50
150
Hz
–
Table 23. LCD Direct Drive AC Specifications[9]
Spec ID
SID159
Parameter
FLCD
Description
LCD frame rate
Note
9. Guaranteed by characterization.
Document Number: 002-19966 Rev. *E
Page 28 of 42
PSoC® 4: PSoC 4100S Plus
Datasheet
PRELIMINARY
Memory
Table 24. Flash DC Specifications
Spec ID
SID173
Parameter
VPE
Description
Min
Typ
Max
Units
Details/Conditions
1.71
–
5.5
V
–
Description
Min
Typ
Max
Units
Details/Conditions
Erase and program voltage
Table 25. Flash AC Specifications
Spec ID
Parameter
SID174
TROWWRITE[10]
Row (block) write time (erase and
program)
–
–
20
SID175
TROWERASE[10]
Row erase time
–
–
16
SID176
Row program time after erase
–
–
4
–
Bulk erase time (64 KB)
–
–
35
–
SID180[11]
TROWPROGRAM[10]
TBULKERASE[10]
TDEVPROG[10]
SID181[11]
FEND
Flash endurance
SID182[11]
FRET
SID178
Total device program time
Row (block) = 256 bytes
ms
–
–
–
7
Seconds
–
100 K
–
–
Cycles
–
Flash retention. TA 55 °C, 100 K
P/E cycles
20
–
–
SID182A[11] –
Flash retention. TA 85 °C, 10 K
P/E cycles
10
–
–
SID256
TWS48
Number of Wait states at 48 MHz
2
–
–
CPU execution from
Flash
SID257
TWS24
Number of Wait states at 24 MHz
1
–
–
CPU execution from
Flash
Min
Typ
Max
Units
1
–
67
V/ms
V
–
Years
–
System Resources
Power-on Reset (POR)
Table 26. Power On Reset (PRES)
Spec ID
Parameter
Description
SID.CLK#6 SR_POWER_UP Power supply slew rate
SID185[11]
VRISEIPOR
Rising trip voltage
0.80
–
1.5
SID186[11]
VFALLIPOR
Falling trip voltage
0.70
–
1.4
Details/Conditions
At power-up
–
–
Table 27. Brown-out Detect (BOD) for VCCD
Min
Typ
Max
Units
Details/Conditions
SID190[11]
Spec ID
VFALLPPOR
Parameter
BOD trip voltage in active and
sleep modes
Description
1.48
–
1.62
V
–
SID192[11]
VFALLDPSLP
BOD trip voltage in Deep Sleep
1.11
–
1.5
–
Notes
10. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
11. Guaranteed by characterization.
Document Number: 002-19966 Rev. *E
Page 29 of 42
PSoC® 4: PSoC 4100S Plus
Datasheet
PRELIMINARY
SWD Interface
Table 28. SWD Interface Specifications
Spec ID
Parameter
Description
Min
Typ
Max
Units
Details/Conditions
SWDCLK ≤ 1/3 CPU
clock frequency
SID213
F_SWDCLK1
3.3 V VDD 5.5 V
–
–
14
SID214
F_SWDCLK2
1.71 V VDD 3.3 V
–
–
7
SWDCLK ≤ 1/3 CPU
clock frequency
SID215[12]
T_SWDI_SETUP T = 1/f SWDCLK
0.25*T
–
–
–
SID216[12]
T_SWDI_HOLD
0.25*T
–
–
SID217[12]
T_SWDO_VALID T = 1/f SWDCLK
–
–
0.5*T
SID217A[12]
T_SWDO_HOLD T = 1/f SWDCLK
1
–
–
Min
Typ
Max
Units
Details/Conditions
MHz
T = 1/f SWDCLK
ns
–
–
–
Internal Main Oscillator
Table 29. IMO DC Specifications
(Guaranteed by Design)
Spec ID
Parameter
Description
SID218
IIMO1
IMO operating current at 48 MHz
–
–
250
µA
–
SID219
IIMO2
IMO operating current at 24 MHz
–
–
180
µA
–
Description
Min
Typ
Max
Units
Details/Conditions
Table 30. IMO AC Specifications
Spec ID
Parameter
SID223
FIMOTOL1
Frequency variation at 24, 32, and
48 MHz (trimmed)
–
–
±2
%
SID226
TSTARTIMO
IMO startup time
–
–
7
µs
–
SID228
TJITRMSIMO2
RMS jitter at 24 MHz
–
145
–
ps
–
Min
Typ
Max
Units
Details/Conditions
–
0.3
1.05
µA
–
Min
Typ
Max
Units
Details/Conditions
Internal Low-Speed Oscillator
Table 31. ILO DC Specifications
(Guaranteed by Design)
Spec ID
SID231
Parameter
IILO1
Description
ILO operating current
Table 32. ILO AC Specifications
Spec ID
SID234[12]
Parameter
TSTARTILO1
SID236[12] TILODUTY
SID237
FILOTRIM1
Description
ILO startup time
–
–
2
ms
–
ILO duty cycle
40
50
60
%
–
ILO frequency range
20
40
80
kHz
–
Note
12. Guaranteed by design.
Document Number: 002-19966 Rev. *E
Page 30 of 42
PSoC® 4: PSoC 4100S Plus
Datasheet
PRELIMINARY
Watch Crystal Oscillator (WCO)
Table 33. WCO Specifications
Min
Typ
Max
Units
SID398
Spec ID#
FWCO
Parameter
Crystal frequency
Description
–
32.768
–
kHz
Details / Conditions
SID399
FTOL
Frequency tolerance
–
50
250
ppm
SID400
ESR
Equivalent series resistance
–
50
–
kΩ
SID401
PD
Drive Level
–
–
1
µW
SID402
TSTART
Startup time
–
–
500
ms
SID403
CL
Crystal Load Capacitance
6
–
12.5
pF
SID404
C0
Crystal Shunt Capacitance
–
1.35
–
pF
SID405
IWCO1
Operating Current (high power mode)
–
–
8
uA
Min
Typ
Max
Units
Details/Conditions
With 20-ppm crystal
External Clock
Table 34. External Clock Specifications
Spec ID
SID305[13]
Parameter
Description
ExtClkFreq
External clock input frequency
0
–
48
MHz
–
SID306[13] ExtClkDuty
Duty cycle; measured at VDD/2
45
–
55
%
–
External Crystal Oscillator and PLL
Table 35. External Crystal Oscillator (ECO) Specifications
Spec ID
Min
Typ
Max
Units
Details/Conditions
SID316[13]
IECO1
Parameter
External clock input frequency
Description
–
–
1.5
mA
–
SID317[13]
FECO
Crystal frequency range
4
–
33
MHz
–
Min
Typ
Max
Units
Table 36. PLL Specifications
Spec ID#
Parameter
Description
Details / Conditions
SID410
IDD_PLL_48
In = 3 MHz, Out = 48 MHz
–
530
610
uA
SID411
IDD_PLL_24
In = 3 MHz, Out = 24 MHz
–
300
405
uA
SID412
Fpllin
PLL input frequency
1
–
48
MHz
SID413
Fpllint
PLL intermediate frequency; prescaler out
1
–
3
MHz
SID414
Fpllvco
VCO output frequency before post-divide
22.5
–
104
MHz
SID415
Divvco
VCO Output post-divider range; PLL
output frequency is Fpplvco/Divvco
1
–
8
SID416
Plllocktime
Lock time at startup
–
–
250
µs
SID417
Jperiod_1
Period jitter for VCO ≥ 67 MHz
–
–
150
ps
Guaranteed by design
SID416A
Jperiod_2
Period jitter for VCO ≤ 67 MHz
–
–
200
ps
Guaranteed by design
Min
Typ
Max
Units
Details/Conditions
3
–
4
Periods
–
System Clock
Table 37. Block Specs
Spec ID
SID262[13]
Parameter
TCLKSWITCH
Description
System clock source switching time
Note
13. Guaranteed by characterization.
Document Number: 002-19966 Rev. *E
Page 31 of 42
PSoC® 4: PSoC 4100S Plus
Datasheet
PRELIMINARY
Smart I/O
Table 38. Smart I/O Pass-through Time (Delay in Bypass Mode)
Spec ID#
Parameter
Description
SID252
PRG_BYPASS Max delay added by Smart I/O in
bypass mode
Min
–
Typ
–
Max
1.6
Units
ns
Details / Conditions
Units
Details/Conditions
CAN
Table 39. CAN Specifications
Spec ID
Parameter
Description
Min
Typ
Max
SID420
IDD_CAN
Block current consumption
–
–
200
µA
SID421
CAN_bits
CAN Bit rate
–
–
1
Mbps
Document Number: 002-19966 Rev. *E
Min 8-MHZ clock
Page 32 of 42
PSoC® 4: PSoC 4100S Plus
Datasheet
PRELIMINARY
Ordering Information
The marketing part numbers for the PSoC 4100S Plus devices are listed in the following table.
4126
4146
4127
4147
Flash (KB)
SRAM (KB)
Op-amp (CTBm)
CSD
10-bit CSD ADC
12-bit SAR ADC
SAR ADC Sample Rate
LP Comparators
TCPWM Blocks
SCB Blocks
ECO
CAN Controller
Smart I/Os
GPIO
44-TQFP (0.8-mm pitch)
64-TQFP (0.5-mm pitch)
64-TQFP (0.8-mm pitch)
CY8C4126AXI-S443
Packages
Max CPU Speed (MHz)
MPN
Category
Features
24
64
8
2
0
1
1
806 ksps
2
8
4
✔
0
24
36
✔
–
–
CY8C4126AZI-S445
24
64
8
2
0
1
1
806 ksps
2
8
5
✔
0
24
54
–
✔
–
CY8C4126AXI-S445
24
64
8
2
0
1
1
806 ksps
2
8
5
✔
0
24
54
–
–
✔
CY8C4126AZI-S455
24
64
8
2
1
1
1
806 ksps
2
8
5
✔
0
24
54
–
✔
–
CY8C4126AXI-S455
24
64
8
2
1
1
1
806 ksps
2
8
5
✔
0
24
54
–
–
✔
CY8C4146AXI-S443
48
64
8
2
0
1
1
1 Msps
2
8
4
✔
0
24
36
✔
–
–
CY8C4146AZI-S445
48
64
8
2
0
1
1
1 Msps
2
8
5
✔
0
24
54
–
✔
–
CY8C4146AXI-S445
48
64
8
2
0
1
1
1 Msps
2
8
5
✔
0
24
54
–
–
✔
CY8C4146AXI-S453
48
64
8
2
1
1
1
1 Msps
2
8
4
✔
0
24
36
✔
–
–
CY8C4146AZI-S455
48
64
8
2
1
1
1
1 Msps
2
8
5
✔
0
24
54
–
✔
–
CY8C4146AXI-S455
48
64
8
2
1
1
1
1 Msps
2
8
5
✔
0
24
54
–
–
✔
CY8C4127AXI-S443
24
128
16
2
0
1
1
806 ksps
2
8
4
✔
0
24
36
✔
–
–
CY8C4127AZI-S445
24
128
16
2
0
1
1
806 ksps
2
8
5
✔
0
24
54
–
✔
–
CY8C4127AXI-S445
24
128
16
2
0
1
1
806 ksps
2
8
5
✔
0
24
54
–
–
✔
CY8C4127AXI-S453
24
128
16
2
1
1
1
806 ksps
2
8
4
✔
0
24
36
✔
–
–
CY8C4127AZI-S455
24
128
16
2
1
1
1
806 ksps
2
8
5
✔
0
24
54
–
✔
–
CY8C4127AXI-S455
24
128
16
2
1
1
1
806 ksps
2
8
5
✔
0
24
54
–
–
✔
CY8C4147AXI-S443
48
128
16
2
0
1
1
1 Msps
2
8
4
✔
0
24
36
✔
–
–
CY8C4147AZI-S445
48
128
16
2
0
1
1
1 Msps
2
8
5
✔
0
24
54
–
✔
–
CY8C4147AXI-S445
48
128
16
2
0
1
1
1 Msps
2
8
5
✔
0
24
54
–
–
✔
CY8C4147AXI-S453
48
128
16
2
1
1
1
1 Msps
2
8
4
✔
0
24
36
✔
–
–
CY8C4147AZI-S455
48
128
16
2
1
1
1
1 Msps
2
8
5
✔
0
24
54
–
✔
–
CY8C4147AXI-S455
48
128
16
2
1
1
1
1 Msps
2
8
5
✔
0
24
54
–
–
✔
CY8C4147AZI-S465
48
128
16
2
0
1
1
1 Msps
2
8
5
✔
1
24
54
–
✔
–
CY8C4147AXI-S465
48
128
16
2
0
1
1
1 Msps
2
8
5
✔
1
24
54
–
–
✔
CY8C4147AZI-S475
48
128
16
2
1
1
1
1 Msps
2
8
5
✔
1
24
54
–
✔
–
CY8C4147AXI-S475
48
128
16
2
1
1
1
1 Msps
2
8
5
✔
1
24
54
–
–
✔
Document Number: 002-19966 Rev. *E
Page 33 of 42
PRELIMINARY
PSoC® 4: PSoC 4100S Plus
Datasheet
The nomenclature used in the preceding table is based on the following part numbering convention:
Field
Description
Values
CY8C
Cypress Prefix
Meaning
4
Architecture
4
PSoC 4
A
Family
1
4100 Family
B
CPU Speed
2
24 MHz
4
48 MHz
4
16 KB
5
32 KB
6
64 KB
7
128 KB
AX
TQFP (0.8-mm pitch)
C
Flash Capacity
DE
Package Code
AZ
TQFP (0.5-mm pitch)
LQ
QFN
PV
SSOP
FN
CSP
F
Temperature Range
I
Industrial
S
Series Designator
S
PSoC 4 S-Series
M
PSoC 4 M-Series
L
PSoC 4 L-Series
XYZ
Attributes Code
BL
PSoC 4 BLE-Series
000-999
Code of feature set in the specific family
The following is an example of a part number:
CY8C 4 A B C DE F – S XYZ
Example
Cypress Prefix
Architecture
4 : PSoC 4
1: 4100 Family
Family within Architecture
CPU Speed
4 : 48 MHz
5 : 32 KB
Flash Capacity
AZ/AX: TQFP
Package Code
I : Industrial
Temperature Range
Series Designator
Attributes Code
Document Number: 002-19966 Rev. *E
Page 34 of 42
PRELIMINARY
PSoC® 4: PSoC 4100S Plus
Datasheet
Packaging
The PSoC 4100S Plus will be offered in 44 TQFP, 64 TQFP Normal pitch, and 64 TQFP Fine Pitch packages.
Package dimensions and Cypress drawing numbers are in the following table.
Table 40. Package List
Spec ID#
Package
BID20
64-pin TQFP
14 × 14 × 1.4-mm height with 0.8-mm pitch
Description
51-85046
Package Dwg
BID27
64-pin TQFP
10 × 10 × 1.6-mm height with 0.5-mm pitch
51-85051
BID34A
44-pin TQFP
10 × 10 × 1.4-mm height with 0.8-mm pitch
51-85064
Table 41. Package Thermal Characteristics
Parameter
Description
Package
Min
Typ
Max
Units
TA
Operating ambient temperature
–40
25
85
°C
TJ
Operating junction temperature
–40
–
100
°C
TJA
Package θJA
44-pin TQFP
–
55.6
–
°C/Watt
TJC
Package θJC
44-pin TQFP
–
14.4
–
°C/Watt
TJA
Package θJA
64-pin TQFP (0.5-mm pitch)
–
46
–
°C/Watt
TJC
Package θJC
64-pin TQFP (0.5-mm pitch)
–
10
–
°C/Watt
TJA
Package θJA
64-pin TQFP (0.8-mm pitch)
–
36.8
–
°C/Watt
TJC
Package θJC
64-pin TQFP (0.8-mm pitch)
–
9.4
–
°C/Watt
Table 42. Solder Reflow Peak Temperature
Package
Maximum Peak
Temperature
Maximum Time at Peak Temperature
All
260 °C
30 seconds
Table 43. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-020
Package
MSL
All
MSL 3
Document Number: 002-19966 Rev. *E
Page 35 of 42
PRELIMINARY
PSoC® 4: PSoC 4100S Plus
Datasheet
Package Diagrams
Figure 7. 64-pin TQFP Package (0.8-mm Pitch) Outline
ș1
ș
ș2
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
A
1.60
A1
0.05
A2
1.35 1.40 1.45
0.15
D
15.75 16.00 16.25
D1
13.95 14.00 14.05
E
15.75 16.00 16.25
E1
13.95 14.00 14.05
R1
0.08
0.20
R2
0.08
0.20
ș
0°
7°
ș1
0°
ș2
11°
13°
12°
b
0.30 0.35 0.40
L
0.45 0.60 0.75
L2
L3
e
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.20
c
L1
NOTE:
1.00 REF
0.25 BSC
0.20
0.80 TYP
51-85046 *H
Document Number: 002-19966 Rev. *E
Page 36 of 42
PRELIMINARY
PSoC® 4: PSoC 4100S Plus
Datasheet
Figure 8. 64-pin TQFP Package (0.5-mm Pitch) Outline
51-85051 *D
Figure 9. 44-Pin TQFP Package Outline
51-85064 *G
Document Number: 002-19966 Rev. *E
Page 37 of 42
PRELIMINARY
PSoC® 4: PSoC 4100S Plus
Datasheet
Acronyms
Table 44. Acronyms Used in this Document
Acronym
Description
Table 44. Acronyms Used in this Document (continued)
Acronym
Description
ETM
embedded trace macrocell
FIR
finite impulse response, see also IIR
FPB
flash patch and breakpoint
FS
full-speed
GPIO
general-purpose input/output, applies to a PSoC
pin
arithmetic logic unit
HVI
high-voltage interrupt, see also LVI, LVD
analog multiplexer bus
IC
integrated circuit
API
application programming interface
IDAC
current DAC, see also DAC, VDAC
APSR
application program status register
IDE
integrated development environment
ARM®
advanced RISC machine, a CPU architecture
ATM
automatic thump mode
BW
bandwidth
CAN
Controller Area Network, a communications
protocol
abus
analog local bus
ADC
analog-to-digital converter
AG
analog global
AHB
AMBA (advanced microcontroller bus
architecture) high-performance bus, an ARM
data transfer bus
ALU
AMUXBUS
I2C,
or IIC
Inter-Integrated Circuit, a communications
protocol
IIR
infinite impulse response, see also FIR
ILO
internal low-speed oscillator, see also IMO
IMO
internal main oscillator, see also ILO
integral nonlinearity, see also DNL
CMRR
common-mode rejection ratio
INL
CPU
central processing unit
I/O
input/output, see also GPIO, DIO, SIO, USBIO
CRC
cyclic redundancy check, an error-checking
protocol
IPOR
initial power-on reset
IPSR
interrupt program status register
DAC
digital-to-analog converter, see also IDAC, VDAC
IRQ
interrupt request
DFB
digital filter block
ITM
instrumentation trace macrocell
DIO
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
LCD
liquid crystal display
DMIPS
Dhrystone million instructions per second
LIN
Local Interconnect Network, a communications
protocol.
DMA
direct memory access, see also TD
LR
link register
DNL
differential nonlinearity, see also INL
LUT
lookup table
DNU
do not use
LVD
low-voltage detect, see also LVI
DR
port write data registers
LVI
low-voltage interrupt, see also HVI
DSI
digital system interconnect
LVTTL
low-voltage transistor-transistor logic
DWT
data watchpoint and trace
MAC
multiply-accumulate
ECC
error correcting code
MCU
microcontroller unit
ECO
external crystal oscillator
MISO
master-in slave-out
EEPROM
electrically erasable programmable read-only
memory
NC
no connect
EMI
electromagnetic interference
NMI
nonmaskable interrupt
EMIF
external memory interface
NRZ
non-return-to-zero
EOC
end of conversion
NVIC
nested vectored interrupt controller
EOF
end of frame
NVL
nonvolatile latch, see also WOL
EPSR
execution program status register
ESD
electrostatic discharge
Document Number: 002-19966 Rev. *E
opamp
operational amplifier
PAL
programmable array logic, see also PLD
Page 38 of 42
PRELIMINARY
Table 44. Acronyms Used in this Document (continued)
Acronym
Description
PSoC® 4: PSoC 4100S Plus
Datasheet
Table 44. Acronyms Used in this Document (continued)
Acronym
Description
PC
program counter
SWV
single-wire viewer
PCB
printed circuit board
TD
transaction descriptor, see also DMA
PGA
programmable gain amplifier
THD
total harmonic distortion
PHUB
peripheral hub
TIA
transimpedance amplifier
PHY
physical layer
TRM
technical reference manual
PICU
port interrupt control unit
TTL
transistor-transistor logic
PLA
programmable logic array
TX
transmit
PLD
programmable logic device, see also PAL
UART
PLL
phase-locked loop
Universal Asynchronous Transmitter Receiver, a
communications protocol
PMDD
package material declaration data sheet
UDB
universal digital block
POR
power-on reset
PRES
precise power-on reset
PRS
pseudo random sequence
PS
port read data register
PSoC®
Programmable System-on-Chip™
PSRR
power supply rejection ratio
PWM
pulse-width modulator
RAM
random-access memory
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
RTL
register transfer language
RTR
remote transmission request
RX
receive
SAR
successive approximation register
SC/CT
switched capacitor/continuous time
SCL
I2C serial clock
SDA
I2C serial data
S/H
sample and hold
SINAD
signal to noise and distortion ratio
SIO
special input/output, GPIO with advanced
features. See GPIO.
SOC
start of conversion
SOF
start of frame
SPI
Serial Peripheral Interface, a communications
protocol
SR
slew rate
SRAM
static random access memory
SRES
software reset
SWD
serial wire debug, a test protocol
Document Number: 002-19966 Rev. *E
USB
Universal Serial Bus
USBIO
USB input/output, PSoC pins used to connect to
a USB port
VDAC
voltage DAC, see also DAC, IDAC
WDT
watchdog timer
WOL
write once latch, see also NVL
WRES
watchdog timer reset
XRES
external reset I/O pin
XTAL
crystal
Page 39 of 42
PRELIMINARY
PSoC® 4: PSoC 4100S Plus
Datasheet
Document Conventions
Units of Measure
Table 45. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
dB
decibel
fF
femto farad
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohour
kHz
kilohertz
k
kilo ohm
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
M
mega-ohm
Msps
megasamples per second
µA
microampere
µF
microfarad
µH
microhenry
µs
microsecond
µV
microvolt
µW
microwatt
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
nV
nanovolt
ohm
pF
picofarad
ppm
parts per million
ps
picosecond
s
second
sps
samples per second
sqrtHz
square root of hertz
V
volt
Document Number: 002-19966 Rev. *E
Page 40 of 42
PRELIMINARY
PSoC® 4: PSoC 4100S Plus
Datasheet
Revision History
Description Title: PSoC® 4: PSoC 4100S Plus Datasheet Programmable System-on-Chip (PSoC)
Document Number: 002-19966
Orig. of Submission
Revision
ECN
Description of Change
Change
Date
*E
5995731
WKA
12/15/2017 New release
Document Number: 002-19966 Rev. *E
Page 41 of 42
PRELIMINARY
PSoC® 4: PSoC 4100S Plus
Datasheet
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Arm® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Community | Projects | Video | Blogs | Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation 2017. This document is the property of Cypress Semiconductor Corporation and its subsidiaries, including Spansion LLC ("Cypress"). This document, including
any software or firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide.
Cypress reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual
property rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby
grants you under its copyright rights in the Software, a personal, non-exclusive, nontransferable license (without the right to sublicense) (a) for Software provided in source code form, to modify and
reproduce the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either
directly or indirectly through resellers and distributors), solely for use on Cypress hardware product units. Cypress also grants you a personal, non-exclusive, nontransferable, license (without the right
to sublicense) under those claims of Cypress's patents that are infringed by the Software (as provided by Cypress, unmodified) to make, use, distribute, and import the Software solely to the minimum
extent that is necessary for you to exercise your rights under the copyright license granted in the previous sentence. Any other use, reproduction, modification, translation, or compilation of the Software
is prohibited.
CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes to this document without further notice. Cypress does not
assume any liability arising out of the application or use of any product or circuit described in this document. Any information provided in this document, including any sample design information or
programming code, is provided only for reference purposes. It is the responsibility of the user of this document to properly design, program, and test the functionality and safety of any application
made of this information and any resulting product. Cypress products are not designed, intended, or authorized for use as critical components in systems designed or intended for the operation of
weapons, weapons systems, nuclear installations, life-support devices or systems, other medical devices or systems (including resuscitation equipment and surgical implants), pollution control or
hazardous substances management, or other uses where the failure of the device or system could cause personal injury, death, or property damage ("Unintended Uses"). A critical component is any
component of a device or system whose failure to perform can be reasonably expected to cause the failure of the device or system, or to affect its safety or effectiveness. Cypress is not liable, in whole
or in part, and Company shall and hereby does release Cypress from any claim, damage, or other liability arising from or related to all Unintended Uses of Cypress products. Company shall indemnify
and hold Cypress harmless from and against all claims, costs, damages, and other liabilities, including claims for personal injury or death, arising from or related to any Unintended Uses of Cypress
products.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners
Document Number: 002-19966 Rev. *E
Revised December 15, 2017
Page 42 of 42
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