CY8C4245PVS-482Z

PSoC™ 4: PSoC™ 4200 Features • • • • • • 32-bit MCU sub-system Low power 1.71 V to 5.5 V operation Capacitive sensing Serial communication Timing and pulse-width modulation Up to 24 programmable GPIOs Product validation Qualified for automotive applications with higher temperature requirements. Product validation according to AEC-Q100. Description PSoC™ 4 is a scalable and reconfigurable platform architecture for a family of mixed-signal programmable embedded system controllers with an Arm® Cortex™-M0 CPU, while being AEC-Q100 compliant. It combines programmable and re-configurable analog and digital blocks with flexible automatic routing. The PSoC™ 4200 product family, based on this platform, is a combination of a microcontroller with digital programmable logic, high-performance analog-to-digital conversion, opamp with Comparator mode, and standard communication and timing peripherals. The PSoC™ 4200 products will be fully upward compatible with members of the PSoC™ 4 platform for new applications and design needs. The programmable analog and digital subsystems allow flexibility and in-field tuning of the design. Datasheet www.infineon.com Please read the sections "Important notice" and "Warnings" at the end of this document 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 Table of contents Table of contents Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 Product validation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Table of contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1 Detailed features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 4 4.1 4.1.1 4.1.2 4.1.3 4.1.4 4.2 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.3 4.3.1 4.3.2 4.3.3 4.3.4 4.4 4.4.1 4.5 4.5.1 4.5.2 4.6 4.7 4.7.1 4.7.2 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 CPU and memory subsystem . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Flash . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 System resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Power system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 Clock system . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 IMO clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 ILO clock source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Analog blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12-bit SAR ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Opamp (CTBm block) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Low-power comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Programmable digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Universal digital blocks (UDBs) and port interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Fixed function digital . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Timer/Counter/PWM block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Serial Communication Blocks (SCB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Special function peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 LCD segment drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 CAPSENSE™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 5 Pinouts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 6 Power . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Datasheet 2 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 Table of contents 6.1 6.2 Unregulated external supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Regulated external supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 7 7.1 7.2 7.3 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Online . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Tools . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8 8.1 8.2 8.2.1 8.2.2 8.3 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.4 8.4.1 8.4.2 8.4.3 8.4.4 8.5 8.6 8.6.1 8.6.2 8.6.3 8.6.4 8.6.5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Device-level specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 GPIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 XRES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Analog peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Opamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 SAR ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 CSD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Digital peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Timer/Counter/PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 LCD direct drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 SPI specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 System resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Power-on-Reset (POR) with Brown Out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Voltage monitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 SWD interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Internal main oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Internal low-speed oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9 9.1 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 Part numbering conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10 Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 11 Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 12 Document conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 13 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 Disclaimer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Datasheet 3 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 1 Detailed features 1 Detailed features 32-bit MCU subsystem • Automotive Electronics Council (AEC) AEC-Q100 qualified • 48 MHz Arm™ Cortex®-M0 CPU with single cycle multiply • Up to 32 kB of flash with Read Accelerator • Up to 4 kB of SRAM Programmable analog • One opamp with reconfigurable high-drive external and high-bandwidth internal drive, Comparator mode, and ADC input buffering capability • 12-bit, 1-Msps SAR ADC with differential and single-ended modes; Channel Sequencer with signal averaging • Two current DACs (IDACs) for general-purpose or capacitive sensing applications on any pin • Two low-power comparators that operate in Deep Sleep Programmable digital • Four programmable logic blocks called universal digital blocks, (UDBs), each with 8 Macrocells and data path • Infineon-provided peripheral component library, user-defined state machines, and Verilog input Capacitive sensing • Infineon Capacitive Sigma-Delta (CSD) provides best-in-class SNR (>5:1) and water tolerance • Infineon-supplied software component makes capacitive sensing design easy • Automatic hardware tuning (SmartSense) Segment LCD drive • LCD drive supported on all pins (common or segment) • Operates in Deep Sleep mode with 4 bits per pin memory Serial communication • Two independent run-time reconfigurable serial communication blocks (SCBs) with reconfigurable I2C, SPI, UART, or LIN Slave 1.3, 2.1/2.2 functionality Timing and Pulse-Width modulation • Four 16-bit Timer/Counter Pulse-Width Modulator (TCPWM) blocks • Center-aligned, Edge, and Pseudo-random modes • Comparator-based triggering of Kill signals for motor drive and other high-reliability digital logic applications Up to 24 programmable GPIOs • 28-pin SSOP package • Any GPIO pin can be CAPSENSE™, LCD, analog, or digital • Drive modes, strengths, and slew rates are programmable Temperature ranges • A Grade: –40 °C to +85 °C • S Grade: –40 °C to +105 °C PSoC Creator design environment • Integrated Development Environment (IDE) provides schematic design entry and build (with analog and digital automatic routing) • Applications Programming Interface (API) component for all fixed-function and programmable peripherals Industry-standard tool compatibility • After schematic entry, development can be done with Arm-based industry-standard development tools Datasheet 4 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 2 Block diagram 2 Block diagram CPU Subsystem PSoC 4200 SWD 32-bit AHB-Lite Cortex M0 48 MHz FLASH Up to 32 kB SRAM Up to 4 kB ROM 4 kB FAST MUL NVIC, IRQMX Read Accelerator SRAM Controller ROM Controller System Resources SAR ADC (12-bit) UDB x1 SMX ... UDB x4 CTBm x1 1x OpAmp 2x LP Comparator Programmable Digital LCD Programmable Analog 2x SCB-I2C/SPI/UART Test DFT Logic DFT Analog Peripheral Interconnect (MMIO) PCLK Capsense Reset Reset Control XRES Peripherals 4x TCPWM Clock Clock Control WDT IMO ILO System Interconnect (Single Layer AHB) IOSS GPIO (5x ports) Power Sleep Control WIC POR LVD REF BOD PWRSYS NVLatches Port Interface & Digital System Interconnect (DSI) High Speed I/O Matrix Power Modes Active/Sleep Deep Sleep Hibernate 24x GPIOs IO Subsystem Figure 1 Datasheet Block diagram 5 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 3 Functional description 3 Functional description The PSoC™ 4200 devices include extensive support for programming, testing, debugging, and tracing both hardware and firmware. The Arm® Serial_Wire Debug (SWD) interface supports all programming and debug features of the device. Complete debug-on-chip functionality enables full-device debugging in the final system using the standard production device. It does not require special interfaces, debugging pods, simulators, or emulators. Only the standard programming connections are required to fully support debug. The PSoC Creator IDE provides fully integrated programming and debug support for the PSoC™ 4200 devices. The SWD interface is fully compatible with industrystandard third-party tools. With the ability to disable debug features, with very robust flash protection, and allowing customer-proprietary functionality to be implemented in on-chip programmable blocks, the PSoC™ 4200 family provides a level of security not possible with multi-chip application solutions or with microcontrollers. The debug circuits are enabled by default and can only be disabled in firmware. If not enabled, the only way to reenable them is to erase the entire device, clear flash protection, and reprogram the device with new firmware that enables debugging. Additionally, all device interfaces can be permanently disabled (device security) for applications concerned about phishing attacks due to a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash programming sequences. Because all programming, debug, and test interfaces are disabled when maximum device security is enabled, PSoC™ 4200 with device security enabled may not be returned for failure analysis. This is a trade-off PSoC™ 4200 allows the customer to make. Datasheet 6 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 4 Functional overview 4 Functional overview 4.1 CPU and memory subsystem 4.1.1 CPU The Cortex-M0 CPU in PSoC™ 4200 is part of the 32-bit MCU subsystem, which is optimized for low-power operation with extensive clock gating. It mostly uses 16-bit instructions and executes a subset of the Thumb-2 instruction set. This enables fully compatible binary upward migration of the code to higher performance processors such as the Cortex-M3 and M4, thus enabling upward compatibility. The Infineon implementation includes a hardware multiplier that provides a 32-bit result in one cycle. It includes a nested vectored interrupt controller (NVIC) block with 32 interrupt inputs and also includes a Wakeup Interrupt Controller (WIC). The WIC can wake the processor up from the Deep Sleep mode, allowing power to be switched off to the main processor when the chip is in the Deep Sleep mode. The Cortex-M0 CPU provides a Non-Maskable Interrupt (NMI) input, which is made available to the user when it is not in use for system functions requested by the user. The CPU also includes a debug interface, the serial wire debug (SWD) interface, which is a two-wire form of JTAG; the debug configuration used for PSoC™ 4200 has four break-point (address) comparators and two watchpoint (data) comparators. 4.1.2 Flash The PSoC™ 4200 device has a flash module with a flash accelerator, tightly coupled to the CPU to improve average access times from the flash block. The flash block is designed to deliver 1 wait-state (WS) access time at 48 MHz and with 0-WS access time at 24 MHz. The flash accelerator delivers 85% of single-cycle SRAM access performance on average. Part of the flash module can be used to emulate EEPROM operation if required. The PSoC™ 4200 flash supports the following flash protection modes at the Memory subsystem level. Open: No Protection. Factory default mode that the product is shipped in. Protected: User may change from Open to Protected. This mode disables Debug interface accesses. The mode can be set back to Open but only after completely erasing the flash. Kill: User may change from Open to Kill. This mode disables all Debug accesses. The part cannot be erased externally thus obviating the possibility of partial erasure by power interruption and potential malfunction and security leaks. This is an irrecvocable mode. In addition, Row level Read/Write protection is also supported to prevent inadvertent Writes as well as selectively block Reads. Flash Read/Write/Erase operations are always available for internal code using system calls. 4.1.3 SRAM SRAM memory is retained during Hibernate. 4.1.4 SROM A supervisory ROM that contains boot and configuration routines is provided. 4.2 System resources 4.2.1 Power system The power system is described in detail in the section Power. It provides assurance that voltage levels are as required for each respective mode and either delay mode entry (on power-on reset (POR), for example) until voltage levels are as required for proper function or generate resets (Brown-Out Detect (BOD)) or interrupts (Low Voltage Detect (LVD)). Datasheet 7 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 4 Functional overview PSoC™ 4200 operates with a single external supply over the range of 1.71 V to 5.5 V and has five different power modes, transitions between which are managed by the power system. The PSoC™ 4200 provides Sleep, Deep Sleep, Hibernate, and Stop low-power modes. 4.2.2 Clock system The PSoC™ 4200 clock system is responsible for providing clocks to all subsystems that require clocks and for switching between different clock sources without glitching. In addition, the clock system ensures that no metastable conditions occur. The clock system for PSoC™ 4200 consists of the IMO and the ILO internal oscillators and provision for an external clock. IMO HFCLK EXTCLK ILO HFCLK LFCLK Prescaler UDB Dividers UDBn Analog Divider SAR clock Peripheral Dividers Figure 2 SYSCLK PERXYZ_CLK PSoC™ 4200 MCU clocking architecture The HFCLK signal can be divided down (see Figure 2) to generate synchronous clocks for the UDBs, and the analog and digital peripherals. There are a total of 12 clock dividers for PSoC™ 4200, each with 16-bit divide capability; this allows eight to be used for the fixed-function blocks and four for the UDBs. The analog clock leads the digital clocks to allow analog events to occur before digital clock-related noise is generated. The 16-bit capability allows a lot of flexibility in generating fine-grained frequency values and is fully supported in PSoC Creator. When UDB-generated Pulse Interrupts are used, SYSCLK must equal HFCLK. 4.2.3 IMO clock source The IMO is the primary source of internal clocking in PSoC™ 4200. It is trimmed during testing to achieve the specified accuracy. Trim values are stored in nonvolatile latches (NVL). Additional trim settings from flash can be used to compensate for changes. The IMO default frequency is 24 MHz and it can be adjusted between 3 to 48 MHz in steps of 1 MHz. IMO Tolerance with Infineon-provided calibration settings is ±2%. Datasheet 8 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 4 Functional overview 4.2.4 ILO clock source The ILO is a very low power oscillator, which is primarily used to generate clocks for peripheral operation in Deep Sleep mode. ILO-driven counters can be calibrated to the IMO to improve accuracy. Infineon provides a software component, which does the calibration. 4.2.5 Watchdog timer A watchdog timer is implemented in the clock block running from the ILO; this allows watchdog operation during Deep Sleep and generates a watchdog reset if not serviced before the timeout occurs. The watchdog reset is recorded in the Reset Cause register. 4.2.6 Reset PSoC™ 4200 can be reset from a variety of sources including a software reset. Reset events are asynchronous and guarantee reversion to a known state. The reset cause is recorded in a register, which is sticky through reset and allows software to determine the cause of the Reset. An XRES pin is reserved for external reset to avoid complications with configuration and multiple pin functions during power-on or reconfiguration. The XRES pin has an internal pullup resistor that is always enabled. 4.2.7 Voltage reference The PSoC™ 4200 reference system generates all internally required references. A 1% voltage reference spec is provided for the 12-bit ADC. To allow better signal to noise ratios (SNR) and better absolute accuracy, it is possible to bypass the internal reference using a GPIO pin or to use an external reference for the SAR. 4.3 Analog blocks 4.3.1 12-bit SAR ADC The 12-bit 1 MSample/second SAR ADC can operate at a maximum clock rate of 18 MHz and requires a minimum of 18 clocks at that frequency to do a 12-bit conversion. The block functionality is augmented for the user by adding a reference buffer to it (trimmable to ±1%) and by providing the choice (for the PSoC™ 4200 case) of three internal voltage references: VDD, VDD/2, and VREF (nominally 1.024 V) as well as an external reference through a GPIO pin. The Sample-and-Hold (S/H) aperture is programmable allowing the gain bandwidth requirements of the amplifier driving the SAR inputs, which determine its settling time, to be relaxed if required. System performance will be 65 dB for true 12-bit precision providing appropriate references are used and system noise levels permit. To improve performance in noisy conditions, it is possible to provide an external bypass (through a fixed pin location) for the internal reference amplifier. The SAR is connected to a fixed set of pins through an 8-input sequencer. The sequencer cycles through selected channels autonomously (sequencer scan) and does so with zero switching overhead (that is, aggregate sampling bandwidth is equal to 1 Msps whether it is for a single channel or distributed over several channels). The sequencer switching is effected through a state machine or through firmware driven switching. A feature provided by the sequencer is buffering of each channel to reduce CPU interrupt service requirements. To accommodate signals with varying source impedance and frequency, it is possible to have different sample times programmable for each channel. Also, signal range specification through a pair of range registers (low and high range values) is implemented with a corresponding out-of-range interrupt if the digitized value exceeds the programmed range; this allows fast detection of out-of-range values without the necessity of having to wait for a sequencer scan to be completed and the CPU to read the values and check for out-of-range values in software. The SAR is able to digitize the output of the on-board temperature sensor for calibration and other temperaturedependent functions. The SAR is not available in Deep Sleep and Hibernate modes as it requires a high-speed clock (up to 18 MHz). The SAR operating range is 1.71 to 5.5 V. Datasheet 9 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 4 Functional overview AHB System Bus and Programmable Logic Interconnect SAR Sequencer vminus vplus Data and Status Flags POS SARADC NEG External Reference and Bypass (optional) Reference Selection P7 Port 2 (8 inputs) SARMUX P0 Sequencing and Control VDD/2 VDDD VREF Inputs from other Ports Figure 3 4.3.2 SAR ADC system diagram Opamp (CTBm block) PSoC™ 4200 has an opamp with Comparator mode which allow most common analog functions to be performed onchip eliminating external components; PGAs, Voltage Buffers, Filters, Trans-Impedance Amplifiers, and other functions can be realized with external passives saving power, cost, and space. The on-chip opamp is designed with enough bandwidth to drive the Sample-and-Hold circuit of the ADC without requiring external buffering. 4.3.3 Temperature sensor PSoC™ 4200 has one on-chip temperature sensor This consists of a diode, which is biased by a current source that can be disabled to save power. The temperature sensor is connected to the ADC, which digitizes the reading and produces a temperature value using Infineon supplied software that includes calibration and linearization. 4.3.4 Low-power comparators PSoC™ 4200 has a pair of low-power comparators, which can also operate in the Deep Sleep and Hibernate modes. This allows the analog system blocks to be disabled while retaining the ability to monitor external voltage levels during low-power modes. The comparator outputs are normally synchronized to avoid metastability unless operating in an asynchronous power mode (Hibernate) where the system wake-up circuit is activated by a comparator switch event. 4.4 Programmable digital 4.4.1 Universal digital blocks (UDBs) and port interfaces PSoC™ 4200 has four UDBs; the UDB array also provides a switched Digital System Interconnect (DSI) fabric that allows signals from peripherals and ports to be routed to and through the UDBs for communication and control. The UDB array is shown in the following figure. Datasheet 10 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 4 Functional overview System Interconnect CPU Sub-system Clocks 8 to 32 4 to 8 BUS IF IRQ IF Other Digital Signals in Chip Routing Channels DSI CLK IF Port Port PortIFIF IF DSI UDB UDB UDB UDB DSI High-Speed I/O Matrix UDBIF DSI Programmable Digital Subsystem Figure 4 UDB array UDBs can be clocked from a clock divider block, from a port interface (required for peripherals such as SPI), and from the DSI network directly or after synchronization. A port interface is defined, which acts as a register that can be clocked with the same source as the PLDs inside the UDB array. This allows faster operation because the inputs and outputs can be registered at the port interface close to the I/O pins and at the edge of the array. The port interface registers can be clocked by one of the I/Os from the same port. This allows interfaces such as SPI to operate at higher clock speeds by eliminating the delay for the port input to be routed over DSI and used to register other inputs (see Figure 5). The UDBs can generate interrupts (one UDB at a time) to the interrupt controller. The UDBs retain the ability to connect to any pin on the chip through the DSI. Datasheet 11 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 4 Functional overview High speed I/O matrix To Clock tree 8 Input registers 7 Digital GlobalClocks 3 DSI signals , 1 I/O signal 9 4 6 ... 0 6 ... 0 3 2 1 0 [1] 4 8 [1] [0] To DSI Figure 5 7 Enables [1] 8 Reset selector 2 block from UDB 4 Output registers [0] Clock selector 2 block from UDB 8 8 From DSI [1] From DSI Port interface 4.5 Fixed function digital 4.5.1 Timer/Counter/PWM block The Timer/Counter/PWM block consists of four 16-bit counters with user-programmable period length. There is a Capture register to record the count value at the time of an event (which may be an I/O event), a period register which is used to either stop or auto-reload the counter when its count is equal to the period register, and compare registers to generate compare value signals which are used as PWM duty cycle outputs. The block also provides true and complementary outputs with programmable offset between them to allow use as deadband programmable complementary PWM outputs. It also has a Kill input to force outputs to a predetermined state; for example, this is used in motor drive systems when an overcurrent state is indicated and the PWMs driving the FETs need to be shut off immediately with no time for software intervention. 4.5.2 Serial Communication Blocks (SCB) PSoC™ 4200 has two SCBs, which can each implement an I2C, UART, SPI, or LIN Slave interface. I2C mode: The hardware I2C block implements a full multi-master and slave interface (it is capable of multimaster arbitration). This block is capable of operating at speeds of up to 1 Mbps (Fast Mode Plus) and has flexible buffering options to reduce interrupt overhead and latency for the CPU. The FIFO mode is available in all channels and is very useful in the absence of DMA. The I2C peripheral is compatible with the I2C Standard-mode, Fast-mode, and Fast-mode Plus devices as defined in the NXP I2C-bus specification and user manual (UM10204). The I2C bus I/O is implemented with GPIO in open-drain modes. The I2C bus uses open-drain drivers for clock and data with pull-up resistors on the bus for clock and data connected to all nodes. Required Rise and Fall times for different I2C speeds are guaranteed by using appropriate pullup resistor values depending on VDD, Bus Capacitance, and resistor tolerance. For detailed information on how to calculate the optimum pull-up resistor value for your design, please refer to the UM10204 I2C bus specification and user manual, the newest revision is available at www.nxp.com. PSoC™ 4200 is not completely compliant with the I2C spec in the following respects: Datasheet 12 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 4 Functional overview • GPIO cells are not overvoltage tolerant and, therefore, cannot be hot-swapped or powered up independently of the rest of the I2C system. • Fast-mode Plus has an IOL specification of 20 mA at a VOL of 0.4 V. The GPIO cells can sink a maximum of 8 mA IOL with a VOL maximum of 0.6 V. • Fast-mode and Fast-mode Plus specify minimum Fall times, which are not met with the GPIO cell; Slow strong mode can help meet this spec depending on the Bus Load. • When the SCB is an I2C Master, it interposes an IDLE state between NACK and Repeated Start; the I2C spec defines Bus free as following a Stop condition so other Active Masters do not intervene but a Master that has just become activated may start an Arbitration cycle. • When the SCB is in I2C Slave mode, and Address Match on External Clock is enabled (EC_AM = 1) along with operation in the internally clocked mode (EC_OP = 0), then its I2C address must be even. UART mode: This is a full-feature UART operating at up to 1 Mbps. It supports automotive single-wire interface (LIN), infrared interface (IrDA), and SmartCard (ISO7816) protocols, all of which are minor variants of the basic UART protocol. In addition, it supports the 9-bit multiprocessor mode that allows addressing of peripherals connected over common RX and TX lines. Common UART functions such as parity error, break detect, and frame error are supported. An 8-deep FIFO allows much greater CPU service latencies to be tolerated. Note that hardware handshaking is not supported. This is not commonly used and can be implemented with a UDB-based UART in the system, if required. SPI mode: The SPI mode supports full Motorola SPI, TI SSP (essentially adds a start pulse used to synchronize SPI Codecs), and National Microwire (half-duplex form of SPI). The SPI block can use the FIFO and also supports an EzSPI mode in which data interchange is reduced to reading and writing an array in memory. LIN Slave mode: The LIN Slave mode uses the SCB hardware block and implements a full LIN slave interface. This LIN slave is compliant with LIN v1.3 and LIN v2.1/2.2 specification standards. It is certified by C&S GmbH based on the standard protocol and data link layer conformance tests. LIN slave can be operated at baud rates of up to ~20 Kbps with a maximum of 40-meter cable length. PSoC Creator software supports up to two LIN slave interfaces in the PSoC™ 4 device, providing built-in application programming interfaces (APIs) based on the LIN specification standard. 4.6 GPIO PSoC™ 4200 has 24 GPIOs. The GPIO block implements the following: • Eight drive strength modes: - Analog input mode (input and output buffers disabled) - Input only - Weak pull-up with strong pull-down - Strong pull-up with weak pull-down - Open drain with strong pull-down - Open drain with strong pull-up - Strong pull-up with strong pull-down - Weak pull-up with weak pull-down • Input threshold select (CMOS or LVTTL). • Individual control of input and output buffer enabling/disabling in addition to the drive strength modes. • Hold mode for latching previous state (used for retaining I/O state in Deep Sleep mode and Hibernate modes). • Selectable slew rates for dV/dt related noise control to improve EMI. The pins are organized in logical entities called ports, which are 8-bit in width. During power-on and reset, the blocks are forced to the disable state so as not to crowbar any inputs and/or cause excess turn-on current. A multiplexing network known as a high-speed I/O matrix is used to multiplex between various signals that may connect to an I/O pin. Pin locations for fixed-function peripherals are also fixed to reduce internal multiplexing complexity (these signals do not go through the DSI network). DSI signals are not affected by this and any pin may be routed to any UDB through the DSI network. Datasheet 13 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 4 Functional overview Data output and pin state registers store, respectively, the values to be driven on the pins and the states of the pins themselves. Every I/O pin can generate an interrupt if so enabled and each I/O port has an interrupt request (IRQ) and interrupt service routine (ISR) vector associated with it (5 for PSoC™ 4200). 4.7 Special function peripherals 4.7.1 LCD segment drive PSoC™ 4200 has an LCD controller which can drive up to four commons and up to 32 segments. It uses full digital methods to drive the LCD segments requiring no generation of internal LCD voltages. The two methods used are referred to as digital correlation and PWM. Digital correlation pertains to modulating the frequency and levels of the common and segment signals to generate the highest RMS voltage across a segment to light it up or to keep the RMS signal zero. This method is good for STN displays but may result in reduced contrast with TN (cheaper) displays. PWM pertains to driving the panel with PWM signals to effectively use the capacitance of the panel to provide the integration of the modulated pulse-width to generate the desired LCD voltage. This method results in higher power consumption but can result in better results when driving TN displays. LCD operation is supported during Deep Sleep refreshing a small display buffer (4 bits; 1 32-bit register per port). 4.7.2 CAPSENSE™ CAPSENSE™ is supported on all pins in PSoC™ 4200 through a CapSense Sigma-Delta (CSD) block that can be connected to any pin through an analog mux bus that any GPIO pin can be connected to via an Analog switch. CapSense function can thus be provided on any pin or group of pins in a system under software control. A component is provided for the CAPSENSE™ block to make it easy for the user. Shield voltage can be driven on another Mux Bus to provide water tolerance capability. Water tolerance is provided by driving the shield electrode in phase with the sense electrode to keep the shield capacitance from attenuating the sensed input. The CAPSENSE™ block has two IDACs which can be used for general purposes if CAPSENSE™ is not being used.(both IDACs are available in that case) or if CAPSENSE™ is used without water tolerance (one IDAC is available). Datasheet 14 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 5  Pinouts 5 Pinouts The following is the pin-list for PSoC™ 4200. Port 2 comprises of the high-speed Analog inputs for the SAR Mux. P1.7 is the optional external input and bypass for the SAR reference. Ports 3 and 4 contain the Digital Communication channels. All pins support CSD CapSense and Analog Mux Bus connections. Pins 28-SSOP Alternate functions for pins Pin description Name Type Pin Name Analog Alt 1 Alt 2 Alt 3 Alt 4 VSSD Power DN – – – – – – Digital Ground P2.2 GPIO 5 P2.2 sarmux.2 – – – – Port 2 Pin 2: gpio, lcd, csd, sarmux P2.3 GPIO 6 P2.3 sarmux.3 – – – – Port 2 Pin 3: gpio, lcd, csd, sarmux P2.4 GPIO 7 P2.4 sarmux.4 tcpwm0_p[ – 1] – – Port 2 Pin 4: gpio, lcd, csd, sarmux, pwm P2.5 GPIO 8 P2.5 sarmux.5 tcpwm0_n[ – 1] – – Port 2 Pin 5: gpio, lcd, csd, sarmux, pwm P2.6 GPIO 9 P2.6 sarmux.6 tcpwm1_p[ – 1] – – Port 2 Pin 6: gpio, lcd, csd, sarmux, pwm P2.7 GPIO 10 P2.7 sarmux.7 tcpwm1_n[ – 1] – – Port 2 Pin 7: gpio, lcd, csd, sarmux, pwm P3.0 GPIO 11 P3.0 – tcpwm0_p[ scb1_uart_ scb1_i2c_scl[ scb1_spi_mo Port 3 Pin 0: gpio, 0] rx[0] 0] si[0] lcd, csd, pwm, scb1 P3.1 GPIO 12 P3.1 – tcpwm0_n[ scb1_uart_ scb1_i2c_sd 0] tx[0] a[0] scb1_spi_mis Port 3 Pin 1: gpio, o[0] lcd, csd, pwm, scb1 P3.2 GPIO 13 P3.2 – tcpwm1_p[ – 0] swd_io scb1_spi_clk[ Port 3 Pin 2: gpio, 0] lcd, csd, pwm, scb1, swd P3.3 GPIO 14 P3.3 – tcpwm1_n[ – 0] swd_clk scb1_spi_ssel Port 3 Pin 3: gpio, _0[0] lcd, csd, pwm, scb1, swd P4.0 GPIO 15 P4.0 – – scb0_uart_ scb0_i2c_scl rx P4.1 GPIO 16 P4.1 – – scb0_uart_ scb0_i2c_sda scb0_spi_mis Port 4 Pin 1: gpio, tx o lcd, csd, scb0 P4.2 GPIO 17 P4.2 csd_c_m – od – – scb0_spi_clk P4.3 GPIO 18 P4.3 csd_c_sh – _tank – – scb0_spi_ssel Port 4 Pin 3: gpio, _0 lcd, csd, scb0 Datasheet 15 scb0_spi_mo Port 4 Pin 0: gpio, si lcd, csd, scb0 Port 4 Pin 2: gpio, lcd, csd, scb0 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 5  Pinouts Pins 28-SSOP Alternate functions for pins Name Type Pin Name Analog P0.0 GPIO 19 P0.0 P0.1 GPIO 20 P0.2 GPIO P0.3 Alt 1 Pin description Alt 2 Alt 3 Alt 4 comp1_i – np – – scb0_spi_ssel Port 0 Pin 0: gpio, _1 lcd, csd, scb0, comp P0.1 comp1_i – nn – – scb0_spi_ssel Port 0 Pin 1: gpio, _2 lcd, csd, scb0, comp 21 P0.2 comp2_i – np – – scb0_spi_ssel Port 0 Pin 2: gpio, _3 lcd, csd, scb0, comp GPIO 22 P0.3 comp2_i – nn – – – P0.6 GPIO 23 P0.6 – ext_clk – – scb1_spi_clk[ Port 0 Pin 6: gpio, 1] lcd, csd, scb1, ext_clk P0.7 GPIO 24 P0.7 – – – wakeup scb1_spi_ssel Port 0 Pin 7: gpio, _0[1] lcd, csd, scb1, wakeup XRES XRES 25 XRES – – – – – Chip reset, active low VCCD Power 26 VCCD – – – – – Regulated supply, connect to 1 µF cap or 1.8 V VDDD Power 27 VDDD – – – – – Common power supply (Analog and Digital) 1.8 V–5.5 V VSSA Power 28( VSS DN) – – – – – Analog Ground P1.0 GPIO 1 P1.0 ctb.oa0.i tcpwm2_p[ – np 1] – – Port 1 Pin 0: gpio, lcd, csd, ctb, pwm P1.1 GPIO 2 P1.1 ctb.oa0.i tcpwm2_n[ – nm 1] – – Port 1 Pin 1: gpio, lcd, csd, ctb, pwm P1.2 GPIO 3 P1.2 ctb.oa0. out – – Port 1 Pin 2: gpio, lcd, csd, ctb, pwm P1.7 GPIO 4 P1.7 ctb.oa1.i – np_alt ext_vref – – Port 1 Pin 7: gpio, lcd, csd, ext_ref tcpwm3_p[ – 1] – Port 0 Pin 3: gpio, lcd, csd, comp Notes: Datasheet 16 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 5  Pinouts 1. 2. tcpwm_p and tcpwm_n refer to tcpwm non-inverted and inverted outputs respectively. P3.2 and P3.3 are SWD pins after boot (reset). Descriptions of the pin functions are as follows: VDDD: Power supply for both analog and digital sections (where there is no VDDA pin). VDDA: Analog VDD pin where package pins allow; shorted to VDDD otherwise. VSSA: Analog ground pin where package pins allow; shorted to VSS otherwise VSS: Ground pin. VCCD: Regulated Digital supply (1.8 V ±5%). Port Pins can all be used as LCD Commons, LCD Segment drivers, or CSD sense and shield pins can be connected to AMUXBUS A or B or can all be used as GPIO pins that can be driven by firmware or DSI signals. The following package is supported: 28-pin SSOP. (GPIO)P1[0] (GPIO)P1[1] (GPIO)P1[2] (GPIO)P1[7] (GPIO)P2[2] (GPIO)P2[3] (GPIO)P2[4] (GPIO)P2[5] (GPIO)P2[6] (GPIO)P2[7] (GPIO)P3[0] (GPIO)P3[1] (GPIO)P3[2] (GPIO)P3[3] Figure 6 Datasheet 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP (Top View) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VSS VDDD VCCD XRES (GPIO)P0[7] (GPIO)P0[6] (GPIO)P0[3] (GPIO)P0[2] (GPIO)P0[1] (GPIO)P0[0] (GPIO)P4[3] (GPIO)P4[2] (GPIO)P4[1] (GPIO)P4[0] 28-pin SSOP pinout 17 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 6 Power 6 Power The following power system diagram shows the minimum set of power supply pins as implemented for PSoC™ 4200. The system has one regulator in Active mode for the digital circuitry. There is no analog regulator; the analog circuits run directly from the VDDA input. There are separate regulators for the Deep Sleep and Hibernate (lowered power supply and retention) modes. There is a separate low-noise regulator for the bandgap. The supply voltage range is 1.71 to 5.5 V with all functions and circuits operating over that range. Digital Domain VDDD VDDD VCCD 1.8 Volt Reg VSSD Figure 7 PSoC™ 4 power supply The PSoC™ 4200 family allows two distinct modes of power supply operation: Unregulated External Supply, and Regulated External Supply modes. 6.1 Unregulated external supply In this mode, the PSoC™ 4200 is powered by an External Power Supply that can be anywhere in the range of 1.8 to 5.5V. This range is also designed for battery-powered operation, for instance, the chip can be powered from a battery system that starts at 3.5V and works down to 1.8V. In this mode, the internal regulator of the PSoC™ 4200 supplies the internal logic and the VCCD output of the PSoC™ 4200 must be bypassed to ground via an external Capacitor (in the range of 1 to 1.6 µF; X5R ceramic or better). Bypass capacitors must be used from VDDD to ground, typical practice for systems in this frequency range is to use a capacitor in the 1 µF range in parallel with a smaller capacitor (0.1 µF for example). Note that these are simply rules of thumb and that, for critical applications, the PCB layout, lead inductance, and the Bypass capacitor parasitic should be simulated to design and obtain optimal bypassing. Power supply Bypass capacitors VDDD–VSS 0.1 µF ceramic capacitor (C2) plus bulk capacitor 1 to 10 µF (C1). Total Capacitance may be greater than 10 µF. VCCD–VSS 1 µF ceramic capacitor at the VCCD pin (C3) VREF–VSS (optional) The internal bandgap may be bypassed with a 1 µF to 10 µF capacitor. Total capacitance may be greater than 10 µF. Datasheet 18 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 6 Power Power supply Bypass capacitors VSS 0.1 µF C 2 C1 1µF VSS (GPIO )P1[0] ( GPIO )P1[1] (GPIO )P1[2] ( GPIO) P1[7] ( GPIO) P2[2] (GPIO ) P2[3] (GPIO ) P2[4] (GPIO ) P2[5] (GPIO) P2[6] ( GPIO) P2[7] ( GPIO) P3[0] (GPIO )P3[1] (GPIO )P3[2] (GPIO )P3[3] Figure 8 6.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP ( Top View) VSS 28 VDDD 27 VCCD26 25 24 23 22 21 20 19 18 17 16 15 XRES ( GPIO) P0[7] ( GPIO) P0[6] ( GPIO) P0[3] ( GPIO) P0[2] ( GPIO) P0[1] ( GPIO) P0[0] ( GPIO) P4[3] ( GPIO)P4[2] ( GPIO)P4[1] ( GPIO)P4[0] C3 1µF VSS 28-pin SSOP example Regulated external supply In this mode, PSoC™ 4200 is powered by an external power supply that must be within the range of 1.71 to 1.89 V (1.8 ± 5%); note that this range needs to include power supply ripple too. In this mode, VCCD, and VDDD pins are all shorted together and bypassed. The internal regulator is disabled in firmware. Datasheet 19 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 7 Development support 7 Development support The PSoC™ 4200 family has a rich set of documentation, development tools, and online resources to assist you during your development process. Visit webpage to find out more. 7.1 Documentation A suite of documentation supports the PSoC™ 4200 family to ensure that you can find answers to your questions quickly. This section contains a list of some of the key documents. Software user guide: A step-by-step guide for using PSoC Creator. The software user guide shows you how the PSoC Creator build process works in detail, how to use source control with PSoC Creator, and much more. Component datasheets: The flexibility of PSoC™ allows the creation of new peripherals (components) long after the device has gone into production. Component data sheets provide all of the information needed to select and use a particular component, including a functional description, API documentation, example code, and AC/DC specifications. Application notes: PSoC™ application notes discuss a particular application of PSoC™ in depth; examples include brushless DC motor control and on-chip filtering. Application notes often include example projects in addition to the application note document. Technical reference manual: The technical reference manual (TRM) contains all the technical detail you need to use a PSoC™ device, including a complete description of all PSoC™ registers. The TRM is available in the Documentation section in webpage. 7.2 Online In addition to print documentation, the Infineon PSoC™ forums connect you with fellow PSoC™ users and experts in PSoC™ from around the world, 24 hours a day, 7 days a week. 7.3 Tools With industry standard cores, programming, and debugging interfaces, the PSoC™ 4200 family is part of a development tool ecosystem. Visit us at PSoC Creator for the latest information on the revolutionary, easy to use PSoC Creator IDE, supported third party compilers, programmers, debuggers, and development kits. Datasheet 20 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications 8 Electrical specifications 8.1 Absolute maximum ratings Table 1 Absolute maximum ratings Spec ID# Parameter Description Min Typ Max Units Details/ conditions SID1 VDDD_ABS Digital supply relative to Vssd –0.5 – 6 V Absolute max SID2 VCCD_ABS Direct digital –0.5 core voltage input relative to Vssd – 1.95 V Absolute max SID3 VGPIO_ABS GPIO voltage –0.5 – VDD+0.5 V Absolute max SID4 IGPIO_ABS Maximum current per GPIO –25 – 25 mA Absolute max SID5 IGPIO_injection GPIO –0.5 injection current, Max for VIH > VDDD, and Min for VIL < VSS – 0.5 mA Absolute max, current injected per pin BID44 ESD_HBM Electrostatic 2200 discharge human body model – – V   BID45 ESD_CDM Electrostatic 500 discharge charged device model – – V   BID46 LU Pin current for latch-up – 200 mA   Note: Datasheet –200 Usage above the absolute maximum conditions listed in Table 1 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification. 21 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications 8.2 Device-level specifications All specifications are valid for –40 °C ≤ TA ≤ 85 °C for A grade devices and –40 °C ≤ TA ≤ 105 °C for S grade devices, except where noted. Specifications are valid for 1.71 V to 5.5 V, except where noted. Table 2 DC specifications Spec ID# Parameter Description SID53 VDD SID255 Min Typ Max Units Details/ conditions Power 1.8 supply input voltage(VDDA = VDDD = VDD) – 5.5 V With regulator enabled VDDD Power 1.71 supply input voltage unregulated 1.8 1.89 V Internally unregulated supply SID54 VCCD Output voltage (for core logic) – 1.8 – V   SID55 CEFC External regulator voltage bypass 1 1.3 1.6 μF X5R ceramic or better SID56 CEXC Power supply decoupling capacitor – 1 – μF X5R ceramic or better Active Mode, VDD = 1.71 V to 5.5 V. Typical values measured at VDD = 3.3 V SID9 IDD4 Execute from – Flash; CPU at 6 MHz – 2.8 mA   SID10 IDD5 Execute from – Flash; CPU at 6 MHz 2.2 – mA T = 25 °C SID12 IDD7 Execute from – Flash; CPU at 12 MHz – 4.2 mA   SID13 IDD8 Execute from – Flash; CPU at 12 MHz 3.7 – mA T = 25 °C SID16 IDD11 Execute from – Flash; CPU at 24 MHz 6.7 – mA T = 25 °C SID17 IDD12 Execute from – Flash; CPU at 24 MHz – 7.2 mA   (table continues...) Datasheet 22 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Table 2 (continued) DC specifications Spec ID# Parameter Description SID19 IDD14 SID20 IDD15 Min Typ Max Units Details/ conditions Execute from – Flash; CPU at 48 MHz 12.8 – mA T = 25 °C Execute from – Flash; CPU at 48 MHz – 13.8 mA   Sleep Mode, VDD = 1.7 V to 5.5 V SID25 IDD20 I2C wakeup, – WDT, and Comparators on. 6 MHz 1.3 1.8 mA VDD = 1.71 V to 5.5 V SID25A IDD20A I2C wakeup, – WDT, and Comparators on. 12 MHz 1.7 2.2 mA VDD = 1.71 V to 5.5 V μA Deep Sleep Mode, VDD = 1.8 V to 3.6V (Regulator on) SID31 IDD26 I2C wakeup and WDT on – 1.3 – SID32 IDD27 I2C wakeup and WDT on – – 45 μA – 1.5 15 μA μA Deep Sleep Mode, VDD = 3.6 V to 5.5 V SID34 IDD29 I2C wakeup and WDT on Deep Sleep Mode, VDD = 1.71 V to 1.89 V (Regulator bypassed) T = 25 °C T = 85 °C Typ at 25 °C Max at 85 °C SID37 IDD32 I2C wakeup and WDT on – 1.7 – SID38 IDD33 I2C wakeup and WDT on – – 60 μA T = 85 °C Deep Sleep Mode, +105 °C T = 25 °C SID33Q IDD28Q I2C wakeup – and WDT on. Regulator Off. – 135 μA VDD = 1.71 V to 1.89 V SID34Q IDD29Q I2C wakeup and WDT on – – 180 μA VDD = 1.8 V to 3.6 V SID35Q IDD30Q I2C wakeup and WDT on – – 140 μA VDD = 3.6 V to 5.5 V Hibernate Mode, VDD = 1.8 V to 3.6 V (Regulator on) (table continues...) Datasheet 23 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Table 2 (continued) DC specifications Spec ID# Parameter Description SID40 IDD35 SID41 SID43 Min Typ Max Units Details/ conditions GPIO & Reset – active 150 – nA T = 25 °C IDD36 GPIO & Reset – active – 1000 nA T = 85 °C IDD38 GPIO & Reset – active 150 – nA T = 25 °C Hibernate Mode, VDD = 1.71 V to 1.89 V (Regulator bypassed) SID46 IDD41 GPIO & Reset – active 150 – nA T = 25 °C SID47 IDD42 GPIO & Reset – active – 1000 nA T = 85 °C Hibernate Mode, +105 °C SID42Q IDD37Q Regulator Off – – 19.4 µA VDD = 1.71 V to 1.89 V SID43Q IDD38Q   – – 17 µA VDD = 1.8 V to 3.6 V SID44Q IDD39Q   – – 16 µA VDD = 3.6 V to 5.5 V IDD43A Stop Mode current; VDD = 3.3 V – 20 80 nA Typ at 25 °C Max at 85 °C Stop Mode current; VDD = 5.5 V – 20 750 nA Typ at 25 °C Max at 85 °C IDD43AQ Stop Mode current; VDD = 3.6 V – – 5645 nA   IDD_XR Supply – current while XRES asserted 2 5 mA   Stop Mode SID304 Stop Mode, +105 °C SID304Q XRES current SID307 Datasheet 24 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Table 3 AC specifications Spec ID# Parameter Description Min Typ Max Units Details/ Conditions SID48 FCPU CPU frequency DC – 48 MHz 1.71 ≤ VDD ≤ 5.5 SID49 TSLEEP Wakeup from sleep mode – 0 – µs Guaranteed by characterizat ion SID50 TDEEPSLEEP Wakeup from Deep Sleep mode – – 25 µs 24-MHz IMO. Guaranteed by characterizat ion SID51 THIBERNATE Wakeup from Hibernate and Stop modes – – 2 ms Guaranteed by characterizat ion SID52 TRESETWIDTH External reset pulse width 1 – – µs Guaranteed by characterizat ion 8.2.1 GPIO Min Typ Max Units Details/ conditions Table 4 GPIO DC specifications Spec ID# Parameter Description SID57 VIH1) Input voltage 0.7 × VDDD high threshold – – V CMOS Input SID58 VIL Input voltage – low threshold – 0.3 × VDDD V CMOS Input SID241 VIH1) LVTTL input, 0.7× VDDD VDDD < 2.7 V – – V   SID242 VIL LVTTL input, – VDDD < 2.7 V – 0.3 × VDDD V   SID243 VIH1) LVTTL input, 2.0 VDDD ≥ 2.7 V – – V   SID244 VIL LVTTL input, – VDDD ≥ 2.7 V – 0.8 V   (table continues...) Datasheet 25 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Table 4 (continued) GPIO DC specifications Spec ID# Parameter Description Min Typ Max Units Details/ conditions SID59 VOH Output voltage high level VDDD –0.6 – – V IOH = 4 mA at 3 V VDDD SID60 VOH Output voltage high level VDDD –0.5 – – V IOH = 1 mA at 1.8 V VDDD SID61 VOL Output voltage low level – – 0.6 V IOL = 4 mA at 1.8 V VDDD SID62 VOL Output voltage low level – – 0.6 V IOL = 8 mA at 3 V VDDD SID62A VOL Output voltage low level – – 0.4 V IOL = 3 mA at 3 V VDDD SID63 RPULLUP Pull-up resistor 3.5 5.6 8.5 kΩ   SID64 RPULLDOWN Pull-down resistor 3.5 5.6 8.5 kΩ   SID65 IIL Input leakage current (absolute value) – – 2 nA 25 °C, VDDD = 3.0 V SID65A IIL_CTBM Input leakage current (absolute value) for CTBM pins – – 4 nA   SID66 CIN Input capacitance – – 7 pF   SID67 VHYSTTL Input hysteresis LVTTL 25 40 – mV VDDD ≥ 2.7 V. Guaranteed by characterizat ion SID68 VHYSCMOS Input hysteresis CMOS 0.05 × VDDD – – mV Guaranteed by characterizat ion (table continues...) Datasheet 26 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Table 4 (continued) GPIO DC specifications Spec ID# Parameter Description Min Typ Max Units Details/ conditions SID69 IDIODE Current through protection diode to VDD/VSS – – 100 µA Guaranteed by characterizat ion SID69A ITOT_GPIO Maximum – Total Source or Sink Chip Current – 200 mA Guaranteed by characterizat ion SID70 TRISEF Rise time in fast strong mode 2 – 12 ns 3.3 V VDDD, Cload = 25 pF SID71 TFALLF Fall time in fast strong mode 2 – 12 ns 3.3 V VDDD, Cload = 25 pF SID72 TRISES Rise time in slow strong mode 10 – 60   3.3 V VDDD, Cload = 25 pF SID73 TFALLS Fall time in slow strong mode 10 – 60   3.3 V VDDD, Cload = 25 pF SID74 FGPIOUT1 GPIO Fout;3.3 V ≤ VDDD ≤ 5.5 V. Fast strong mode. – – 33 MHz 90/10%, 25 pF load, 60/40 duty cycle SID75 FGPIOUT2 GPIO Fout;1.7 V≤ VDDD≤ 3.3 V. Fast strong mode. – – 16.7 MHz 90/10%, 25 pF load, 60/40 duty cycle SID76 FGPIOUT3 GPIO Fout;3.3 V ≤ VDDD ≤ 5.5 V. Slow strong mode. – – 7 MHz 90/10%, 25 pF load, 60/40 duty cycle SID245 FGPIOUT4 GPIO Fout;1.7 V ≤ VDDD ≤ 3.3 V. Slow strong mode. – – 3.5 MHz 90/10%, 25 pF load, 60/40 duty cycle (table continues...) Datasheet 27 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Table 4 (continued) GPIO DC specifications Spec ID# Parameter Description SID246 FGPIOIN GPIO input – operating frequency; 1.71 V ≤ VDDD ≤ 5.5 V 1) Min Typ Max Units Details/ conditions – 48 MHz 90/10% VIO VIH must not exceed VDDD + 0.2 V. Table 5 GPIO AC specifications (Guaranteed by characterization) Spec ID# Parameter Description Min Typ Max Units Details/ conditions SID70 TRISEF Rise time in fast strong mode 2 – 12 ns 3.3 V VDDD, Cload = 25 pF SID71 TFALLF Fall time in fast strong mode 2 – 12 ns 3.3 V VDDD, Cload = 25 pF SID72 TRISES Rise time in slow strong mode 10 – 60   3.3 V VDDD, Cload = 25 pF SID73 TFALLS Fall time in slow strong mode 10 – 60   90/10%, 25 pF load, 60/40 duty cycle SID74 FGPIOUT1 GPIO Fout;3.3 V ≤ VDDD ≤ 5.5 V. Fast strong mode. – – 33 MHz 90/10%, 25 pF load, 60/40 duty cycle SID75 FGPIOUT2 GPIO Fout;1.7 V ≤ VDDD ≤ 3.3 V. Fast strong mode. – – 16.7 MHz 90/10%, 25 pF load, 60/40 duty cycle SID76 FGPIOUT3 GPIO Fout;3.3 V ≤ VDDD ≤ 5.5 V. Slow strong mode. – – 7 MHz 90/10%, 25 pF load, 60/40 duty cycle SID245 FGPIOUT4 GPIO Fout;1.7 V ≤ VDDD ≤ 3.3 V. Slow strong mode. – – 3.5 MHz 90/10%, 25 pF load, 60/40 duty cycle SID246 FGPIOIN GPIO input operating frequency; 1.71 V ≤ VDDD ≤ 5.5 V – – 48 MHz 90/10%, 25 pF load, 60/40 duty cycle Datasheet 28 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications 8.2.2 XRES Table 6 XRES DC specifications Spec ID# Parameter Description SID77 VIH SID78 Typ Max Units Details/ conditions Input voltage 0.7 ×VDDD high threshold – – V CMOS Input VIL Input voltage – low threshold – 0.3 ×VDDD V CMOS Input SID79 RPULLUP Pull-up resistor 3.5 5.6 8.5 kΩ   SID80 CIN Input capacitance – 3 – pF   SID81 VHYSXRES Input voltage – hysteresis 100 – mV Guaranteed by characterizat ion SID82 IDIODE Current through protection diode to VDDD/VSS – – 100 µA Guaranteed by characterizat ion Table 7 Min XRES AC specifications Spec ID# Parameter Description Min Typ Max Units Details/ conditions SID83 TRESETWIDTH Reset pulse width 1 – – µs Guaranteed by characterizat ion Datasheet 29 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications 8.3 Analog peripherals 8.3.1 Opamp Table 8 Opamp specifications (Guaranteed by characterization) Spec ID# Parameter Description Min Typ Max Units Details/ conditions   IDD Opamp block current. No load. – – – –   SID269 IDD_HI Power = high – 1100 1850 µA   SID270 IDD_MED Power = medium – 550 950 µA   SID271 IDD_LOW Power = low – 150 350 µA     GBW Load = 20 pF, – 0.1 mA. VDDA = 2.7 V – – –   SID272 GBW_HI Power = high 6 – – MHz   SID273 GBW_MED Power = medium 4 – – MHz   SID274 GBW_LO Power = low – 1 – MHz     IOUT_MAX VDDA ≥ 2.7 V, – 500 mV from rail – – –   SID275 IOUT_MAX_HI Power = high 10 – – mA   SID276 IOUT_MAX_MID Power = medium 10 – – mA   SID277 IOUT_MAX_LO Power = low – 5 – mA     IOUT VDDA = 1.71 V, – 500 mV from rail – – –   SID278 IOUT_MAX_HI Power = high 4 – – mA   SID279 IOUT_MAX_MID Power = medium 4 – – mA   SID280 IOUT_MAX_LO Power = low – 2 – mA   SID281 VIN Charge pump on, VDDA ≥ 2.7 V –0.05 – VDDA – 0.2 V   (table continues...) Datasheet 30 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Table 8 (continued) Opamp specifications (Guaranteed by characterization) Spec ID# Parameter Description Min Typ Max Units Details/ conditions SID282 VCM Charge pump on, VDDA ≥ 2.7 V –0.05 – VDDA – 0.2 V     VOUT VDDA ≥ 2.7 V – – –     SID283 VOUT_1 Power = 0.5 high, Iload=10 mA – VDDA – 0.5 V   SID284 VOUT_2 Power = 0.2 high, Iload=1 mA – VDDA – 0.2 V   SID285 VOUT_3 Power = medium, Iload=1 mA 0.2 – VDDA – 0.2 V   SID286 VOUT_4 Power = low, 0.2 Iload=0.1mA – VDDA – 0.2 V   SID288 VOS_TR Offset voltage, trimmed 1 ±0.5 1 mV High mode SID288A VOS_TR Offset voltage, trimmed – ±1 – mV Medium mode SID288B VOS_TR Offset voltage, trimmed – ±2 – mV Low mode SID290 VOS_DR_TR Offset –10 voltage drift, trimmed ±3 10 µV/°C SID290Q VOS_DR_TR Offset –15 voltage drift, trimmed ±3 15 μV/°C High mode.TA < 85 °C. SID290A VOS_DR_TR Offset – voltage drift, trimmed ±10 – µV/°C Medium mode SID290B VOS_DR_TR Offset – voltage drift, trimmed ±10 – µV/°C Low mode SID291 CMRR DC 70 80 – dB VDDD = 3.6 V SID292 PSRR At 1 kHz, 100 70 mV ripple 85 – dB VDDD = 3.6 V High mode.TA ≤ 105 °C (table continues...) Datasheet 31 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Table 8 (continued) Opamp specifications (Guaranteed by characterization) Spec ID# Parameter Description Min Typ Max Units Details/ conditions   Noise   – – – –   SID293 VN1 Input – referred, 1 Hz - 1GHz, power = high 94 – µVrms   SID294 VN2 Input – referred, 1 kHz, power = high 72 – nV/rtHz   SID295 VN3 Input – referred, 10kHz, power = high 28 – nV/rtHz   SID296 VN4 Input – referred, 100kHz, power = high 15 – nV/rtHz   SID297 Cload Stable up to – maximum load. Performance specs at 50 pF. – 125 pF   SID298 Slew_rate Cload = 50 pF, Power = High,VDDA ≥ 2.7 V – – V/µs   SID299 T_op_wake From disable – to enable, no external RC dominating 300 – µs     Comp_mode Comparator – mode; 50 mV drive, Trise = Tfall (approx.) – –     SID299A OL_GAIN Open Loop Gain – 90 – dB Guaranteed by Design SID300 TPD1 Response time; power = high – 150 – ns   6 (table continues...) Datasheet 32 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Table 8 (continued) Opamp specifications (Guaranteed by characterization) Spec ID# Parameter Description Min Typ Max Units Details/ conditions SID301 TPD2 Response time; power = medium – 400 – ns   SID302 TPD3 Response time; power = low – 2000 – ns   SID303 Vhyst_op Hysteresis – 10 – mV   8.3.2 Comparator Typ Max Units Details/ conditions Table 9 Comparator DC specifications Spec ID# Parameter Description SID85 VOFFSET2 Input offset – voltage, Common Mode voltage range from 0 to VDD-1 – ±4 mV   SID85A VOFFSET3 Input offset – voltage. Ultra lowpower mode (VDDD ≥ 2.2 V for Temp < 0 °C, VDDD ≥ 1.8 V for Temp > 0 °C) ±12 – mV   SID86 VHYST Hysteresis – when enabled, Common Mode voltage range from 0 to VDD -1. 10 35 mV Guaranteed by characterizat ion (table continues...) Datasheet Min 33 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Table 9 (continued) Comparator DC specifications Spec ID# Parameter Description Min Typ Max Units Details/ conditions SID87 VICM1 Input common mode voltage in normal mode 0 – VDDD – 0.1 V Modes 1 and 2. SID247 VICM2 Input 0 common mode voltage in low power mode (VDDD ≥ 2.2 V for Temp < 0 °C, VDDD ≥ 1.8 V for Temp > 0 °C) – VDDD V   SID247A VICM3 Input 0 common mode voltage in ultra low power mode – VDDD – 1.15 V   SID88 CMRR Common mode rejection ratio 50 – – dB VDDD ≥ 2.7 V. Guaranteed by characterizat ion SID88A CMRR Common mode rejection ratio 42 – – dB VDDD < 2.7 V. Guaranteed by characterizat ion SID89 ICMP1 Block current, normal mode – – 400 µA Guaranteed by characterizat ion SID248 ICMP2 Block – current, low power mode – 100 µA Guaranteed by characterizat ion (table continues...) Datasheet 34 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Table 9 (continued) Comparator DC specifications Spec ID# Parameter Description SID259 ICMP3 SID90 ZCMP Table 10 Min Typ Max Units Details/ conditions Block – current, ultra low power mode (VDDD ≥ 2.2 V for Temp < 0 °C, VDDD ≥ 1.8 V for Temp > 0 °C) 6 28 µA Guaranteed by characterizat ion DC input impedance of comparator – – MΩ Guaranteed by characterizat ion Typ Max Units Details/ conditions 35 Comparator AC specifications Guaranteed by characterization Spec ID# Parameter Description SID91 TRESP1 Response – time, normal mode – 110 ns 50 mV overdrive SID258 TRESP2 Response – time, low power mode – 200 ns 50 mV overdrive SID92 TRESP3 Response – time, ultra low power mode(VDDD ≥ 2.2 V for Temp < 0 °C, VDDD ≥ 1.8 V for Temp > 0 °C) – 15 µs 200 mV overdrive 8.3.3 Temperature sensor Typ Max Units Details/ conditions ±1 +5 °C –40 to +85 °C Table 11 Min Temperature sensor specifications Spec ID# Parameter Description SID93 TSENSACC Temperature –5 sensor accuracy Datasheet Min 35 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications 8.3.4 Table 12 SAR ADC SAR ADC DC specifications Spec ID# Parameter Description Min Typ Max Units Details/ conditions SID94 A_RES Resolution – – 12 bits   SID95 A_CHNIS_S Number of – channels single ended – 8   8 full speed SID96 A-CHNKS_D Number of channels differential – – 4   Diff inputs use neighboring I/O SID97 A-MONO Monotonicity – – –   Yes. Based on characterizat ion SID98 A_GAINERR Gain error – – ±0.1 % With external reference. Guaranteed by characterizat ion SID99 A_OFFSET Input offset voltage – – 2 mV Measured with 1-V VREF. Guaranteed by characterizat ion SID100 A_ISAR Current – consumption – 1 mA   SID101 A_VINS Input voltage VSS range single ended – VDDA V Based on device characterizat ion SID102 A_VIND Input voltage VSS range differential – VDDA V Based on device characterizat ion SID103 A_INRES Input resistance – – 2.2 KΩ Based on device characterizat ion SID104 A_INCAP Input capacitance – – 10 pF Based on device characterizat ion Datasheet 36 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Table 13 SAR ADC AC specifications (Guaranteed by characterization) Spec ID# Parameter Description Min Typ Max Units Details/ conditions SID106 A_PSRR Power supply rejection ratio 70 – – dB   SID107 A_CMRR Common mode rejection ratio 66 – – dB Measured at 1V SID108 A_SAMP_1 Sample rate – with external reference bypass cap – 1 Msps   SID108A A_SAMP_2 Sample rate with no bypass cap. Reference = VDD – – 500 Ksps   SID108B A_SAMP_3 Sample rate with no bypass cap. Internal reference – – 100 Ksps   SID109 A_SNDR Signal-to65 noise and distortion ratio (SINAD) – – dB FIN = 10 kHz SID111 A_INL Integral non linearity –1.7 – +2 LSB VDD = 1.71 to 5.5, 1 Msps, Vref = 1 to 5.5. –40 °C ≤ TA ≤ 85 °C –1.9 – +2 LSB VDD = 1.71 to 5.5, 1 Msps, Vref = 1 to 5.5. –40 °C ≤ TA ≤ 105 °C –1.5 – +1.7 LSB VDDD = 1.71 to 3.6, 1 Msps, Vref = 1.71 to VDDD. –40 °C ≤ TA ≤ 85 °C SID111A A_INL Integral non linearity (table continues...) Datasheet 37 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Table 13 (continued) SAR ADC AC specifications (Guaranteed by characterization) Spec ID# Parameter Description Min Typ Max Units Details/ conditions –1.9 – +2 LSB VDDD = 1.71 to 3.6, 1 Msps, Vref = 1.71 to VDDD. –40 °C ≤ TA ≤ 105 °C –1.5 – +1.7 LSB VDDD = 1.71 to 5.5, 500 Ksps, Vref = 1 to 5.5. SID111B A_INL Integral non linearity SID112 A_DNL Differential –1 non linearity – +2.2 LSB VDDD = 1.71 to 5.5, 1 Msps, Vref = 1 to 5.5. –40 °C ≤ TA ≤ 85 °C –1 – +2.3 LSB VDDD = 1.71 to 5.5, 1 Msps, Vref = 1 to 5.5. –40 °C ≤ TA ≤ 105 °C Differential –1 non linearity – +2 LSB VDDD = 1.71 to 3.6, 1 Msps, Vref = 1.71 to VDDD. –40 °C ≤ TA ≤ 85 °C –1 – +2.2 LSB VDDD = 1.71 to 3.6, 1 Msps, Vref = 1.71 to VDDD. –40 °C ≤ TA ≤ 105 °C SID112A A_DNL SID112B A_DNL Differential –1 non linearity – +2.2 LSB VDDD = 1.71 to 5.5, 500 Ksps, Vref = 1 to 5.5. SID113 A_THD Total harmonic distortion – –65 dB FIN = 10 kHz. Datasheet – 38 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications 8.3.5 CSD Table 14 Spec ID# CSD block specification Parameter Description Min Typ Max Units Details/ conditions 1.71 – 5.5 V   CSD specification SID308 VCSD Voltage range of operation SID309 IDAC1 DNL for 8-bit –1 resolution – 1 LSB   SID310 IDAC1 INL for 8-bit resolution –3 – 3 LSB   SID311 IDAC2 DNL for 7-bit –1 resolution – 1 LSB   SID312 IDAC2 INL for 7-bit resolution – 3 LSB   SID313 SNR Ratio of 5 counts of finger to noise. Guaranteed by characterizat ion – – Ratio Capacitance range of 9 to 35 pF, 0.1 pF sensitivity SID314 IDAC1_CRT1 Output – current of Idac1 (8-bits) in High range 612 – µA   SID314A IDAC1_CRT2 Output – current of Idac1(8-bits) in Low range 306 – µA   SID315 IDAC2_CRT1 Output – current of Idac2 (7-bits) in High range 304.8 – µA   SID315A IDAC2_CRT2 Output – current of Idac2 (7-bits) in Low range 152.4 – µA   8.4 Digital peripherals –3 The following specifications apply to the Timer/Counter/PWM peripherals in the Timer mode. Datasheet 39 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications 8.4.1 Table 15 Timer/Counter/PWM TCPWM specifications (Guaranteed by characterization) Spec ID Parameter Description Min Typ Max Units Details/ conditions SID.TCPWM.1 ITCPWM1 Block – current consumption at 3 MHz – 45 µA All modes(Time r/Counter/ PWM) SID.TCPWM.2 ITCPWM2 Block – current consumption at 12 MHz – 155 µA All modes(Time r/Counter/ PWM) SID.TCPWM.2 ITCPWM3 A Block – current consumption at 48 MHz – 650 µA All modes(Time r/Counter/ PWM) – Fc MHz Fc max = Fcpu. Maximum = 24 MHz SID.TCPWM.4 TPWMENEXT Input Trigger 2/Fc Pulse Width for all Trigger Events – – ns Trigger Events can be Stop, Start, Reload, Count, Capture, or Kill depending on which mode of operation is selected. SID.TCPWM.5 TPWMEXT – – ns Minimum possible width of Overflow, Underflow, and CC (Counter equals Compare value) trigger outputs SID.TCPWM.3 TCPWMFREQ Operating frequency – Output 2/Fc Trigger Pulse widths (table continues...) Datasheet 40 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Table 15 (continued) TCPWM specifications (Guaranteed by characterization) Spec ID Parameter Description Min Typ Max Units Details/ conditions SID.TCPWM.5 TCRES A Resolution of 1/Fc Counter – – ns Minimum time between successive counts SID.TCPWM.5 PWMRES B PWM Resolution 1/Fc – – ns Minimum pulse width of PWM Output SID.TCPWM.5 QRES C Quadrature inputs resolution 1/Fc – – ns Minimum pulse width between Quadrature phase inputs. Typ Max Units Details/ conditions 8.4.2 I2C Fixed I2C DC specifications Table 16 (Guaranteed by characterization) Spec ID Parameter Description SID149 II2C1 Block – current consumption at 100 kHz – 50 pA   SID150 II2C2 Block – current consumption at 400 kHz – 135 pA   SID151 II2C3 Block – current consumption at 1 Mbps – 310 pA   SID152 II2C4 I2C enabled in Deep Sleep mode – 1.4 pA   Datasheet Min – 41 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Fixed I2C AC specifications Table 17 (Guaranteed by characterization) Spec ID Parameter Description Min Typ Max Units Details/ conditions SID153 FI2C1 Bit rate   – – 1 Mbps 8.4.3 LCD direct drive Table 18 LCD direct drive DC specifications (Guaranteed by characterization) Spec ID Parameter Description Min Typ Max Units Details/ conditions SID154 ILCDLOW Operating current in low power mode – 5 – µA 16 × 4 small segment disp. at 50 Hz SID155 CLCDCAP LCD capacitance per segment/ common driver – 500 5000 pF Guaranteed by Design SID156 LCDOFFSET Long-term segment offset – 20 – mV   SID157 ILCDOP1 PWM Mode current. 5-V bias.24-MHz IMO. 25 °C – 0.6 – mA 32 × 4 segments. 50 Hz SID158 ILCDOP2 PWM Mode current. 3.3V bias. 24MHz IMO. 25 °C – 0.5 – mA 32 × 4 segments. 50 Hz Table 19 LCD direct drive AC specifications (Guaranteed by characterization) Spec ID Parameter Description Min Typ Max Units Details/ conditions SID159 FLCD LCD frame rate 10 50 150 Hz   Datasheet 42 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Table 20 Fixed UART DC specifications (Guaranteed by characterization) Spec ID Parameter Description SID160 IUART1 SID161 IUART2 Table 21 Min Typ Max Units Details/ conditions Block – current consumption at100 Kbits/sec – 55 µA   Block – current consumption at1000 Kbits/sec – 312 µA   Fixed UART AC specifications (Guaranteed by characterization) Spec ID Parameter Description Min Typ Max Units SID162 FUART Bit rate – – 1 Mbps 8.4.4 Table 22 SPI specifications Fixed SPI DC specifications (Guaranteed by characterization) Spec ID Parameter Description Min Typ Max Units SID163 ISPI1 Block current consumption at 1 Mbits/sec – – 360 µA SID164 ISPI2 Block current consumption at 4 Mbits/sec – – 560 µA SID165 ISPI3 Block current consumption at 8 Mbits/sec – – 600 µA Min Typ Max Units – 8 MHz Table 23 Fixed SPI AC specifications (Guaranteed by characterization) Spec ID Parameter Description SID166 FSPI SPI operating – frequency (master; 6X oversampling) Datasheet 43 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Table 24 Fixed SPI Master mode AC specifications (Guaranteed by characterization) Spec ID Parameter Description Min Typ Max Units SID167 TDMO MOSI valid after Sclock driving edge – – 15 ns SID168 TDSI MISO valid 20 before Sclock capturing edge. Full clock, late MISO Sampling used – – ns SID169 THMO Previous MOSI 0 data hold time with respect to capturing edge at Slave – – ns Table 25 Fixed SPI Slave mode AC specifications (Guaranteed by characterization) Spec ID Parameter Description Min Typ Max Units Details/ conditions SID170 TDMI MOSI valid before Sclock capturing edge 40 – – ns   SID171 TDSO MISO valid – after Sclock driving edge – 42 + 3 × Tscbclk ns   SID171A TDSO_ext MISO valid – after Sclock driving edge in Ext. Clock mode – 48 ns   SID172 THSO Previous MISO data hold time – – ns   SID172A TSSELSCK SSEL Valid to 100 first SCK Valid edge – – ns   Datasheet 0 44 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications 8.5 Memory Table 26 Flash DC specifications Spec ID Parameter Description Min Typ Max Units Details/ conditions SID173 VPE Erase and program voltage 1.71 – 5.5 V   Table 27 Flash AC specifications Spec ID Parameter Description Min Typ Max Units Details/ conditions SID174 TROWWRITE1) Row (block) write time (erase and program) – – 20 ms Row (block) =128 bytes. – 40 °C ≤ TA ≤ 85 °C – – 26 ms Row (block) =128 bytes. – 40 °C ≤ TA ≤ 105 °C SID175 TROWERASE1) Row erase time – – 13 ms   SID176 TROWPROGRAM 1) Row program time after erase – – 7 ms –40 °C ≤ TA ≤ 85 °C – – 13 ms –40 °C ≤ TA ≤ 105 °C SID178 TBULKERASE1) Bulk erase time (32 KB) – – 35 ms   SID180 TDEVPROG1) Total device program time – – 7 seconds Guaranteed by characterizat ion SID181 FEND Flash endurance 100 K – – cycles Guaranteed by characterizat ion SID182 FRET Flash 20 retention. TA ≤ 55 °C, 100 K P/E cycles – – years Guaranteed by characterizat ion SID182A   Flash 10 retention. TA ≤ 85 °C, 10 K P/E cycles – – years Guaranteed by characterizat ion (table continues...) Datasheet 45 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Table 27 (continued) Flash AC specifications Spec ID Parameter Description SID182B FRETQ Flash 10 retention. TA ≤ 105 °C, 10K P/E cycles, ≤ three years at TA > 85 °C. 1) Min Typ Max Units Details/ conditions 20 –   Guaranteed by characterizat ion. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs. Make certain that these are not inadvertently activated. 8.6 System resources 8.6.1 Power-on-Reset (POR) with Brown Out Table 28 Imprecise Power On Reset (PRES) Spec ID Parameter Description Min Typ Max Units Details/ conditions SID185 VRISEIPOR Rising trip voltage 0.80 – 1.45 V Guaranteed by characterizat ion SID186 VFALLIPOR Falling trip voltage 0.75 – 1.4 V Guaranteed by characterizat ion SID187 VIPORHYST Hysteresis 15 – 200 mV Guaranteed by characterizat ion Datasheet 46 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Table 29 Precise Power On Reset (POR) Spec ID Parameter Description SID190 VFALLPPOR SID192 Typ Max Units Details/ conditions BOD trip 1.64 voltage in active and sleep modes – – V Full functionality between 1.71 V and BOD trip voltage is guaranteed by characterizat ion VFALLDPSLP BOD trip voltage in Deep Sleep – – V Guaranteed by characterizat ion BID55 Svdd Maximum – power supply ramp rate – 67 kV/sec   8.6.2 Voltage monitors Table 30 Min 1.4 Voltage monitors DC specifications Spec ID Parameter Description Min Typ Max Units Details/ conditions SID195 VLVI1 LVI_A/ 1.71 D_SEL[3:0] = 0000b 1.75 1.79 V   SID196 VLVI2 LVI_A/ 1.76 D_SEL[3:0] = 0001b 1.80 1.85 V   SID197 VLVI3 LVI_A/ 1.85 D_SEL[3:0] = 0010b 1.90 1.95 V   SID198 VLVI4 LVI_A/ 1.95 D_SEL[3:0] = 0011b 2.00 2.05 V   SID199 VLVI5 LVI_A/ 2.05 D_SEL[3:0] = 0100b 2.10 2.15 V   SID200 VLVI6 LVI_A/ 2.15 D_SEL[3:0] = 0101b 2.20 2.26 V   (table continues...) Datasheet 47 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Table 30 (continued) Voltage monitors DC specifications Spec ID Parameter Description Min Typ Max Units Details/ conditions SID201 VLVI7 LVI_A/ 2.24 D_SEL[3:0] = 0110b 2.30 2.36 V   SID202 VLVI8 LVI_A/ 2.34 D_SEL[3:0] = 0111b 2.40 2.46 V   SID203 VLVI9 LVI_A/ 2.44 D_SEL[3:0] = 1000b 2.50 2.56 V   SID204 VLVI10 LVI_A/ 2.54 D_SEL[3:0] = 1001b 2.60 2.67 V   SID205 VLVI11 LVI_A/ 2.63 D_SEL[3:0] = 1010b 2.70 2.77 V   SID206 VLVI12 LVI_A/ 2.73 D_SEL[3:0] = 1011b 2.80 2.87 V   SID207 VLVI13 LVI_A/ 2.83 D_SEL[3:0] = 1100b 2.90 2.97 V   SID208 VLVI14 LVI_A/ 2.93 D_SEL[3:0] = 1101b 3.00 3.08 V   SID209 VLVI15 LVI_A/ 3.12 D_SEL[3:0] = 1110b 3.20 3.28 V   SID210 VLVI16 LVI_A/ 4.39 D_SEL[3:0] = 1111b 4.50 4.61 V   SID211 LVI_IDD Block current – 100 µA Guaranteed by characterizat ion Table 31 – Voltage monitors AC specifications Spec ID Parameter Description Min Typ Max Units Details/ conditions SID212 TMONTRIP Voltage monitor trip time – – 1 µs Guaranteed by characterizat ion Datasheet 48 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications 8.6.3 Table 32 SWD interface SWD interface specifications Spec ID Parameter Description Min Typ Max Units Details/ conditions SID213 F_SWDCLK1 3.3 V ≤ VDD ≤ 5.5 V – – 14 MHz SWDCLK ≤ 1/3 CPU clock frequency SID214 F_SWDCLK2 1.71 V ≤ VDD ≤ – 3.3 V – 7 MHz SWDCLK ≤ 1/3 CPU clock frequency SID215 T_SWDI_SET T = 1/f UP SWDCLK 0.25*T – – ns Guaranteed by characterizat ion SID216 T_SWDI_HOL T = 1/f D SWDCLK 0.25*T – – ns Guaranteed by characterizat ion SID217 T_SWDO_VA T = 1/f LID SWDCLK – – 0.5*T ns Guaranteed by characterizat ion SID217A T_SWDO_HO T = 1/f LD SWDCLK 1 – – ns Guaranteed by characterizat ion 8.6.4 Internal main oscillator Typ Max Units Details/ conditions Table 33 IMO DC specifications (Guaranteed by design) Spec ID Parameter Description Min SID218 IIMO1 IMO – operating current at 48 MHz – 1000 pA   SID219 IIMO2 IMO – operating current at 24 MHz – 325 pA   (table continues...) Datasheet 49 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Table 33 (continued) IMO DC specifications (Guaranteed by design) Spec ID Parameter Description SID220 IIMO3 SID221 SID222 Typ Max Units Details/ conditions IMO – operating current at 12 MHz – 225 pA   IIMO4 IMO operating current at 6 MHz – – 180 pA   IIMO5 IMO operating current at 3 MHz – – 150 pA   Table 34 Min IMO AC specifications Spec ID Parameter Description Min Typ Max Units Details/ conditions SID223 FIMOTOL1 Frequency variation from 3 to 48 MHz – – ±2 % +3% if TA > 85 °C and IMO frequency < 24 MHz SID226 TSTARTIMO IMO startup time – – 12 µs   SID227 TJITRMSIMO1 RMS Jitter at – 3 MHz 156 – ps   SID228 TJITRMSIMO2 RMS Jitter at – 24 MHz 145 – ps   SID229 TJITRMSIMO3 RMS Jitter at – 48 MHz 139 – ps   8.6.5 Internal low-speed oscillator Typ Max Units Details/ conditions 0.3 1.05 µA Guaranteed by characterizat ion Table 35 ILO DC specifications (Guaranteed by design) Spec ID Parameter Description Min SID231 IILO1 ILO – operating current at 32 kHz (table continues...) Datasheet 50 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Table 35 (continued) ILO DC specifications (Guaranteed by design) Spec ID Parameter Description Min Typ Max Units Details/ conditions SID233 IILOLEAK ILO leakage current – 2 15 nA Guaranteed by design Table 36 ILO AC specifications Spec ID Parameter Description Min Typ Max Units Details/ conditions SID234 TSTARTILO1 ILO startup time – – 2 ms Guaranteed by characterizat ion SID236 TILODUTY ILO duty cycle 40 50 60 % Guaranteed by characterizat ion SID237 FILOTRIM1 32 kHz trimmed frequency 15 32 50 kHz Max. ILO frequency is 70 kHz if TA > 85 °C Table 37 External clock specifications Spec ID Parameter Description Min Typ Max Units Details/ conditions SID305 ExtClkFreq External Clock input Frequency 0 – 48 MHz Guaranteed by characterizat ion SID306 ExtClkDuty Duty cycle; 45 Measured at VDD/2 – 55 % Guaranteed by characterizat ion Typ Max Units Details/ conditions – 48 MHz   Table 38 UDB AC specifications (Guaranteed by characterization) Spec ID Parameter Description Min Datapath performance SID249 FMAX-TIMER Max – frequency of 16-bit timer in a UDB pair (table continues...) Datasheet 51 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Table 38 (continued) UDB AC specifications (Guaranteed by characterization) Spec ID Parameter Description SID250 FMAX-ADDER SID251 FMAX_CRC Min Typ Max Units Details/ conditions Max – frequency of 16-bit adder in a UDB pair – 48 MHz   Max – frequency of 16-bit CRC/PRS in a UDB pair – 48 MHz   Max – frequency of 2-pass PLD function in a UDB pair – 48 MHz   PLD performance in UDB SID252 FMAX_PLD Clock to output performance SID253 TCLK_OUT_UDB Prop. delay – for clock in 1 to data out at 25 °C, Typ. 15 – ns   SID254 TCLK_OUT_UDB Prop. delay for clock in 2 to data out, Worst case. – 25 – ns   Table 39 Block specs Spec ID Parameter Description Min Typ Max Units Details/ conditions SID256* TWS48* Number of wait states at 48 MHz 1 – –   CPU execution fromFlash. Guaranteed by characterizat ion (table continues...) Datasheet 52 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Table 39 (continued) Block specs Spec ID Parameter Description Min Typ Max Units Details/ conditions SID257 TWS24* Number of wait states at 24 MHz 0 – –   CPU execution fromFlash. Guaranteed by characterizat ion SID260 VREFSAR Trimmed internal reference to SAR –1 – +1 % Percentage of Vbg (1.024 V). Guaranteed by characterizat ion SID262 TCLKSWITCH Clock switching from clk1 to clk2 in clk1 periods 3 – 4 Periods Guaranteed bydesign * Tws48 and Tws24 are guaranteed by Design Table 40 UDB port adaptor specifications (Based on LPC Component Specs, Guaranteed by Characterization -10-pF load, 3-V VDDIO and VDDD) Spec ID Parameter Description SID263 TLCLKDO SID264 Min Typ Max Units Details/ conditions LCLK to – output delay – 18 ns   TDINLCLK Input setup – time to LCLCK rising edge – 7 ns   SID265 TDINLCLKHLD Input hold time from LCLK rising edge 5 – – ns   SID266 TLCLKHIZ LCLK to output tristated – – 28 ns   SID267 TFLCLK LCLK frequency – – 33 MHz   (table continues...) Datasheet 53 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 8 Electrical specifications Table 40 (continued) UDB port adaptor specifications (Based on LPC Component Specs, Guaranteed by Characterization -10-pF load, 3-V VDDIO and VDDD) Spec ID Parameter Description Min Typ Max Units Details/ conditions SID268 TLCLKDUTY LCLK duty cycle (percentage high) 40 – 60 %   Datasheet 54 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 9 Ordering information 9 Ordering information The PSoC™ 4200 part numbers and features are listed in the following table. Opamp (CTBm) CAPSENSE™ Direct LCD drive 12-bit SAR ADC TCPWM blocks SCB blocks GPIO 28-SSOP –40 to +85 °C (A grade) –40 to +105 °C (S grade) 2 1 ✓ ✓ 1 Msps 2 4 2 24 ✓ ✓ – CY8C4245PVA- 48 452Z 32 4 4 0 – ✓ – 0 4 2 24 ✓ ✓ – CY8C4245PVA- 48 472Z 32 4 4 1 – ✓ 1 Msps 2 4 2 24✓   ✓ – CY8C4245PVA- 48 482Z 32 4 4 1 ✓ ✓ 1 Msps 2 4 2 24 ✓ ✓ – CY8C4244PVS- 48 442Z 16 4 2 1 ✓ ✓ 1 Msps 2 4 2 24 ✓ – ✓ CY8C4245PVS- 48 452Z 32 4 4 0 – ✓ – 0 4 2 24 ✓ – ✓ CY8C4245PVS- 48 472Z 32 4 4 1 – ✓ 1 Msps 2 4 2 24 ✓ – ✓ CY8C4245PVS- 48 482Z 32 4 4 1 ✓ ✓ 1 Msps 2 4 2 24 ✓ – ✓ CY8C4245PVA- 48 482 32 4 4 1 ✓ ✓ 1 Msps 2 4 2 24 ✓ ✓ – 9.1 LP comparators UDB 4 Max CPU speed (MHz) 16 Product 4200 CY8C4244PVA- 48 442Z Family SRAM (KB) Package Operating temperature Flash (KB) Features Part numbering conventions PSoC™ 4 devices follow the part numbering convention described in the following table. All fields are single-character alphanumeric (0, 1, 2, …, 9, A,B, …, Z) unless stated otherwise. The part numbers are of the form CY8C4ABCDEF-GHI where the fields are defined as follows. Datasheet 55 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 9 Ordering information Example CY8C 4 A B C DE F - GH I Z Cypress (An Infineon company) 4 : PSoC4 Architecture 2 : 4200Family Family within Architecture 4 : 48 MHz Speed Grade 5 : 32 KB Flash Capacity PV : SSOP Package Code A: Automotive -40 to +85 °C S: Automotive: -40 to +105 °C Temperature Range Attributes Set Fab Location Change: Z Figure 9 Part numbering conventions The field values are listed in the following table. Field Description Values Meaning CY8C Cypress (An Infineon company)     4 Architecture 4 PSoC™ 4 A Family within architecture 1 4100 Family 2 4200 Family 2 24 MHz 4 48 MHz 4 16 KB 5 32 KB B C CPU speed Flash capacity DE Package code PV SSOP F Temperature range A/S Automotive GHI Attributes code 000-999 Code of feature set in specific family Z Fab location change     Datasheet 56 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 10 Packaging 10 Table 41 Packaging Package characteristics Parameter Description Conditions Min Typ Max Units TA Operating ambient temperature For A grade devices –40 25.00 85 °C TA Operating ambient temperature For S grade devices –40 25.00 105 °C TJ Operating junction temperature For A grade devices –40 – 100 °C TJ Operating junction temperature For S grade devices –40 – 120 °C   – 66.58 – °C/W   – 46.28 – °C/W TJA TJC Table 42 Package θJA (28-pin SSOP) Package θJC (28-pin SSOP) Solder reflow peak temperature Package Maximum peak temperature Maximum time at peak temperature 28-pin SSOP 260 °C 30 seconds Table 43 Package moisture sensitivity level (MSL), IPC/JEDEC J-STD-2 Package MSL 28-pin SSOP MSL 3 PSoC™ 4 CAB Libraries with Schematics Symbols and PCB Footprints are on the Infineon webpage at http:// www.cypress.com/cad-resources/psoc-4-cad-libraries?source=search&cat=technical_documents Datasheet 57 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 10 Packaging Figure 10 Datasheet 28-pin SSOP (210 Mils) Package Outline, 51-85079 (PG-SSOP-28) 58 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 11 Acronyms 11 Acronyms Table 44 Acronyms used in this document Acronym Description abus analog local bus ADC analog-to-digital converter AG analog global AHB AMBA (advanced microcontroller bus architecture) highperformance bus, an Arm® data transfer bus ALU arithmetic logic unit AMUXBUS analog multiplexer bus API application programming interface APSR application program status register ® Arm advanced RISC machine, a CPU architecture ATM automatic thump mode BW bandwidth CAN Controller Area Network, a communications protocol CMRR common-mode rejection ratio CPU central processing unit CRC cyclic redundancy check, an error-checking protocol DAC digital-to-analog converter, see also IDAC, VDAC DFB digital filter block DIO digital input/output, GPIO with only digital capabilities, no analog. See GPIO. DMIPS Dhrystone million instructions per second DMA direct memory access, see also TD DNL differential nonlinearity, see also INL DNU do not use DR port write data registers DSI digital system interconnect DWT data watchpoint and trace ECC error correcting code ECO external crystal oscillator EEPROM electrically erasable programmable read-only memory EMI electromagnetic interference EMIF external memory interface EOC (table continues...) end of conversion Datasheet 59 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 11 Acronyms Table 44 (continued) Acronyms used in this document Acronym Description EOF end of frame EPSR execution program status register ESD electrostatic discharge ETM embedded trace macrocell FIR finite impulse response, see also IIR FPB flash patch and breakpoint FS full-speed GPIO general-purpose input/output, applies to a PSoC™ pin HVI high-voltage interrupt, see also LVI, LVD IC integrated circuit IDAC current DAC, see also DAC, VDAC IDE integrated development environment I2C, or IIC Inter-Integrated Circuit, a communications protocol IIR infinite impulse response, see also FIR ILO internal low-speed oscillator, see also IMO IMO internal main oscillator, see also ILO INL integral nonlinearity, see also DNL I/O input/output, see also GPIO, DIO, SIO, USBIO IPOR initial power-on reset IPSR interrupt program status register IRQ interrupt request ITM instrumentation trace macrocell LCD liquid crystal display LIN Local Interconnect Network, a communications protocol. LR link register LUT lookup table LVD low-voltage detect, see also LVI LVI low-voltage interrupt, see also HVI LVTTL low-voltage transistor-transistor logic MAC multiply-accumulate MCU microcontroller unit MISO master-in slave-out NC (table continues...) no connect Datasheet 60 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 11 Acronyms Table 44 (continued) Acronyms used in this document Acronym Description NMI nonmaskable interrupt NRZ non-return-to-zero NVIC nested vectored interrupt controller NVL nonvolatile latch, see also WOL opamp operational amplifier PAL programmable array logic, see also PLD PC program counter PCB printed circuit board PGA programmable gain amplifier PHUB peripheral hub PHY physical layer PICU port interrupt control unit PLA programmable logic array PLD programmable logic device, see also PAL PLL phase-locked loop PMDD package material declaration data sheet POR power-on reset PRES precise power-on reset PRS pseudo random sequence PS port read data register PSoC™ Programmable System-on-ChipTM PSRR power supply rejection ratio PWM pulse-width modulator RAM random-access memory RISC reduced-instruction-set computing RMS root-mean-square RTC real-time clock RTL register transfer language RTR remote transmission request RX receive SAR successive approximation register SC/CT switched capacitor/continuous time SCL (table continues...) I2C serial clock Datasheet 61 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 11 Acronyms Table 44 (continued) Acronyms used in this document Acronym Description SDA I2C serial data S/H sample and hold SINAD signal to noise and distortion ratio SIO special input/output, GPIO with advanced features. See GPIO. SOC start of conversion SOF start of frame SPI Serial Peripheral Interface, a communications protocol SR slew rate SRAM static random access memory SRES software reset SWD serial wire debug, a test protocol SWV single-wire viewer TD transaction descriptor, see also DMA THD total harmonic distortion TIA transimpedance amplifier TRM technical reference manual TTL transistor-transistor logic TX transmit UART Universal Asynchronous Transmitter Receiver, a communications protocol UDB universal digital block USB Universal Serial Bus USBIO USB input/output, PSoC™ pins used to connect to a USB port VDAC voltage DAC, see also DAC, IDAC WDT watchdog timer WOL write once latch, see also NVL WRES watchdog timer reset XRES external reset I/O pin XTAL crystal Datasheet 62 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 12 Document conventions 12 Document conventions Units of measure Table 45 Units of measure Symbol Unit of measure °C degrees Celsius dB decibel fF femtofarad Hz hertz KB 1024 bytes kbps kilobits per second Khr kilohour kHz kilohertz kΩ kilo ohm ksps kilosamples per second LSB least significant bit Mbps megabits per second MHz megahertz MΩ mega-ohm Msps megasamples per second μF microampere μV microsecond μA μH microfarad μW microvolt mA milliampere ms millisecond mV millivolt nA nanoampere ns nanosecond nV nanovolt Ω ohm pF picofarad ppm parts per million ps picosecond s second sps (table continues...) samples per second microhenry μs Datasheet microwatt 63 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 12 Document conventions Table 45 (continued) Units of measure Symbol Unit of measure sqrtHz square root of hertz V volt Datasheet 64 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 13 References 13 References Worldwide sales and design support Infineon maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit webpage. Products Arm® Cortex® Microcontrollers Automotive Clocks & Timing Solutions Transceivers Internet of Things Memories Microcontroller Power Management ICs Touch Sensing USB Controllers Wireless Connectivity PSoC™ Solutions PSoC™ 1 | PSoC™ 3 | PSoC™ 4 | PSoC™ 5LP | PSoC™ 6 MCU Infineon developer community Technical support Datasheet 65 001-93573 Rev. *H 2023-11-06 PSoC™ 4: PSoC™ 4200 Revision history Revision history Table 46 Revision history Document version Date of release Description of change *D 2016-07-04 Changed status from Preliminary to Final. *E 2017-03-28 Updated Ordering Information Updated part numbers. Updated to new template. *F 2017-05-29 No technical updates. Completing Sunset Review. *G 2019-03-08 Added CY84245PVA-472Z and CY84245PVS-472Z in Ordering Information. *H 2023-11-06 Migrated to IFX template Updated Ordering Information Completing Sunset review Datasheet 66 001-93573 Rev. *H 2023-11-06 Trademarks All referenced product or service names and trademarks are the property of their respective owners. Edition 2023-11-06 Published by Infineon Technologies AG 81726 Munich, Germany   © 2023 Infineon Technologies AG All Rights Reserved.   Do you have a question about any aspect of this document? Email: erratum@infineon.com   Document reference IFX-wvs1691059611019 Important notice The information contained in this application note is given as a hint for the implementation of the product only and shall in no event be regarded as a description or warranty of a certain functionality, condition or quality of the product. Before implementation of the product, the recipient of this application note must verify any function and other technical information given herein in the real application. Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind (including without limitation warranties of non-infringement of intellectual property rights of any third party) with respect to any and all information given in this application note. The data contained in this document is exclusively intended for technically trained staff. It is the responsibility of customer’s technical departments to evaluate the suitability of the product for the intended application and the completeness of the product information given in this document with respect to such application. Warnings Due to technical requirements products may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies office. Except as otherwise explicitly approved by Infineon Technologies in a written document signed by authorized representatives of Infineon Technologies, Infineon Technologies’ products may not be used in any applications where a failure of the product or any consequences of the use thereof can reasonably be expected to result in personal injury.