Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
PSoC 4: PSoC 4500S Datasheet
Programmable System-on-Chip (PSoC)
General Description
PSoC® 4 is a scalable and reconfigurable platform architecture for a family of programmable embedded system controllers with an
Arm® Cortex™-M0+ CPU. It combines programmable and reconfigurable analog and digital blocks with flexible automatic routing.
PSoC 4500S is a member of the PSoC 4 platform architecture. It is a combination of a microcontroller with standard communication
and timing peripherals, a capacitive touch-sensing system (CapSense) with best-in-class performance, programmable
general-purpose continuous-time and switched-capacitor analog blocks, and programmable connectivity. PSoC 4500S products will
be upward compatible with members of the PSoC 4 platform for new applications and design needs.
Features
32-bit MCU Subsystem
Motor Control Accelerator (MCA)
■
48-MHz Arm Cortex-M0+ CPU with single-cycle multiply
■
Up to 256 KB of flash with Read Accelerator
■
Up to 32 KB of SRAM
■
8-channel DMA engine
■
Two Divide and Square Root computation accelerators
■
Hardware Square Root and Divide Block
■
Accelerates execution of Field Oriented Control (FOC) and
Power Factor Correction (PFC) Blocks
Serial Communication
■
Programmable Analog
■
Four opamps with reconfigurable high-drive external and
high-bandwidth internal drive and Comparator modes and ADC
input buffering capability. Opamps can operate in Deep Sleep
low-power mode.
■
Two 12-bit 1-Msps SAR ADCs with differential and
single-ended modes, and Channel Sequencer with signal
averaging. Simultaneous sampling is provided.
■
Single-slope 10-bit ADC function provided by a capacitance
sensing block
■
Two current DACs (IDACs) for general-purpose or capacitive
sensing applications on any pin
■
Two low-power comparators that operate in Deep Sleep
low-power mode
Programmable Digital
■
Programmable logic blocks allowing Boolean operations to be
performed on port inputs and outputs
Low-Power 1.71-V to 5.5-V Operation
■
Deep Sleep mode with operational analog and 2.5-µA digital
system current
Capacitive Sensing
■
Cypress CapSense Sigma-Delta (CSD) provides best-in-class
signal-to-noise ratio (SNR) (>5:1) and water tolerance
■
Cypress-supplied software component makes capacitive
sensing design easy
■
Automatic hardware tuning (SmartSense™)
Timing and Pulse-Width Modulation
■
Eight 16-bit timer/counter/pulse-width modulator (TCPWM)
blocks
■
Center-aligned, Edge, and Pseudo-random modes
■
Comparator-based triggering of Kill signals for motor drive and
other high-reliability digital logic applications
■
Quadrature decoder
Up to 53 Programmable GPIO Pins
■
48-pin TQFP (0.5-mm pitch), and 64-pin TQFP normal
(0.8 mm) and Fine Pitch (0.5 mm) packages
■
Any GPIO pin can be CapSense, analog, or digital
Drive modes, strengths, and slew rates are programmable
Clock Sources
■
4 to 33 MHz external crystal oscillator (ECO)
■
PLL to generate 48-MHz frequency
■
32-kHz Watch Crystal Oscillator (WCO)
■
±2% Internal Main Oscillator (IMO)
■
40-kHz Internal Low-power Oscillator (ILO)
ModusToolbox™ Software
■
Comprehensive collection of multi-platform tools and software
libraries
■
Includes board support packages (BSPs), peripheral driver
library (PDL), and middleware such as CapSense
LCD Drive Capability
■
LCD segment drive capability on GPIOs
Cypress Semiconductor Corporation
Document Number: 002-26354 Rev. *C
•
Five
independent
run-time
reconfigurable
Serial
Communication Blocks (SCBs) with re-configurable I2C, SPI,
or UART functionality
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 23, 2020
PSoC 4: PSoC 4500S Datasheet
PSoC Creator Design Environment
■
Integrated development environment (IDE) provides schematic
design entry and build (with analog and digital automatic
routing) with debugging
■
Application programming interface (API) component for all
fixed-function and programmable peripherals
Document Number: 002-26354 Rev. *C
Industry-Standard Tool Compatibility
■
After schematic entry, development can be done with
Arm-based industry-standard development tools
Page 2 of 43
PSoC 4: PSoC 4500S Datasheet
Document Ecosystem
PSoC 4 MCU Resources
Cypress provides a wealth of data at www.cypress.com to help you select the right PSoC device and quickly and effectively integrate
it into your design. The following is an abbreviated, hyperlinked list of resources for PSoC 4 MCU:
■
Overview: PSoC Portfolio, PSoC Roadmap
■
Development Tools
❐ ModusToolbox™ Software enables cross platform code
development with a robust suite of tools and software
libraries.
❐ PSoC Creator is a free Windows-based IDE. It enables
concurrent hardware and firmware design of PSoC 3, PSoC
4, PSoC 5LP, and PSoC 6 MCU based systems. Applications
are created using schematic capture and over 150
pre-verified, production-ready peripheral Components.
❐ CY8CKIT-045S PSoC 4500S Pioneer Kit is a low-cost
hardware platform that enables design and debug of the
PSoC 4500S device.
❐ MiniProg4
and MiniProg3 all-in-one development
programmers and debuggers.
❐ PSoC 4 MCU CAD libraries provide footprint and schematic
support for common tools. IBIS models are also available
■
Product Selectors: PSoC 4 MCU
■
Application Notes cover a broad range of topics, from basic
to advanced level, and include the following:
❐ AN79953: Getting Started With PSoC 4. This application note
has a convenient flow chart to help decide which IDE to use:
ModusToolbox™ Software or PSoC Creator.
❐ AN91184: PSoC 4 BLE - Designing BLE Applications
❐ AN88619: PSoC 4 Hardware Design Considerations
❐ AN73854: Introduction To Bootloaders
❐ AN89610: Arm Cortex Code Optimization
❐ AN86233: PSoC 4 MCU Power Reduction Techniques
❐ AN57821: Mixed Signal Circuit Board Layout
❐ AN85951: PSoC 4, PSoC 6 CapSense Design Guide
■
Code Examples demonstrate product features and usage, and
are also available on Cypress GitHub repositories.
■
Training Videos are available on a wide range of topics
including the PSoC 4 MCU 101 series.
■
Technical Reference Manuals (TRMs) provide detailed
descriptions of PSoC 4 MCU architecture and registers.
■
■
PSoC 4 MCU Programming Specification provides the information necessary to program PSoC 4 MCU nonvolatile
memory.
Cypress Developer Community enables connection with
fellow PSoC developers around the world, 24 hours a day, 7
days a week, and hosts a dedicated PSoC 4 MCU Community.
Document Number: 002-26354 Rev. *C
Page 3 of 43
PSoC 4: PSoC 4500S Datasheet
ModusToolbox™ Software
ModusToolbox Software is Cypress' comprehensive collection of multi-platform tools and software libraries that enable an immersive
development experience for creating converged MCU and wireless systems. It is:
■
Comprehensive - it has the resources you need
■
Flexible - you can use the resources in your own workflow
■
Atomic - you can get just the resources you want
Cypress provides a large collection of code repositories on GitHub, including:
■
Board Support Packages (BSPs) aligned with Cypress kits
■
Low-level resources, including a peripheral driver library (PDL)
■
Middleware enabling industry-leading features such as CapSense
■
An extensive set of thoroughly tested code example applications
ModusToolbox Software is IDE-neutral and easily adaptable to your workflow and preferred development environment. It includes a
project creator, peripheral and library configurators, a library manager, as well as the optional Eclipse IDE for ModusToolbox, as
Figure 1 shows. For information on using Cypress tools, refer to the documentation delivered with ModusToolbox software, and
AN79953: Getting Started with PSoC 4.
Figure 1. ModusToolbox Software Tools
Document Number: 002-26354 Rev. *C
Page 4 of 43
PSoC 4: PSoC 4500S Datasheet
PSoC Creator
PSoC Creator is a free Windows-based IDE. It enables you to design hardware and firmware systems concurrently, based on PSoC
4 MCU. As Figure 2 shows, with PSoC Creator you can:
1. Explore the library of 200+ Components
2. Drag and drop Component icons to complete your hardware system design in the main design workspace
3. Configure Components using the Component configuration tools and the Component datasheets
4. Co-design your application firmware and hardware in the PSoC Creator IDE or build a project for a third-party IDE
5. Prototype your solution with the PSoC 4 Pioneer kits. If a design change is needed, PSoC Creator and Components enable you
to make changes on-the-fly without the need for hardware revisions.
Figure 2. Multiple-Sensor Example Project in PSoC Creator
1
2
3
4
5
Document Number: 002-26354 Rev. *C
Page 5 of 43
PSoC 4: PSoC 4500S Datasheet
Contents
Functional Definition ........................................................ 8
CPU and Memory Subsystem ..................................... 8
System Resources ...................................................... 8
Analog Blocks .............................................................. 9
Programmable Digital Blocks .................................... 10
Fixed Function Digital Blocks .................................... 10
GPIO ......................................................................... 10
Special Function Peripherals ..................................... 11
Pinouts ............................................................................ 12
Alternate Pin Functions ............................................. 13
Power ............................................................................... 16
Mode 1: 1.8 V to 5.5 V External Supply .................... 16
Mode 2: 1.8 V ±5% External Supply .......................... 16
Electrical Specifications ................................................ 17
Absolute Maximum Ratings ...................................... 17
Device Level Specifications ....................................... 17
Analog Peripherals .................................................... 21
Document Number: 002-26354 Rev. *C
Digital Peripherals ..................................................... 28
Memory ..................................................................... 30
System Resources .................................................... 30
Ordering Information ...................................................... 34
Packaging ........................................................................ 36
Package Diagrams .................................................... 37
Acronyms ........................................................................ 39
Document Conventions ................................................. 41
Units of Measure ....................................................... 41
Revision History ............................................................. 42
Sales, Solutions, and Legal Information ...................... 43
Worldwide Sales and Design Support ....................... 43
Products .................................................................... 43
PSoC® Solutions ...................................................... 43
Cypress Developer Community ................................. 43
Technical Support ..................................................... 43
Page 6 of 43
PSoC 4: PSoC 4500S Datasheet
Figure 3. Block Diagram
CPU Subsystem
PSoC 4500S
SWD/TC, MTB
SPCIF
Cortex
M0+
48 MHz
FLASH
256 KB
SRAM
32 KB
ROM
8 KB
DataWire/
DMA
FAST MUL
NVIC, IRQMUX, MPU
Read Accelerator
SRAM Controller
ROM Controller
Initiator/MMIO
32-bit
AHB-Lite
System Resources
Lite
System Interconnect (Single Layer AHB)
x1
SARMUX
CTBm
x1
2x OpAmp
SARMUX
2x LP Comparator
x1
LCD
SAR ADC
(12-bit)
WCO
SAR ADC
(12-bit)
2X MCA
Programmable
Analog
5x SCB-I2C/SPI/UART
Programmable
Analog
CapSense
Test
TestMode Entry
Digital DFT
Analog DFT
IOSS GPIO (8x ports)
Reset
Reset Control
XRES
EXCO (w/PLL)
Clock
Clock Control
WDT
ILO
IMO
Peripheral Interconnect (MMIO)
PCLK
8x TCPWM
Power
Sleep Control
WIC
POR
REF
PWRSYS
CTBm
x1
2x OpAmp
High Speed I/O Matrix & 2 Ports Smart I/O
Power Modes
Active/Sleep
DeepSleep
53x GPIOs
IO Subsystem
This device includes extensive support for programming, testing,
debugging, and tracing both hardware and firmware.
The Arm Serial-Wire Debug (SWD) interface supports all
programming and debug features of the device.
Complete debug-on-chip functionality enables full-device
debugging in the final system using the standard production
device. It does not require special interfaces, debugging pods,
simulators, or emulators. Only the standard programming
connections are required to fully support debug.
The PSoC Creator IDE provides fully integrated programming
and debug support for this device. The SWD interface is fully
compatible with industry-standard third-party tools. This device
provides a level of security not possible with multi-chip
application solutions or with microcontrollers. It has the following
advantages:
■
Allows disabling of debug features
■
Robust flash protection
■
Allows customer-proprietary functionality to be implemented in
on-chip programmable blocks
Document Number: 002-26354 Rev. *C
The debug circuits are enabled by default and can be disabled
in firmware. If they are not enabled, the only way to re-enable
them is to erase the entire device, clear flash protection, and
reprogram the device with new firmware that enables debugging.
Thus firmware control of debugging cannot be over-ridden
without erasing the firmware thus providing security.
Additionally, all device interfaces can be permanently disabled
(device security) for applications concerned about phishing
attacks due to a maliciously reprogrammed device or attempts to
defeat security by starting and interrupting flash programming
sequences. All programming, debug, and test interfaces are
disabled when maximum device security is enabled. Therefore,
this device, with device security enabled, may not be returned for
failure analysis. This is a trade-off it allows the customer to make.
Page 7 of 43
PSoC 4: PSoC 4500S Datasheet
Functional Definition
CPU and Memory Subsystem
CPU
The Cortex-M0+ CPU in PSoC 4500S is part of the 32-bit MCU
subsystem, which is optimized for low-power operation with
extensive clock gating. Most instructions are 16 bits in length and
the CPU executes a subset of the Thumb-2 instruction set. It
includes a nested vectored interrupt controller (NVIC) block with
eight interrupt inputs and also includes a Wakeup Interrupt
Controller (WIC). The WIC can wake the processor from Deep
Sleep mode, allowing power to be switched off to the main
processor when the chip is in Deep Sleep mode.
Two Divide and Square Root compute accelerators (MCA) are
provided to speed up computation of control loops for applications such as motor and power control. Two blocks are provided
so that each may be independently used by the
Field-Oriented-Control (FOC) and Power Factor Control (PFC)
Control loops, which are interrupt-driven and asynchronous
processes. Using two blocks eliminates any possibility of MCA
operations either blocking or being corrupted by interrupts
arriving at critical times.
The CPU subsystem includes an 8-channel DMA engine and
also includes a debug interface, the serial wire debug (SWD)
interface, which is a two-wire form of JTAG. The debug configuration used for PSoC 4500S has four breakpoint (address)
comparators and two watchpoint (data) comparators.
All subsystems are operational in Active mode. The CPU
subsystem (CPU, flash, and SRAM) is clock-gated off in Sleep
mode, while all peripherals and interrupts are active with
instantaneous wake-up on a wake-up event. In Deep Sleep
mode, the high-speed clock and associated circuitry is switched
off; wake-up from this mode takes 35 µs. The opamps can
remain operational in Deep Sleep mode.
Clock System
The PSoC 4500S clock system is responsible for providing
clocks to all subsystems that require clocks and for switching
between different clock sources without glitching. In addition, the
clock system ensures that there are no metastable conditions.
The clock system for the PSoC 4500S consists of the IMO, ILO,
a 32-kHz Watch Crystal Oscillator (WCO), MHz ECO and PLL,
and provision for an external clock. The WCO block allows
locking the IMO to the 32-kHz oscillator.
Figure 4. MCU Clocking Architecture
IMO
Divide By
2,4,8
clk_hf
clk_ext
PLL
ECO
ILO
clk_lf
WCO
Flash
The PSoC 4500S device has a 256 KB flash module with a flash
accelerator, tightly coupled to the CPU to improve average
access times from the flash block. The low-power flash block is
designed to deliver two wait-state (WS) access time at 48 MHz.
The flash accelerator delivers 85% of single-cycle SRAM access
performance on average.
SRAM
32 KB of SRAM are provided with zero wait-state access at
48 MHz.
SROM
An 8-KB supervisory ROM that contains boot and configuration
routines is provided.
System Resources
Power System
The power system is described in detail in the section Power. It
provides assurance that voltage levels are as required for each
respective mode and either delays mode entry (for example, on
power-on reset (POR)) until voltage levels are as required for
proper functionality, or generates resets (for example, on
brown-out detection). PSoC 4500S operates with a single
external supply over the range of either 1.8 V ±5% (externally
regulated) or 1.8 to 5.5 V (internally regulated) and has three
different power modes, transitions between which are managed
by the power system. PSoC 4500S provides Active, Sleep, and
Deep Sleep low-power modes.
Document Number: 002-26354 Rev. *C
clk_hf
Prescaler
clk_sys
Peripheral
Dividers
Peripheral Clocks
Analog
Divider
SAR Clock
The HFCLK signal can be divided down as shown to generate
synchronous clocks for the Analog and Digital peripherals. There
are 18 clock dividers for the PSoC 4500S (six with fractional
divide capability, twelve with integer divide only). There are 12
16-bit dividers allowing a lot of flexibility in generating
fine-grained frequencies.
In addition, there are five 16-bit fractional dividers and one 24-bit
fractional divider.
IMO Clock Source
The IMO is the primary source of internal clocking in the PSoC
4500S. It is trimmed during testing to achieve the specified
accuracy.The IMO default frequency is 24 MHz and it can be
adjusted from 24 to 48 MHz in steps of 4 MHz. The IMO tolerance
with Cypress-provided calibration settings is ±2% over the entire
voltage and temperature range.
ILO Clock Source
The ILO is a very low power, nominally 40-kHz oscillator, which
is primarily used to generate clocks for the watchdog timer
(WDT) and peripheral operation in Deep Sleep mode. ILO-driven
counters can be calibrated to the IMO to improve accuracy.
Cypress provides a software component, which does the
calibration.
Page 8 of 43
PSoC 4: PSoC 4500S Datasheet
Watch Crystal Oscillator (WCO)
There are two SAR ADC blocks in the PSoC 4500S.
The PSoC 4500S clock subsystem also implements a
low-frequency (32-kHz watch crystal) oscillator that can be used
for precision timing applications. The WCO block allows locking
the IMO to the 32 kHz oscillator.
Figure 5. SAR ADC
AHB System Bus and Programmable Logic
Interconnect
SAR Sequencer
Watchdog Timer and Counters
A watchdog timer is implemented in the clock block running from
the ILO; this allows watchdog operation during Deep Sleep and
generates a watchdog reset if not serviced before the set timeout
occurs. The watchdog reset is recorded in a Reset Cause
register, which is firmware readable. The Watchdog counters can
be used to implement a Real-Time clock using the 32-kHz WCO.
The WCO block allows locking the IMO to the 32 kHz oscillator.
SARMUX
The PSoC 4500S also implements a 4 to 33 MHz crystal oscillator.
SARMUX Port
(Up to 16 inputs)
External Crystal Oscillators (ECO)
vminus vplus
Sequencing
and Control
Data and
Status Flags
POS
SARADC
NEG
Reference
Selection
VDDA /2
VDDA
External
Reference and
Bypass
(optional)
VREF
Inputs from other Ports
Opamps (Continuous-Time Block; CTB)
PSoC 4500S can be reset from a variety of sources including a
software reset. Reset events are asynchronous and guarantee
reversion to a known state. The reset cause is recorded in a
register, which is sticky through reset and allows software to
determine the cause of the reset. An XRES pin is reserved for
external reset by asserting it active low. The XRES pin has an
internal pull-up resistor that is always enabled.
PSoC 4500S has four opamps with Comparator modes which
allow most common analog functions to be performed on-chip
eliminating external components; PGAs, Voltage Buffers, Filters,
Trans-Impedance Amplifiers, and other functions can be
realized, in some cases with external passives. saving power,
cost, and space. The on-chip opamps are designed with enough
bandwidth to drive the Sample-and-Hold circuit of the ADC
without requiring external buffering. One of the opamps is
connected only as an internal buffer to drive one of the SAR
ADCs.
Analog Blocks
Low-power Comparators (LPC)
Reset
12-bit SAR ADC
The 12-bit, 1-Msps SAR ADC can operate at a maximum clock
rate of 18 MHz and requires a minimum of 18 clocks to do a 12-bit
conversion.
The Sample-and-Hold (S/H) aperture is programmable allowing
the gain bandwidth requirements of the amplifier driving the SAR
inputs, which determine its settling time, to be relaxed if required.
It is possible to provide an external bypass (through a fixed pin
location) for the internal reference amplifier.
The SAR is connected to a fixed set of pins through an 8-input
sequencer. The sequencer cycles through selected channels
autonomously (sequencer scan) with zero switching overhead
(that is, aggregate sampling bandwidth is equal to 1 Msps
whether it is for a single channel or distributed over several
channels). The sequencer switching is effected through a state
machine or through firmware driven switching. A feature
provided by the sequencer is buffering of each channel to reduce
CPU interrupt service requirements. To accommodate signals
with varying source impedance and frequency, it is possible to
have different sample times programmable for each channel.
Also, signal range specification through a pair of range registers
(low and high range values) is implemented with a corresponding
out-of-range interrupt if the digitized value exceeds the
programmed range; this allows fast detection of out-of-range
values without the necessity of having to wait for a sequencer
scan to be completed and the CPU to read the values and check
for out-of-range values in software.
PSoC 4500S has a pair of low-power comparators, which can
also operate in low power modes. This allows the analog system
blocks to be disabled while retaining the ability to monitor
external voltage levels during low-power modes. The
comparator outputs are normally synchronized to avoid
metastability unless operating in an asynchronous power mode
where the system wake-up circuit is activated by a comparator
switch event. The LPC outputs can be routed to pins.
Current DACs
PSoC 4500S has two 7-bit IDACs, which can drive any of the
pins on the chip. These IDACs have programmable current
ranges.
Analog Multiplexed Buses
PSoC 4500S has two concentric independent buses that go
around the periphery of the chip. These buses (called amux
buses) are connected to firmware-programmable analog
switches that allow the chip's internal resources (IDACs,
comparator) to connect to any pin on the I/O Ports.
The SAR is not available in Deep Sleep mode as it requires a
high-speed clock (up to 18 MHz). The SAR operating range is
1.71 V to 5.5 V.
Document Number: 002-26354 Rev. *C
Page 9 of 43
PSoC 4: PSoC 4500S Datasheet
Programmable Digital Blocks
Smart I/O Block
The Smart I/O block is a fabric of switches and LUTs that allows
Boolean functions to be performed in signals being routed to the
pins of a GPIO port. The Smart I/O can perform logical operations on input pins to the chip and on signals going out as
outputs. There are two Smart I/O blocks in the PSoC 4500S.
Fixed Function Digital Blocks
Timer/Counter/PWM (TCPWM) Block
The TCPWM block consists of a 16-bit counter with
user-programmable period length. There is a capture register to
record the count value at the time of an event (which may be an
I/O event), a period register that is used to either stop or
auto-reload the counter when its count is equal to the period
register, and compare registers to generate compare value
signals that are used as PWM duty cycle outputs. The block also
provides true and complementary outputs with programmable
offset between them to allow use as dead-band programmable
complementary PWM outputs. It also has a Kill input to force
outputs to a predetermined state; for example, this is used in
motor drive systems when an over-current state is indicated and
the PWM driving the FETs needs to be shut off immediately with
no time for software intervention. Each block also incorporates a
Quadrature decoder. There are eight TCPWM blocks in PSoC
4500S.
Serial Communication Block (SCB)
PSoC 4500S has five serial communication blocks, which can be
programmed to have SPI, I2C, or UART functionality.
I2C Mode: The hardware I2C block implements a full
multi-master and slave interface (it is capable of multi-master
arbitration). This block is capable of operating at speeds of up to
400 kbps (Fast Mode) and has flexible buffering options to
reduce interrupt overhead and latency for the CPU. It also
supports EZI2C that creates a mailbox address range in the
memory of PSoC 4500S and effectively reduces I2C communication to reading from and writing to an array in memory. In
addition, the block supports an 8-deep FIFO for receive and
transmit which, by increasing the time given for the CPU to read
data, greatly reduces the need for clock stretching caused by the
CPU not having read data on time.
The I2C peripheral is compatible with the I2C Standard-mode and
Fast-mode devices as defined in the NXP I2C-bus specification
and user manual (UM10204). The I2C bus I/O is implemented
with GPIO in open-drain modes.
UART Mode: This is a full-feature UART operating at up to
1 Mbps. It supports automotive single-wire interface (LIN),
infrared interface (IrDA), and SmartCard (ISO7816) protocols, all
of which are minor variants of the basic UART protocol. In
addition, it supports the 9-bit multiprocessor mode that allows
addressing of peripherals connected over common RX and TX
lines. Common UART functions such as parity error, break
detect, and frame error are supported. An 8-deep FIFO allows
much greater CPU service latencies to be tolerated.
SPI Mode: The SPI mode supports full Motorola SPI, TI SSP
(adds a start pulse used to synchronize SPI Codecs), and
National Microwire (half-duplex form of SPI). The SPI block can
use the FIFO.
GPIO
PSoC 4500S has up to 53 GPIOs. The GPIO block implements
the following:
■ Eight drive modes:
❐ Analog input mode (input and output buffers disabled)
❐ Input only
❐ Weak pull-up with strong pull-down
❐ Strong pull-up with weak pull-down
❐ Open drain with strong pull-down
❐ Open drain with strong pull-up
❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
■ Input threshold select (CMOS or LVTTL).
■ Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes
■ Selectable slew rates for dV/dt related noise control to improve
EMI
The pins are organized in logical entities called ports, which are
8-bit in width (less for Ports 5 and 6). During power-on and reset,
the blocks are forced to the disable state so as not to crowbar
any inputs and/or cause excess turn-on current. A multiplexing
network known as a high-speed I/O matrix is used to multiplex
between various signals that may connect to an I/O pin.
Data output and pin state registers store, respectively, the values
to be driven on the pins and the states of the pins themselves.
Every I/O pin can generate an interrupt if so enabled and each
I/O port has an interrupt request (IRQ) and interrupt service
routine (ISR) vector associated with it.
PSoC 4500S is not completely compliant with the I2C spec in the
following respect:
■
GPIO cells are not overvoltage tolerant and, therefore, cannot
be hot-swapped or powered up independently of the rest of the
I2C system.
Document Number: 002-26354 Rev. *C
Page 10 of 43
PSoC 4: PSoC 4500S Datasheet
Special Function Peripherals
CapSense
CapSense is supported in the PSoC 4500S through a CapSense
Sigma-Delta (CSD) block that can be connected to any pins
through an analog multiplex bus via analog switches. CapSense
function can thus be provided on any available pin or group of
pins in a system under software control. A PSoC Creator
component is provided for the CapSense block to make it easy
for the user.
Shield voltage can be driven on another analog multiplex bus to
provide water-tolerance capability. Water tolerance is provided
by driving the shield electrode in phase with the sense electrode
to keep the shield capacitance from attenuating the sensed
input. Proximity sensing can also be implemented.
The CapSense block has two IDACs, which can be used for
general purposes if CapSense is not being used (both IDACs are
available in that case) or if CapSense is used without water
tolerance (one IDAC is available).
LCD Segment Drive
PSoC 4500S has an LCD controller, which can drive up to 4
commons and up to 50 segments. Any pin can be either a
common or a segment pin. It uses full digital methods to drive the
LCD segments requiring no generation of internal LCD voltages.
The two methods used are referred to as Digital Correlation and
PWM. Digital Correlation pertains to modulating the frequency
and drive levels of the common and segment signals to generate
the highest RMS voltage across a segment to light it up or to
keep the RMS signal to zero. This method is good for STN
displays but may result in reduced contrast with TN (cheaper)
displays. PWM pertains to driving the panel with PWM signals to
effectively use the capacitance of the panel to provide the
integration of the modulated pulse-width to generate the desired
LCD voltage. This method results in higher power consumption
but can result in better results when driving TN displays.
The CapSense block also provides a 10-bit Slope ADC function
which can be used in conjunction with the CapSense function.
The CapSense block is an advanced, low-noise, programmable
block with programmable voltage references and current source
ranges for improved sensitivity and flexibility. It can also use an
external reference voltage. It has a full-wave CSD mode that
alternates sensing to VDDA and ground to null out power-supply
related noise.
Document Number: 002-26354 Rev. *C
Page 11 of 43
PSoC 4: PSoC 4500S Datasheet
Pinouts
The following table provides the pin list for PSoC 4500S for the 48-pin TQFP and 64-pin TQFP Normal and Fine Pitch packages.
64-TQFP
48-TQFP
64-TQFP
48-TQFP
Pin
Name
Pin
Name
Pin
Name
Pin
Name
39
P0.0
28
P0.0
8
P2.6
8
P2.6
40
P0.1
29
P0.1
9
P2.7
9
P2.7
41
P0.2
30
P0.2
10
VSSD
10
VSSD
42
P0.3
31
P0.3
11
VDDA
43
P0.4
32
P0.4
44
P0.5
33
P0.5
12
VSSA
45
P0.6
34
P0.6
13
P6.1
46
P0.7
35
P0.7
14
P6.2
47
XRES
36
XRES
15
P6.4
48
VCCD
37
VCCD
16
P6.5
49
VSSD
38
VSSD
17
VSSD
50
VDDD
39
VDDD
18
51
P5.0
19
52
P5.1
53
P5.2
54
55
56
VDDA
40
57
VSSA
41
58
P1.0
59
P1.1
60
61
11
VSSA
12
P6.5
P3.0
13
P3.0
P3.1
14
P3.1
20
P3.2
15
P3.2
21
P3.3
16
P3.3
P5.3
22
P3.4
17
P3.4
P5.5
23
P3.5
18
P3.5
VDDA
24
P3.6
19
P3.6
VSSA
25
P3.7
20
P3.7
42
P1.0
26
VDDD
21
VDDD
43
P1.1
27
P4.0
22
P4.0
P1.2
44
P1.2
28
P4.1
23
P4.1
P1.3
45
P1.3
29
P4.2
24
P4.2
62
P1.4
46
P1.4
30
P4.3
25
P4.3
63
P1.5
47
P1.5
31
P4.4
64
P1.6
48
P1.6
32
P4.5
1
P1.7
1
P1.7
33
P4.6
2
P2.0
2
P2.0
34
P4.7
3
P2.1
3
P2.1
35
P5.6
4
P2.2
4
P2.2
36
P5.7
5
P2.3
5
P2.3
37
P7.0
26
P7.0
6
P2.4
6
P2.4
38
P7.1
27
P7.1
7
P2.5
7
P2.5
Descriptions of the Power pins are as follows:
GPIOs by package:
VDDD: Power supply for the digital section.
VDDA: Power supply for the analog section.
VSSD, VSSA: Ground pins for the digital and analog sections
respectively.
Number
64-TQFP
48-TQFP
53
39
VCCD: Regulated digital supply (1.8 V ±5%)
Document Number: 002-26354 Rev. *C
Page 12 of 43
PSoC 4: PSoC 4500S Datasheet
Alternate Pin Functions
Each Port pin has can be assigned to one of multiple functions; it can, for example, be an analog I/O, a digital peripheral function, an LCD pin, or a CapSense pin. The pin
assignments are shown in the following table.
Name
Analog
ACT #1
ACT #3
DS #2
DS #3
P0.0
lpcomp.in_p[0]
Smart I/O
ACT #0
tcpwm.tr_in[0]
scb[2].uart_cts:0
scb[2].i2c_scl:0
scb[0].spi_select1:0
P0.1
lpcomp.in_n[0]
tcpwm.tr_in[1]
scb[2].uart_rts:0
scb[2].i2c_sda:0
scb[0].spi_select2:0
P0.2
lpcomp.in_p[1]
P0.3
lpcomp.in_n[1]
P0.4
wco_in
P0.5
wco_out
scb[0].spi_select3:0
scb[2].spi_select0:1
scb[1].uart_rx:0
P0.6
scb[2].uart_rx:0
scb[1].i2c_scl:0
scb[1].spi_mosi:1
scb[1].i2c_sda:0
scb[1].spi_miso:1
scb[1].uart_tx:0
scb[2].uart_tx:0
ext_clk
scb[1].uart_cts:0
scb[2].uart_tx:1
tcpwm.line[0]:3
scb[1].uart_rts:0
scb[1].spi_clk:1
eco_in
P0.7
eco_out
scb[1].spi_select0:1
P5.0
tcpwm.line[4]:2
P5.1
tcpwm.line_compl[4]:2
P5.2
tcpwm.line[5]:2
P5.3
tcpwm.line_compl[5]:2
scb[2].uart_rts:1
P5.5
P1.0
scb[2].uart_rx:1
scb[2].i2c_scl:1
scb[2].spi_mosi:0
scb[2].uart_tx:2
scb[2].i2c_sda:1
scb[2].spi_miso:0
scb[2].uart_cts:1
lpcomp.comp[0]:2
scb[2].spi_clk:0
lpcomp.comp[1]:0
scb[2].spi_select0:0
tcpwm.line_compl[6]:2
pass[0].ctb0_oa0+
tcpwm.line[2]:1
scb[2].spi_select2:0
scb[0].uart_rx:1
scb[0].i2c_scl:0
scb[0].spi_mosi:1
P1.1
pass[0].ctb0_oa0-
tcpwm.line_compl[2]:1
scb[0].uart_tx:1
scb[0].i2c_sda:0
scb[0].spi_miso:1
P1.2
pass[0].ctb0_oa0_out
tcpwm.line[3]:1
scb[0].uart_cts:1
tcpwm.tr_in[2]
scb[2].i2c_scl:2
scb[0].spi_clk:1
P1.3
pass[0].ctb0_oa1_out
tcpwm.line_compl[3]:1
scb[0].uart_rts:1
tcpwm.tr_in[3]
scb[2].i2c_sda:2
scb[0].spi_select0:1
P1.4
pass[0].ctb0_oa1-
tcpwm.line[6]:1
scb[3].i2c_scl:0
scb[0].spi_select1:1
P1.5
pass[0].ctb0_oa1+
tcpwm.line_compl[6]:1
scb[3].i2c_sda:0
scb[0].spi_select2:1
P1.6
pass[0].ctb0_oa0+
tcpwm.line[7]:1
scb[0].spi_select3:1
P1.7
pass[0].ctb0_oa1+
pass[0].sar_ext_vref
tcpwm.line_compl[7]:1
scb[2].spi_clk:1
P2.0
pass[0].sarmux_pads[0]
prgio[0].io[0]
tcpwm.line[4]:0
P2.1
pass[0].sarmux_pads[1]
prgio[0].io[1]
tcpwm.line_compl[4]:0
Document Number: 002-26354 Rev. *C
csd.comp
tcpwm.tr_in[4]
scb[1].i2c_scl:1
scb[1].spi_mosi:2
tcpwm.tr_in[5]
scb[1].i2c_sda:1
scb[1].spi_miso:2
Page 13 of 43
PSoC 4: PSoC 4500S Datasheet
Name
Analog
Smart I/O
ACT #0
ACT #1
ACT #3
DS #2
DS #3
P2.2
pass[0].sarmux_pads[2]
prgio[0].io[2]
tcpwm.line[5]:1
scb[1].spi_clk:2
P2.3
pass[0].sarmux_pads[3]
prgio[0].io[3]
tcpwm.line_compl[5]:1
scb[1].spi_select0:2
P2.4
pass[0].sarmux_pads[4]
prgio[0].io[4]
tcpwm.line[0]:1
scb[3].uart_rx:1
scb[1].spi_select1:1
P2.5
pass[0].sarmux_pads[5]
prgio[0].io[5]
tcpwm.line_compl[0]:1
scb[3].uart_tx:1
scb[1].spi_select2:1
P2.6
pass[0].sarmux_pads[6]
prgio[0].io[6]
tcpwm.line[1]:1
scb[3].uart_cts:1
scb[1].spi_select3:1
P2.7
pass[0].sarmux_pads[7]
prgio[0].io[7]
tcpwm.line_compl[1]:1
scb[3].uart_rts:1
lpcomp.comp[0]:0
scb[2].spi_mosi:1
P6.1
pass[1].ctb0_oa0+
tcpwm.line_compl[4]:1
scb[3].uart_tx:0
scb[3].i2c_sda:1
scb[3].spi_miso:0
P6.2
pass[1].ctb0_oa0-
tcpwm.line[5]:0
scb[3].uart_cts:0
tcpwm.line[6]:3
scb[4].i2c_scl
scb[3].spi_select1:1
tcpwm.line_compl[6]:3
scb[4].i2c_sda
scb[3].spi_select2:1
scb[1].uart_rx:1
scb[1].i2c_scl:2
scb[1].spi_mosi:0
P6.4
scb[3].spi_clk:0
pass[1].ctb0_oa0_out
P6.5
pass[1].ctb0_oa0+
pass[1].sar_ext_vref
P3.0
pass[1].sarmux_pads[0]
prgio[1].io[0]
tcpwm.line[0]:0
P3.1
pass[1].sarmux_pads[1]
prgio[1].io[1]
tcpwm.line_compl[0]:0
scb[1].uart_tx:1
scb[1].i2c_sda:2
scb[1].spi_miso:0
P3.2
pass[1].sarmux_pads[2]
prgio[1].io[2]
tcpwm.line[1]:0
scb[1].uart_cts:1
cpuss.swd_data
scb[1].spi_clk:0
scb[1].uart_rts:1
cpuss.swd_clk
scb[1].spi_select0:0
P3.3
pass[1].sarmux_pads[3]
prgio[1].io[3]
tcpwm.line_compl[1]:0
P3.4
pass[1].sarmux_pads[4]
prgio[1].io[4]
tcpwm.line[2]:0
P3.5
pass[1].sarmux_pads[5]
prgio[1].io[5]
tcpwm.line_compl[2]:0
P3.6
pass[1].sarmux_pads[6]
prgio[1].io[6]
tcpwm.line[3]:0
prgio[1].io[7]
tcpwm.line_compl[3]:0
P3.7
pass[1].sarmux_pads[7]
P4.0
csd.vref_ext
P4.1
csd.cshield
P4.2
csd.cmod
P4.3
csd.csh_tank
tcpwm.tr_in[6]
scb[1].spi_select2:0
scb[4].spi_select3
P4.5
scb[1].spi_select3:0
lpcomp.comp[1]:1
scb[2].spi_miso:1
scb[0].i2c_scl:1
scb[0].spi_mosi:0
scb[0].uart_tx:0
scb[0].i2c_sda:1
scb[0].spi_miso:0
scb[0].uart_cts:0
lpcomp.comp[0]:1
scb[0].spi_clk:0
scb[0].uart_rts:0
lpcomp.comp[1]:2
scb[0].spi_select0:0
scb[4].uart_rx
scb[4].spi_mosi
scb[0].spi_select1:2
scb[0].uart_rx:0
P4.4
scb[1].spi_select1:0
scb[4].uart_tx
scb[4].spi_miso
scb[0].spi_select2:2
P4.6
tcpwm.line[6]:0
scb[4].uart_cts
scb[4].spi_clk
scb[0].spi_select3:2
P4.7
tcpwm.line_compl[6]:0
scb[4].uart_rts
P5.6
tcpwm.line[7]:0
Document Number: 002-26354 Rev. *C
scb[4].spi_select0
scb[3].spi_select2:0
scb[4].spi_select1
scb[2].spi_select3:0
Page 14 of 43
PSoC 4: PSoC 4500S Datasheet
Name
Analog
Smart I/O
ACT #0
ACT #1
ACT #3
DS #2
DS #3
P5.7
tcpwm.line_compl[7]:0
scb[4].spi_select2
scb[3].spi_select1:0
P7.0
tcpwm.line[0]:2
scb[3].uart_rx:2
scb[3].i2c_scl:2
scb[3].spi_mosi:1
P7.1
tcpwm.line_compl[0]:2
scb[3].uart_tx:2
scb[3].i2c_sda:2
scb[3].spi_miso:1
Document Number: 002-26354 Rev. *C
Page 15 of 43
PSoC 4: PSoC 4500S Datasheet
Power
Mode 1: 1.8 V to 5.5 V External Supply
The following power system diagram shows the set of power
supply pins as implemented for PSoC 4500S. The system has
one regulator in Active mode for the digital circuitry. There is no
analog regulator; the analog circuits run directly from the VDDA
input.
Figure 6. Power Supply Connections
VDDA
VDDD
VDDA
VSSA
Mode 2: 1.8 V ±5% External Supply
VDDD
Analog
Domain
In this mode, PSoC 4500S is powered by an external power
supply that must be within the range of 1.71 to 1.89 V; note that
this range needs to include the power supply ripple too. In this
mode, the VDD and VCCD pins are shorted together and
bypassed. The internal regulator can be disabled in the firmware.
Digital
Domain
VSSD
1.8 Volt
Regulator
In this mode, PSoC 4500S is powered by an external power
supply that can be anywhere in the range of 1.8 to 5.5 V. This
range is also designed for battery-powered operation. For
example, the chip can be powered from a battery system that
starts at 3.5 V and works down to 1.8 V. In this mode, the internal
regulator of PSoC 4500S supplies the internal logic and its output
is connected to the VCCD pin. The VCCD pin must be bypassed
to ground via an external capacitor (0.1 µF; X5R ceramic or
better) and must not be connected to anything else.
Bypass capacitors must be used from VDDD to ground. The
typical practice for systems in this frequency range is to use a
capacitor in the 1-µF range, in parallel with a smaller capacitor
(0.1 µF, for example). Note that these are simply rules of thumb
and that, for critical applications, the PCB layout, lead inductance, and the bypass capacitor parasitic should be simulated to
design and obtain optimal bypassing.
VCCD
There are two distinct modes of operation. In Mode 1, the supply
voltage range is 1.8 V to 5.5 V (unregulated externally; internal
regulator operational). In Mode 2, the supply range is1.8 V ±5%
(externally regulated; 1.71 to 1.89, internal regulator bypassed).
An example of a bypass scheme is shown in the following
diagram.
Figure 7. External Supply Range from 1.8 V to 5.5 V with Internal Regulator Active
Power supply bypass connections example
1.8 V to 5.5 V
1.8 V to 5.5 V
VDDA
VDDD
1 F
1 F
0.1 F
0.1 F
VCCD
0.1 F
PSoC 4500S
VSS
Document Number: 002-26354 Rev. *C
Page 16 of 43
PSoC 4: PSoC 4500S Datasheet
Electrical Specifications
Absolute Maximum Ratings
Table 1. Absolute Maximum Ratings[1]
Spec ID#
SID1
SID2
Parameter
Description
Min
Typ
Max
Unit
VDDD_ABS
Digital supply relative to VSS
–0.5
–
6
V
VCCD_ABS
Direct digital core voltage input relative
to VSS
–0.5
–
1.95
V
Details/
Conditions
–
–
SID3
VGPIO_ABS
GPIO voltage
–0.5
–
VDD+0.5
V
–
SID4
IGPIO_ABS
Maximum current per GPIO
–25
–
25
mA
–
SID5
IGPIO_injection
GPIO injection current, Max for VIH >
VDDD, and Min for VIL < VSS
–0.5
–
0.5
mA
Current injected
per pin
BID44
ESD_HBM
Electrostatic discharge human body
model
2200
–
–
V
BID45
ESD_CDM
Electrostatic discharge charged device
model
500
–
–
V
BID46
LU
Pin current for latch-up
–140
–
140
mA
–
–
–
Device Level Specifications
All specifications are valid for –40 °C TA 105 °C and TJ 125 °C, except where noted. Specifications are valid for 1.71 V to 5.5 V,
except where noted.
Table 2. DC Specifications
Typical values measured at VDD = 3.3 V and 25 °C.
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details/
Conditions
SID53
VDD
Power supply input voltage
1.8
–
5.5
V
Internally
regulated supply
SID255
VDD
Power supply input voltage (VCCD =
VDDD = VDDA)
1.71
–
1.89
V
Internally
unregulated
supply
SID54
VCCD
Output voltage (for core logic)
–
1.8
–
V
–
SID55
CEFC
External regulator voltage bypass
–
0.1
–
µF
X5R ceramic or
better
SID56
CEXC
Power supply bypass capacitor
–
1
–
µF
X5R ceramic or
better
Active Mode, VDD = 1.8 V to 5.5 V. Typical values measured at VDD = 3.3 V and 25 °C.
SID10
IDD5
Execute from flash; CPU at 6 MHz
–
1.8
2.4
mA
–
SID16
IDD8
Execute from flash; CPU at 24 MHz
–
3.0
4.6
mA
–
SID19
IDD11
Execute from flash; CPU at 48 MHz
–
5.4
7.1
mA
–
–
1.1
2.1
mA
6 MHZ
–
1.5
2.8
mA
12 MHZ
Sleep Mode, VDDD = 1.8 V to 5.5 V (Regulator on)
SID22
SID25
IDD17
IDD20
I2C wakeup WDT, and Comparators on
2
I C wakeup, WDT, and Comparators on
Note
1. Usage above the absolute maximum conditions listed in Table 1 may cause permanent damage to the device. Exposure to Absolute Maximum conditions for extended
periods of time may affect device reliability. The Maximum Storage Temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below Absolute Maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 002-26354 Rev. *C
Page 17 of 43
PSoC 4: PSoC 4500S Datasheet
Table 2. DC Specifications (continued)
Typical values measured at VDD = 3.3 V and 25 °C.
Spec ID#
Parameter
Description
Details/
Conditions
Min
Typ
Max
Unit
–
1.1
2.1
mA
6 MHZ
–
1.5
2.8
mA
12 MHZ
Sleep Mode, VDDD = 1.71 V to 1.89 V (Regulator bypassed)
SID28
SID28A
IDD23
IDD23A
I2C wakeup, WDT, and Comparators on
2
I C wakeup, WDT, and Comparators on
Deep Sleep Mode, VDD = 1.8 V to 3.6 V (Regulator on)
SID30
IDD25
I2C wakeup and WDT on; T = –40 °C to
60 °C
–
2.5
40
µA
T = –40 °C to
60 °C
SID31
IDD26
I2C wakeup and WDT on
–
2.5
125
µA
Max is at 3.6 V
and 85 °C
2.5
40
µA
2.5
125
2.5
60
Deep Sleep Mode, VDD = 3.6 V to 5.5 V (Regulator on)
SID33
IDD28
I2C wakeup and WDT on; T = –40 °C to
60 °C
–
SID34
IDD29
I2C wakeup and WDT on
–
µA
T = –40 °C to
60 °C
Max is at 5.5 V
and 85 °C
Deep Sleep Mode, VDD = VCCD = 1.71 V to 1.89 V (Regulator bypassed)
SID36
IDD31
I2C wakeup and WDT on; T = –40 °C to
60 °C
–
SID37
IDD32
I2C wakeup and WDT on
–
2.5
180
IDD_XR
Supply current while XRES asserted
–
2
Min
µA
T = –40 °C to
60 °C
µA
Max is at 1.89 V
and 85 °C
5
mA
–
Typ
Max
Unit
DC
–
48
MHz
XRES Current
SID307
Table 3. AC Specifications
Spec ID#
Parameter
Description
Details/
Conditions
1.71 VDD 5.5
FCPU
CPU frequency
[2]
TSLEEP
Wakeup from Sleep mode
–
0
–
µs
–
[2]
TDEEPSLEEP
Wakeup from Deep Sleep mode
–
35
–
µs
–
SID48
SID49
SID50
Note
2. Guaranteed by characterization.
Document Number: 002-26354 Rev. *C
Page 18 of 43
PSoC 4: PSoC 4500S Datasheet
GPIO
Table 4. GPIO DC Specifications
Spec ID#
SID57
Parameter
VIH
[3]
Description
Input voltage high threshold
Min
Typ
Max
Unit
0.7 VDDD
Details/Conditions
–
–
V
CMOS Input
0.3
VDDD
V
CMOS Input
–
SID58
VIL
Input voltage low threshold
–
–
SID241
VIH[3]
LVTTL input, VDDD < 2.7 V
0.7 VDDD
–
–
V
SID242
VIL
LVTTL input, VDDD < 2.7 V
–
–
0.3
VDDD
V
SID243
VIH[3]
LVTTL input, VDDD 2.7 V
2.0
–
–
V
–
SID244
VIL
LVTTL input, VDDD 2.7 V
–
–
0.8
V
–
SID59
VOH
Output voltage high level
VDDD –0.6
–
–
V
IOH = 4 mA at 3 V VDDD
SID60
VOH
Output voltage high level
VDDD –0.5
–
–
V
IOH = 1 mA at 1.8 V VDDD
SID61
VOL
Output voltage low level
–
–
0.6
V
IOL = 4 mA at 1.8 V VDDD
SID62
VOL
Output voltage low level
–
–
0.6
V
IOL = 10 mA at 3 V VDDD
SID62A
VOL
Output voltage low level
–
–
0.4
V
IOL = 3 mA at 3 V VDDD
SID63
RPULLUP
Pull-up resistor
3.5
5.6
8.5
kΩ
–
SID64
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
kΩ
–
SID65
IIL
Input leakage current (absolute
value)
–
–
2
nA
25 °C, VDDD = 3.0 V
SID66
CIN
Input capacitance
–
–
7
pF
–
SID67[4]
VHYSTTL
Input hysteresis LVTTL
25
40
–
mV
VDDD 2.7 V
VHYSCMOS
Input hysteresis CMOS
0.05 × VDDD
–
–
mV
VDD < 4.5 V
200
–
–
mV
VDD > 4.5 V
–
[4]
SID68
SID68A
[4]
VHYSCMOS5V5 Input hysteresis CMOS
SID69[4]
IDIODE
Current through protection diode to
VDD/VSS
–
–
100
µA
SID69A[4]
ITOT_GPIO
Maximum total source or sink chip
current
–
–
200
mA
–
–
Notes
3. VIH must not exceed VDDD + 0.2 V.
4. Guaranteed by characterization.
Document Number: 002-26354 Rev. *C
Page 19 of 43
PSoC 4: PSoC 4500S Datasheet
Table 5. GPIO AC Specifications
(Guaranteed by Characterization)
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
SID70
TRISEF
Rise time in fast strong mode
2
–
12
ns
3.3 V VDDD,
Cload = 25 pF
SID71
TFALLF
Fall time in fast strong mode
2
–
12
ns
3.3 V VDDD,
Cload = 25 pF
SID72
TRISES
Rise time in slow strong mode
10
–
60
ns
3.3 V VDDD,
Cload = 25 pF
SID73
TFALLS
Fall time in slow strong mode
10
–
60
ns
3.3 V VDDD,
Cload = 25 pF
SID74
FGPIOUT1
GPIO FOUT; 3.3 V VDDD 5.5 V
Fast strong mode
–
–
33
MHz
90/10%, 25 pF load,
60/40 duty cycle
SID75
FGPIOUT2
GPIO FOUT; 1.71 VVDDD3.3 V
Fast strong mode
–
–
16.7
MHz
90/10%, 25 pF load,
60/40 duty cycle
SID76
FGPIOUT3
GPIO FOUT; 3.3 V VDDD 5.5 V
Slow strong mode
–
–
7
MHz
90/10%, 25 pF load,
60/40 duty cycle
SID245
FGPIOUT4
GPIO FOUT; 1.71 V VDDD 3.3 V
Slow strong mode.
–
–
3.5
MHz
90/10%, 25 pF load,
60/40 duty cycle
SID246
FGPIOIN
GPIO input operating frequency;
1.71 V VDDD 5.5 V
–
–
48
MHz
90/10% VIO
XRES
Table 6. XRES DC Specifications
Min
Typ
Max
Unit
SID77
Spec ID#
VIH
Parameter
Input voltage high threshold
Description
0.7 × VDDD
–
–
V
Details/Conditions
SID78
VIL
Input voltage low threshold
–
–
0.3 VDDD
V
SID79
RPULLUP
Pull-up resistor
–
60
–
kΩ
–
SID80
CIN
Input capacitance
–
–
7
pF
–
SID81[5]
VHYSXRES
Input voltage hysteresis
–
100
–
mV
Typical hysteresis is
200 mV for VDD > 4.5 V
SID82
IDIODE
Current through protection diode
to VDD/VSS
–
–
100
µA
CMOS Input
–
Table 7. XRES AC Specifications
Min
Typ
Max
Unit
SID83[5]
Spec ID#
TRESETWIDTH
Parameter
Reset pulse width
Description
1
–
–
µs
–
Details/Conditions
BID194[5]
TRESETWAKE
Wake-up time from reset release
–
–
2.7
ms
–
Note
5. Guaranteed by characterization.
Document Number: 002-26354 Rev. *C
Page 20 of 43
PSoC 4: PSoC 4500S Datasheet
Analog Peripherals
CTBm Opamp
Table 8. CTBm Opamp Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
IDD
Opamp block current, External load
SID269
IDD_HI
power=hi
–
1100
1900
µA
–
SID270
IDD_MED
power=med
–
550
1020
µA
–
SID271
IDD_LOW
power=lo
–
150
370
µA
–
GBW
Load = 50 pF, 0.1 mA
VDDA = 2.7 V
SID272
GBW_HI
power=hi
6
–
–
MHz
Input and output are
0.2 V to VDDA-0.2 V
SID273
GBW_MED
power=med
3
–
–
MHz
Input and output are
0.2 V to VDDA-0.2 V
SID274
GBW_LO
power=lo
–
1
–
MHz
Input and output are
0.2 V to VDDA-0.2 V
IOUT_MAX
VDDA = 2.7 V, 500 mV from rail
SID275
IOUT_MAX_HI
power=hi
10
–
–
mA
Output is 0.5 V to
VDDA -0.5 V
SID276
IOUT_MAX_MID
power=mid
10
–
–
mA
Output is 0.5 V to
VDDA -0.5 V
SID277
IOUT_MAX_LO
power=lo
–
5
–
mA
Output is 0.5 V to
VDDA -0.5 V
IOUT
VDDA = 1.71 V, 500 mV from rail
SID278
IOUT_MAX_HI
power=hi
4
–
–
mA
Output is 0.5 V to
VDDA -0.5 V
SID279
IOUT_MAX_MID
power=mid
4
–
–
mA
Output is 0.5 V to
VDDA-0.5 V
SID280
IOUT_MAX_LO
power=lo
–
2
–
mA
Output is 0.5 V to
VDDA-0.5 V
IDD_Int
Opamp block current Internal Load
SID269_I
IDD_HI_Int
power=hi
–
1500
1700
µA
–
SID270_I
IDD_MED_Int
power=med
–
700
980
µA
–
IDD_LOW_Int
power=lo
–
–
405
µA
–
GBW
VDDA = 2.7 V
–
–
–
GBW_HI_Int
power=hi
8
–
–
MHz
SID271_I
SID272_I
–
Output is 0.25 V to
VDDA-0.25 V
General opamp specs for both
internal and external modes
SID281
VIN
Charge-pump on, VDDA = 2.7 V
–0.05
–
VDDA-0.2
V
–
SID282
VCM
Charge-pump on, VDDA = 2.7 V
–0.05
–
VDDA-0.2
V
–
VOUT
VDDA = 2.7 V
SID283
VOUT_1
power=hi, Iload=10 mA
0.5
–
VDDA -0.5
V
–
SID284
VOUT_2
power=hi, Iload=1 mA
0.2
–
VDDA -0.2
V
–
Document Number: 002-26354 Rev. *C
Page 21 of 43
PSoC 4: PSoC 4500S Datasheet
Table 8. CTBm Opamp Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
SID285
VOUT_3
power=med, Iload=1 mA
0.2
–
VDDA -0.2
V
–
SID286
VOUT_4
power=lo, Iload=0.1 mA
0.2
–
VDDA -0.2
V
–
SID288
VOS_TR
Offset voltage, trimmed
–1.0
0.5
1.0
mV
High mode, input 0 V
to VDDA-0.2 V
SID288A
VOS_TR
Offset voltage, trimmed
–
1
–
mV
Medium mode, input
0 V to VDDA-0.2 V
SID288B
VOS_TR
Offset voltage, trimmed
–
2
–
mV
Low mode, input 0 V
to VDDA-0.2 V
SID290
VOS_DR_TR
Offset voltage drift, trimmed
–10
3
10
µV/°C
High mode
SID290A
VOS_DR_TR
Offset voltage drift, trimmed
–
10
–
µV/°C
Medium mode
10
–
µV/°C
Low mode
80
–
dB
Input is 0 V to
VDDA-0.2 V, Output is
0.2 V to VDDA-0.2 V
dB
VDDD = 3.6 V,
high-power mode,
input is 0.2 V to
VDDA-0.2 V
SID290B
VOS_DR_TR
Offset voltage drift, trimmed
–
SID291
CMRR
DC
70
SID292
PSRR
At 1 kHz, 10-mV ripple
70
85
–
Noise
SID294
VN2
Input-referred, 1 kHz, power = Hi
–
72
–
Input and output are
nV/rtHz at
0.2 V to VDDA-0.2 V
SID295
VN3
Input-referred, 10 kHz, power = Hi
–
28
–
Input and output are
nV/rtHz at 0.2 V to
VDDA-0.2 V
SID296
VN4
Input-referred, 100 kHz, power = Hi
–
15
–
Input and output are
nV/rtHz at 0.2 V to
VDDA-0.2 V
SID297
CLOAD
Stable up to max. load. Performance
specs at 50 pF.
–
–
125
pF
SID298
SLEW_RATE
Cload = 50 pF, Power = High,
VDDA = 2.7 V
4
–
–
V/µs
SID299
T_OP_WAKE
From disable to enable, no external
RC dominating
–
–
25
µs
SID299A
OL_GAIN
Open Loop Gain
–
90
–
dB
–
COMP_MODE
Comparator mode; 50 mV drive,
Trise=Tfall (approx.)
SID300
TPD1
Response time; power=hi
–
150
–
ns
Input is 0.2 V to
VDDA-0.2 V
SID301
TPD2
Response time; power=med
–
500
–
ns
Input is 0.2 V to
VDDA-0.2 V
SID302
TPD3
Response time; power=lo
–
2500
–
ns
Input is 0.2 V to
VDDA-0.2 V
SID303
VHYST_OP
Hysteresis
–
10
–
mV
–
Document Number: 002-26354 Rev. *C
–
–
–
Page 22 of 43
PSoC 4: PSoC 4500S Datasheet
Table 8. CTBm Opamp Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
–
–
25
µs
Details/Conditions
–
WUP_CTB
Wake-up time from Enabled to
Usable
Deep Sleep
Mode
Mode 2 is lowest current range.
Mode 1 has higher GBW.
SID_DS_1
IDD_HI_M1
Mode 1, High current
–
1400
–
µA
25 °C
SID_DS_2
IDD_MED_M1
Mode 1, Medium current
–
700
–
µA
25 °C
200
–
µA
25 °C
SID304
SID_DS_3
IDD_LOW_M1
Mode 1, Low current
–
SID_DS_4
IDD_HI_M2
Mode 2, High current
–
120
–
µA
25 °C
SID_DS_5
IDD_MED_M2
Mode 2, Medium current
–
60
–
µA
25 °C
SID_DS_6
IDD_LOW_M2
Mode 2, Low current
–
15
–
µA
25 °C
SID_DS_7
GBW_HI_M1
Mode 1, High current
–
4
–
MHz
20-pF load, no DC
load 0.2 V to
VDDA-0.2 V
SID_DS_8
GBW_MED_M1
Mode 1, Medium current
–
2
–
MHz
20-pF load, no DC
load 0.2 V to
VDDA-0.2 V
SID_DS_9
GBW_LOW_M1
Mode 1, Low current
–
0.5
–
MHz
20-pF load, no DC
load 0.2 V to
VDDA-0.2 V
SID_DS_10 GBW_HI_M2
Mode 2, High current
–
0.5
–
MHz
20-pF load, no DC
load 0.2 V to
VDDA-0.2 V
SID_DS_11 GBW_MED_M2
Mode 2, Medium current
–
0.2
–
MHz
20-pF load, no DC
load 0.2 V to
VDDA-0.2 V
SID_DS_12 GBW_Low_M2
Mode 2, Low current
–
0.1
–
MHz
20-pF load, no DC
load 0.2 V to
VDDA-0.2 V
SID_DS_13 VOS_HI_M1
Mode 1, High current
–
5
–
mV
With trim 25 °C, 0.2 V
to VDDA-0.2 V
SID_DS_14 VOS_MED_M1
Mode 1, Medium current
–
5
–
mV
With trim 25 °C, 0.2 V
to VDDA-0.2 V
SID_DS_15 VOS_LOW_M1
Mode 1, Low current
–
5
–
mV
With trim 25 °C, 0.2 V
to VDDA-0.2 V
SID_DS_16 VOS_HI_M2
Mode 2, High current
–
5
–
mV
With trim 25 °C, 0.2V
to VDDA-0.2 V
SID_DS_17 VOS_MED_M2
Mode 2, Medium current
–
5
–
mV
With trim 25 °C, 0.2 V
to VDDA-0.2 V
SID_DS_18 VOS_LOW_M2
Mode 2, Low current
–
5
–
mV
With trim 25 °C, 0.2 V
to VDDA-0.2 V
SID_DS_19 IOUT_HI_M1
Mode 1, High current
–
10
–
mA
Output is 0.5 V to
VDDA-0.5 V
SID_DS_20 IOUT_MED_M1
Mode 1, Medium current
–
10
–
mA
Output is 0.5 V to
VDDA-0.5 V
Document Number: 002-26354 Rev. *C
Page 23 of 43
PSoC 4: PSoC 4500S Datasheet
Table 8. CTBm Opamp Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
SID_DS_21 IOUT_LOW_M1
Mode 1, Low current
–
4
–
mA
Output is 0.5 V to
VDDA-0.5 V
SID_DS_22 IOUT_HI_M2
Mode 2, High current
–
1
–
mA
–
SID_DS_23 IOUT_MED_M2
Mode 2, Medium current
–
1
–
mA
–
SID_DS_24 IOUT_LOW_M2
Mode 2, Low current
–
0.5
–
mA
–
Comparator
Table 9. Comparator DC Specifications
Max
Unit
SID84
Spec ID#
VOFFSET1
Parameter
Input offset voltage, Factory trim
Description
Min Typ
–
–
±10
mV
–
Details/Conditions
SID85
VOFFSET2
Input offset voltage, Custom trim
–
–
±4
mV
–
SID86
VHYST
Hysteresis when enabled
–
10
35
mV
–
SID87
VICM1
Input common mode voltage in normal
mode
0
–
VDDD-0.1
V
SID247
VICM2
Input common mode voltage in low
power mode
0
–
VDDD
V
SID247A
VICM3
Input common mode voltage in ultra
low power mode
0
–
VDDD-1.15
V
VDDD ≥ 2.2 V at –40 °C
SID88
CMRR
Common mode rejection ratio
50
–
–
dB
VDDD ≥ 2.7V
SID88A
CMRR
Common mode rejection ratio
42
–
–
dB
VDDD ≤ 2.7V
SID89
ICMP1
Block current, normal mode
–
–
400
µA
–
SID248
ICMP2
Block current, low power mode
–
–
100
µA
–
SID259
ICMP3
Block current in ultra low-power mode
–
–
6
µA
VDDD ≥ 2.2 V at –40 °C
SID90
ZCMP
DC Input impedance of comparator
35
–
–
MΩ
–
Modes 1 and 2
–
Table 10. Comparator AC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
SID91
TRESP1
Response time, normal mode, 50 mV
overdrive
–
38
110
ns
SID258
TRESP2
Response time, low power mode, 50 mV
overdrive
–
70
200
ns
SID92
TRESP3
Response time, ultra-low power mode,
200 mV overdrive
–
2.3
15
µs
Details/Conditions
–
–
VDDD ≥ 2.2 V at –40 °C
Temperature Sensor
Table 11. Temperature Sensor Specifications
Spec ID#
SID93
Parameter
Description
TSENSACC
Temperature sensor accuracy
Min
Typ
Max
Unit
–5
±1
5
°C
Details/
Conditions
–40 to +85 °C
Note
6. Guaranteed by characterization.
Document Number: 002-26354 Rev. *C
Page 24 of 43
PSoC 4: PSoC 4500S Datasheet
SAR ADC
Table 12. SAR ADC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Resolution
–
–
12
bits
Details/
Conditions
SAR ADC DC Specifications
SID94
A_RES
SID95
A_CHNLS_S
Number of channels - single ended
–
–
16
–
SID96
A-CHNKS_D
Number of channels - differential
–
–
4
Diff inputs use
neighboring I/O
SID97
A-MONO
Monotonicity
SID98
A_GAINERR
Gain error
–
–
±0.125
%
With external
reference
SID99
A_OFFSET
Input offset voltage
–
–
±2.3
mV
Measured with 1-V
reference
SID100
A_ISAR
Current consumption
–
–
1
mA
–
SID101
A_VINS
Input voltage range - single ended
VSS
–
VDDA
V
–
VSS
–
VDDA
V
–
–
–
2.2
KΩ
–
Yes
SID102
A_VIND
Input voltage range - differential
SID103
A_INRES
Input resistance
SID104
A_INCAP
Input capacitance
SID260
VREFSAR
Trimmed internal reference to SAR
–
–
–
–
10
pF
–
1.188
1.2
1.212
V
–
Power supply rejection ratio
70
–
–
dB
–
dB
Measured at 1 V
SAR ADC AC Specifications
SID106
A_PSRR
SID107
A_CMRR
Common mode rejection ratio
66
–
–
SID108
A_SAMP
Sample rate
–
–
1
Msps –
SID109
A_SNR
Signal-to-noise and distortion ratio (SINAD)
64
–
–
dB
FIN = 10 kHz
SID110
A_BW
Input bandwidth without aliasing
–
–
A_samp/2
kHz
–
SID111
A_INL
Integral Non Linearity for SAR_1
–1
–
1
LSB
SAR_1
SID111A
A_INL
Integral Non Linearity for SAR_0
–3
–
3
LSB
SAR_0
SID112
A_DNL
Integral Non Linearity for SAR_1
–1
–
1
LSB
SAR_1
SID112A
A_DNL
Differential Non Linearity for SAR_0
–1
–
3
LSB
SAR_0
SID113
A_THD
Total harmonic distortion
–
–
–62
dB
SID261
FSARINTREF SAR operating speed without external reference
bypass
100
ksps
–
–
Fin = 10 kHz
12-bit resolution
CSD and IDAC
Table 13. CSD and IDAC Specifications
Min
Typ
Max
Unit
SYS.PER#3
Spec ID#
VDD_RIPPLE Max allowed ripple on power
supply, DC to 10 MHz
Parameter
–
–
±50
mV
VDD > 2 V (with ripple),
25 °C TA, Sensitivity =
0.1 pF
SYS.PER#16
VDD_RIPPLE_1.8
Max allowed ripple on power
supply, DC to 10 MHz
–
–
±25
mV
VDD > 1.75V (with ripple),
25 °C TA, Parasitic Capacitance (CP) < 20 pF,
Sensitivity ≥ 0.4 pF
Maximum block current
–
–
4000
µA
Maximum block current for
both IDACs in dynamic
(switching) mode including
comparators, buffer, and
reference generator
SID.CSD.BLK ICSD
Description
Document Number: 002-26354 Rev. *C
Details / Conditions
Page 25 of 43
PSoC 4: PSoC 4500S Datasheet
Table 13. CSD and IDAC Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
0.6
1.2
VDDA - 0.6
V
VDDA – 0.6 or 4.4, whichever
is lower
SID.CSD#15
VREF
Voltage reference for CSD and
Comparator
SID.CSD#16
IDAC1IDD
IDAC1 (7-bits) block current
–
–
1750
µA
–
SID.CSD#17
IDAC2IDD
IDAC2 (7-bits) block current
–
–
1750
µA
–
Voltage range of operation
1.71
–
5.5
V
1.8 V ±5% or 1.8 V to 5.5 V
0.6
–
VDDA –0.6
V
VDDA – 0.6 or 4.4, whichever
is lower
SID308
VCSD
SID308A
VCOMPIDAC Voltage compliance range of
IDAC
SID309
IDAC1DNL
IDAC1DNL
–1
–
1
LSB
–
SID310
IDAC1INL
IDAC1INL
–2
–
2
LSB
INL is ±5.5 LSB for VDDA <
2V
SID311
IDAC2DNL
IDAC2DNL
–1
–
1
LSB
–
SID312
IDAC2INL
IDAC2INL
–2
–
2
LSB
INL is ±5.5 LSB for VDDA <
2V
SID313
SNR
Ratio of counts of finger to noise.
Guaranteed by characterization
5
–
–
Ratio Capacitance range of 5 to
35 pF, 0.1-pF sensitivity. All
use cases. VDDA > 2 V.
SID314
IDAC1CRT1
Output current of IDAC1 (7 bits)
in low range
4.2
–
5.4
µA
LSB = 37.5-nA typ
SID314A
IDAC1CRT2
Output current of IDAC1(7 bits) in
medium range
34
–
41
µA
LSB = 300-nA typ
SID314B
IDAC1CRT3
Output current of IDAC1(7 bits) in
high range
275
–
330
µA
LSB = 2.4-µA typ
SID314C
IDAC1CRT12 Output current of IDAC1 (7 bits)
in low range, 2X mode
8
–
10.5
µA
LSB = 75-nA typ
SID314D
IDAC1CRT22 Output current of IDAC1(7 bits) in
medium range, 2X mode
69
–
82
µA
LSB = 600-nA typ.
SID314E
IDAC1CRT32 Output current of IDAC1(7 bits) in
high range, 2X mode
540
–
660
µA
LSB = 4.8-µA typ
SID315
IDAC2CRT1
Output current of IDAC2 (7 bits)
in low range
4.2
–
5.4
µA
LSB = 37.5-nA typ
SID315A
IDAC2CRT2
Output current of IDAC2 (7 bits)
in medium range
34
–
41
µA
LSB = 300-nA typ
SID315B
IDAC2CRT3
Output current of IDAC2 (7 bits)
in high range
275
–
330
µA
LSB = 2.4-µA typ
SID315C
IDAC2CRT12 Output current of IDAC2 (7 bits)
in low range, 2X mode
8
–
10.5
µA
LSB = 75-nA typ
SID315D
IDAC2CRT22 Output current of IDAC2(7 bits) in
medium range, 2X mode
69
–
82
µA
LSB = 600-nA typ
SID315E
IDAC2CRT32 Output current of IDAC2(7 bits) in
high range, 2X mode
540
–
660
µA
LSB = 4.8-µA typ
SID315F
IDAC3CRT13 Output current of IDAC in 8-bit
mode in low range
8
–
10.5
µA
LSB = 37.5-nA typ
SID315G
IDAC3CRT23 Output current of IDAC in 8-bit
mode in medium range
69
–
82
µA
LSB = 300-nA typ
SID315H
IDAC3CRT33 Output current of IDAC in 8-bit
mode in high range
540
–
660
µA
LSB = 2.4-µA typ
SID320
IDACOFFSET All zeroes input
–
–
1
LSB
SID321
IDACGAIN
–
–
±10
%
Full-scale error less offset
Document Number: 002-26354 Rev. *C
Polarity set by Source or
Sink. Offset is 2 LSBs for
37.5 nA/LSB mode
–
Page 26 of 43
PSoC 4: PSoC 4500S Datasheet
Table 13. CSD and IDAC Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
SID322
IDACMISMATCH1
Mismatch between IDAC1 and
IDAC2 in Low range
–
–
9.2
LSB
LSB = 37.5-nA typ
SID322A
IDACMISMATCH2
Mismatch between IDAC1 and
IDAC2 in Medium range
–
–
5.6
LSB
LSB = 300-nA typ
SID322B
IDACMISMATCH3
Mismatch between IDAC1 and
IDAC2 in High range
–
–
6.8
LSB
LSB = 2.4-µA typ
SID323
IDACSET8
Settling time to 0.5 LSB for 8-bit
IDAC
–
–
5
µs
Full-scale transition. No
external load
SID324
IDACSET7
Settling time to 0.5 LSB for 7-bit
IDAC
–
–
5
µs
Full-scale transition. No
external load
SID325
CMOD
External modulator capacitor.
–
2.2
–
nF
5-V rating, X7R or NP0 cap
10-bit CapSense ADC
Table 14. 10-bit CapSense ADC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
SIDA94
A_RES
Resolution
–
–
10
bits Auto-zeroing is required
every millisecond
SIDA95
A_CHNLS_S
Number of channels - single ended
–
–
16
SIDA97
A-MONO
Monotonicity
SIDA98
A_GAINERR
Gain error
–
–
±3
SIDA99
A_OFFSET
Input offset voltage
–
–
±18
mV In VREF (2.4 V) mode with
VDDA bypass capacitance of 10 µF
SIDA100
A_ISAR
Current consumption
–
–
0.25
mA –
VSSA
–
VDDA
V
–
–
2.2
–
KΩ
–
Defined by AMUX Bus
Yes
–
%
In VREF (2.4 V) mode with
VDDA bypass capacitance of 10 µF
SIDA101
A_VINS
Input voltage range - single ended
SIDA103
A_INRES
Input resistance
SIDA104
A_INCAP
Input capacitance
–
20
–
pF
–
SIDA106
A_PSRR
Power supply rejection ratio
–
60
–
dB
In VREF (2.4 V) mode with
VDDA bypass capacitance of 10 µF
SIDA107
A_TACQ
Sample acquisition time
–
1
–
µs
–
SIDA108
A_CONV8
Conversion time for 8-bit resolution at
conversion rate = Fhclk/(2^(N+2)).
Clock frequency = 48 MHz.
–
–
21.3
µs
Does not include acquisition time. Equivalent to
44.8 ksps including
acquisition time.
SIDA108A
A_CONV10
Conversion time for 10-bit resolution at
conversion rate = Fhclk/(2^(N+2)).
Clock frequency = 48 MHz.
–
–
85.3
µs
Does not include acquisition time. Equivalent to
11.6 ksps including
acquisition time.
SIDA109
A_SND
Signal-to-noise and Distortion ratio
(SINAD)
–
59
–
dB
With 10-Hz input sine
wave, internal reference,
VREF (2.4 V) mode
SIDA110
A_BW
Input bandwidth without aliasing
–
–
22.4
SIDA111
A_INL
Integral Non Linearity. 1 ksps
–
–
2
SIDA112
A_DNL
Differential Non Linearity. 1 ksps
–
–
1
Document Number: 002-26354 Rev. *C
KHz 8-bit resolution
LSB VREF = 2.4 V or greater
LSB –
Page 27 of 43
PSoC 4: PSoC 4500S Datasheet
Digital Peripherals
Timer Counter Pulse-Width Modulator (TCPWM)
Table 15. TCPWM Specifications
Spec ID#
SID.TCPWM.1
Parameter
ITCPWM1
Description
Block current consumption at 3 MHz
Min
–
Typ
–
Max
45
Unit
μA
Details/Conditions
All modes (TCPWM)
SID.TCPWM.2
ITCPWM2
Block current consumption at 12 MHz
–
–
155
μA
All modes (TCPWM)
SID.TCPWM.2A ITCPWM3
Block current consumption at 48 MHz
–
–
650
μA
All modes (TCPWM)
–
–
Fc
MHz
Fc max = CLK_SYS
Maximum = 48 MHz
SID.TCPWM.3
TCPWMFREQ
Operating frequency
SID.TCPWM.4
TPWMENEXT
Input trigger pulse width
2/Fc
–
–
ns
For all trigger events[7]
SID.TCPWM.5
TPWMEXT
Output trigger pulse widths
2/Fc
–
–
ns
Minimum possible width
of Overflow, Underflow,
and CC (Counter equals
Compare value) outputs
SID.TCPWM.5A TCRES
Resolution of counter
1/Fc
–
–
ns
Minimum time between
successive counts
SID.TCPWM.5B PWMRES
PWM resolution
1/Fc
–
–
ns
Minimum pulse width of
PWM Output
SID.TCPWM.5C QRES
Quadrature inputs resolution
1/Fc
–
–
ns
Minimum pulse width
between Quadrature
phase inputs
Description
Min
Typ
Max
Unit
–
–
50
µA
I2C
Table 16. Fixed I2C DC Specifications[7]
Spec ID#
Parameter
Details/Conditions
SID149
II2C1
Block current consumption at 100 kHz
SID150
II2C2
Block current consumption at 400 kHz
–
–
135
µA
–
SID151
II2C3
Block current consumption at 1 Mbps
–
–
310
µA
–
SID152
II2C4
Block current enabled in Deep Sleep
mode
–
1
–
µA
–
–
Table 17. Fixed I2C AC Specifications[7]
Spec ID#
SID153
Parameter
Description
Bit rate
FI2C1
Min
Typ
Max
–
–
1
Unit
Details/Conditions
Msps –
SPI
Table 18. SPI DC Specifications[7]
Spec ID#
Parameter
Description
Min
Typ
Max
SID163
ISPI1
Block current consumption at 1 Mbps
–
–
360
SID164
ISPI2
Block current consumption at 4 Mbps
–
–
560
SID165
ISPI3
Block current consumption at 8 Mbps
–
–
600
Unit
Details/Conditions
–
µA
–
–
Note
7. Guaranteed by characterization.
Document Number: 002-26354 Rev. *C
Page 28 of 43
PSoC 4: PSoC 4500S Datasheet
Table 19. SPI AC Specifications[8]
Spec ID#
SID166
Parameter
FSPI
Description
Min
Typ
Max
Unit
SPI Operating frequency (Master; 6X
Oversampling)
–
–
8
MHz
Details/Conditions
–
Fixed SPI Master Mode AC Specifications
SID167
TDMO
MOSI Valid after SClock driving edge
–
–
15
SID168
TDSI
MISO Valid before SClock capturing
edge
20
–
–
SID169
THMO
Previous MOSI data hold time
0
–
–
–
ns
Full clock, late MISO
sampling
Referred to Slave capturing
edge
Fixed SPI Slave Mode AC Specifications
–
SID170
TDMI
MOSI Valid before Sclock Capturing
edge
40
–
–
SID171
TDSO
MISO Valid after Sclock driving edge
–
–
42 +
3*Tcpu
SID171A
TDSO_EXT
MISO Valid after Sclock driving edge
in Ext. Clk mode
–
–
48
SID172
THSO
Previous MISO data hold time
0
–
–
SID172A
TSSELSSCK
SSEL Valid to first SCK Valid edge
100
–
–
ns
Min
Typ
Max
Unit
ns
TCPU = 1/FCPU
–
–
–
UART
Table 20. UART DC Specifications[8]
Spec ID#
Parameter
Description
SID160
IUART1
Block current consumption at
100 Kbps
–
–
55
µA
SID161
IUART2
Block current consumption at
1000 Kbps
–
–
312
µA
Min
Typ
Max
–
–
1
Details/Conditions
–
–
Table 21. UART AC Specifications[8]
Spec ID#
SID162
Parameter
FUART
Description
Bit rate
Unit
Details/Conditions
Mbps –
LCD Direct Drive
Table 22. LCD Direct Drive DC Specifications[8]
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
SID155
CLCDCAP
LCD capacitance per segment/common driver
–
500
5000
pF
–
SID156
LCDOFFSET
Long-term segment offset
–
20
–
mV
–
SID157
ILCDOP1
LCD system operating current Vbias = 5 V
2
–
SID158
ILCDOP2
LCD system operating current Vbias = 3.3 V
2
–
–
–
mA
32 4 segments at
50 Hz 25 °C
32 4 segments at
50 Hz 25 °C
Table 23. LCD Direct Drive AC Specifications[8]
Spec ID#
SID159
Parameter
FLCD
Description
LCD frame rate
Min
Typ
Max
Unit
10
50
150
Hz
Details/Conditions
–
Note
8. Guaranteed by characterization.
Document Number: 002-26354 Rev. *C
Page 29 of 43
PSoC 4: PSoC 4500S Datasheet
Memory
Table 24. Flash DC Specifications
Spec ID#
SID173
Parameter
VPE
Description
Min
Typ
Max
Unit
1.71
–
5.5
V
Description
Min
Typ
Max
Unit
Details/Conditions
Erase and program voltage
Details/Conditions
–
Table 25. Flash AC Specifications
Spec ID#
Parameter
SID174
TROWWRITE[9]
Row (block) write time (erase and
program)
–
–
20
ms
Row (block) = 256 bytes
SID175
TROWERASE[9]
Row erase time
–
–
16
ms
–
SID176
Row program time after erase
–
–
4
ms
–
Bulk erase time (256 KB)
–
–
35
ms
–
SID180
TROWPROGRAM[9]
TBULKERASE[9]
TDEVPROG[9]
SID181[10]
FEND
Flash endurance
SID182[10]
FRET
SID182A[10]
–
SID182B
FRETQ
SID256
SID257
SID178
[10]
Total device program time
–
–
7
100 K
–
–
Seconds –
Flash retention. TA 55 °C, 100 K
P/E cycles
20
–
–
Flash retention. TA 85 °C, 10 K
P/E cycles
10
–
–
Flash retention. TA 105 °C, 10K
P/E cycles, three years at TA ≥
85 °C
10
–
–
TWS48
Number of Wait states at 48 MHz
2
–
–
CPU execution from
Flash
TWS24
Number of Wait states at 24 MHz
1
–
–
CPU execution from
Flash
Min
Typ
Max
Unit
1
–
67
V/ms
V
Cycles
–
–
Years
years
–
Guaranteed by characterization.
System Resources
Power-on Reset (POR)
Table 26. Power On Reset (PRES)
Spec ID#
Parameter
Description
SID.CLK#6 SR_POWER_UP Power supply slew rate
SID185[10]
VRISEIPOR
Rising trip voltage
0.80
–
1.5
[10]
VFALLIPOR
Falling trip voltage
0.70
–
1.4
Min
Typ
Max
Unit
V
SID186
Details/Conditions
At power-up and
power-down.
–
–
Table 27. Brown-out Detect (BOD) for VCCD
Spec ID#
[10]
Parameter
Description
SID190
VFALLPPOR
BOD trip voltage in active and
sleep modes
1.48
–
1.62
SID192[10]
VFALLDPSLP
BOD trip voltage in Deep Sleep
1.11
–
1.5
Details/Conditions
–
–
Notes
9. It can take as much as 20 milliseconds to write to Flash. During this time the device should not be Reset, or Flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
10. Guaranteed by characterization.
Document Number: 002-26354 Rev. *C
Page 30 of 43
PSoC 4: PSoC 4500S Datasheet
SWD Interface
Table 28. SWD Interface Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details/Conditions
SWDCLK ≤ 1/3 CPU
clock frequency
SID213
F_SWDCLK1
3.3 V VDD 5.5 V
–
–
14
SID214
F_SWDCLK2
1.71 V VDD 3.3 V
–
–
7
SWDCLK ≤ 1/3 CPU
clock frequency
SID215[11]
T_SWDI_SETUP T = 1/f SWDCLK
0.25*T
–
–
–
T_SWDI_HOLD
0.25*T
–
–
T_SWDO_VALID T = 1/f SWDCLK
–
–
0.5*T
T_SWDO_HOLD T = 1/f SWDCLK
1
–
–
Min
Typ
Max
Unit
MHz
[11]
SID216
[11]
SID217
SID217A
[11]
T = 1/f SWDCLK
–
ns
–
–
Internal Main Oscillator
Table 29. IMO DC Specifications
(Guaranteed by Design)
Spec ID#
Parameter
Description
Details/Conditions
SID218
IIMO1
IMO operating current at 48 MHz
–
–
250
µA
–
SID219
IIMO2
IMO operating current at 24 MHz
–
–
180
µA
–
Description
Min
Typ
Max
Unit
Table 30. IMO AC Specifications
Spec ID#
Parameter
Details/Conditions
SID223
FIMOTOL1
Frequency variation at 24, 32, and
48 MHz (trimmed)
–
–
±2
%
–
SID226
TSTARTIMO
IMO startup time
–
–
7
µs
–
SID228
TJITRMSIMO2
RMS jitter at 24 MHz
–
145
–
ps
–
Min
Typ
Max
Unit
–
0.3
1.05
µA
Min
Typ
Max
Unit
Internal Low-Speed Oscillator
Table 31. ILO DC Specifications
(Guaranteed by Design)
Spec ID#
SID231
Parameter
IILO1
Description
ILO operating current
Details/Conditions
–
Table 32. ILO AC Specifications
Spec ID#
SID234[11]
Parameter
TSTARTILO1
SID236[11] TILODUTY
SID237
FILOTRIM1
Description
Details/Conditions
ILO startup time
–
–
2
ms
–
ILO duty cycle
40
50
60
%
–
ILO frequency range
20
40
80
kHz
–
Note
11. Guaranteed by design.
Document Number: 002-26354 Rev. *C
Page 31 of 43
PSoC 4: PSoC 4500S Datasheet
Watch Crystal Oscillator (WCO)
Table 33. WCO Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
–
32.768
–
kHz
–
50
250
ppm
–
50
–
kΩ
–
1
µW
–
–
500
ms
–
SID398
FWCO
Crystal frequency
SID399
FTOL
Frequency tolerance
SID400
ESR
Equivalent series resistance
SID401
PD
Drive Level
–
SID402
TSTART
Startup time
–
Details / Conditions
–
With 20-ppm crystal
–
SID403
CL
Crystal Load Capacitance
6
–
12.5
pF
–
SID404
C0
Crystal Shunt Capacitance
–
1.35
–
pF
–
SID405
IWCO1
Operating Current (high power mode)
–
–
8
µA
–
External Clock
Table 34. External Clock Specifications
Min
Typ
Max
Unit
SID305[12] ExtClkFreq
Spec ID#
Parameter
Block current
Description
0
–
48
MHz
–
Details/Conditions
SID306[12] ExtClkDuty
Duty cycle; measured at VDD/2
45
–
55
%
–
Min
Typ
Max
Unit
External Crystal Oscillator and PLL
Table 35. External Crystal Oscillator (ECO) Specifications
Spec ID#
Parameter
Description
Details/Conditions
SID316[12] IECO1
Block current
–
–
1.5
mA
–
SID317[12] FECO
Crystal frequency range
4
–
33
MHz
–
Min
Typ
Table 36. PLL Specifications
Spec ID#
Parameter
Description
Max
Unit
Details / Conditions
SID410
IDD_PLL_48
In = 3 MHz, Out = 48 MHz
–
530
610
µA
–
SID411
IDD_PLL_24
In = 3 MHz, Out = 24 MHz
–
300
405
µA
–
SID412
Fpllin
PLL input frequency
1
–
48
MHz
–
SID413
Fpllint
PLL intermediate frequency;
prescaler out
1
–
3
MHz
SID414
Fpllvco
VCO output frequency before
post-divide
22.5
–
104
MHz
SID415
Divvco
VCO Output post-divider range; PLL
output frequency is Fpplvco/Divvco
1
–
8
SID416
Plllocktime
Lock time at startup
–
–
250
µs
–
SID417
Jperiod_1
Period jitter for VCO ≥ 67 MHz
–
–
150
ps
Guaranteed by design
SID416A
Jperiod_2
Period jitter for VCO ≤ 67 MHz
–
–
200
ps
Guaranteed by design
–
–
–
Note
12. Guaranteed by characterization.
Document Number: 002-26354 Rev. *C
Page 32 of 43
PSoC 4: PSoC 4500S Datasheet
System Clock
Table 37. System Clock Spec
Spec ID#
[13]
SID262
Parameter
TCLKSWITCH
Description
System clock source switching time
Min
Typ
Max
Unit
3
–
4
Min
Typ
Max
Unit
–
–
1.6
ns
Details/Conditions
Periods –
Smart I/O
Table 38. Smart I/O Pass-through Time (Delay in Bypass Mode)
Spec ID#
SID252
Parameter
Description
PRG_BYPASS Max delay added by Smart I/O in
bypass mode
Details / Conditions
–
Note
13. Guaranteed by characterization.
Document Number: 002-26354 Rev. *C
Page 33 of 43
PSoC 4: PSoC 4500S Datasheet
Ordering Information
The marketing part numbers for the PSoC 4500S devices are listed in the following table.
45x6
45x7
45x8
Divide and Square Root Accelerator
Op-amp (CTBm)
12-bit SAR ADC
SAR ADC Sample Rate
CapSense
Direct LCD Drive
LP Comparators
TCPWM Blocks
SCB Blocks
ECO
Smart IOs
GPIO
48-TQFP
64-TQFP (0.5mm pitch)
64-TQFP (0.8mm pitch)
Temp Range (oC)
CY8C4546AZI-S473
SRAM (KB)
MPN
Flash (KB)
Category
Package
Max CPU Speed (MHz)
Feature
48
64
16
X
2
2
1 Msps
X
2
8
4
X
16
38
X
-40 to 85
CY8C4546AZI-S475
48
64
16
X
3
2
1 Msps
X
2
8
5
X
16
53
X
-40 to 85
CY8C4546AXI-S475
48
64
16
X
3
2
1 Msps
X
2
8
5
X
16
53
X
-40 to 85
CY8C4547AZI-S453
48 128 32
X
2
1
1 Msps
X
2
8
4
X
16
38
X
-40 to 85
CY8C4547AZQ-S453
48 128 32
X
2
1
1 Msps
X
2
8
4
X
16
38
X
-40 to 105
CY8C4547AZI-S455
48 128 32
X
2
1
1 Msps
X
2
8
5
X
16
53
X
-40 to 85
CY8C4547AZQ-S455
48 128 32
X
2
1
1 Msps
X
2
8
5
X
16
53
X
-40 to 105
CY8C4547AZI-S463
48 128 32
X
2
1
1 Msps
X
X
2
8
4
X
16
38
X
-40 to 85
CY8C4547AZI-S465
48 128 32
X
3
1
1 Msps
X
X
2
8
5
X
16
53
X
-40 to 85
CY8C4547AZI-S473
48 128 32
X
2
2
1 Msps
X
2
8
4
X
16
38
X
-40 to 85
CY8C4547AZQ-S473
48 128 32
X
2
2
1 Msps
X
2
8
4
X
16
38
X
-40 to 105
CY8C4547AZI-S475
48 128 32
X
3
2
1 Msps
X
2
8
5
X
16
53
X
-40 to 85
CY8C4547AZQ-S475
48 128 32
X
3
2
1 Msps
X
2
8
5
X
16
53
X
-40 to 105
CY8C4547AXI-S475
48 128 32
X
3
2
1 Msps
X
2
8
5
X
16
53
X
-40 to 85
CY8C4547AXQ-S475
48 128 32
X
3
2
1 Msps
X
2
8
5
X
16
53
X
-40 to 105
CY8C4548AZI-S475
48 256 32
X
3
2
1 Msps
X
2
8
5
X
16
53
X
-40 to 85
CY8C4548AXI-S475
48 256 32
X
3
2
1 Msps
X
2
8
5
X
16
53
X
-40 to 85
CY8C4548AZI-S483
48 256 32
X
2
2
1 Msps
X
X
2
8
4
X
16
38
X
-40 to 85
CY8C4548AZQ-S483
48 256 32
X
2
2
1 Msps
X
X
2
8
4
X
16
38
X
-40 to 105
CY8C4548AZI-S485
48 256 32
X
3
2
1 Msps
X
X
2
8
5
X
16
53
X
-40 to 85
CY8C4548AZQ-S485
48 256 32
X
3
2
1 Msps
X
X
2
8
5
X
16
53
X
-40 to 105
CY8C4548AXI-S485
48 256 32
X
3
2
1 Msps
X
X
2
8
5
X
16
53
X
-40 to 85
CY8C4548AXQ-S485
48 256 32
X
3
2
1 Msps
X
X
2
8
5
X
16
53
X
-40 to 105
Document Number: 002-26354 Rev. *C
Page 34 of 43
PSoC 4: PSoC 4500S Datasheet
The nomenclature used in the preceding table is based on the following part numbering convention:
Field
Description
CY8C
Cypress Prefix
Values
Meaning
4
Architecture
4
PSoC 4
A
Family
1
4500S Family
B
CPU Speed
2
24 MHz
4
48 MHz
4
16 KB
5
32 KB
6
64 KB
7
128 KB
AX
TQFP (0.8-mm pitch)
C
Flash Capacity
DE
Package Code
AZ
TQFP (0.5-mm pitch)
LQ
QFN
PV
SSOP
FN
CSP
Industrial
Extended Industrial
F
Temperature Range
I
Q
S
Series Designator
S
PSoC 4 S-Series
M
PSoC 4 M-Series
XYZ
Attributes Code
L
PSoC 4 L-Series
BL
PSoC 4 BLE-Series
000-999
Code of feature set in the specific family
The following is an example of a part number:
CY8C 4 A B C DE F – S XYZ
Example
Cypress Prefix
Architecture
4 : PSoC 4
1: 4500S Family
Family within Architecture
CPU Speed
4 : 48 MHz
5 : 32 KB
Flash Capacity
AZ/AX: TQFP
Package Code
I : Industrial
Temperature Range
Series Designator
Attributes Code
Document Number: 002-26354 Rev. *C
Page 35 of 43
PSoC 4: PSoC 4500S Datasheet
Packaging
The PSoC 4500S will be offered in 48 TQFP, 64 TQFP Normal pitch, and 64 TQFP Fine Pitch packages.
Package dimensions and Cypress drawing numbers are in the following table.
Table 39. Package List
Spec ID#
Package
BID20
64-pin TQFP
14 × 14 × 1.4-mm height with 0.8-mm pitch
Description
51-85046
Package Dwg
BID27
64-pin TQFP
10 × 10 × 1.6-mm height with 0.5-mm pitch
51-85051
BID70
48-pin TQFP
7 × 7 × 1.4-mm height with 0.5-mm pitch
51-85135
Table 40. Package Thermal Characteristics
Parameter
Description
Package
Min
Typ
Max
Unit
TA
Operating ambient temperature
–40
25
105
°C
TJ
Operating junction temperature
–40
–
125
°C
TJA
Package θJA
64-pin TQFP (0.5-mm pitch)
–
46
–
°C/Watt
TJC
Package θJC
64-pin TQFP (0.5-mm pitch)
–
10
–
°C/Watt
TJA
Package θJA
64-pin TQFP (0.8-mm pitch)
–
36.8
–
°C/Watt
TJC
Package θJC
64-pin TQFP (0.8-mm pitch)
–
9.4
–
°C/Watt
TJA
Package θJA
48-pin TQFP (0.5-mm pitch)
–
39.4
–
°C/Watt
TJC
Package θJC
48-pin TQFP (0.5-mm pitch)
–
9.3
–
°C/Watt
Table 41. Solder Reflow Peak Temperature
Package
Maximum Peak
Temperature
Maximum Time at Peak Temperature
All
260 °C
30 seconds
Table 42. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-020
Package
MSL
All
MSL 3
Document Number: 002-26354 Rev. *C
Page 36 of 43
PSoC 4: PSoC 4500S Datasheet
Package Diagrams
Figure 8. 64-pin TQFP Package (0.8-mm Pitch) Outline
ș1
ș
ș2
SYMBOL
DIMENSIONS
MIN. NOM. MAX.
A
1.60
A1
0.05
A2
1.35 1.40 1.45
D
15.75 16.00 16.25
D1
13.95 14.00 14.05
E
15.75 16.00 16.25
E1
13.95 14.00 14.05
R1
0.08
0.20
R2
0.08
0.20
ș
0°
7°
ș1
0°
ș2
11°
13°
12°
b
0.30 0.35 0.40
L
0.45 0.60 0.75
L1
L2
L3
e
1. JEDEC STD REF MS-026
2. BODY LENGTH DIMENSION DOES NOT
INCLUDE MOLD PROTRUSION/END FLASH
MOLD PROTRUSION/END FLASH SHALL
NOT EXCEED 0.0098 in (0.25 mm) PER SIDE
BODY LENGTH DIMENSIONS ARE MAX PLASTIC
BODY SIZE INCLUDING MOLD MISMATCH
3. DIMENSIONS IN MILLIMETERS
0.20
c
Document Number: 002-26354 Rev. *C
0.15
NOTE:
1.00 REF
0.25 BSC
0.20
0.80 TYP
51-85046 *H
Page 37 of 43
PSoC 4: PSoC 4500S Datasheet
Figure 9. 64-pin TQFP Package (0.5-mm Pitch) Outline
51-85051 *D
Figure 10. 48-Pin 7 × 7 × 1.4 mm TQFP Package Outline
51-85135 *C
Document Number: 002-26354 Rev. *C
Page 38 of 43
PSoC 4: PSoC 4500S Datasheet
Acronyms
Table 43. Acronyms Used in this Document
Acronym
Description
abus
analog local bus
ADC
analog-to-digital converter
AG
analog global
AHB
AMBA (advanced microcontroller bus
architecture) high-performance bus, an Arm data
transfer bus
Table 43. Acronyms Used in this Document (continued)
Acronym
Description
ESD
electrostatic discharge
ETM
embedded trace macrocell
FIR
finite impulse response, see also IIR
FPB
flash patch and breakpoint
FS
full-speed
GPIO
general-purpose input/output, applies to a PSoC
pin
ALU
arithmetic logic unit
AMUXBUS
analog multiplexer bus
HVI
high-voltage interrupt, see also LVI, LVD
API
application programming interface
IC
integrated circuit
APSR
application program status register
IDAC
current DAC, see also DAC, VDAC
Arm®
advanced RISC machine, a CPU architecture
IDE
integrated development environment
ATM
automatic thump mode
I
BW
bandwidth
CAN
Controller Area Network, a communications
protocol
2C,
or IIC
IIR
Inter-Integrated Circuit, a communications
protocol
infinite impulse response, see also FIR
ILO
internal low-speed oscillator, see also IMO
internal main oscillator, see also ILO
CMRR
common-mode rejection ratio
IMO
CPU
central processing unit
INL
integral nonlinearity, see also DNL
CRC
cyclic redundancy check, an error-checking
protocol
I/O
input/output, see also GPIO, DIO, SIO, USBIO
IPOR
initial power-on reset
DAC
digital-to-analog converter, see also IDAC,
VDAC
IPSR
interrupt program status register
DFB
digital filter block
IRQ
interrupt request
DIO
digital input/output, GPIO with only digital
capabilities, no analog. See GPIO.
ITM
instrumentation trace macrocell
DMIPS
Dhrystone million instructions per second
DMA
direct memory access, see also TD
DNL
differential nonlinearity, see also INL
DNU
do not use
DR
port write data registers
DSI
digital system interconnect
DWT
data watchpoint and trace
ECC
error correcting code
ECO
external crystal oscillator
EEPROM
electrically erasable programmable read-only
memory
LCD
liquid crystal display
LIN
Local Interconnect Network, a communications
protocol.
LR
link register
LUT
lookup table
LVD
low-voltage detect, see also LVI
LVI
low-voltage interrupt, see also HVI
LVTTL
low-voltage transistor-transistor logic
MAC
multiply-accumulate
MCU
microcontroller unit
MISO
master-in slave-out
NC
no connect
nonmaskable interrupt
EMI
electromagnetic interference
NMI
EMIF
external memory interface
NRZ
non-return-to-zero
EOC
end of conversion
NVIC
nested vectored interrupt controller
EOF
end of frame
NVL
nonvolatile latch, see also WOL
execution program status register
opamp
operational amplifier
EPSR
Document Number: 002-26354 Rev. *C
Page 39 of 43
PSoC 4: PSoC 4500S Datasheet
Table 43. Acronyms Used in this Document (continued)
Acronym
Description
Table 43. Acronyms Used in this Document (continued)
Acronym
Description
PAL
programmable array logic, see also PLD
SWD
serial wire debug, a test protocol
PC
program counter
SWV
single-wire viewer
PCB
printed circuit board
TD
transaction descriptor, see also DMA
PGA
programmable gain amplifier
THD
total harmonic distortion
PHUB
peripheral hub
TIA
transimpedance amplifier
PHY
physical layer
TRM
technical reference manual
PICU
port interrupt control unit
TTL
transistor-transistor logic
PLA
programmable logic array
TX
transmit
PLD
programmable logic device, see also PAL
UART
PLL
phase-locked loop
Universal Asynchronous Transmitter Receiver, a
communications protocol
PMDD
package material declaration data sheet
POR
power-on reset
PRES
precise power-on reset
PRS
pseudo random sequence
PS
port read data register
PSoC®
Programmable System-on-Chip™
PSRR
power supply rejection ratio
PWM
pulse-width modulator
RAM
random-access memory
RISC
reduced-instruction-set computing
RMS
root-mean-square
RTC
real-time clock
RTL
register transfer language
RTR
remote transmission request
RX
receive
SAR
successive approximation register
SC/CT
switched capacitor/continuous time
SCL
I2C serial clock
SDA
I2C serial data
S/H
sample and hold
SINAD
signal to noise and distortion ratio
SIO
special input/output, GPIO with advanced
features. See GPIO.
SOC
start of conversion
SOF
start of frame
SPI
Serial Peripheral Interface, a communications
protocol
SR
slew rate
SRAM
static random access memory
SRES
software reset
Document Number: 002-26354 Rev. *C
UDB
universal digital block
USB
Universal Serial Bus
USBIO
USB input/output, PSoC pins used to connect to
a USB port
VDAC
voltage DAC, see also DAC, IDAC
WDT
watchdog timer
WOL
write once latch, see also NVL
WRES
watchdog timer reset
XRES
external reset I/O pin
XTAL
crystal
Page 40 of 43
PSoC 4: PSoC 4500S Datasheet
Document Conventions
Units of Measure
Table 44. Units of Measure
Symbol
Unit of Measure
°C
degrees Celsius
dB
decibel
fF
femto farad
Hz
hertz
KB
1024 bytes
kbps
kilobits per second
Khr
kilohour
kHz
kilohertz
k
kilo ohm
ksps
kilosamples per second
LSB
least significant bit
Mbps
megabits per second
MHz
megahertz
M
mega-ohm
Msps
megasamples per second
µA
microampere
µF
microfarad
µH
microhenry
µs
microsecond
µV
microvolt
µW
microwatt
mA
milliampere
ms
millisecond
mV
millivolt
nA
nanoampere
ns
nanosecond
nV
nanovolt
ohm
pF
picofarad
ppm
parts per million
ps
picosecond
s
second
sps
samples per second
sqrtHz
square root of hertz
V
volt
Document Number: 002-26354 Rev. *C
Page 41 of 43
PSoC 4: PSoC 4500S Datasheet
Revision History
Description Title: PSoC 4: PSoC 4500S Datasheet Programmable System-on-Chip (PSoC)
Document Number: 002-26354
Submission
Revision
ECN
Description of Change
Date
*B
6828229
03/18/2020 Release to web.
Added ModusToolbox™ in Features.
*C
7047110
12/23/2020 Updated Document Ecosystem.
Updated Conditions for SR_POWER_UP in Table 26.
Document Number: 002-26354 Rev. *C
Page 42 of 43
PSoC 4: PSoC 4500S Datasheet
Sales, Solutions, and Legal Information
Worldwide Sales and Design Support
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office
closest to you, visit us at Cypress Locations.
PSoC® Solutions
Products
Arm® Cortex® Microcontrollers
Automotive
cypress.com/arm
cypress.com/automotive
Clocks & Buffers
Interface
cypress.com/clocks
cypress.com/interface
Internet of Things
Memory
cypress.com/iot
cypress.com/memory
Microcontrollers
cypress.com/mcu
PSoC
cypress.com/psoc
Power Management ICs
Cypress Developer Community
Community | Code Examples | Projects | Video | Blogs |
Training | Components
Technical Support
cypress.com/support
cypress.com/pmic
Touch Sensing
cypress.com/touch
USB Controllers
Wireless Connectivity
PSoC 1 | PSoC 3 | PSoC 4 | PSoC 5LP | PSoC 6 MCU
cypress.com/usb
cypress.com/wireless
© Cypress Semiconductor Corporation, 2019-2020. This document is the property of Cypress Semiconductor Corporation and its subsidiaries ("Cypress"). This document, including any software or
firmware included or referenced in this document ("Software"), is owned by Cypress under the intellectual property laws and treaties of the United States and other countries worldwide. Cypress
reserves all rights under such laws and treaties and does not, except as specifically stated in this paragraph, grant any license under its patents, copyrights, trademarks, or other intellectual property
rights. If the Software is not accompanied by a license agreement and you do not otherwise have a written agreement with Cypress governing the use of the Software, then Cypress hereby grants
you a personal, non-exclusive, nontransferable license (without the right to sublicense) (1) under its copyright rights in the Software (a) for Software provided in source code form, to modify and reproduce
the Software solely for use with Cypress hardware products, only internally within your organization, and (b) to distribute the Software in binary code form externally to end users (either directly or
indirectly through resellers and distributors), solely for use on Cypress hardware product units, and (2) under those claims of Cypress's patents that are infringed by the Software (as provided by
Cypress, unmodified) to make, use, distribute, and import the Software solely for use with Cypress hardware products. Any other use, reproduction, modification, translation, or compilation of the
Software is prohibited.
TO THE EXTENT PERMITTED BY APPLICABLE LAW, CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS DOCUMENT OR ANY SOFTWARE
OR ACCOMPANYING HARDWARE, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. No computing
device can be absolutely secure. Therefore, despite security measures implemented in Cypress hardware or software products, Cypress shall have no liability arising out of any security breach, such
as unauthorized access to or use of a Cypress product. CYPRESS DOES NOT REPRESENT, WARRANT, OR GUARANTEE THAT CYPRESS PRODUCTS, OR SYSTEMS CREATED USING
CYPRESS PRODUCTS, WILL BE FREE FROM CORRUPTION, ATTACK, VIRUSES, INTERFERENCE, HACKING, DATA LOSS OR THEFT, OR OTHER SECURITY INTRUSION (collectively, "Security
Breach"). Cypress disclaims any liability relating to any Security Breach, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any Security Breach. In
addition, the products described in these materials may contain design defects or errors known as errata which may cause the product to deviate from published specifications. To the extent permitted
by applicable law, Cypress reserves the right to make changes to this document without further notice. Cypress does not assume any liability arising out of the application or use of any product or
circuit described in this document. Any information provided in this document, including any sample design information or programming code, is provided only for reference purposes. It is the
responsibility of the user of this document to properly design, program, and test the functionality and safety of any application made of this information and any resulting product. "High-Risk Device"
means any device or system whose failure could cause personal injury, death, or property damage. Examples of High-Risk Devices are weapons, nuclear installations, surgical implants, and other
medical devices. "Critical Component" means any component of a High-Risk Device whose failure to perform can be reasonably expected to cause, directly or indirectly, the failure of the High-Risk
Device, or to affect its safety or effectiveness. Cypress is not liable, in whole or in part, and you shall and hereby do release Cypress from any claim, damage, or other liability arising from any use of
a Cypress product as a Critical Component in a High-Risk Device. You shall indemnify and hold Cypress, its directors, officers, employees, agents, affiliates, distributors, and assigns harmless from
and against all claims, costs, damages, and expenses, arising out of any claim, including claims for product liability, personal injury or death, or property damage arising from any use of a Cypress
product as a Critical Component in a High-Risk Device. Cypress products are not intended or authorized for use as a Critical Component in any High-Risk Device except to the limited extent that (i)
Cypress's published data sheet for the product explicitly states Cypress has qualified the product for use in a specific High-Risk Device, or (ii) Cypress has given you advance written authorization to
use the product as a Critical Component in the specific High-Risk Device and you have signed a separate indemnification agreement.
Cypress, the Cypress logo, Spansion, the Spansion logo, and combinations thereof, WICED, PSoC, CapSense, EZ-USB, F-RAM, and Traveo are trademarks or registered trademarks of Cypress in
the United States and other countries. For a more complete list of Cypress trademarks, visit cypress.com. Other names and brands may be claimed as property of their respective owners.
Document Number: 002-26354 Rev. *C
Revised December 23, 2020
Page 43 of 43
工商网监
湘ICP备2023018690号
