Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
PSoC® 5LP: CY8C54LP Family
Datasheet
®
Programmable System-on-Chip (PSoC )
General Description
PSoC® 5LP is a true programmable embedded system-on-chip, integrating configurable analog and digital peripherals, memory, and
a microcontroller on a single chip. The PSoC 5LP architecture boosts performance through:
32-bit Arm® Cortex®-M3 core plus DMA controller at up to 80 MHz
Ultra low power with industry's widest voltage range
Programmable digital and analog peripherals enable custom functions
Flexible routing of any analog or digital peripheral function to any pin
PSoC devices employ a highly configurable system-on-chip architecture for embedded control design. They integrate configurable
analog and digital circuits, controlled by an on-chip microcontroller. A single PSoC device can integrate as many as 100 digital and
analog peripheral functions, reducing design time, board space, power consumption, and system cost while improving system quality.
Features
Operating characteristics
Analog peripherals
Voltage range: 1.71 to 5.5 V, up to 6 power domains
[1]
Temperature range (ambient) –40 to 85 °C
DC to 80-MHz operation
Power modes
• Active mode 3.1 mA at 6 MHz, and 15.4 mA at 48 MHz
• 2-µA sleep mode
• 300-nA hibernate mode with RAM retention
Boost regulator from 0.5-V input up to 5-V output
Configurable 8- to 12-bit delta-sigma ADC
12-bit SAR ADC
Two 8-bit DACs
Four comparators
Two opamps
Two programmable analog blocks, to create:
• Programmable gain amplifier (PGA)
• Transimpedance amplifier (TIA)
• Mixer
• Sample and hold circuit
®
CapSense support, up to 62 sensors
1.024 V ±1% internal voltage reference
Performance
32-bit Arm Cortex-M3 CPU, 32 interrupt inputs
24-channel direct memory access (DMA) controller
Memories
Versatile I/O system
46 to 72 I/O pins – up to 62 general-purpose I/Os (GPIOs)
Up to eight performance I/O (SIO) pins
• 25 mA current sink
• Programmable input threshold and output high voltages
• Can act as a general-purpose comparator
• Hot swap capability and overvoltage tolerance
Two USBIO pins that can be used as GPIOs
Route any digital or analog peripheral to any GPIO
LCD direct drive from any GPIO, up to 46 × 16 segments
CapSense support from any GPIO
1.2-V to 5.5-V interface voltages, up to four power domains
Up to 256 KB program flash, with cache and security features
Up to 32 KB additional flash for error correcting code (ECC)
Up to 64 KB RAM
2 KB EEPROM
Digital peripherals
Four 16-bit timer, counter, and PWM (TCPWM) blocks
I2C, 1 Mbps bus speed
USB 2.0 certified Full-Speed (FS) 12 Mbps peripheral interface (TID#10840032) using internal oscillator[2]
20 to 24 universal digital blocks (UDB), programmable to
create any number of functions:
• 8-, 16-, 24-, and 32-bit timers, counters, and PWMs
• I2C, UART, SPI, I2S, LIN 2.0 interfaces
• Cyclic redundancy check (CRC)
• Pseudo random sequence (PRS) generators
• Quadrature decoders
• Gate-level logic functions
Programmable clocking
Programming, debug, and trace
JTAG (4-wire), serial wire debug (SWD) (2-wire), single wire
viewer (SWV), and Traceport (5-wire) interfaces
Arm debug and trace modules embedded in the CPU core
2
Bootloader programming through I C, SPI, UART, USB, and
other interfaces
Package options: 68-pin QFN,100-pin TQFP, and 99-pin CSP
Development support with free PSoC Creator™ tool
3- to 74-MHz internal oscillator, 2% accuracy at 3 MHz
4- to 25-MHz external crystal oscillator
Internal PLL clock generation up to 80 MHz
Low-power internal oscillator at 1, 33, and 100 kHz
32.768-kHz external watch crystal oscillator
12 clock dividers routable to any peripheral or I/O
Schematic and firmware design support
Over 100 PSoC Components™ integrate multiple ICs and
system interfaces into one PSoC. Components are free
embedded ICs represented by icons. Drag and drop
component icons to design systems in PSoC Creator.
Includes free GCC compiler, supports Keil/Arm MDK
compiler
Supports device programming and debugging
Notes
1. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life.
2. This feature on select devices only. See Ordering Information on page 116 for details.
Cypress Semiconductor Corporation
Document Number: 001-84934 Rev. *M
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 27, 2019
PSoC® 5LP: CY8C54LP Family
Datasheet
More Information
Cypress provides a wealth of data at www.cypress.com to help you to select the right PSoC device for your design, and to help you
to quickly and effectively integrate the device into your design. For a comprehensive list of resources, see the knowledge base article
KBA86521, How to Design with PSoC 3, PSoC 4, and PSoC 5LP. Following is an abbreviated list for PSoC 5LP:
Overview: PSoC Portfolio, PSoC Roadmap
Development Kits:
Product Selectors: PSoC 1, PSoC 3, PSoC 4, PSoC 5LP
In addition, PSoC Creator includes a device selection tool.
Application notes: Cypress offers a large number of PSoC
application notes and code examples covering a broad range
of topics, from basic to advanced level. Recommended application notes for getting started with PSoC 5LP are:
AN77759: Getting Started With PSoC 5LP
AN77835: PSoC 3 to PSoC 5LP Migration Guide
AN61290: Hardware Design Considerations
AN57821: Mixed Signal Circuit Board Layout
AN58304: Pin Selection for Analog Designs
AN81623: Digital Design Best Practices
AN73854: Introduction To Bootloaders
CY8CKIT-059 is a low-cost platform for prototyping, with a
unique snap-away programmer and debugger on the USB
connector.
CY8CKIT-050 is designed for analog performance, for developing high-precision analog, low-power, and low-voltage applications.
CY8CKIT-001 provides a common development platform for
any one of the PSoC 1, PSoC 3, PSoC 4, or PSoC 5LP
families of devices.
The MiniProg3 device provides an interface for flash programming and debug.
Technical Reference Manuals (TRM)
Architecture TRM
Registers TRM
Programming Specification
PSoC Creator
PSoC Creator is a free Windows-based Integrated Design Environment (IDE). It enables concurrent hardware and firmware design
of PSoC 3, PSoC 4, and PSoC 5LP based systems. Create designs using classic, familiar schematic capture supported by over 100
pre-verified, production-ready PSoC Components; see the list of component datasheets. With PSoC Creator, you can:
1. Drag and drop component icons to build your hardware
3. Configure components using the configuration tools
system design in the main design workspace
4. Explore the library of 100+ components
2. Codesign your application firmware with the PSoC hardware,
5. Review component datasheets
using the PSoC Creator IDE C compiler
Figure 1. Multiple-Sensor Example Project in PSoC Creator
1
2
3
4
5
Document Number: 001-84934 Rev. *M
Page 2 of 126
PSoC® 5LP: CY8C54LP Family
Datasheet
Contents
1. Architectural Overview ................................................ 4
2. Pinouts .......................................................................... 6
3. Pin Descriptions ......................................................... 11
4. CPU .............................................................................. 12
4.1 Arm Cortex-M3 CPU ........................................... 12
4.2 Cache Controller ................................................. 15
4.3 DMA and PHUB .................................................. 15
4.4 Interrupt Controller .............................................. 17
5. Memory ........................................................................ 19
5.1 Static RAM .......................................................... 19
5.2 Flash Program Memory ....................................... 19
5.3 Flash Security ...................................................... 19
5.4 EEPROM ............................................................. 19
5.5 Nonvolatile Latches (NVLs) ................................. 20
5.6 External Memory Interface .................................. 21
5.7 Memory Map ....................................................... 22
6. System Integration ..................................................... 23
6.1 Clocking System .................................................. 23
6.2 Power System ..................................................... 27
6.3 Reset ................................................................... 31
6.4 I/O System and Routing ...................................... 33
7. Digital Subsystem ...................................................... 40
7.1 Example Peripherals ........................................... 40
7.2 Universal Digital Block ......................................... 42
7.3 UDB Array Description ........................................ 45
7.4 DSI Routing Interface Description ....................... 45
7.5 USB ..................................................................... 47
7.6 Timers, Counters, and PWMs ............................. 47
7.7 I2C ....................................................................... 48
8. Analog Subsystem ..................................................... 50
8.1 Analog Routing .................................................... 51
8.2 Delta-sigma ADC ................................................. 53
8.3 Successive Approximation ADC .......................... 54
8.4 Comparators ........................................................ 54
8.5 Opamps ............................................................... 56
8.6 Programmable SC/CT Blocks ............................. 56
8.7 LCD Direct Drive ................................................. 57
8.8 CapSense ............................................................ 58
8.9 Temp Sensor ....................................................... 58
8.10 DAC ................................................................... 58
8.11 Up/Down Mixer .................................................. 59
8.12 Sample and Hold ............................................... 60
Document Number: 001-84934 Rev. *M
9. Programming, Debug Interfaces, Resources ........... 60
9.1 JTAG Interface .................................................... 61
9.2 SWD Interface ..................................................... 62
9.3 Debug Features ................................................... 63
9.4 Trace Features .................................................... 63
9.5 SWV and TRACEPORT Interfaces ..................... 63
9.6 Programming Features ........................................ 63
9.7 Device Security ................................................... 63
9.8 CSP Package Bootloader .................................... 64
10. Development Support .............................................. 64
10.1 Documentation .................................................. 64
10.2 Online ................................................................ 64
10.3 Tools .................................................................. 64
11. Electrical Specifications .......................................... 65
11.1 Absolute Maximum Ratings ............................... 65
11.2 Device Level Specifications ............................... 66
11.3 Power Regulators .............................................. 69
11.4 Inputs and Outputs ............................................ 73
11.5 Analog Peripherals ............................................ 81
11.6 Digital Peripherals ........................................... 101
11.7 Memory ........................................................... 105
11.8 PSoC System Resources ................................ 109
11.9 Clocking ........................................................... 112
12. Ordering Information .............................................. 116
12.1 Part Numbering Conventions .......................... 117
13. Packaging ................................................................ 118
14. Acronyms ................................................................ 121
15. Document Conventions ......................................... 123
15.1 Units of Measure ............................................. 123
Document History Page ............................................... 124
Sales, Solutions, and Legal Information .................... 126
Worldwide Sales and Design Support ..................... 126
Products .................................................................. 126
PSoC® Solutions .................................................... 126
Cypress Developer Community ............................... 126
Technical Support ................................................... 126
Page 3 of 126
PSoC® 5LP: CY8C54LP Family
Datasheet
1. Architectural Overview
Introducing the CY8C54LP family of ultra low-power, flash Programmable System-on-Chip (PSoC®) devices, part of a scalable 8-bit
PSoC 3 and 32-bit PSoC 5LP platform. The CY8C54LP family provides configurable blocks of analog, digital, and interconnect circuitry
around a CPU subsystem. The combination of a CPU with a flexible analog subsystem, digital subsystem, routing, and I/O enables
a high level of integration in a wide variety of consumer, industrial, and medical applications.
Figure 1-1. Simplified Block Diagram
Analog Interconnect
8- Bit
Timer
UDB
UDB
UDB
UDB
I 2C Slave
Sequencer
Quadrature Decoder
16-Bit
PWM
SO
I2C
UDB
UDB
12- Bit SPI
UDB
UDB
UDB
UDB
UDB
UDB
8- Bit
Timer
Logic
UDB
UDB
UDB
UDB
UDB
UDB
UDB
UDB
8- Bit SPI
UDB
Master /
Slave
16 -Bit PRS
UDB
22 Ω
FS USB
2.0
4x
Timer
Counter
PWM
Logic
UDB
UART
UDB
USB
PHY
GPIOs
IMO
Digital System
Universal Digital Block Array(24 x UDB)
Usage Example for UDB
32.768 kHz
( Optional)
GPIOs
Xtal
Osc
Clock Tree
System Wide
Resources
I
4- 25 MHz
( Optional)
GPIOs
Digital Interconnect
12- Bit PWM
RTC
Timer
WDT
and
Wake
Memory System
CPU System
EEPROM
SRAM
Cortex M 3 CPU
Interrupt
Controller
EMIF
Flash
Cache
Controller
PHUB
DMA
Program &
Debug
Program
GPIOs
System Bus
GPIOs
Debug &
Trace
ILO
Boundary
Scan
Analog System
LCD Direct
Drive
POR and
LVD
1.71 to
5.5 V
Sleep
Power
GPIOs
Power Management
System
2 x SC/CT Blocks
(TIA, PGA, Mixer etc)
1.8V LDO
Temperature
Sensor
SMP
CapSense
2 x DAC
ADC
SAR
ADC
Del Sig
ADC
+
2x
Opamp
-
+
4x
CMP
-
3 per
Opamp
GPIOs
SIOs
Clocking System
0. 5 to 5.5 V
( Optional)
Figure 1-1 on page 4 illustrates the major components of the
CY8C54LP family. They are:
Arm Cortex-M3 CPU subsystem
Nonvolatile subsystem
Programming, debug, and test subsystem
Inputs and outputs
Clocking
Power
Digital subsystem
PSoC’s digital subsystem provides half of its unique
configurability. It connects a digital signal from any peripheral to
any pin through the digital system interconnect (DSI). It also
provides functional flexibility through an array of small, fast,
low-power UDBs. PSoC Creator provides a library of pre-built
and tested standard digital peripherals (UART, SPI, LIN, PRS,
CRC, timer, counter, PWM, AND, OR, and so on) that are
mapped to the UDB array. You can also easily create a digital
circuit using boolean primitives by means of graphical design
entry. Each UDB contains programmable array logic
(PAL)/programmable logic device (PLD) functionality, together
with a small state machine engine to support a wide variety of
peripherals.
Analog subsystem
Document Number: 001-84934 Rev. *M
Page 4 of 126
PSoC® 5LP: CY8C54LP Family
Datasheet
In addition to the flexibility of the UDB array, PSoC also provides
configurable digital blocks targeted at specific functions. For the
CY8C54LP family these blocks can include four 16-bit timer,
counter, and PWM blocks; I2C slave, master, and multimaster;
Full-Speed USB.
For more details on the peripherals see the “Example
Peripherals” section on page 40 of this datasheet. For
information on UDBs, DSI, and other digital blocks, see the
“Digital Subsystem” section on page 40 of this datasheet.
PSoC’s analog subsystem is the second half of its unique
configurability. All analog performance is based on a highly
accurate absolute voltage reference with less than 1% error over
temperature and voltage. The configurable analog subsystem
includes:
Analog muxes
Comparators
Analog mixers
Voltage references
Analog-to-Digital Converters (ADC)
Digital-to-Analog Converters (DACs)
All GPIO pins can route analog signals into and out of the device
using the internal analog bus. This allows the device to interface
up to 62 discrete analog signals.
Some CY8C54LP devices offer a fast, accurate, configurable
delta-sigma ADC with these features:
Less than 100 µV offset
A gain error of 0.2 percent
INL less than ±1 LSB
DNL less than ±1 LSB
SINAD better than 66 dB
The CY8C54LP family also offers a SAR ADC. Featuring 12-bit
conversions at up to 1 M samples per second, it also offers low
nonlinearity and offset errors and SNR better than 70 dB. It is
well suited for a variety of higher speed analog applications.
Two high speed voltage or current DACs support 8-bit output
signals at an update rate of up to 8 Msps. They can be routed
out of any GPIO pin. You can create higher resolution voltage
PWM DAC outputs using the UDB array. This can be used to
create a pulse width modulated (PWM) DAC of up to 10 bits, at
up to 48 kHz. The digital DACs in each UDB support PWM, PRS,
or delta-sigma algorithms with programmable widths.
In addition to the ADC and DACs, the analog subsystem
provides multiple:
Comparators
Uncommitted opamps
Configurable switched capacitor/continuous time (SC/CT)
blocks. These support:
Transimpedance amplifiers
Programmable gain amplifiers
Mixers
Other similar analog components
Document Number: 001-84934 Rev. *M
See the “Analog Subsystem” section on page 50 of this
datasheet for more details.
PSoC’s CPU subsystem is built around a 32-bit three-stage
pipelined Arm Cortex-M3 processor running at up to 80 MHz.
The Cortex-M3 includes a tightly integrated nested vectored
interrupt controller (NVIC) and various debug and trace modules.
The overall CPU subsystem includes a DMA controller, flash
cache, and RAM. The NVIC provides low latency, nested
interrupts, and tail-chaining of interrupts and other features to
increase the efficiency of interrupt handling. The DMA controller
enables peripherals to exchange data without CPU involvement.
This allows the CPU to run slower (saving power) or use those
CPU cycles to improve the performance of firmware algorithms.
The flash cache also reduces system power consumption by
allowing less frequent flash access.
PSoC’s nonvolatile subsystem consists of flash, byte-writeable
EEPROM, and nonvolatile configuration options. It provides up
to 256 KB of on-chip flash. The CPU can reprogram individual
blocks of flash, enabling boot loaders. You can enable an error
correcting code (ECC) for high reliability applications. A powerful
and flexible protection model secures the user's sensitive
information, allowing selective memory block locking for read
and write protection. Two KB of byte-writable EEPROM is
available on-chip to store application data. Additionally, selected
configuration options such as boot speed and pin drive mode are
stored in nonvolatile memory. This allows settings to activate
immediately after POR.
The three types of PSoC I/O are extremely flexible. All I/Os have
many drive modes that are set at POR. PSoC also provides up
to four I/O voltage domains through the VDDIO pins. Every GPIO
has analog I/O, LCD drive, CapSense, flexible interrupt
generation, slew rate control, and digital I/O capability. The SIOs
on PSoC allow VOH to be set independently of VDDIO when used
as outputs. When SIOs are in input mode they are high
impedance. This is true even when the device is not powered or
when the pin voltage goes above the supply voltage. This makes
the SIO ideally suited for use on an I2C bus where the PSoC may
not be powered when other devices on the bus are. The SIO pins
also have high current sink capability for applications such as
LED drives. The programmable input threshold feature of the
SIO can be used to make the SIO function as a general purpose
analog comparator. For devices with Full-Speed USB the USB
physical interface is also provided (USBIO). When not using
USB these pins may also be used for limited digital functionality
and device programming. All the features of the PSoC I/Os are
covered in detail in the “I/O System and Routing” section on
page 33 of this datasheet.
The PSoC device incorporates flexible internal clock generators,
designed for high stability and factory trimmed for high accuracy.
The internal main oscillator (IMO) is the master clock base for
the system, and has 2% accuracy at 3 MHz. The IMO can be
configured to run from 3 MHz up to 74 MHz. Multiple clock
derivatives can be generated from the main clock frequency to
meet application needs. The device provides a PLL to generate
system clock frequencies up to 80 MHz from the IMO, external
crystal, or external reference clock. It also contains a separate,
very low-power internal low speed oscillator (ILO) for the sleep
and watchdog timers. A 32.768-kHz external watch crystal is
also supported for use in real time clock (RTC) applications. The
clocks, together with programmable clock dividers, provide the
flexibility to integrate most timing requirements.
Page 5 of 126
PSoC® 5LP: CY8C54LP Family
Datasheet
The CY8C54LP family supports a wide supply operating range
from 1.71 to 5.5 V. This allows operation from regulated supplies
such as 1.8 ± 5%, 2.5 V ±10%, 3.3 V ± 10%, or 5.0 V ± 10%, or
directly from a wide range of battery types. In addition, it provides
an integrated high efficiency synchronous boost converter that
can power the device from supply voltages as low as 0.5 V. This
enables the device to be powered directly from a single battery.
In addition, you can use the boost converter to generate other
voltages required by the device, such as a 3.3 V supply for LCD
glass drive. The boost’s output is available on the VBOOST pin,
allowing other devices in the application to be powered from the
PSoC.
Figure 2-1. VDDIO Current Limit
IDDIO X
mA
VDDIO X
I/O Pins
PSoC
PSoC supports a wide range of low-power modes. These include
a 300-nA hibernate mode with RAM retention and a 2-µA sleep
mode with RTC. In the second mode the optional 32.768-kHz
watch crystal runs continuously and maintains an accurate RTC.
Power to all major functional blocks, including the programmable
digital and analog peripherals, can be controlled independently
by firmware. This allows low-power background processing
when some peripherals are not in use. This, in turn, provides a
total device current of only 3.1 mA when the CPU is running at
6 MHz.
Conversely, for the 100-pin and 68-pin devices, the set of I/O
pins associated with any VDDIO may sink up to 100 mA total, as
shown in Figure 2-2.
Figure 2-2. I/O Pins Current Limit
The details of the PSoC power modes are covered in the “Power
System” section on page 27 of this datasheet.
PSoC uses JTAG (4-wire) or SWD (2-wire) interfaces for
programming, debug, and test. Using these standard interfaces
you can debug or program the PSoC with a variety of hardware
solutions from Cypress or third party vendors. The Cortex-M3
debug and trace modules include FPB, DWT, ETM, and ITM.
These modules have many features to help solve difficult debug
and trace problems. Details of the programming, test, and
debugging interfaces are discussed in the “Programming, Debug
Interfaces, Resources” section on page 60 of this datasheet.
2. Pinouts
Ipins
VDDIO X
mA
I/O Pins
PSoC
VSSD
Each VDDIO pin powers a specific set of I/O pins. (The USBIOs
are powered from VDDD.) Using the VDDIO pins, a single PSoC
can support multiple voltage levels, reducing the need for
off-chip level shifters. The black lines drawn on the pinout
diagrams in Figure 2-3 and Figure 2-4, as well as Table 2-1,
show the pins that are powered by each VDDIO.
Each VDDIO may source up to 100 mA total to its associated I/O
pins, as shown in Figure 2-1.
Document Number: 001-84934 Rev. *M
Page 6 of 126
PSoC® 5LP: CY8C54LP Family
Datasheet
P0[5] (GPIO, OPAM P2-)
P0[4] (GPIO, OPAM P2+/SAR0 EXTREF)
VDDIO0
P0[7] (GPIO, IDAC2)
P0[6] (GPIO, IDAC0 )
55
54
53
52
58
57
56
P2[2] (GPIO)
P2[1] (GPIO)
P2[0] (GPIO)
VDDIO2
P2[4] (GPIO, TRACEDATA[0])
P2[3] (GPIO, TRACECLK)
P15[5] (GPOI)
P15[4] (GPIO)
VDDD
VSSD
VCCD
51
50
LINES SHOW VDDIO
TO IO SUPPLY
ASSOCIATION
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
QFN
P12[1] (SIO, I2C1 : SDA)
P12[0] (SIO, 12C1 : SCL)
P3[7] ( GPIO)
P3[6] ( GPIO)
VDDIO 3
(GPIO) P3[5]
(GPIO) P3[3]
(GPIO) P3[4]
VDDD
VSSD
VCCD
(MHZ XTAL: XO, GPIO) P15[0]
(GPIO) P1[6]
(GPIO) P1[7]
(SIO) P12[6]
(SIO) P12[7]
[4]
(USBIO, D+, SWDIO) P15[6]
[4] (USBIO, D-, SWDCK) P15[7]
P0[3] ( GPIO, OPAMP0 -/EXTREF0)
P0[2] ( GPIO, OPAMP0+/SAR1 EXTREF)
P0[1] ( GPIO, OPAMP0 OUT
)
P0[0] ( GPIO, OPAMP2 OUT)
P12[3] (SIO)
P12[2] (SIO)
VSSD
VDDA
VSSA
VCCA
P15[3] ( GPIO, KHZ XTAL: XI)
P15[2] ( GPIO, KHZ XTAL: XO)
28
29
30
31
32
33
34
(TOP VIEW
)
(MHZ XTAL: XI, GPIO) P15[1]
(GPIO) P3[0]
(GPIO) P3[1]
(EXTREF1, GPIO) P3[2]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
(TRACEDATA[2] , GPIO) P2[6]
(TRACEDATA[3] , GPIO) P2[7]
(I2C0 : SCL, SIO) P12[4]
(I2C0 : SDA, SIO) P12[5]
VSSB
IND
VBOOST
VBAT
VSSD
XRES
( TMS, SWDIO, GPIO) P1[0]
( TCK, SWDCK, GPIO) P1[1]
( Configurable XRES, GPIO) P1[2]
( TDO, SWV, GPIO) P1[3]
( TDI, GPIO) P1[4]
( NTRST, GPIO) P1[5]
VDDIO1
66
65
64
63
62
61
60
59
68
67
P2[5] (GPIO, TRACEDATA[1])
Figure 2-3. 68-Pin QFN Part Pinout[3]
Notes
3. The center pad on the QFN package should be connected to digital ground (VSSD) for best mechanical, thermal, and electrical performance. If not connected to
ground, it should be electrically floated and not connected to any other signal. For more information, see AN72845, Design Guidelines for QFN Devices.
4. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-84934 Rev. *M
Page 7 of 126
PSoC® 5LP: CY8C54LP Family
Datasheet
P0[6] (GPIO, IDAC0)
P0[5] (GPIO, OPAMP2-)
P0[4] (GPIO, OPAMP2+/SAR0 EXTREF)
77
76
P4[5] (GPIO)
P4[4] (GPIO)
P4[3] (GPIO)
P4[2] (GPIO)
P0[7] (GPIO, IDAC2)
87
86
85
84
83
82
81
80
79
78
90
89
88
P15[4] (GPIO)
P6[3] (GPIO)
P6[2] (GPIO)
P6[1] (GPIO)
P6[0] (GPIO)
VDDD
VSSD
VCCD
P4[7] (GPIO)
P4[6] (GPIO)
P2[1] (GPIO)
P2[0] (GPIO)
P15[5] (GPIO)
98
97
96
95
94
93
92
91
75
74
Lines show VDDIO to
I/O supply association
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDIO 0
P0[3] ( GPIO,OPAMP0-/ EXTREF0)
P0[2] ( GPIO,OPAMP0 +/SAR1 EXTREF)
P0[1] ( GPIO,OPAMP0OUT)
P0[0] ( GPIO,OPAMP2OUT)
P4[1] ( GPIO)
P4[0] ( GPIO)
P12[3] ( SIO)
P12[2] ( SIO)
VSSD
VDDA
VSSA
VCCA
NC
NC
NC
NC
NC
NC
P15[3] ( GPIO, KHZ XTAL:XI)
P15[2] ( GPIO, KHZ XTAL:XO)
P12[1] ( SIO ,I2C1 : SDA)
P12[0] ( SIO ,I2C1 : SCL)
P3[7] ( GPIO)
P3[6] ( GPIO)
(GPIO) P3[5]
VDDIO3
NC
NC
(MHZ XTAL: XO, GPIO) P15[0]
(MHZ XTAL: XI, GPIO) P15[1]
(GPIO) P3[0]
(GPIO) P3[1]
(EXTREF1, GPIO) P3[2]
(GPIO) P3[3]
(GPIO) P3[4]
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
TQFP
26
27
28
29
30
31
32
33
34
35
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
VDDIO1
(GPIO) P1[6]
(GPIO) P1[7]
(SIO) P12[6]
(SIO) P12[7]
(GPIO) P5[4]
(GPIO) P5[5]
(GPIO) P5[6]
(GPIO) P5[7]
[5]
(USBIO, D+, SWDIO) P15[6]
[5]
(USBIO, D-, SWDCK) P15[7]
VDDD
VSSD
VCCD
(TRACEDATA[1] , GPIO)P2[5]
(TRACEDATA[2] , GPIO)P2[6]
(TRACEDATA[3] , GPIO)P2[7]
(I2C0 : SCL, SIO ) P12[4]
(I2C0 : SDA, SIO ) P12[5]
( GPIO)P6[4]
( GPIO)P6[5]
( GPIO)P6[6]
( GPIO)P6[7]
VSSB
IND
VBOOST
VBAT
VSSD
XRES
( GPIO)P5[0]
( GPIO)P5[1]
( GPIO)P5[2]
( GPIO)P5[3]
( TMS, SWDIO, GPIO)P1[0]
( TCK, SWDCK, GPIO)P1[1]
(Configurable XRES , GPIO)P1[2]
( TDO, SWV, GPIO)P1[3]
( TDI , GPIO)P1[4]
( NTRST, GPIO)P1[5]
100
99
VDDIO2
P2[4] (GPIO, TRACEDATA[0])
P2[3] (GPIO, TRACECLK])
P2[2] (GPIO)
Figure 2-4. 100-Pin TQFP Part Pinout
Table 2-1. VDDIO and Port Pin Associations
VDDIO
Port Pins
VDDIO0
P0[7:0], P4[7:0], P12[3:2]
VDDIO1
P1[7:0], P5[7:0], P12[7:6]
VDDIO2
P2[7:0], P6[7:0], P12[5:4], P15[5:4]
VDDIO3
P3[7:0], P12[1:0], P15[3:0]
VDDD
P15[7:6] (USB D+, D-)
Note
5. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-84934 Rev. *M
Page 8 of 126
PSoC® 5LP: CY8C54LP Family
Datasheet
Table 2-2 shows the pinout for the 99-pin CSP package. Since there are four VDDIO pins, the set of I/O pins associated with any VDDIO
may sink up to 100 mA total, same as for the 100-pin and 68-pin devices.
Table 2-2. CSP Pinout
Ball
Name
Ball
Name
Ball
Name
Ball
Name
E5
P2[5]
L2
VIO1
B2
P3[6]
C8
VIO0
G6
P2[6]
K2
P1[6]
B3
P3[7]
D7
P0[4]
G5
P2[7]
C9
P4[2]
C3
P12[0]
E7
P0[5]
H6
P12[4]
E8
P4[3]
C4
P12[1]
B9
P0[6]
K7
P12[5]
K1
P1[7]
E3
P15[2]
D8
P0[7]
L8
P6[4]
H2
P12[6]
E4
P15[3]
D9
P4[4]
J6
P6[5]
F4
P12[7]
A1
NC
F8
P4[5]
H5
P6[6]
J1
P5[4]
A9
NC
F7
P4[6]
J5
P6[7]
H1
P5[5]
L1
NC
E6
P4[7]
L7
VSSB
F3
P5[6]
L9
NC
E9
VCCD
K6
Ind
G1
P5[7]
A3
VCCA
F9
VSSD
L6
VBOOST
G2
P15[6][6]
A4
VSSA
G9
VDDD
K5
VBAT
F2
P15[7][6]
B7
VSSA
H9
P6[0]
L5
VSSD
E2
VDDD
B8
VSSA
G8
P6[1]
L4
XRES
F1
VSSD
C7
VSSA
H8
P6[2]
J4
P5[0]
E1
VCCD
A5
VDDA
J9
P6[3]
K4
P5[1]
D1
P15[0]
A6
VSSD
G7
P15[4]
K3
P5[2]
D2
P15[1]
B5
P12[2]
F6
P15[5]
L3
P5[3]
C1
P3[0]
A7
P12[3]
F5
P2[0]
H4
P1[0]
C2
P3[1]
C5
P4[0]
J7
P2[1]
J3
P1[1]
D3
P3[2]
D5
P4[1]
J8
P2[2]
H3
P1[2]
D4
P3[3]
B6
P0[0]
K9
P2[3]
J2
P1[3]
B4
P3[4]
C6
P0[1]
H7
P2[4]
G4
P1[4]
A2
P3[5]
A8
P0[2]
K8
VIO2
G3
P1[5]
B1
VIO3
D6
P0[3]
Note
6. Pins are Do Not Use (DNU) on devices without USB. The pin must be left floating.
Document Number: 001-84934 Rev. *M
Page 9 of 126
PSoC® 5LP: CY8C54LP Family
Datasheet
Figure 2-5 and Figure 2-6 show an example schematic and an
example PCB layout, for the 100-pin TQFP part, for optimal
analog performance on a 2-layer board.
on page 27. The trace between the two VCCD pins should be
as short as possible.
The two pins labeled VSSD must be connected together.
The two pins labeled VDDD must be connected together.
For information on circuit board layout issues for mixed signals,
refer to the application note AN57821 - Mixed Signal Circuit
Board Layout Considerations for PSoC® 3 and PSoC 5.
The two pins labeled VCCD must be connected together, with
capacitance added, as shown in Figure 2-5 and Power System
Figure 2-5. Example Schematic for 100-Pin TQFP Part with Power Connections
VDDD
VDDD
C1
1 UF
VDDD
C2
0.1 UF
VSSD
VDDIO0
OA0-, REF0, P0[3]
OA0+, SAR1REF, P0[2]
OA0OUT, P0[1]
OA2OUT, P0[0]
P4[1]
P4[0]
SIO, P12[3]
SIO, P12[2]
VSSD
VDDA
VSSA
VCCA
NC
NC
NC
NC
NC
NC
KHZXIN, P15[3]
KHZXOUT, P15[2]
SIO, P12[1]
SIO, P12[0]
OA3OUT, P3[7]
VSSD
VSSD
VDDD
C12
0.1 UF
C15
1 UF
C16
0.1 UF
VDDA
VDDD
C8
0.1 UF
C17
1 UF
VSSD
VSSD
VDDA
VSSA
VCCA
VSSD
VSSA
VDDA
C9
1 UF
C10
0.1 UF
VSSA
VDDIO3
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
VDDD
C11
0.1 UF
VCCD
VDDD
OA1OUT, P3[6]
P3[5], OA1+
VDDIO1
P1[6]
P1[7]
P12[6], SIO
P12[7], SIO
P5[4]
P5[5]
P5[6]
P5[7]
USB D+, P15[6]
USB D-, P15[7]
VDDD
VSSD
VCCD
NC
NC
P15[0], MHZXOUT
P15[1], MHZXIN
P3[0], IDAC1
P3[1], IDAC3
P3[2], OA3-, REF1
P3[3], OA3+
P3[4], OA1-
P2[5]
P2[6]
P2[7]
P12[4], SIO
P12[5], SIO
P6[4]
P6[5]
P6[6]
P6[7]
VSSB
IND
VBOOST
VBAT
VSSD
XRES
P5[0]
P5[1]
P5[2]
P5[3]
P1[0], SWDIO, TMS
P1[1], SWDCK, TCK
P1[2]
P1[3], SWV, TDO
P1[4], TDI
P1[5], NTRST
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
VSSD
1
2
3
4
5
6
7
8
9
10
11
12
13
VSSD 14
15
16
17
18
19
20
21
22
23
24
25
VSSD
VDDIO2
P2[4]
P2[3]
P2[2]
P2[1]
P2[0]
P15[5]
P15[4]
P6[3]
P6[2]
P6[1]
P6[0]
VDDD
VSSD
VCCD
P4[7]
P4[6]
P4[5]
P4[4]
P4[3]
P4[2]
IDAC2, P0[7]
IDAC0, P0[6]
OA2-, P0[5]
OA2+,
SAR0REF,
P0[4]
VSSD
VDDD
100
99
98
97
96
95
94
93
92
91
90
89
88 VDDD
VSSD
87
86
85
84
83
82
81
80
79
78
77
76
VCCD
C6
0.1 UF
VSSD
VSSD
Note The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended,
as shown in Figure 2-6.
For more information on pad layout, refer to http://www.cypress.com/cad-resources/psoc-5lp-cad-libraries.
Document Number: 001-84934 Rev. *M
Page 10 of 126
PSoC® 5LP: CY8C54LP Family
Datasheet
Figure 2-6. Example PCB Layout for 100-Pin TQFP Part for Optimal Analog Performance
VSSA
VDD D
VSSD
VD DA
VSSA
Plane
VSSD
Plane
3. Pin Descriptions
IDAC0, IDAC2. Low resistance output pin for high current DACs
(IDAC).
SIO. Special I/O provides interfaces to the CPU, digital
peripherals and interrupts with a programmable high threshold
voltage, analog comparator, high sink current, and high
impedance state when the device is unpowered.
Opamp0out, Opamp2out. High current output of uncommitted
opamp[7].
SWDCK. Serial Wire Debug Clock programming and debug port
connection.
Extref0, Extref1. External reference input to the analog system.
SWDIO. Serial Wire Debug Input and Output programming and
debug port connection.
SAR0 EXTREF, SAR1 EXTREF. External references for SAR
ADCs.
Opamp0-, Opamp2-. Inverting input to uncommitted opamp.
Opamp0+, Opamp2+. Noninverting
opamp.
input
to
uncommitted
GPIO. General purpose I/O pin provides interfaces to the CPU,
digital peripherals, analog peripherals, interrupts, LCD segment
drive, and CapSense[7].
I2C0: SCL, I2C1: SCL. I2C SCL line providing wake from sleep
on an address match. Any I/O pin can be used for I2C SCL if
wake from sleep is not required.
I2C0: SDA, I2C1: SDA. I2C SDA line providing wake from sleep
on an address match. Any I/O pin can be used for I2C SDA if
wake from sleep is not required.
Ind. Inductor connection to boost pump.
kHz XTAL: Xo, kHz XTAL: Xi. 32.768 kHz crystal oscillator pin.
MHz XTAL: Xo, MHz XTAL: Xi. 4 to 25 MHz crystal oscillator
pin.
nTRST. Optional JTAG Test Reset programming and debug port
connection to reset the JTAG connection.
TCK. JTAG Test Clock programming and debug port connection.
TDI. JTAG Test Data In programming and debug port
connection.
TDO. JTAG Test Data Out programming and debug port
connection.
TMS. JTAG Test Mode Select programming and debug port
connection.
TRACECLK. Cortex-M3
TRACEDATA pins.
TRACEPORT
TRACEDATA[3:0]. Cortex-M3
output data.
connection,
TRACEPORT
clocks
connections,
SWV. Single Wire Viewer output.
USBIO, D+. Provides D+ connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from VDDD instead
of from a VDDIO. Pins are Do Not Use (DNU) on devices without
USB.
USBIO, D-. Provides D- connection directly to a USB 2.0 bus.
May be used as a digital I/O pin; it is powered from VDDD instead
of from a VDDIO. Pins are Do Not Use (DNU) on devices without
USB.
VBOOST. Power sense connection to boost pump.
Note
7. GPIOs with opamp outputs are not recommended for use with CapSense
Document Number: 001-84934 Rev. *M
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PSoC® 5LP: CY8C54LP Family
Datasheet
VBAT. Battery supply to boost pump.
VCCA. Output of the analog core regulator or the input to
the analog core. Requires a 1uF capacitor to VSSA. The
regulator output is not designed to drive external circuits. Note
that if you use the device with an external core regulator
(externally regulated mode), the voltage applied to this pin
must not exceed the allowable range of 1.71 V to 1.89 V.
When using the internal core regulator, (internally regulated
mode, the default), do not tie any power to this pin. For details
see Power System on page 27.
VCCD. Output of the digital core regulator or the input to the
digital core. The two VCCD pins must be shorted together, with
the trace between them as short as possible, and a 1uF capacitor
to VSSD. The regulator output is not designed to drive external
circuits. Note that if you use the device with an external core
regulator (externally regulated mode), the voltage applied to
this pin must not exceed the allowable range of 1.71 V to
1.89 V. When using the internal core regulator (internally
regulated mode, the default), do not tie any power to this pin. For
details see Power System on page 27.
VDDA. Supply for all analog peripherals and analog core
regulator. VDDA must be the highest voltage present on the
Document Number: 001-84934 Rev. *M
device. All other supply pins must be less than or equal to
VDDA.
VDDD. Supply for all digital peripherals and digital core
regulator. VDDD must be less than or equal to VDDA.
VSSA. Ground for all analog peripherals.
VSSB. Ground connection for boost pump.
VSSD. Ground for all digital logic and I/O pins.
VDDIO0, VDDIO1, VDDIO2, VDDIO3. Supply for I/O pins. Each
VDDIO must be tied to a valid operating voltage (1.71 V to 5.5 V),
and must be less than or equal to VDDA.
XRES. External reset pin. Active low with internal pull-up.
4. CPU
4.1 Arm Cortex-M3 CPU
The CY8C54LP family of devices has an ARM Cortex-M3 CPU
core. The Cortex-M3 is a low power 32-bit three-stage pipelined
Harvard architecture CPU that delivers 1.25 DMIPS/MHz. It is
intended for deeply embedded applications that require fast
interrupt handling features.
Page 12 of 126
PSoC® 5LP: CY8C54LP Family
Datasheet
Figure 4-1. Arm Cortex-M3 Block Diagram
Interrupt Inputs
Nested
Vectored
Interrupt
Controller
(NVIC)
I- Bus
JTAG/SWD
D-Bus
Embedded
Trace Module
(ETM)
Instrumentation
Trace Module
(ITM)
S- Bus
Trace Pins:
Debug Block
(Serial and
JTAG)
Flash Patch
and Breakpoint
(FPB)
Trace Port
5 for TRACEPORT or
Interface Unit 1 for SWV mode
(TPIU)
Cortex M3 Wrapper
C-Bus
AHB
32 KB
SRAM
Data
Watchpoint and
Trace (DWT)
Cortex M3 CPU Core
AHB
Bus
Matrix
Bus
Matrix
1 KB
Cache
256 KB
ECC
Flash
AHB
32 KB
SRAM
Bus
Matrix
AHB Bridge & Bus Matrix
DMA
PHUB
AHB Spokes
GPIO &
EMIF
Prog.
Digital
Prog.
Analog
Special
Functions
Peripherals
Document Number: 001-84934 Rev. *M
Page 13 of 126
PSoC® 5LP: CY8C54LP Family
Datasheet
The Cortex-M3 CPU subsystem includes these features:
Arm Cortex-M3 CPU
Programmable NVIC, tightly integrated with the CPU core
Full-featured debug and trace modules, tightly integrated with
the CPU core
Up to 128 KB of flash memory, 2 KB of EEPROM, and 32 KB
of SRAM
At the user level, access to certain instructions, special registers,
configuration registers, and debugging components is blocked.
Attempts to access them cause a fault exception. At the
privileged level, access to all instructions and registers is
allowed.
The processor runs in the handler mode (always at the privileged
level) when handling an exception, and in the thread mode when
not.
4.1.3 CPU Registers
Cache controller
Peripheral HUB (PHUB)
The Cortex-M3 CPU registers are listed in Table 4-2. Registers
R0-R15 are all 32 bits wide.
DMA controller
Table 4-2. Cortex M3 CPU Registers
External memory interface (EMIF)
Register
R0-R12
4.1.1 Cortex-M3 Features
The Cortex-M3 CPU features include:
4-GB address space. Predefined address regions for code,
Low Registers: Registers R0-R7 are acces-
data, and peripherals. Multiple buses for efficient and
simultaneous accesses of instructions, data, and peripherals.
The
sible by all instructions that specify a general
purpose register.
Thumb®-2
instruction set, which offers Arm-level
performance at Thumb-level code density. This includes 16-bit
and 32-bit instructions. Advanced instructions include:
Bit-field control
Hardware multiply and divide
Saturation
If-Then
Wait for events and interrupts
Exclusive access and barrier
Special register access
The Cortex-M3 does not support Arm instructions.
High Registers: Registers R8-R12 are acces-
R13
Bit-band support for the SRAM region. Atomic bit-level write
and read operations for SRAM addresses.
Unaligned data storage and access. Contiguous storage of
data of different byte lengths.
Operation at two privilege levels (privileged and user) and in
two modes (thread and handler). Some instructions can only
be executed at the privileged level. There are also two stack
pointers: Main (MSP) and Process (PSP). These features
support a multitasking operating system running one or more
user-level processes.
Extensive interrupt and system exception support.
4.1.2 Cortex-M3 Operating Modes
The Cortex-M3 operates at either the privileged level or the user
level, and in either the thread mode or the handler mode.
Because the handler mode is only enabled at the privileged level,
there are actually only three states, as shown in Table 4-1.
Table 4-1. Operational Level
Condition
Privileged
User
Running an exception Handler mode
Not used
Running main program Thread mode
Thread mode
Document Number: 001-84934 Rev. *M
Description
General purpose registers R0-R12 have no
special architecturally defined uses. Most
instructions that specify a general purpose
register specify R0-R12.
R14
R15
xPSR
sible by all 32-bit instructions that specify a
general purpose register; they are not accessible by all 16-bit instructions.
R13 is the stack pointer register. It is a banked
register that switches between two 32-bit stack
pointers: the Main Stack Pointer (MSP) and the
Process Stack Pointer (PSP). The PSP is used
only when the CPU operates at the user level in
thread mode. The MSP is used in all other
privilege levels and modes. Bits[0:1] of the SP
are ignored and considered to be 0, so the SP is
always aligned to a word (4 byte) boundary.
R14 is the Link Register (LR). The LR stores the
return address when a subroutine is called.
R15 is the Program Counter (PC). Bit 0 of the PC
is ignored and considered to be 0, so instructions
are always aligned to a half word (2 byte)
boundary.
The Program status registers are divided into
three status registers, which are accessed either
together or separately:
Application Program Status Register (APSR)
holds program execution status bits such as
zero, carry, negative, in bits[27:31].
Interrupt Program Status Register (IPSR)
holds the current exception number in bits[0:8].
Execution Program Status Register (EPSR)
holds control bits for interrupt continuable and
IF-THEN instructions in bits[10:15] and
[25:26]. Bit 24 is always set to 1 to indicate
Thumb mode. Trying to clear it causes a fault
exception.
Page 14 of 126
PSoC® 5LP: CY8C54LP Family
Datasheet
Table 4-2. Cortex M3 CPU Registers (continued)
Table 4-3. PHUB Spokes and Peripherals
Register
PRIMASK
PHUB Spokes
Peripherals
0
SRAM
1
IOs, PICU, EMIF
2
PHUB local configuration, Power manager,
Clocks, IC, SWV, EEPROM, Flash
programming interface
3
Analog interface and trim, Decimator
4
USB, I2C, Timers, Counters, and PWMs
5
Reserved
6
UDBs group 1
7
UDBs group 2
Description
A 1-bit interrupt mask register. When set, it
allows only the nonmaskable interrupt (NMI) and
hard fault exception. All other exceptions and
interrupts are masked.
FAULTMASK A 1-bit interrupt mask register. When set, it
allows only the NMI. All other exceptions and
interrupts are masked.
BASEPRI
A register of up to nine bits that define the
masking priority level. When set, it disables all
interrupts of the same or higher priority value. If
set to 0 then the masking function is disabled.
CONTROL
A 2-bit register for controlling the operating
mode.
Bit 0: 0 = privileged level in thread mode,
1 = user level in thread mode.
Bit 1: 0 = default stack (MSP) is used,
1 = alternate stack is used. If in thread mode or
user level then the alternate stack is the PSP.
There is no alternate stack for handler mode; the
bit must be 0 while in handler mode.
4.2 Cache Controller
The CY8C58LP family has a 1 KB, 4-way set-associative
instruction cache between the CPU and the flash memory. This
guarantees a faster instruction execution rate. The flash cache
also reduces system power consumption by requiring less
frequent flash access.
4.3 DMA and PHUB
The PHUB and the DMA controller are responsible for data
transfer between the CPU and peripherals, and also data
transfers between peripherals. The PHUB and DMA also control
device configuration during boot. The PHUB consists of:
A central hub that includes the DMA controller, arbiter, and
router
Multiple spokes that radiate outward from the hub to most
peripherals
There are two PHUB masters: the CPU and the DMA controller.
Both masters may initiate transactions on the bus. The DMA
channels can handle peripheral communication without CPU
intervention. The arbiter in the central hub determines which
DMA channel is the highest priority if there are multiple requests.
4.3.1 PHUB Features
CPU and DMA controller are both bus masters to the PHUB
Eight multi-layer AHB bus parallel access paths (spokes) for
peripheral access
Simultaneous CPU and DMA access to peripherals located on
different spokes
Simultaneous DMA source and destination burst transactions
on different spokes
Supports 8-, 16-, 24-, and 32-bit addressing and data
Document Number: 001-84934 Rev. *M
4.3.2 DMA Features
24 DMA channels
Each channel has one or more transaction descriptors (TDs)
to configure channel behavior. Up to 128 total TDs can be
defined
TDs can be dynamically updated
Eight levels of priority per channel
Any digitally routable signal, the CPU, or another DMA channel,
can trigger a transaction
Each channel can generate up to two interrupts per transfer
Transactions can be stalled or canceled
Supports transaction size of infinite or 1 to 64k bytes
Large transactions may be broken into smaller bursts of 1 to
127 bytes
TDs may be nested and/or chained for complex transactions
4.3.3 Priority Levels
The CPU always has higher priority than the DMA controller
when their accesses require the same bus resources. Due to the
system architecture, the CPU can never starve the DMA. DMA
channels of higher priority (lower priority number) may interrupt
current DMA transfers. In the case of an interrupt, the current
transfer is allowed to complete its current transaction. To ensure
latency limits when multiple DMA accesses are requested
simultaneously, a fairness algorithm guarantees an interleaved
minimum percentage of bus bandwidth for priority levels 2
through 7. Priority levels 0 and 1 do not take part in the fairness
algorithm and may use 100% of the bus bandwidth. If a tie occurs
on two DMA requests of the same priority level, a simple round
robin method is used to evenly share the allocated bandwidth.
The round robin allocation can be disabled for each DMA
channel, allowing it to always be at the head of the line. Priority
levels 2 to 7 are guaranteed the minimum bus bandwidth shown
in Table 4-4 after the CPU and DMA priority levels 0 and 1 have
satisfied their requirements.
When the fairness algorithm is disabled, DMA access is granted
based solely on the priority level; no bus bandwidth guarantees
are made.
Page 15 of 126
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Table 4-4. Priority Levels
Priority Level
0
1
2
3
4
5
6
7
4.3.4 Transaction Modes Supported
The flexible configuration of each DMA channel and the ability to
chain multiple channels allow the creation of both simple and
complex use cases. General use cases include, but are not
limited to:
% Bus Bandwidth
100.0
100.0
50.0
25.0
12.5
6.2
3.1
1.5
4.3.4.1 Simple DMA
In a simple DMA case, a single TD transfers data between a
source and sink (peripherals or memory location). The basic
timing diagrams of DMA read and write cycles are shown in
Figure 4-2. For more description on other transfer modes, refer
to the Technical Reference Manual.
Figure 4-2. DMA Timing Diagram
ADDRESS Phase
DATA Phase
ADDRESS Phase
CLK
ADDR 16/32
DATA Phase
CLK
A
ADDR 16/32
B
WRITE
A
B
WRITE
DATA (A)
DATA
READY
DATA
DATA (A)
READY
Basic DMA Read Transfer without wait states
4.3.4.2 Auto Repeat DMA
Auto repeat DMA is typically used when a static pattern is
repetitively read from system memory and written to a peripheral.
This is done with a single TD that chains to itself.
4.3.4.3 Ping Pong DMA
A ping pong DMA case uses double buffering to allow one buffer
to be filled by one client while another client is consuming the
data previously received in the other buffer. In its simplest form,
this is done by chaining two TDs together so that each TD calls
the opposite TD when complete.
4.3.4.4 Circular DMA
Circular DMA is similar to ping pong DMA except it contains more
than two buffers. In this case there are multiple TDs; after the last
TD is complete it chains back to the first TD.
4.3.4.5 Indexed DMA
In an indexed DMA case, an external master requires access to
locations on the system bus as if those locations were shared
memory. As an example, a peripheral may be configured as an
SPI or I2C slave where an address is received by the external
master. That address becomes an index or offset into the internal
system bus memory space. This is accomplished with an initial
“address fetch” TD that reads the target address location from
the peripheral and writes that value into a subsequent TD in the
chain. This modifies the TD chain on the fly. When the “address
fetch” TD completes it moves on to the next TD, which has the
new address information embedded in it. This TD then carries
out the data transfer with the address location required by the
external master.
Document Number: 001-84934 Rev. *M
Basic DMA Write Transfer without wait states
4.3.4.6 Scatter Gather DMA
In the case of scatter gather DMA, there are multiple
noncontiguous sources or destinations that are required to
effectively carry out an overall DMA transaction. For example, a
packet may need to be transmitted off of the device and the
packet elements, including the header, payload, and trailer, exist
in various noncontiguous locations in memory. Scatter gather
DMA allows the segments to be concatenated together by using
multiple TDs in a chain. The chain gathers the data from the
multiple locations. A similar concept applies for the reception of
data onto the device. Certain parts of the received data may need
to be scattered to various locations in memory for software
processing convenience. Each TD in the chain specifies the
location for each discrete element in the chain.
4.3.4.7 Packet Queuing DMA
Packet queuing DMA is similar to scatter gather DMA but
specifically refers to packet protocols. With these protocols,
there may be separate configuration, data, and status phases
associated with sending or receiving a packet.
For instance, to transmit a packet, a memory mapped
configuration register can be written inside a peripheral,
specifying the overall length of the ensuing data phase. The CPU
can set up this configuration information anywhere in system
memory and copy it with a simple TD to the peripheral. After the
configuration phase, a data phase TD (or a series of data phase
TDs) can begin (potentially using scatter gather). When the data
phase TD(s) finish, a status phase TD can be invoked that reads
some memory mapped status information from the peripheral
and copies it to a location in system memory specified by the
CPU for later inspection. Multiple sets of configuration, data, and
status phase “subchains” can be strung together to create larger
Page 16 of 126
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chains that transmit multiple packets in this way. A similar
concept exists in the opposite direction to receive the packets.
4.3.4.8 Nested DMA
One TD may modify another TD, as the TD configuration space
is memory mapped similar to any other peripheral. For example,
a first TD loads a second TD’s configuration and then calls the
second TD. The second TD moves data as required by the
application. When complete, the second TD calls the first TD,
which again updates the second TD’s configuration. This
process repeats as often as necessary.
4.4 Interrupt Controller
The Cortex-M3 NVIC supports 16 system exceptions and 32
interrupts from peripherals, as shown in Table 4-5.
Table 4-5. Cortex-M3 Exceptions and Interrupts
Exception
Number
1
2
3
Reset
NMI
Hard fault
–3 (highest)
–2
–1
Exception Table
Address Offset
0x00
0x04
0x08
0x0C
4
MemManage
Programmable
0x10
5
Bus fault
Programmable
0x14
6
Usage fault
Programmable
0x18
7–10
11
12
13
14
15
16–47
–
SVC
Debug monitor
–
PendSV
SYSTICK
IRQ
–
Programmable
Programmable
–
Programmable
Programmable
Programmable
0x1C–0x28
0x2C
0x30
0x34
0x38
0x3C
0x40–0x3FC
Exception Type
Priority
Bit 0 of each exception vector indicates whether the exception is
executed using Arm or Thumb instructions. Because the
Cortex-M3 only supports Thumb instructions, this bit must
always be 1. The Cortex-M3 non maskable interrupt (NMI) input
can be routed to any pin, via the DSI, or disconnected from all
pins. See “DSI Routing Interface Description” section on
page 45.
The NVIC handles interrupts from the peripherals, and passes
the interrupt vectors to the CPU. It is closely integrated with the
CPU for low latency interrupt handling. Features include:
32 interrupts. Multiple sources for each interrupt.
Eight priority levels, with dynamic priority control.
Priority grouping. This allows selection of preempting and non
preempting interrupt levels.
Document Number: 001-84934 Rev. *M
Function
Starting value of R13 / MSP
Reset
Non maskable interrupt
All classes of fault, when the corresponding fault handler
cannot be activated because it is currently disabled or
masked
Memory management fault, for example, instruction
fetch from a nonexecutable region
Error response received from the bus system; caused
by an instruction prefetch abort or data access error
Typically caused by invalid instructions or trying to
switch to Arm mode
Reserved
System service call via SVC instruction
Debug monitor
Reserved
Deferred request for system service
System tick timer
Peripheral interrupt request #0–#31
Support for tail-chaining, and late arrival, of interrupts. This
enables back-to-back interrupt processing without the
overhead of state saving and restoration between interrupts.
Processor state automatically saved on interrupt entry, and
restored on interrupt exit, with no instruction overhead.
If the same priority level is assigned to two or more interrupts,
the interrupt with the lower vector number is executed first. Each
interrupt vector may choose from three interrupt sources: Fixed
Function, DMA, and UDB. The fixed function interrupts are direct
connections to the most common interrupt sources and provide
the lowest resource cost connection. The DMA interrupt sources
provide direct connections to the two DMA interrupt sources
provided per DMA channel. The third interrupt source for vectors
is from the UDB digital routing array. This allows any digital signal
available to the UDB array to be used as an interrupt source. All
interrupt sources may be routed to any interrupt vector using the
UDB interrupt source connections.
Page 17 of 126
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Table 4-6. Interrupt Vector Table
Interrupt #
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
Cortex-M3 Exception #
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
Document Number: 001-84934 Rev. *M
Fixed Function
Low voltage detect (LVD)
Cache/ECC
Reserved
Sleep (Pwr Mgr)
PICU[0]
PICU[1]
PICU[2]
PICU[3]
PICU[4]
PICU[5]
PICU[6]
PICU[12]
PICU[15]
Comparators Combined
Switched Caps Combined
I2C
Reserved
Timer/Counter0
Timer/Counter1
Timer/Counter2
Timer/Counter3
USB SOF Int
USB Arb Int
USB Bus Int
USB Endpoint[0]
USB Endpoint Data
Reserved
LCD
Reserved
Decimator Int
phub_err_int
eeprom_fault_int
DMA
phub_termout0[0]
phub_termout0[1]
phub_termout0[2]
phub_termout0[3]
phub_termout0[4]
phub_termout0[5]
phub_termout0[6]
phub_termout0[7]
phub_termout0[8]
phub_termout0[9]
phub_termout0[10]
phub_termout0[11]
phub_termout0[12]
phub_termout0[13]
phub_termout0[14]
phub_termout0[15]
phub_termout1[0]
phub_termout1[1]
phub_termout1[2]
phub_termout1[3]
phub_termout1[4]
phub_termout1[5]
phub_termout1[6]
phub_termout1[7]
phub_termout1[8]
phub_termout1[9]
phub_termout1[10]
phub_termout1[11]
phub_termout1[12]
phub_termout1[13]
phub_termout1[14]
phub_termout1[15]
UDB
udb_intr[0]
udb_intr[1]
udb_intr[2]
udb_intr[3]
udb_intr[4]
udb_intr[5]
udb_intr[6]
udb_intr[7]
udb_intr[8]
udb_intr[9]
udb_intr[10]
udb_intr[11]
udb_intr[12]
udb_intr[13]
udb_intr[14]
udb_intr[15]
udb_intr[16]
udb_intr[17]
udb_intr[18]
udb_intr[19]
udb_intr[20]
udb_intr[21]
udb_intr[22]
udb_intr[23]
udb_intr[24]
udb_intr[25]
udb_intr[26]
udb_intr[27]
udb_intr[28]
udb_intr[29]
udb_intr[30]
udb_intr[31]
Page 18 of 126
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Datasheet
5. Memory
5.1 Static RAM
CY8C54LP static RAM (SRAM) is used for temporary data
storage. Code can be executed at full speed from the portion of
SRAM that is located in the code space. This process is slower
from SRAM above 0x20000000. The device provides up to 64
KB of SRAM. The CPU or the DMA controller can access all of
SRAM. The SRAM can be accessed simultaneously by the
Cortex-M3 CPU and the DMA controller if accessing different
32-KB blocks.
“Device Security” section on page 63). For more information on
how to take full advantage of the security features in PSoC, see
the PSoC 5 TRM.
Table 5-1. Flash Protection
Protection
Setting
Allowed
Not Allowed
Unprotected
External read and write –
+ internal read and write
Factory
Upgrade
External write + internal
read and write
External read
5.2 Flash Program Memory
Field Upgrade Internal read and write
Flash memory in PSoC devices provides nonvolatile storage for
user firmware, user configuration data, bulk data storage, and
optional ECC data. The main flash memory area contains up to
256 KB of user program space.
External read and
write
Full Protection Internal read
External read and
write + internal write
Up to an additional 32 KB of flash space is available for Error
Correcting Codes (ECC). If ECC is not used this space can store
device configuration data and bulk user data. User code may not
be run out of the ECC flash memory section. ECC can correct
one bit error and detect two bit errors per 8 bytes of firmware
memory; an interrupt can be generated when an error is
detected. The flash output is 9 bytes wide with 8 bytes of data
and 1 byte of ECC data.
The CPU or DMA controller read both user code and bulk data
located in flash through the cache controller. This provides
higher CPU performance. If ECC is enabled, the cache controller
also performs error checking and correction.
Flash programming is performed through a special interface and
preempts code execution out of flash. Code execution may be
done out of SRAM during flash programming.
The flash programming interface performs flash erasing,
programming and setting code protection levels. Flash in-system
serial programming (ISSP), typically used for production
programming, is possible through both the SWD and JTAG
interfaces. In-system programming, typically used for
bootloaders, is also possible using serial interfaces such as I2C,
USB, UART, and SPI, or any communications protocol.
5.3 Flash Security
All PSoC devices include a flexible flash protection model that
prevents access and visibility to on-chip flash memory. This
prevents duplication or reverse engineering of proprietary code.
Flash memory is organized in blocks, where each block contains
256 bytes of program or data and 32 bytes of ECC or
configuration data.
The device offers the ability to assign one of four protection
levels to each row of flash. Table 5-1 lists the protection modes
available. Flash protection levels can only be changed by
performing a complete flash erase. The Full Protection and Field
Upgrade settings disable external access (through a debugging
tool such as PSoC Creator, for example). If your application
requires code update through a boot loader, then use the Field
Upgrade setting. Use the Unprotected setting only when no
security is needed in your application. The PSoC device also
offers an advanced security feature called Device Security which
permanently disables all test, programming, and debug ports,
protecting your application from external access (see the
Document Number: 001-84934 Rev. *M
Disclaimer
Note the following details of the flash code protection features on
Cypress devices.
Cypress products meet the specifications contained in their
particular Cypress datasheets. Cypress believes that its family of
products is one of the most secure families of its kind on the
market today, regardless of how they are used. There may be
methods, unknown to Cypress, that can breach the code
protection features. Any of these methods, to our knowledge,
would be dishonest and possibly illegal. Neither Cypress nor any
other semiconductor manufacturer can guarantee the security of
their code. Code protection does not mean that we are
guaranteeing the product as “unbreakable.”
Cypress is willing to work with the customer who is concerned
about the integrity of their code. Code protection is constantly
evolving. We at Cypress are committed to continuously
improving the code protection features of our products.
5.4 EEPROM
PSoC EEPROM memory is a byte addressable nonvolatile
memory. The CY8C54LP has 2 KB of EEPROM memory to store
user data. Reads from EEPROM are random access at the byte
level. Reads are done directly; writes are done by sending write
commands to an EEPROM programming interface. CPU code
execution can continue from flash during EEPROM writes.
EEPROM is erasable and writeable at the row level. The
EEPROM is divided into 128 rows of 16 bytes each. The factory
default values of all EEPROM bytes are 0.
Because the EEPROM is mapped to the Cortex-M3 Peripheral
region, the CPU cannot execute out of EEPROM. There is no
ECC hardware associated with EEPROM. If ECC is required it
must be handled in firmware.
It can take as much as 20 milliseconds to write to EEPROM or
flash. During this time the device should not be reset, or
unexpected changes may be made to portions of EEPROM or
flash. Reset sources (see Section 6.3.1) include XRES pin,
software reset, and watchdog; care should be taken to make
sure that these are not inadvertently activated. In addition, the
low voltage detect circuits should be configured to generate an
interrupt instead of a reset.
Page 19 of 126
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Datasheet
5.5 Nonvolatile Latches (NVLs)
PSoC has a 4-byte array of nonvolatile latches (NVLs) that are used to configure the device at reset. The NVL register map is shown
in Table 5-3.
Table 5-2. Device Configuration NVL Register Map
Register Address
7
6
5
4
3
2
1
0
0x00
PRT3RDM[1:0]
PRT2RDM[1:0]
PRT1RDM[1:0]
PRT0RDM[1:0]
0x01
PRT12RDM[1:0]
PRT6RDM[1:0]
PRT5RDM[1:0]
PRT4RDM[1:0]
0x02
XRESMEN
0x03
DBGEN
DIG_PHS_DLY[3:0]
PRT15RDM[1:0]
ECCEN
DPS[1:0]
CFGSPEED
The details for individual fields and their factory default settings are shown in Table 5-3:.
Table 5-3. Fields and Factory Default Settings
Field
Description
Settings
PRTxRDM[1:0]
Controls reset drive mode of the corresponding IO port. 00b (default) - high impedance analog
See “Reset Configuration” on page 39. All pins of the port 01b - high impedance digital
are set to the same mode.
10b - resistive pull up
11b - resistive pull down
XRESMEN
0 (default) - GPIO
Controls whether pin P1[2] is used as a GPIO or as an
external reset. P1[2] is generally used as a GPIO, and not 1 - external reset
as an external reset.
DBGEN
Debug Enable allows access to the debug system, for
third-party programmers.
0 - access disabled
1 (default) - access enabled
CFGSPEED
Controls the speed of the IMO-based clock during the
device boot process, for faster boot or low-power
operation
0 (default) - 12 MHz IMO
1 - 48 MHz IMO
DPS[1:0]
Controls the usage of various P1 pins as a debug port.
See “Programming, Debug Interfaces, Resources” on
page 60.
00b - 5-wire JTAG
01b (default) - 4-wire JTAG
10b - SWD
11b - debug ports disabled
ECCEN
Controls whether ECC flash is used for ECC or for general 0 - ECC disabled
configuration and data storage. See “Flash Program
1 (default) - ECC enabled
Memory” on page 19.
DIG_PHS_DLY[3:0]
Selects the digital clock phase delay.
See the TRM for details.
Although PSoC Creator provides support for modifying the device configuration NVLs, the number of NVL erase/write cycles is limited
– see “Nonvolatile Latches (NVL)” on page 106.
Document Number: 001-84934 Rev. *M
Page 20 of 126
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Datasheet
5.6 External Memory Interface
CY8C54LP provides an EMIF for connecting to external memory
devices. The connection allows read and write accesses to
external memories. The EMIF operates in conjunction with
UDBs, I/O ports, and other hardware to generate external
memory address and control signals. At 33 MHz, each memory
access cycle takes four bus clock cycles.
Figure 5-1 is the EMIF block diagram. The EMIF supports
synchronous and asynchronous memories. The CY8C54LP only
supports one type of external memory device at a time.
External memory is located in the Cortex-M3 external RAM
space; it can use up to 24 address bits. See Table 5-4 on page
22Memory Map on page 22. The memory can be 8 or 16 bits
wide.
Cortex-M3 instructions can be fetched from external memory if it
is 16-bit. Other limitations apply; for details, see application note
AN89610, PSoC® 4 and PSoC 5LP Arm Cortex Code
Optimization.There is no provision for code security in external
memory. If code must be kept secure, then it should be placed in
internal flash. See Flash Security on page 19 and Device
Security on page 63.
Figure 5-1. EMIF Block Diagram
Address Signals
External_ MEM_ ADDR[23:0]
I/O
PORTs
Data Signals
External_ MEM_ DATA[15:0]
I/O
PORTs
Control Signals
I/O
PORTs
Data,
Address,
and Control
Signals
IO IF
PHUB
Data,
Address,
and Control
Signals
Control
DSI Dynamic Output
Control
UDB
DSI to Port
Data,
Address,
and Control
Signals
EM Control
Signals
Other
Control
Signals
EMIF
Document Number: 001-84934 Rev. *M
Page 21 of 126
PSoC® 5LP: CY8C54LP Family
Datasheet
5.7 Memory Map
Table 5-5. Peripheral Data Address Map (continued)
The Cortex-M3 has a fixed address map, which allows
peripherals to be accessed by simple memory access
instructions.
5.7.1 Address Map
The 4-GB address space is divided into the ranges shown in
Table 5-4:
Table 5-4. Address Map
Address Range
0x00000000–
0x1FFFFFFF
0x20000000–
0x3FFFFFFF
Size
Use
0.5 GB
Program code. This includes
the exception vector table at
power up, which starts at
address 0.
0.5 GB
Static RAM. This includes a 1
MByte bit-band region
starting at 0x20000000 and a
32 Mbyte bit-band alias
region starting at
0x22000000.
0x40000000–
0x5FFFFFFF
0.5 GB
Peripherals.
0x60000000–
0x9FFFFFFF
1 GB
External RAM.
0xA0000000–
0xDFFFFFFF
1 GB
External peripherals.
0xE0000000–
0xFFFFFFFF
0.5 GB
Internal peripherals, including
the NVIC and debug and
trace modules.
Table 5-5. Peripheral Data Address Map
Address Range
0x00000000–0x0003FFFF
Purpose
256K Flash
0x1FFF8000–0x1FFFFFFF 32K SRAM in Code region
0x20000000–0x20007FFF
32K SRAM in SRAM region
0x40004000–0x400042FF
Clocking, PLLs, and oscillators
0x40004300–0x400043FF
Power management
0x40004500–0x400045FF
Ports interrupt control
0x40004700–0x400047FF
Flash programming interface
0x40004800–0x400048FF
Cache controller
0x40004900–0x400049FF
I2C controller
0x40004E00–0x40004EFF
Decimator
Document Number: 001-84934 Rev. *M
Address Range
Purpose
0x40004F00–0x40004FFF
Fixed timer/counter/PWMs
0x40005000–0x400051FF
I/O ports control
0x40005400–0x400054FF
External Memory Interface
(EMIF) control registers
0x40005800–0x40005FFF
Analog Subsystem Interface
0x40006000–0x400060FF
USB Controller
0x40006400–0x40006FFF
UDB Working Registers
0x40007000–0x40007FFF
PHUB Configuration
0x40008000–0x400087FF
EEPROM
0x4000A000–0x4000A400
Reserved
0x40010000–0x4001FFFF
Digital Interconnect Configuration
0x48000000–0x48007FFF
Flash ECC Bytes
0x60000000–0x60FFFFFF
External Memory Interface
(EMIF)
0xE0000000–0xE00FFFFF
Cortex-M3 PPB Registers,
including NVIC, debug, and trace
The bit-band feature allows individual bits in SRAM to be read or
written as atomic operations. This is done by reading or writing
bit 0 of corresponding words in the bit-band alias region. For
example, to set bit 3 in the word at address 0x20000000, write a
1 to address 0x2200000C. To test the value of that bit, read
address 0x2200000C and the result is either 0 or 1 depending
on the value of the bit.
Most memory accesses done by the Cortex-M3 are aligned, that
is, done on word (4-byte) boundary addresses. Unaligned
accesses of words and 16-bit half-words on nonword boundary
addresses can also be done, although they are less efficient.
5.7.2 Address Map and Cortex-M3 Buses
The ICode and DCode buses are used only for accesses within
the Code address range, 0–0x1FFFFFFF.
The system bus is used for data accesses and debug accesses
within
the
ranges
0x20000000–0xDFFFFFFF
and
0xE0100000–0xFFFFFFFF. Instruction fetches can also be
done within the range 0x20000000–0x3FFFFFFF, although
these can be slower than instruction fetches via the ICode bus.
The private peripheral bus (PPB) is used within the Cortex-M3 to
access system control registers and debug and trace module
registers.
Page 22 of 126
PSoC® 5LP: CY8C54LP Family
Datasheet
6. System Integration
Key features of the clocking system include:
Seven general purpose clock sources
6.1 Clocking System
The clocking system generates, divides, and distributes clocks
throughout the PSoC system. For the majority of systems, no
external crystal is required. The IMO and PLL together can
generate up to a 80-MHz clock, accurate to ±2% over voltage
and temperature. Additional internal and external clock sources
allow each design to optimize accuracy, power, and cost. All of
the system clock sources can be used to generate other clock
frequencies in the 16-bit clock dividers and UDBs for anything
the user wants, for example a UART baud rate generator.
Clock generation and distribution is automatically configured
through the PSoC Creator IDE graphical interface. This is based
on the complete system’s requirements. It greatly speeds the
design process. PSoC Creator allows designers to build clocking
systems with minimal input. The designer can specify desired
clock frequencies and accuracies, and the software locates or
builds a clock that meets the required specifications. This is
possible because of the programmability inherent in PSoC.
3- to 74-MHz IMO, ±2% at 3 MHz
4- to 25-MHz external crystal oscillator (MHzECO)
Clock doubler provides a doubled clock frequency output for
the USB block, see USB Clock Domain on page 26
DSI signal from an external I/O pin or other logic
24- to 80-MHz fractional PLL sourced from IMO, MHzECO,
or DSI
1-kHz, 33-kHz, 100-kHz ILO for watchdog timer (WDT) and
sleep timer
32.768-kHz external crystal oscillator (kHzECO) for RTC
IMO has a USB mode that auto locks to USB bus clock requiring
no external crystal for USB. (USB equipped parts only)
Independently sourced clock in all clock dividers
Eight 16-bit clock dividers for the digital system
Four 16-bit clock dividers for the analog system
Dedicated 16-bit divider for the CPU bus and CPU clock
Automatic clock configuration in PSoC Creator
Table 6-1. Oscillator Summary
Source
Fmin
Tolerance at Fmin
Fmax
Tolerance at Fmax
Startup Time
IMO
3 MHz
±2% over voltage and temperature
74 MHz
±7%
13 µs max
MHzECO
4 MHz
Crystal dependent
25 MHz
Crystal dependent
5 ms typ, max is
crystal dependent
DSI
0 MHz
Input dependent
33 MHz
Input dependent
Input dependent
PLL
24 MHz
Input dependent
80 MHz
Input dependent
250 µs max
Doubler
48 MHz
Input dependent
48 MHz
Input dependent
1 µs max
ILO
1 kHz
–50%, +100%
100 kHz
-55%, +100%
15 ms max in lowest
power mode
kHzECO
32 kHz
Crystal dependent
32 kHz
Crystal dependent
500 ms typ, max is
crystal dependent
Document Number: 001-84934 Rev. *M
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PSoC® 5LP: CY8C54LP Family
Datasheet
Figure 6-1. Clocking Subsystem
3-74 MHz
IMO
4-25 MHz
ECO
External IO
or DSI
0-33 MHz
32 kHz ECO
1,33,100 kHz
ILO
CPU
Clock
48 MHz
Doubler for
USB
24-80 MHz
PLL
System
Clock Mux
Bus
Clock
Bus Clock Divider
16 bit
7
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
7
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
Digital Clock
Divider 16 bit
Digital Clock
Divider 16 bit
Analog Clock
Divider 16 bit
s
k
e
w
6.1.1 Internal Oscillators
Figure 6-1 shows that there are two internal oscillators. They can
be routed directly or divided. The direct routes may not have a
50% duty cycle. Divided clocks have a 50% duty cycle.
6.1.1.1 Internal Main Oscillator
In most designs the IMO is the only clock source required, due
to its ±2% accuracy. The IMO operates with no external
components and outputs a stable clock. A factory trim for each
frequency range is stored in the device. With the factory trim,
tolerance varies from ±2% at 3 MHz, up to ±7% at 74 MHz. The
IMO, in conjunction with the PLL, allows generation of CPU and
system clocks up to the device's maximum frequency (see
Phase-Locked Loop)
The IMO provides clock outputs at 3-, 6-, 12-, 24-, 48-, and
74-MHz.
6.1.1.2 Clock Doubler
The clock doubler outputs a clock at twice the frequency of the
input clock. The doubler works at input frequency of 24 MHz,
providing 48 MHz for the USB. It can be configured to use a clock
from the IMO, MHzECO, or the DSI (external pin).
6.1.1.3 Phase-Locked Loop
The PLL allows low frequency, high accuracy clocks to be
multiplied to higher frequencies. This is a tradeoff between
Document Number: 001-84934 Rev. *M
higher clock frequency and accuracy and, higher power
consumption and increased startup time.
The PLL block provides a mechanism for generating clock
frequencies based upon a variety of input sources. The PLL
outputs clock frequencies in the range of 24 to 80 MHz. Its input
and feedback dividers supply 4032 discrete ratios to create
almost any desired system clock frequency. The accuracy of the
PLL output depends on the accuracy of the PLL input source.
The most common PLL use is to multiply the IMO clock at 3 MHz,
where it is most accurate, to generate the CPU and system
clocks up to the device’s maximum frequency.
The PLL achieves phase lock within 250 µs (verified by bit
setting). It can be configured to use a clock from the IMO,
MHzECO, or DSI (external pin). The PLL clock source can be
used until lock is complete and signaled with a lock bit. The lock
signal can be routed through the DSI to generate an interrupt.
Disable the PLL before entering low power modes.
6.1.1.4 Internal Low Speed Oscillator
The ILO provides clock frequencies for low power consumption,
including the watchdog timer, and sleep timer. The ILO
generates up to three different clocks: 1 kHz, 33 kHz, and
100 kHz.
The 1-kHz clock (CLK1K) is typically used for a background
‘heartbeat’ timer. This clock inherently lends itself to low power
supervisory operations such as the watchdog timer and long
sleep intervals using the central timewheel (CTW).
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PSoC® 5LP: CY8C54LP Family
Datasheet
The central timewheel is a 1-kHz, free-running, 13-bit counter
clocked by the ILO. The central timewheel is always enabled
except in hibernate mode and when the CPU is stopped during
debug on chip mode. It can be used to generate periodic
interrupts for timing purposes or to wake the system from a low
power mode. Firmware can reset the central timewheel.
The central timewheel can be programmed to wake the system
periodically and optionally issue an interrupt. This enables
flexible, periodic wakeups from low power modes or coarse
timing applications. Systems that require accurate timing should
use the RTC capability instead of the central timewheel.
The 100-kHz clock (CLK100K) can be used as a low power
system clock to run the CPU. It can also generate time intervals
using the fast timewheel.
6.1.2.2 32.768 kHz ECO
The 32.768-kHz external crystal oscillator (32kHzECO) provides
precision timing with minimal power consumption using an
external 32.768-kHz watch crystal (see Figure 6-3). The
32kHzECO also connects directly to the sleep timer and provides
the source for the RTC. The RTC uses a 1-second interrupt to
implement the RTC functionality in firmware.
The oscillator works in two distinct power modes. This allows
users to trade off power consumption with noise immunity from
neighboring circuits. The GPIO pins connected to the external
crystal and capacitors are fixed.
Figure 6-3. 32kHzECO Block Diagram
The fast timewheel is a 5-bit counter, clocked by the 100-kHz
clock. It features programmable settings and automatically
resets when the terminal count is reached. An optional interrupt
can be generated each time the terminal count is reached. This
enables flexible, periodic interrupts of the CPU at a higher rate
than is allowed using the central timewheel.
The 33-kHz clock (CLK33K) comes from a divide-by-3 operation
on CLK100K. This output can be used as a reduced accuracy
version of the 32.768-kHz ECO clock with no need for a crystal.
6.1.2 External Oscillators
Figure 6-1 shows that there are two external oscillators. They
can be routed directly or divided. The direct routes may not have
a 50% duty cycle. Divided clocks have a 50% duty cycle.
32 kHz
Crystal Osc
Xi
(Pin P15[3])
External
Components
XCLK32K
Xo
(Pin P15[2])
32 kHz
crystal
Capacitors
6.1.2.1 MHz External Crystal Oscillator
The MHzECO provides high frequency, high precision clocking
using an external crystal (see Figure 6-2). It supports a wide
variety of crystal types, in the range of 4 to 25 MHz. When used
in conjunction with the PLL, it can generate CPU and system
clocks up to the device's maximum frequency (see
Phase-Locked Loop on page 24). The GPIO pins connecting to
the external crystal and capacitors are fixed. MHzECO accuracy
depends on the crystal chosen.
Figure 6-2. MHzECO Block Diagram
It is recommended that the external 32.768-kHz watch crystal
have a load capacitance (CL) of 6 pF or 12.5 pF. Check the
crystal manufacturer's datasheet. The two external capacitors,
CL1 and CL2, are typically of the same value, and their total
capacitance, CL1CL2 / (CL1 + CL2), including pin and trace
capacitance, should equal the crystal CL value. For more information, refer to application note AN54439: PSoC 3 and PSoC 5
External Oscillators. See also pin capacitance specifications in
the “GPIO” section on page 73.
6.1.2.3 Digital System Interconnect
4 - 25 MHz
Crystal Osc
Xi
(Pin P15[1])
External
Components
XCLK_MHZ
Xo
(Pin P15[0])
The DSI provides routing for clocks taken from external clock
oscillators connected to I/O. The oscillators can also be
generated within the device in the digital system and Universal
Digital Blocks.
While the primary DSI clock input provides access to all clocking
resources, up to eight other DSI clocks (internally or externally
generated) may be routed directly to the eight digital clock
dividers. This is only possible if there are multiple precision clock
sources.
4 – 25 MHz
crystal
Capacitors
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PSoC® 5LP: CY8C54LP Family
Datasheet
6.1.3 Clock Distribution
All seven clock sources are inputs to the central clock distribution
system. The distribution system is designed to create multiple
high precision clocks. These clocks are customized for the
design’s requirements and eliminate the common problems
found with limited resolution prescalers attached to peripherals.
The clock distribution system generates several types of clock
trees.
The system clock is used to select and supply the fastest clock
in the system for general system clock requirements and clock
synchronization of the PSoC device.
Bus clock 16-bit divider uses the system clock to generate the
system’s bus clock used for data transfers and the CPU. The
CPU clock is directly derived from the bus clock.
Eight fully programmable 16-bit clock dividers generate digital
Each clock divider consists of an 8-input multiplexer, a 16-bit
clock divider (divide by 2 and higher) that generates ~50% duty
cycle clocks, system clock resynchronization logic, and deglitch
logic. The outputs from each digital clock tree can be routed into
the digital system interconnect and then brought back into the
clock system as an input, allowing clock chaining of up to 32 bits.
6.1.4 USB Clock Domain
The USB clock domain is unique in that it operates largely
asynchronously from the main clock network. The USB logic
contains a synchronous bus interface to the chip, while running
on an asynchronous clock to process USB data. The USB logic
requires a 48 MHz frequency. This frequency can be generated
from different sources, including DSI clock at 48 MHz or doubled
value of 24 MHz from internal oscillator, DSI signal, or crystal
oscillator.
system clocks for general use in the digital system, as
configured by the design’s requirements. Digital system clocks
can generate custom clocks derived from any of the seven
clock sources for any purpose. Examples include baud rate
generators, accurate PWM periods, and timer clocks, and
many others. If more than eight digital clock dividers are
required, the UDBs and fixed function timer/counter/PWMs can
also generate clocks.
Four 16-bit clock dividers generate clocks for the analog system
components that require clocking, such as the ADC. The
analog clock dividers include skew control to ensure that critical
analog events do not occur simultaneously with digital
switching events. This is done to reduce analog system noise.
Document Number: 001-84934 Rev. *M
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PSoC® 5LP: CY8C54LP Family
Datasheet
6.2 Power System
The power system consists of separate analog, digital, and I/O supply pins, labeled VDDA, VDDD, and VDDIOX, respectively. It also
includes two internal 1.8 V regulators that provide the digital (VCCD) and analog (VCCA) supplies for the internal core logic. The output
pins of the regulators (VCCD and VCCA) and the VDDIO pins must have capacitors connected as shown in Figure 6-4. The two VCCD
pins must be shorted together, with as short a trace as possible, and connected to a 1 µF ±10% X5R capacitor. The power system
also contains a sleep regulator, an I2C regulator, and a hibernate regulator.
Figure 6-4. PSoC Power System
VDDD
1 µF
VDDIO2
VDDD
I/O Supply
VSSD
VCCD
VDDIO 2
VDDIO0
0.1 µF
0.1 µF
I/O Supply
VDDIO0
0.1 µF
I2C
Regulator
Sleep
Regulator
Digital
Domain
VDDA
VDDA
Digital
Regulators
VSSB
VCCA
Analog
Regulator
0.1 µF
1 µF
.
VSSA
Analog
Domain
0.1µF
I/O Supply
VDDIO3
VDDD
VSSD
I/O Supply
VCCD
VDDIO1
Hibernate
Regulator
0.1µF
0.1 µF
VDDIO1
VDDD
VDDIO3
Notes
The two VCCD pins must be connected together with as short a trace as possible. A trace under the device is recommended, as
shown in Figure 2-6.
You can power the device in internally regulated mode, where the voltage applied to the VDDx pins is as high as 5.5 V, and the
internal regulators provide the core voltages. In this mode, do not apply power to the VCCx pins, and do not tie the VDDx pins
to the VCCx pins.
You can also power the device in externally regulated mode, that is, by directly powering the VCCD and VCCA pins. In this configuration,
the VDDD pins should be shorted to the VCCD pins and the VDDA pin should be shorted to the VCCA pin. The allowed supply range
in this configuration is 1.71 V to 1.89 V. After power up in this configuration, the internal regulators are on by default, and should be
disabled to reduce power consumption.
It is good practice to check the datasheets for your bypass capacitors, specifically the working voltage and the DC bias specifications.
With some capacitors, the actual capacitance can decrease considerably when the DC bias (VDDX or VCCX in Figure 6-4) is a
significant percentage of the rated working voltage.
Document Number: 001-84934 Rev. *M
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PSoC® 5LP: CY8C54LP Family
Datasheet
6.2.1 Power Modes
PSoC 5LP devices have four different power modes, as shown
in Table 6-2 and Table 6-3. The power modes allow a design to
easily provide required functionality and processing power while
simultaneously minimizing power consumption and maximizing
battery life in low power and portable devices.
PSoC 5LP power modes, in order of decreasing power
consumption are:
Active
Alternate Active
Active is the main processing mode. Its functionality is
configurable. Each power controllable subsystem is enabled or
disabled by using separate power configuration template
registers. In alternate active mode, fewer subsystems are
enabled, reducing power. In sleep mode most resources are
disabled regardless of the template settings. Sleep mode is
optimized to provide timed sleep intervals and Real Time Clock
functionality. The lowest power mode is hibernate, which retains
register and SRAM state, but no clocks, and allows wakeup only
from I/O pins. Figure 6-5 illustrates the allowable transitions
between power modes. Sleep and hibernate modes should not
be entered until all VDDIO supplies are at valid voltage levels.
Sleep
Hibernate
Table 6-2. Power Modes
Power Modes
Active
Alternate
Active
Sleep
Hibernate
Entry
Wakeup
Condition
Source
Primary mode of operation, all periph- Wakeup,
Any interrupt
erals available (programmable)
reset,
manual
register entry
Description
Active Clocks
Regulator
Any (program- All regulators available.
mable)
Digital and analog
regulators can be disabled if
external regulation used.
Similar to Active mode, and is typically Manual
Any interrupt
Any (programconfigured to have fewer peripherals register entry
mable)
active to reduce power. One possible
configuration is to use the UDBs for
processing, with the CPU turned off
All subsystems automatically disabled Manual
Comparator,
ILO/kHzECO
register entry PICU, I2C, RTC,
CTW, LVD
PICU
All subsystems automatically disabled Manual
Lowest power consuming mode with all register entry
peripherals and internal regulators
disabled, except hibernate regulator is
enabled
Configuration and memory contents
retained
All regulators available.
Digital and analog
regulators can be disabled if
external regulation used.
Both digital and analog
regulators buzzed.
Digital and analog
regulators can be disabled if
external regulation used.
Only hibernate regulator
active.
Table 6-3. Power Modes Wakeup Time and Power Consumption
Sleep
Modes
Wakeup
Time
Current
(Typ)
Code
Execution
Digital
Resources
Analog
Resources
Clock Sources
Available
Wakeup
Sources
Reset
Sources
Active
–
3.1 mA[8]
Yes
All
All
All
–
All
Alternate
Active
–
–
User
defined
All
All
All
–
All
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