Please note that Cypress is an Infineon Technologies Company.
The document following this cover page is marked as “Cypress” document as this is the
company that originally developed the product. Please note that Infineon will continue
to offer the product to new and existing customers as part of the Infineon product
portfolio.
Continuity of document content
The fact that Infineon offers the following product as part of the Infineon product
portfolio does not lead to any changes to this document. Future revisions will occur
when appropriate, and any changes will be set out on the document history page.
Continuity of ordering part numbers
Infineon continues to support existing part numbers. Please continue to use the
ordering part numbers listed in the datasheet for ordering.
www.infineon.com
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
PSoC 61 MCU
General Description
PSoC® 6 MCU is a high-performance, ultra-low-power and secured MCU platform, purpose-built for IoT applications. The CY8C61x6/7
product line, based on the PSoC 6 MCU platform, is a combination of a high-performance microcontroller with low-power flash
technology, digital programmable logic, high-performance analog-to-digital conversion and standard communication and timing
peripherals.
Features
32-bit Dual CPU Subsystem
Quad SPI (QSPI)/Serial Memory Interface (SMIF)
Note: In PSoC 61 the Cortex M0+ is reserved for system
functions, and is not available for applications.
■
■
150-MHz Arm® Cortex®-M4F (CM4) CPU with single-cycle
multiply, floating point, and memory protection unit (MPU)
100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply
and MPU
■ Core logic operation at either 1.1 V or 0.9 V, depending on the
part selected. See Ordering Information.
■ Active CPU current slope with 1.1-V core operation
❐ Cortex-M4: 40 µA/MHz
❐ Cortex-M0+: 20 µA/MHz
■ Active CPU current slope with 0.9-V core operation
❐ Cortex-M4: 22 µA/MHz
❐ Cortex-M0+: 15 µA/MHz
■ Two DMA controllers with 16 channels each
■
■
■
■
Memory Subsystem
Segment LCD Drive
■
■
■
One-time-programmable (OTP) 1-Kb eFuse array
Low-Power 1.7-V to 3.6-V Operation
Six power modes for fine-grained power management
■ Deep Sleep mode current of 7 µA with 64-KB SRAM retention
■ On-chip Single-In Multiple Out (SIMO) DC-DC buck converter,
2.7 V
DRIVE_SEL 3
4.7 kΩ typ.
XRES
drive
No restrictions
XRES
Watchdog timer (WDT or MCWDT) to reset the device if
firmware fails to service it within a specified timeout period.
■ Software-initiated reset to reset the device on demand using
firmware.
■ Logic-protection fault can trigger an interrupt or reset the device
if unauthorized operating conditions occur; for example,
reaching a debug breakpoint while executing privileged code.
■ Hibernate wakeup reset to bring the device out of the system
Hibernate low-power mode.
■
Watchdog Timers (WDT, MCWDT)
PSoC 6 MCU has one WDT and two multi-counter WDTs
(MCWDTs). The WDT has a 16-bit free-running counter. Each
MCWDT has two 16-bit counters and one 32-bit counter, with
multiple operating modes. All of the 16-bit counters can generate
a watchdog device reset. All of the counters can generate an
interrupt on a match event.
The WDT is clocked by the ILO. It can do interrupt/wakeup
generation in system LP/ULP, Deep Sleep, and Hibernate power
modes. The MCWDTs are clocked by LFCLK (ILO or WCO). It
can do periodic interrupt/wakeup generation in system LP/ULP
and Deep Sleep power modes.
Reset events are asynchronous and guarantee reversion to a
known state. Some of the reset sources are recorded in a
register, which is retained through reset and allows software to
determine the cause of the reset.
Clock Dividers
Integer and fractional clock dividers are provided for peripheral
use and timing purposes. There are:
■ Eight 8-bit clock dividers
■ Sixteen 16-bit integer clock dividers
■ Four 16.5-bit fractional clock dividers
■ One 24.5-bit fractional clock divider
Document Number: 002-21414 Rev. *M
Page 14 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Programmable Analog Subsystem
12-bit SAR ADC
The 12-bit, 1-Msps SAR ADC can operate at a maximum clock
rate of 18 MHz and requires a minimum of 18 clocks at that
frequency to do a 12-bit conversion. One of three internal
references may be used for the ADC reference voltage: VDDA,
VDDA/2, and an analog reference (AREF). AREF is nominally
1.2 V, trimmed to ±1%; see Table 23. An external reference may
also be used, by driving the VREF pin. When using VDDA/2 or
AREF as a reference, an external bypass capacitor may be
connected to the VREF pin to improve performance in noisy
conditions. These reference options allow ratio-metric readings
or absolute readings at the accuracy of the reference used. The
input range of the ADC is the full supply voltage between VSS
and VDDA/VDDIOA. The SAR ADC may be configured with a mix
of single-ended and differential signals in the same
configuration.
The SAR ADC’s sample-and-hold (S/H) aperture is
programmable to allow sufficient time for signals with a high
impedance to settle sufficiently, if required. System performance
will be 65 dB for true 12-bit precision provided appropriate
references are used and system noise levels permit it.
The SAR is connected to a fixed set of pins through an input
multiplexer. The multiplexer cycles through the selected
channels autonomously (sequencer scan) and does so with zero
switching overhead (that is, the aggregate sampling bandwidth
is equal to 1 Msps whether it is for a single channel or distributed
over several channels). The result of each channel is buffered,
so that an interrupt may be triggered only when a full scan of all
channels is complete. Also, a pair of range registers can be set
to detect and cause an interrupt if an input exceeds a minimum
and/or maximum value. This allows fast detection of out-of-range
values without having to wait for a sequencer scan to be
completed and the CPU to read the values and check for
out-of-range values in software. The SAR can also be
connected, under firmware control, to most other GPIO pins via
the Analog Multiplexer Bus (AMUXBUS). The SAR is not
available in Deep Sleep and Hibernate modes as it requires a
high -speed clock (up to 18 MHz). The SAR operating range is
1.71 to 3.6 V.
ADC accuracy is affected by GPIO switching noise. To improve
accuracy, implement the GPIO port restrictions listed in Table 6.
In addition, there should be no switching outputs on ports 9 and
10.
Document Number: 002-21414 Rev. *M
Temperature Sensor
An on-chip temperature sensor is part of the SAR and may be
scanned by the SAR ADC. It consists of a diode, which is biased
by a current source that can be disabled to save power. The
temperature sensor may be connected directly to the SAR ADC
as one of the measurement channels. The ADC digitizes the
temperature sensor’s output and a Cypress-supplied software
function may be used to convert the reading to temperature
which includes calibration and linearization.
12-bit Digital-Analog Converter
There is a 12-bit voltage mode DAC on the chip, which can settle
in less than 2 µs. The DAC may be driven by the DMA controllers
to generate user-defined waveforms. The DAC output from the
chip can either be the resistive ladder output (highly linear near
ground) or a buffered output using an opamp in the CTBm block.
Continuous Time Block mini (CTBm) with Two Opamps
This block consists of two opamps, which have their inputs and
outputs connected to pins and other analog blocks, as Figure 7
shows. They have three power modes (high, medium, and low)
and a comparator mode. The opamps can be used to buffer SAR
inputs and DAC outputs. The non-inverting inputs of these
opamps can be connected to either of two pins, thus allowing
independent sensors to be used at different times. The pin
selection can be made via firmware.
The opamps also support operation in system Deep Sleep mode,
with lower performance and reduced power consumption.
Low-Power Comparators
Two low-power comparators are provided, which can operate in
all power modes. This allows other analog system resources to
be disabled while retaining the ability to monitor external voltage
levels during system Deep Sleep and Hibernate modes. The
comparator outputs are normally synchronized to avoid
metastability unless operating in an asynchronous power mode
(Hibernate) where the system wake-up circuit is activated by a
comparator-switch event.
Page 15 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Figure 7 shows an overview of the analog subsystem. This diagram is a high-level abstraction. See the Architecture TRMfor detailed
connectivity information.
P8.0
P8.1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
Figure 7. Analog Subsystem
AMUXBUSA
AMUXBUSB
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
P6.7
CSD
LPCOMP0
inp
inn
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
shield_pad
vref_ext
csh
cmod
amuxbusa
amuxbusb
LPCOMP1
inp
inn
P5.0
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
Red dots indicate
AMUXBUS splitter
switches
VDDA
CTDAC
vref
vout
The DAC output is also
routed directly to P9.6;
not shown in this
diagram.
See the Alternate Port
Pin Functionality table..
S/H
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
P3.3
P3.4
P3.5
P4.0
P4.1
P14.0
P14.1
OA1
P9.3
P9.7
P9.5
10x
+
-
comp out
1x
P9.4
P9.0
P9.6
OA0
+
Bold lines indicate
direct connections
from the opamp 10x
ouputs to port pins.
10x
comp out
-
P9.1
1x
P11.0
P11.1
P11.2
P11.3
P11.4
P11.5
P11.6
P11.7
P9.2
AREF, 1.2 V
SARMUX (2)
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7
TEMP
temp
VSS
Document Number: 002-21414 Rev. *M
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
SAR ADC
vplus
vminus
vref
VDDA
V DDA / 2
SARREF
To VREF pin, for bypass capacitor
P12.0
P12.1
P12.2
P12.3
P12.4
P12.5
P12.6
P12.7
P13.0
P13.1
P13.2
P13.3
P13.4
P13.5
P13.6
P13.7
Page 16 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Programmable Digital
Fixed-Function Digital
Smart I/O
Timer/Counter/Pulse-width Modulator (TCPWM) Block
Smart I/O is a programmable logic fabric that enables Boolean
operations on signals traveling from device internal resources to
the GPIO pins or on signals traveling into the device from
external sources. A Smart I/O block sits between the GPIO pins
and the high-speed I/O matrix (HSIOM) and is dedicated to a
single port.
There are two Smart I/O blocks: one on Port 8 and one on Port 9.
When Smart I/O is not enabled, all signals on Port 8 and Port 9
bypass the Smart I/O hardware.
Smart I/O supports:
■
System Deep Sleep operation
■
Boolean operations without CPU intervention
■
Asynchronous or synchronous (clocked) operation
Each Smart I/O block contains a data unit (DU) and eight lookup
tables (LUTs).
The DU:
■
Performs unique functions based on a selectable opcode.
■
Can source input signals from internal resources, the GPIO
port, or a value in the DU register.
Each LUT:
■
Has three selectable input sources. The input signals may be
sourced from another LUT, an internal resource, an external
signal from a GPIO pin, or from the DU.
■
Acts as a programmable Boolean logic table.
■
Can be synchronous or asynchronous.
The TCPWM supports the following operational modes:
❐ Timer-counter with compare
❐ Timer-counter with capture
❐ Quadrature decoding
❐ Pulse width modulation (PWM)
❐ Pseudo-random PWM
❐ PWM with dead time
■ Up, down, and up/down counting modes.
■ Clock prescaling (division by 1, 2, 4, ... 64, 128)
■ Double buffering of compare/capture and period values
■ Underflow, overflow, and capture/compare output signals
■ Supports interrupt on:
❐ Terminal count – Depends on the mode; typically occurs on
overflow or underflow
❐ Capture/compare – The count is captured to the capture register or the counter value equals the value in the compare
register
■ Complementary output for PWMs
■
■
In this device there are:
■
Eight 32-bit TCPWMs
■
Twenty-four 16-bit TCPWMs
Serial Communication Blocks (SCB)
This product line has nine SCBs:
Universal Digital Blocks (UDBs)
■
This product line has 12 UDBs. Each UDB is a collection of
uncommitted logic (PLD) and nano-CPU (datapath) optimized to
create common embedded peripherals and custom functionality,
as Figure 8 shows. UDB datapaths are 8 bits wide, and can be
chained to form 16, 24, and 32-bit functions. Included with the
UDBs is the digital system interconnect (DSI), which routes
signals among UDBs, fixed function peripherals, I/O pins and
other system blocks to implement full featured device connectivity. The DSI enables routing between any digital function and
any pin. Port adapter blocks extend the UDBs to provide an
interface to the GPIOs through the HSIOM.
■
Figure 8. UDB Block Diagram
PLD
Chaining
Clock
and Reset
Control
Status and
Control
PLD
12C4
(8 PTs)
PLD
12C4
(8 PTs)
Datapath
Selectable start, reload, stop, count, and capture event signals
for each TCPWM; with rising edge, falling edge, both edges,
and level trigger options. The TCPWM has a Kill input to force
outputs to a predetermined state.
Datapath
Chaining
Eight can implement either I2C, UART, or SPI.
One SCB (SCB #8) can operate in system Deep Sleep mode
with an external clock; this SCB can be either SPI slave or I2C
slave.
I2C Mode: The SCB can implement a full multi-master and slave
interface (it is capable of multimaster arbitration). This block can
operate at speeds of up to 1 Mbps (Fast Mode Plus). It also
supports EZI2C, which creates a mailbox address range and
effectively reduces I2C communication to reading from and
writing to an array in the memory.The SCB supports a 256-byte
FIFO for receive and transmit.
The I2C peripheral is compatible with I2C standard-mode, Fast
Mode, and Fast Mode Plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus
I/O is implemented with GPIO in open-drain modes.
UART Mode: This is a full-feature UART operating at up to
8 Mbps. It supports automotive single-wire interface (LIN),
infrared interface (IrDA), and SmartCard (ISO7816) protocols, all
of which are minor variants of the basic UART protocol. In
addition, it supports the 9-bit multiprocessor mode that allows the
addressing of peripherals connected over common Rx and Tx
lines. Common UART functions such as parity error, break
detect, and frame error are supported. A 256-byte FIFO allows
much greater CPU service latencies to be tolerated.
Routing Channel
Document Number: 002-21414 Rev. *M
Page 17 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
SPI Mode: The SPI mode supports full Motorola SPI, TI Secure
Simple Pairing (SSP) (essentially adds a start pulse that is used
to synchronize SPI Codecs), and National Microwire (half-duplex
form of SPI). The SPI block supports an EZSPI mode in which
the data interchange is reduced to reading and writing an array
in memory. The SPI interface operates with a 25-MHz clock.
GPIO
This product line has up to 100 GPIOs, which implement:
■
Eight drive strength modes:
❐ Analog input mode (input and output buffers disabled)
❐ Input only
❐ Weak pull-up with strong pull-down
❐ Strong pull-up with weak pull-down
❐ Open drain with strong pull-down
❐ Open drain with strong pull-up
❐ Strong pull-up with strong pull-down
❐ Weak pull-up with weak pull-down
A serial memory interface is provided, running at up to 80 MHz.
It supports single, dual, quad, dual-quad and octal SPI
configurations, and supports up to four external memory devices.
It supports two modes of operation:
■
Input threshold select (CMOS or LVTTL)
■
Hold mode for latching previous state (used for retaining the
I/O state in system Hibernate mode)
■
Memory-mapped I/O (MMIO), a command mode interface that
provides data access via the SMIF registers and FIFOs
■
Selectable slew rates for dV/dt-related noise control to improve
EMI
■
Execute in Place (XIP), in which AHB reads and writes are
directly translated to SPI read and write transfers.
USB Full-Speed Device Interface
PSoC 6 incorporates a full-speed USB device interface. The
device can have up to eight endpoints. A 512-byte SRAM buffer
is provided and DMA is supported.
QSPI Interface Serial Memory Interface (SMIF)
In XIP mode, the external memory is mapped into the PSoC 6
MCU internal address space, enabling code execution directly
from the external memory. To improve performance, a 4-KB
cache is included. XIP mode also supports AES-128 on-the-fly
encryption and decryption, enabling secured storage and access
of code and data in the external memory.
LCD
This block drives LCD commons and segments; routing is
available to most of the GPIOs. One to eight of the GPIOs must
be used for commons, the rest can be used for segments.
The LCD block has two modes of operation: high speed (8 MHz)
and low speed (32 kHz). Both modes operate in system LP and
ULP modes. Low-speed mode operates with reduced contrast in
system Deep Sleep mode - review the number of common and
segment lines, viewing angle requirements, and prototype
performance before using this mode.
The pins are organized in logical entities called ports, which are
up to 8 pins in width. Data output and pin state registers store,
respectively, the values to be driven on the pins and the input
states of the pins.
Every pin can generate an interrupt if enabled; each port has an
interrupt request (IRQ) associated with it.
The port 1 pins are capable of overvoltage-tolerant (OVT)
operation, where the input voltage may be higher than VDDD.
OVT pins are commonly used with I2C, to allow powering the
chip OFF while maintaining a physical connection to an
operating I2C bus without affecting its functionality.
GPIO pins can be ganged to source or sink higher values of
current. GPIO pins, including OVT pins, may not be pulled up
higher than the absolute maximum; see Electrical Specifications.
During power-on and reset, the pins are forced to the analog
input drive mode, with input and output buffers disabled, so as
not to crowbar any inputs and/or cause excess turn-on current.
A multiplexing network known as the high-speed I/O matrix
(HSIOM) is used to multiplex between various peripheral and
analog signals that may connect to an I/O pin.
Analog performance is affected by GPIO switching noise. In
order to get the best analog performance, the following
frequency and drive mode constraints must be applied. The
DRIVE_SEL values (refer to Table 6) represent drive strengths
(see the Architecture and Register TRMs for further detail).
See also Table 5 for additional restrictions for ECO use.
Table 6. DRIVE_SEL Values
Ports
Max Frequency
Port 0
8 MHz
Port 1
1 MHz; slow slew rate, 2 outputs max
Port 2
50 MHz
Drive Strength for VDDD ≤ 2.7 V Drive Strength for VDDD > 2.7 V
DRIVE_SEL 2
DRIVE_SEL 3
Ports 3 to 10
16 MHz; 25 MHz for SPI
Ports 11 to 13
80 MHz for SMIF (QSPI).
DRIVE_SEL 1
DRIVE_SEL 2
Ports 9 and 10
8 MHz; slow slew rate setting for TQFP
Packages for ADC performance
No restrictions
No restrictions
Document Number: 002-21414 Rev. *M
Page 18 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Special-Function Peripherals
CapSense
Audio Subsystem
Capacitive touch sensors are designed for user interfaces that
rely on human body capacitance to detect the presence of a
finger on or near a sensor. Cypress CapSense solutions bring
elegant, reliable, and simple capacitive touch sensing functions
to applications including IoT, industrial, automotive, and home
appliances.
This subsystem consists of the following hardware blocks:
■
■
One Inter-IC Sound (I2S) interface
Two pulse-density modulation (PDM) to pulse-code modulation
(PCM) decoder channels
The I2S interface implements two independent hardware FIFO
buffers – TX and RX, which can operate in master or slave mode.
The following features are supported:
The Cypress-proprietary CapSense technology offers the
following features:
■
Best-in-class signal-to-noise ratio (SNR) and robust sensing
under harsh and noisy conditions
■
Self-capacitance (CSD) and mutual-capacitance (CSX)
sensing methods
■
Support for various widgets, including buttons, matrix buttons,
sliders, touchpads, and proximity sensors
■
High-performance sensing across a variety of materials
■
Best-in-class liquid tolerance
The I2S interface is commonly used to connect with audio
codecs, simple DACs, and digital microphones.
■
SmartSense auto-tuning technology that helps avoid complex
manual tuning processes
The PDM-to-PCM decoder implements a single hardware Rx
FIFO that decodes a stereo or mono 1-bit PDM input stream to
PCM data output. The following features are supported:
■
Superior immunity against external noise
■
Spread-spectrum clocks for low radiated emissions
■
Gesture and built-in self-test libraries
■
Ultra-low power consumption
■
An integrated graphical CapSense tuner for real-time tuning,
testing, and debugging
■
Multiple data formats – I2S, left-justified, Time Division Multiplexed (TDM) mode A, and TDM mode B
■
Programmable channel/word lengths – 8/16/18/20/24/32 bits
■
Internal/external clock operation. Up to 192 ksps
■
Interrupt mask events – trigger, not empty, full, overflow,
underflow, watchdog
■
Configurable FIFO trigger level with DMA support
■
Programmable data output word length – 16/18/20/24 bits
■
Programmable gain amplifier (PGA) for volume control – from
–12 dB to +10.5 dB in 1.5 dB steps
■
Configurable PDM clock generation. Range from 384 kHz to
3.072 MHz
■
Droop correction and configurable decimation rate for
sampling; up to 48 ksps
■
Programmable high-pass filter gain
■
Interrupt mask events – not empty, overflow, trigger, underflow
■
Configurable FIFO trigger level with DMA support
The PDM-to-PCM decoder is commonly used to connect to
digital PDM microphones. Up to two microphones can be
connected to the same PDM Data line.
CapSense Subsystem
CapSense is supported in PSoC 6 MCU through a CapSense
sigma-delta (CSD) hardware block. It is designed for
high-sensitivity self-capacitance and mutual-capacitance
measurements, and is specifically built for user interface
solutions.
In addition to CapSense, the CSD hardware block supports three
general-purpose functions. These are available when CapSense
is not being used. Alternatively, two or more functions can be
time-multiplexed in an application under firmware control. The
four functions supported by the CSD hardware block are:
■
CapSense
■
10-bit ADC
■
Programmable current sources (IDAC)
■
Comparator
Document Number: 002-21414 Rev. *M
CapSense sensitivity and accuracy are affected by GPIO
switching noise. To improve sensitivity and accuracy, implement
the GPIO port restrictions listed in Table 6, and do the following:
■
Restrict CapSense pins to ports 6 and 7
■
There should be no other GPIO output activity on ports 6 and 7
■
There should be no more than two GPIO outputs on ports 5
and 8
■
Restrict GPIO output switching in ports 5 and 8 to 1 MHz, with
slow slew rate setting
ADC
The CapSense subsystem slope ADC offers the following
features:
■
Selectable 8- or 10-bit resolution
■
Selectable input range: GND to VREF and GND to VDDA on any
GPIO input
■
Measurement of VDDA against an internal reference without the
use of GPIO or external components
IDAC
The CSD block has two programmable current sources, which
offer the following features:
■
7-bit resolution
■
Sink and source current modes
■
A current source programmable from 37.5 nA to 609 A
■
Two IDACs that can be used in parallel to form one 8-bit IDAC
Page 19 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Comparator
The CapSense subsystem comparator operates in the system
Low Power and Ultra-Low Power modes. The inverting input is
connected to an internal programmable reference voltage and
the non-inverting input can be connected to any GPIO via the
AMUXBUS.
CapSense Hardware Subsystem
Figure 9 shows the high-level hardware overview of the
CapSense subsystem, which includes a delta sigma converter,
internal clock dividers, a shield driver, and two programmable
current sources.
The inputs are managed through analog multiplexed buses
(AMUXBUS A/B). The input and output of all functions offered by
the CSD block can be provided on any GPIO or on a group of
GPIOs under software control, with the exception of the
comparator output and external capacitors that use dedicated
GPIOs.
Self-capacitance is supported by the CSD block using
AMUXBUS A, an external modulator capacitor, and a GPIO for
each sensor. There is a shield electrode (optional) for
self-capacitance sensing. This is supported using AMUXBUS B
and an optional external shield tank capacitor (to increase the
drive capability of the shield driver) should this be required.
Mutual-capacitance is supported by the CSD block using
AMUXBUS A, two external integrated capacitors, and a GPIO for
transmit and receive electrodes.
The ADC does not require an external component. Any GPIO
that can be connected to AMUXBUS A can be an input to the
ADC under software control. The ADC can accept VDDA as an
input without needing GPIOs (for applications such as battery
voltage measurement).
The two programmable current sources (IDACs) in
general-purpose mode can be connected to AMUXBUS A or B.
They can therefore connect to any GPIO pin. The comparator
resides in the delta-sigma converter. The comparator inverting
input can be connected to the reference. Both comparator inputs
can be connected to any GPIO using AMUXBUS B; see
Figure 9. The reference has a direct connection to a dedicated
GPIO; see Table 9.
The CSD block can operate in active and sleep CPU power
modes, and seamlessly transition between system LP and ULP
modes. It can be powered down in system Deep Sleep and
Hibernate modes. Upon wakeup from Hibernate mode, the CSD
block requires re-initialization. However, operation can be
resumed without re-initialization upon exit from Deep Sleep
mode, under firmware control.
Figure 9. CapSense Hardware Subsystem
AMUXBUS
A
B
GPIO Pin
CSD Sensor 1
GPIO
Cell
Clock Input
CS1
I / O Configured for CSD Mode
GPIO Pin
GPIO
Cell
CSD Sensor 2
CS2
CSD Hardware Block
CMOD Pin
C MOD
C
SH_TANK
Sense clock
Clock
Generator
GPIO Pin
( optional )
Shield Drive
Circuit
GPIO Pin
Modulator
Clock
GPIO
Cell
Compensation
IDAC
C SHIELD
Shield Electrode
Modulator
IDAC
GPIO Pin
Tx
CSX Sensor 3
IDAC control
GPIO
Cell
I / O Configured for CSX Mode
CS3
Rx
GPIO Pin
C INTA Pin
CINT
A
I / O for General Purpose
Mode
CINT
B
Document Number: 002-21414 Rev. *M
CINTB Pin
GPIO
Cell
Sigma Delta
Converter
Raw
Count
V REF
GPIO
Cell
GPIO
Cell
ADC Input
IDAC Outputs
Comp Input
Page 20 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Figure 10 shows the high-level software overview. Cypress
provides middleware libraries for CapSense, ADC, and IDAC on
GitHub to enable quick integration. The Board Support Package
for any kit with CapSense capabilities automatically includes the
CapSense library in any application that uses the BSP.
User applications interact only with middleware to implement
functions of the CSD block. The middleware interacts with
underlying drivers to access hardware as necessary. The CSD
driver facilitates time-multiplexing of the CSD hardware if more
than one piece of CSD-related middleware is present in a project.
It prevents access conflicts in this case.
ModusToolbox Software provides a CapSense configurator to
enable fast library configuration. It also provides a tuner for
performance evaluation and real-time tuning of the system. The
tuner requires an EZI2C communication interface in the
application to enable real-time tuning capability. The tuner can
update configuration parameters directly in the device as well as
in the configurator.
CapSense and ADC middleware use the CSD interrupt to
implement non-blocking sensing and A-to-D conversion.
Therefore, interrupt service routines are a defined part of the
middleware, which must be initialized by the application.
Middleware and drivers can operate on either CPU. Cypress
recommends using the middleware only in one CPU. If both
CPUs must access the CSD driver, memory access should be
managed in the application.
Refer to AN85951: PSoC 4 and PSoC 6 MCU CapSense Design
Guide for more details on CSX sensing, CSD sensing, shield
electrode usage and its benefits, and capacitive system design
guidelines.
Refer to the API reference guides for CapSense, ADC, and IDAC
available on GitHub.
Figure 10. CapSense Software/Firmware Subsystem
Application Program
Software
Middleware
Comp
IDAC
ADC
CapSense
Configurator
Tuner
SCB Driver
(EZI2C)
CSD Driver
GPIO / Clock
Drivers
SCB
CSD Block
GPIOs / Clock
Hardware and Drivers
Document Number: 002-21414 Rev. *M
Page 21 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Pinouts
Note: The CY8C61x6/CY8C61x7 datasheet web page contains a spreadsheet with a consolidated list of pinouts and pin alternate
functions with HSIOM mapping.
GPIO ports are powered by VDDx pins as follows:
■
P0: VBACKUP
■
P1: VDDD. Port 1 pins are overvoltage tolerant (OVT).
■
P2, P3, P4: VDDIO2
■
P5, P6, P7, P8: VDDIO1
■
P9, P10: VDDIOA, VDDA (VDDIOA, when present, and VDDA must be connected together on the PCB)
■
P11, P12, P13: VDDIO0
■
P14: VDDUSB
Table 7. Packages and Pin Information
Pin
VDDD
VCCD
VDDA
VDDIOA
VDDIO0
VDDIO1
VDDIO2
VBACKUP
VDDUSB
VSS
VDD_NS
VIND1
VIND2
VBUCK1
VRF
XRES
VREF
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P2.0
Packages
124-BGA
A1
A2
A12
A13
C4
K12
L4
D1
M1
B12, C3, D4,
D10, K4, K10
80-WLCSP
B11
A10
F1
A6
M1
D11
P11
A8, D1, P5, R8
J1
J2
K2
K3
K1
F1
B13
E3
E2
E1
F3
F2
G3
G2
G1
H3
H2
H1
J3
M2
Document Number: 002-21414 Rev. *M
Pin
Packages
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
P3.1
P3.2
124-BGA
N2
L3
M3
N3
N1
M4
N4
L5
M5
N5
80-WLCSP
-
K11
L10
M11
N10
G10
P3.3
P3.4
P3.5
P4.0
P4.1
L6
M6
N6
L7
M7
-
P5.0
N7
M9
C10
D9
E10
F9
G8
F11
H11
H9
K9
J10
-
P5.1
P5.2
P5.3
P5.4
P5.5
P5.6
P5.7
P6.0
P6.1
P6.2
P6.3
P6.4
P6.5
P6.6
L8
M8
N8
L9
M9
N9
N10
M10
L10
L11
M11
N11
M12
N12
N8
R6
P7
L8
M7
R4
N6
J8
K7
L6
R2
P3
N4
M5
Page 22 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Table 7. Packages and Pin Information (continued)
Pin
Packages
124-BGA
80-WLCSP
P6.7
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
M13
L13
L12
K13
N13
K11
J13
J12
J11
J6
N2
M3
L4
K5
L2
P8.0
P8.1
H13
H12
H3
K1
P8.2
P8.3
P8.4
P8.5
P8.6
P8.7
P9.0
P9.1
P9.2
P9.3
P9.4
P9.5
P9.6
P9.7
P10.0
P10.1
P10.2
H11
G13
G12
G11
F13
F12
E11
E12
E13
F11
D13
D12
D11
C13
C12
A11
B11
K3
J4
J2
H1
G2
E2
C2
F3
A2
G4
H5
-
P10.3
P10.4
C11
A10
B3
Document Number: 002-21414 Rev. *M
Pin
Packages
124-BGA
80-WLCSP
P10.5
P10.6
P10.7
P11.0
P11.1
P11.2
P11.3
P11.4
B10
C10
A9
B9
C9
A8
B8
C8
D3
E4
F5
G6
A4
C4
P11.5
P11.6
A7
B7
B5
D5
P11.7
P12.0
P12.1
P12.2
P12.3
P12.4
P12.5
P12.6
P12.7
P13.0
P13.1
P13.2
P13.3
P13.4
P13.5
P13.6
P13.7
C7
A6
B6
C6
A5
B5
C5
A4
B4
B1
A3
B3
B2
C2
C1
D3
D2
C6
B7
D7
C8
B9
E6
E8
F7
H7
-
P14.0 / USBDP
P14.1 / USBDM
L2
L1
R10
P9
Page 23 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Each Port Pin has multiple alternate functions. These are defined in Table 8.
Table 8. Multiple Alternate Functions[1]
Port/
Pin
ACT #0
ACT #1
DS #2
ACT #4 ACT #5
ACT #6
ACT #7
srss.ext
_clk:0
ACT #8
ACT #9
ACT #10
ACT #12
peri.tr_io_i
nput[0]:0
scb[0].spi
_select2:0
peri.tr_io_i
nput[1]:0
ACT #14
ACT #15
DS #4
P0.0
tcpwm[0].l tcpwm[1].line
ine[0]:0
[0]:0
P0.1
tcpwm[0].l
tcpwm[1].line
ine_comp
_compl[0]:0
l[0]:0
P0.2
tcpwm[0].l tcpwm[1].line
ine[1]:0
[1]:0
scb[0].ua scb[0].i2
rt_rx:0
c_scl:0
scb[0].spi
_mosi:0
P0.3
tcpwm[0].l
tcpwm[1].line
ine_comp
_compl[1]:0
l[1]:0
scb[0].ua scb[0].i2
rt_tx:0
c_sda:0
scb[0].spi
_miso:0
P0.4
tcpwm[0].l tcpwm[1].line
ine[2]:0
[2]:0
scb[0].ua
rt_rts:0
scb[0].spi
_clk:0
peri.tr_io_
output[0]:2
P0.5
tcpwm[0].l
tcpwm[1].line
ine_comp
_compl[2]:0
l[2]:0
scb[0].ua
rt_cts:0
scb[0].spi
_select0:0
peri.tr_io_
output[1]:2
P1.0
tcpwm[0].l tcpwm[1].line
ine[3]:0
[3]:0
scb[7].ua scb[7].i2
rt_rx:0
c_scl:0
scb[7].spi
_mosi:0
peri.tr_io_i
nput[2]:0
P1.1
tcpwm[0].l
tcpwm[1].line
ine_comp
_compl[3]:0
l[3]:0
scb[7].ua scb[7].i2
rt_tx:0
c_sda:0
scb[7].spi
_miso:0
peri.tr_io_i
nput[3]:0
P1.2
tcpwm[0].l tcpwm[1].line
ine[4]:4
[12]:1
scb[7].ua
rt_rts:0
scb[7].spi
_clk:0
P1.3
tcpwm[0].l
tcpwm[1].line
ine_comp
_compl[12]:1
l[4]:4
scb[7].ua
rt_cts:0
scb[7].spi
_select0:0
P1.4
tcpwm[0].l tcpwm[1].line
ine[5]:4
[13]:1
scb[7].spi
_select1:0
P1.5
tcpwm[0].l
tcpwm[1].line
ine_comp
_compl[14]:1
l[5]:4
scb[7].spi
_select2:0
P2.0
tcpwm[0]. tcpwm[1].line
line[6]:4
[15]:1
scb[1].ua scb[1].i2
rt_rx:0
c_scl:0
scb[1].spi
_mosi:0
peri.tr_io_i
n put[4]:0
bless.mxd_dpslp_ret_switch_h
v
P2.1
tcpwm[0].l
tcpwm[1].line
ine_-com
_compl[15]:1
pl[
scb[1].ua scb[1].i2
rt_tx:0
c_sda:0
scb[1].spi
_miso:0
peri.tr_io_i
nput[5]:0
bless.mxd_dpslp_ret_ldo_ol_h
v
srss.ext
_clk:1
scb[0].spi
_select1:0
ACT #13
DS #5
DS #6
cpuss.swj_
trstn
Note
1. The notation for a signal is of the form IPName[x].signal_name[u]:y.
IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates
copies of the signal name.
For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal
copies are provided to allow flexibility in routing and to maximize utilization of on-chip resources.
Document Number: 002-21414 Rev. *M
Page 24 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Table 8. Multiple Alternate Functions[1] (continued)
Port/
Pin
ACT #0
ACT #1
DS #2
ACT #4 ACT #5
ACT #6
ACT #7
ACT #8
ACT #9
ACT #10
ACT #12
ACT #13
ACT #14
ACT #15
DS #4
P2.2
tcpwm[0].l tcpwm[1].line
ine[7]:4
[16]:1
scb[1].ua
rt_rts:0
scb[1].spi
_clk:0
bless.mxd_dpslp_-buck_en
P2.3
tcpwm[0].l
tcpwm[1].line
ine_-com
_compl[16]:1
pl[7]:4
scb[1].ua
rt_cts:0
scb[1].spi
_select0:0
bless.mxd_dpslp_reset_n
P2.4
tcpwm[0].l tcpwm[1].line
ine[0]:5
[17]:1
scb[1].spi
_select1:0
bless.mxd_dpslp_-clk_en
P2.5
tcpwm[0].l
tcpwm[1].line
ine_-com
_compl[17]:1
pl[0]:5
scb[1].spi
_select2:0
bless.mxd_dpslp_isolate_n
P2.6
tcpwm[0].l tcpwm[1].line
ine[1]:5
[18]:1
scb[1].spi
_select3:0
bless.mxd_dpslp_act_ldo_en
P2.7
tcpwm[0].l
tcpwm[1].line
ine_-com
_compl[18]:1
pl[1]:5
P3.0
tcpwm[0]. tcpwm[1].line
line[2]:5
[19]:1
scb[2].ua scb[2].i2
rt_rx:1
c_scl:1
scb[2].spi
_mosi:1
peri.tr_io_i
nput[6]:0
P3.1
tcpwm[0].
line_tcpwm[1].line
compl[2]: _compl[19]:1
5
scb[2].ua scb[2].i2
rt_tx:1
c_sda:1
scb[2].spi
_miso:1
peri.tr_io_i
nput[7]:0
P3.2
tcpwm[0]. tcpwm[1].line
line[3]:5
[20]:1
scb[2].ua
rt_rts:1
scb[2].spi
_clk:1
bless.mxd_act
_dbus_tx_en
P3.3
tcpwm[0].
line_tcpwm[1].line
compl[3]: _compl[20]:1
5
scb[2].ua
rt_cts:1
scb[2].spi
_select0:1
bless.mxd_act
_bpktctl
P3.4
tcpwm[0]. tcpwm[1].line
line[4]:5
[21]:1
scb[2].spi
_select1:1
bless.mxd_act
_txd_rxd
P3.5
tcpwm[0].
line_tcpwm[1].line
compl[4]: _compl[21]:1
5
scb[2].spi
_select2:1
bless.mxd_dpslp_rcb_data
P4.0
tcpwm[0]. tcpwm[1].line
line[5]:5
[22]:1
scb[7].ua scb[7].i2
rt_rx:1
c_scl:1
scb[7].spi
_mosi:1
peri.tr_io_i
nput[8]:0
bless.mxd_dpslp_rcb_clk
P4.1
tcpwm[0].
line_tcpwm[1].line
compl[5]: _compl[22]:1
5
scb[7].ua scb[7].i2
rt_tx:1
c_sda:1
scb[7].spi
_miso:1
peri.tr_io_i
nput[9]:0
bless.mxd_dpslp_rcb_le
P5.0
tcpwm[0]. tcpwm[1].line
line[4]:0
[4]:0
scb[5].ua scb[5].i2
rt_rx:0
c_scl:0
scb[5].spi
_mosi:0
audioss.clk peri.tr_io_i
_i2s_if
nput[10]:0
DS #5
DS #6
bless.mxd_dpslp_xtal_en
bless.mxd_dpslp_dig_ldo_en
bless.mxd_act
_dbus_rx_en
Note
1. The notation for a signal is of the form IPName[x].signal_name[u]:y.
IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates
copies of the signal name.
For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal
copies are provided to allow flexibility in routing and to maximize utilization of on-chip resources.
Document Number: 002-21414 Rev. *M
Page 25 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Table 8. Multiple Alternate Functions[1] (continued)
Port/
Pin
ACT #0
ACT #1
DS #2
ACT #4 ACT #5
ACT #6
ACT #7
ACT #8
ACT #9
ACT #10
ACT #12
ACT #13
ACT #14
ACT #15
DS #4
DS #5
DS #6
P5.1
tcpwm[0].
line_tcpwm[1].line
compl[4]: _compl[4]:0
0
scb[5].ua scb[5].i2
rt_tx:0
c_sda:0
scb[5].spi
_miso:0
audioss.tx peri.tr_io_i
_sck
nput[11]:0
P5.2
tcpwm[0]. tcpwm[1].line
line[5]:0
[5]:0
scb[5].ua
rt_rts:0
scb[5].spi
_clk:0
audioss.tx
_ws
P5.3
tcpwm[0].
line_tcpwm[1].line
compl[5]: _compl[5]:0
0
scb[5].ua
rt_cts:0
scb[5].spi
_select0:0
audioss.tx
_sdo
P5.4
tcpwm[0]. tcpwm[1].line
line[6]:0
[6]:0
scb[5].spi
_select1:0
audioss.rx
_sck
P5.5
tcpwm[0].
line_tcpwm[1].line
compl[6]: _compl[6]:0
0
scb[5].spi
_select2:0
audioss.rx
_ws
P5.6
tcpwm[0]. tcpwm[1].line
line[7]:0
[7]:0
scb[5].spi
_select3:0
audioss.rx
_sdi
P5.7
tcpwm[0].
line_tcpwm[1].line
compl[7]: _compl[7]:0
0
scb[3].spi
_select3:0
P6.0
tcpwm[0]. tcpwm[1].line scb[8].i2
line[0]:1
[8]:0
c_scl:0
scb[3].ua scb[3].i2
rt_rx:0
c_scl:0
scb[3].spi
_mosi:0
cpuss.fault
_out[0]
scb[8].spi
_mosi:0
P6.1
tcpwm[0].
line_tcpwm[1].line scb[8].i2
compl[0]: _compl[8]:0 c_sda:0
1
scb[3].ua scb[3].i2
rt_tx:0
c_sda:0
scb[3].spi
_miso:0
cpuss.fault
_out[1]
scb[8].spi
_miso:0
P6.2
tcpwm[0]. tcpwm[1].line
line[1]:1
[9]:0
scb[3].ua
rt_rts:0
scb[3].spi
_clk:0
scb[8].spi
_clk:0
P6.3
tcpwm[0].
line_tcpwm[1].line
compl[1]: _compl[9]:0
1
scb[3].ua
rt_cts:0
scb[3].spi
_select0:0
scb[8].spi
_select0:0
P6.4
tcpwm[0]. tcpwm[1].line scb[8].i2
line[2]:1
[10]:0
c_scl:1
scb[6].ua scb[6].i2
rt_rx:2
c_scl:2
scb[6].spi
_mosi:2
peri.tr_io_i peri.tr_io_
nput[12]:0 output[0]:1
cpuss.swj_ scb[8].spi
swo_tdo
_mosi:1
P6.5
tcpwm[0].
line_tcpwm[1].line scb[8].i2
compl[2]: _compl[10]:0 c_sda:1
1
scb[6].ua scb[6].i2
rt_tx:2
c_sda:2
scb[6].spi
_miso:2
peri.tr_io_i peri.tr_io_
nput[13]:0 output[1]:1
cpuss.swj_ scb[8].spi
swdoe_tdi
_miso:1
P6.6
tcpwm[0].l tcpwm[1].line
ine[3]:1
[11]:0
scb[6].ua
rt_rts:2
scb[6].spi
_clk:2
cpuss.swj_ scb[8].spi
swdio_tms
_clk:1
Note
1. The notation for a signal is of the form IPName[x].signal_name[u]:y.
IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates
copies of the signal name.
For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal
copies are provided to allow flexibility in routing and to maximize utilization of on-chip resources.
Document Number: 002-21414 Rev. *M
Page 26 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Table 8. Multiple Alternate Functions[1] (continued)
Port/
Pin
ACT #0
ACT #1
DS #2
ACT #4 ACT #5
ACT #6
ACT #7
ACT #8
ACT #9
ACT #10
ACT #12
ACT #13
ACT #14
ACT #15
P6.7
tcpwm[0].l
ine_comp tcpwm[1].line
_compl[11]:0
l[3]:1
scb[6].ua
rt_cts:2
scb[6].spi
_select0:2
P7.0
tcpwm[0].l tcpwm[1].line
ine[4]:1
[12]:0
scb[4].ua scb[4].i2
rt_rx:1
c_scl:1
scb[4].spi
_mosi:1
peri.tr_io_i
nput[14]:0
P7.1
tcpwm[0].l tcpwm[1].line
ine_comp
_compl[12]:0
l[4]:1
scb[4].ua scb[4].i2
rt_tx:1
c_sda:1
scb[4].spi
_miso:1
peri.tr_io_i
nput[15]:0
P7.2
tcpwm[0].l tcpwm[1].line
ine[5]:1
[13]:0
scb[4].ua
rt_rts:1
scb[4].spi
_clk:1
P7.3
tcpwm[0].l tcpwm[1].line
ine_comp
_compl[13]:0
l[5]:1
scb[4].ua
rt_cts:1
scb[4].spi
_select0:1
P7.4
tcpwm[0].l tcpwm[1].line
ine[6]:1
[14]:0
scb[4].spi
_select1:1
bless.ext_lna_rx_ctl_out
P7.5
tcpwm[0].l tcpwm[1].line
ine_comp _compl[14]:0
l[6]:1
scb[4].spi
_select2:1
bless.ext_pa_t cpuss.trac
x_ctl_out
e_data[2]:2
P7.6
tcpwm[0].l tcpwm[1].line
ine[7]:1
[15]:0
scb[4].spi
_select3:1
bless.ext_pa_l- cpuss.trac
na_chip_en_ou e_data[1]:2
t
P7.7
tcpwm[0].l tcpwm[1].line
ine_comp _compl[15]:0
l[7]:1
scb[3].spi cpuss.clk_
_select1:0 fm_pump
P8.0
tcpwm[0].l tcpwm[1].line
ine[0]:2
[16]:0
scb[4].ua scb[4].i2
rt_rx:0
c_scl:0
scb[4].spi
_mosi:0
peri.tr_io_i
nput[16]:0
P8.1
tcpwm[0].l
ine_comp tcpwm[1].line
_compl[16]:0
l[0]:2
scb[4].ua scb[4].i2
rt_tx:0
c_sda:0
scb[4].spi
_miso:0
peri.tr_io_i
nput[17]:0
P8.2
tcpwm[0].l tcpwm[1].line
ine[1]:2
[17]:0
scb[4].ua
rt_rts:0
scb[4].spi
_clk:0
P8.3
tcpwm[0].l tcpwm[1].line
ine_comp _compl[17]:0
l[1]:2
scb[4].ua
rt_cts:0
scb[4].spi
_select0:0
P8.4
tcpwm[0].l tcpwm[1].line
ine[2]:2
[18]:0
scb[4].spi
_select1:0
P8.5
tcpwm[0].l
ine_comp tcpwm[1].line
_compl[18]:0
l[2]:2
scb[4].spi
_select2:0
P8.6
tcpwm[0].l tcpwm[1].line
ine[3]:2
[19]:0
scb[4].spi
_select3:0
DS #4
DS #5
DS #6
cpuss.swj_ scb[8].spi
swclk_tclk _select0:1
cpuss.trace_clock
cpuss.trac
e_data[3]:2
cpuss.trac
e_data[0]:2
Note
1. The notation for a signal is of the form IPName[x].signal_name[u]:y.
IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates
copies of the signal name.
For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal
copies are provided to allow flexibility in routing and to maximize utilization of on-chip resources.
Document Number: 002-21414 Rev. *M
Page 27 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Table 8. Multiple Alternate Functions[1] (continued)
Port/
Pin
ACT #0
ACT #1
DS #2
ACT #4 ACT #5
ACT #6
ACT #7
ACT #8
ACT #9
ACT #10
ACT #12
ACT #13
ACT #14
ACT #15
P8.7
tcpwm[0].l
ine_comp tcpwm[1].line
_compl[19]:0
l[3]:2
P9.0
tcpwm[0].l tcpwm[1].line
ine[4]:2
[20]:0
scb[2].ua scb[2].i2
rt_rx:0
c_scl:0
scb[2].spi
_mosi:0
peri.tr_io_i
nput[18]:0
cpuss.trac
e_data[3]:0
P9.1
tcpwm[0].l tcpwm[1].line
ine_comp
_compl[20]:0
l[4]:2
scb[2].ua scb[2].i2
rt_tx:0
c_sda:0
scb[2].spi
_miso:0
peri.tr_io_i
nput[19]:0
cpuss.trac
e_data[2]:0
P9.2
tcpwm[0].l tcpwm[1].line
ine[5]:2
[21]:0
scb[2].ua
rt_rts:0
scb[2].spi
_clk:0
pass.dsi_ct
b_cmp0:1
cpuss.trac
e_data[1]:0
P9.3
tcpwm[0].l tcpwm[1].line
ine_comp
_compl[21]:0
l[5]:2
scb[2].ua
rt_cts:0
scb[2].spi
_select0:0
pass.dsi_ct
b_cmp1:1
cpuss.trac
e_data[0]:0
P9.4
tcpwm[0].l tcpwm[1].line
ine[7]:5
[0]:2
scb[2].spi
_select1:0
P9.5
tcpwm[0].l tcpwm[1].line
ine_comp _compl[0]:2
l[7]:5
scb[2].spi
_select2:0
P9.6
tcpwm[0].l tcpwm[1].line
ine[0]:6
[1]:2
scb[2].spi
_select3:0
P9.7
tcpwm[0].l
ine_comp tcpwm[1].line
_compl[1]:2
l[0]:6
P10.0
tcpwm[0].l tcpwm[1].line
ine[6]:2
[22]:0
scb[1].ua scb[1].i2
rt_rx:1
c_scl:1
scb[1].spi
_mosi:1
peri.tr_io_i
nput[20]:0
cpuss.trac
e_data[3]:1
tcpwm[0].l
P10.1 ine_comp tcpwm[1].line
_compl[22]:0
l[6]:2
scb[1].ua scb[1].i2
rt_tx:1
c_sda:1
scb[1].spi
_miso:1
peri.tr_io_i
nput[21]:0
cpuss.trac
e_data[2]:1
P10.2 tcpwm[0].l tcpwm[1].line
ine[7]:2
[23]:0
scb[1].ua
rt_rts:1
scb[1].spi
_clk:1
cpuss.trac
e_data[1]:1
tcpwm[0].l
P10.3 ine_comp tcpwm[1].line
_compl[23]:0
l[7]:2
scb[1].ua
rt_cts:1
scb[1].spi
_select0:1
cpuss.trac
e_data[0]:1
DS #5
DS #6
scb[3].spi
_select2:0
tcpwm[0].l tcpwm[1].line
ine[0]:3
[0]:1
scb[1].spi audioss.p
_select1:1 dm_clk
tcpwm[0].l
P10.5 ine_comp tcpwm[1].line
_compl[0]:1
l[0]:3
scb[1].spi audioss.p
_select2:1 dm_data
tcpwm[1].line
P10.6 tcpwm[0].l
ine[1]:6
[2]:2
scb[1].spi
_select3:1
P10.4
DS #4
Note
1. The notation for a signal is of the form IPName[x].signal_name[u]:y.
IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates
copies of the signal name.
For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal
copies are provided to allow flexibility in routing and to maximize utilization of on-chip resources.
Document Number: 002-21414 Rev. *M
Page 28 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Table 8. Multiple Alternate Functions[1] (continued)
Port/
Pin
ACT #0
ACT #1
DS #2
ACT #4 ACT #5
ACT #6
ACT #7
ACT #8
ACT #9
ACT #10
ACT #12
ACT #13
ACT #14
ACT #15
DS #4
DS #5
DS #6
tcpwm[0].l
P10.7 ine_comp tcpwm[1].line
_compl[2]:2
l[1]:6
P11.0
tcpwm[0].l tcpwm[1].line
ine[1]:3
[1]:1
smif.spi_ scb[5].ua scb[5].i2
select2
rt_rx:1
c_scl:1
scb[5].spi
_mosi:1
peri.tr_io_i
nput[22]:0
P11.1
tcpwm[0].l tcpwm[1].line
ine_comp
_compl[1]:1
l[1]:3
smif.spi_ scb[5].ua scb[5].i2
select1
rt_tx:1
c_sda:1
scb[5].spi
_miso:1
peri.tr_io_i
nput[23]:0
P11.2 tcpwm[0].l tcpwm[1].line
ine[2]:3
[2]:1
smif.spi_ scb[5].ua
select0
rt_rts:1
scb[5].spi
_clk:1
P11.3
tcpwm[0].l tcpwm[1].line
ine_comp _compl[2]:1
l[2]:3
smif.spi_ scb[5].ua
data3
rt_cts:1
scb[5].spi
_select0:1
peri.tr_io_
output[0]:0
P11.4
tcpwm[0].l tcpwm[1].line
ine[3]:3
[3]:1
smif.spi_
data2
scb[5].spi
_select1:1
peri.tr_io_
output[1]:0
P11.5
tcpwm[0].l
ine_comp tcpwm[1].line
_compl[3]:1
l[3]:3
smif.spi_
data1
scb[5].spi
_select2:1
P11.6
smif.spi_
data0
scb[5].spi
_select3:1
P11.7
smif.spi_
clk
P12.0 tcpwm[0].l tcpwm[1].line
ine[4]:3
[4]:1
smif.spi_ scb[6].ua scb[6].i2
data4
rt_rx:0
c_scl:0
scb[6].spi
_mosi:0
peri.tr_io_i
nput[24]:0
tcpwm[0].l
P12.1 ine_comp tcpwm[1].line
_compl[4]:1
l[4]:3
smif.spi_ scb[6].ua scb[6].i2
data5
rt_tx:0
c_sda:0
scb[6].spi
_miso:0
peri.tr_io_i
nput[25]:0
tcpwm[0].l tcpwm[1].line
ine[5]:3
[5]:1
smif.spi_ scb[6].ua
data6
rt_rts:0
scb[6].spi
_clk:0
tcpwm[0].l tcpwm[1].line
P12.3 ine_comp _compl[5]:1
l[5]:3
smif.spi_ scb[6].ua
data7
rt_cts:0
scb[6].spi
_select0:0
P12.4 tcpwm[0].l tcpwm[1].line
ine[6]:3
[6]:1
smif.spi_
select3
scb[6].spi
_select1:0
audioss.p
dm_clk
tcpwm[0].l
P12.5 ine_comp tcpwm[1].line
_compl[6]:1
l[6]:3
scb[6].spi
_select2:0
audioss.p
dm_data
tcpwm[0].l tcpwm[1].line
ine[7]:3
[7]:1
scb[6].spi
_select3:0
P12.2
P12.6
Note
1. The notation for a signal is of the form IPName[x].signal_name[u]:y.
IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates
copies of the signal name.
For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal
copies are provided to allow flexibility in routing and to maximize utilization of on-chip resources.
Document Number: 002-21414 Rev. *M
Page 29 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Table 8. Multiple Alternate Functions[1] (continued)
Port/
Pin
ACT #0
ACT #1
DS #2
ACT #4 ACT #5
ACT #6
ACT #7
ACT #8
ACT #9
ACT #10
ACT #12
ACT #13
ACT #14
ACT #15
DS #4
DS #5
DS #6
tcpwm[0].l
P12.7 ine_comp tcpwm[1].line
_compl[7]:1
l[7]:3
tcpwm[0].l tcpwm[1].line
ine[0]:4
[8]:1
scb[6].ua scb[6].i2
rt_rx:1
c_scl:1
scb[6].spi
_mosi:1
peri.tr_io_i
nput[26]:0
tcpwm[0].l
P13.1 ine_comp tcpwm[1].line
_compl[8]:1
l[0]:4
scb[6].ua scb[6].i2
rt_tx:1
c_sda:1
scb[6].spi
_miso:1
peri.tr_io_i
nput[27]:0
P13.2 tcpwm[0].l tcpwm[1].line
ine[1]:4
[9]:1
scb[6].ua
rt_rts:1
scb[6].spi
_clk:1
tcpwm[0].l tcpwm[1].line
P13.3 ine_comp _compl[9]:1
l[1]:4
scb[6].ua
rt_cts:1
scb[6].spi
_select0:1
P13.0
tcpwm[0].l tcpwm[1].line
ine[2]:4
[10]:1
scb[6].spi
_select1:1
tcpwm[0].l
P13.5 ine_comp tcpwm[1].line
_compl[10]:1
l[2]:4
scb[6].spi
_select2:1
tcpwm[0].l tcpwm[1].line
ine[3]:4
[11]:1
scb[6].spi
_select3:1
P13.4
P13.6
tcpwm[0].l
P13.7 ine_comp tcpwm[1].line
_compl[11]:1
l[3]:4
Note
1. The notation for a signal is of the form IPName[x].signal_name[u]:y.
IPName = Name of the block (such as tcpwm), x = Unique instance of the IP, Signal_name = Name of the signal, u = Signal number where there are more than one signals for a particular signal name, y = Designates
copies of the signal name.
For example, the name tcpwm[0].line_compl[3]:4 indicates that this is instance 0 of a tcpwm block, the signal is line_compl # 3 (complement of the line output) and this is the fourth occurrence (copy) of the signal. Signal
copies are provided to allow flexibility in routing and to maximize utilization of on-chip resources.
Document Number: 002-21414 Rev. *M
Page 30 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Analog, Smart I/O, and DSI alternate Port Pin functionality is provided in Table 9.
Table 9. Port Pin Analog, Smart I/O, and DSI Functions
Port/Pin
Name
P0.0
P0.0
wco_in
dsi[0].port_if[0]
P0.1
P0.1
wco_out
dsi[0].port_if[1]
P0.2
P0.2
dsi[0].port_if[2]
P0.3
P0.3
dsi[0].port_if[3]
P0.4
P0.4
pmic_wakeup_in
hibernate_wakeup[1]
P0.5
P0.5
pmic_wakeup_out
P1.0
P1.0
dsi[1].port_if[0]
P1.1
P1.1
dsi[1].port_if[1]
P1.2
P1.2
dsi[1].port_if[2]
P1.3
P1.3
P1.4
P1.4
Analog
Digital HV
DSI
SMARTIO
USB
dsi[0].port_if[4]
dsi[0].port_if[5]
dsi[1].port_if[3]
hibernate_wakeup[0]
dsi[1].port_if[4]
P1.5
P1.5
P14.0
USBDP
dsi[1].port_if[5]
P14.1
USBDM
P2.0
P2.0
dsi[2].port_if[0]
P2.1
P2.1
dsi[2].port_if[1]
P2.2
P2.2
dsi[2].port_if[2]
P2.3
P2.3
dsi[2].port_if[3]
P2.4
P2.4
dsi[2].port_if[4]
P2.5
P2.5
dsi[2].port_if[5]
P2.6
P2.6
dsi[2].port_if[6]
P2.7
P2.7
dsi[2].port_if[7]
P3.0
P3.0
P3.1
P3.1
P3.2
P3.2
P3.3
P3.3
P3.4
P3.4
usb.usb_dp_pad
usb.usb_dm_pad
P3.5
P3.5
P4.0
P4.0
dsi[0].port_if[6]
P4.1
P4.1
dsi[0].port_if[7]
P4.2
P4.2
dsi[1].port_if[6]
P4.3
P4.3
dsi[1].port_if[7]
P5.0
P5.0
dsi[3].port_if[0]
P5.1
P5.1
dsi[3].port_if[1]
P5.2
P5.2
dsi[3].port_if[2]
P5.3
P5.3
dsi[3].port_if[3]
P5.4
P5.4
dsi[3].port_if[4]
P5.5
P5.5
P5.6
P5.6
lpcomp.inp_comp0
dsi[3].port_if[6]
P5.7
P5.7
lpcomp.inn_comp0
dsi[3].port_if[7]
P6.0
P6.0
dsi[3].port_if[5]
Document Number: 002-21414 Rev. *M
dsi[4].port_if[0]
Page 31 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Table 9. Port Pin Analog, Smart I/O, and DSI Functions (continued)
Port/Pin
Name
Analog
Digital HV
DSI
SMARTIO
P6.1
P6.1
P6.2
P6.2
lpcomp.inp_comp1
dsi[4].port_if[2]
P6.3
P6.3
lpcomp.inn_comp1
dsi[4].port_if[3]
P6.4
P6.4
dsi[4].port_if[4]
P6.5
P6.5
dsi[4].port_if[5]
P6.6
P6.6
swd_data
dsi[4].port_if[6]
P6.7
P6.7
swd_clk
dsi[4].port_if[7]
P7.0
P7.0
P7.1
P7.1
csd.cmodpadd
csd.cmodpads
dsi[5].port_if[1]
P7.2
P7.2
csd.csh_tankpadd
csd.csh_tankpads
dsi[5].port_if[2]
P7.3
P7.3
csd.vref_ext
dsi[5].port_if[3]
P7.4
P7.4
dsi[5].port_if[4]
P7.5
P7.5
dsi[5].port_if[5]
P7.6
P7.6
P7.7
P7.7
P8.0
P8.0
dsi[11].port_if[0]
smartio[8].io[0]
P8.1
P8.1
dsi[11].port_if[1]
smartio[8].io[1]
P8.2
P8.2
dsi[11].port_if[2]
smartio[8].io[2]
P8.3
P8.3
dsi[11].port_if[3]
smartio[8].io[3]
P8.4
P8.4
dsi[11].port_if[4]
smartio[8].io[4]
P8.5
P8.5
dsi[11].port_if[5]
smartio[8].io[5]
P8.6
P8.6
dsi[11].port_if[6]
smartio[8].io[6]
P8.7
P8.7
dsi[11].port_if[7]
smartio[8].io[7]
USB
dsi[4].port_if[1]
dsi[5].port_if[0]
dsi[5].port_if[6]
csd.cshieldpads
dsi[5].port_if[7]
P9.0
P9.0
ctb_oa0+
dsi[10].port_if[0]
smartio[9].io[0]
P9.1
P9.1
ctb_oa0-
dsi[10].port_if[1]
smartio[9].io[1]
P9.2
P9.2
ctb_oa0_out
dsi[10].port_if[2]
smartio[9].io[2]
P9.3
P9.3
ctb_oa1_out
dsi[10].port_if[3]
smartio[9].io[3]
P9.4
P9.4
ctb_oa1-
dsi[10].port_if[4]
smartio[9].io[4]
P9.5
P9.5
ctb_oa1+
dsi[10].port_if[5]
smartio[9].io[5]
P9.6
P9.6
ctb_oa0+
dsi[10].port_if[6]
smartio[9].io[6]
P9.7
P9.7
ctb_oa1+
or ext_vref
dsi[10].port_if[7]
smartio[9].io[7]
P10.0
P10.0
sarmux[0]
dsi[9].port_if[0]
P10.1
P10.1
sarmux[1]
dsi[9].port_if[1]
P10.2
P10.2
sarmux[2]
dsi[9].port_if[2]
P10.3
P10.3
sarmux[3]
dsi[9].port_if[3]
P10.4
P10.4
sarmux[4]
dsi[9].port_if[4]
P10.5
P10.5
sarmux[5]
dsi[9].port_if[5]
P10.6
P10.6
sarmux[6]
dsi[9].port_if[6]
P10.7
P10.7
sarmux[7]
dsi[9].port_if[7]
Document Number: 002-21414 Rev. *M
Page 32 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Table 9. Port Pin Analog, Smart I/O, and DSI Functions (continued)
Port/Pin
Name
P11.0
P11.0
dsi[8].port_if[0]
P11.1
P11.1
dsi[8].port_if[1]
P11.2
P11.2
dsi[8].port_if[2]
P11.3
P11.3
dsi[8].port_if[3]
P11.4
P11.4
dsi[8].port_if[4]
P11.5
P11.5
dsi[8].port_if[5]
P11.6
P11.6
dsi[8].port_if[6]
P11.7
P11.7
dsi[8].port_if[7]
P12.0
P12.0
dsi[7].port_if[0]
P12.1
P12.1
dsi[7].port_if[1]
P12.2
P12.2
dsi[7].port_if[2]
P12.3
P12.3
dsi[7].port_if[3]
P12.4
P12.4
dsi[7].port_if[4]
P12.5
P12.5
dsi[7].port_if[5]
P12.6
P12.6
eco_in
dsi[7].port_if[6]
P12.7
P12.7
eco_out
dsi[7].port_if[7]
P13.0
P13.0
dsi[6].port_if[0]
P13.1
P13.1
dsi[6].port_if[1]
P13.2
P13.2
dsi[6].port_if[2]
P13.3
P13.3
dsi[6].port_if[3]
P13.4
P13.4
dsi[6].port_if[4]
P13.5
P13.5
dsi[6].port_if[5]
P13.6
P13.6
dsi[6].port_if[6]
P13.7
P13.7
dsi[6].port_if[7]
Document Number: 002-21414 Rev. *M
Analog
Digital HV
DSI
SMARTIO
USB
Page 33 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Power Supply Considerations
The following power system diagrams show typical connections for power pins for all supported packages, and with and without usage
of the buck regulator.
In these diagrams, the package pin is shown with the pin name, for example "VDDA, A12". For VDDx pins, the I/O port that is powered
by that pin is also shown, for example "VDDD, A1; I/O port P1".
Figure 11. 124-BGA Power Connection Diagram
1.7 to 3.6 V
CY8C61x6/7, 124-BGA package
1 KΩ at
100 MHz
1 KΩ at
100 MHz
1 KΩ at
100 MHz
10 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
10 µF
0.1 µF
VDDD , A1; I/O port P1
VDD_NS, J1
VBACKUP, D1; I/O port P0
V BUCK1, K3
0.1 µF
10 µF
4.7 µF
VDDIO0, C4; I/O ports P11, P12, P13
VCCD , A2
VDDIO1, K12; I/O ports P5, P6, P7, P8
VDDIO2 , L4; I/O ports P2, P3, P4
VIND1, J2
2.2 µH
VDDUSB , M1; I/O port P14
VIND2, K2
V DDA, A12
V RF, K1
0.1 µF
10 µF
V DDIOA, A13; I/O ports P9, P10
B12,C3,D4,D10,K4,K10
V SS
Document Number: 002-21414 Rev. *M
Page 34 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Figure 12. 124-BGA (No Buck) Power Connection Diagram
1.7 to 3.6 V
CY8C61x6/7, 124-BGA package
1 KΩ at
100 MHz
1 KΩ at
100 MHz
10 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
10 µF
0.1 µF
VDDD, A1; I/O port P1
VDD_NS, J1
VBACKUP, D1; I/O port P0
VBUCK1, K3
VDDIO0, C4; I/O ports P11, P12, P13
VCCD, A2
VDDIO1, K12; I/O ports P5, P6, P7, P8
VDDIO2, L4; I/O ports P2, P3, P4
VIND1, J2
VDDUSB, M1; I/O port P14
VIND2, K2
VDDA, A12
4.7 µF
VRF, K1
VDDIOA, A13; I/O ports P9, P10
B12,C3,D4,D10,K4,K10
VSS
Document Number: 002-21414 Rev. *M
Page 35 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Figure 13. 80-WLCSP Power Connection Diagram
1.7 to 3.6 V
CY8C61x6/7, 80-WLCSP package
1 KΩ at
100 MHz
10 µF
0.1 µF
1 µF
0.1 µF
1 µF
1 KΩ at
100 MHz
1 KΩ at
100 MHz
V DDD, B11; I/O port P1
V BACKUP, D11; I/O port P0
0.1 µF
1 µF
0.1 µF
10 µF
0.1 µF
VBUCK1, N10
0.1 µF
10 µF
4.7 µF
V DDIO0, A6; I/O ports P11, P12
0.1 µF
1 µF
VDD_NS, K11
V CCD, A10
V DDIO1, M1; I/O ports P5, P6, P7, P8
V DDUSB, P11; I/O port P14
VIND1, L10
2.2 µH
VDDA , F1; I/O ports P9, P10
V IND2, M11
0.1 µF
A8, D1, P5, R8
VSS
Figure 14. 80-WLCSP (No Buck) Power Connection Diagram
1.7 to 3.6 V
CY8C61x6/7, 80-WLCSP package
1 KΩ at
100 MHz
1 KΩ at
100 MHz
10 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
1 µF
0.1 µF
10 µF
0.1 µF
VDDD, B11; I/O port P1
VDD_NS, K11
VBACKUP, D11; I/O port P0
VBUCK1, N10
VDDIO0, A6; I/O ports P11, P12
VCCD, A10
VDDIO1, M1; I/O ports P5, P6, P7, P8
VDDUSB, P11; I/O port P14
VIND1, L10
VDDA, F1; I/O ports P9, P10
VIND2, M11
4.7 µF
A8, D1, P5, R8
VSS
Document Number: 002-21414 Rev. *M
Page 36 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
There are as many as eight VDDx supply pins, depending on the
package, and multiple VSS ground pins. The power pins are:
■
VDDD: the main digital supply. It powers the low dropout (LDO)
regulators and I/O port 1. .
■
VCCD: the main LDO output. It requires a 4.7-µF capacitor for
regulation. The LDO can be turned off when VCCD is driven
from the switching regulator (see VBUCK1 below). For more
information, see the power system block diagram in the device
technical reference manual (TRM).
■
VDDA: the supply for the analog peripherals. Voltage must be
applied to this pin for correct device initialization and boot up.
■
VDDIOA: the supply for I/O ports 9 and 10. If it is present in the
device package, it must be connected to VDDA.
■
VDDIO0: the supply for I/O ports 11, 12, and 13.
■
VDDIO1: the supply for I/O ports 5, 6, 7, and 8.
■
VDDIO2: the supply for I/O ports 2, 3, and 4.
■
VBACKUP: the supply for the backup domain, which includes the
32-kHz WCO and the RTC. It can be a separate supply as low
as 1.4 V, for battery or supercapacitor backup, as Figure 15
shows. Otherwise it is connected to VDDD. It powers I/O port 0.
Figure 15. Separate Battery Connection to VBACKUP
1.7 to 3.6 V
10 µF
0.1 µF
1 µF
0.1 µF
1.4 to 3.6 V
■
VDDD
VBACKUP
VDDUSB: the supply for the USB peripheral and the USBDP and
USBDM pins. It must be 2.85 V to 3.6 V for USB operation. If
USB is not used, it can be 1.7 V to 3.6 V, and the USB pins can
be used as limited-capability GPIOs on I/O port 14.
Table 10 shows a summary of the I/O port supplies:
Table 10. I/O Port Supplies
Port
Supply
Alternate Supply
0
VBACKUP
VDDD
1
VDDD
-
2, 3, 4
VDDIO2
-
5, 6, 7, 8
VDDIO1
-
9, 10
VDDIOA
VDDA
11, 12, 13
VDDIO0
-
14
VDDUSB
-
Document Number: 002-21414 Rev. *M
Voltage must be applied to the VDDD pin, and the VDDA pin as
noted above, for correct device initialization and operation. If an
I/O port is not being used, applying voltage to the corresponding
VDDx pin is optional.
■
VSS: ground pins for the above supplies. All ground pins should
be connected together to a common ground.
In addition to the LDO regulator, a single input multiple output
(SIMO) switching regulator is included. It provides two regulated
outputs using a single inductor. The regulator pins are:
■
VDD_NS: the regulator supply.
■
VIND1 and VIND2: the inductor and capacitor connections.
■
VBUCK1: the first regulator output. It is typically used to drive
VCCD, see above.
■
VRF: the second regulator output. It is typically not used; the
pin may not be available in some packages.
The various VDD power pins are not connected together on chip.
They can be connected off chip, in one or more separate nets. If
separate power nets are used, they can be isolated from noise
from the other nets using optional ferrite beads, as indicated in
the diagrams.
No external load should be placed on VCCD, VRF, or any of the
switching regulator power pins; whether or not the switching
regulator is used.
There are no power pin sequencing requirements; power
supplies may be brought up in any order. The power
management system holds the device in reset until all power pins
are at the voltage levels required for proper operation.
Note: If a battery is installed on the PCB first, VDDD must be
cycled for at least 50 µs. This prevents premature drain of the
battery during product manufacture and storage.
Bypass capacitors must be connected to a common ground from
the VDDx and other pins, as indicated in the diagrams. Typical
practice for systems in this frequency range is to use a 10-µF or
1-µF capacitor in parallel with a smaller capacitor (0.1 µF, for
example). Note that these are simply rules of thumb and that, for
critical applications, the PCB layout, lead inductance, and the
bypass capacitor parasitic should be simulated for optimal
bypassing.
All capacitors and inductors should be ±20% or better. The
capacitor connected to VIND2 should be 100 nF. The
recommended inductor value is 2.2 µH ±20% (for example, TDK
MLP2012H2R2MT0S1).
It is good practice to check the datasheets for your bypass
capacitors, specifically the working voltage and the DC bias
specifications. With some capacitors, the actual capacitance can
decrease considerably when the applied voltage is a significant
percentage of the rated working voltage.
For more information on pad layout, refer to PSoC 6 CAD
libraries.
Page 37 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Electrical Specifications
All specifications are valid for –40 °C ≤ TA ≤ 85 °C and for 1.71 V to 3.6 V except where noted.
Absolute Maximum Ratings
Table 11. Absolute Maximum Ratings[2]
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
SID1
VDD_ABS
Analog or digital supply relative to VSS
(VSSD = VSSA)
–0.5
–
4
V
SID2
VCCD_ABS
Direct digital core voltage input
relative to VSSD
–0.5
–
1.2
V
SID3
VGPIO_ABS
GPIO voltage; VDDD or VDDA
–0.5
–
VDD + 0.5
V
SID4
IGPIO_ABS
Current per GPIO
–25
–
25
mA
SID5
IGPIO_injection
GPIO injection current per pin
–0.5
–
0.5
mA
SID3A
ESD_HBM
Electrostatic discharge Human Body
Model
2200
–
–
V
SID4A
ESD_CDM
Electrostatic discharge Charged
Device Model
500
–
–
V
SID5A
LU
Pin current for latchup-free operation
–100
–
100
mA
Details / Conditions
Device-Level Specifications
Table 14 provides detailed specifications of CPU current. Table 12 summarizes these specifications, for rapid review of CPU currents
under common conditions. Note that the max frequency for CM4 is 150 MHz, and for CM0+ is 100 MHz. IMO and FLL are used to
generate the CPU clocks; FLL is not used when the CPU clock frequency is 8 MHz.
Table 12. CPU Current Specifications Summary
Condition
Range
Typ Range
Max Range
0.9–6.3 mA
0.8–3.8 mA
0.7–1.5 mA
0.7–1.3 mA
0.6–0.7 mA
1.5–7 mA
1.3–4.5 mA
1.3–2.2 mA
1.3–2 mA
1.1–1.1 mA
0.65–1.6 mA
0.51–0.91 mA
0.42–0.76 mA
0.41–0.62 mA
0.39–0.54 mA
7–9 µA
300–800 nA
0.8–2.2mA
0.72–1.25 mA
0.65–1.1 mA
0.6–0.9 mA
0.6–0.76 mA
-
LP Mode, VDDD = 3.3 V, VCCD = 1.1 V, with buck regulator
CM4 active, CM0+ sleep
CM0+ active, CM4 sleep
CM4 sleep, CM0+ sleep
Across CPUs clock ranges: 8–150/100 MHz; Dhrystone
with flash cache enabled
CM0+ sleep, CM4 off
Minimum regulator current mode
Across CM4/CM0+ CPU active/sleep modes
ULP Mode, VDDD = 3.3 V, VCCD = 0.9 V, with buck regulator
CM4 active, CM0+ sleep
CM0+ active, CM4 sleep
CM4 sleep, CM0+ sleep
Across CPUs clock ranges: 8 – 50/25 MHz; Dhrystone
with flash cache enabled
CM0+ sleep, CM4 off
Minimum regulator current mode
Across CM4/CM0+ CPU active/sleep modes
Deep Sleep
Across SRAM retention
Hibernate
Across VDDD
Note
2. Usage above the absolute maximum conditions listed in Table 11 may cause permanent damage to the device. Exposure to absolute maximum conditions for extended
periods of time may affect device reliability. The maximum storage temperature is 150 °C in compliance with JEDEC Standard JESD22-A103, High Temperature
Storage Life. When used below absolute maximum conditions but above normal operating conditions, the device may not operate to specification.
Document Number: 002-21414 Rev. *M
Page 38 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Figure 16. Typical Device Currents vs. CPU Frequency; System Low Power (LP) Mode
7
CM4 Active, CM0+ Sleep 1/2 CM4
6
CM4 Active, CM0+ Sleep same as CM4
CM0+ Active, CM4 Sleep
IDDD, mA
5
4
3
2
1
0
0
25
50
75
100
125
150
CPU Clock, MHz
Power Supplies
Table 13. Power Supply DC Specifications
Spec ID# Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
SID6
VDDD
Internal regulator and Port 1 GPIO
supply
1.7
–
3.6
V
–
SID7
VDDA
Analog power supply voltage.
Shorted to VDDIOA on PCB.
1.7
–
3.6
V
Internally unregulated supply
SID7A
VDDIO1
GPIO supply for ports 5 to 8 when
present
1.7
–
3.6
V
Must be ≥ VDDA.
SID7B
VDDIO0
GPIO supply for ports 11 to 13
when present
1.7
–
3.6
V
–
SID7E
VDDIO0
Supply for eFuse programming
2.38
2.5
2.62
V
SID7C
VDDIO2
GPIO supply for ports 2 to 4 when
present
1.7
–
3.6
V
–
SID7D
VDDIOA
GPIO supply for ports 9 and 10
when present. Must be connected
to VDDA on PCB.
1.7
–
3.6
V
–
SID7F
VDDUSB
Supply for port 14 (USB or GPIO)
when present
1.7
–
3.6
V
Min. supply is 2.85 V for USB
SID6B
VBACKUP
Backup power and GPIO Port 0
supply when present
1.7
–
3.6
V
Min. is 1.4 V when VDDD is removed.
SID8
VCCD1
Output voltage (for core logic
bypass)
–
1.1
–
V
System LP mode
SID9
VCCD2
Output voltage (for core logic
bypass)
–
0.9
–
V
ULP mode. Valid for –20 to 85 °C.
SID10
CEFC
External regulator voltage (VCCD)
bypass
3.8
4.7
5.6
µF
X5R ceramic or better;
Value for 0.8 to 1.2 V.
SID11
CEXC
Power supply decoupling capacitor
–
10
–
µF
X5R ceramic or better
Document Number: 002-21414 Rev. *M
Page 39 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
CPU Current and Transition Times
Table 14. CPU Current and Transition Times
Spec ID# Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
LP RANGE POWER SPECIFICATIONS (for VCCD = 1.1 V with Buck and LDO)
Cortex M4. Active Mode
Execute with Cache Disabled (Flash)
SIDF1
SIDF2
IDD1
IDD2
Execute from Flash; CM4 Active
50 MHz,
CM0+ Sleep 25 MHz.
With IMO & FLL. While(1).
Execute from Flash; CM4 Active
8 MHz, CM0+ Sleep 8 MHz. With
IMO. While(1).
–
2.3
3.2
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
3.1
3.6
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
–
5.7
6.5
mA
VDDD = 1.8 to 3.3 V, LDO, Max at 85 °C
–
0.9
1.5
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
1.2
1.6
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
–
2.8
3.5
mA
VDDD = 1.8 to 3.3 V, LDO, Max at 85 °C
–
6.3
7
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
Execute with Cache Enabled
SIDC1
SIDC2
SIDC3
SIDC4
IDD3
IDD4
IDD5
IDD6
Execute from Cache; CM4 Active
150 MHz, CM0+ Sleep 75 MHz.
IMO & FLL. Dhrystone.
Execute from Cache;
CM4 Active 100 MHz, CM0+ Sleep
100 MHz. IMO & FLL. Dhrystone.
Execute from Cache; CM4 Active
50 MHz, CM0+ Sleep 25 MHz. IMO
& FLL. Dhrystone
Execute from Cache; CM4 Active
8 MHz, CM0+ Sleep 8 MHz. IMO.
Dhrystone.
–
9.7
11.2
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
–
14.4
15.1
mA
VDDD = 1.8 to 3.3 V, LDO, Max at 85 °C
–
4.8
5.8
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
7.4
8.4
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
–
11.3
12
mA
VDDD = 1.8 to 3.3 V, LDO, Max at 85 °C
–
2.4
3.4
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
3.7
4.1
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
–
6.3
7.2
mA
VDDD = 1.8 to 3.3 V, LDO, Max at 85 °C
–
0.9
1.5
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
1.3
1.8
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
–
3
3.8
mA
VDDD = 1.8 to 3.3 V, LDO, Max at 85 °C
–
2.4
3.3
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
3.2
3.7
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
–
5.6
6.3
mA
VDDD = 1.8 to 3.3 V, LDO, Max at 85 °C
–
0.8
1.5
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
1.1
1.6
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
–
2.60
3.4
mA
VDDD = 1.8 to 3.3 V, LDO, Max at 85 °C
Cortex M0+. Active Mode
Execute with Cache Disabled (Flash)
SIDF3
SIDF4
IDD7
IDD8
Execute from Flash;
CM4 Off, CM0+ Active 50 MHz.
With IMO & FLL. While (1).
Execute from Flash;
CM4 Off, CM0+ Active 8 MHz.
With IMO. While (1).
Document Number: 002-21414 Rev. *M
Page 40 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Table 14. CPU Current and Transition Times (continued)
Spec ID# Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
–
3.8
4.5
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
5.9
6.5
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
–
9
9.7
mA
VDDD = 1.8 to 3.3 V, LDO, Max at 85 °C
–
0.8
1.3
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
1.20
1.7
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
–
2.60
3.4
mA
VDDD = 1.8 to 3.3 V, LDO, Max at 85 °C
–
1.5
2.2
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
2.2
2.7
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
–
4
4.6
mA
VDDD = 1.8 to 3.3 V, LDO, Max at 85 °C
–
1.2
1.9
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
1.7
2.2
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
–
3.4
4.3
mA
VDDD = 1.8 to 3.3 V, LDO, Max at 85 °C
–
0.7
1.3
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
1
1.5
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
–
2.4
3.3
mA
VDDD = 1.8 to 3.3 V, LDO, Max at 85 °C
–
1.3
2
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
1.9
2.4
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
Execute with Cache Enabled
SIDC5
SIDC6
IDD9
IDD10
Execute from Cache;
CM4 Off, CM0+ Active 100 MHz.
With IMO & FLL. Dhrystone.
Execute from Cache;
CM4 Off, CM0+ Active 8 MHz.
With IMO. Dhrystone.
Cortex M4. Sleep Mode
SIDS1
SIDS2
SIDS3
IDD11
IDD12
IDD13
CM4 Sleep 100 MHz;
CM0+ Sleep 25 MHz. With IMO &
FLL.
CM4 Sleep 50 MHz;
CM0+ Sleep 25 MHz. With IMO &
FLL.
CM4 Sleep 8 MHz, CM0+ Sleep 8
MHz.
With IMO.
Cortex M0+. Sleep Mode
SIDS4
SIDS5
IDD14
IDD15
CM4 Off, CM0+ Sleep 50 MHz.
With IMO & FLL.
CM4 Off, CM0+ Sleep 8 MHz. With
IMO.
–
3.80
4.6
mA
VDDD = 1.8 to 3.3 V, LDO, Max at 85 °C
–
0.7
1.3
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
1
1.5
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
–
2.4
3.3
mA
VDDD = 1.8 to 3.3 V, LDO, Max at 85 °C
–
0.9
1.5
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
1.2
1.7
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
–
2.8
3.5
mA
VDDD = 1.8 to 3.3 V, LDO, Max at 85 °C
–
0.9
1.5
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
1.3
1.8
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
–
2.9
3.7
mA
VDDD = 1.8 to 3.3 V, LDO, Max at 85 °C
–
0.8
1.4
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
1.1
1.6
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
–
2.7
3.6
mA
VDDD = 1.8 to 3.3 V, LDO, Max at 85 °C
Cortex M4. Minimum Regulator Current Mode
SIDLPA1
SIDLPA2
IDD16
IDD17
Execute from Flash; CM4 LPA 8
MHz, CM0+ Sleep 8 MHz. With
IMO. While (1).
Execute from Cache; CM4 LPA 8
MHz, CM0+ Sleep 8 MHz. With
IMO. Dhrystone.
Cortex M0+. Minimum Regulator Current Mode
SIDLPA3
IDD18
Execute from Flash;
CM4 Off, CM0+ Active 8 MHz.
With IMO. While (1).
Document Number: 002-21414 Rev. *M
Page 41 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Table 14. CPU Current and Transition Times (continued)
Spec ID# Parameter
SIDLPA4
IDD19
Description
Execute from Cache; CM4 Off,
CM0+ Active 8 MHz. With IMO.
Dhrystone.
Min
Typ
Max
Unit
Details / Conditions
–
0.8
1.4
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
1.2
1.7
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
–
2.7
3.6
mA
VDDD = 1.8 to 3.3 V, LDO, Max at 85 °C
–
0.7
1.1
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
1
1.5
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
–
2.4
3.3
mA
VDDD = 1.8 to 3.3 V, LDO, Max at 85 °C
–
0.6
1.1
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
0.9
1.5
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
–
2.4
3.3
mA
VDDD = 1.8 to 3.3 V, LDO, Max at 85 °C
Cortex M4. Minimum Regulator Current Mode
SIDLPS1
IDD20
CM4 Sleep 8 MHz, CM0+ Sleep 8
MHz.
With IMO.
Cortex M0+. Minimum Regulator Current Mode
SIDLPS3
IDD22
CM4 Off, CM0+ Sleep 8 MHz. With
IMO.
ULP RANGE POWER SPECIFICATIONS (for VCCD = 0.9 V using the Buck). ULP mode is valid from –20 to +85 °C.
Cortex M4. Active Mode
Execute with Cache Disabled (Flash)
SIDF5
SIDF6
IDD3
IDD4
Execute from Flash; CM4 Active 50
MHz, CM0+ Sleep 25 MHz.
With IMO & FLL. While(1).
–
1.7
2.2
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
2.1
2.4
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
Execute from Flash; CM4 Active 8
MHz, CM0+ Sleep 8 MHz. With
IMO. While (1)
–
0.56
0.8
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
0.75
1
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
Execute from Cache; CM4 Active
50 MHz, CM0+ Sleep 25 MHz.
With IMO & FLL. Dhrystone.
–
1.6
2.2
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
2.4
2.7
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
Execute from Cache; CM4 Active 8
MHz, CM0+ Sleep 8 MHz.
With IMO. Dhrystone.
–
0.65
0.8
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
0.8
1.1
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
Execute with Cache Enabled
SIDC8
SIDC9
IDD10
IDD11
Cortex M0+. Active Mode
Execute with Cache Disabled (Flash)
SIDF7
SIDF8
IDD16
Execute from Flash; CM4 Off,
CM0+ Active 25 MHz. With IMO &
FLL. Write(1).
–
1
1.4
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
1.34
1.6
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
IDD17
Execute from Flash; CM4 Off,
CM0+ Active 8 MHz. With IMO.
While(1).
–
0.54
0.75
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
0.73
1
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
Execute with Cache Enabled
SIDC10
SIDC11
IDD18
Execute from Cache; CM4 Off,
CM0+ Active 25 MHz. With IMO &
FLL. Dhrystone.
–
0.91
1.25
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
1.34
1.6
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
IDD19
Execute from Cache; CM4 Off,
CM0+ Active 8 MHz. With IMO.
Dhrystone.
–
0.51
0.72
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
0.73
0.95
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
Document Number: 002-21414 Rev. *M
Page 42 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Table 14. CPU Current and Transition Times (continued)
Spec ID# Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
IDD21
CM4 Sleep 50 MHz, CM0+ Sleep
25 MHz. With IMO & FLL.
–
0.76
1.1
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
1.1
1.4
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
IDD22
CM4 Sleep 8 MHz, CM0+ Sleep 8
MHz.
With IMO.
–
0.42
0.65
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
0.59
0.8
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
Cortex M4. Sleep Mode
SIDS7
SIDS8
Cortex M0+. Sleep Mode
SIDS9
SIDS10
IDD23
CM4 Off, CM0+ Sleep 25 MHz.
With IMO & FLL.
–
0.62
0.9
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
0.88
1.1
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
IDD24
CM4 Off, CM0+ Sleep 8 MHz.
With IMO.
–
0.41
0.6
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
0.58
0.8
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
Cortex M4. Minimum Regulator Current Mode
SIDLPA5
SIDLPA6
IDD25
Execute from Flash. CM4 Active 8
MHz, CM0+ Sleep 8 MHz. With
IMO. While(1).
–
0.52
0.75
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
0.76
1
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
IDD26
Execute from Cache. CM4 Active 8
MHz, CM0+ Sleep 8 MHz. With
IMO. Dhrystone.
–
0.54
0.76
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
0.78
1
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
Cortex M0+. Minimum Regulator Current Mode
IDD27
Execute from Flash. CM4 Off,
CM0+ Active 8 MHz. With IMO.
While (1).
–
0.51
0.75
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
0.75
1
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
IDD28
Execute from Cache. CM4 Off,
CM0+ Active 8 MHz. With IMO.
Dhrystone.
–
0.48
0.7
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
0.7
0.95
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
–
0.4
0.6
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
0.57
0.8
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
CM4 Off, CM0+ Sleep 8 MHz. With
IMO.
–
0.39
0.6
mA
VDDD = 3.3 V, Buck ON, Max at 60 °C
–
0.56
0.8
mA
VDDD = 1.8 V, Buck ON, Max at 60 °C
With internal Buck enabled and
64K SRAM retention
–
7
–
µA
Max value is at 85 °C
SIDDS1_B IDD33A_B
With internal Buck enabled and
64K SRAM retention
–
7
–
µA
Max value is at 60 °C
SIDDS2
With internal Buck enabled and
256K SRAM retention
–
9
–
µA
Max value is at 85 °C
With internal Buck enabled and
256K SRAM retention
–
9
–
µA
Max value is at 60 °C
SIDLPA7
SIDLPA8
Cortex M4. Minimum Regulator Current Mode
SIDLPS5
IDD29
CM4 Sleep 8 MHz, CM0 Sleep 8
MHz.
With IMO.
Cortex M0+. Minimum Regulator Current Mode
SIDLPS7
IDD31
Deep Sleep Mode
SIDDS1
IDD33A
IDD33B
SIDDS2_B IDD33B_B
Hibernate Mode
SIDHIB1
IDD34
VDDD = 1.8 V
–
300
–
nA
No clocks running
SIDHIB2
IDD34A
VDDD = 3.3 V
–
800
–
nA
No clocks running
Document Number: 002-21414 Rev. *M
Page 43 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Table 14. CPU Current and Transition Times (continued)
Spec ID# Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
Power Mode Transition Times
SID12
TLPACT_AC Minimum regulator current to LP
transition time
T
–
–
35
µs
Including PLL lock time
SID13
TDS_LPACT Deep Sleep to LP transition time
–
–
25
µs
Guaranteed by design
SID14
THIB_ACT
–
500
–
µs
Including PLL lock time
Hibernate to LP transition time
XRES
Table 15. XRES DC Specifications
Spec ID#
Parameter
Description
IDD when XRES asserted
Min
Typ
Max
Unit
Details / Conditions
–
300
–
nA
VDDD = 1.8 V
SID17
TXRES_IDD
SID17A
TXRES_IDD_1 IDD when XRES asserted
–
800
–
nA
VDDD = 3.3 V
SID77
VIH
Input voltage high threshold
0.7 ×
VDD
–
–
V
CMOS Input
SID78
VIL
Input voltage low threshold
–
–
0.3 ×
VDD
V
CMOS Input
SID80
CIN
Input capacitance
–
3
–
pF
–
SID81
VHYSXRES
Input voltage hysteresis
–
100
–
mV
–
SID82
IDIODE
Current through protection diode to
VDD/VSS
–
–
100
µA
–
Table 16. XRES AC Specifications
Min
Typ
Max
Unit
SID15
Spec ID#
TXRES_ACT
Parameter
Time from XRES release to
Cortex-M0+ executing application
code
Description
–
750
–
µs
Not minimum regulator current
mode; Cortex-M0+ executing at
50 MHz
Details / Conditions
SID16
TXRES_PW
XRES Pulse width
5
–
–
µs
–
Min
Typ
Max
GPIO
Table 17. GPIO DC Specifications
Spec ID#
Parameter
Description
Unit
Details / Conditions
SID57
VIH
Input voltage high threshold
0.7 × VDD
–
–
V
CMOS Input
SID57A
IIHS
Input current when Pad > VDDIO
for OVT inputs
–
–
10
µA
Per I2C Spec
SID58
VIL
Input voltage low threshold
–
–
0.3 ×
VDD
V
CMOS Input
SID241
VIH
LVTTL input, VDD < 2.7 V
0.7 × VDD
–
–
V
–
SID242
VIL
LVTTL input, VDD < 2.7 V
–
–
0.3 ×
VDD
V
–
SID243
VIH
LVTTL input, VDD ≥ 2.7 V
2.0
–
–
V
–
SID244
VIL
LVTTL input, VDD ≥ 2.7 V
–
–
0.8
V
–
SID59
VOH
Output voltage high level
VDD – 0.5
–
–
V
IOH = 8 mA
SID62A
VOL
Output voltage low level
–
–
0.4
V
IOL = 8 mA
Document Number: 002-21414 Rev. *M
Page 44 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Table 17. GPIO DC Specifications (continued)
Min
Typ
Max
Unit
SID63
Spec ID#
RPULLUP
Parameter
Pull-up resistor
Description
3.5
5.6
8.5
kΩ
–
Details / Conditions
SID64
RPULLDOWN
Pull-down resistor
3.5
5.6
8.5
kΩ
–
SID65
IIL
Input leakage current (absolute
value)
–
–
2
nA
25 °C, VDD = 3.0 V
SID65A
IIL_CTBM
Input leakage on CTBm input pins
–
–
4
nA
–
SID66
CIN
Input Capacitance
–
–
5
pF
–
SID67
VHYSTTL
Input hysteresis LVTTL VDD >
2.7 V
100
0
–
mV
–
SID68
VHYSCMOS
Input hysteresis CMOS
0.05 × VDD
–
–
mV
–
SID69
IDIODE
Current through protection diode
to VDD/VSS
–
–
100
µA
–
SID69A
ITOT_GPIO
Maximum total source or sink
Chip Current
–
–
200
mA
–
Table 18. GPIO AC Specifications
Min
Typ
Max
Unit
SID70
Spec ID#
TRISEF
Parameter
Rise time in Fast Strong Mode.
10% to 90% of VDD
Description
–
–
2.5
ns
Cload = 15 pF, 8 mA
drive strength
SID71
TFALLF
Fall time in Fast Strong Mode.
10% to 90% of VDD
–
–
2.5
ns
Cload = 15 pF, 8 mA
drive strength
SID72
TRISES_1
Rise time in Slow Strong Mode.
10% to 90% of VDD
52
–
142
ns
Cload = 15 pF, 8 mA
drive strength,
VDD 2.7 V
SID72A
TRISES_2
Rise time in Slow Strong Mode.
10% to 90% of VDD
48
–
102
ns
Cload = 15 pF, 8 mA
drive strength, 2.7 V <
VDD 3.6 V
SID73
TFALLS_1
Fall time in Slow Strong Mode.
10% to 90% of VDD
44
–
211
ns
Cload = 15 pF, 8 mA
drive strength,
VDD 2.7 V
SID73A
TFALLS_2
Fall time in Slow Strong Mode.
10% to 90% of VDD
42
–
93
ns
Cload = 15 pF, 8 mA
drive strength,
2.7 V < VDD 3.6 V
SID73G
TFALL_I2C
Fall time (30% to 70% of VDD) in 20 × VDDIO/
Slow Strong mode
5.5
–
250
ns
Cload = 10 pF to 400 pF,
8-mA drive strength
SID74
FGPIOUT1
GPIO Fout. Fast Strong mode.
–
–
100
MHz
90/10%, 15-pF load,
60/40 duty cycle
SID75
FGPIOUT2
GPIO Fout; Slow Strong mode.
–
–
16.7
MHz
90/10%, 15-pF load,
60/40 duty cycle
SID76
FGPIOUT3
GPIO Fout; Fast Strong mode.
–
–
7
MHz
90/10%, 25-pF load,
60/40 duty cycle
SID245
FGPIOUT4
GPIO Fout; Slow Strong mode.
–
–
3.5
MHz
90/10%, 25-pF load,
60/40 duty cycle
SID246
FGPIOIN
GPIO input operating
frequency;1.71 V VDD 3.6 V
–
–
100
MHz
90/10% VIO
Document Number: 002-21414 Rev. *M
Details / Conditions
Page 45 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Analog Peripherals
Opamp
Table 19. Opamp Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
IDD
Opamp block current. No load.
–
–
–
SID269
IDD_HI
Power = Hi
–
1300
1500
µA
–
–
SID270
IDD_MED
Power = Med
–
450
600
µA
–
SID271
IDD_LOW
Power = Lo
–
250
350
µA
–
GBW
Load = 50 pF, 0.1 mA.
VDDA 2.7 V
–
–
–
–
SID272
GBW_HI
Power = Hi
6
–
–
MHz
–
SID273
GBW_MED
Power = Med
3
–
–
MHz
–
SID274
GBW_LO
Power = Lo
1
–
–
MHz
IOUT_MAX
VDDA 2.7 V, 500 mV from rail
–
–
–
–
–
SID275
IOUT_MAX_HI
Power = Hi
10
–
–
mA
–
SID276
IOUT_MAX_MID
Power = Med
10
–
–
mA
–
SID277
IOUT_MAX_LO
Power = Lo
–
5
–
mA
IOUT
VDDA = 1.71 V, 500 mV from rail
–
–
–
SID278
IOUT_MAX_HI
Power = Hi
4
–
–
mA
–
SID279
IOUT_MAX_MID
Power = Med
4
–
–
mA
–
SID280
IOUT_MAX_LO
Power = Lo
–
2
–
mA
V
V
–
–
–
SID281
VIN
Input voltage range
0
–
VDDA –
0.2
SID282
VCM
Input common mode voltage
0
–
VDDA –
1.5
VOUT
VDDA ≥ 2.7 V
–
–
–
SID283
VOUT_1
Power = Hi, Iload = 10 mA
0.5
–
VDDA –
0.5
V
SID284
VOUT_2
Power = Hi, Iload = 1 mA
0.2
–
VDDA –
0.2
V
SID285
VOUT_3
Power = Med, Iload = 1 mA
0.2
–
VDDA –
0.2
V
SID286
VOUT_4
Power = Lo, Iload = 0.1 mA
0.2
–
VDDA –
0.2
V
SID288
VOS_TR
Offset voltage
–1
±0.5
1
mV
SID288A
VOS_TR
Offset voltage
–
±1
–
mV
Power = Med
SID288B
VOS_TR
Offset voltage
–
±2
–
mV
Power = Lo
SID290
VOS_DR_TR
Offset voltage drift
–10
±3
10
µV/°C
SID290A
VOS_DR_TR
Offset voltage drift
–
±10
–
µV/°C Power = Med
SID290B
VOS_DR_TR
Offset voltage drift
–
±10
–
µV/°C Power = Lo
SID291
CMRR
DC common mode rejection ratio
67
80
–
dB
VDDA ≥ 2.7 V
SID292
PSRR
Power supply rejection ratio at
1 kHz, 10-mV ripple
70
85
–
dB
VDDA ≥ 2.7 V
SID65A
IIL_CTBM
Input leakage on CTBm input pins
–
–
4
nA
–
Document Number: 002-21414 Rev. *M
Charge pump ON
Charge pump OFF,
VDDA 2.7 V
–
–
–
–
–
Power = Hi, 0.2 V < VOUT
< (VDDA - 0.2 V)
Power = Hi, 0.2 V < VOUT
< (VDDA - 0.2 V)
Page 46 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Table 19. Opamp Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
Noise
SID293
VN1
Input-referred, 1 Hz – 1 GHz,
power = Hi
–
100
–
µVrms
SID294
VN2
Input-referred, 1 kHz,
power = Hi
–
180
–
nV/rtHz
SID295
VN3
Input-referred, 10 kHz,
power = Hi
–
70
–
nV/rtHz
SID296
VN4
Input-referred, 100 kHz,
power = Hi
–
38
–
nV/rtHz
SID297
CLOAD
Stable up to max. load.
Performance specs at 50 pF.
–
–
125
pF
SID298
SLEW_RATE
Output slew rate
4
–
–
V/µs
SID299
T_OP_WAKE
From disable to enable, no
external RC dominating
–
25
–
µs
COMP_MODE
Comparator mode; 50-mV
overdrive, Trise = Tfall (approx.)
–
–
–
–
–
–
Cload = 50 pF,
Power = Hi, VDDA 2.7 V
Refer to Figure 17 and
Figure 18.
–
–
–
SID300
TPD1
Response time; power = Hi
–
150
–
ns
–
SID301
TPD2
Response time; power = Med
–
400
–
ns
–
SID302
TPD3
Response time; power = Lo
–
2000
–
ns
–
SID303
VHYST_OP
Hysteresis
–
10
–
mV
–
Deep Sleep mode
operation: VDDA ≥ 2.7 V.
VIN is 0.2 to VDDA –1.5 V
Deep Sleep Mode
Mode 2 is lowest current range.
Mode 1 has higher GBW.
SID_DS_1
IDD_HI_M1
Mode 1, High current
–
1300
SID_DS_2
IDD_MED_M1
Mode 1, Medium current
–
460
600
µA
Typ at 25 °C
SID_DS_3
IDD_LOW_M1
Mode 1, Low current
–
230
350
µA
Typ at 25 °C
SID_DS_4
IDD_HI_M2
Mode 2, High current
–
120
–
µA
25 °C
SID_DS_5
IDD_MED_M2
Mode 2, Medium current
–
60
–
µA
25 °C
SID_DS_6
IDD_LOW_M2
Mode 2, Low current
–
15
–
µA
25 °C
SID_DS_7
GBW_HI_M1
Mode 1, High current
–
4
–
MHz
25 °C
1500
µA
Typ at 25 °C
SID_DS_8
GBW_MED_M1 Mode 1, Medium current
–
2
–
MHz
25 °C
SID_DS_9
GBW_LOW_M1 Mode 1, Low current
–
0.5
–
MHz
25 °C
SID_DS_10
GBW_HI_M2
–
0.5
–
MHz
20-pF load, no DC load
0.2 V to VDDA – 1.5 V
SID_DS_11
GBW_MED_M2 Mode 2, Medium current
–
0.2
–
MHz
20-pF load, no DC load
0.2 V to VDDA – 1.5 V
SID_DS_12
GBW_LOW_M2 Mode 2, Low current
–
0.1
–
MHz
20-pF load, no DC load
0.2 V to VDDA – 1.5 V
SID_DS_13
VOS_HI_M1
Mode 1, High current
–
5
–
mV
25 °C, 0.2 V to VDDA –
1.5 V
SID_DS_14
VOS_MED_M1
Mode 1, Medium current
–
5
–
mV
25 °C, 0.2 V to VDDA –
1.5 V
SID_DS_15
VOS_LOW_M1
Mode 1, Low current
–
5
–
mV
25 °C, 0.2 V to VDDA –
1.5 V
Mode 2, High current
Document Number: 002-21414 Rev. *M
Page 47 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Table 19. Opamp Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
SID_DS_16
VOS_HI_M2
Mode 2, High current
–
5
–
mV
25 °C, 0.2 V to VDDA –
1.5 V
SID_DS_17
VOS_MED_M2
Mode 2, Medium current
–
5
–
mV
25 °C, 0.2 V to VDDA –
1.5 V
SID_DS_18
VOS_LOW_M2
Mode 2, Low current
–
5
–
mV
25 °C, 0.2 V to VDDA –
1.5 V
SID_DS_19
IOUT_HI_M1
Mode 1, High current
–
10
–
mA
Output is 0.5 V to VDDA –
0.5 V
SID_DS_20
IOUT_MED_M1
Mode 1, Medium current
–
10
–
mA
Output is 0.5 V to
VDDA – 0.5 V
SID_DS_21
IOUT_LOW_M1
Mode 1, Low current
–
4
–
mA
Output is 0.5 V to VDDA –
0.5 V
SID_DS_22
IOUT_HI_M2
Mode 2, High current
–
1
–
mA
Output is 0.5 V to VDDA –
0.5 V
SID_DS_23
IOUT_MED_M2
Mode 2, Medium current
–
1
–
mA
Output is 0.5 V to VDDA –
0.5 V
SID_DS_24
IOUT_LOW_M2
Mode 2, Low current
–
0.5
–
mA
Output is 0.5 V to VDDA –
0.5 V
Figure 18. Opamp Step Response, Falling
1.4
1.4
1.2
1.2
Input and Output Signals, V
Input and Output Signals, V
Figure 17. Opamp Step Response, Rising
1
0.8
0.6
Input
0.4
Output, Power = Hi
0.2
0
-0.25
Output, Power = Med
0
0.25
0.5
Time, µs
Document Number: 002-21414 Rev. *M
0.75
1
Input
Output, Power = Hi
1
Output, Power = Med
0.8
0.6
0.4
0.2
0
-0.25
0
0.25
0.5
Time. µs
0.75
1
Page 48 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Low-Power (LP) Comparator
Table 20. LP Comparator DC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
COMP0 offset is ±25 mV
SID84
VOFFSET1
Input offset voltage for COMP1.
Normal power mode.
–10
–
10
mV
SID85A
VOFFSET2
Input offset voltage. Low-power
mode.
–25
±12
25
mV
SID85B
VOFFSET3
Input offset voltage. Ultra
low-power mode.
–25
±12
25
mV
SID86
VHYST1
Hysteresis when enabled in
Normal mode
–
–
60
mV
SID86A
VHYST2
Hysteresis when enabled in
Low-power mode
–
–
80
mV
SID87
VICM1
Input common mode voltage in
Normal mode
0
–
VDDIO1 – 0.1
V
SID247
VICM2
Input common mode voltage in
Low power mode
0
–
VDDIO1 – 0.1
V
SID247A
VICM3
Input common mode voltage in
Ultra low power mode
0
–
VDDIO1 – 0.1
V
SID88
CMRR
Common mode rejection ratio in
Normal power mode
50
–
–
dB
SID89
ICMP1
Block Current, Normal mode
–
–
150
µA
–
SID248
ICMP2
Block Current, Low power mode
–
–
10
µA
–
SID259
ICMP3
Block Current in Ultra low-power
mode
–
0.3
0.85
µA
SID90
ZCMP
DC Input impedance of
comparator
35
–
–
MΩ
Min
Typ
Max
Unit
–
–
–
–
–
–
–
–
–
–
Table 21. LP Comparator AC Specifications
Spec ID#
Parameter
Description
Details / Conditions
SID91
TRESP1
Response time, Normal mode,
100 mV overdrive
–
–
100
ns
SID258
TRESP2
Response time, Low power
mode, 100 mV overdrive
–
–
1000
ns
SID92
TRESP3
Response time, Ultra-low power
mode, 100 mV overdrive
–
–
20
µs
SID92E
T_CMP_EN1
Time from Enabling to operation
–
–
10
µs
Normal and Low-power
modes
SID92F
T_CMP_EN2
Time from Enabling to operation
–
–
50
µs
Ultra low-power mode
Min
Typ
Max
Unit
–5
±1
5
°C
Description
Min
Typ
Max
Unit
–
1.188
1.2
1.212
V
–
–
–
Table 22. Temperature Sensor Specifications
Spec ID#
SID93
Parameter
TSENSACC
Description
Temperature sensor accuracy
Details / Conditions
–40 to +85 °C
Table 23. Internal Reference Specification
Spec ID#
SID93R
Parameter
VREFBG
Document Number: 002-21414 Rev. *M
Details / Conditions
–
Page 49 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
SAR ADC
Table 24. 12-bit SAR ADC DC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
SID94
A_RES
SAR ADC Resolution
–
–
12
bits
–
SID95
A_CHNLS_S
Number of channels single-ended
–
–
16
–
8 full speed.
SID96
A-CHNKS_D
Number of channels - differential
–
–
8
–
Diff inputs use neighboring
I/O
SID97
A-MONO
Monotonicity
–
–
–
–
Yes
SID98
A_GAINERR
Gain error
–
–
±0.2
%
With external reference.
SID99
A_OFFSET
Input offset voltage
–
–
2
mV
Measured with 1-V reference
SID100
A_ISAR_1
Current consumption at 1 Msps
–
–
1
mA
At 1 Msps. External Bypass
Cap.
SID100A A_ISAR_2
Current consumption at 1 Msps.
Reference = VDD
–
–
1.25
mA
At 1 Msps. External Bypass
Cap.
SID101
A_VINS
Input voltage range - single-ended
VSS
–
VDDA
V
–
SID102
A_VIND
Input voltage range - differential
VSS
–
VDDA
V
–
SID103
A_INRES
Input resistance
–
–
2.2
kΩ
–
SID104
A_INCAP
Input capacitance
–
–
10
pF
–
Min
Typ
Max
Unit
Table 25. 12-bit SAR ADC AC Specifications
Spec ID#
Parameter
Description
Details / Conditions
12-bit SAR ADC AC Specifications
SID106
A_PSRR
Power supply rejection ratio
70
–
–
dB
–
SID107
A_CMRR
Common mode rejection ratio
66
–
–
dB
Measured at 1 V.
One Megasample per second mode:
SID108
A_SAMP_1
Sample rate with external reference
bypass cap.
–
–
1
Msps
–
SID108A
A_SAMP_2
Sample rate with no bypass cap;
Reference = VDD
–
–
250
ksps
–
SID108B
A_SAMP_3
Sample rate with no bypass cap.
Internal reference.
–
–
100
ksps
–
SID109
A_SINAD
Signal-to-noise and Distortion ratio
(SINAD). VDDA = 2.7 to 3.6 V,
1 Msps.
64
–
–
dB
SID111A
A_INL
Integral Non Linearity.
VDDA = 2.7 to 3.6 V, 1 Msps
–2
–
2
LSB
Measured with internal
VREF = 1.2 V and bypass cap.
SID111B
A_INL
Integral Non Linearity.
VDDA = 2.7 to 3.6 V, 1 Msps
–4
–
4
LSB
Measured with external
VREF ≥ 1 V and VIN common
mode < 2 * Vref.
SID112A
A_DNL
Differential Non Linearity.
VDDA = 2.7 to 3.6 V, 1 Msps
–1
–
1.4
LSB
Measured with internal
VREF = 1.2 V and bypass cap.
SID112B
A_DNL
Differential Non Linearity.
VDDA = 2.7 to 3.6 V, 1 Msps
–1
–
1.7
LSB
Measured with external
VREF ≥ 1 V and VIN common
mode < 2 * Vref.
SID113
A_THD
Total harmonic distortion.
VDDA = 2.7 to 3.6 V, 1 Msps.
–
–
–65
dB
Document Number: 002-21414 Rev. *M
Fin = 10 kHz
Fin = 10 kHz
Page 50 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
DAC
Table 26. 12-bit DAC DC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
SID108D DAC_RES
DAC resolution
–
–
12
bits
–
SID111D
Integral non-linearity
–4
–
4
LSB
–
SID112D DAC_DNL
Differential non-linearity
–2
–
2
LSB
Monotonic to 11 bits.
SID99D
Output Voltage zero offset error
–2
–
1
mV
For 000 (hex)
SID103D DAC_OUT_RES DAC Output Resistance
–
15
–
kΩ
–
SID100D DAC_IDD
DAC Current
–
–
125
µA
–
SID101D DAC_QIDD
DAC Current when DAC stopped
–
–
1
µA
–
DAC_INL
DAC_OFFSET
Table 27. 12-bit DAC AC Specifications
Min
Typ
Max
Unit
Details / Conditions
SID109D DAC_CONV
Spec ID#
Parameter
DAC Settling time
Description
–
–
2
µs
Driving through CTBm buffer;
25-pF load
SID110D DAC_Wakeup
Time from Enabling to ready for
conversion
–
–
10
µs
–
CSD
Table 28. CapSense Sigma-Delta (CSD) Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
CSD V2 Specifications
SYS.PER#3
VDD_RIPPLE
Max allowed ripple on power
supply, DC to 10 MHz
–
–
±50
mV
VDDA > 2 V (with ripple), 25 °C
TA,
Sensitivity = 0.1 pF
SYS.PER#16
VDD_RIPPLE_1.8
Max allowed ripple on power
supply, DC to 10 MHz
–
–
±25
mV
VDDA > 1.75 V (with ripple),
25 ° C TA, Parasitic Capacitance (CP) < 20 pF, Sensitivity
≥ 0.4 pF
4500
µA
–
VDDA –
0.6
V
VDDA – VREF ≥ 0.6 V
VDDA –
0.6
V
VDDA – VREF ≥ 0.6 V
SID.CSD.BLK ICSD
Maximum block current
SID.CSD#15
Voltage reference for CSD and
Comparator
0.6
SID.CSD#15A VREF_EXT
External Voltage reference for
CSD and Comparator
0.6
SID.CSD#16
IDAC1IDD
IDAC1 (7-bits) block current
–
–
1900
µA
–
SID.CSD#17
IDAC2IDD
IDAC2 (7-bits) block current
–
–
1900
µA
–
SID308
VCSD
Voltage range of operation
1.7
–
3.6
V
1.71 to 3.6 V
SID308A
VCOMPIDAC
Voltage compliance range of
IDAC
0.6
–
VDDA –
0.6
V
VDDA – VREF ≥ 0.6 V
SID309
IDAC1DNL
DNL
–1
–
1
LSB –
SID310
IDAC1INL
INL
–3
–
3
LSB If VDDA < 2 V then for LSB of
2.4 µA or less
SID311
IDAC2DNL
DNL
–1
–
1
LSB –
SID312
IDAC2INL
INL
–3
–
3
LSB If VDDA < 2 V then for LSB of
2.4 µA or less
VREF
Document Number: 002-21414 Rev. *M
1.2
Page 51 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Table 28. CapSense Sigma-Delta (CSD) Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
SNRC of the following is Ratio of counts of finger to noise. Guaranteed by characterization
SID313_1A
SNRC_1
SRSS Reference. IMO + FLL
Clock Source. 0.1-pF sensitivity
5
–
–
Ratio 9.5-pF max. capacitance
SID313_1B
SNRC_2
SRSS Reference. IMO + FLL
Clock Source. 0.3-pF sensitivity
5
–
–
Ratio 31-pF max. capacitance
SID313_1C
SNRC_3
SRSS Reference. IMO + FLL
Clock Source. 0.6-pF sensitivity
5
–
–
Ratio 61-pF max. capacitance
SID313_2A
SNRC_4
PASS Reference. IMO + FLL
Clock Source. 0.1-pF sensitivity
5
–
–
Ratio 12-pF max. capacitance
SID313_2B
SNRC_5
PASS Reference. IMO + FLL
Clock Source. 0.3-pF sensitivity
5
–
–
Ratio 47-pF max. capacitance
SID313_2C
SNRC_6
PASS Reference. IMO + FLL
Clock Source. 0.6-pF sensitivity
5
–
–
Ratio 86-pF max. capacitance
SID313_3A
SNRC_7
PASS Reference. IMO + PLL
Clock Source. 0.1-pF sensitivity
5
–
–
Ratio 27-pF max. capacitance
SID313_3B
SNRC_8
PASS Reference. IMO + PLL
Clock Source. 0.3-pF sensitivity
5
–
–
Ratio 86-pF max. capacitance
SID313_3C
SNRC_9
PASS Reference. IMO + PLL
Clock Source. 0.6-pF sensitivity
5
–
–
Ratio 168-pF max. capacitance
SID314
IDAC1CRT1
Output current of IDAC1 (7 bits)
in low range
4.2
5.7
µA
LSB = 37.5-nA typ
SID314A
IDAC1CRT2
Output current of IDAC1(7 bits)
in medium range
33.7
45.6
µA
LSB = 300-nA typ.
SID314B
IDAC1CRT3
Output current of IDAC1(7 bits)
in high range
270
365
µA
LSB = 2.4-µA typ.
SID314C
IDAC1CRT12
Output current of IDAC1 (7 bits)
in low range, 2X mode
8
11.4
µA
LSB = 37.5-nA typ.
2X output stage
SID314D
IDAC1CRT22
Output current of IDAC1(7 bits)
in medium range, 2X mode
67
91
µA
LSB = 300-nA typ.
2X output stage
SID314E
IDAC1CRT32
Output current of IDAC1(7 bits)
in high range, 2X mode. VDDA >
2V
540
730
µA
LSB = 2.4-µA typ.
2X output stage
SID315
IDAC2CRT1
Output current of IDAC2 (7 bits)
in low range
4.2
5.7
µA
LSB = 37.5-nA typ.
SID315A
IDAC2CRT2
Output current of IDAC2 (7 bits)
in medium range
33.7
45.6
µA
LSB = 300-nA typ.
SID315B
IDAC2CRT3
Output current of IDAC2 (7 bits)
in high range
270
365
µA
LSB = 2.4-µA typ.
SID315C
IDAC2CRT12
Output current of IDAC2 (7 bits)
in low range, 2X mode
8
11.4
µA
LSB = 37.5-nA typ.
2X output stage
SID315D
IDAC2CRT22
Output current of IDAC2(7 bits)
in medium range, 2X mode
67
91
µA
LSB = 300-nA typ.
2X output stage
SID315E
IDAC2CRT32
Output current of IDAC2(7 bits)
in high range, 2X mode. VDDA >
2V
540
730
µA
LSB = 2.4-µA typ.
2X output stage
SID315F
IDAC3CRT13
Output current of IDAC in 8-bit
mode in low range
8
11.4
µA
LSB = 37.5-nA typ.
Document Number: 002-21414 Rev. *M
Page 52 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Table 28. CapSense Sigma-Delta (CSD) Specifications (continued)
Max
Unit
SID315G
Spec ID#
IDAC3CRT23
Parameter
Output current of IDAC in 8-bit
mode in medium range
Description
Min
67
Typ
91
µA
LSB = 300-nA typ.
Details / Conditions
SID315H
IDAC3CRT33
Output current of IDAC in 8-bit
mode in high range. VDDA > 2V
540
730
µA
LSB = 2.4-µA typ.
SID320
IDACOFFSET
All zeroes input
–
–
1
SID321
IDACGAIN
Full-scale error less offset
–
–
±15
SID322
IDACMISMATCH1
Mismatch between IDAC1 and
IDAC2 in Low mode
–
–
9.2
LSB LSB = 37.5-nA typ.
SID322A
IDACMISMATCH2
Mismatch between IDAC1 and
IDAC2 in Medium mode
–
–
6
LSB LSB = 300-nA typ.
SID322B
IDACMISMATCH3
Mismatch between IDAC1 and
IDAC2 in High mode
–
–
5.8
LSB LSB = 2.4-µA typ.
SID323
IDACSET8
Settling time to 0.5 LSB for 8-bit
IDAC
–
–
10
µs
Full-scale transition.
No external load.
SID324
IDACSET7
Settling time to 0.5 LSB for 7-bit
IDAC
–
–
10
µs
Full-scale transition.
No external load.
SID325
CMOD
External modulator capacitor.
–
2.2
–
nF
5-V rating, X7R or NP0 cap.
LSB Polarity set by Source or Sink
%
LSB = 2.4-µA typ.
Table 29. CSD ADC Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
CSDv2 ADC Specifications
SIDA94
A_RES
Resolution
–
–
10
bits
Auto-zeroing is required every
millisecond
SID95
A_CHNLS_S
Number of channels - single
ended
–
–
–
16
–
SIDA97
A-MONO
Monotonicity
–
–
Yes
–
VREF mode
SIDA98
A_GAINERR_VREF Gain error
–
0.6
–
%
Reference Source: SRSS
(VREF = 1.20 V, VDDA < 2.2 V),
(VREF = 1.6 V, 2.2 V < VDDA<
2.7 V), (VREF = 2.13 V, VDDA >
2.7 V)
SIDA98A
A_GAINERR_VDDA Gain error
–
0.2
–
%
Reference Source: SRSS
(VREF = 1.20 V, VDDA < 2.2V),
(VREF = 1.6 V,
2.2 V < VDDA < 2.7 V),
(VREF = 2.13 V, VDDA > 2.7 V)
SIDA99
A_OFFSET_VREF
Input offset voltage
–
0.5
–
LSB
After ADC calibration, Ref. Src
= SRSS, (VREF = 1.20 V,
VDDA < 2.2 V), (VREF = 1.6 V,
2.2 V < VDDA < 2.7 V),
(VREF = 2.13 V, VDDA > 2.7 V)
SIDA99A
A_OFFSET_VDDA
Input offset voltage
–
0.5
–
LSB
After ADC calibration, Ref.
Src = SRSS, (VREF = 1.20 V,
VDDA < 2.2 V),
(VREF = 1.6 V, 2.2 V < VDDA <
2.7 V),
(VREF = 2.13 V, VDDA > 2.7 V)
SIDA100
A_ISAR_VREF
Current consumption
–
0.3
–
mA
CSD ADC Block current
Document Number: 002-21414 Rev. *M
Page 53 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Table 29. CSD ADC Specifications (continued)
Spec ID#
Parameter
SIDA100A
A_ISAR_VDDA
Current consumption
Description
Min
Typ
Max
Unit
–
0.3
–
mA
SIDA101
A_VINS_VREF
SIDA101A
A_VINS_VDDA
Details / Conditions
Input voltage range - single
ended
VSSA
–
VREF
V
(VREF = 1.20 V, VDDA < 2.2 V),
(VREF = 1.6 V, 2.2 V < VDDA <
2.7 V),
(VREF = 2.13 V, VDDA > 2.7 V)
Input voltage range - single
ended
VSSA
–
VDDA
V
(VREF = 1.20 V, VDDA < 2.2 V),
(VREF = 1.6 V, 2.2 V < VDDA <
2.7 V),
(VREF = 2.13 V, VDDA > 2.7 V)
CSD ADC Block current
SIDA103
A_INRES
Input charging resistance
–
15
–
kΩ
–
SIDA104
A_INCAP
Input capacitance
–
41
–
pF
–
SIDA106
A_PSRR
Power supply rejection ratio
(DC)
–
60
–
dB
–
SIDA107
A_TACQ
Sample acquisition time
–
10
–
µs
Measured with 50-Ω source
impedance. 10 µs is default
software driver acquisition time
setting. Settling to within
0.05%.
SIDA108
A_CONV8
Conversion time for 8-bit
resolution at conversion rate =
Fhclk/(2"(N+2)). Clock
frequency = 50 MHz.
–
25
–
µs
Does not include acquisition
time.
SIDA108A
A_CONV10
Conversion time for 10-bit
resolution at conversion rate =
Fhclk/(2"(N+2)). Clock
frequency = 50 MHz.
–
60
–
µs
Does not include acquisition
time.
SIDA109
A_SND_VRE
Signal-to-noise and Distortion
ratio (SINAD)
–
57
–
dB
Measured with 50-Ω source
impedance
SIDA109A
A_SND_VDDA
Signal-to-noise and Distortion
ratio (SINAD)
–
52
–
dB
Measured with 50-Ω source
impedance
SIDA111
A_INL_VREF
Integral non-linearity. 11.6 ksps
–
–
2
LSB
Measured with 50-Ω source
impedance
SIDA111A
A_INL_VDDA
Integral non-linearity. 11.6 ksps
–
–
2
LSB
Measured with 50-Ω source
impedance
SIDA112
A_DNL_VREF
Differential non-linearity.
11.6 ksps
–
–
1
LSB
Measured with 50-Ω source
impedance
SIDA112A
A_DNL_VDDA
Differential non- linearity.
11.6 ksps
–
–
1
LSB
Measured with 50-Ω source
impedance
Document Number: 002-21414 Rev. *M
Page 54 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Digital Peripherals
Table 30. Timer/Counter/PWM (TCPWM) Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
–
–
70
µA
All modes (TCPWM)
SID.TCPWM.1
ITCPWM1
Block current consumption at
8 MHz
SID.TCPWM.2
ITCPWM2
Block current consumption at
24 MHz
–
–
180
µA
All modes (TCPWM)
SID.TCPWM.2A ITCPWM3
Block current consumption at
50 MHz
–
–
270
µA
All modes (TCPWM)
SID.TCPWM.2B ITCPWM4
Block current consumption at
100 MHz
–
–
540
µA
All modes (TCPWM)
–
–
100
MHz
Fc max = Fcpu
Maximum = 100 MHz
SID.TCPWM.3
TCPWMFREQ Operating frequency
SID.TCPWM.4
Input Trigger Pulse Width for
TPWMENEXT
all Trigger Events
2 / Fc
–
–
ns
Trigger Events can be Stop, Start,
Reload, Count, Capture, or Kill
depending on which mode of operation
is selected. Fc is counter operating
frequency.
SID.TCPWM.5
TPWMEXT
Output Trigger Pulse widths
1.5 /
Fc
–
–
ns
Minimum possible width of Overflow,
Underflow, and CC (Counter equals
Compare value) trigger outputs
SID.TCPWM.5A TCRES
Resolution of Counter
1 / Fc
–
–
ns
Minimum time between successive
counts
SID.TCPWM.5B PWMRES
PWM Resolution
1 / Fc
–
–
ns
Minimum pulse width of PWM Output
SID.TCPWM.5C QRES
Quadrature inputs resolution
2 / Fc
–
–
ns
Minimum pulse width between
Quadrature phase inputs. Delays from
pins should be similar.
Table 31. Serial Communication Block (SCB) Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
2
Fixed I C DC Specifications
SID149
II2C1
Block current consumption at
100 kHz
–
–
30
µA
–
SID150
II2C2
Block current consumption at
400 kHz
–
–
80
µA
–
SID151
II2C3
Block current consumption at
1 Mbps
–
–
180
µA
–
SID152
II2C4
I2C enabled in Deep Sleep
mode
–
–
1.7
µA
At 60 °C
Bit Rate
–
–
1
Fixed I2C AC Specifications
SID153
FI2C1
Mbps –
Fixed UART DC Specifications
SID160
IUART1
Block current consumption at
100 kbps
–
–
30
µA
–
SID161
IUART2
Block current consumption at
1000 kbps
–
–
180
µA
–
Document Number: 002-21414 Rev. *M
Page 55 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Table 31. Serial Communication Block (SCB) Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
–
–
3
–
–
8
Unit
Details / Conditions
Fixed UART AC Specifications
SID162A
FUART1
SID162B
FUART2
Bit Rate
Mbps ULP Mode
LP Mode
Fixed SPI DC Specifications
SID163
ISPI1
Block current consumption at
1 Mbps
–
–
220
µA
–
SID164
ISPI2
Block current consumption at
4 Mbps
–
–
340
µA
–
SID165
ISPI3
Block current consumption at
8 Mbps
–
–
360
µA
–
SID165A
ISP14
Block current consumption at
25 Mbps
–
–
800
µA
–
Fixed SPI AC Specifications for LP Mode (1.1 V) unless noted otherwise.
SID166
FSPI
SPI Operating Frequency
Master and Externally
Clocked Slave
–
–
25
MHz 14-MHz max for ULP (0.9 V) mode
SID166A
FSPI_IC
SPI Slave Internally Clocked
–
–
15
MHz 5-MHz max for ULP (0.9 V) mode
SID166B
FSPI_EXT
SPI Operating Frequency
Master (FSCB is SPI Clock)
–
–
FSCB/4
MHz FSCB max is 100 MHz in LP mode, 25
MHz max in ULP mode
Fixed SPI Master mode AC Specifications for LP Mode (1.1 V) unless noted otherwise.
SID167
TDMO
MOSI Valid after SClock
driving edge
–
–
12
ns
20-ns max for ULP (0.9 V) mode
SID168
TDSI
MISO Valid before SClock
capturing edge
5
–
–
ns
Full clock, late MISO sampling
SID169
THMO
MOSI data hold time
0
–
–
ns
Referred to Slave capturing edge
SID169A
TSSELMSCK1
SSEL Valid to first SCK Valid
edge
18
–
–
ns
Referred to Master clock edge
SID169B
TSSELMSCK2
SSEL Hold after last SCK
Valid edge
18
–
–
ns
Referred to Master clock edge
Fixed SPI Slave mode AC Specifications for LP Mode (1.1 V) unless noted otherwise.
SID170
TDMI
MOSI Valid before Sclock
Capturing edge
5
–
–
ns
–
SID171A
TDSO_EXT
MISO Valid after Sclock
driving edge in Ext. Clk. mode
–
–
20
ns
35-ns max. for ULP (0.9 V) mode
SID171
TDSO
MISO Valid after Sclock
driving edge in Internally Clk.
Mode
–
–
TDSO_EXT
+
3 × Tscb
ns
Tscb is Serial Comm. Block clock
period.
SID171B
TDSO
MISO Valid after Sclock
driving edge in Internally Clk.
Mode with Median filter
enabled.
–
–
TDSO_EXT
+
4 × Tscb
ns
Tscb is Serial Comm. Block clock
period.
SID172
THSO
Previous MISO data hold time
5
–
–
ns
–
SID172A
TSSELSCK1
SSEL Valid to first SCK Valid
edge
65
–
–
ns
–
SID172B
TSSELSCK2
SSEL Hold after Last SCK
Valid edge
65
–
–
ns
Document Number: 002-21414 Rev. *M
Page 56 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
LCD Specifications
Table 32. LCD Direct Drive DC Specifications
Spec ID# Parameter
Description
SID154 ILCDLOW
Operating current in low-power mode
Min
–
Typ
5
Max
–
Unit
Details / Conditions
µA 16 × 4 small segment display at 50 Hz
SID155
CLCDCAP
LCD capacitance per segment/common
driver
–
500
5000
pF
SID156
LCDOFFSET
Long-term segment offset
–
20
–
mV
SID157
ILCDOP1
PWM Mode current.
3.3-V bias. 8-MHz IMO. 25 °C.
–
0.6
–
mA
32 × 4 segments
50 Hz
SID158
ILCDOP2
PWM Mode current.
3.3-V bias. 8-MHz IMO. 25 °C.
–
0.5
–
mA
32 × 4 segments
50 Hz
–
–
Table 33. LCD Direct Drive AC Specifications
Spec ID# Parameter
SID159
FLCD
Description
LCD frame rate
Min
Typ
Max
Unit
10
50
150
Hz
Min
Typ
Max
Unit
–
–
6
mA
Details / Conditions
–
Memory
Flash
Table 34. Flash DC Specifications[3]
Spec ID#
Parameter
SID173A IPE
Description
Erase and program current
Details / Conditions
–
Table 35. Flash AC Specifications
Spec ID#
SID174
Min
Typ
Max
Unit
TROWWRITE
Parameter
Row write time (erase & program)
Description
–
–
16
ms
Row = 512 bytes
Row erase time
–
–
11
ms
–
–
–
5
ms
–
SID175
TROWERASE
SID176
TROWPROGRAM Row program time after erase
SID178
TBULKERASE
SID179
TSECTORERASE Sector erase time (256 KB)
Bulk erase time (1024 KB)
Details / Conditions
–
–
11
ms
–
–
–
11
ms
512 rows per sector
SID178S TSSERIAE
Subsector erase time
–
–
11
ms
8 rows per subsector
SID179S TSSWRITE
Subsector write time; 1 erase plus 8
program times
–
–
51
ms
–
SID180S TSWRITE
Sector write time; 1 erase plus 512
program times
–
–
2.6
seconds –
SID180
TDEVPROG
Total device write time
–
–
15
seconds –
SID181
FEND
Flash Endurance
100 k
–
–
cycles –
FRET1
Flash Retention. TA 25 °C, 100 k P/E
cycles
10
–
–
years
–
SID182A FRET2
Flash Retention. TA 85 °C, 10 k P/E
cycles
10
–
–
years
–
SID182B FRET3
Flash Retention. TA 55 °C, 20 k P/E
cycles
20
–
–
years
–
SID256
TWS100
Number of Wait states at 100 MHz
3
–
–
–
SID257
TWS50
Number of Wait states at 50 MHz
2
–
–
–
SID182
Note
3. It can take as much as 16 milliseconds to write to flash. During this time, the device should not be reset, or flash operations will be interrupted and cannot be relied
on to have completed. Reset sources include the XRES pin, software resets, CPU lockup states and privilege violations, improper power supply levels, and watchdogs.
Make certain that these are not inadvertently activated.
Document Number: 002-21414 Rev. *M
Page 57 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
System Resources
Power-on-Reset
Table 36. Power-On-Reset (POR) with Brown-out Detect (BOD) DC Specifications
Spec ID#
SID190
SID192
Parameter
Min
Typ
Max
Unit
VFALLPPOR
BOD trip voltage in system LP and
ULP modes.
Description
1.54
–
–
V
VFALLDPSLP
BOD trip voltage in system Deep
Sleep mode.
1.54
–
–
V
Min
Typ
Max
Unit
Details / Conditions
Reset guaranteed for VDDD
levels below 1.54 V
Table 37. POR with BOD AC Specifications
Spec ID#
Parameter
Description
Details / Conditions
SID192A VDDRAMP
Maximum power supply ramp rate
(any supply)
–
–
100
mV/µs System LP mode
SID194A VDDRAMP_DS
Maximum power supply ramp rate
(any supply) in system Deep Sleep
mode
–
–
10
mV/µs BOD operation guaranteed
Voltage Monitors
Table 38. Voltage Monitors DC Specifications
Min
Typ
Max
Unit
SID195R VHVD0
SID195 VHVDI1
Spec ID#
Parameter
Description
1.18
1.23
1.27
V
–
1.38
1.43
1.47
V
–
SID196
VHVDI2
1.57
1.63
1.68
V
–
SID197
VHVDI3
1.76
1.83
1.89
V
–
SID198
VHVDI4
1.95
2.03
2.1
V
–
SID199
VHVDI5
2.05
2.13
2.2
V
–
SID200
VHVDI6
2.15
2.23
2.3
V
–
SID201
VHVDI7
2.24
2.33
2.41
V
–
SID202
VHVDI8
2.34
2.43
2.51
V
–
SID203
VHVDI9
2.44
2.53
2.61
V
–
SID204
VHVDI10
2.53
2.63
2.72
V
–
SID205
VHVDI11
2.63
2.73
2.82
V
–
SID206
VHVDI12
2.73
2.83
2.92
V
–
SID207
VHVDI13
2.82
2.93
3.03
V
–
SID208
VHVDI14
2.92
3.03
3.13
V
–
SID209
VHVDI15
3.02
3.13
3.23
V
–
SID211
LVI_IDD
–
5
15
µA
–
Min
Typ
Max
Unit
–
–
170
ns
Block current
Details / Conditions
Table 39. Voltage Monitors AC Specification
Spec ID#
SID212
Parameter
TMONTRIP
Description
Voltage monitor trip time
Document Number: 002-21414 Rev. *M
Details / Conditions
–
Page 58 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
SWD and Trace Interface
Table 40. SWD and Trace Specifications
Spec ID#
Parameter
SID214
F_SWDCLK2
SID214L
F_SWDCLK2L
Description
Min
Typ
Max
Unit
Details / Conditions
1.7 V VDDD 3.6 V
–
–
25
MHz
LP mode.
VCCD = 1.1 V
1.7 V VDDD 3.6 V
–
–
12
MHz
ULP mode.
VCCD = 0.9 V
SID215
T_SWDI_SETUP T = 1/f SWDCLK
0.25 * T
–
–
ns
–
SID216
T_SWDI_HOLD T = 1/f SWDCLK
0.25 * T
–
–
ns
–
SID217
T_SWDO_VALID T = 1/f SWDCLK
–
–
0.5 * T
ns
–
SID217A T_SWDO_HOLD T = 1/f SWDCLK
1
–
–
ns
–
SID214T
F_TRCLK_LP1
With Trace Data setup/hold times of
2/1 ns respectively
–
–
75
MHz
LP Mode.
VDD = 1.1 V
SID215T
F_TRCLK_LP2
With Trace Data setup/hold times of
3/2 ns respectively
–
–
70
MHz
LP Mode.
VDD = 1.1 V
SID216T
F_TRCLK_ULP
With Trace Data setup/hold times of
3/2 ns respectively
–
–
25
MHz
ULP Mode.
VDD = 0.9 V
Min
Typ
Max
Unit
–
9
15
µA
Min
Typ
Max
Unit
Internal Main Oscillator
Table 41. IMO DC Specifications
Spec ID#
SID218
Parameter
IIMO1
Description
IMO operating current at 8 MHz
Details / Conditions
–
Table 42. IMO AC Specifications
Spec ID#
Parameter
Description
SID223
FIMOTOL1
Frequency variation centered on
8 MHz
–
–
±2
%
SID227
TJITR
Cycle-to-Cycle and Period jitter
–
±250
–
ps
Min
Typ
Max
Unit
–
0.3
0.7
µA
Min
Typ
Max
Unit
Details / Conditions
–
–
Internal Low-Speed Oscillator
Table 43. ILO DC Specification
Spec ID#
SID231
Parameter
IILO2
Description
ILO operating current at 32 kHz
Details / Conditions
–
Table 44. ILO AC Specifications
Spec ID#
Parameter
Description
SID234
TSTARTILO1
ILO startup time
–
–
SID236
TLIODUTY
SID237
FILOTRIM1
ILO Duty cycle
45
50
ILO frequency
28.8
32
Document Number: 002-21414 Rev. *M
Details / Conditions
µs
Startup time to 95% of
final frequency
55
%
–
36.1
kHz
7
Factory trimmed
Page 59 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Crystal Oscillator
Table 45. ECO Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
Block operating current with Cload up to
18 pF
–
800
1600
µA
Crystal frequency range
16
–
35
MHz
Block operating current with 32-kHz
crystal
–
0.38
1
µA
SID321E ESR32K
Equivalent Series Resistance
–
80
–
kΩ
–
SID322E PD32K
Drive level
–
–
1
µW
–
32-kHz frequency
–
32.768
–
kHz
–
MHz ECO DC Specifications
SID316
IDD_MHz
Max = 35 MHz,
Typ = 16 MHz
MHz ECO AC Specifications
SID317
F_MHz
–
kHz ECO DC Specification
SID318
IDD_kHz
–
kHz ECO AC Specification
SID319
F_kHz
SID320
Ton_kHz
SID320E FTOL32K
Startup time
–
–
500
ms
–
Frequency tolerance
–
50
250
ppm
–
Min
Typ
Max
Unit
External Clock
Table 46. External Clock Specifications
Spec ID#
Parameter
Description
Details / Conditions
SID305
EXTCLKFREQ
External Clock input Frequency
0
–
100
MHz
–
SID306
EXTCLKDUTY
Duty cycle; Measured at VDD/2
45
–
55
%
–
Min
Typ
Max
Unit
PLL
Table 47. PLL Specifications
Spec ID#
Parameter
Description
Details / Conditions
SID305P PLL_LOCK
Time to achieve PLL Lock
–
16
35
µs
–
SID306P PLL_OUT
Output frequency from PLL Block
–
–
150
MHz
–
SID307P PLL_IDD
PLL Current
–
0.55
1.1
mA
Typ at 100 MHz out.
SID308P PLL_JTR
Period Jitter
–
–
150
ps
100-MHz output
frequency
Min
Typ
Max
Unit
Clock Source Switching Time
Table 48. Clock Source Switching Time Specifications
Spec ID#
SID262
Parameter
TCLKSWITCH
Description
Clock switching from clk1 to clk2 in clock
periods[4]
–
–
Details / Conditions
4 clk1 +
–
periods
3 clk2
Note
4. As an example, if the clk_path[1] source is changed from the IMO to the FLL (see Figure 4) then clk1 is the IMO and clk2 is the FLL.
Document Number: 002-21414 Rev. *M
Page 60 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
FLL
Table 49. Frequency Locked Loop (FLL) Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
SID450
FLL_RANGE
Input frequency range.
0.001
–
100
MHz
Lower limit allows lock to
USB SOF signal (1 kHz).
Upper limit is for External
input.
SID451
FLL_OUT_DIV2
Output frequency range.
VCCD = 1.1 V
24.00
–
100.00
MHz
Output range of FLL
divided-by-2 output
SID451A
FLL_OUT_DIV2
Output frequency range.
VCCD = 0.9 V
24.00
–
50.00
MHz
Output range of FLL
divided-by-2 output
SID452
FLL_DUTY_DIV2 Divided-by-2 output; High or Low
47.00
–
53.00
%
–
SID454
FLL_WAKEUP
Time from stable input clock to 1%
of final value on deep sleep wakeup
–
–
7.50
µs
With IMO input, less than
10 °C change in
temperature while in Deep
Sleep, and Fout ≥ 50 MHz.
SID455
FLL_JITTER
Period jitter (1 sigma at 100 MHz)
–
–
35.00
ps
50 ps at 48 MHz, 35 ps at
100 MHz
SID456
FLL_CURRENT
CCO + Logic current
–
–
5.50
Min
Typ
Max
Unit
µA/MHz –
UDB
Table 50. UDB AC Specifications
Spec ID#
Parameter
Description
Details / Conditions
Data Path Performance
SID249
FMAX-TIMER
Max frequency of 16-bit timer in a
UDB pair
–
–
100
MHz
–
SID250
FMAX-ADDER
Max frequency of 16-bit adder in a
UDB pair
–
–
100
MHz
SID251
FMAX_CRC
Max frequency of 16-bit CRC/PRS
in a UDB pair
–
–
100
MHz
Max frequency of 2-pass PLD
function in a UDB pair
–
–
100
MHz
Prop. delay for clock in to data out
–
5
–
ns
–
–
–
PLD Performance in UDB
SID252
FMAX_PLD
–
Clock to Output Performance
SID253
TCLK_OUT_UDB1
UDB Port Adapter Specifications
Conditions: 10-pF load, 3-V VDDIO and VDDD
SID263
TLCLKDO
LCLK to Output delay
–
–
11
ns
LCLK is a selected clock;
for more information see
the TRM
SID264
TDINLCLK
Input setup time to LCLK rising edge
–
–
7
ns
–
SID265
TDINLCLKHLD
Input hold time from LCLK rising
edge
5
–
–
ns
–
SID266
TLCLKHIZ
LCLK to Output tristated
–
–
28
ns
–
SID267
TFLCLK
LCLK frequency
–
–
33
MHz
–
SID268
TLCLKDUTY
LCLK duty cycle (percentage high)
40%
–
60%
%
–
Document Number: 002-21414 Rev. *M
Page 61 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
USB
Table 51. USB Specifications (USB requires LP Mode 1.1-V Internal Supply)
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
USB Block Specifications
SID322U
Vusb_3.3
Device supply for USB operation
3.15
–
3.6
V
USB Configured
SID323U
Vusb_3
Device supply for USB operation
(functional operation only)
2.85
–
3.6
V
USB Configured
SID325U
Iusb_config
Device supply current in Active mode
–
8
–
mA
VDDD = 3.3 V
SID328
Isub_suspend
Device supply current in Sleep mode
–
0.5
–
mA
VDDD = 3.3 V, Device
connected
SID329
Isub_suspend
Device supply current in Sleep mode
–
0.3
–
mA
VDDD = 3.3 V, Device
disconnected
SID330U
USB_Drive_Res
USB driver impedance
28
–
44
Ω
Series resistors are on
chip
SID331U
USB_Pulldown
USB pull-down resistors in Host
mode
14.25
–
24.8
kΩ
–
SID332U
USB_Pullup_Idle
Idle mode range
900
–
1575
Ω
Bus idle
SID333U
USB_Pullup
Active mode
1425
–
3090
Ω
Upstream device
transmitting
QSPI
Table 52. QSPI Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
SMIF QSPI Specifications. All specs with 15-pF load.
SID390Q
Fsmifclock
SMIF QSPI output clock frequency
–
–
80
MHz
LP mode (1.1 V)
SID390QU
Fsmifclocku
SMIF QSPI output clock frequency
–
–
50
MHz
ULP mode (0.9 V).
Guaranteed by Char.
SID397Q
Idd_qspi
Block current in LP mode (1.1 V)
–
–
1900
µA
LP mode (1.1 V)
SID398Q
Idd_qspi_u
Block current in ULP mode (0.9 V)
–
–
590
µA
ULP mode (0.9 V)
SID391Q
Tsetup
Input data set-up time with respect to
clock capturing edge
4.5
–
–
ns
–
SID392Q
Tdatahold
Input data hold time with respect to
clock capturing edge
0
–
–
ns
–
SID393Q
Tdataoutvalid
Output data valid time with respect to
clock falling edge
–
–
3.7
ns
7.5-ns max for ULP
mode (0.9 V)
SID394Q
Tholdtime
Output data hold time with respect to
clock rising edge
3
–
–
ns
–
SID395Q
Tseloutvalid
Output Select valid time with respect to
clock rising edge
–
–
7.5
ns
15-ns max for ULP
mode (0.9 V)
SID396Q
Tselouthold
Output Select hold time with respect to
clock rising edge
0.5*
Tsclk
–
–
ns
Tsclk = Fsmifclk cycle
time
Document Number: 002-21414 Rev. *M
Page 62 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Audio Subsystem
Table 53. Audio Subsystem Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
PDM Specifications
SID400P
PDM_IDD1
PDM Active current, Stereo
operation, 1-MHz clock
–
175
–
µA
16-bit audio at 16 ksps
SID401
PDM_IDD2
PDM Active current, Stereo
operation, 3-MHz clock
–
600
–
µA
24-bit audio at 48 ksps
SID402
PDM_JITTER
RMS Jitter in PDM clock
–200
–
200
ps
–
SID403
PDM_CLK
PDM Clock speed
0.384
–
3.072
MHz
–
SID403A
PDM_BLK_CLK
PDM Block input clock
1.024
–
49.152
MHz
–
SID403B
PDM_SETUP
Data input set-up time to
PDM_CLK edge
10
–
–
ns
–
SID403C
PDM_HOLD
Data input hold time to PDM_CLK
edge
10
–
–
ns
–
SID404
PDM_OUT
Audio sample rate
8
–
48
ksps
–
SID405
PDM_WL
Word Length
16
–
24
bits
–
SID406
PDM_SNR
Signal-to-Noise Ratio
(A-weighted)
–
100
–
dB
PDM input, 20 Hz to
20 kHz BW
SID407
PDM_DR
Dynamic Range (A-weighted)
–
100
–
dB
20 Hz to 20 kHz BW,
–60 dB FS
SID408
PDM_FR
Frequency Response
–0.2
–
0.2
dB
DC to 0.45f. DC
Blocking filter off.
SID409
PDM_SB
Stop Band
–
0.566
–
f
–
SID410
PDM_SBA
Stop Band Attenuation
–
60
–
dB
–
SID411
PDM_GAIN
Adjustable Gain
–12
–
10.5
dB
PDM to PCM,
1.5 dB/step
SID412
PDM_ST
Startup time
–
48
–
–
32
WS (Word Select)
cycles
I2S Specifications. The same for LP and ULP modes unless stated otherwise.
SID413
I2S_WORD
Length of I2S Word
8
bits
–
Word Clock frequency in LP mode
–
–
192
kHz
12.288-MHz bit clock
with 32-bit word
SID414M I2S_WS_U
Word Clock frequency in ULP
mode
–
–
48
kHz
3.072-MHz bit clock
with 32-bit word
SID414A
I2S_WS_TDM
Word Clock frequency in TDM
mode for LP
–
–
48
kHz
Eight 32-bit channels
SID414X
I2S_WS_TDM_U
Word Clock frequency in TDM
mode for ULP
–
–
12
kHz
Eight 32-bit channels
SID414
I2S_WS
I2S Slave Mode
SID430
TS_WS
WS Setup Time to the Following
Rising Edge of SCK for LP Mode
5
–
–
ns
–
SID430U
TS_WS
WS Setup Time to the Following
Rising Edge of SCK for ULP Mode
11
–
–
ns
–
SID430A
TH_WS
WS Hold Time to the Following
Edge of SCK
TMCLK_SOC[5]
+5
–
–
ns
–
Note
5. TMCLK_SOC is the internal I2S master clock period.
Document Number: 002-21414 Rev. *M
Page 63 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Table 53. Audio Subsystem Specifications (continued)
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
TMCLK_SOC +
25
ns
Associated clock edge
depends on selected
polarity
SID432
TD_SDO
Delay Time of TX_SDO Transition
–
from Edge of TX_SCK for LP
(TMCLK_SOC +
mode
25)
SID432U
TD_SDO
Delay Time of TX_SDO Transition
–
from Edge of TX_SCK for ULP
(TMCLK_SOC +
mode
70)
–
TMCLK_SOC +
70
ns
Associated clock edge
depends on selected
polarity
SID433
TS_SDI
RX_SDI Setup Time to the
Following Edge of RX_SCK in Lp
Mode
5
–
–
ns
–
SID433U
TS_SDI
RX_SDI Setup Time to the
Following Edge of RX_SCK in
ULP mode
11
–
–
ns
–
SID434
TH_SDI
RX_SDI Hold Time to the Rising
Edge of RX_SCK
TMCLK_SOC +
5
–
–
ns
–
SID435
TSCKCY
TX/RX_SCK Bit Clock Duty Cycle
45
–
55
%
–
–
I2S Master Mode
SID437
TD_WS
WS Transition Delay from Falling
Edge of SCK in LP mode
–10
–
20
ns
–
SID437U
TD_WS_U
WS Transition Delay from Falling
Edge of SCK in ULP mode
–10
–
40
ns
–
SID438
TD_SDO
SDO Transition Delay from
Falling Edge of SCK in LP mode
–10
–
20
ns
–
SID438U
TD_SDO
SDO Transition Delay from
Falling Edge of SCK in ULP mode
–10
–
40
ns
–
SID439
TS_SDI
SDI Setup Time to the Associated
Edge of SCK
5
–
–
ns
Associated clock edge
depends on selected
polarity
SID440
TH_SDI
SDI Hold Time to the Associated
Edge of SCK
TMCLK_SOC +
5
–
–
ns
T is TX/RX_SCK Bit
Clock period.
Associated clock edge
depends on selected
polarity.
SID443
TSCKCY
SCK Bit Clock Duty Cycle
45
–
55
%
–
SID445
FMCLK_SOC
MCLK_SOC Frequency in LP
mode
1.024
–
98.304
MHz FMCLK_SOC =
8 * Bit-clock
SID445U
FMCLK_SOC_U
MCLK_SOC Frequency in ULP
mode
1.024
–
24.576
MHz
SID446
TMCLKCY
MCLK_SOC Duty Cycle
45
–
55
%
–
SID447
TJITTER
MCLK_SOC Input Jitter
–100
–
100
ps
–
Document Number: 002-21414 Rev. *M
FMCLK_SOC_U =
8 * Bit-clock
Page 64 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Smart I/O
Table 54. Smart I/O Specifications
Spec ID#
Parameter
Description
Min
Typ
Max
Unit
Details / Conditions
SID420
SMIO_BYP
Smart I/O Bypass delay
–
–
2
ns
–
SID421
SMIO_LUT
Smart I/O LUT prop delay
–
8
–
ns
–
Precision ILO (PILO)
Table 55. PILO Specifications
Min
Typ
Max
Unit
SID 430R IPILO
Spec ID#
Parameter
Operating current
Description
–
1.2
4
µA
–
Details / Conditions
SID431
F_PILO
PILO nominal frequency
–
32768
–
Hz
T = 25 °C
SID432R
ACC_PILO
PILO accuracy with periodic calibration –500
–
500
ppm
–
JTAG Boundary Scan
Table 56. JTAG Boundary Scan
Spec ID#
Parameter
Description Min Typ Max
Units
JTAG Boundary Scan Parameters
JTAG Boundary Scan Parameters for 1.1 V (LP) Mode Operation:
SID468
TCKLOW
TCK LOW
52
–
–
ns
–
SID469
TCKHIGH
TCK HIGH
10
–
–
ns
–
SID470
TCK_TDO
TCK falling edge to output valid
–
40
ns
–
SID471
TSU_TCK
Input valid to TCK rising edge
12
–
–
ns
–
SID472
TCk_THD
Input hold time to TCK rising edge
10
–
–
ns
–
SID473
TCK_TDOV
TCK falling edge to output valid
(High-Z to Active).
40
–
–
ns
–
SID474
TCK_TDOZ
TCK falling edge to output valid (Active
to High-Z).
40
–
–
ns
–
JTAG Boundary Scan Parameters for 0.9 V (ULP) Mode Operation:
SID468A
TCKLOW
TCK low
102
–
–
ns
–
SID469A
TCKHIGH
TCK high
20
–
–
ns
–
SID470A
TCK_TDO
TCK falling edge to output valid
–
80
ns
–
SID471A
TSU_TCK
Input valid to TCK rising edge
22
–
–
ns
–
SID472A
TCk_THD
Input hold time to TCK rising edge
20
–
–
ns
–
SID473A
TCK_TDOV
TCK falling edge to output valid (high-Z
to active).
80
–
–
ns
–
SID474A
TCK_TDOZ
TCK falling edge to output valid (active
to high-Z).
80
–
–
ns
–
Document Number: 002-21414 Rev. *M
Page 65 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Ordering Information
Table 57 lists the CY8C61x6 and CY8C61x7 part numbers and features. All devices include QSPI SMIF, ADC, DAC, 9 SCBs, USB-FS,
32 TCPWMs, 2 PDMs, and I2S. See also the product selector guide.
61
CPU Speed (CM4)
CPU Speed
(CM0+)
Single CPU/Dual
CP
ULP/LP
Flash (KB)
SRAM (KB)
No of CTBMs
No. of UDBs
CapSense
GPIOs
CRYPTO
PDM-PCM
SIMO BUCK
Package
60
MPN
Family
Table 57. Marketing Part Numbers
CY8C6036BZI-F04
150
–
Single
LP
512
128
0
0
No
100
No
No
No
124-BGA
CY8C6016BZI-F04
50
–
Single
ULP
512
128
0
0
No
100
No
No
No
124-BGA
CY8C6116BZI-F54
50
–
Single
ULP
512
128
1
12
Yes
100
Yes
Yes
Yes
124-BGA
CY8C6136BZI-F14
150
–
Single
LP
512
128
0
0
Yes
100
No
Yes
Yes
124-BGA
CY8C6136BZI-F34
150
–
Single
LP
512
128
1
12
Yes
100
No
Yes
Yes
124-BGA
CY8C6137BZI-F14
150
–
Single
LP
1024
288
0
0
Yes
100
No
Yes
Yes
124-BGA
CY8C6137BZI-F34
150
–
Single
LP
1024
288
1
12
Yes
100
No
Yes
Yes
124-BGA
CY8C6137BZI-F54
150
–
Single
LP
1024
288
1
12
Yes
100
Yes
Yes
Yes
124-BGA
CY8C6117BZI-F34
50
–
Single
ULP 1024
288
1
12
Yes
100
No
Yes
Yes
124-BGA
CY8C6136FTI-F42
150
–
Single
128
0
0
Yes
62
Yes
Yes
Yes
Thin
LP
512
CY8C6136FDI-F42
150
–
Single
LP
512
128
0
0
Yes
62
Yes
Yes
Yes
80-WLCSP
CY8C6137FDI-F02
150
–
Single
LP
1024
288
0
0
No
62
No
Yes
Yes
80-WLCSP
CY8C6117FDI-F02
50
–
Single
ULP 1024
288
0
0
No
62
No
Yes
Yes
80-WLCSP
Document Number: 002-21414 Rev. *M
Page 66 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
PSoC 6 MPN Decoder
CY XX 6 A B C DD E - FF G H I JJ K L
Field
CY
XX
6
A
B
Description
Cypress
Firmware
Architecture
Line
Speed
Values
CY
8C
Standard
B0
“Secure Boot” v1
S0
“Standard Secure” AWS
6
PSoC 6
0
Value
1
Programmable
2
Performance
3
Connectivity
4
Secured
2
100 MHz
3
150 MHz
4
150/50 MHz
0-3
C
Memory Size
(Flash/SRAM)
Meaning
Field
Description
Cypress
Reserved
4
256K/128K
5
512K/256K
6
512K/128K
7
1024K/288K
8
1024K/512K
9
Reserved
A
2048K/1024K
Values
C
E
FF
Temperature Range
Feature Code
I
Industrial
Q
Extended Industrial
Cypress internal
S2-S6
BL
G
CPU Core
H
Attributes Code
I
GPIO count
JJ
Engineering sample
(optional)
K
Die Revision
(optional)
L
Tape/Reel Shipment
(optional)
Meaning
Consumer
Integrated Bluetooth LE
F
Single Core
D
Dual Core
0–9
Feature set
1
31–50
2
51–70
3
71–90
4
91–110
ES
Engineering samples or
not
Base
A1–A9
T
Die revision
Tape and Reel shipment
AZ, AX TQFP
DD
Package
LQ
QFN
BZ
BGA
FM
M-CSP
FN, FD,
WLCSP
FT
Document Number: 002-21414 Rev. *M
Page 67 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Packaging
This product line is offered in 124-BGA[6] and 80-ball WLCSP packages in 0.43 mm and 0.33 mm[6] heights. The 124-BGA package
qualification is in process.
Table 58. Package Dimensions
Spec ID#
Package
PKG_1
124-BGA
PKG_2
80-WLCSP
PKG_3
Description
Package Drawing Number
124-BGA, 9 mm 9 mm 1 mm height with 0.65-mm pitch
001-97718
80-WLCSP, 3.7 mm 3.2 mm 0.43 mm height with 0.35-mm pitch
002-20310
Thin 80-WLCSP Thin 80 -WLCSP, 3.7 mm 3.3 mm 0.33mm height with 0.35-mm pitch
002-23411
Table 59. Package Characteristics
Parameter
Description
Conditions
Min
Typ
Max
Unit
TA
Operating ambient temperature
–
–40
25
85
°C
TJ
Operating junction temperature
–
–40
–
100
°C
TJA
Package JA (124-BGA)
–
–
36.2
–
°C/watt
TJC
Package JC (124-BGA)
–
–
15
–
°C/watt
TJA
Package JA (80-WLCSP)
–
–
20.4
–
°C/watt
TJC
Package JC (80-WLCSP)
–
–
0.2
–
°C/watt
TJA
Package JA (Thin 80-WLCSP)
–
–
20.4
–
°C/watt
TJC
Package JC (Thin 80-WLCSP)
–
–
0.2
–
°C/watt
Table 60. Solder Reflow Peak Temperature
Package
Maximum Peak Temperature
Maximum Time at Peak Temperature
All
260 °C
30 seconds
Table 61. Package Moisture Sensitivity Level (MSL), IPC/JEDEC J-STD-2
Package
MSL
124-BGA
MSL 3
80-WLCSP Packages
MSL 1
Note
6. The 124-BGA and Thin 80-WLCSP packages are in the process of qualification.
Document Number: 002-21414 Rev. *M
Page 68 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Figure 19. 124-BGA 9.0 × 9.0 ×1.0 mm
001-97718 *B
Document Number: 002-21414 Rev. *M
Page 69 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Figure 20. 80-Ball WLCSP 3.676 × 3.190 × 0.467 mm
DIMENSIONS
NOTES
SYMBOL
MIN.
NOM.
A
0.387
0.427
A1
0.122
1. ALL DIMENSIONS ARE IN MILLIMETERS.
0.467
0.182
3.676 BSC
D
E
3.190 BSC
D1
3.031 BSC
E1
2.450 BSC
n
Øb
MAX.
80
0.188
0.218
eD
0.303 BSC
eE
0.350 BSC
0.248
002-20310 *A
Document Number: 002-21414 Rev. *M
Page 70 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Figure 21. Thin 80-Ball WLCSP 3.676 × 3.190 × 0.33 mm
6
6
7
5
NOTES:
DIMENSIONS
SYMBOL
1. ALL DIMENSIONS ARE IN MILLIMETERS.
MIN
NOM
MAX
A
-
-
0.33
A1
0.081
-
-
2. SOLDER BALL POSITION DESIGNATION PER JEP95, SECTION 3, SPP-020.
3. "e" REPRESENTS THE SOLDER BALL GRID PITCH.
4. SYMBOL "MD" IS THE BALL MATRIX SIZE IN THE "D" DIRECTION.
SYMBOL "ME" IS THE BALL MATRIX SIZE IN THE "E" DIRECTION.
D
3.676 BSC
E
3.190 BSC
D1
3.031 BSC
E1
2.450 BSC
MD
11
ME
15
DEFINE THE POSITION OF THE CENTER SOLDER BALL IN THE OUTER ROW.
N
80
WHEN THERE IS AN ODD NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" OR "SE" = 0.
Øb
0.1035
0.1150
eD
0.303 BSC
eE
0.350 BSC
SD
0.00 BSC
SE
0.00 BSC
N IS THE NUMBER OF POPULATED SOLDER BALL POSITIONS FOR MATRIX
SIZE MD X ME.
5. DIMENSION "b" IS MEASURED AT THE MAXIMUM BALL DIAMETER IN A
PLANE PARALLEL TO DATUM C.
6. "SD" AND "SE" ARE MEASURED WITH RESPECT TO DATUMS A AND B AND
0.1265
WHEN THERE IS AN EVEN NUMBER OF SOLDER BALLS IN THE OUTER ROW,
"SD" = eD/2 AND "SE" = eE/2.
7. A1 CORNER TO BE IDENTIFIED BY CHAMFER, LASER OR INK MARK,
METALIZED MARK, INDENTATION OR OTHER MEANS.
8. JEDEC SPECIFICATION NO. REF. : N/A
002-23411 **
Document Number: 002-21414 Rev. *M
Page 71 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Acronyms
Acronym
Description
3DES
triple DES (data encryption standard)
ADC
analog-to-digital converter
AES
Acronym
FS
Description
full-speed
GND
Ground
advanced encryption standard
GPIO
general-purpose input/output, applies to a PSoC
pin
AHB
AMBA (advanced microcontroller bus architecture)
high-performance bus, an Arm data transfer bus
HMAC
Hash-based message authentication code
HSIOM
high-speed I/O matrix
AMUX
analog multiplexer
I/O
input/output, see also GPIO, DIO, SIO, USBIO
AMUXBUS
analog multiplexer bus
API
application programming interface
I S
Arm®
advanced RISC machine, a CPU architecture
IC
integrated circuit
BGA
ball grid array
IDAC
current DAC, see also DAC, VDAC
BOD
brown-out detect
IDE
integrated development environment
CAD
computer aided design
ILO
internal low-speed oscillator, see also IMO
CCO
current controlled oscillator
IMO
internal main oscillator, see also ILO
CM0+
Cortex-M0+, an Arm CPU
INL
integral nonlinearity, see also DNL
CM4
Cortex-M4, an Arm CPU
IoT
internet of things
CMAC
cipher-based message authentication code
IPC
inter-processor communication
CMOS
complementary metal-oxide-semiconductor, a
process technology for IC fabrication
IRQ
interrupt request
ISR
interrupt service routine
CMRR
common-mode rejection ratio
JTAG
Joint Test Action Group
CPU
central processing unit
LCD
liquid crystal display
CRC
cyclic redundancy check, an error-checking
protocol
LIN
Local Interconnect Network, a communications
protocol
CSD
CapSense Sigma-Delta
LP
low power
CSX
Cypress mutual capacitance sensing method. See
also CSD
LS
low-speed
DAC
digital-to-analog converter, see also IDAC, VDAC
DAP
debug access port
DES
data encryption standard
DMA
direct memory access, see also TD
DNL
differential nonlinearity, see also INL
DSI
digital system interconnect
DU
data unit
ECC
elliptic curve cryptography
ECO
external crystal oscillator
EEPROM
electrically erasable programmable read-only
memory
2
Inter-Integrated Circuit, a communications protocol
2
inter-IC sound
I C, or IIC
LUT
lookup table
LVD
low-voltage detect, see also LVI
LVTTL
low-voltage transistor-transistor logic
MAC
multiply-accumulate
M-CSP
molded chip scale package
MCU
microcontroller unit
MCWDT
multi-counter watchdog timer
MISO
master-in slave-out
MMIO
memory-mapped input output
MOSI
master-out slave-in
MPU
memory protection unit
moisture sensitivity level
EMI
electromagnetic interference
MSL
ESD
electrostatic discharge
Msps
million samples per second
ETM
embedded trace macrocell
MTB
micro trace buffer
FIFO
first-in, first-out
MUL
multiplier
FLL
frequency locked loop
NC
no connect
floating-point unit
NMI
nonmaskable interrupt
FPU
Document Number: 002-21414 Rev. *M
Page 72 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Acronym
Description
Acronym
Description
NVIC
nested vectored interrupt controller
SWO
single wire output
OTP
one-time programmable
SWV
serial-wire viewer
OVT
overvoltage tolerant
TCPWM
timer, counter, pulse-width modulator
PASS
programmable analog subsystem
TDM
time division multiplexed
PCB
printed circuit board
TQFP
thin quad flat package
PCM
pulse code modulation
TRM
technical reference manual
PDM
pulse density modulation
TRNG
true random number generator
PHY
physical layer
TX
transmit
PICU
port interrupt control unit
UART
PLL
phase-locked loop
Universal Asynchronous Transmitter Receiver, a
communications protocol
PMIC
power management integrated circuit
UDB
universal digital block
POR
power-on reset
ULP
ultra-low power
PPU
peripheral protection unit
USB
Universal Serial Bus
WCO
watch crystal oscillator
PRNG
pseudo random number generator
PSoC®
Programmable System-on-Chip™
PSRR
power supply rejection ratio
PWM
pulse-width modulator
QD
quadrature decoder
QSPI
quad serial peripheral interface
RAM
random-access memory
RISC
reduced-instruction-set computing
RMS
root-mean-square
ROM
read-only memory
RSA
Rivest–Shamir–Adleman, a public-key cryptography algorithm
RTC
real-time clock
RX
receive
S/H
sample and hold
SAR
successive approximation register
SARMUX
SAR ADC multiplexer bus
SCB
serial communication block
SFlash
supervisory flash
SHA
secure hash algorithm
SINAD
signal to noise and distortion ratio
SNR
signal-to-noise ration
SOF
start of frame
SPI
Serial Peripheral Interface, a communications
protocol
SRAM
static random access memory
SROM
supervisory read-only memory
SRSS
system resources subsystem
SWD
serial wire debug, a test protocol
SWJ
serial wire JTAG
Document Number: 002-21414 Rev. *M
WDT
watchdog timer
WIC
wakeup interrupt controller
WLCSP
wafer level chip scale package
XIP
execute-in-place
XRES
external reset input pin
Page 73 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Document Conventions
Unit of Measure
Table 62. Unit of Measure (continued)
Table 62. Unit of Measure
Symbol
Symbol
Unit of Measure
Unit of Measure
µH
microhenry
microsecond
°C
degrees Celsius
µs
dB
decibel
µV
microvolt
fF
femto farad
µW
microwatt
Hz
hertz
mA
milliampere
KB
1024 bytes
ms
millisecond
kbps
kilobits per second
mV
millivolt
khr
kilohour
nA
nanoampere
kHz
kilohertz
ns
nanosecond
k
kilo ohm
nV
nanovolt
ksps
kilosamples per second
ohm
LSB
least significant bit
pF
picofarad
Mbps
megabits per second
ppm
parts per million
MHz
megahertz
ps
picosecond
M
mega-ohm
s
second
Msps
megasamples per second
sps
samples per second
µA
microampere
sqrtHz
square root of hertz
microfarad
V
volt
µF
Document Number: 002-21414 Rev. *M
Page 74 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Revision History
Description Title: PSoC 6 MCU: CY8C61x6, CY8C61x7 Datasheet
Document Number: 002-21414
Submission
Revision
ECN
Description of Change
Date
**
5896512
09/27/2017 New datasheet
*A
5956122
11/03/2017 Corrected typo in Development Support.
Updated Table 5.
Updated SID84 description and conditions.
Updated Table 13.
*B
5974156
11/29/2017 Updated max value for SID223.
Updated min and max values of SID432R.
Updated Table 39.
Updated Revision History
Updated Active CPU power consumption in 32-bit Dual Core CPU Subsystem.
Updated Table 5, Table 6, Table 16, Table 21, Table 32, and Table 35.
Updated min value for SID4B and SID291.
Updated Fixed UART AC specifications.
*C
6065337
02/10/2018
Updated SID190 and removed SID194.
Removed SID226.
Updated max value for SID234.
Updated Revision History.
Corrected typo in the block diagram.
*D
6190455
05/29/2018
Updated 80-ball WLCSP package diagram.
Updated Features and Ordering Information.
Updated IMO Clock Source: Corrected the IMO tolerance and locking information and
*E
6215538
06/26/2018 TCPWM and PLL description errors.
Updated Packaging: Added Thin 80-WLCSP package dimension and package diagram.
Updated Table 39, Table 40, and Table 42.
Removed Preliminary document status.
Corrected units usage throughout the document.
Added note explaining Fc for the SID.TCPWM.4 parameter.
Updated Features, CPU, Flash, ILO Clock Source, Watchdog Timer (WDT), Serial Communication Blocks (SCB), Ordering Information, Packaging, and Acronyms.
*F
6221434
09/08/2018 Removed “Errata” section.
Updated package diagram (spec 001-97718 *A to *B) in Packaging.
Updated Figure 2.
Added a note in Table 2.
Updated Table 5, Table 6 through Table 8, Table 15, Table 18, Table 21, Table 30, Table 32,
and Table 36.
Updated the title.
*G
6658244
09/20/2019 Updated Ordering Information.
Added UDB in Acronyms.
Updated Features.
*H
6757930
12/20/2019 Updated Blocks and Functionality and Functional Description.
Updated Pinouts and Power Supply Considerations.
Updated Features.
Updated Functional Description.
*I
6842918
03/31/2020
Updated Pinouts.
Updated PSoC 6 MPN Decoder.
Updated Development Ecosystem, GPIO, and LCD sections.
*J
6898008
06/22/2020 Added External Crystal Oscillators.
Updated Errata
Document Number: 002-21414 Rev. *M
Page 75 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
Description Title: PSoC 6 MCU: CY8C61x6, CY8C61x7 Datasheet
Document Number: 002-21414
Updated Flexible Clocking Options, Block Diagram, CPUs, Clock System, and SID431.
Updated Universal Digital Blocks (UDBs), UDB Port Adapter Specifications Conditions.
Added InterProcessor Communication (IPC).
Updated Analog Subsystem diagram.
Updated the XRES bullet in Reset, updated SID15 Description and Conditions, and
Power-on-Reset specifications table.
Updated ModusToolbox Software.
Updated Clocking Diagram.
Removed Secure Boot information.
Updated Security Built into Platform Architecture, PSoC 6 MCU Resources, Protection
*K
7004924
11/09/2020
Units, and Boot Code.
Updated Power Supply Considerations.
Added footnote to TMCLK_SOC specs.
Updated Opamp Specifications.
Updated SID7A conditions, SID7C Description, SID7D description, and SID8 conditions.
Added spec SID468 - SID474, and SID468A - SID474A.
Updated Audio Spec SID408.
Updated Ordering Information.
Integrated ECO erratum into External Crystal Oscillators. Added ECO Usage Guidelines
table.
Added Table 12 and Figure 16.
Updated conditions for SID316 and updated description of SID319.
Changed BLE references to Bluetooth LE.
*L
7094508
02/26/2021
Updated Security terminology to Infineon standards.
Removed the Errata section; incorporated errata into the GPIO, ADC, and CapSense
sections.
Added opamp graphs (Figure 17 and Figure 18).
*M
7173987
06/30/2021
Corrected typo in Figure 12 and Figure 14.
Document Number: 002-21414 Rev. *M
Page 76 of 77
PSoC 6 MCU: CY8C61x6,
CY8C61x7 Datasheet
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Document Number: 002-21414 Rev. *M
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