CY8C9540-24PVXI

Cypress Semiconductor CY8C9520, CY8C9540, and CY8C9560 Preliminary Data Sheet 20-, 40-, and 60-Bit I/O Expander with EEPROM Features ■ ■ Overview The CY8C95xx is a multi-port I/O expander with on-board useravailable EEPROM and several PWM outputs. All devices in this family operate identically but differ in I/O pins, number of PWMs, and internal EEPROM size. The CY8C95xx operates as two I2C slave devices. The first device is a multi-port I/O expander (single I2C address to access all ports via registers). The second device is a serial EEPROM. Dedicated configuration registers can be used to disable the EEPROM. The EEPROM utilizes 2-byte addressing to support the 28-Kbyte EEPROM address space. The selected device is defined by the most significant bits of the I2C address or by specific register addressing. The I/O expander's data pins can be independently assigned as inputs, outputs, quasi-bidirectional input/outputs or PWM ouputs. The individual data pins can be configured as open drain/collector, strong drive (10 mA source, 25 mA sink), resistively pulled-up/-down, or high-impedance. The factory default configuration is pulled-up internally. The system master writes to the I/O configuration registers via the I2C bus. Configuration and output register settings can be stored as user defaults in a dedicated section of the EEPROM. If user defaults have been stored in EEPROM, they are restored to the ports at power-up. While this device can share the bus with SMBus devices, it can only communicate with I2C-masters. There is one dedicated pin that is configured as an interrupt output (INT) and can be connected to the interrupt logic of the system master. This signal can inform the system master that there is incoming data on its ports or that the PWM output state was changed. The EEPROM is byte-readable and supports byte-by-byte writing. A pin can be configured as an EEPROM Write Disable (WD) input that blocks write operations when set high. The configuration registers can also disable EEPROM operations. The CY8C95xx has one fixed address pin (A0) and up to six additional pins (A1-A6) which allow up to 128 devices to share a common two-wire I2C data bus. The Extendable Soft Addressing algorithm provides the option to choose the number of pins needed to assign the desired address. Pins not used for address bits are available as GPIO pins. I2C™ interface logic electrically compatible with SMBus. Up to 20 (CY8C9520), 40 (CY8C9540) or 60 (CY8C9560) I/O data pins independently configurable as inputs, outputs, bi-directional input/outputs or PWM outputs. 4/8/16 PWM sources with 8-bit resolution. Extendable Soft Addressing™ algorithm allowing flexible I2C-address configuration. Internal 3-/11-/27-Kbyte EEPROM. Storage of user defaults and I/O port settings in the internal EEPROM. Optional EEPROM Write Disable (WD) input. Interrupt output indicates input pin level changes and pulse width modulator (PWM) state changes. Internal power-on reset (POR). ■ ■ ■ ■ ■ ■ ■ WD EEPROM User Settings Area User Available Area Clocks 32 kHz 24 MHz 1.5 MHz GPort 1 GPort 0 8 Bit I/O 93.75 kHz Divider (1-255) GPort 2 5 Bit I/O 3 Bit I/O or A4-A6 4 Bit I/O or A1-A3, W PWM 0 Control Unit GPort 3 8 Bit I/O PWM 15 GPort 7 8 Bit I/O SCL SDA V dd V ss Pow er-on-Reset INT A0 Figure 1-1. Top Level Block Diagram August 17, 2005 © Cypress Semiconductor Corp. 2005 — Document No. 38-12036 Rev. *A 1 CY8C95xx Preliminary Data Sheet Overview There are 4 (CY8C9520), 8 (CY8C9540) or 16 (CY8C9560) independently configurable 8-bit PWMs. These PWMs are denoted as PWM0-PWM15. Each PWM can be clocked by one of six available clock sources. 7 Drive Mode Registers GPortx Architecture The figure titled “Top Level Block Diagram” on page 1 illustrates the device block diagram. The main blocks include the control unit, PWMs, EEPROM and I/O ports. The control unit executes commands received from the I2C bus and transfers data between other bus devices and the master device. The on-chip EEPROM can be separated conventionally into two regions. The first region is designed to store data and is available for byte-wide read/writes via the I2C bus. It is possible to prevent write operations by setting the WD pin to high. All EEPROM operations can be blocked by configuration register settings. The second region allows the user to store the port and PWM default settings using special commands. These defaults will be automatically reloaded and processed after device power-on. The number of I/O lines and PWM sources is presented in the following table. Table 1-1. GPIO Availability Port GPort 0 GPort 1 GPort 2 GPort 3 GPort 4 GPort 5 GPort 6 GPort 7 PWMs CY8C9520 8 bit 5-8 bit∗ 0-4 bit∗ 4 CY8C9540 8 bit 5-8∗ bit 0-4∗ bit 8 bit 8 bit 4 bit 8 CY8C9560 8 bit 5-8 bit∗ 0-4 bit∗ 8 bit 8 bit 8 bit 8 bit 8 bit 16 DriveMode Pull-Up Output Register Data DriveMode High-Z PWMs Select PWM Interrupt Status Input Register Interrupt Mask 8 Bit I/O Pin Direction Inversion Figure 1-2. Logical Structure of the I/O Port The Port Input and Output registers are separated. When the Output register is written, the data is sent to the external pins. When the Input register is read, the external pin logic levels are captured and transferred. As a result, the read data can be different from written Output register data. This allows for implementation of a quasi-bidirectional input-output mode, when the corresponding binary digit is configured as pulled-up/down output. Each GPort has an Interrupt Mask register and an Interrupt Status register. Each high bit in the Interrupt Status register signals that there has been a change in the corresponding input line since the last read of that Interrupt Status register. The Interrupt Status register is cleared after each read. The Interrupt Mask register enables/disables activation of the INT line when input levels are changed. Each high in the Interrupt Mask register masks (disables) an interrupt generated from the corresponding input line. * This port contains configuration-dependant GPIO lines or A1-A6 and WD lines. There are four pins on GPort 2 and three on GPort 1 that can be used as general purpose I/O or EEPROM Write Disable (WD) and I2C-address input (A1-A6), depending on configuration settings. The figure titled “Logical Structure of the I/O Port” shows the single port logical structure. The Port Drive Mode register gives the option to select one of seven available modes for each pin separately: pulled-up/-down, open drain high/low, strong drive fast/slow, or high-impedance. By default these configuration registers store values setting I/O pins to pulled-up. The Invert register allows for inversion of the logic of the Input registers separately for each pin. The Select PWM register allows pins to be assigned as PWM outputs. All of these configuration registers are read/writable using corresponding commands in the multi-port device. Applications Each GPIO pin can be used to monitor and control various board-level devices, including LEDs and system intrusion detection devices. The on-board EEPROM can be used to store information such as error codes or board manufacturing data for read-back by application software for diagnostic purposes. August 17, 2005 Document No. 38-12036 Rev. *A 2 CY8C95xx Preliminary Data Sheet Overview Device Access Addressing Following a start condition, the I2C master device sends a byte to address an I2C slave. This address selects the device to be accessed in the CY8C95xx. By default there are two possible address formats in binary representation: 010000A0X and 101000A0X. The first is used to access the multi-port device and the second to access the EEPROM. If additional address lines (A1-A6) are used then the Device Addressing Table 1-2 defines the device addresses. This addressing method uses a technique called Extendable Soft Addressing™, described later in this document. Table 1-2. Device Addressing Multi-Port Device 01 0 0 0 0 0 A6 1 1 1 1 A5 A5 0 0 0 0 0 0 0 0 0 A2 0 A1 A1 A1 A1 A1 A1 A0 A0 A0 A0 A0 A0 A0 R/W R/W R/W R/W R/W R/W 1 1 1 1 1 1 0 0 0 0 0 A5 A5 EEPROM Device 1 1 1 1 A4 A4 A4 0 0 0 A3 A3 A3 A3 0 0 A2 A2 A2 A2 A2 0 A1 A1 A1 A1 A1 A1 A0 R/W A0 R/W A0 R/W A0 R/W A0 R/W A0 R/W A0 R/W Multi-Port I/O Device This device allows the user to set various configurations and I/O operations through internal registers. Each data transfer is preceded by the command byte. This byte is used as a pointer to a register that will receive or transmit data. Available registers are listed in Table 3-1, “The Device Register Address Map,” on page 11. A3 A2 A4 A3 A2 A4 A3 A2 A4 A3 A2 R/W A6 When all address lines A1-A6 are used, the device being accessed is defined by the first byte following the address in the write transaction. If the most significant bit (MSb) of this byte is ‘0’, this byte is treated as a command (register address) byte of the multi-port device. If the MSb is ‘1’, this byte is the first of a 2byte EEPROM address. In this case, the device will mask the MSb to determine the EEPROM address. Serial EEPROM Device EEPROM reading and writing operations require 2 bytes, AHI and ALO, which indicate which memory address to use. To read one or more bytes, the master device addresses the unit with a write cycle (= 0) to send AHI followed by ALO, readdresses the unit with a read cycle (= 1), and reads one or more data bytes. Each data byte read will increment the internal address counter by one up to the end of the EEPROM address space. A read or write beyond the end of the EEPROM address space should result in a NAK response by the Port Expander. To write data to the EEPROM, the master device performs one write cycle, with the first two bytes being AHI followed by ALO. This is followed by one or more data bytes. In the case of block writing it is advisable to set the starting address on the beginning of the 64-byte boundary, for example 01C0h or 0080h, but this is not mandatory. When a 64-byte boundary is crossed in the EEPROM, the I2C clock is stretched while the device performs an EEPROM write sequence. If the end of available EEPROM space is reached, then further writes will be responded to with a NAK. Refer to Figure 2-2, “Memory Reading and Writing,” on page 10, which illustrates memory reading and writing procedures for the EEPROM device. August 17, 2005 Document No. 38-12036 Rev. *A 3 CY8C95xx Preliminary Data Sheet Overview Document Conventions Acronyms The following table lists the acronyms that are used in this document. Acronym AC DC EEPROM GPIO I/O MSb POR PWM alternating current direct current electrically erasable programmable read-only memory (E2) general purpose IO input/output most-significant bit power on reset pulse width modulator Description Table of Contents The following is a table of contents for the remainder of this data sheet. 2. Pinouts and Pin Descriptions ..................................................5 2.1 Pinouts ..............................................................................5 2.1.1 28-Pin Part Pinout ................................................5 2.1.2 48-Pin Part Pinout ................................................6 2.1.3 100-Pin Part Pinout ..............................................7 2.2 PIN Descriptions ................................................................9 2.2.1 Extendable Soft Addressing™ .............................9 2.2.2 Interrupt Pin (INT) .................................................9 2.2.3 Write Disable Pin (WD) ........................................9 2.2.4 External Reset Pin (XRES) ..................................9 2.2.5 Working with PWMs .............................................9 Register Reference .................................................................11 3.1 Register Mapping Table ..................................................11 3.2 Register Descriptions ......................................................12 3.2.1 Input Port Registers (00h - 07h) .........................12 3.2.2 Output Port Registers (08h - 0Fh) ......................12 3.2.3 Int. Status Port Registers (10h - 17h) .................12 3.2.4 Port Select Register (18h) ..................................12 3.2.5 Interrupt Mask Port Register (19h) .....................12 3.2.6 Select PWM Register (1Ah) ...............................12 3.2.7 Inversion Register (1Bh) .....................................12 3.2.8 Port Direction Register (1Ch) .............................12 3.2.9 Drive Mode Registers (1Dh-23h) ........................13 3.2.10 PWM Select Register (28h) ................................13 3.2.11 Config (29h) ........................................................13 3.2.12 Period Register (2Ah) .........................................13 3.2.13 Pulse Width Register (2Bh) ................................13 3.2.14 Divider Register (2Ch) ........................................13 3.2.15 Enable Register (2Dh) ........................................13 3.2.16 Device ID/Status Register (2Eh) ........................14 3.2.17 Command Register (30h) ...................................14 3.3 Commands Description ...................................................14 3.3.1 Store Config to E2 POR Defaults Cmd (01h) .....14 3.3.2 Restore Factory Defaults Cmd (02h) ..................14 3.3.3 Write E2 POR Defaults Cmd (03h) .....................14 3.3.4 Read E2 POR Defaults Cmd (04h) ....................15 3.3.5 Write Device Config Cmd (05h) ..........................15 3.3.6 Read Device Config Cmd (06h) .........................15 3.3.7 Reconfigure Device Cmd (07h) ..........................15 Electrical Specifications .........................................................16 4.1 Absolute Maximum Ratings .............................................16 4.2 Operating Temperature ...................................................17 4.3 DC Electrical Characteristics ...........................................17 4.3.1 DC Chip-Level Specifications .............................17 4.3.2 DC Programming Specifications ........................18 4.3.3 DC General Purpose I/O Specifications .............18 4.4 AC Electrical Characteristics ...........................................19 4.4.1 AC General Purpose I/O Specifications .............19 4.4.2 AC PWM Output Jitter Specifications .................19 4.4.3 AC I2C Specifications .........................................20 Packaging Information ...........................................................21 5.1 Packaging Dimensions ....................................................21 5.2 Thermal Impedances .......................................................23 5.3 Solder Reflow Peak Temperature ...................................23 Ordering Information ..............................................................24 6.1 Ordering Code Definitions ...............................................24 Sales and Service Information ...............................................25 7.1 Revision History ..............................................................25 7.2 Copyrights and Code Protection .....................................25 3. Units of Measure A units of measure table is located in the Electrical Specifications section. Table 4-1, “Units of Measure,” on page 16 lists all the abbreviations used in Section 4. Numeric Naming Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal. 4. 5. 6. 7. August 17, 2005 Document No. 38-12036 Rev. *A 4 2. Pinouts and Pin Descriptions This chapter describes, lists, and illustrates the CY8C95xx device pins and pinout configurations, along with application examples. 2.1 2.1.1 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pinouts 28-Pin Part Pinout CY8C9520 28-Pin Device GPort0_Bit0_PWM3 GPort0_Bit1_PWM1 GPort0_Bit2_PWM3 GPort0_Bit3_PWM1 GPort0_Bit4_PWM3 GPort0_Bit5_PWM1 GPort0_Bit6_PWM3 GPort0_Bit7_PWM1 Vss I2C Serial Clock (SCL) I2C Serial Clock (SDA) GPort2_Bit3_PWM3/A1 A0 Vss The CY8C95xx device is available in a variety of packages, which are listed and illustrated in the following tables. Table 2-1. 28-Pin Part Pinout (SSOP) Pin Name GPort0_Bit0_PWM3 GPort0_Bit1_PWM1 GPort0_Bit2_PWM3 GPort0_Bit3_PWM1 GPort0_Bit4_PWM3 GPort0_Bit5_PWM1 GPort0_Bit6_PWM3 GPort0_Bit7_PWM1 VSS I2C Serial Clock (SCL) I2C Serial Data (SDA) GPort2_Bit3_PWM3/A1 A0 VSS GPort2_Bit2_PWM0/WD INT GPort2_Bit1_PWM0/A2 GPort2_Bit0_PWM2/A3 XRES GPort1_Bit7_PWM0/A4 GPort1_Bit6_PWM2/A5 GPort1_Bit5_PWM0/A6 GPort1_Bit4_PWM2 GPort1_Bit3_PWM0 GPort1_Bit2_PWM2 GPort1_Bit1_PWM0 GPort1_Bit0_PWM2 Vdd Description Port 0, Bit 0, PWM 3. Port 0, Bit 1, PWM 1. Port 0, Bit 2, PWM 3. Port 0, Bit 3, PWM 1. Port 0, Bit 4, PWM 3. Port 0, Bit 5, PWM 1. Port 0, Bit 6, PWM 3. Port 0, Bit 7, PWM 1. Ground connection. I2C Clock. I2C Data. Port 2, Bit 3, PWM 3, Address 1. Address 0. Ground connection. Port 2, Bit 2, PWM 0, E2 Write Disable. Port 2, Bit 1, PWM 0, Address 2. Port 2, Bit 0, PWM 2, Address 3. Active high external reset with internal pull down. Port 1, Bit 7, PWM 0, Address 4. Port 1, Bit 6, PWM 2, Address 5. Port 1, Bit 5, PWM 0, Address 6. Port 1, Bit 4, PWM 2. Port 1, Bit 3, PWM 0. Port 1, Bit 2, PWM 2. Port 1, Bit 1, PWM 0. Port 1, Bit 0, PWM 2. Supply voltage. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd GPort1_Bit0_PWM2 GPort1_Bit1_PWM0 GPort1_Bit2_PWM2 GPort1_Bit3_PWM0 GPort1_Bit4_PWM2 GPort1_Bit5_PWM0/A6 GPort1_Bit6_PWM2/A5 GPort1_Bit7_PWM0/A4 XRES GPort2_Bit0_PWM2/A3 GPort2_Bit1_PWM0/A2 INT GPort2_Bit2_PWM0/WD August 17, 2005 Document No. 38-12036 Rev. *A 5 CY8C95xx Preliminary Data Sheet 2. Pinouts and Pin Descriptions 2.1.2 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 48-Pin Part Pinout CY8C9540 48-Pin Device Table 2-2. 48-Pin Part Pinout (SSOP) Pin Name GPort0_Bit0_PWM7 GPort0_Bit1_PWM5 GPort0_Bit2_PWM3 GPort0_Bit3_PWM1 GPort0_Bit4_PWM7 GPort0_Bit5_PWM5 GPort0_Bit6_PWM3 GPort0_Bit7_PWM1 GPort3_Bit0_PWM7 GPort3_Bit1_PWM5 GPort3_Bit2_PWM3 GPort3_Bit3_PWM1 VSS GPort3_Bit4_PWM7 GPort3_Bit5_PWM5 GPort3_Bit6_PWM3 GPort3_Bit7_PWM1 GPort5_Bit2_PWM3 GPort5_Bit3_PWM1 I2C Serial Clock (SCL) I2C Serial Data (SDA) GPort2_Bit3_PWM3/A1 A0 VSS GPort2_Bit2_PWM0/WD INT GPort2_Bit1_PWM4/A2 GPort2_Bit0_PWM6/A3 GPort5_Bit1_PWM0 GPort5_Bit0_PWM2 GPort4_Bit7_PWM0 GPort4_Bit6_PWM2 GPort4_Bit5_PWM4 GPort4_Bit4_PWM6 XRES GPort4_Bit3_PWM0 GPort4_Bit2_PWM2 GPort4_Bit1_PWM4 GPort4_Bit0_PWM6 GPort1_Bit7_PWM0/A4 GPort1_Bit6_PWM2/A5 GPort1_Bit5_PWM4/A6 GPort1_Bit4_PWM6 GPort1_Bit3_PWM0 GPort1_Bit2_PWM2 GPort1_Bit1_PWM4 GPort1_Bit0_PWM6 Vdd Description Port 0, Bit 0, PWM 7. Port 0, Bit 1, PWM 5. Port 0, Bit 2, PWM 3. Port 0, Bit 3, PWM 1. Port 0, Bit 4, PWM 7. Port 0, Bit 5, PWM 5. Port 0, Bit 6, PWM 3. Port 0, Bit 7, PWM 1. Port 3, Bit 0, PWM 7. Port 3, Bit 1, PWM 5. Port 3, Bit 2, PWM 3. Port 3, Bit 3, PWM 1. Ground connection. Port 3, Bit 4, PWM 7. Port 3, Bit 5, PWM 5. Port 3, Bit 6, PWM 3. Port 3, Bit 7, PWM 1. Port 5, Bit 2, PWM 3. Port 5, Bit 3, PWM 1. I2C Clock. I2C Data. Port 2, Bit 3, PWM 3, Address 1. Address 0. Ground connection. Port 2, Bit 2, PWM 0, E2 Write Disable. Port 2, Bit 1, PWM 4, Address 2. Port 2, Bit 0, PWM 6, Address 3. Port 5, Bit 1, PWM 0. Port 5, Bit 0, PWM 2. Port 4, Bit 7, PWM 0. Port 4, Bit 6, PWM 2. Port 4, Bit 5, PWM 4. Port 4, Bit 4, PWM 6. Active high external reset with internal pull down. Port 4, Bit 3, PWM 0. Port 4, Bit 2, PWM 2. Port 4, Bit 1, PWM 4. Port 4, Bit 0, PWM 6. Port 1, Bit 7, PWM 0, Address 4. Port 1, Bit 6, PWM 2, Address 5. Port 1, Bit 5, PWM 4, Address 6. Port 1, Bit 4, PWM 6. Port 1, Bit 3, PWM 0. Port 1, Bit 2, PWM 2. Port 1, Bit 1, PWM 4. Port 1, Bit 0, PWM 6. Supply voltage. GPort0_Bit0_PWM7 GPort0_Bit1_PWM5 GPort0_Bit2_PWM3 GPort0_Bit3_PWM1 GPort0_Bit4_PWM7 GPort0_Bit5_PWM5 GPort0_Bit6_PWM3 GPort0_Bit7_PWM1 GPort3_Bit0_PWM7 GPort3_Bit1_PWM5 GPort3_Bit2_PWM3 GPort3_Bit3_PWM1 Vss GPort3_Bit4_PWM7 GPort3_Bit5_PWM5 GPort3_Bit6_PWM3 GPort3_Bit7_PWM1 GPort5_Bit2_PWM3 GPort5_Bit3_PWM1 I2C Serial Clock (SCL) I2C Serial Data (SDA) GPort2_Bit3_PWM3/A1 A0 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Vdd GPort1_Bit0_PWM6 GPort1_Bit1_PWM4 GPort1_Bit2_PWM2 GPort1_Bit3_PWM0 GPort1_Bit4_PWM6 GPort1_Bit5_PWM4/A6 GPort1_Bit6_PWM2/A5 GPort1_Bit7_PWM0/A4 GPort4_Bit0_PWM6 GPort4_Bit1_PWM4 GPort4_Bit2_PWM2 GPort4_Bit3_PWM0 XRES GPort4_Bit4_PWM6 GPort4_Bit5_PWM4 GPort4_Bit6_PWM2 GPort4_Bit7_PWM0 GPort5_Bit0_PWM2 GPort5_Bit1_PWM0 GPort2_Bit0_PWM6/A3 GPort2_Bit1_PWM4/A2 INT GPort2_Bit2_PWM0/WD August 17, 2005 Document No. 38-12036 Rev. *A 6 CY8C95xx Preliminary Data Sheet 2. Pinouts and Pin Descriptions 2.1.3 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100-Pin Part Pinout Pin No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Table 2-3. 100-Pin Part Pinout (TQFP) Name DNU DNU GPort0_Bit3_PWM1 GPort0_Bit4_PWM7 GPort0_Bit5_PWM5 GPort0_Bit6_PWM3 GPort0_Bit7_PWM1 GPort3_Bit0_PWM7 GPort3_Bit1_PWM5 GPort3_Bit2_PWM3 GPort3_Bit3_PWM1 DNU DNU DNU VSS GPort3_Bit4_PWM15 GPort3_Bit5_PWM13 GPort3_Bit6_PWM11 GPort3_Bit7_PWM9 GPort5_Bit7_PWM15 GPort5_Bit6_PWM13 GPort5_Bit2_PWM11 GPort5_Bit3_PWM9 I2C Serial Clock (SCL) DNU DNU DNU I2C Serial Data (SDA) GPort2_Bit3_PWM11/A1 A0 DNU Vdd DNU VSS DNU GPort7_Bit7_PWM15 GPort7_Bit6_PWM14 GPort7_Bit5_PWM13 GPort7_Bit4_PWM12 GPort7_Bit3_PWM11 GPort7_Bit2_PWM10 GPort7_Bit1_PWM9 GPort7_Bit0_PWM8 GPort2_Bit2_PWM8/WD INT GPort2_Bit1_PWM12/A2 GPort2_Bit0_PWM14/A3 DNU DNU DNU Description DNU = Do Not Use; leave floating. DNU = Do Not Use; leave floating. Port 0, Bit 3, PWM 1. Port 0, Bit 4, PWM 7. Port 0, Bit 5, PWM 5. Port 0, Bit 6, PWM 3. Port 0, Bit 7, PWM 1. Port 3, Bit 0, PWM 7. Port 3, Bit 1, PWM 5. Port 3, Bit 2, PWM 3. Port 3, Bit 3, PWM 1. DNU = Do Not Use; leave floating. DNU = Do Not Use; leave floating. DNU = Do Not Use; leave floating. Ground connection. Port 3, Bit 4, PWM 157. Port 3, Bit 5, PWM 13. Port 3, Bit 6, PWM 11. Port 3, Bit 7, PWM 9. Port 5, Bit 7, PWM 15. Port 5, Bit 6, PWM 13. Port 5, Bit 2, PWM 11. Port 5, Bit 3, PWM 9. I2C Clock. DNU = Do Not Use; leave floating. DNU = Do Not Use; leave floating. DNU = Do Not Use; leave floating. I2C Data. Port 2, Bit 3, PWM 11, Address 1. Address 0. DNU = Do Not Use; leave floating. Supply voltage. DNU = Do Not Use; leave floating. Ground connection. DNU = Do Not Use; leave floating. Port 7, Bit 7, PWM 15. Port 7, Bit 6, PWM 14. Port 7, Bit 5, PWM 13. Port 7, Bit 4, PWM 12. Port 7, Bit 3, PWM 11. Port 7, Bit 2, PWM 10. Port 7, Bit 1, PWM 9. Port 7, Bit 0, PWM 8. Port 2, Bit 2, PWM 8, E2 Write Disable. Port 7, Bit 7, PWM 0, Address 4. Port 7, Bit 6, PWM 2, Address 5. DNU = Do Not Use; leave floating. DNU = Do Not Use; leave floating. DNU = Do Not Use; leave floating. Name DNU GPort5_Bit1_PWM8 GPort5_Bit0_PWM10 GPort5_Bit4_PWM12 GPort5_Bit5_PWM14 GPort4_Bit7_PWM8 GPort4_Bit6_PWM10 GPort4_Bit5_PWM12 GPort4_Bit4_PWM14 DNU DNU XRES GPort4_Bit3_PWM0 GPort4_Bit2_PWM2 VSS GPort4_Bit1_PWM4 GPort4_Bit0_PWM6 GPort1_Bit7_PWM0/A4 GPort1_Bit6_PWM2/A5 GPort1_Bit5_PWM4/A6 DNU GPort1_Bit4_PWM6 DNU GPort1_Bit3_PWM0 DNU DNU GPort1_Bit2_PWM2 DNU GPort1_Bit1_PWM4 DNU GPort1_Bit0_PWM6 Vdd Vdd VSS VSS GPort6_Bit0_PWM0 GPort6_Bit1_PWM1 GPort6_Bit2_PWM2 GPort6_Bit3_PWM3 GPort6_Bit4_PWM4 GPort6_Bit5_PWM5 GPort6_Bit6_PWM6 GPort6_Bit7_PWM7 DNU GPort0_Bit0_PWM7 DNU GPort0_Bit1_PWM5 DNU GPort0_Bit2_PWM3 DNU Description DNU = Do Not Use; leave floating. Port 5, Bit 1, PWM 8. Port 5, Bit 0, PWM 10. Port 5, Bit 4, PWM 12. Port 5, Bit 5, PWM 14. Port 4, Bit 7, PWM 8. Port 4, Bit 6, PWM 10. Port 4, Bit 5, PWM 12. Port 4, Bit 4, PWM 14. DNU = Do Not Use; leave floating. DNU = Do Not Use; leave floating. Active high external reset with internal pull down. Port 4, Bit 3, PWM 0. Port 4, Bit 2, PWM 2. Ground connection. Port 4, Bit 1, PWM 4. Port 4, Bit 0, PWM 6. Port 1, Bit 7, PWM 0, Address 4. Port 1, Bit 6, PWM 2, Address 5. Port 1, Bit 5, PWM 4, Address 6. DNU = Do Not Use; leave floating. Port 1, Bit 4, PWM 6. DNU = Do Not Use; leave floating. Port 1, Bit 3, PWM 0. DNU = Do Not Use; leave floating. DNU = Do Not Use; leave floating. Port 1, Bit 2, PWM 2. DNU = Do Not Use; leave floating. Port 1, Bit 1, PWM 4. DNU = Do Not Use; leave floating. Port 1, Bit 0, PWM 6. Supply voltage. Supply voltage. Ground connection. Ground connection. Port 6, Bit 0, PWM 0. Port 6, Bit 1, PWM 1. Port 6, Bit 2, PWM 2. Port 6, Bit 3, PWM 3. Port 6, Bit 4, PWM 4. Port 6, Bit 5, PWM 5. Port 6, Bit 6, PWM 6. Port 6, Bit 7, PWM 7. DNU = Do Not Use; leave floating. Port 0, Bit 0, PWM 7. DNU = Do Not Use; leave floating. Port 0, Bit 1, PWM 5. DNU = Do Not Use; leave floating. Port 0, Bit 2, PWM 3. DNU = Do Not Use; leave floating. August 17, 2005 Document No. 38-12036 Rev. *A 7 CY8C95xx Preliminary Data Sheet 2. Pinouts and Pin Descriptions CY8C9560 100-Pin Device DNU GPort0_Bit2_PWM3 DNU GPort0_Bit1_PWM5 DNU GPort0_Bit0_PWM7 DNU GPort6_Bit7_PWM7 GPort6_Bit6_PWM6 GPort6_Bit5_PWM5 GPort6_Bit4_PWM4 GPort6_Bit3_PWM3 GPort6_Bit2_PWM2 GPort6_Bit1_PWM1 GPort6_Bit0_PWM0 Vss Vss Vdd Vdd GPort1_Bit0_PWM6 DNU GPort1_Bit1_PWM4 DNU GPort1_Bit2_PWM2 DNU 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DNU GPort1_Bit3_PWM0 DNU GPort1_Bit4_PWM6 DNU GPort1_Bit5_PWM4/A6 GPort1_Bit6_PWM2/A5 GPort1_Bit7_PWM0/A4 GPort4_Bit0_PWM6 GPort4_Bit1_PWM4 Vss GPort4_Bit2_PWM2 GPort4_Bit3_PWM0 XRES DNU DNU GPort4_Bit4_PWM14 GPort4_Bit5_PWM12 GPort4_Bit6_PWM10 GPort4_Bit7_PWM8 GPort5_Bit5_PWM14 GPort5_Bit4_PWM12 GPort5_Bit0_PWM10 GPort5_Bit1_PWM8 DNU 100 99 26 27 28 29 30 31 32 33 34 35 a.) DNU = Do Not Use; leave floating. August 17, 2005 Document No. 38-12036 Rev. *A GPort2_Bit2_PWM8/WD INT GPort2_Bit1_PWM12/A2 GPort2_Bit0_PWM14/A3 DNU DNU DNU DNU DNU I2C Serial Data (SDA) GPort2_Bit3_PWM11/A1 A0 DNU Vdd DNU Vss DNU GPort7_Bit7_PWM15 GPort7_Bit6_PWM14 GPort7_Bit5_PWM13 GPort7_Bit4_PWM12 GPort7_Bit3_PWM11 GPort7_Bit2_PWM10 GPort7_Bit1_PWM9 GPort7_Bit0_PWM8 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 DNUa DNU GPort0_Bit3_PWM1 GPort0_Bit4_PWM7 GPort0_Bit5_PWM5 GPort0_Bit6_PWM3 GPort0_Bit7_PWM1 GPort3_Bit0_PWM7 GPort3_Bit1_PWM5 GPort3_Bit2_PWM3 GPort3_Bit3_PWM1 DNU DNU DNU Vss GPort3_Bit4_PWM15 GPort3_Bit5_PWM13 GPort3_Bit6_PWM11 GPort3_Bit7_PWM9 GPort5_Bit7_PWM15 GPort5_Bit6_PWM13 GPort5_Bit2_PWM11 GPort5_Bit3_PWM9 I2C Serial Clock (SCL) DNU 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 TQFP 8 CY8C95xx Preliminary Data Sheet 2. Pinouts and Pin Descriptions 2.2 2.2.1 PIN Descriptions Extendable Soft Addressing™ 2.2.5 Working with PWMs The A0 line is always used to define the corresponding bit of the I2C address. This pin should be pulled up or down. If A0 is a strong pull-up or a strong pull-down (wired through 330 or less resistor to Vdd or Vss), then that is the only address line being specified and the A1-A6 lines are used as GPIO. If A0 is a weak pull-up or a weak pull-down (connected to Vdd or Vss through 75K- 200K-ohm resistor), then A0 is not the only externally defined address bit. There is a pin assigned to be A1 if it is needed. This pin can be pulled-up or pulled-down strong or weak with a resistor. As with A0, the type of pull determines whether the address bit is the last externally defined address bit. Differently from A0, A1 is not dedicated as an address pin. It is only used if A0 is not the only address bit externally defined. There are also predefined pins for A2, A3, A4, A5 and A6 that will only be used for addressing if needed. The last address bit in the chain is pulled strong. That way, only the number of pins needed to assign the address desired for the part are allocated as address pins, any pins not used for address bits are available to be used as GPIO pins. The Table , “Device Addressing,” on page 3 defines the resulting device I2C address. There are four independent PWMs in the CY8C9520, eight in the CY8C9540 and sixteen in the CY8C9560. Each I/O pin can be configured as a PWM output by writing ‘1’ to the corresponding bit of the Select PWM register (see Table 3-2, “Output and Select PWM Registers Logic,” on page 127). The next step of PWM configuration is clock source selection using the Config PWM registers. There are six available clock sources: 32 kHz (default), 24 MHz, 1.5 MHz, 93.75 kHz, 367.6 Hz or previous PWM output. (see Figure 2-1). 32 kHz 24 mHz 1.5 mHz 93.75 kHz Divider (1-255) 367.6 Hz 93.75 kHz Figure 2-1. Clock Sources By default, 32 kHz is selected as the PWM clock. PWM Period registers are used to set the output period: 2.2.2 Interrupt Pin (INT) The interrupt output (if enabled) is activated if one of the following events occurs: ■ One of the GPIO port pins changes state and the corresponding bit t OUT = Period × t CL K Allowed values are between 1 and FFh. Equation 1 in the Interrupt Mask register is set low. ■ When a PWM driven by the slowest clock source (367.6 Hz) and assigned to a pin changes state and the pin’s corresponding bit in the Interrupt Mask register is set low. The interrupt line is deactivated when the master device performs a read from the corresponding Interrupt Status register. The PWM Pulse Width register sets the duration of the PWM output pulse. Allowed values are between zero and the (Period1) value. The duty cycle ratio can be computed using the following equation: 2.2.3 Write Disable Pin (WD) PulseWidth D utyCycle = -----------------------------Period Equation 2 If this feature is enabled, ‘0’ allows writes to the EEPROM and ‘1’ blocks any memory writes. This pin is checked immediately before performing any write to memory. If the EEE bit in the Enable register is not set (EEPROM disabled) or bit EERO is set (EEPROM is read-only) then WD line level is ignored. Note that ‘1’ on this line blocks all commands which perform operations with EEPROM (see Table 3-9, “Available Commands,” on page 14). This line may be enabled/disabled by bit 1 of the Enable register (2Dh): ‘1’ enables WD function, ‘0’ disables. 2.2.4 External Reset Pin (XRES) A full device reset is caused by pulling the XRES pin high. The XRES pin has an always-on pull-down resistor, so it does not require an external pull down for operation. It can be tied directly to ground or left open. Behavior after XRES is similar to POR. August 17, 2005 Document No. 38-12036 Rev. *A 9 CY8C95xx Preliminary Data Sheet 2. Pinouts and Pin Descriptions slave address memory address R/W S A6 A5 A4 A3 A2 A1 A0 0 A start High(Addr) A Low(Addr) R/W A S A6 A5 A4 A3 A2 A1 A0 1 A data(Addr) A data(Addr+1) A ACK from master ... stop NP No ACK from master ACK from slave ACK from slave ACK from slave ACK from slave ACK from master Reading from EEPROM slave address memory address up to the end of address space R/W S A6 A5 A4 A3 A2 A1 A0 0 A start High(Addr) A Low(Addr) A data 1 A data 2 A ... stop AP ACK from slave ACK from slave ACK from slave If current address crosses 64-byte block boundary, then device performs real writing to EEPROM Writing to EEPROM Figure 2-2. Memory Reading and Writing slave address Register address = 1 Reading from GPort 2 At this moment, device performs reading from GPort 1 R/W R/W ... stop NP No ACK from master S A6 A5 A4 A3 A2 A1 A0 0 A 0 0 0 0 0 0 0 1 A S A6 A5 A4 A3 A2 A1 A0 1 A data from GPort1 A data from GPort 2 A start ACK from slave ACK from slave ACK from master Reading from GPort 1 slave address Register address = 09h At this moment, device performs output to GPort 1 R/W Output to GPort 2 Output to GPort 3 stop ... P S A6 A5 A4 A3 A2 A1 A0 0 A 0 0 0 0 1 0 0 1 A data from GPort1 A data from GPort 2 A data from GPort 0 A start ACK from slave ACK from slave ACK from slave ACK from slave Writing from GPort 1 Figure 2-3. Port Reading and Writing in Multi-Port Device August 17, 2005 Document No. 38-12036 Rev. *A 10 3. Register Reference This chapter lists and describes the registers of the CY8C95xx device, starting with a register map and then detailed descriptions of register types. 3.1 Register Mapping Table Table 3-1. The Device Register Address Map (continued) Address 13h 14h 15h 16h 17h 18h 19h Register Interrupt Status Port 3 Interrupt Status Port 4 Interrupt Status Port 5 Interrupt Status Port 6 Interrupt Status Port 7 Port Select Interrupt Mask Select PWM for Port Output Inversion Pin Direction - Input/Output Drive Mode - Pull Up Drive Mode - Pull Down Drive Mode - Open Drain High Drive Mode - Open Drain Low Drive Mode - Strong Drive Mode - Slow Strong Drive Mode - High-Z Reserved Reserved Reserved Reserved PWM Select Config PWM Period PWM Pulse Width PWM Programmable Divider Enable WDE, EEE, EERO Device ID/Status Reserved Command Default Register Value 00h 00h 00h 00h 00h 00h FFh 00h 00h 00h FFh 00h 00h 00h 00h 00h 00h None None None None 00h 00h FFh 80h FFh 00h 20h/40h/60h None 00h The register address is auto-incrementing. If the master device writes or reads data to or from one register and then continues data transfer in the same I2C transaction, sequential bytes will be written or read to or from the following registers. For example, if the first byte is sent to the Output Port 1 register, then the next bytes will be written to Output Port 2, Output Port 3, Output Port 4 etc. The first byte of each write transaction is treated as the register address. To read data from a seires of registers, the master device should write the starting register address byte then perform a start and series of read transactions. If no address was sent, reads start from address 0. To read a specific register address, the master device should write the register address byte, then perform a start and read transaction. See Figure 1-3, “Port Reading and Writing in Multi-Port Device,” on page 11. The device’s register mapping is listed in Table 3-1. Table 3-1. The Device Register Address Map Address 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 0Eh 0Fh 10h 11h 12h Input Port 0 Input Port 1 Input Port 2 Input Port 3 Input Port 4 Input Port 5 Input Port 6 Input Port 7 Output Port 0 Output Port 1 Output Port 2 Output Port 3 Output Port 4 Output Port 5 Output Port 6 Output Port 7 Interrupt Status Port 0 Interrupt Status Port 1 Interrupt Status Port 2 Register Default Register Value None None None None None None None None FFh FFh FFh FFh FFh FFh FFh FFh 00h 00h 00h 1Ah 1Bh 1Ch 1Dh 1Eh 1Fh 20h 21h 22h 23h 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh 30h August 17, 2005 Document No. 38-12036 Rev. *A 11 CY8C95xx Preliminary Data Sheet 3. Register Reference 3.2 Register Descriptions 3.2.6 Select PWM Register (1Ah) The registers for the CY8C95xx are described in the sections that follow. Note that the PWM registers are located at addresses 28h to 2Bh. 3.2.1 Input Port Registers (00h - 07h) This register is used to allow each port to act as a PWM output. By default, all ports are configured as GPIO lines. Each ’1’ in this register connects the corresponding pin of the GPort selected by the Port Select register (18h) to the PWM output. Output register data also affects the pin state when a PWM is enabled. See Table 3-2. Note that a pin used as PWM output should be configured to the appropriate drive mode. See Table 3-4 on page 13 for more information. Table 3-2 describes the logic of the Output and Select PWM registers. Table 3-2. Output and Select PWM Registers Logic Output 0 1 0 1 Select PWM 0 0 1 1 Pin State 0 1 0 Current PWM These registers represent actual logical levels on the pins and are used for I/O port reading operations. They are read-only. The Inversion registers will change the state of reads to these ports. 3.2.2 Output Port Registers (08h - 0Fh) These registers are used for writing data to GPIO ports. By default, all ports are in the pull-up mode allowing quasi-bidirectional I/O. To allow input operations without reconfiguration, these registers have to store ’1’s. Output register data also affects pin states when PWMs are enabled. See Table 3-2. Output and Select PWM Registers Logic for details. Figure 2-3 on page 10 illustrates port read/write procedures. The Inversion registers have no effect on these ports. 3.2.7 Inversion Register (1Bh) 3.2.3 Int. Status Port Registers (10h - 17h) This register can invert the logic of the input ports. Each ’1’ written to this register inverts the logic of the corresponding bit in the Input register of the GPort selected by the Port Select register (18h). The Input registers' logic is presented in Table 3-3. These registers have no effect on outputs or PWMs. Table 3-3. Inversion Register Logic Pin State 0 1 0 1 Invert 0 0 1 1 Input 0 1 1 0 Each ’1’ bit in these registers signals that there has been a change in the corresponding input line since the last read of that Interrupt Status register. Each Interrupt (Int.) Status register is cleared only after a read of that register. If a PWM is assigned to a pin, then all state changes of the PWM will set the corresponding bit in the Interrupt Status register. If the pin's interrupt mask is cleared and the PWM is set to the slowest possible rate allowed (driven by the programmable clock source with divide register 2Dh set to FFh), then the INT line will also be driven on the PWM state change. 3.2.4 Port Select Register (18h) 3.2.8 Port Direction Register (1Ch) This register is used to select the GPort to be configured. Write a value of 0-7 to this register to select the port to program with the following registers, 19h-23h. 3.2.5 Interrupt Mask Port Register (19h) The Interrupt Mask register enables/disables activation of the INT line when GPIO input levels are changed. Each ’1’ in the Interrupt Mask register masks (disables) interrupts generated from the corresponding input line of the GPort selected by the Port Select register (18h). Each bit in a port can be configured as either an input or an output. To perform this configuration, the Port Direction register (1Ch) is used for the GPort selected by the Port Select register (18h). If a bit in this register is set (written with '1'), the corresponding port pin is enabled as an input. If a bit in this register is cleared (written with '0'), the corresponding port pin is enabled as an output. August 17, 2005 Document No. 38-12036 Rev. *A 12 CY8C95xx Preliminary Data Sheet 3. Register Reference 3.2.9 Drive Mode Registers (1Dh-23h) Each port's data pins can be set separately to one of seven available modes: pull-up/-down, open drain high/low, strong drive fast/slow, or high-impedance input. To perform this configuration, the seven drive mode registers are used for the GPort selected by the Port Select register (18h). Each ’1’ written to this register changes the corresponding line drive mode. Registers 1Dh through 23h have last-register priority meaning that the bit set to high in which the last register was written will override those that came before. Reading these registers reflects the actual setting, not what was originally written. Table 3-4. Drive Mode Register Settings Register 1Dh 1Eh 1Fh 20h 21h 22h 23h Pin State Resistive pull up Resistive pull down Open drain high Open drain low Strong drive Slow strong drive HIgh impedance Description Resistive high, strong low (default) Strong high, resistive low Slow strong high, High-Z low Slow strong low, High-Z high Strong high, strong low, fast output mode Strong high, strong low, slow output mode High-Z Each PWM can generate an interrupt at the rising or falling edge of the output pulse. There is a limitation on the clock source for a PWM to generate an interrupt. Only the slowest speed source (programmed to 367.6 Hz) with the divider equal to 255 allows interrupt generation. Consequently, to create a PWM interrupt, it is necessary to choose the programmable divider output as the clock source (write xxxxx100b to Config register (29h)), write 255 to the Divide register (2Ch), and select PWM for pin output (1Ah). Interrupt status is reflected in the Interrupt Status registers (10h17h) and can cause INT line activation if enabled by the corresponding mask bit in the Interrupt Mask register: 3.2.12 Period Register (2Ah) Table 3-6. Period Register Config PWM xxxx0xxxb xxxx1xxxb PWM Interrupt on Falling pulse edge (default) Rising pulse edge This register sets the period of the PWM counter. Allowed values are between 1 and FFh. The effective output waveform period of the PWM is: tOUT = Period ⋅ tCLK 3.2.10 PWM Select Register (28h) 3.2.13 This register is used to select the PWM to be configured. Write a value of 00h-0Fh to this register to select the PWM to program with the following registers, 29h-2Bh. Pulse Width Register (2Bh) 3.2.11 Config (29h) This register sets the pulse width of the PWM output. Allowed values are between zero and the (Period - 1) value. The duty cycle ratio can be computed using the following equation: DutyCycle = PulseWidth . Period This register is used to choose the clock source for the PWM selected by the PWM Select register (28h) and interrupt logic. There are six available clock sources: 32 kHz (default), 24 MHz, 1.5 MHz, 93.75 kHz, 367.6 Hz, or previous PWM output. The 367.6 Hz clock is user programmable. It divides the 93.75 kHz clock source by the divisor stored in the Divider register (2Ch). The default divide ratio is 255. (see Table 3-5 for details). By default, all PWMs are clocked from 32 kHz. Table 3-5. PWM Clock Sources Config PWM xxxxx000b xxxxx001b xxxxx010b xxxxx011b xxxxx100b xxxxx101b 32 kHz (default) 24 MHz 1.5 MHz 93.75 kHz 367.6 Hz (programmable) Previous PWM PWM Clock Source 3.2.14 Divider Register (2Ch) This register sets the frequency on the output of the programmable divider: Frequency = 93.75 kHz . Divider Allowed values are between 1 and 255. 3.2.15 Enable Register (2Dh) The WDE bit configures the write disable pin to operate either as a GPIO or as WD. It also enables/disables EEPROM operations (EEE bit) or makes the EEPROM read-only (EERO bit). Bit assignments are shown in Table 3-7 on page 14. August 17, 2005 Document No. 38-12036 Rev. *A 13 CY8C95xx Preliminary Data Sheet 3. Register Reference Each ’1’ enables the corresponding feature, ’0’ disables. Table 3-7. Enable Register Bit Function Default 7 6 5 Reserved Reserved 4 3 2 EERO 0 1 EEE 0 0 WDE 0 Note that registers are not restored in parallel. Do not assume any particular order to the restoration process. Table 3-9. Available Commands Command 01h 02h Description Store device configuration to EEPROM POR defaults Restore Factory Defaults Write EEPROM POR defaults Read EEPROM POR defaults Write device configuration Read device configuration Reconfigure device with stored POR defaults Writes to this register differ from other registers. The write sequence to modify the Enable register is as follows: 1. Send device I2C address with bit 0. 2. Send register address 2Dh. 3. Send unlock key - the sequence of three bytes: 43h, 4Dh, 53h; ('C', 'M', 'S' in ASCII bytes). 4. Send new Enable register value. This write sequence secures the register from accidental changes. The register can be read without the use of the unlock key. By default, EERO and EEPROM (EEE bit) are disabled and WD line (WDE bit) is set to GPIO (WD disabled). When performing a burst write operation that crosses this register, the data written to this register will be ignored and the address will increment to 2Eh. 03h 04h 05h 06h 07h 3.3 3.3.1 Commands Description Store Config to E2 POR Defaults Cmd (01h) The current ports settings (drive modes and output data) and other configuration registers are saved in the EEPROM by using the store configuration command (Cmd). These settings will be automatically loaded after the next device power-up or if the 07h command is issued. 3.2.16 Device ID/Status Register (2Eh) 3.3.2 Restore Factory Defaults Cmd (02h) This register stores device identifiers (2xh/4xh/6xh) and reflects which settings were loaded during startup, either factory defaults (FD) or user defaults (UD). By default during startup, the device will attempt to load the user default block. If it seems to be corrupted then factory defaults are loaded and the low nibble of this register is set high to inform which set is active. The high nibble is always equal to 2 for CY8C9520, 4 for CY8C9540, and 6 for CY8C9560. This register is read-only. Table 3-8. Device ID Status Register Bit Function 7 8 5 4 3 2 Reserved 1 0 FD/UD Device Family (2, 4,or 6) This command replaces the saved user configuration with the factory default configuration. Current settings are unaffected by this command. New settings will be loaded after the next device power-up or if the 07h command is issued. 3.3.3 Write E2 POR Defaults Cmd (03h) This command is used to send new power-up defaults to the CY8C95xx without changing current settings unless the 07h command is issued afterwards. This command is followed by 147 data bytes according to Table 3-10. The CRC is calculated as the XOR of the 146 data bytes (00h-91h). If the CRC check fails or an incomplete block is sent, then the slave will respond with a NAK and the data will not be saved to EEPROM. To define new POR defaults the user must: 3.2.17 Command Register (30h) ■ ■ ■ Write command 03h; Write 146 data bytes with new values of registers; Write 1 CRC byte calculated as XOR of previous 146 data bytes. This register sends commands to the device, including current configuration as new POR defaults, restore factory defaults, define POR defaults, read POR defaults, write device configuration, read device configuration, and reconfigure device with stored POR defaults. The command set is presented in Table 39. Content of the data block is described in Table 3-10. August 17, 2005 Document No. 38-12036 Rev. *A 14 CY8C95xx Preliminary Data Sheet 3. Register Reference Table 3-10. POR Defaults Data Structure Offset 00h – 07h 08h – 0Fh 10h – 17h 18h – 1Fh 20h – 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh – 35h 36h – 3Ch 3Dh – 43h 44h – 4Ah 4Bh – 51h 52h – 58h 59h – 5Fh 60h 61h 62h 63h – 65h … 8Dh – 8Fh 90h 91h 92h Output Port 0-7 Interrupt mask Port 0-7 Select PWM Port 0-7 Inversion Port 0-7 Pin Direction Port 0-7 Resistive pull up Drive Mode Port 0 Resistive pull down Drive Mode Port 0 Open drain high Drive Mode Port 0 Open drain low Drive Mode Port 0 Strong drive Drive Mode Port 0 Slow strong drive Drive Mode Port 0 High impedance Drive Mode Port 0 Drive Modes Port 1 Drive Modes Port 2 Drive Modes Port 3 Drive Modes Port 4 Drive Modes Port 5 Drive Modes Port 6 Drive Modes Port 7 Config setting PWM0 Period setting PWM0 Pulse Width setting PWM0 PWM1 settings … PWM15 settings Divider Enable CRC Value 3.3.5 Write Device Config Cmd (05h) This command is used to send a new device configuration to the CY8C95xx. It is followed by 146 data bytes according to Table 3-10. The CRC is calculated as the XOR of the 146 data bytes (00h-91h). If the CRC check fails or an incomplete block is sent, then the slave will respond with a NAK and the device will not use the data. This gives the user ‘flat-address-space’ access to all device settings. To set the current device configuration the user must: ■ ■ ■ Write command 05h; Write 146 data bytes with new values of registers; Write 1 CRC byte calculated as XOR of previous 146 data bytes. If the CRC check passes, then the device will use the new settings immediately. Content of the data block is described in Table 3-10. 3.3.6 Read Device Config Cmd (06h) This command is used to read the current device configuration. It gives the user ‘flat-address-space’ access to all device settings. To read device configuration the user must: ■ ■ ■ Write command 06h; Read 146 data bytes (see Table 3-10). Read 1 CRC byte. 3.3.4 Read E2 POR Defaults Cmd (04h) 3.3.7 Reconfigure Device Cmd (07h) This command is used to read the POR settings stored in the EEPROM. To read POR defaults the user must: This command is used to immediately reconfigure the device with actual POR defaults from EEPROM. It has the same effect on the registers as a POR. ■ ■ ■ Write command 04h; Read 146 data bytes (see Table 3-10). Read 1 CRC byte. August 17, 2005 Document No. 38-12036 Rev. *A 15 4. Electrical Specifications This chapter presents the DC and AC electrical specifications of the CY8C95xx device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/psoc. Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted. The following table lists the units of measure that are used in this chapter. Table 4-1: Units of Measure Symbol o Unit of Measure degree Celsius kilohertz megahertz microsecond microvolts microvolts root-mean-square Symbol mA nA ns pF V milli-ampere nanoampere nanosecond picofarad volts Unit of Measure C kHz MHz µs µV µVrms 4.1 Symbol TSTG TA Vdd VIO VIOZ IMIO ESD LU Absolute Maximum Ratings Description Storage Temperature Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Electro Static Discharge Voltage Latch-up Current Min -45 -40 -0.5 Vss - 0.5 Vss - 0.5 -25 2000 – – – – – – – – – Typ Max +100 +85 +6.0 o Table 4-2: Absolute Maximum Ratings Units C C Notes Higher storage temperatures will reduce data retention time. o V Vdd + 0.5 V Vdd + 0.5 V +50 – 200 mA V mA Human Body Model ESD. August 17, 2005 Document No. 38-12036 Rev. *A 16 CY8C95xx Preliminary Data Sheet 4. Electrical Specifications 4.2 Symbol TA TJ Operating Temperature Description Ambient Temperature Junction Temperature Min -40 -40 – – Typ Max +85 +100 Units oC oC Table 4-3: Operating Temperature Notes The temperature rise from ambient to junction is package specific. See “Thermal Impedances” on page 23. The user must limit the power consumption to comply with this requirement. 4.3 4.3.1 DC Electrical Characteristics DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 4-4: CY8C9520 DC Chip-Level Specifications Symbol Vdd IDD IDD3 Supply Voltage Supply Current Vdd 5V Supply Current Vdd 3.3V Description – – Min 3.00 – 3.8 2.3 Typ 5 3 Max 5.25 V mA mA Conditions are 5.0V, TA = 25 oC, IOH = 0. Conditions are 3.3V, TA = 25 oC, IOH = 0. Units Notes Table 4-5: CY8C9540 DC Chip-Level Specifications Symbol Vdd IDD IDD3 Supply Voltage Supply Current Vdd 5V Supply Current Vdd 3.3V Description – – Min 3.00 – 6 3.3 Typ 9 6 Max 5.25 V mA mA Conditions are 5.0V, TA = 25 oC, IOH = 0. Conditions are 3.3V, TA = 25 oC, IOH = 0. Units Notes Table 4-6: CY8C9560 DC Chip-Level Specifications Symbol Vdd IDD IDD3 Supply Voltage Supply Current Vdd 5V Supply Current Vdd 3.3V Description – – Min 3.00 – 15 5 Typ 25 9 Max 5.25 V mA mA Conditions are 5.0V, TA = 25 oC, IOH = 0. Conditions are 3.3V, TA = 25 oC, IOH = 0. Units Notes August 17, 2005 Document No. 38-12036 Rev. *A 17 CY8C95xx Preliminary Data Sheet 4. Electrical Specifications 4.3.2 DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 4-7. DC Programming Specifications Symbol FlashENPB FlashENT FlashDR Description Flash (EEPROM) Endurance (per block) Flash Endurance (total)1 Flash Data Retention Min 50,000 – 1,800,000 – 10 – Typ – – – Max – – Years Units Erase/write cycles. Notes Erase/write cycles per block. 1. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). 4.3.3 DC General Purpose I/O Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 4-8: DC GPIO Specifications Symbol VOH High Output Level Description Min Vdd - 1.0 – Typ – Max V Units Notes IOH = 10 mA for any one pin, Vdd = 4.75 to 5.25V. 40 mA maximum combined IOH for GPort0; GPort2_Bit3; GPort3; GPort5_Bit2, 3, 6, 7; GPort6. 40 mA maximum combined IOH for GPort1; GPort2_Bit0, 1, 2; GPort4; GPort5_Bit0, 1, 4, 5; GPort7. 80 mA maximum combined IOH. IOL = 25 mA for any one pin, Vdd = 4.75 to 5.25V. 100 mA maximum combined IOL for GPort0; GPort2_Bit3; GPort3; GPort5_Bit2, 3, 6, 7; GPort6. 100 mA maximum combined IOL for GPort1; GPort2_Bit0, 1, 2; GPort4; GPort5_Bit0, 1, 4, 5; GPort7. 200 mA maximum combined IOL. Vdd = 3.0 to 5.5. Vdd = 3.0 to 5.5. Gross tested to 1 µA. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC. VOL Low Output Level – – 0.75 V VIL VIH IIL CIN COUT Input Low Level Input High Level Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output – 2.1 – – – – – 1 3.5 3.5 0.8 V V – 10 10 nA pF pF August 17, 2005 Document No. 38-12036 Rev. *A 18 CY8C95xx Preliminary Data Sheet 4. Electrical Specifications 4.4 4.4.1 AC Electrical Characteristics AC General Purpose I/O Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only or unless otherwise specified. Table 4-9: AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF 0 3 2 10 10 Min – – – 27 22 Typ 12 18 18 – – Max Units MHz ns ns ns ns Notes Normal Strong Mode Vdd = 4.75 to 5.25V, 10% - 90% Vdd = 4.75 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS Figure 4-1. GPIO Timing Diagram 4.4.2 AC PWM Output Jitter Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only or unless otherwise specified. Table 4-10: AC PWM Output Jitter Specifications Symbol Description – – Min Typ 0.1 2.5 Max 1.5 5.0 Units % % Notes 24 MHz, 1.5 MHz, 93.75kHz and 367.6 Hz (programmable) sources. 32 kHz clock source. Jitter24MHzPWM 24 MHz-Based PWM Peak-to-Peak Period Jitter Jitter32kHzPWM 32 kHz-Based PWM Peak-to-Peak Period Jitter August 17, 2005 Document No. 38-12036 Rev. *A 19 CY8C95xx Preliminary Data Sheet 4. Electrical Specifications 4.4.3 AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only or unless otherwise specified. Table 4-11: AC Characteristics of the I2C SDA and SCL Pins Standard Mode Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Set-up Time for a Repeated START Condition Data Hold Time Data Set-up Time Set-up Time for STOP Condition Bus Free Time Between a STOP and START Condition Pulse Width of spikes are suppressed by the input filter. Description 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 – Min – – – – – – – – – Max 100 0 0.6 1.3 0.6 0.6 0 100 0.6 1.3 0 3 Fast Mode Min – – – – – – – – 50 Max 400 µs µs µs µs µs ns µs µs ns Units kHz Notes SDA TLOWI2C TSUDATI2C THDSTAI2C TSPI2C TBUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C Sr TSUSTOI2C P S Figure 4-2. Definition for Timing for Fast/Standard Mode on the I2C Bus August 17, 2005 Document No. 38-12036 Rev. *A 20 5. Packaging Information This chapter illustrates the packaging specifications for the CY8C95xx device, along with the thermal impedances for each package, the typical package capacitance on crystal pins, and the solder reflow peak temperature. Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/support/link.cfm?mr=poddim. 5.1 Packaging Dimensions 51-85079 - *C Figure 5-1. 28-Lead (210-Mil) SSOP August 17, 2005 Document No. 38-12036 Rev. *A 21 CY8C95xx Preliminary Data Sheet 5. Packaging Information 51-85061 - *C Figure 5-2. 48-Lead (300-Mil) SSOP 51-85048 - *B Figure 5-3. 100-Lead (14 x 14 x 1.0 mm) TQFP August 17, 2005 Document No. 38-12036 Rev. *A 22 CY8C95xx Preliminary Data Sheet 5. Packaging Information 5.2 Thermal Impedances Package 28 SSOP 48 SSOP 100 TQFP Typical o Table 5-1. Thermal Impedances per Package θJA * 101 C/W 69oC/W 48oC/W * TJ = TA + POWER x θJA 5.3 Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Table 5-2. Solder Reflow Peak Temperature Package 28 SSOP 48 SSOP 100 TQFP Minimum Peak Temperature* 240oC 220oC 220oC Maximum Peak Temperature 260oC 260oC 260oC *Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220+/-5oC with Sn-Pb or 245+/-5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. August 17, 2005 Document No. 38-12036 Rev. *A 23 6. Ordering Information The following table lists the CY8C95xx device’s key package features and ordering codes. A definition of the ordering number code is presented below. Table 6-1. CY8C95xx Device Key Features and Ordering Information Configurable I/O Pins 20 20 40 40 60 60 Temperature Range EEPROM (Bytes) Ordering Code Package PWM Sources 4 4 8 8 16 16 28 Pin (210 Mil) SSOP 28 Pin (210 Mil) SSOP (Tape and Reel) 48 Pin (300 Mil) SSOP 48 Pin (300 Mil) SSOP (Tape and Reel) 100 Pin TQFP 100 Pin TQFP (Tape and Reel) CY8C9520-24PVXI CY8C9520-24PVXIT CY8C9540-24PVXI CY8C9540-24PVXIT CY8C9560-24AXI CY8C9560-24AXIT 3K 3K 11K 11K 27K 27K -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C 6.1 Ordering Code Definitions CY 8 C 9 xxx-SPxx Package Type: PX = PDIP Pb-Free SX = SOIC Pb-Free PVX = SSOP Pb-Free LFX = MLF Pb-Free AX = TQFP Pb-Free Speed: 24 MHz Part Number Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress MicroSystems Company ID: CY = Cypress Thermal Rating: C = Commercial I = Industrial E = Extended August 17, 2005 Document No. 38-12036 Rev. *A 24 7. Sales and Service Information To obtain information about Cypress Semiconductor or sales and technical support, reference the following informationt. Cypress Semiconductor 2700 162nd Street SW, Building D Lynnwood, WA 98087 Phone: Facsimile: Web Sites: 800.669.0557 425.787.4641 Company Information – http://www.cypress.com Sales – http://www.cypress.com/aboutus/sales_locations.cfm Technical Support – http://www.cypress.com/support/login.cfm 7.1 Revision History Table 7-1. CY8C95xx Data Sheet Revision History Document Title: CY8C95xx Preliminary Data Sheet Document Number: 38-12036 Revision ** *A ECN # 346754 392484 Issue Date See ECN See ECN Origin of Change HMT HMT Description of Change New silicon, document. Correct pin 79 on the TQFP. Add AC PWM Output Jitter spec. table. Upgrade to CY Perform logo and update zip code and trademarks. Distribution: External/Public Posting: None 7.2 Copyrights Copyrights and Code Protection © Cypress Semiconductor Corp. 2005. All rights reserved. PSoC™, PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. The information contained herein is subject to change without notice. Cypress Semiconductor assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. Cypress Semiconductor products are not warranted nor intended to be used for medical, life-support, life-saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress Semiconductor. Flash Code Protection Note the following details of the Flash code protection features on Cypress Semiconductor PSoC-related devices. Cypress MicroSystems products meet the specifications contained in their particular Cypress Semiconductor Data Sheets. Cypress Semiconductor believes that its family of products is one of the most secure families of its kind on the market today, regardless of how they are used. There may be methods, unknown to Cypress Semiconductor, that can breach the code protection features. Any of these methods, to our knowledge, would be dishonest and possibly illegal. Neither Cypress Semiconductor nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Cypress Semiconductor is willing to work with the customer who is concerned about the integrity of their code. Code protection is constantly evolving. We at Cypress Semiconductor are committed to continuously improving the code protection features of our products. August 17, 2005 © Cypress Semiconductor Corp. 2005 — Document No. 38-12036 Rev. *A 25