CY8CLED04D01_1105

CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 ® PowerPSoC Intelligent LED Driver PowerPSoC Intelligent LED Driver 1. Features ■ Integrated power peripherals ❐ Four internal 32 V low side N-Channel power FETs • RDS(ON)– 0.5  for 1.0 A devices • Up to 2 MHz configurable switching frequency ❐ Four hysteretic controllers • Independently programmable upper and lower thresholds • Programmable minimum ON/OFF timers ❐ Four low side gate drivers with programmable drive strength ❐ Four precision high side current sense amplifiers ❐ Three 16-bit LED dimming modulators: PrISM, DMM, and PWM ❐ Six fast response (100 ns) voltage comparators ❐ Six 8-bit reference DACs ❐ Built-in switching regulator eliminates external 5 V supply ❐ Multiple topologies including floating load buck, floating load buck-boost, and boost ■ M8C CPU core ❐ Processor speeds up to 24 MHz ■ Advanced peripherals (PSoC® Blocks) ❐ Capacitive sensing application capability ❐ DMX512 interface ❐ I2C master or slave ❐ Full-duplex UARTs ❐ Multiple SPI masters or slaves ❐ Integrated temperature sensor ❐ Up to 12-bit ADCs ❐ 6 to 12-bit incremental ADCs ❐ Up to 9-bit DACs ❐ Programmable gain amplifiers ❐ Programmable filters and comparators ❐ 8 to 32-bit timers and counters ❐ Complex peripherals by combining blocks ❐ Configurable to all GPIO pins ■ Programmable pin configurations ❐ 25 mA sink, 10 mA source on all GPIO and function pins ❐ Pullup, pull down, high Z, strong, or open drain drive modes on all GPIO and function pins ❐ Up to 10 analog inputs on GPIO ❐ Two 30 mA analog outputs on GPIO ❐ Configurable interrupt on all GPIO ■ Flexible on-chip memory ❐ 16 K Flash program storage 50,000 erase and write cycles ❐ 1 K SRAM data storage ❐ In-System Serial Programming (ISSP) ❐ Partial Flash updates ❐ Flexible protection modes ❐ EEPROM emulation in Flash ■ Complete development tools ❐ Free development software: PSoC Designer™ ❐ Full featured, In-Circuit Emulator and Programmer ❐ Full speed emulation ❐ Complex breakpoint structure ❐ 128 kBytes trace memory ■ Applications ❐ Stage LED lighting ❐ Architectural LED lighting ❐ General purpose LED lighting ❐ Automotive and emergency vehicle LED lighting ❐ Landscape LED lighting ❐ Display LED lighting ❐ Effects LED lighting ❐ Signage LED lighting ■ Device options ❐ CY8CLED04D0x • Four internal FETs with 0.5 A and 1.0 A options • Four external gate drivers ❐ CY8CLED04G01 • Four external gate drivers ❐ CY8CLED03D0x • Three internal FETs with 0.5 A and 1.0 A options • Three external gate drivers ❐ CY8CLED03G01 • Three external gate drivers ❐ CY8CLED02D01 • Two 1.0 A internal FETs • Two external gate drivers ❐ CY8CLED01D01 • One 1.0 A internal FET • One external gate driver ■ 56-pin QFN package Figure 1-1. PowerPSoC Architectural Block Diagram Port 2 Port 1 Port 0 Analog Drivers FN0 CSA CSA Analog Mux Bus Global Digital Interconnect Global Analog Interconnect Interupt Bus SYSTEM BUS Logic Core PrISM/ DMM / PWM Power System Analog Bus PSoC SRAM (1 K bytes ) Interrupt Controller CORE Clock Signals Supervisory ROM Flash Nonvolatile Memory( K) 16 ( SROM) Decoder DAC Hysteretic PWM Chbond_bus PWM Controller Channels( LV) Gate Driver(LV) Power FETs (HV) GDRV CPU (M8C) Core Analog Block C1 Sleep and Watchdog System Bus C2 24 MHz Internal Main Oscillator( IMO) Internal Low Speed Oscillator ( ILO) C3 DAC Hysteretic PWM GDRV C5 DIGITAL SYSTEM Digital PSoC Block Array DBB 00 DBB 01 DCB 02 DCB 03 ANALOG SYSTEM Analog PSoC Block Array Analog Ref C6 Comparator Bank Power System Digital Bus Multiple Clock Sources C4 DAC Hysteretic PWM GDRV CT SC SC CT SC SC AINX DAC DBB 01 DBB 11 DCB 12 DCB13 DAC DAC DAC DAC Bank 2 Digital Rows Hysteretic PWM GDRV 2Analog Columns Vref Digital Clocks MACs (2) Decimator ( Type2) POR and LVD I2C System Resets Internal IO Analog Voltage Multiplexer Reference SW Regulator POWER PERIPHERALS PSoC SYSTEM RESOURCES CSA CSA Cypress Semiconductor Corporation Document Number: 001-46319 Rev. *N • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised May 4, 2011 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 2. Contents Logic Block Diagrams ...................................................... 3 PowerPSoC® Functional Overview ................................. 9 Power Peripherals ............................................................ 9 Hysteretic Controllers ..................................................9 Low Side N-Channel FETs ........................................10 External Gate Drivers ................................................10 Dimming Modulation Schemes ..................................10 Current Sense Amplifier ............................................10 Voltage Comparators ................................................11 Reference DACs .......................................................11 Built-in Switching Regulator ......................................11 Analog Multiplexer .....................................................11 Digital Multiplexer ......................................................12 Function Pins (FN0[0:3]) ...........................................12 PSoC Core ....................................................................... 13 Digital System ...........................................................13 Analog System ..........................................................13 Analog Multiplexer System ........................................14 Additional System Resources ...................................14 Applications .................................................................... 15 PowerPSoC Device Characteristics .............................. 16 Getting Started ................................................................ 17 Application Notes ......................................................17 Development Kits ......................................................17 Training .....................................................................17 CYPros Consultants ..................................................17 Technical Support .....................................................17 Development Tools ........................................................ 17 PSoC Designer Software Subsystems ......................17 In-Circuit Emulator .....................................................18 Designing with User Modules ....................................... 18 Pin Information ............................................................... 19 CY8CLED04D0x 56-Pin Part Pinout (without OCD) ............................................................19 CY8CLED04G01 56-Pin Part Pinout (without OCD) ............................................................20 CY8CLED04DOCD1 56-Pin Part Pinout (with OCD) .................................................................21 CY8CLED03D0x 56-Pin Part Pinout (without OCD) ............................................................22 CY8CLED03G01 56-Pin Part Pinout (without OCD) ............................................................23 CY8CLED02D01 56-Pin Part Pinout (without OCD) ............................................................24 CY8CLED01D01 56-Pin Part Pinout (without OCD) ............................................................25 Register General Conventions ...................................... 26 Abbreviations Used ...................................................26 Register Naming Conventions ...................................26 Register Mapping Tables ..........................................26 Register Map Bank 0 Table .......................................26 Register Map Bank 1 Table: User Space ..................27 Electrical Specifications ................................................ 29 Absolute Maximum Ratings .......................................29 Operating Temperature .............................................30 Electrical Characteristics ............................................... 30 System Level .............................................................30 Chip Level .................................................................30 Power Peripheral Low Side N-Channel FET .........................................................32 Power Peripheral External Power FET Driver .................................................................33 Power Peripheral Hysteretic Controller .....................33 Power Peripheral Comparator ...................................34 Power Peripheral Current Sense Amplifier ................35 Power Peripheral PWM/PrISM/DMM Specification Table ....................................................36 Power Peripheral Reference DAC Specification ..............................................................37 Power Peripheral Built-in Switching Regulator ...................................................................37 General Purpose I/O / Function Pin I/O .....................40 PSoC Core Operational Amplifier Specifications ............................................................41 PSoC Core Low Power Comparator .........................42 PSoC Core Analog Output Buffer ..............................43 PSoC Core Analog Reference ..................................44 PSoC Core Analog Block ..........................................44 PSoC Core POR and LVD ........................................45 PSoC Core Programming Specifications ..................45 PSoC Core Digital Block Specifications ....................46 PSoC Core I2C Specifications ..................................47 Ordering Information ...................................................... 48 Ordering Code Definitions ......................................... 48 Packaging Information ................................................... 49 Packaging Dimensions ..............................................49 Thermal Impedance ..................................................49 Solder Reflow Peak Temperature .............................49 Acronyms ........................................................................ 50 Document Conventions ................................................. 50 Units of Measure .......................................................50 Document History Page ................................................. 52 Sales, Solutions, and Legal Information ...................... 53 Worldwide Sales and Design Support .......................53 Products ....................................................................53 PSoC Solutions .........................................................53 Document Number: 001-46319 Rev. *N Page 2 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 3. Logic Block Diagrams Figure 3-1. CY8CLED04D0x Logic Block Diagram CSA0 CSP0 CSN0 SW0 DAC0 DAC1 Hysteretic Mode Controller 0 Gate Drive 0 PGND0 External Gate Drive 0 GD 0 CSA1 CSP1 CSN1 SW1 DAC2 DAC3 Gate Drive 1 Hysteretic Mode Controller 1 PGND1 External Gate Drive 1 GD 1 CSA2 CSP2 CSN2 Analog Mux DAC4 DAC5 Gate Drive 2 Hysteretic Mode Controller 2 External Gate Drive 2 SW2 PGND2 GD 2 CSA3 CSP3 CSN3 DAC6 DAC7 Gate Drive 3 Hysteretic Mode Controller 3 External Gate Drive 3 SW3 PGND3 GD 3 FN0[0:3] FN0 Power Peripherals Digital Mux Comp 10 Comp 11 Comp 12 Comp 8 Comp 9 4 4 Comp 13 4 Channel PWM/ PrISM/DMM Power Peripherals Analog Mux SREGHVIN DAC10 DAC11 DAC12 DAC9 6 DAC13 DAC8 SREGSW From Analog Mux AINX System Bus Auxiliary Power Regulator SREGCSP SREGCSN SREGFB SREGCOMP Global Digital Interconnect Global Analog Interconnect PSoC CORE SRAM 1K Interrupt Controller SROM Flash 16K Sleep and Watchdog Port 2 P2[2] CPU Core (M8C) Port 1 P1[0,1,4,5,7] Clock Sources (Includes IMO and ILO) Port 0 P0[3,4,5,7] DIGITAL SYSTEM ANALOG SYSTEM A nalog Ref. Digital Block Array Analog Block Array Digital Clocks 2 MACs Decimator Type 2 I2C POR and LVD System Resets Internal Voltage Ref. Analog Input Muxing SYSTEM RESOURCES Document Number: 001-46319 Rev. *N Page 3 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 Figure 3-2. CY8CLED04G01 Logic Block Diagram CSA0 CSP0 CSN0 DAC0 DAC1 Hysteretic Mode Controller 0 External Gate Drive 0 GD 0 CSA1 CSP1 CSN1 DAC2 DAC3 Hysteretic Mode Controller 1 External Gate Drive 1 GD 1 CSA2 CSP2 CSN2 Analog Mux DAC4 DAC5 Hysteretic Mode Controller 2 External Gate Drive 2 GD 2 CSA3 CSP3 CSN3 DAC6 DAC7 Hysteretic Mode Controller 3 External Gate Drive 3 GD 3 FN0[0:3] FN0 Power Peripherals Digital Mux Comp 10 Comp 11 Comp 12 Comp 8 Comp 9 4 4 Comp 13 4 Channel PWM/ PrISM/DMM Power Peripherals Analog Mux SREGHVIN DAC10 DAC11 DAC12 6 DAC13 DAC8 DAC9 SREGSW From Analog Mux AINX System Bus Auxiliary Power Regulator SREGCSP SREGCSN SREGFB SREGCOMP Global Digital Interconnect Global Analog Interconnect PSoC CORE SRAM 1K Interrupt Controller SROM Flash 16K Sleep and Watchdog Port 2 P2[2] CPU Core (M8C) Port 1 P1[0,1,4,5,7] Clock Sources (Includes IMO and ILO) Port 0 P0[3,4,5,7] DIGITAL SYSTEM ANALOG SYSTEM Analog Ref. Digital Block Array Analog Block Array Digital Clocks 2 MACs Decimator Type 2 I2C POR and LVD System Resets Internal Voltage Ref. Analog Input Muxing SYSTEM RESOURCES Document Number: 001-46319 Rev. *N Page 4 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 Figure 3-3. CY8CLED03D0x Logic Block Diagram CSA0 CSP0 CSN0 SW0 DAC0 DAC1 Hysteretic Mode Controller 0 Gate Drive 0 PGND0 External Gate Drive 0 GD 0 CSA1 CSP1 CSN1 SW1 DAC2 DAC3 Analog Mux Gate Drive 1 Hysteretic Mode Controller 1 PGND1 External Gate Drive 1 GD 1 CSA2 CSP2 CSN2 DAC4 DAC5 Gate Drive 2 Hysteretic Mode Controller 2 External Gate Drive 2 SW2 PGND2 GD 2 FN0[0:3] FN0 Power Peripherals Digital Mux Comp 10 Comp 11 Comp 12 Comp 8 Comp 9 4 4 Comp 13 3 Channel PWM/ PrISM/DMM Power Peripherals Analog Mux SREGHVIN DAC10 DAC11 DAC12 6 DAC13 DAC8 DAC9 SREGSW From Analog Mux AINX System Bus Auxiliary Power Regulator SREGCSP SREGCSN SREGFB SREGCOMP Global Digital Interconnect Global Analog Interconnect PSoC CORE SRAM 1K Interrupt Controller SROM Flash 16K Sleep and Watchdog Port 2 P2[2] CPU Core (M8C) Port 1 P1[0,1,4,5,7] Clock Sources (Includes IMO and ILO) Port 0 P0[3,4,5,7] DIGITAL SYSTEM ANALOG SYSTEM Analog Ref. Digital Block Array Analog Block Array Digital Clocks 2 MACs Decimator Type 2 I2C POR and LVD System Resets Internal Voltage Ref. Analog Input Muxing SYSTEM RESOURCES Document Number: 001-46319 Rev. *N Page 5 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 Figure 3-4. CY8CLED03G01 Logic Block Diagram CSA0 CSP0 CSN0 DAC0 DAC1 Hysteretic Mode Controller 0 External Gate Drive 0 GD 0 CSA1 CSP1 CSN1 DAC2 DAC3 Analog Mux Hysteretic Mode Controller 1 External Gate Drive 1 GD 1 CSA2 CSP2 CSN2 DAC4 DAC5 Hysteretic Mode Controller 2 External Gate Drive 2 GD 2 FN0[0:3] FN0 Power Peripherals Digital Mux Comp 10 Comp 11 Comp 12 Comp 8 Comp 9 4 4 Comp 13 3 Channel PWM/ PrISM/DMM Power Peripherals Analog Mux SREGHVIN DAC10 DAC11 DAC12 6 DAC13 DAC8 DAC9 SREGSW From Analog Mux AINX System Bus Auxiliary Power Regulator SREGCSP SREGCSN SREGFB SREGCOMP Global Digital Interconnect Global Analog Interconnect PSoC CORE SRAM 1K Interrupt Controller SROM Flash 16K Sleep and Watchdog Port 2 P2[2] CPU Core (M8C) Port 1 P1[0,1,4,5,7] Clock Sources (Includes IMO and ILO) Port 0 P0[3,4,5,7] DIGITAL SYSTEM ANALOG SYSTEM Analog Ref. Digital Block Array Analog Block Array Digital Clocks 2 MACs Decimator Type 2 I2C POR and LVD System Resets Internal Voltage Ref. Analog Input Muxing SYSTEM RESOURCES Document Number: 001-46319 Rev. *N Page 6 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 Figure 3-5. CY8CLED02D01 Logic Block Diagram CSA0 CSP0 CSN0 SW0 DAC0 DAC1 Hysteretic Mode Controller 0 Gate Drive 0 PGND0 External Gate Drive 0 GD 0 CSA1 CSP1 SW1 DAC2 Analog Mux DAC3 Gate Drive 1 Hysteretic Mode Controller 1 PGND1 CSN1 External Gate Drive 1 GD 1 FN0[0:3] FN0 Power Peripherals Digital Mux Comp 10 Comp 11 Comp 12 Comp 8 Comp 9 4 4 Comp 13 2 Channel PWM/ PrISM/DMM Power Peripherals Analog Mux SREGHVIN DAC10 DAC11 DAC12 6 DAC13 DAC8 DAC9 SREGSW From Analog Mux AINX System Bus Auxiliary Power Regulator SREGCSP SREGCSN SREGFB SREGCOMP Global Digital Interconnect Global Analog Interconnect PSoC CORE SRAM 1K Interrupt Controller SROM Flash 16K Sleep and Watchdog Port 2 P2[2] CPU Core (M8C) Port 1 P1[0,1,4,5,7] Clock Sources (Includes IMO and ILO) Port 0 P0[3,4,5,7] DIGITAL SYSTEM ANALOG SYSTEM Analog Ref. Digital Block Array Analog Block Array Digital Clocks 2 MACs Decimator Type 2 I2C POR and LVD System Resets Internal Voltage Ref. Analog Input Muxing SYSTEM RESOURCES Document Number: 001-46319 Rev. *N Page 7 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 Figure 3-6. CY8CLED01D01 Logic Block Diagram CSA0 CSP0 CSN0 SW0 DAC0 DAC1 Analog Mux Hysteretic Mode Controller 0 Gate Drive 0 PGND0 External Gate Drive 0 GD 0 FN0[0:3] FN0 Power Peripherals Digital Mux Comp 10 Comp 11 Comp 12 Comp 8 Comp 9 4 4 Comp 13 1 Channel PWM/ PrISM/DMM Power Peripherals Analog Mux SREGHVIN DAC10 DAC11 DAC12 6 DAC13 DAC8 DAC9 SREGSW From Analog Mux AINX System Bus Auxiliary Power Regulator SREGCSP SREGCSN SREGFB SREGCOMP Global Digital Interconnect Global Analog Interconnect PSoC CORE SRAM 1K Interrupt Controller SROM Flash 16K Sleep and Watchdog Port 2 P2[2] CPU Core (M8C) Port 1 P1[0,1,4,5,7] Clock Sources (Includes IMO and ILO) Port 0 P0[3,4,5,7] DIGITAL SYSTEM ANALOG SYSTEM Analog Ref. Digital Block Array Analog Block Array Digital Clocks 2 MACs Decimator Type 2 I2C POR and LVD System Resets Internal Voltage Ref. Analog Input Muxing SYSTEM RESOURCES Document Number: 001-46319 Rev. *N Page 8 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 4. PowerPSoC® Functional Overview The PowerPSoC family incorporates programmable system-on-chip technology with the best in class power electronics controllers and switching devices to create easy to use power-system-on-chip solutions for lighting applications. All PowerPSoC family devices are designed to replace traditional MCUs, system ICs, and the numerous discrete components that surround them. PowerPSoC devices feature high performance power electronics including 1 ampere 2 MHz power FETs, hysteretic controllers, current sense amplifiers, and PrISM/PWM modulators to create a complete power electronics solution for LED power management. Configurable power, analog, digital, and interconnect circuitry enables a high level of integration in a host of industrial, commercial, and consumer LED lighting applications. This architecture integrates programmable analog and digital blocks to enable you to create customized peripheral configurations that match the requirements of each individual application. Additionally, the device includes a 24 MHz CPU, Flash program memory, SRAM data memory, and configurable I/O in a range of convenient pinouts and packages. The PowerPSoC architecture, as illustrated in the block diagrams, comprises five main areas: PSoC core, digital system, analog system, system resources, and power peripherals, which include power FETs, hysteretic controllers, current sense amplifiers, and PrISM/PWM modulators. Configurable global busing combines all the device resources into a complete custom system. The PowerPSoC family of devices have 10-port I/Os that connect to the global digital and analog interconnects, providing access to eight digital blocks and six analog blocks. 5.1 Hysteretic Controllers The PowerPSoC contains four hysteretic controllers. There is one hysteretic controller for each channel of the device. The hysteretic controllers provide cycle by cycle switch control with fast transient response, which simplifies system design by requiring no external compensation. The hysteretic controllers include the following key features: ■ ■ ■ ■ ■ Four independent channels DAC configurable thresholds Wide switching frequency range from 20 kHz to 2 MHz Programmable minimum on and off time Floating load buck, floating load buck-boost and boost topology controller The reference inputs (REF_A and REF_B in Figure 5-1.) of the hysteretic controller are provided by the reference DACs as illustrated in the top level block diagram (see Figure 3-1. on page 3). The hysteretic control function output is generated by comparing the feedback value to two thresholds. Going below the lower threshold turns the switch ON and exceeding the upper threshold turns the switch OFF as shown in Figure 5-1. The output current waveforms are shown in Figure 5-2. The hysteretic controller also controls the minimum on-time and off-time. This circuit prevents oscillation at very high frequencies; which can be very destructive to output switches. The output to the gate drivers is gated by the Trip, DIM and Enable signals. The Enable signal is a direct result of the enable bit in the control register for the hysteretic controller. The Trip signal can be any digital signal that follows TTL logic (logic high and logic low). It is an active high input. The DIM Modulation signal is the output of the dedicated modulators that are present in the power peripherals, or any other digital modulation signal. Figure 5-1. Generating Hysteretic Control Function Output Lower Limit Comparator REF_A S CSA FN0[x] IFB Upper Limit Comparator R REF_B Min Off Timer DIM Modulation Enable Trip Function Hyst Out Q Min ON Timer 5. Power Peripherals PowerPSoC is designed to operate at voltages from 7 V to 32 V, drive up to 1 ampere of current using internal MOSFET switches, and over 1 ampere with external MOSFETs. This family of devices (CY8CLED0xD/G0y) combines up to four independent channels of constant current drivers. These drivers feature hysteretic controllers with the Programmable System-on-Chip (PSoC) that contains an 8-bit microcontroller, configurable digital and analog peripherals, and embedded flash memory. The CY8CLED0xD/G0y is the first product in the PowerPSoC family to integrate power peripherals to add further integration for your power electronics applications.The PowerPSoC family of intelligent power controller ICs are used in lighting applications that need traditional MCUs and discrete power electronics support. The power peripherals of the CY8CLED0xD/G0y include up to four 32 volt power MOSFETs with current ratings up to 1 ampere each. It also integrates gate drivers that enable applications to drive external MOSFETs for higher current and voltage capabilities. The controller is a programmable threshold hysteretic controller, with user-selectable feedback paths that uses the IC in current mode floating load buck, floating load buck-boost, and boost configurations. Document Number: 001-46319 Rev. *N Page 9 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 Figure 5-2. Current Waveforms REF_B 5.4.1 PrISM Mode Configuration ■ ■ ■ ■ ■ High resolution operation up to 16 bits Dedicated PrISM module enables customers to use core PSoC digital blocks for other needs Clocking up to 48 MHz Selectable output signal density Reduced EMI ILED REF_A ON DIM OFF The PrISM mode compares the output of a pseudo-random counter with a signal density value. The comparator output asserts when the count value is less than or equal to the value in the signal density register. 5.4.2 DMM Mode Configuration ■ High resolution operation up to 16 bits Configurable output frequency and delta sigma modulator width to trade off repeat rates versus resolution Dedicated DMM module enables customers to use PSoC digital blocks for other uses Clocking up to 48 MHz Hyst Out ■ ■ The minimum on-time and off-time circuits in the PowerPSoC prevent oscillations at very high frequencies, which can be very destructive to output switches. ■ 5.2 Low Side N-Channel FETs The internal low side N-Channel FETs are designed to enhance system integration. The low side N-Channel FETs include the following key features: ■ ■ ■ ■ ■ The DMM modulator consists of a 12-bit PWM block and a 4-bit Delta Sigma Modulator (DSM) block. The width of the PWM, the width of the DMM, and the clock defines the output frequency. The duty cycle of the PWM output is dithered by using the DSM block which has a user-selectable resolution up to 4 bits. 5.4.3 PWM Mode Configuration ■ ■ ■ ■ ■ ■ ■ Drive capability up to 1 A Switching times of 20 ns (rise and fall times) to ensure high efficiency (more than 90%) Drain source voltage rating 32 V Low RDS(ON) to ensure high efficiency Switching frequency up to 2 MHz High resolution operation up to 16 bits User programmable period from 1 to 65535 clocks Dedicated PWM module enables customers to use core PSoC digital blocks for other use Interrupt on rising edge of the output or terminal count Precise PWM phase control to manage system current edges Phase synchronization among the four channels PWM output can be aligned to left, right, or center 5.3 External Gate Drivers These gate drivers enable the use of external FETs with higher current capabilities or lower RDS(ON). The external gate drivers directly drive MOSFETs that are used in switching applications. The gate driver provides multiple programmable drive strength steps to enable improved EMI management. The external gate drivers include the following key features: ■ ■ The PWM features a down counter and a pulse width register. A comparator output is asserted when the count value is less than or equal to the value in the pulse width register. Programmable drive strength options (25%, 50%, 75%, 100%) for EMI management Rise and fall times at 55 ns with 4 nF load 5.5 Current Sense Amplifier The high side current sense amplifiers provide a differential sense capability to sense the voltage across current sense resistors in lighting systems. The current sense amplifier includes the following key features: ■ ■ ■ 5.4 Dimming Modulation Schemes There are three dimming modulation schemes available with the PowerPSoC. The configurable modulation schemes are: ■ ■ ■ Operation with high common mode voltage to 32 V High common mode rejection ratio Programmable bandwidth to optimize system noise immunity Precise Intensity Signal Modulation (PrISM) Delta Sigma Modulation Mode (DMM) Pulse Width Modulation (PWM) An off-chip resistor Rsense is used for high side current measurement as shown in Figure 5-3. on page 11. The output of the current sense amplifier goes to the power peripherals analog multiplexer where, you select the hysteretic controller to which Page 10 of 55 Document Number: 001-46319 Rev. *N [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 the routing is done. Table 5-1 illustrates example values of Rsense for different currents. The method to calculate the Rsense value for a desired average current is explained in the application note, Floating Load Buck Topology for HB-LEDs - AN52699 Table 5-1. Rsense Values for Different Currents Max Load Current (mA) 1000 750 500 350 Typical Rsense (m) 100 130 200 300 ■ ■ Low gain errors 10 us settling time These DACs are available to provide programmable references for the various analog and comparator functions and are controlled by memory mapped registers. DAC[0:7] are embedded in the hysteretic controllers and are required to set the upper and lower thresholds for channel 0 to 3. DAC [8:13] are connected to the Power Peripherals Analog Multiplexer and provide programmable references to the comparator bank. These are used to set trip points which enable over voltage, over current, and other system event detection. 5.8 Built-in Switching Regulator The switching regulator is used to power the low voltage (5 V portion of the PowerPSoC) from the input line. This regulator is based upon a peak current control loop which can support up to 250 mA of output current. The current not being consumed by PowerPSoC is used to power additional system peripherals. The key features of the built-in switching regulator include: ■ ■ ■ Figure 5-3. High Side Current Measurement CSP0 Rsense0 CSN0 CS0 . . . CSP3 Rsense3 Power Peripheral Analog Mux Ability to self power device from input line Small filter component sizes Fast response to transients Refer to Table 16-20 for component values. The 'Ref' signal that forms the reference to the Error Amplifier is internally generated and there is no user control over it. Figure 5-4. Built-in Switching Regulator CSN3 CS3 5.6 Voltage Comparators There are six comparators that provide high speed comparator operation for over voltage, over current, and various other system event detections. For example, the comparators may be used for zero crossing detection for an AC input line or monitoring total DC bus current. Programmable internal analog routing enables these comparators to monitor various analog signals. These comparators include the following key features: ■ ■ ■ Ref Error Amplifier Osc SREGHVIN VREGIN C IN Logic and Gate Drive Comparator Current Sense Amplifier SREGSW L D1 SREGCSP SREGCSN Rsense Rfb1 VREGOUT = 5V ESR High speed comparator operation: 100 ns response time Programmable interrupt generation Low input offset voltage and input bias currents Rfb2 SREGCOMP Ccomp SREGFB Rcomp C1 Six precision voltage comparators are available. The differential positive and negative inputs of the comparators are routed from the analog multiplexer and the output goes to the digital multiplexer. A programmable inverter is used to select the output polarity. User-selectable hysteresis can be enabled or disabled to trade-off noise immunity versus comparator sensitivity. 5.9 Analog Multiplexer The PowerPSoC family’s analog MUX is designed to route signals from the CSA output, function I/O pins and the DACs to comparator inputs and the current sense inputs of the hysteretic controllers. Additionally, CSA outputs can be routed to the AINX block using this MUX. For a full matrix representation of all possible routing using this MUX, refer to the PowerPSoC Technical Reference Manual. The CPU configures the Power Peripherals Analog Multiplexer connections using memory mapped registers. The analog multiplexer includes the following key features: ■ 5.7 Reference DACs The reference DACs are used to generate set points for various analog modules such as Hysteretic controllers and comparators. The reference DACs include the following key features: ■ ■ 8-bit resolution Guaranteed monotonic operation Signal integrity for minimum signal corruption Document Number: 001-46319 Rev. *N Page 11 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 5.10 Digital Multiplexer The PowerPSoC family’s digital MUX is a configurable switching matrix that connects the power peripheral digital resources. For a full matrix representation of all possible routing using this MUX, refer to the PowerPSoC Technical Reference Manual. This Power Peripheral Digital Multiplexer is independent of the main PSoC digital buses or global interconnect of the PSoC core. The digital multiplexer includes the following key features: ■ FN0[x] DIM Figure 5-6. PowerPSoC in Master/Slave Configuration PowerPSoC (Slave 0) Hysteretic Controller PowerPSoC (Slave 1) Connect signals to ensure needed flexibility FN0[0] FN0[x] DIM Hysteretic Controller 5.11 Function Pins (FN0[0:3]) The function I/O pins are a set of dedicated control pins used to perform system level functions with the power peripheral blocks of the PowerPSoC. These pins are dynamically configurable, enabling them to perform a multitude of input and output functions. These I/Os have direct access to the input and output of the voltage comparators, input of the hysteretic controller, and output of the digital PWM blocks for the device. The function I/O pins are register mapped. The microcontroller can control and read the state of these pins and the interrupt function. Some of the key system benefits of the function I/O are: ■ ■ ■ PowerPSoC (Master) FN0[1] FN0[2] FN0[3] FN0[x] DIM PowerPSoC (Slave 2) Hysteretic Controller Enabling an external higher voltage current-sense amplifier as shown in Figure 5-5. Synchronizing dimming of multiple PowerPSoC controllers as shown in Figure 5-6. Programmable fail-safe monitor and dedicated shutdown of hysteretic controller as shown in Figure 5-7. Figure 5-7. Event Detection FN0[x] DIM PowerPSoC (Slave 3) Hysteretic Controller Along with the these functions, these I/Os also provide interrupt functionality, enabling intelligent system responses to power control lighting system status. Figure 5-5. External CSA and FET Application External CSA + - Event Detect FN0[0] Trip Hysteretic Mode Controller 0 External Gate Drive 0 GD0 HVDD Rsense VLED > 32V { . . . . . . . . . PowerPSoC DAC0 FN0[0] DAC1 Event Detect FN0[3] Trip Hysteretic Mode Controller 3 External Gate Drive 3 GD3 Hysteretic Mode Controller 0 External Gate Drive 0 GD 0 External FET FN0[1] FN0[2] FN0[3] DAC6 . . . Hysteretic Mode Controller 3 DAC7 External Gate Drive 3 GD 3 Document Number: 001-46319 Rev. *N Page 12 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 6. PSoC Core The PSoC core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable General Purpose I/O(GPIO). The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with up to 20 vectors to simplify programming of real time embedded events. The program execution is timed and protected using the included Sleep and Watchdog Timers (WDT) time and protect program execution. Memory encompasses 16 K of Flash for program storage, 1K of SRAM for data storage, and up to 2 K of EEPROM emulated using the Flash. Program Flash uses four protection levels on blocks of 64 bytes, allowing customized software IP protection. The PSoC device incorporates flexible internal clock generators, including a 24 MHz internal main oscillator (IMO) accurate to 4 percent over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz internal low speed oscillator (ILO) is provided for the Sleep timer and WDT. The clocks, together with programmable clock dividers (as a system resource), provide the flexibility to integrate almost any timing requirement into the PowerPSoC device. PowerPSoC GPIOs provide connection to the CPU, digital, and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. 8 8 Row Input also allow signal multiplexing and performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. There are four digital blocks in each row. This allows optimum choice of system resources for your application. Figure 6-1. Digital System Block Diagram P o rt 1 P o rt 2 P o rt 0 D ig ita l C lo c k s F ro m C o re T o S y s te m B u s T o A n a lo g S y s te m D IG IT A L S Y S T E M D ig ita l P S o C B lo c k A r r a y Configuration Row 0 DBB00 DBB01 DCB02 4 DCB03 4 8 8 Configuration Row Output DBB00 Configuration Row 1 DBB10 DBB11 D Row Input 4 DCB13 4 Configuration Row Output DCB12 G IE [7 :0 ] G IO [7 :0 ] G lo b a l D ig ita l In te rc o n n e c t G O E [7 :0 ] G O O [7 :0 ] 6.2 Analog System The analog system contains six configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PowerPSoC analog functions (most available as user modules) are: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ 6.1 Digital System The digital system contains eight digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Digital peripheral configurations include: ■ ■ ■ ■ ■ ■ ■ ■ ■ DMX512 Counters (8 to 32 bit) Timers (8 to 32 bit) UART 8-bit with selectable parity SPI master and slave I2C master, slave, and multi-master Cyclical redundancy checker/generator (8 to 32 bit) IrDA Pseudo random sequence generators (8 to 32 bit) Analog-to-digital converters (up to 2, with 6 to 12-bit resolution, selectable as incremental, Delta Sigma, and SAR) Filters (2 and 4 pole band-pass, low-pass, and notch) Amplifiers (up to 2, with selectable gain to 48x) Instrumentation amplifiers (1 with selectable gain to 93x) Comparators (up to 2, with 16 selectable thresholds) DACs (up to 2, with 6 to 9-bit resolution) Multiplying DACs (up to 2, with 6 to 9-bit resolution) High current output drivers (two with 30 mA drive as a PSoC core resource) 1.3 V reference (as a system resource) Modulators Correlators Peak detectors Many other topologies possible Note The DALI interface is supported through the use of a combination of the above mentioned user modules. For more details on the exact configuration and an example project, refer to the application note, Implementing a DALI Receiver System Using PowerPSoC™ - AN52525. The digital blocks can be connected to any GPIO through a series of global buses that route any signal to any pin. The buses Document Number: 001-46319 Rev. *N Page 13 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 Analog blocks are arranged in two columns of three blocks each, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks, as shown in Figure 6-2. on page 14. Figure 6-2. Analog System Block Diagram P0[7] P0[4] measurement for applications such as touch sensing. Other multiplexer applications include: ■ ■ Track pad, finger sensing Crosspoint connection between any I/O pin combinations P0[5] P1[4] P0[3] P1[7] P1[0] P1[5] P1[1] AINX P2[2] Like other PSoC devices, PowerPSoC has specific pins allocated to the reference capacitor (Ref Cap) and modulation resistor (Mod resistor). These are indicated in the device pin outs (Section 13). For more details on Capacitive Sensing, refer to the application notes AN2394 - CapSense Best Practices, AN2292 - Capacitance Sensing Layout Guidelines for PSoC CapSense and AN47456 - Design Guide CapSense buttons with CSD. Apart from these, there are a number of application notes on Capacitive Sensing on the Cypress webbiest. The PowerPSoC Technical Reference Manual provides details on the analog system configuration that enables all I/Os in the device to be CapSense inputs. CSA Buffered Output 6.4 Additional System Resources Analog Mux Bus Right Array Input Configuration Analog Mux Bus Left ACI0[1:0] ACM0 ACol1Mux AC1 ACol0Mux SplitMux Bit Array ACB00 ASC10 ASD20 ACB01 ASD11 ASC21 BCol1Mux ACI1[1:0] ACM1 System resources provide additional capability useful in complete systems. Additional resources include a multiplier, decimator, low voltage detection, and power on reset. Brief statements describing the merits of each resource follow. ■ Two multiply accumulates (MACs) provide fast 8-bit multipliers with 32-bit accumulate, to assist in both general math and digital filters. A decimator provides a custom hardware filter for digital signal processing applications including creation of Delta Sigma ADCs. Low Voltage Detection (LVD) interrupts signal the application of falling voltage levels, while the advanced POR (power on reset) circuit eliminates the need for a system supervisor. Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. The designer can generate additional clocks using digital PSoC blocks as clock dividers. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master applications are supported. An internal 1.3 V reference provides an absolute reference for the analog system, including ADCs and DACs. Versatile analog multiplexer system. ■ ■ Interface to Digital System Vdd Vss AGND=VBG Reference Generators Bandgap ■ Microcontroller Interface (Address Bus, Data Bus, Etc.) 6.3 Analog Multiplexer System The Analog Mux Bus connects to every GPIO pin in ports 0 to 2. Pins can be connected to the bus individually or in any combination. The bus also connects to the analog system for analysis with comparators and analog-to-digital converters. It can be split into two sections for simultaneous dual-channel processing. An additional analog input multiplexer provides a second path to bring Port 0 pins to the analog array. Switch control logic enables selected pins to precharge continuously under hardware control. This enables capacitive ■ ■ ■ Document Number: 001-46319 Rev. *N Page 14 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 7. Applications The following figures show examples of applications in which the PowerPSoC family of devices adds intelligent power control for power applications. Figure 7-1. LED Lighting with RGGB Color Mixing Configured as Floating Load Buck Converter HVDD RSENSE HVDD RSENSE HVDD RSENSE HVDD RSENSE Dual mode Hysteretic PWM 1 PWM Hysteretic references DAC0 DAC1 Dim MOD Hysteretic PWM Hysteretic references DAC0 DAC1 Dim MOD Hysteretic PWM Hysteretic references DAC0 DAC1 Dim MOD Hysteretic PWM Hysteretic references DAC0 DAC1 Dim MOD Oscillator and Power I2C Master and Slave Configurable Analog Flash, RAM, and ROM M8C Core and IRQ Configurable Digital Blocks Auxiliary Power Regulator Figure 7-2. LED Lighting with RGBA Color Mixing Driving External MOSFETS as Floating Load Buck Converter HVDD Rsense HVDD Rsense HVDD Rsense HVDD Rsense Dual mode 1 Hysteretic PWM References DAC0 DAC1 Dim MOD Gate Drive Dual mode 1 Hysteretic PWM References DAC0 DAC1 Dim MOD Gate Drive Dual mode 1 Hysteretic PWM References DAC0 DAC1 Dim MOD Gate Drive Dual mode 1 Hysteretic PWM References DAC0 DAC1 Dim MOD Gate Drive Oscillator and Power I2C Master and Slave Configurable Analog Auxiliary Power Regulator Flash , RAM , and ROM M8C Core and IRQ Configurable Digital Blocks Document Number: 001-46319 Rev. *N Page 15 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 Figure 7-3. LED Lighting with a Single Channel Boost Driving Three Floating Load Buck Channels HVDD R SENSE R SENSE R SENSE R SENSE Hysteretic PWM Hysteretic references DAC0 DAC1 Dim MOD Hysteretic PWM Hysteretic references DAC0 DAC1 Dim MOD Hysteretic PWM Hysteretic references DAC0 DAC1 Dim MOD Hysteretic PWM Hysteretic references DAC0 DAC1 Dim MOD Oscillator and Power I2 C Master and Slave Configurable Analog Flash, RAM, and ROM M8C Core and IRQ Configurable Digital Blocks Auxiliary Power Regulator 8. PowerPSoC Device Characteristics There are two major groups of devices in the PowerPSoC family. One group is a 4-channel 56-pin QFN and the other is a 3-channel 56-pin QFN. These are summarized in the following table. Table 8-1. PowerPSoC Device Characteristics Device Group CY8CLED04D01-56LTXI CY8CLED04D02-56LTXI CY8CLED04G01-56LTXI CY8CLED03D01-56LTXI CY8CLED03D02-56LTXI CY8CLED03G01-56LTXI CY8CLED02D01-56LTXI CY8CLED01D01-56LTXI CY8CLED01D01-56LTXQ Internal Power FETs 4X1.0 A 4X0.5 A 0 3X1.0 A 3X0.5 A 0 2X1.0 A 1X1.0 A 1X1.0 A External Gate Drivers 4 4 4 3 3 3 2 1 1 Digital I/O 14 14 14 14 14 14 14 14 14 Digital Rows 2 2 2 2 2 2 2 2 2 Digital Blocks 8 8 8 8 8 8 8 8 8 Analog Inputs 14 14 14 14 14 14 14 14 14 Analog Outputs 2 2 2 2 2 2 2 2 2 Analog Columns 2 2 2 2 2 2 2 2 2 Analog Blocks 6 6 6 6 6 6 6 6 6 SRAM Size 1K 1K 1K 1K 1K 1K 1K 1K 1K Flash Size 16 K 16 K 16 K 16 K 16 K 16 K 16 K 16 K 16 K Document Number: 001-46319 Rev. *N Page 16 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 9. Getting Started The quickest way to understand the PowerPSoC device is to read this datasheet and then use the PSoC Designer Integrated Development Environment (IDE). This datasheet is an overview of the PowerPSoC integrated circuit and presents specific pin, register, and electrical specifications. For in depth information, along with detailed programming information, refer to the PowerPSoC Technical Reference Manual. For up-to-date ordering, packaging, and electrical specification information, see the latest PowerPSoC device datasheets on the web at www.cypress.com. PSoC Designer also supports C language compilers developed specifically for the devices in the PowerPSoC family. 10.1 PSoC Designer Software Subsystems 10.1.1 Chip-Level View The chip-level view is a more traditional integrated development environment (IDE) based on PSoC Designer. Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PowerPSoC blocks. Examples of user modules are Current Sense Amplifiers, PrISM, PWM, DMM, Floating Load Buck, and Boost. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time. 10.1.2 Code Generation Tools PSoC Designer supports multiple third party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours. Assemblers. The assemblers allow assembly code to merge seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PowerPSoC family of devices. The products allow you to create complete C programs for the PowerPSoC family of devices. The optimizing C compilers provide all the features of C tailored to the PowerPSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. 10.1.3 Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PowerPSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write I/O registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. 10.1.4 Online Help System The online help system displays online, context-sensitive help for you. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. 9.1 Application Notes Application notes are an excellent introduction to a wide variety of possible PowerPSoC designs. Layout Guidelines, Thermal Management and Firmware Design Guidelines are some of the topics covered. To view the PowerPSoC application notes, go to htttp://www.cypress.com/powerpsoc and click on the Application Notes link. 9.2 Development Kits Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for PowerPSoC development. For more information on the kits or to purchase a kit from the Cypress web site, go to htttp://www.cypress.com/powerpsoc and click on the Development Kits link. 9.3 Training Free PowerPSoC technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training. The training covers a wide variety of topics and skill levels to assist you in your designs. 9.4 CYPros Consultants Certified PSoC Consultants offer everything from technical assistance to completed PowerPSoC designs. To contact or become a PSoC Consultant go to www.cypress.com/cypros. 9.5 Technical Support PowerPSoC application engineers take pride in fast and accurate response. They can be reached with a 24-hour guaranteed response at http://www.cypress.com/support/. If you cannot find an answer to your question, call technical support at 1-800-541-4736. 10. Development Tools PSoC Designer is a Microsoft® Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE runs on Windows XP, Windows Vista, or Windows 7. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built-in support for third-party assemblers and C compilers. Document Number: 001-46319 Rev. *N Page 17 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 10.2 In-Circuit Emulator A low cost, high functionality In-Circuit Emulator (ICE) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with all PowerPSoC devices. 11. Designing with User Modules The development process for the PowerPSoC device differs from that of a traditional fixed function microprocessor. The configurable power, analog, and digital hardware blocks give the PowerPSoC architecture a unique flexibility that pays dividends in managing specification change during development and by lowering inventory costs. These configurable resources, called PowerPSoC Blocks, have the ability to implement a wide variety of user-selectable functions. The PowerPSOC development process can be summarized in the following four steps: 1. Select Components 2. Configure Components 3. Organize and Connect 4. Generate, Verify and Debug Select Components. In the chip-level view the components are called “user modules”. User modules make selecting and implementing peripheral devices simple and come in power, analog, digital, and mixed signal varieties. The standard user module library contains over 50 common peripherals such as Current Sense Amplifiers, PrISM, PWM, DMM, Floating Buck, Boost, ADCs, DACs, Timers, Counters, UARTs, and other not so common peripherals such as DTMF generators and Bi-Quad analog filter sections. Configure Components. Each of the components selected establishes the basic register settings that implement the selected function. They also provide parameters allowing precise configuration to your particular application. For example, a PWM User Module configures one or more digital PSoC blocks, one for each 8 bits of resolution. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. The chip-level user modules are documented in datasheets that are viewed directly in PSoC Designer. These datasheets explain the internal operation of the component and provide performance specifications. Each datasheet describes the use of each user module parameter and other information needed to successfully implement your design. Organize and Connect. Signal chains can be built at the chip level by interconnecting user modules to each other and the I/O pins. In the chip-level view, perform the selection, configuration, and routing so that you have complete control over the use of all on-chip resources. Generate, Verify, and Debug. When ready to test the hardware configuration or move on to developing code for the project, perform the “Generate Application” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the high level user module API functions. The chip-level designs generate software based on your design. The chip-level view provides application programming interfaces (APIs) with high level functions to control and respond to hardware events at run-time and interrupt service routines that you can adapt as needed. A complete code development environment allows development and customization of your applications in C, assembly language, or both. The last step in the development process takes place inside the PSoC Designer’s Debugger subsystem. The Debugger downloads the HEX image to the ICE where it runs at full speed. Debugger capabilities rival those of systems costing many times more. In addition to traditional single step, run-to-breakpoint and watch-variable features, the Debugger provides a large trace buffer and allows you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals. Document Number: 001-46319 Rev. *N Page 18 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 12. Pin Information 12.1 CY8CLED04D0x 56-Pin Part Pinout (without OCD) The CY8CLED04D01 and CY8CLED04D02 PowerPSoC devices are available with the following pinout information. Every port pin (labeled with a “P” and “FN0”) is capable of Digital I/O. Table 12-1. CY8CLED04D0x 56-Pin Part Pinout (QFN) Pin No. Digital Rows Type Analog Power Columns Peripherals Figure 12-1. CY8CLED04D0x 56-Pin PowerPSoC Device Name P1[0] Description GPIO/I2C SDA (Secondary)/ ISSP SDATA P2[2] GPIO/Direct Switch Cap connection P0[3] GPIO/Analog Input (Column 0)/ Analog Output (Column 0) P0[5] GPIO/Analog Input (Column 0)/ Analog Output (Column 1)/ Capsense Ref Cap P0[7] GPIO/Analog Input (Column 0)/ Capsense Ref Cap P1[1] GPIO/I2C SCL (Secondary)/ISSP SCLK P1[5] GPIO/I2C SDA (Primary) P1[7] GPIO/I2C SCL (Primary) VSS Digital Ground NC No Connect NC No Connect NC No Connect NC No Connect XRES External Reset VDD Digital Power Supply VSS Digital Ground AVSS Analog Ground AVDD Analog Power Supply CSN2 Current Sense Negative Input CSA2 CSP2 Current Sense Positive Input and Power Supply - CSA2 CSP3 Current Sense Positive Input and Power Supply - CSA3 CSN3 Current Sense Negative Input 3 SREGCOMP Voltage Regulator Error Amp Comp SREGFB Regulator Voltage Mode Feedback Node SREGCSN Current Mode Feedback Negative SREGCSP Current Mode Feedback Positive SREGSW Switch Mode Regulator OUT SREGHVIN Switch Mode Regulator IN GDVDD Gate Driver Power Supply GDVSS Gate Driver Ground PGND3[1] GD3 SW3 PGND2[1] GD2 SW2 SW1 GD1 PGND1[1] SW0 O GD0 PGND0[1] GDVSS Power FET Ground 3 External Low Side Gate Driver 3 Power Switch 3 Power FET Ground 2 External Low Side Gate Driver 2 Power Switch 2 Power Switch 1 External Low Side Gate Driver 1 Power FET Ground 1 Power Switch 0 External Low Side Gate Driver 0 Power FETGround 0 Gate Driver Ground 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 I/O I/O I/O I/O I/O I/O I/O I/O I I I/O I/O I I I I QFN Top View I P1[0] P2[2] P0[3] P0[5] P0[7] P1[1] P1[5] P1[7] VSS NC NC NC NC XRES VDD VSS AVSS AVDD CSN2 CSP2 CSP3 CSN3 SREGCOMP SREGFB SREGCSN SREGCSP I * Connect Exposed Pad to PGNDx I I I I O Pin No. Digital 44 45 46 47 48 49 50 51 52 53 54 55 56 Type Name GDVDD FN0[0] FN0[1] FN0[2] FN0[3] CSN0 CSP0 CSP1 I CSN1 P0[4] VDD VSS P1[4] Description Gate Driver Power Supply Function I/O Function I/O Function I/O Function I/O Current Sense Negative Input 0 Current Sense Positive Input and Power Supply - CSA0 Current Sense Positive Input and Power Supply - CSA1 Current Sense Negative Input 1 GPIO/Analog Input (Column 1) / Bandgap Output Digital Power Supply Digital Ground GPIO / External Clock Input Analog Power Rows Columns Peripherals O O I/O I/O I/O I/O I O I/O I I/O I Note 1. All PGNDx pins must be connected to the ground plane on the PCB irrespective of whether the corresponding PowerPSoC channel is used or not. Document Number: 001-46319 Rev. *N SREGSW SREGHVIN 15 16 17 18 19 20 21 22 23 24 25 26 27 28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 56 55 54 53 52 51 50 49 48 47 46 45 44 43 P1[4] VSS VDD P0[4] CSN1 CSP1 CSP0 CSN0 FN0[3] FN0[2] FN0[1] FN0[0] GDVDD GDVSS Exposed Pad 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PGND0 GD0 SW0 PGND1 GD1 SW1 SW2 GD2 PGND2 SW3 GD3 PGND3 GDVSS GDVDD Page 19 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 12.2 CY8CLED04G01 56-Pin Part Pinout (without OCD) The CY8CLED04G01 PowerPSoC device is available with the following pinout information. Every port pin (labeled with a “P” and “FN0”) is capable of Digital I/O. Table 12-2. CY8CLED04G01 56-Pin Part Pinout (QFN) Pin No. Digital Rows Type Analog Power Columns Peripherals Name P1[0] Description Figure 12-2. CY8CLED04G01 56-Pin PowerPSoC Device 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 I/O I/O I/O I/O I/O I/O I/O I/O I I I/O I/O I I I I I I I I I I O GPIO/I2C SDA (Secondary)/ ISSP SDATA P2[2] GPIO/Direct Switch Cap connection P0[3] GPIO/Analog Input (Column 0)/ Analog Output (Column 0) P0[5] GPIO/Analog Input (Column 0)/ Analog Output (Column 1)/ Capsense Ref Cap P0[7] GPIO/Analog Input (Column 0)/ Capsense Ref Cap P1[1] GPIO/I2C SCL (Secondary)/ ISSP SCLK P1[5] GPIO/I2C SDA (Primary) P1[7] GPIO/I2C SCL (Primary) VSS Digital Ground NC No Connect NC No Connect NC No Connect NC No Connect XRES External Reset VDD Digital Power Supply VSS Digital Ground AVSS Analog Ground AVDD Analog Power Supply CSN2 Current Sense Negative Input 2 CSP2 Current Sense Positive Input and Power Supply - CSA2 CSP3 Current Sense Positive Input and Power Supply - CSA3 CSN3 Current Sense Negative Input 3 SREGCOMP Voltage Regulator Error Amp Comp SREGFB Regulator Voltage Mode Feedback Node SREGCSN Current Mode Feedback Negative SREGCSP Current Mode Feedback Positive SREGSW Switch Mode Regulator OUT SREGHVIN Switch Mode Regulator IN GDVDD Gate Driver Power Supply Pin GDVSS Gate Driver Ground No. Digital PGND3[3] GD3 DNC[2] PGND2[3] GD2 DNC[2] DNC[2] GD1 PGND1[3] DNC[2] Power FET Ground 3 External Low Side Gate Driver 3 Do Not Connect Power FET Ground 2 External Low Side Gate Driver 2 Do Not Connect Do Not Connect External Low Side Gate Driver 1 Power FET Ground 1 Do Not Connect External Low Side Gate Driver 0 Power FET Ground 0 Gate Driver Ground 44 45 46 47 48 49 50 51 52 53 54 55 56 QFN Top View P1[4] VSS VDD P0[4] CSN1 CSP1 CSP0 CSN0 FN0[3] FN0[2] FN0[1] FN0[0] GDVDD GDVSS P1[0] P2[2] P0[3] P0[5] P0[7] P1[1] P1[5] P1[7] VSS NC NC NC NC XRES 1 2 3 4 5 6 7 8 9 10 11 12 13 14 56 55 54 53 52 51 50 49 48 47 46 45 44 43 Exposed Pad VDD VS S AVS S AVD D CSN 2 CSP 2 CSP 3 CSN 3 SREGCOMP SREGFB SREGCSN * Connect Exposed Pad to PGNDx Type Name GDVDD FN0[0] FN0[1] FN0[2] FN0[3] CSN0 CSP0 CSP1 I CSN1 P0[4] VDD VSS P1[4] Description Gate Driver Power Supply Function I/O Function I/O Function I/O Function I/O Current Sense Negative Input 0 Current Sense Positive Input and Power Supply - CSA0 Current Sense Positive Input and Power Supply - CSA1 Current Sense Negative Input 1 GPIO/Analog Input (Column 1) / Bandgap Output Digital Power Supply Digital Ground GPIO / External Clock Input Analog Power Rows Columns Peripherals O O I/O I/O I/O I/O I O I/O I O GD0 PGND0[3] GDVSS I/O I Notes 2. Do Not Connect (DNC) pins must be left unconnected, or floating. Connecting these pins to power or ground may cause improper operation or failure of the device. 3. All PGNDx pins must be connected to the ground plane on the PCB irrespective of whether the corresponding PowerPSoC channel is used or not. Document Number: 001-46319 Rev. *N SREGHVIN SREGCSP SREGSW 15 16 17 18 19 20 21 22 23 24 25 26 27 28 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PGND0 GD0 DNC PGND1 GD1 DNC DNC GD2 PGND2 DNC GD3 PGND3 GDVSS GDVDD Page 20 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 12.3 CY8CLED04DOCD1 56-Pin Part Pinout (with OCD) The CY8CLED04DOCD1 PowerPSoC device is available with the following pinout information. Every port pin (labeled with a “P” and “FN0”) is capable of Digital I/O. Table 12-3. CY8CLED04DOCD1 56-Pin Part Pinout (QFN) Pin No. Digital 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 O I I I I O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I Type Name P1[0] Description Figure 12-3. CY8CLED04DOCD1 56-Pin PowerPSoC Device Analog Power Rows Columns Peripherals I I I/O I/O I I I I I GPIO/I2C SDA (Secondary)/ ISSP SDATA P2[2] GPIO/Direct Switch Cap connection P0[3] GPIO/Analog Input (Column 0)/ Analog Output (Column 0) P0[5] GPIO/Analog Input (Column 0)/ Analog Output (Column 1) / Capsense Ref Cap P0[7] GPIO/Analog Input (Column 0)/ Capsense Ref Cap P1[1] GPIO/I2C SCL (Secondary)/ ISSP SCLK P1[5] GPIO/I2C SDA (Primary) P1[7] GPIO/I2C SCL (Primary) VSS Digital Ground OCDE On Chip Debugger Port OCDO On Chip Debugger Port CCLK On Chip Debugger Port HCLK On Chip Debugger Port XRES External Reset VDD Digital Power Supply VSS Digital Ground AVSS Analog Ground AVDD Analog Power Supply CSN2 Current Sense Negative Input 2 CSP2 Current Sense Positive Input and Power Supply - CSA2 CSP3 Current Sense Positive Input and Power Supply - CSA3 CSN3 Current Sense Negative Input 3 SREGCOMP Voltage Regulator Error Amp Comp SREGFB Regulator Voltage Mode Feedback Node SREGCSN Current Mode Feedback Negative SREGCSP Current Mode Feedback Positive SREGSW Switch Mode Regulator OUT SREGHVIN Switch Mode Regulator IN GDVDD Gate Driver Power Supply Pin GDVSS Gate Driver Ground No. Digital PGND3[4] GD3 SW3 PGND2[4] GD2 SW2 SW1 GD1 PGND1[4] SW0 GD0 PGND0[4] GDVSS Power FET Ground 3 External Low Side Gate Driver 3 Power Switch 3 Power FET Ground 2 External Low Side Gate Driver 2 Power Switch 2 Power Switch 1 External Low Side Gate Driver 1 Power FET Ground 1 Power Switch 0 External Low Side Gate Driver 0 Power FET Ground 0 Gate Driver Ground 44 45 46 47 48 49 50 51 52 53 54 55 56 QFN Top View CSN0 FN0[3] FN0[2] FN0[1] FN0[0] GDVDD GDVSS 44 43 CSN1 CSP1 CSP0 P1[4] VSS VDD P0[4] P1[0] P2[2] P0[3] P0[5] P0[7] P1[1] P1[5] P1[7] VSS OCDE OCDO CCLK HCLK XRES 1 2 3 4 5 6 7 8 9 10 11 12 13 14 56 55 54 53 52 51 50 49 48 47 46 45 Exposed Pad 15 16 17 18 19 20 21 22 23 24 AVSS AVDD CSN2 CSP2 CSP3 VDD VSS CSN3 SREGCOMP SREGFB * Connect Exposed Pad to PGNDx Type Name GDVDD FN0[0] FN0[1] FN0[2] FN0[3] CSN0 CSP0 CSP1 I CSN1 P0[4] VDD VSS P1[4] Description Gate Driver Power Supply Function I/O Function I/O Function I/O Function I/O Current Sense Negative Input 0 Current Sense Positive Input and Power Supply - CSA0 Current Sense Positive Input and Power Supply - CSA1 Current Sense Negative Input 1 GPIO/Analog Input (Column 1) / Bandgap Output Digital Power Supply Digital Ground GPIO / External Clock Input Analog Power Rows Columns Peripherals O O I/O I/O I/O I/O I O I/O I I/O I Note 4. All PGNDx pins must be connected to the ground plane on the PCB irrespective of whether the corresponding PowerPSoC channel is used or not. Document Number: 001-46319 Rev. *N SREGSW SREGHVIN SREGCSN SREGCSP 25 26 27 28 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PGND0 GD0 SW0 PGND1 GD1 SW1 SW2 GD2 PGND2 SW3 GD3 PGND3 GDVSS GDVDD Page 21 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 12.4 CY8CLED03D0x 56-Pin Part Pinout (without OCD) The CY8CLED03D01 and CY8CLED03D02 PowerPSoC devices are available with the following pinout information. Every port pin (labeled with a “P” and “FN0”) is capable of Digital I/O. Table 12-4. CY8CLED03D0x 56-Pin Part Pinout (QFN) Type Pin No. Digital Analog 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 O I/O I/O I/O I/O I/O I/O I/O I/O I I I/O I/O I I I I Figure 12-4. CY8CLED03D0x 56-Pin PowerPSoC Device Name P1[0] Description GPIO/I2C SDA (Secondary)/ ISSP SDATA P2[2] GPIO/Direct Switch Cap connection P0[3] GPIO/Analog Input (Column 0)/ Analog Output (Column 0) P0[5] GPIO/Analog Input (Column 0)/ Analog Output (Column 1)/ Capsense Ref Cap P0[7] GPIO/Analog Input (Column 0)/ Capsense Ref Cap P1[1] GPIO/I2C SCL (Secondary)/ ISSP SCLK P1[5] GPIO/I2C SDA (Primary) P1[7] GPIO/I2C SCL (Primary) VSS Digital Ground NC No Connect NC No Connect NC No Connect NC No Connect XRES External Reset VDD Digital Power Supply VSS Digital Ground AVSS Analog Ground AVDD Analog Power Supply CSN2 Current Sense Negative Input CSA2 CSP2 Current Sense Positive Input and Power Supply - CSA2 DNC[5] Do Not Connect DNC[5] Do Not Connect SREGCOMP Voltage Regulator Error Amp Comp SREGFB Regulator Voltage Mode Feedback Node SREGCSN Current Mode Feedback Negative SREGCSP Current Mode Feedback Positive SREGSW Switch Mode Regulator OUT SREGHVIN Switch Mode Regulator IN GDVDD Gate Driver Power Supply Pin GDVSS Gate Driver Ground No. Digital Rows Power Rows Columns Peripherals QFN Top View P1[4] VSS VDD P0[4] CSN1 CSP1 CSP0 CSN0 FN0[3] FN0[2] FN0[1] FN0[0] GDVDD GDVSS P1[0] P2[2] P0[3] P0[5] P0[7] P1[1] P1[5] P1[7] VSS NC NC NC NC XRES 1 2 3 4 5 6 7 8 9 10 11 12 13 14 56 55 54 53 52 51 50 49 48 47 46 45 44 43 Exposed Pad I VDD VSS AVSS AVDD CSN2 CSP2 DNC DNC SREGCOMP SREGFB SREGCSN SREGCSP I * Connect Exposed Pad to PGNDx I I I O Type Analog Power Columns Peripherals Name GDVDD FN0[0] FN0[1] FN0[2] FN0[3] CSN0 CSP0 CSP1 SREGSW SREGHVIN 15 16 17 18 19 20 21 22 23 24 25 26 27 28 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PGND0 GD0 SW0 PGND1 GD1 SW1 SW2 GD2 PGND2 DNC DNC PGND3 GDVSS GDVDD Description Gate Driver Power Supply Function I/O Function I/O Function I/O Function I/O Current Sense Negative Input 0 Current Sense Positive Input and Power Supply - CSA0 Current Sense Positive Input and Power Supply - CSA1 Current Sense Negative Input 1 GPIO/Analog Input (Column 1) / Bandgap Output Digital Power Supply Digital Ground GPIO / External Clock Input O PGND3[6] DNC[5] DNC[5] PGND2[6] GD2 SW2 SW1 GD1 PGND1 SW0 [6] Power FET Ground 3 Do Not Connect Do Not Connect Power FET Ground 2 External Low Side Gate Driver 2 Power Switch 2 Power Switch 1 External Low Side Gate Driver 1 Power FET Ground 1 Power Switch 0 External Low Side Gate Driver 0 Power FETGround 0 Gate Driver Ground 44 45 46 47 48 49 50 51 52 53 54 55 56 I/O I/O I/O I/O I O I I/O I CSN1 P0[4] VDD VSS P1[4] GD0 PGND0[6] GDVSS I/O I Notes 5. Do Not Connect (DNC) pins must be left unconnected, or floating. Connecting these pins to power or ground may cause improper operation or failure of the device. 6. All PGNDx pins must be connected to the ground plane on the PCB irrespective of whether the corresponding PowerPSoC channel is used or not. Document Number: 001-46319 Rev. *N Page 22 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 12.5 CY8CLED03G01 56-Pin Part Pinout (without OCD) The CY8CLED03G01 PowerPSoC device is available with the following pinout information. Every port pin (labeled with a “P” and “FN0”) is capable of Digital I/O. Table 12-5. CY8CLED03G01 56-Pin Part Pinout (QFN) Pin No. Digital Rows Type Analog Power Columns Peripherals Name P1[0] Description Figure 12-5. CY8CLED03G01 56-Pin PowerPSoC Device 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 I/O I/O I/O I/O I/O I/O I/O I/O I I I/O I/O I I I I I I I I I O GPIO/I2C SDA (Secondary)/ ISSP SDATA P2[2] GPIO/Direct Switch Cap connection P0[3] GPIO/Analog Input (Column 0)/ Analog Output (Column 0) P0[5] GPIO/Analog Input (Column 0)/ Analog Output (Column 1)/ Capsense Ref Cap P0[7] GPIO/Analog Input (Column 0)/ Capsense Ref Cap P1[1] GPIO/I2C SCL (Secondary)/ ISSP SCLK P1[5] GPIO/I2C SDA (Primary) P1[7] GPIO/I2C SCL (Primary) VSS Digital Ground NC No Connect NC No Connect NC No Connect NC No Connect XRES External Reset VDD Digital Power Supply VSS Digital Ground AVSS Analog Ground AVDD Analog Power Supply CSN2 Current Sense Negative Input 2 CSP2 Current Sense Positive Input and Power Supply - CSA2 DNC[7] Do Not Connect DNC[7] Do Not Connect SREGCOMP Voltage Regulator Error Amp Comp SREGFB Regulator Voltage Mode Feedback Node SREGCSN Current Mode Feedback Negative SREGCSP Current Mode Feedback Positive SREGSW Switch Mode Regulator OUT SREGHVIN Switch Mode Regulator IN GDVDD Gate Driver Power Supply Pin GDVSS Gate Driver Ground No. Digital PGND3[8] DNC[7] DNC[7] PGND2[8] GD2 DNC[7] DNC[7] GD1 PGND1 DNC[7] [8] QFN Top View P1[4] VSS VDD P0[4] CSN1 CSP1 CSP0 CSN0 FN0[3] FN0[2] FN0[1] FN0[0] GDVDD GDVSS P1[0] P2[2] P0[3] P0[5] P0[7] P1[1] P1[5] P1[7] VSS NC NC NC NC XRES 1 2 3 4 5 6 7 8 9 10 11 12 13 14 56 55 54 53 52 51 50 49 48 47 46 45 44 43 Exposed Pad VDD VSS AVSS AVDD CSN2 CSP2 DNC DNC SREGCOMP SREGFB SREGCSN SREGCSP * Connect Exposed Pad to PGNDx Type Name GDVDD FN0[0] FN0[1] FN0[2] FN0[3] CSN0 CSP0 CSP1 I CSN1 P0[4] VDD VSS P1[4] Description Gate Driver Power Supply Function I/O Function I/O Function I/O Function I/O Current Sense Negative Input 0 Current Sense Positive Input and Power Supply - CSA0 Current Sense Positive Input and Power Supply - CSA1 Current Sense Negative Input 1 GPIO/Analog Input (Column 1) / Bandgap Output Digital Power Supply Digital Ground GPIO / External Clock Input Analog Power Rows Columns Peripherals O Power FET Ground 3 Do Not Connect Do Not Connect Power FET Ground 2 External Low Side Gate Driver 2 Do Not Connect Do Not Connect External Low Side Gate Driver 1 Power FET Ground 1 Do Not Connect External Low Side Gate Driver 0 Power FET Ground 0 Gate Driver Ground 44 45 46 47 48 49 50 51 52 53 54 55 56 I/O I/O I/O I/O I O I/O I O GD0 PGND0[8] GDVSS I/O I Notes 7. Do Not Connect (DNC) pins must be left unconnected, or floating. Connecting these pins to power or ground may cause improper operation or failure of the device. 8. All PGNDx pins must be connected to the ground plane on the PCB irrespective of whether the corresponding PowerPSoC channel is used or not. Document Number: 001-46319 Rev. *N SREGSW SREGHVIN 15 16 17 18 19 20 21 22 23 24 25 26 27 28 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PGND0 GD0 DNC PGND1 GD1 DNC DNC GD2 PGND2 DNC DNC PGND3 GDVSS GDVDD Page 23 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 12.6 CY8CLED02D01 56-Pin Part Pinout (without OCD) The CY8CLED02D01 PowerPSoC devices are available with the following pinout information. Every port pin (labeled with a “P” and “FN0”) is capable of Digital I/O. Table 12-6. CY8CLED02D01 56-Pin Part Pinout (QFN) Type Pin No. Digital Analog 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 O O I/O I/O I/O I/O I/O I/O I/O I/O I I I/O I/O I I I I Figure 12-6. CY8CLED02D01 56-Pin PowerPSoC Device Name P1[0] Description GPIO/I2C SDA (Secondary)/ ISSP SDATA P2[2] GPIO/Direct Switch Cap connection P0[3] GPIO/Analog Input (Column 0)/ Analog Output (Column 0) P0[5] GPIO/Analog Input (Column 0)/ Analog Output (Column 1)/ Capsense Ref Cap P0[7] GPIO/Analog Input (Column 0)/ Capsense Ref Cap P1[1] GPIO/I2C SCLK (Secondary)/ ISSP SCLK P1[5] GPIO/I2C SDA (Primary) P1[7] GPIO/I2C SCL (Primary) VSS Digital Ground NC No Connect NC No Connect NC No Connect NC No Connect XRES External Reset VDD Digital Power Supply VSS Digital Ground AVSS Analog Ground AVDD Analog Power Supply DNC[9] Do Not Connect DNC[9] Do Not Connect DNC[9] Do Not Connect DNC[9] Do Not Connect SREGCOMP Voltage Regulator Error Amp Comp SREGFB Regulator Voltage Mode Feedback Node SREGCSN Current Mode Feedback Negative SREGCSP Current Mode Feedback Positive SREGSW Switch Mode Regulator OUT SREGHVIN Switch Mode Regulator IN GDVDD Gate Driver Power Supply Pin GDVSS Gate Driver Ground No. Digital Rows Power Rows Columns Peripherals QFN Top View P1[4] VSS VDD P0[4] CSN1 CSP1 CSP0 CSN0 FN0[3] FN0[2] FN0[1] FN0[0] GDVDD GDVSS P1[0] P2[2] P0[3] P0[5] P0[7] P1[1] P1[5] P1[7] VSS NC NC NC NC XRES 1 2 3 4 5 6 7 8 9 10 11 12 13 14 56 55 54 53 52 51 50 49 48 47 46 45 44 43 Exposed Pad I VDD VSS AVSS AVDD DNC DNC DNC DNC SREGCOMP SREGFB SREGCSN SREGCSP * Connect Exposed Pad to PGNDx I I I O Type Analog Power Columns Peripherals Name GDVDD FN0[0] FN0[1] FN0[2] FN0[3] CSN0 CSP0 CSP1 SREGSW SREGHVIN 15 16 17 18 19 20 21 22 23 24 25 26 27 28 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PGND0 GD0 SW0 PGND1 GD1 SW1 DNC DNC PGND2 DNC DNC PGND3 GDVSS GDVDD Description Gate Driver Power Supply Function I/O Function I/O Function I/O Function I/O Current Sense Negative Input 0 Current Sense Positive Input and Power Supply - CSA0 Current Sense Positive Input and Power Supply - CSA1 Current Sense Negative Input 1 GPIO/Analog Input (Column 1) / Bandgap Output Digital Power Supply Digital Ground GPIO / External Clock Input PGND3[10] DNC[9] DNC[9] PGND2[10] DNC[9] DNC[9] SW1 GD1 PGND1[10] SW0 GD0 PGND0[10] GDVSS Power FET Ground 3 Do Not Connect Do Not Connect Power FET Ground 2 Do Not Connect Do Not Connect Power Switch 1 External Low Side Gate Driver 1 Power FET Ground 1 Power Switch 0 External Low Side Gate Driver 0 Power FETGround 0 Gate Driver Ground 44 45 46 47 48 49 50 51 52 53 54 55 56 I/O I/O I/O I/O I I I/O I CSN1 P0[4] VDD VSS P1[4] I/O I Notes 9. Do Not Connect (DNC) pins must be left unconnected, or floating. Connecting these pins to power or ground may cause improper operation or failure of the device. 10. All PGNDx pins must be connected to the ground plane on the PCB irrespective of whether the corresponding PowerPSoC channel is used or not. Document Number: 001-46319 Rev. *N Page 24 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 12.7 CY8CLED01D01 56-Pin Part Pinout (without OCD) The CY8CLED01D01 PowerPSoC device is available with the following pinout information. Every port pin (labeled with a “P” and “FN0”) is capable of Digital I/O. Table 12-7. CY8CLED01D01 56-Pin Part Pinout (QFN) Pin No. Digital Rows Type Analog Power Columns Peripherals Name P1[0] Description Figure 12-7. CY8CLED01D01 56-Pin PowerPSoC Device 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 I/O I/O I/O I/O I/O I/O I/O I/O I I I/O I/O I I I I I I I I O GPIO/I2C SDA (Secondary)/ ISSP SDATA P2[2] GPIO/Direct Switch Cap connection P0[3] GPIO/Analog Input (Column 0)/ Analog Output (Column 0) P0[5] GPIO/Analog Input (Column 0)/ Analog Output (Column 1)/ Capsense Ref Cap P0[7] GPIO/Analog Input (Column 0)/ Capsense Ref Cap P1[1] GPIO/I2C SCLK (Secondary)/ ISSP SCLK P1[5] GPIO/I2C SDA (Primary) P1[7] GPIO/I2C SCL (Primary) VSS Digital Ground NC No Connect NC No Connect NC No Connect NC No Connect XRES External Reset VDD Digital Power Supply VSS Digital Ground AVSS Analog Ground AVDD Analog Power Supply DNC[11] Do Not Connect DNC[11] Do Not Connect DNC[11] Do Not Connect DNC[11] Do Not Connect SREGCOMP Voltage Regulator Error Amp Comp SREGFB Regulator Voltage Mode Feedback Node SREGCSN Current Mode Feedback Negative SREGCSP Current Mode Feedback Positive SREGSW Switch Mode Regulator OUT SREGHVIN Switch Mode Regulator IN GDVDD Gate Driver Power Supply Pin GDVSS Gate Driver Ground No. Digital PGND3[12] DNC[11] DNC[11] PGND2[12] DNC[11] DNC[11] DNC[11] DNC[11] PGND1[12] SW0 Power FET Ground 3 Do Not Connect Do Not Connect Power FET Ground 2 Do Not Connect Do Not Connect Do Not Connect Do Not Connect Power FET Ground 1 Power Switch 0 External Low Side Gate Driver 0 Power FET Ground 0 Gate Driver Ground 44 45 46 47 48 49 50 51 52 53 54 55 56 QFN Top View P1[4] VSS VDD P0[4] DNC DNC CSP0 CSN0 FN0[3] FN0[2] FN0[1] FN0[0] GDVDD GDVSS P1[0] P2[2] P0[3] P0[5] P0[7] P1[1] P1[5] P1[7] VSS NC NC NC NC XRES 1 2 3 4 5 6 7 8 9 10 11 12 13 14 56 55 54 53 52 51 50 49 48 47 46 45 44 43 Exposed Pad VDD VSS AVSS AVDD DNC DNC DNC DNC SREGCOMP SREGFB SREGCSN SREGCSP * Connect Exposed Pad to PGNDx Type Name GDVDD FN0[0] FN0[1] FN0[2] FN0[3] CSN0 CSP0 Description Analog Power Rows Columns Peripherals I/O I/O I/O I/O I I/O I O GD0 PGND0[12] GDVSS I/O I Gate Driver Power Supply Function I/O Function I/O Function I/O Function I/O Current Sense Negative Input 0 Current Sense Positive Input and Power Supply - CSA0 [11] Do Not Connect DNC DNC[11] Do Not Connect P0[4] GPIO/Analog Input (Column 1) / Bandgap Output VDD Digital Power Supply VSS Digital Ground P1[4] GPIO / External Clock Input Notes 11. Do Not Connect (DNC) pins must be left unconnected, or floating. Connecting these pins to power or ground may cause improper operation or failure of the device. 12. All PGNDx pins must be connected to the ground plane on the PCB irrespective of whether the corresponding PowerPSoC channel is used or not. Document Number: 001-46319 Rev. *N SREGSW SREGHVIN 15 16 17 18 19 20 21 22 23 24 25 26 27 28 42 41 40 39 38 37 36 35 34 33 32 31 30 29 PGND0 GD0 SW0 PGND1 DNC DNC DNC DNC PGND2 DNC DNC PGND3 GDVSS GDVDD Page 25 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 13. Register General Conventions 13.1 Abbreviations Used The register conventions specific to this section are listed in Table 13-1. Table 13-1. Register Conventions Convention R W L C # Description Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific Therefore, ASD13CR3 is a register for an analog PowerPSoC block in row 1 column 3. The register naming convention specific to the power peripheral section of PowerPSoC blocks and their registers is: x where x = number of channel Therefore, CSA0_CR is a register for a power peripheral PowerPSoC block in for Current Sense Amplifier, channel 0. 13.3 Register Mapping Tables The PowerPSoC device has a total register address space of 512 bytes. The register space is also referred to as I/O space and is broken into two parts. The XIO bit in the Flag register (CPU_F) determines which bank you are currently in. When the XIO bit is set, you are said to be in the “extended” address space or the “configuration” registers. More detailed description of the Registers are found in the PowerPSoC TRM. The TRM can be found at http://www.cypress.com/powerpsoc and clicking on the Technical Reference Manual link. 13.2 Register Naming Conventions The register naming convention specific to the PSoC core section of PowerPSoC blocks and their registers is: mn where m = row index, n = column index Document Number: 001-46319 Rev. *N Page 26 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 13.4 Register Map Bank 0 Table Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 FN0DR FN0IE FN0GS FN0DM2 Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DPWM0PCF DPWM0PDH DPWM0PDL DPWM0PWH DPWM0PWL DPWM0PCH DPWM0PCL DPWM0GCFG DPWM1PCF DPWM1PDH DPWM1PDL DPWM1PWH DPWM1PWL DPWM1PCH DPWM1PCL DPWM1GCFG DPWM2PCF DPWM2PDH DPWM2PDL DPWM2PWH DPWM2PWL DPWM2PCH DPWM2PCL DPWM2GCFG DPWM3PCF DPWM3PDH DPWM3PDL DPWM3PWH DPWM3PWL DPWM3PCH DPWM3PCL DPWM3GCFG AMX_IN AMUX_CFG ARF_CR CMP_CR0 ASY_CR CMP_CR1 PAMUX_S1 PAMUX_S2 PAMUX_S3 PAMUX_S4 TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 DPWM0PCFG DPWM1PCFG DPWM2PCFG DPWM3PCFG DPWMINTFLG DPWMINTMSK DPWMSYNC Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # # RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Access RW RW RW RW RW RW RW RW Name VDAC0_CR VDAC0_DR0 VDAC0_DR1 VDAC1_CR VDAC1_DR0 VDAC1_DR1 VDAC2_CR VDAC2_DR0 VDAC2_DR1 VDAC3_CR VDAC3_DR0 VDAC3_DR1 RW RW RW RW RW RW RW RW CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W RC RC RW RW W W R R RW RW RW RW ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 PDMUX_S1 PDMUX_S2 PDMUX_S3 PDMUX_S4 PDMUX_S5 PDMUX_S6 CHBOND_CR DBB00DR0 DBB00DR1 DBB00DR2 DBB00CR0 DBB01DR0 DBB01DR1 DBB01DR2 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 DCB03DR1 DCB03DR2 DCB03CR0 DBB10DR0 DBB10DR1 DBB10DR2 DBB10CR0 DBB11DR0 DBB11DR1 DBB11DR2 DBB11CR0 DCB12DR0 DCB12DR1 DCB12DR2 DCB12CR0 DCB13DR0 DCB13DR1 DCB13DR2 DCB13CR0 RW RW RW RW RW RW RW # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # VDAC6_CR VDAC6_DR0 VDAC6_DR1 VDAC4_CR VDAC4_DR0 VDAC4_DR1 VDAC5_CR VDAC5_DR0 VDAC5_DR1 MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RW RW RW RW RW RW RW RW RW W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW CPU_F RL DAC_D CPU_SCR1 CPU_SCR0 RW # # Document Number: 001-46319 Rev. *N Page 27 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 13.5 Register Map Bank 1 Table: User Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 FN0DM0 FN0DM1 FN0IC0 FN0IC1 Addr (1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name CSA0_CR Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Access RW Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF Access RW RW RW RW RW RW RW RW Name CMPCH0_CR CMPCH2_CR CMPCH4_CR CMPCH6_CR CMPBNK8_CR CMPBNK9_CR CMPBNK10_CR CMPBNK11_CR CMPBNK12_CR CMPBNK13_CR Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access RW RW RW RW RW RW RW RW RW RW CSA1_CR RW CSA2_CR RW CSA3_CR RW ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 RW RW RW RW RW RW RW RW GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU HYSCTLR0CR HYSCTLR1CR HYSCTLR2CR HYSCTLR3CR MUX_CR0 MUX_CR1 MUX_CR2 SREG_TST OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW R DBB00FN DBB00IN DBB00OU DBB01FN DBB01IN DBB01OU DCB02FN DCB02IN DCB02OU DCB03FN DCB03IN DCB03OU DBB10FN DBB10IN DBB10OU DBB11FN DBB01IN DBB01OU DCB12FN DCB12IN DCB12OU DCB13FN DCB13IN DCB13OU RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN AMD_CR1 ALT_CR0 ALT_CR1 CLK_CR2 RW RW RW RW RW RW RW RW RW DEC_CR2 IMO_TR ILO_TR BDG_TR RW RW RW RW TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 GDRV0_CR GDRV1_CR GDRV2_CR GDRV3_CR RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RW RW RW RW RW RW RW RW CPU_F RW RW RW RW RW RW RW RL DAC_CR CPU_SCR1 CPU_SCR0 RW # # Document Number: 001-46319 Rev. *N Page 28 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 14. Electrical Specifications This section presents the DC and AC electrical specifications of the CY8CLED04D0X, CY8CLED04G01, CY8CLED03D0X, CY8CLED03G01, CY8CLED02D01, and CY8CLED01D01 of the PowerPSoC device family. For the most up to date electrical specifications, confirm that you have the most recent datasheet by going to the web at http://www.cypress.com/powerpsoc. Specifications for Industrial rated devices are valid for –40 °C  TA  85 °C, TJ  115 °C and for Extended Temperature rated devices for –40 °C  TA  105 °C, TJ  125 °C, except where noted. 14.1 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. Not all user guidelines are production tested. Table 14-1. Absolute Maximum Ratings Symbol TSTG Description Storage temperature Min –55 Typ – Max +115 Units °C Notes Higher storage temperatures reduces data retention time. Recommended storage temperature is 0 °C to 50 °C. TJ 115 °C (Industrial rated) TJ 125 °C (Extended Temperature rated) Relative to VSS, AVSS, and GDVSS respectively Applies only to GPIO and FN0 pins PGNDx is connected to GDVSS TA VDD, AVDD, GDVDD VIO VIO2 VFET VREGIN VCSP,VCSN VSENSE IMAIO IMIO LU ESD SRREGIN Ambient temperature with power applied –40 -40 –0.5 – – – +85 +105 +6.0 °C °C V Supply voltage on VDD, AVDD, and GDVDD DC input voltage VSS – 0.5 – – – – – – – – – – – – – VDD + 0.5 VDD + 0.5 36[13] 36[13] 36[13] 1.0 +50 +50 – – 32 3.2 15 V V V V V V mA mA mA V V/s V/s V/ms DC voltage applied to tristate VSS – 0.5 Maximum voltage from power Switch – (SWx) to Power FET Ground (PGNDx) Maximum voltage on SREGHVIN Pin – relative to VSS Maximum voltage applied to CSA pins –0.5 relative to VSS Maximum input differential voltage across –1.0 CSA input Maximum current into any port pin –50 configured as analog driver Maximum current into any port and –25 function pin Latch up current 200 Electrostatic Discharge Voltage 2000 Ramp Rate for the SREGHVIN pin – – – JESD78A Conformal Human Body Model ESD. SRCSP Ramp Rate for the CSPx pins SRHVDD-FLB High Voltage Supply Ramp Rate for Floating Load Buck Configuration SRVDD-EXT External VDD Supply Ramp Rate (VDD, AVDD, and GDVDD pins) – – 0.2 V/s For other topologies, to enable operation with faster ramp rates, or if the LED string voltage is < 6.5 V, see the PowerPSoC Technical Reference Manual. Applies only when powered by a source other than the Built-in Switching Regulator Note 13. Stresses beyond the “Absolute Maximum Ratings” on page 29 may cause permanent damage to the device. You must ensure that the Absolute Maximum Ratings are NEVER exceeded. Functional operation is not implied under any conditions beyond the “Electrical Characteristics” on page 30 onwards. Extended exposure to “Absolute Maximum Ratings” on page 29 may affect reliability of the device. Document Number: 001-46319 Rev. *N Page 29 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 14.2 Operating Temperature Symbol TA Description Ambient Temperature Min –40 –40 –40 –40 Typ – – – – Max +85 +105 +115 +125 Units °C °C °C °C Notes TJ 115 °C (Industrial rated) TJ 125 °C (Extended Temperature rated) Industrial rated Extended Temperature rated TJ Junction Temperature 15. Electrical Characteristics 15.1 System Level The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V, TJ  115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ  125 °C for Extended Temperature rated devices. Typical parameters apply to 5 V at 25 °C. These are for design guidance only. Table 15-1. System Level Operating Specifications Symbol fSW tD,MAX Description Circuit switching frequency range for hysteretic control loop Maximum Delay Time from CSA input to FET state change Min 0.02 – – D E Output duty cycle for hysteretic controllers Power converter efficiency 5 90 Typ – – – – 95 Max 2 100 115 95 – Units MHz ns ns % % Notes HVDD = 24 V, ID = 1 A, fSW = 2 MHz (Industrial rated) HVDD = 24 V, ID = 1 A, fSW = 2 MHz (Extended Temperature rated) fSW < 0.25 MHz HVDD = 24 V, ID = 1 A, fSW = 2 MHz 15.2 Chip Level The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V, TJ  115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ  125 °C for Extended Temperature rated devices. Typical parameters apply to 5 V at 25 °C. These are for design guidance only. Note See the PowerPSoC Technical Reference Manual for more information on the DPWMxPCF register Table 15-2. Chip Level DC Specifications Symbol VDD, AVDD, GDVDD HVDD HVPINS IVDD Description Digital, analog, and gate driver supply voltage range Power converter high voltage supply range Voltage range for the CSPx and SREGHVIN pins Supply current (VDD pins), IMO = 24 MHz Min 4.75 7 7 – Typ – – – 16 Max 5.25 32 32 50 Units Notes V All should be powered from the same source. V V Not all pins need to be at the same voltage level. mA Conditions are VDD = 5 V, TJ = 25 °C, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz, analog power = off. mA Conditions are VDD = 5 V, TJ = 25 °C, IAVDD Supply current (AVDD pin) – – 25 Document Number: 001-46319 Rev. *N Page 30 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 Table 15-2. Chip Level DC Specifications Symbol IGDVDD ISB Description Supply current per channel (GDVDD pins) Sleep (mode) current with POR, LVD, sleep timer, and WDT. Min – – – Typ – – 18 Max 25 100 25 Units Notes mA Internal Power FET at 2 MHz mA External Gate Driver at 1 MHz, CL = 4 nF at VDD = 5 V A TJ  25 °C, Built-in Switching Regulator disabled, DPWMxPCF = 0, Power Peripherals disabled, analog power = off A TJ  115 °C (Industrial rated) and TJ  125 °C (Extended Temperature rated), Built-in Switching Regulator disabled, DPWMxPCF = 0, Power Peripherals disabled, analog power = OFF – 30 550 Table 15-3. Chip Level AC Specifications Symbol fIMO24 fCPU1 fBLK f32K1 f32K_U Description Internal main oscillator frequency for 24 MHz CPU frequency Digital PSoC Block frequency Internal low-speed oscillator frequency Internal low speed oscillator (ILO) untrimmed frequency Min 23.04 0.093 0 15 5 Typ 24 24 48 32 – Max 24.96 24.96 49.92[14 ] Units MHz MHz Notes MHz Refer to “PSoC Core Digital Block Specifications” on page 48. kHz kHz After a reset and before the M8C starts to run, the ILO is not trimmed. See the System Resets section of the PowerPSoC Technical Reference Manual for details on timing this. 64 – DCILO Jitter32K Jitter24M1 tPOWERUP Internal low speed oscillator duty cycle 32 kHz period jitter 24 MHz period jitter (IMO) peak-to-peak Time from end of POR to CPU executing code 20 – – – 50 100 600 30 80 – – 100 % ns ps ms Power up from 0 V. See the System Resets section of the PowerPSoC Technical Reference Manual. Figure 15-1. 24 MHz Period Jitter (IMO) Timing Diagram Note 14. See the individual user module datasheets for information on maximum frequencies for user modules. Document Number: 001-46319 Rev. *N Page 31 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 15.3 Power Peripheral Low Side N-Channel FET The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V, TJ  115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ  125 °C for Extended Temperature rated devices. Typical parameters apply to 5 V at 25 °C. These are for design guidance only. Table 15-4. Low Side N-Channel FET DC Specifications Symbol VDS VDS,INST ID IDMAX Description Operating drain to source voltage Instantaneous drain source voltage Average drain current Maximum instantaneous repetitive pulsed current Min – – – – – – Typ – – – – – – Max 32 36 1 0.5 3 1.5 Units V V A A A A CY8CLED04/3/2/1D01 devices CY8CLED04/3D02 devices Less than 33% duty cycle for an average current of 1 A, fSW = 0.1 MHz. CY8CLED04/3/2/1D01 devices Less than 33% duty cycle for an average current of 0.5 A, fSW = 0.1 MHz. CY8CLED04/3D02 devices ID = 1 A, GDVDD = 5 V, TJ = 25 °C CY8CLED04/3/2/1D01 devices ID = 0.5 A, GDVDD = 5 V, TJ = 25 °C CY8CLED04/3D02 devices TJ = 25 °C TJ  115 °C (Industrial rated) and TJ  125 °C (Extended Temperature rated) fSW = 2 MHz Notes RDS(ON) Drain to source ON resistance – – – – – – 0.5 1 10 250   A A IDSS Switching node to PGND leakage – – ISFET Supply current per channel - FET (internal gate driver) – – 6.25 mA Table 15-5. Low Side N-Channel FET AC Specifications Symbol tR tF Rise time Fall time Description Min – – Typ – – Max 20 20 Units ns ns Notes ID = 1 A, RD = 32  ID = 1 A, RD = 32  Figure 15-2. Low Side N-Channel FET Test Circuit for IDSS, tR, and tF RD ID RG V INPU T VG Document Number: 001-46319 Rev. *N Page 32 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 15.4 Power Peripheral External Power FET Driver The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V, TJ  115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ  125 °C for Extended Temperature rated devices. Typical parameters apply to 5 V at 25 °C. These are for design guidance only. Table 15-6. Power FET Driver DC Specifications Symbol VOHN VOLN ISFETDRV Description N-channel FET driver output voltage -drive high N-channel FET driver output voltage -drive low Supply current per channel - external FET driver Min VDD – 0.45 VDD – 0.10 – – – Typ – – – – – Max – – 0.45 0.1 25 Units V V V V mA IOH = 100 mA IOH = 10 mA IOL = 100 mA IOL = 10 mA CL = 4 nF FSW = 1 MHz Notes Table 15-7. Power FET Driver AC Specifications Symbol tR tF tP(LH) tP(HL) Rise time Fall time Propagation delay (low-to-high) Propagation delay (high-to-low)) Description Min – – – – Typ 45 45 – – Max 55 55 10 10 Units ns ns ns ns CL = 4 nF Notes 15.5 Power Peripheral Hysteretic Controller The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V, TJ  115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ  125 °C for Extended Temperature rated devices. Typical parameters apply to 5 V at 25 °C. These are for design guidance only. Table 15-8. Hysteretic Controller DC Specifications Symbol VIO Description Comparator input offset voltage Min – – – VICM VHYS Input common mode voltage range Hysteresis voltage 0 4.5 4.5 Typ – – – – – – Max 7.5 10 15 VDD 11 13 Units mV mV mV V mV mV 1.5 V  VICM  2.5 V (Industrial rated) 1.5 V  VICM  2.5 V (Extended Temperature rated) Includes two Power Peripheral Comparators and one Reference DAC, fSW = 2 MHz Notes 1 V VICM 3 V (Industrial rated) 1 V VICM 3 V (Extended Temperature rated) 0 V VICM VDD ISHYST Supply current - hysteretic controller – 2 – mA Table 15-9. Hysteretic Controller AC Specifications Symbol Description Min Typ Max Units Notes tON / tOFF Minimum ON/OFF timer Document Number: 001-46319 Rev. *N Page 33 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 Table 15-9. Hysteretic Controller AC Specifications Symbol Description MONOSHOT = 00 MONOSHOT = 01 MONOSHOT = 10 MONOSHOT = 11 Min 10 20 40 – Typ – – – – Max 30 60 110 – Units ns ns ns ns Timers Disabled Notes 15.6 Power Peripheral Comparator The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V, TJ  115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ  125 °C for Extended Temperature rated devices. Typical parameters apply to 5 V at 25 °C. These are for design guidance only. Table 15-10. Comparator DC Specifications Symbol VIN VIO Description Input voltage range Comparator input offset voltage Min 0 – – – VHYS Hysteresis voltage 2.5 4.5 4.5 VOVDRV ISCOMP Overdrive voltage Supply current - comparator 5 – 0 Typ – – – – – – – – – – Max VDD 7.5 10 15 30 11 13 – 650 VDD Units V mV mV mV mV mV mV mV A V 1 V VICM 3 V (Industrial rated) 1 V VICM 3 V (Extended Temperature rated) 0 V VICM VDD 0 V < VICM < VDD 1.5 V  VICM  2.5 V (Industrial rated) 1.5 V  VICM  2.5 V (Extended Temperature rated) Notes VICM,COMP Comparator input common mode voltage range Table 15-11. Comparator AC Specifications Symbol tD Description Comparator delay time (FN0[x] pin to FN0[x] pin) Min – Typ 150 Max – Units ns Notes VOVDRV = 5 mV, CL = 10 pF at VDD =5V Document Number: 001-46319 Rev. *N Page 34 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 Figure 15-3. Comparator Timing Diagram Document Number: 001-46319 Rev. *N Page 35 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 15.7 Power Peripheral Current Sense Amplifier The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V, TJ  115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ  125 °C for Extended Temperature rated devices. Typical parameters apply to VDD of 5 V and HVDD of 32 V at 25 °C. These are for design guidance only. Table 15-12. Current Sense Amplifier DC Specifications Symbol VICM Description Input common mode voltage operating range Min 7 0 Typ – – Max 32 32 Units V Notes Either terminal of the amplifier must not exceed this range for functionality Absolute maximum rating for VSENSE should never be exceeded. See Absolute Maximum Ratings on page 29 mV mA A A dB V/V V/V mV pF pF fSW < 2 MHz VSENSE = 50 mV to 130 mV (Industrial rated) VSENSE = 50 mV to 130 mV (Extended Temperature rated) VSENSE = 50 mV to 130 mV Enabling CSA causes an incremental draw of 1 mA on the AVDD rail. VICM(Tolerant) Non functional operating range VSENSE IS,CSA IBIASP IBIASN PSRHV K Input differential voltage range Supply current - CSA Input bias current (+) Input bias current (-) Power supply rejection (CSP pin) Gain 0 – – – – 19.7 19.4 – – – – – 20 20 2 – – 150 1 600 1 –25 20.3 20.6 4 5 2 VIOS CIN_CSP CIN_CSN Input offset CSP input capacitance CSN input capacitance – – – Table 15-13. Current Sense Amplifier AC Specifications Symbol tSETTLE tPOWERUP Description Output settling time to 1% of final value Power up time to 1% of final value Min – – Typ – – Max 5 5 Units s s Notes Figure 15-4. Current Sense Amplifier Timing Diagram VINPUT VINPUT -50 mV VINPUT -150 mV V CSN t SETTLE t SETTLE tDELAY t ACTIVATE VCSP VCSP ,V CSN tPOWERUP OUT K*25 mV 0V Not Valid K*100 mV time Document Number: 001-46319 Rev. *N Page 36 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 15.8 Power Peripheral PWM/PrISM/DMM Specification Table The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V, TJ  115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ  125 °C for Extended Temperature rated devices. Typical parameters apply to 5 V at 25 °C. These are for design guidance only. See the PowerPSoC Technical Reference Manual for more information on PWM/PrISM/DMM. Table 15-14. PWM/PrISM/DMM DC Specifications Symbol IS,Modulation Description Supply current - PWM, PrISM, or DMM Min – Typ – Max 5 Units mA Notes Table 15-15. PWM/PrISM/DMM AC Specifications Symbol PWM Mode fRANGE16 fRANGE8 PrISM Mode fRANGE DMM Mode fRANGE,Dimming DMM dimming frequency range 24,000,000/ (256*Max DMM Period) – 48,000,000/(Mi n DMM Period) Hz Min DMM Period: 2 (Right Aligned), 3 (Center Aligned), 4(Left Aligned) Max DMM Period: 212 (Right Aligned), 8190 (Center Aligned), 212 (Left Aligned) PrISM output frequency range 24,000,000/(256*(2M–1) – 48,000,000/2 Hz Min: N = 255, Maqx: N = 0, M = 2 to 16 PWM output frequency range 16-bit period PWM output frequency range 8-bit period 24,000,000/(256*216) 24,000,000/(256*28) – – 48,000,000/216 48,000,000/28 Hz Hz Period Value = 216 –1, Min: N = 255, Max: N = 0 Period Value = 28 –1, Min: N = 255, Max: N = 0 Description Min Typ Max Units Notes fRANGE,Dither DMM dither frequency range (1/16)*(Min fRANGE,Dimming) – (15/16)*(Max fRANGE,Dimming) Hz Document Number: 001-46319 Rev. *N Page 37 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 15.9 Power Peripheral Reference DAC Specification The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V, TJ  115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ  125 °C for Extended Temperature rated devices. Typical parameters apply to 5 V at 25 °C. These are for design guidance only. Table 15-16. Reference DAC DC Specifications Symbol ISDAC INL DNL AERROR OSERROR VDACFS VDACMM Description Supply current - reference DAC Integral non linearity Differential non linearity Gain error Offset error Fullscale voltage - reference DAC Fullscale voltage mismatch (pair of reference DACs - even and odd) Min – –1 –1.5 –0.5 –5 –7 – – – – – – – Typ – – – – – – – – – – – – – Max 600 1 1.5 0.5 5 7 1 2.6 1.3 9 14 10.5 15.5 Units A LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB LSB Mode 0 Mode 1 Mode 0 and Mode1 Mode 0 Mode 1 Mode 0 and Mode1 Mode 0 Mode 1 Mode 0 (DAC0 through DAC7) Mode 1 (DAC0 through DAC7) Mode 0 (DAC8 through DAC13) Mode 1 (DAC8 through DAC13) Notes Mode 0 and Mode1 Table 15-17. Reference DAC AC Specifications Symbol tSETTLE tSTARTUP Description Output settling time to 0.5 LSB of final value Startup time to within 0.5 LSB of final value Min – – Typ – – Max 10 10.5 Units s s Notes Mode 0 and Mode1 Mode 0 and Mode1 15.10 Power Peripheral Built-in Switching Regulator The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V, TJ  115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ  125 °C for Extended Temperature rated devices. Typical parameters apply to 5 V at 25 °C. These are for design guidance only. Table 15-18. Built-in Switching Regulator DC Specifications Symbol VREGIN Description Input supply voltage range Min 7 8 Typ – – Max 32 32 Units V V Notes Industrial rated Extended Temperature rated See Absolute Maximum Ratings on page 29 Does not include VRIPPLE VREGIN < VUVLO: Power down mode VREGIN > VUVLO: Active mode VREGOUT VRIPPLE VUVLO ILOAD IS,BSR ISB,HV IINRUSH Output voltage range Output ripple Under voltage lockout voltage DC output current -active mode Supply current - built-in switching regulator Standby current (high voltage) Inrush current 4.8 – 5.5 0.01 – – – – 5.0 – – – – – – – 2.5 1 5.2 100 6.5 250 4 250 1.2 1.5 – – V mV V mA mA A A A  mV VREGIN = 32 V, SRREGIN = 32 V/ms (Industrial rated) VREGIN = 32 V, SRREGIN = 32 V/ms (Extended Temperature rated) ILOAD = 250 mA, VREGIN = 7 V to 32 V Page 38 of 55 RDS(ON),PFET PFET drain to source ON resistance LineREG Line regulation – – Document Number: 001-46319 Rev. *N [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 Table 15-18. Built-in Switching Regulator DC Specifications LoadREG PSRR EBSR Load regulation Power supply rejection ratio Built-in switching regulator efficiency – – 80 1 –60 – – – – mV dB % VREGIN = 24 V, ILOAD = 2.5 mA to 250 mA VRIPPLE = 0.2 * VREGIN, fRIPPLE = 1 kHz to 10 kHz VREGIN = 24 V, ILOAD = 250 mA Table 15-19. Built-in Switching Regulator AC Specifications Symbol fSW tRESP tSU tPD tPD_ACT tACT_PD SRREGIN Description Switching frequency Response time to within 0.5% of final value Startup time Power down time Time from power down to active mode Time from active mode to power down mode Ramp rate for the SREGHVIN pin Min 0.956 – – – – – – Typ 1 10 – – – – – Max 1.04 – 1 100 1 50 32 Units MHz s ms s ms s V/s Notes See Absolute Maximum Ratings on page 29 Table 15-20. Built-in Switching Regulator Recommended Components Component Name Rfb1 Rfb2 Ccomp Rcomp L Rsense C1 Cin Value 2 0.698 2200 20 47 0.5 10 1 Unit k k pF k H  F F Notes Tolerance 1% or better Tolerance 1% or better Tolerance 20% or better Tolerance 5% or better Tolerance 20% or better, Saturation current rating of 1.5 A or higher Tolerance 1% or better Ceramic, X7R grade, Minimum ESR of 0.1 Ceramic, X7R grade Note If the built-in switching regulator is not being used in a design, it must be configured as per the following instructions to ensure it is disabled in a safe state. SREGFB: 5 V SREGCSN: 5 V SREGCSP: 5 V SREGCOMP: Floating SREGHVIN:  VDD rail SREGSW: Floating/Tie to SREGHVIN If the switching regulator is disabled through wiring its input pins (as previously explained) then it must be disabled through software as well (bit SREG_TST[0] = 1), which is set in the Global Resources in the Interconnect View of PSoC Designer. Document Number: 001-46319 Rev. *N Page 39 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 Figure 15-5. Built-in Switching Regulator Timing Diagram VREGIN VREGIN 5 tSU VREGOUT tPD Powerdown MODE tPD_ACT Time Figure 15-6. Built-in Switching Regulator VSS Error Amplifier Osc SREGHVIN VREGIN C IN Ref Logic and Gate Drive Comparator SREGSW L D1 SREGCSP SREGCSN Rfb2 SREGCOMP Ccomp SREGFB Rcomp Rsense Rfb1 VREGOUT = 5V Current Sense Amp ESR C1 Document Number: 001-46319 Rev. *N Page 40 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 15.11 General Purpose I/O / Function Pin I/O The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V, TJ  115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ  125 °C for Extended Temperature rated devices. Typical parameters apply to 5 V at 25 °C. These are for design guidance only. Table 15-21. GPIO/FN0 Pin I/O DC Specifications Symbol RPU RPD VOH VOL IOH Description Pull-up resistor Pull-down resistor High output level Low output level High level source current Min 4 4 VDD – 1.0 – 10 Typ 5.6 5.6 – – – Max 8 8 – 0.75 – Units k k V V mA Notes IOL VIL VIH VH IIL CIN COUT Low level sink current Input low level Input high level Input hysterisis Input leakage (absolute value) Capacitive load on pins as input Capacitive load on pins as output 25 – 2.1 – – – – – – – 60 1 3.5 3.5 – 0.8 – – 10 10 mA V V mV nA pF pF IOH = 10 mA, 80 mA maximum combined IOH budget IOL = 25 mA, 200 mA maximum combined IOL budget VOH = VDD–1.0 V, see the limitations of the total current in the note for VOH VOL = 0.75 V, see the limitations of the total current in the note for VOL Gross tested to 1 A TJ = 25 °C. TJ = 25 °C. Table 15-22. GPIO/FN0 Pin I/O AC Specifications Symbol fGPIO tRiseF tFallF tRiseS tFallS Description GPIO operating frequency Rise time, normal strong mode, Cload = 50 pF Fall time, normal strong mode, Cload = 50 pF Rise time, slow strong mode, Cload = 50 pF Fall time, slow strong mode, Cload = 50 pF Min 0 3 2 10 10 Typ – – – 27 22 Max 12 18 18 – – Units MHz ns ns ns ns 10% – 90% Notes Normal strong mode Figure 15-7. GPIO/Function I/O Timing Diagram Document Number: 001-46319 Rev. *N Page 41 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 15.12 PSoC Core Operational Amplifier Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V, TJ  115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ  125 °C for Extended Temperature rated devices. Typical parameters apply to 5 V at 25 °C. These are for design guidance only. The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Table 15-23. Operational Amplifier DC Specifications Symbol VOSOA Description Input offset voltage (absolute value) Power = low, opamp bias = high Power = medium, opamp bias = high Power = high, opamp bias = high Min – – – – – – Typ 1.6 1.6 1.3 1.3 1.2 1.2 Max 10 15 8 13 7.5 12 Units mV mV mV mV mV mV Notes Industrial rated Extended Temperature rated Industrial rated Extended Temperature rated Industrial rated Extended Temperature rated TCVOSOA Average input offset voltage drift IEBOA CINOA VCMOA Input leakage current (Port 0 analog pins) Input capacitance (Port 0 analog pins) Common mode voltage range Common mode voltage range (high power or high opamp bias) – – – 0.0 0.5 7.0 20 4.5 – – 35.0 – 9.5 VDD VDD – 0.5 V / °C pA pF V V Gross tested to 1 A. TJ = 25 °C. The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. GOLOA Open loop gain Power = low, opamp bias = high Power = medium, opamp bias = high Power = high, opamp bias = high 60 60 80 VDD – 0.2 VDD – 0.2 VDD – 0.5 – – – – – – – – – – – – – – – – – – 0.2 0.2 0.5 dB dB dB V V V V V V VOHIGHOA High output voltage swing (internal signals) Power = low, opamp bias = high Power = medium, opamp bias = high Power = high, opamp bias = high VOLOWOA Low output voltage swing (internal signals) Power = low, opamp bias = high Power = medium, opamp bias = high Power = high, opamp bias = high ISOA Supply current (including associated analog output buffer) Power = low, opamp bias = low Power = low, opamp bias = high Power = medium, opamp bias = low Power = medium, opamp bias = high Power = high, opamp bias = low Power = high, opamp bias = high Supply voltage rejection ratio – – – – – – 52 400 500 800 1200 2400 4600 80 800 900 1000 1600 3200 6400 – A A A A A A dB VSS  VIN  (VDD – 2.25) or (VDD – 1.25 V)  VIN  VDD. PSRROA Document Number: 001-46319 Rev. *N Page 42 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 Table 15-24. Operational Amplifier AC Specifications Symbol Description tROA Rising settling time from 80% of V to 0.1% of V (10 pF load, Unity Gain) Power = low, opamp bias = low Power = medium, opamp bias = high Power = high, opamp bias = high tSOA Falling settling time from 20% of V to 0.1% of V (10 pF load, unity gain) Power = low, opamp bias = low Power = medium, opamp bias = high Power = high, opamp bias = high SRROA Rising slew rate (20% to 80%) (10 pF load, unity gain) Power = low, opamp bias = low Power = medium, opamp bias = high Power = high, opamp bias = high SRFOA Falling slew rate (20% to 80%) (10 pF load, unity gain) Power = low, opamp bias = low Power = medium, opamp bias = high Power = high, opamp bias = high Gain bandwidth product BWOA Power = low, opamp bias = low Power = medium, opamp bias = high Power = high, opamp bias = high ENOA Noise at 1 kHz (power = medium, opamp bias = high) Min Typ Max Units s s s s s s V/s V/s V/s V/s V/s V/s MHz MHz MHz nV/r-Hz Notes – – – – – – 3.9 0.72 0.62 – – – – – – 5.9 0.92 0.72 0.15 1.7 6.5 – – – – – – 0.01 0.5 4.0 0.75 3.1 5.4 – – – – – – – 100 – – – – – – – 15.13 PSoC Core Low Power Comparator The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V, TJ  115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ  125 °C for Extended Temperature rated devices. Typical parameters apply to 5 V at 25 °C. These are for design guidance only. Table 15-25. Low Power Comparator DC Specifications Symbol VREFLPC ISLPC VOSLPC Description Low power comparator (LPC) reference voltage range LPC supply current LPC voltage offset Min 0.2 – – Typ – 10 2.5 Max VDD – 1 40 40 Units V A mV Notes Table 15-26. Low Power Comparator AC Specifications Symbol tRLPC Description LPC response time Min – Typ – Max 50 Units s Notes  50 mV overdrive comparator reference set within VREFLPC. Document Number: 001-46319 Rev. *N Page 43 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 15.14 PSoC Core Analog Output Buffer The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V, TJ  115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ  125 °C for Extended Temperature rated devices. Typical parameters apply to 5 V at 25 °C. These are for design guidance only. Table 15-27. Analog Output Buffer DC Specifications Symbol VOSOB Description Input offset voltage (absolute value) Min – – – 0.5 – – 0.5 x VDD + 1.1 0.5 x VDD + 1.1 – – Typ 3 3 +6 – 0.6 0.6 – – Max 12 18 – VDD – 1.0 – – – – Units mV mV V/°C V   V V Notes Industrial rated Extended Temperature rated TCVOSOB Average input offset voltage drift VCMOB Common-mode input voltage range ROUTOB Output resistance Power = low Power = high VOHIGHOB High output voltage swing (load = 32 ohms to VDD/2) Power = low Power = high VOLOWOB Low output voltage swing (load = 32 ohms to VDD/2) Power = low Power = high ISOB Supply current including bias cell (no load) Power = low Power = high Supply voltage rejection ratio – – 0.5 x VDD – 1.3 0.5 x VDD – 1.3 5.1 8.8 – V V PSRROB – – 52 1.1 2.6 64 mA mA dB (0.5 x VDD – 1.3)  VOUT  (VDD – 2.3). Table 15-28. Analog Output Buffer AC Specifications Symbol tROB Description Rising settling time to 0.1%, 1 V Step, 100 pF load Power = low Power = high Falling settling time to 0.1%, 1 V Step, 100 pF load Power = low Power = high Min Typ Max Units Notes – – – – 2.5 2.5 s s tSOB – – – – 2.2 2.2 s s Document Number: 001-46319 Rev. *N Page 44 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 Table 15-28. Analog Output Buffer AC Specifications Symbol SRROB Description Rising slew rate (20% to 80%), 1 V step, 100 pF load Power = low Power = high Falling slew rate (80% to 20%), 1 V step, 100 pF load Power = low Power = high Small signal bandwidth, 20 mVpp, 3 dB BW, 100 pF load Power = low Power = high Large signal bandwidth, 1 Vpp, 3 dB BW, 100 pF load Power = low Power = high Min Typ Max Units Notes 0.65 0.65 – – – – V/s V/s SRFOB 0.65 0.65 – – – – V/s V/s BWOBSS 0.8 0.8 – – – – MHz MHz BWOBLS 300 300 – – – – kHz kHz Document Number: 001-46319 Rev. *N Page 45 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 15.15 PSoC Core Analog Reference The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V, TJ  115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ  125 °C for Extended Temperature rated devices. Typical parameters apply to 5 V at 25 °C. These are for design guidance only. The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high. Table 15-29. Analog Reference DC Specifications Symbol BG Description Bandgap voltage reference Min 1.28 1.27 Typ 1.30 1.30 Max 1.32 1.33 Units V V Notes Industrial rated Extended Temperature rated Industrial rated Extended Temperature rated – AGND = VDD/2[15] VDD/2 – 0.04 VDD/2 – 0.02 VDD/2 – 0.01 VDD/2 VDD/2 + 0.007 VDD/2 + 0.02 V V – – – – – – – – AGND = 2 x BandGap[15] AGND = BandGap[15] AGND = 1.6 x BandGap[15] AGND Block to Block Variation (AGND = VDD/2)[15] RefHi = VDD/2 + BandGap RefHi = 3 x BandGap RefHi = 3.2 x BandGap RefLo = VDD/2 – BandGap 2 x BG – 0.048 BG – 0.009 –0.034 VDD/2 + BG – 0.10 3 x BG – 0.06 3.2 x BG – 0.112 VDD/2 – BG – 0.04 VDD/2 – BG – 0.06 BG – 0.06 2 x BG – 0.030 BG + 0.008 0.000 VDD/2 + BG 3 x BG 3.2 x BG VDD/2 – BG + 0.024 VDD/2 – BG 2 x BG + 0.024 BG + 0.016 0.034 VDD/2 + BG + 0.10 3 x BG + 0.06 3.2 x BG + 0.076 VDD/2 – BG + 0.04 VDD/2 – BG + 0.06 BG + 0.06 V V V V V V V V V Industrial rated Extended Temperature rated 1.6 x BG – 0.022 1.6 x BG – 0.010 1.6 x BG + 0.018 – RefLo = BandGap BG V 15.16 PSoC Core Analog Block The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V, TJ  115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ  125 °C for Extended Temperature rated devices. Typical parameters apply to 5 V at 25 °C. These are for design guidance only. Table 15-30. Analog Block DC Specifications Symbol RCT CSC Description Resistor unit value (continuous time) Capacitor unit value (switched capacitor) Min – – Typ 12.2 80 Max – – Units k fF Notes Notes 15. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3 V ± 0.02 V. Document Number: 001-46319 Rev. *N Page 46 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 15.17 PSoC Core POR and LVD The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V, TJ  115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ  125 °C for Extended Temperature rated devices. Typical parameters apply to 5 V at 25 °C. These are for design guidance only. Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. See the PowerPSoC Technical Reference Manual for more information on the VLT_CR register. Table 15-31. POR and LVD DC Specifications Symbol VPPOR2 Description VDD Value for PPOR Trip PORLEV[1:0] = 10b VDD Value for LVD Trip VM[2:0] = 110b VM[2:0] = 111b Min – Typ 4.55 Max 4.70 Units V Notes VLVD6 VLVD7 4.62 4.71 4.73 4.81 4.83 4.95 V V 15.18 PSoC Core Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V, TJ  115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ  125 °C for Extended Temperature rated devices. Typical parameters apply to 5 V at 25 °C. These are for design guidance only. Table 15-32. Programming DC Specifications Symbol IDDP VILP VIHP IILP IIHP VOLV VOHV Description Supply current during programming or verify Input low voltage during programming or verify Input high voltage during programming or verify Input current when applying Vilp to P1[0] or P1[1] during programming or verify Input current when applying Vihp to P1[0] or P1[1] during programming or verify Output low voltage during programming or verify Output high voltage during programming or verify Min – – 2.1 – – – VDD – 1.0 50,000 1,800,000 10 Typ 15 – – – – – – – – – Max 30 0.8 – 0.2 1.5 VSS + 0.75 VDD – – – Units mA V V mA mA V V – – Years Erase/write cycles per block. Erase/write cycles. Driving internal pull down resistor. Driving internal pull down resistor. Notes FlashENPB Flash endurance (per block) FlashENT FlashDR Flash endurance (total)[16] Flash data retention [17] Notes 16. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36 x 1 blocks of 50,000 maximum cycles each, 36 x 2 blocks of 25,000 maximum cycles each, or 36 x 4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36 x 50,000 and that no single block ever sees more than 50,000 cycles) 17. Guaranteed for –40 °C  TA  85 °C for Industrial rated devices and –40 °C  TA  105 °C for Extended Temperature rated devices. Document Number: 001-46319 Rev. *N Page 47 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 Table 15-33. Programming AC Specifications Symbol tRSCLK tFSCLK tSSCLK tHSCLK fSCLK tERASEB tWRITE tDSCLK tERASEALL tPROGRAM_HOT tPROGRAM_COLD Description Rise time of SCLK Fall time of SCLK Data set up time to falling edge of SCLK Data hold time from falling edge of SCLK Frequency of SCLK Flash erase time (block) Flash block write time Data out delay from falling edge of SCLK Flash erase time (bulk) Min 1 1 40 40 0 – – – – Typ – – – – – 10 40 – 40 Max 20 20 – – 8 – – 50 – 100[18] 200[18] Units ns ns ns ns MHz ms ms ns ms Notes Flash block erase + flash block write time Flash block erase + flash block write time – – – – ms ms Erase all blocks and protection fields immediately 0 °C  Tj  100 °C –40 °C  Tj  0 °C 15.19 PSoC Core Digital Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V, TJ  115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ  125 °C for Extended Temperature rated devices. Typical parameters apply to 5 V at 25 °C. These are for design guidance only. Table 15-34. Digital Block AC Specifications Function Timer Description Capture pulse width Maximum frequency, no capture Maximum frequency, with capture Enable pulse width Maximum frequency, no enable input Maximum frequency, enable input Kill pulse width: Asynchronous restart mode Synchronous restart mode Disable mode Maximum Frequency Maximum input clock frequency Maximum input clock frequency Maximum input clock frequency Min 50[19] – – 50[19] – – 20 50[19] 50[19] – – – – Typ – – – – – – – – – – – – – Max – 49.92 24.96 – 49.92 24.96 – – – 49.92 49.92 24.96 8.32 Units ns MHz MHz ns MHz MHz ns ns ns MHz MHz MHz MHz Maximum data rate at 4.1 MHz due to 2 x over clocking. Notes Counter Dead Band CRCPRS (PRS Mode) CRCPRS (CRC Mode) SPIM SPIS Transmitter Maximum input clock frequency Width of SS_ Negated between transmissions Maximum input clock frequency Maximum input clock frequency with VDD  4.75 V, 2 stop bits – 50[19] – – – – – – 4.16 – 24.96 49.92 MHz ns MHz MHz Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. Notes 18. For the full industrial range, you must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. 19. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). Document Number: 001-46319 Rev. *N Page 48 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 Table 15-34. Digital Block AC Specifications Receiver Maximum input clock frequency Maximum input clock frequency with VDD  4.75 V, 2 stop bits – – – – 24.96 49.92 MHz MHz Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. 15.20 PSoC Core I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75 V to 5.25 V, TJ  115 °C for Industrial rated devices and 4.75 V to 5.25 V, TJ  125 °C for Extended Temperature rated devices. Typical parameters apply to 5 V at 25 °C. These are for design guidance only. Table 15-35. AC Characteristics of the I2C SDA and SCL Pins Symbol fSCLI2C tHDSTAI2C tLOWI2C tHIGHI2C tSUSTAI2C tHDDATI2C tSUDATI2C tSUSTOI2C tBUFI2C tSPI2C Description SCL clock frequency Hold time (repeated) START condition. After this period, the first clock pulse is generated. LOW period of the SCL clock HIGH period of the SCL clock Setup time for a repeated START condition Data hold time Data setup time Setup time for STOP condition Bus free time between a STOP and START condition Pulse width of spikes are suppressed by the input filter. Standard Mode Min 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 – Max 100 – – – – – – – – – Fast Mode Min 0 0.6 1.3 0.6 0.6 0 100[20] 0.6 1.3 0 Max 400 – – – – – – – – 50 Units kHz s s s s s ns s s ns Notes Figure 15-8. Definition of Timing for Fast/Standard Mode on the I2C Bus Note 20. A fast mode I2C bus device can be used in a standard mode I2C bus system, but the requirement tSUDATI2  250 ns must then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSUDATI2 = 1000 + 250 = 1250 ns (according to the standard mode I2C bus specification) before the SCL line is released. Document Number: 001-46319 Rev. *N Page 49 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 16. Ordering Information Table 16-1. Device Key Features and Ordering Information Internal FETs 4 X 1.0 A 4 X 0.5 A 0 4 X 1.0 A 3 X 1.0 A 3 X 0.5 A 0 2 X 1.0 A 1 X 1.0 A 1 X 1.0 A Gate Drivers for External Low Side N-FETs 4 4 4 4 3 3 3 2 1 1 PowerPSoC Part Number CY8CLED04D01-56LTXI CY8CLED04D02-56LTXI CY8CLED04G01-56LTXI CY8CLED04DOCD1-56LTXI CY8CLED03D01-56LTXI CY8CLED03D02-56LTXI CY8CLED03G01-56LTXI CY8CLED02D01-56LTXI CY8CLED01D01-56LTXI CY8CLED01D01-56LTXQ No. of Pins 56 QFN 56 QFN 56 QFN 56 QFN 56 QFN 56 QFN 56 QFN 56 QFN 56 QFN 56 QFN Package 8 mm X 8 mm 8 mm X 8 mm 8 mm X 8 mm 8 mm X 8 mm 8 mm X 8 mm 8 mm X 8 mm 8 mm X 8 mm 8 mm X 8 mm 8 mm X 8 mm 8 mm X 8 mm Channels 4 4 4 4 3 3 3 2 1 1 Voltage 32 V 32 V 32 V 32 V 32 V 32 V 32 V 32 V 32 V 32 V 16.1 Ordering Code Definitions CY 8 C LED0x xxx (xxxx) - xx xxxx Package Type: LTX=QFN Pb-free Thermal Rating: I = Industrial Q = Extended Temperature Pin Count OCD1 = On Chip Debugger Part Number: D01 = Internal 1.0 A FETs, D02 = Internal 0.5 A FETs, G01 = No Internal FETs Family Code: 4 = 4 Channel, 3 = 3 Channel, 2 = 2 Channel, 1 = 1 Channel Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress Document Number: 001-46319 Rev. *N Page 50 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 17. Packaging Information Packaging Dimensions This section illustrates the package specification for the CY8CLED04D0X, CY8CLED04G01, CY8CLED03D0X, CY8CLED03G01, CY8CLED02D01, and CY8CLED01D01 along with the thermal impedance for the package and solder reflow peak temperatures. Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. Figure 17-1. 56-Pin (8x8 mm) QFN 51-85187 *E 17.1 Thermal Impedance Package 56 QFN[22] Typical JA [21] 16.6 °C/W 17.2 Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Package 56 QFN Minimum Peak Temperature[23] 240 °C Maximum Peak Temperature 260 °C Notes 21. TJ = TA + POWER x JA 22. To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane. 23. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5 °C with Sn-Pb or 245 ± 5 °C with Sn-Ag-Cu paste Refer to the solder manufacturer specifications. Document Number: 001-46319 Rev. *N Page 51 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 18. Acronyms Acronym AC ADC API CPU CSA CT DAC DALI DC DMM DMX DSM DTMF ECO EEPROM EMI FAQ FET FSR GPIO GUI HBM IC ICE IDE ILO IMO ISSP I/O IPOR LED LSB LVD MCU MOSFET MSB OCD PC POR PPOR PowerPSoC Description alternating current analog-to-digital converter application programming interface central processing unit current sense amplifier continuous time digital-to-analog converter digital addressable lighting interface direct current delta sigma modulation mode digital multiplexing delta sigma modulator dual-tone multi frequency external crystal oscillator electrically erasable programmable read-only memory electromagnetic interference frequently asked questions field effect transistor full scale range general purpose i/o graphical user interface human body model integrated circuit in-circuit emulator integrated development environment internal low-speed oscillator internal main oscillator in-system serial programming input/output imprecise power on reset light emitting diode least-significant bit low voltage detect microcontroller metal-oxide-semiconductor field effect transistor most-significant bit on chip debugger program counter power on reset precision power on reset power programmable system-on-chip™ Acronym PrISM PSoC PWM QFN RGBA RGGB SAR SC SCL SCLK SDA SDATA SPI SRAM TRM UART USB WDT Description precise intensity signal modulation programmable system-on-chip™ pulse width modulator quad flat no leads package red, green, blue, amber red, green, green, blue successive approximation register switched capacitor serial I2C serial issp clock serial i2c data serial issp data serial peripheral interface static random access memory technical reference manual universal asynchronous receiver/transmitter universal serial bus watch dog timer 19. Document Conventions 19.1 Units of Measure Symbol °C dB Hz pp  V  KB ppm sps W A Kbit KHz K MHz M A F H s V Vrms Unit of Measure degrees Celsius decibels Hertz peak-to-peak sigma:one standard deviation volts ohms 1024 bytes parts per million samples per second watts amperes 1024 bits kilohertz kilohms megahertz megaohms microamperes microfarads microhenrys microseconds microvolts microvolts root-mean-square Page 52 of 55 Document Number: 001-46319 Rev. *N [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 Symbol W mA ms mV mW nA ns nV pA pF ps fF Unit of Measure microwatts milliampere millisecond millivolts milliwatts nanoamperes nanoseconds nanovolts picoamperes picofarads picoseconds femtofarads Document Number: 001-46319 Rev. *N Page 53 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 20. Document History Page Document Title: CY8CLED04D01, CY8CLED04D02, CY8CLED04G01, CY8CLED03D01, CY8CLED03D02, CY8CLED03G01, CY8CLED02D01, CY8CLED01D01 PowerPSoC® Intelligent LED Driver Document Number: 001-46319 Revision ECN No. ** *A 2506500 2575708 Orig. of Change ANWA/ DSG ANWA/ AESA Submission Date 05/20/08 10/01/08 New datasheet. 1) Updated Logic Block Diagram with AINX label and SREGFB pin. 2) Updated Current Sense Amplifier Specification Table. 3) Updated External Gate Driver Specification Table. 4) Updated Register Table. Extensive changes made to content and electrical specifications. Updated Notes in electrical specifications. Updated sections 8, 9, and 10 on pages 14, 15, and 16. Release to the external web site. Updated Figure 15-2., and Figure 15-4.. Added 1 and 2 channel part information. Updated electrical specifications. Added Table of Contents Updated Absolute Maximum Ratings, DC GPIO, AC Chip-Level, and AC Programming Specifications as follows: Added VREGINMAX absolute maximum specification. Modified tWRITE specification. Added IOH, IOL, DCILO, f32K_U, tPOWERUP, tERASEALL, tPROGRAM_HOT, and tPROGRAM_COLD specifications Updated package diagram Datasheet reviewed and updated with a view to improve clarity, readability and customer-friendliness. This includes language, consistency in terminology to match software and other PowerPSoC documentation, changes to reflect major changes in software such as removal of system level design addition of links to relevant collateral such as kits, technical reference manuals and application notes. Removed DALI in Page 1 and Page 13, and added the DALI note in Page 13. Added a note to Section 15.10 after Table 15-20 on page 38. Updated as per the new Cypress Style and datasheet template. Updated datasheet to add Extended Temperature rated device CY8CLED01D01-56LTXQ Updated certain specifications for Extended Temperature rated device Updated description for Symbol VREGIN and VCSP,VCSN in Table 14-1. Updated Figure 15-6. Description of Change *B *C *D *E *F *G *H *I 2662774 KJV 02/19/09 02/25/09 03/10/09 04/03/09 04/27/09 07/10/09 09/17/09 02/01/10 2665155 KJV/PYRS 2671254 KJV/PYRS 2683506 2735072 2765369 VED KJV KJV 2698529 KJV/PYRS 2870389 FRE/PYRS *J 2952677 FRE/UKK 06/15/10 *K 3031567 FRE/UKK 09/16/10 *L *M *N 3073506 3178540 3244595 KJV KJV KJV 11/08/2010 02/28/2011 05/04/2011 Document Number: 001-46319 Rev. *N Page 54 of 55 [+] Feedback CY8CLED04D01, CY8CLED04D02, CY8CLED04G01 CY8CLED03D01, CY8CLED03D02, CY8CLED03G01 CY8CLED02D01, CY8CLED01D01 21. Sales, Solutions, and Legal Information 21.1 Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2008-2011. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-46319 Rev. *N Revised May 4, 2011 Page 55 of 55 PSoC Designer™, Programmable System-on-Chip™, and PrISM™ are trademarks and PSoC® and, PowerPSoC® are registered trademarks of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. [+] Feedback