CY8CLED08-48LFXI

CY8CLED08 EZ-Color™ HB LED Controller Features ■ HB LED Controller ❐ Configurable Dimmers Support up to 8 Independent LED Channels ❐ 8-32 Bits of Resolution per Channel ❐ Dynamic Reconfiguration Enables LED ❐ Controller plus other Features; Battery ❐ Charging, Motor Control Visual Embedded Design, PSoC Express ❐ LED Based Express Drivers • Binning Compensation • Temperature Feedback • DMX512 PrISM Modulation Technology ❐ Reduces Radiated EMI ❐ Reduces Low Frequency Blinking Powerful Harvard Architecture Processor ❐ M8C Processor Speeds to 24 MHz ❐ 3.0 to 5.25V Operating Voltage ❐ Operating Voltages down to 1.0V using On-Chip Switch Mode Pump (SMP) ❐ Industrial Temperature Range: -40°C to +85°C Flexible On-Chip Memory ❐ 16K Flash Program Storage 50,000 Erase/Write Cycles ❐ 256 Bytes SRAM Data Storage ❐ In-System Serial Programming (ISSP) ❐ Partial Flash Updates ❐ Flexible Protection Modes ❐ EEPROM Emulation in Flash ■ ■ Advanced Peripherals (PSoC Blocks) ❐ 8 Digital PSoC Blocks Provide: • 8 to 32-Bit Timers, Counters, and PWMs • Up to 2 Full-Duplex UART • Multiple SPI™ Masters or Slaves • Connectable to all GPIO Pins ❐ 12 Rail-to-Rail Analog PSoC Blocks Provide: • Up to 14-Bit ADCs • Up to 9-Bit DACs • Programmable Gain Amplifiers • Programmable Filters and Comparators ❐ Complex Peripherals by Combining Blocks Flexible On-Chip Memory ❐ 16K Flash Program Storage 50,000 Erase/Write Cycles ❐ 256 Bytes SRAM Data Storage ❐ In-System Serial Programming (ISSP) ❐ Partial Flash Updates ❐ Flexible Protection Modes ❐ EEPROM Emulation in Flash Programmable Pin Configurations ❐ 25 mA Sink on all GPIO ❐ Pull up, Pull down, High Z, Strong, or Open Drain Drive Modes on all GPIO ❐ Up to 12 Analog Inputs on GPIO ❐ Four 30 mA Analog Outputs on GPIO ❐ Configurable Interrupt on all GPIO Complete Development Tools ❐ Free Development Software • PSoC Designer™ • PSoC Express™ ❐ Full featured, In-Circuit Emulator and Programmer ❐ Full Speed Emulation ❐ Complex Breakpoint Structure ❐ 128 KBytes Trace Memory ■ ■ ■ ■ ■ ■ Cypress Semiconductor Corporation Document Number: 001-12981 Rev. ** • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 12, 2007 CY8CLED08 Overview Block Diagram Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Analog Drivers PSoC CORE System Bus Global Digital Interconnect SRAM 256 Bytes Interrupt Controller Global Analog Interconnect Flash 16K Sleep and Watchdog SROM CPU Core (M8C) Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) DIGITAL SYSTEM Digital Block Array ANALOG SYSTEM Analog Ref. Analog Block Array Analog Input Muxing Digital Clocks Multiply Accum. POR and LVD Decimator I 2C System Resets Internal Voltage Ref. Switch Mode Pump SYSTEM RESOURCES Document Number: 001-12981 Rev. ** Page 2 of 37 CY8CLED08 EZ-Color Functional Overview Cypress' EZ-Color family of devices offers the ideal control solution for High Brightness LED applications requiring intelligent dimming control. EZ-Color devices combine the power and flexibility of PSoC (Programmable System-on-Chip™); with Cypress' PrISM (precise illumination signal modulation) modulation technology providing lighting designers a fully customizable and integrated lighting solution platform. The EZ-Color family supports up to 16 independent LED channels with up to 32 bits of resolution per channel, enabling lighting designers the flexibility to choose the LED array size and color quality. PSoC Express software, with lighting specific drivers, can significantly cut development time and simplify implementation of fixed color points through temperature and LED binning compensation. EZ-Color's virtually limitless analog and digital customization allow for simple integration of features in addition to intelligent lighting, such as Battery Charging, Image Stabilization, and Motor Control during the development process. These features, along with Cypress' best-in-class quality and design support, make EZ-Color the ideal choice for intelligent HB LED control applications. Resource), provide the flexibility to integrate almost any timing requirement into the EZ-Color device. EZ-Color GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. The Digital System The Digital System is composed of 8 digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Figure 1. Digital System Block Diagram Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Digital Clocks From Core To System Bus To Analog System Target Applications ■ ■ ■ ■ ■ ■ LCD Backlight Large Signs Row Input Configuration DIGITAL SYSTEM Digital PSoC Block Array Row 0 DBB00 DBB01 DCB02 4 DCB03 4 Row Output Configuration General Lighting Architectural Lighting Camera/Cell Phone Flash Flashlights 8 8 8 Row Input Configuration Row 1 DBB10 DBB11 DCB12 4 DCB13 4 8 Row Output Configuration The PSoC Core The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose IO). The M8C CPU core is a powerful processor with speeds up to 48 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with 17 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT). Memory encompasses 16K of Flash for program storage, 256 bytes of SRAM for data storage, and up to 2K of EEPROM emulated using the Flash. Program Flash utilizes four protection levels on blocks of 64 bytes, allowing customized software IP protection. The EZ-Color family incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to 2.5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Document Number: 001-12981 Rev. ** GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] Digital peripheral configurations include those listed below. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ PrISM (8 to 32 bit) PWMs (8 to 32 bit) PWMs with Dead band (8 to 32 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) UART 8 bit with selectable parity (up to 2) SPI slave and master (up to 2) I2C slave and multi-master (1 available as a System Resource) Cyclical Redundancy Checker/Generator (8 to 32 bit) IrDA (up to 2) Generators (8 to 32 bit) Page 3 of 37 CY8CLED08 The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by EZ-Color device family. This allows you the optimum choice of system resources for your application. Family resources are shown in the table titled EZ-Color Device Characteristics. Figure 2. Analog System Block Diagram P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6] P0[4] P0[2] P0[0] P2[6] P2[3] The Analog System The Analog System is composed of 12 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common EZ-Color analog functions (most available as user modules) are listed below. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ P2[1] P2[4] P2[2] P2[0] Analog-to-digital converters (up to 4, with 6- to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR) Filters (2, 4, 6, and 8 pole band-pass, low-pass, and notch) Amplifiers (up to 4, with selectable gain to 48x) Instrumentation amplifiers (up to 2, with selectable gain to 93x) Comparators (up to 4, with 16 selectable thresholds) DACs (up to 4, with 6- to 9-bit resolution) Multiplying DACs (up to 4, with 6- to 9-bit resolution) High current output drivers (four with 30 mA drive as a Core Resource) 1.3V reference (as a System Resource) DTMF Dialer Modulators Correlators Peak detectors Many other topologies possible Interface to Digital System ACB00 ASC10 ASD20 ACI0[1:0] Array Input Configuration ACI1[1:0] ACI2[1:0] ACI3[1:0] Block Array ACB01 ASD11 ASC21 ACB02 ASC12 ASD22 ACB03 ASD13 ASC23 Analog Reference RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap Analog blocks are provided in columns of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks, as shown in the figure below. M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 001-12981 Rev. ** Page 4 of 37 CY8CLED08 Additional System Resources System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, switch mode pump, low voltage detection, and power on reset. Statements describing the merits of each system resource are below. ■ ■ The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3V reference provides an absolute reference for the analog system, including ADCs and DACs. An integrated switch mode pump (SMP) generates normal operating voltages from a single 1.2V battery cell, providing a low cost boost converter. ■ Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. Multiply accumulate (MAC) provides fast 8-bit multiplier with 32-bit accumulate, to assist in general math and digital filters. The decimator provides a custom hardware filter for digital signal processing applications including the creation of Delta Sigma ADCs. ■ ■ ■ ■ EZ-Color Device Characteristics Depending on your EZ-Color device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. The following table lists the resources available for specific EZ-Color device groups. The device covered by this data sheet is shown in the highlighted row of the table Table 1. EZ-Color Device Characteristics PSoC Part Number CY8CLED04 CY8CLED08 CY8CLED16 CapSense Yes No No LED Channels Analog Columns Analog Outputs Analog Inputs Analog Blocks Digital Blocks Digital IO Digital Rows SRAM Size Flash Size 16K 16K 32K 4 8 16 56 44 64 1 2 4 4 8 16 48 12 12 2 4 4 2 4 4 6 12 12 1K 256 Bytes 2K Document Number: 001-12981 Rev. ** Page 5 of 37 CY8CLED08 Getting Started The quickest path to understanding the EZ-Color silicon is by reading this data sheet and using the PSoC Express Integrated Development Environment (IDE). This data sheet is an overview of the EZ-Color integrated circuit and presents specific pin, register, and electrical specifications. For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest device data sheets on the web at http://www.cypress.com/ez-color. Development Tools PSoC Express is a high-level design tool for creating embedded systems with devices using Cypress's PSoC Mixed-Signal technology. With PSoC Express you create a complete embedded solution including all necessary on-chip peripherals, block configuration, interrupt handling and application software without writing a single line of assembly or C code. PSoC Express solves design problems the way you think about the system: ■ Development Kits Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click EZ-Color to view a current list of available items. ■ ■ ■ Select input and output devices based upon system requirements. Add a communications interface and define its interface to system (using registers). Define when and how an output device changes state based upon any and all other system devices. Based upon the design, automatically select one or more PSoC Mixed-Signal Controllers that match system requirements. Figure 3. PSoC Express Technical Training Modules Free PSoC technical training modules are available for users new to PSoC. Training modules cover designing, debugging, advanced analog and CapSense. Go to http://www.cypress.com/techtrain. Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to http://www.cypress.com, click on Design Support located on the left side of the web page, and select CYPros Consultants. Technical Support PSoC application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support/login.cfm. PSoC Express Subsystems Express Editor The Express Editor allows you to create designs visually by dragging and dropping inputs, outputs, communication interfaces, and other design elements, and then describing the logic that controls them. Project Manager The Project Manager allows you to work with your applications and projects in PSoC Express. A PSoC Express application is a top level container for projects and their associated files. Each project contains a design that uses a single PSoC device. An application can contain multiple projects so if you are creating an application that uses multiple PSoC devices you can keep all of the projects together in a single application. Most of the files associated with a project are automatically generated by PSoC Express during the build process, but you can make changes directly to the custom.c and custom.h files Application Notes A long list of application notes will assist you in every aspect of your design effort. To view the PSoC application notes, go to the http://www.cypress.com web site and select Application Notes under the Design Resources list located in the center of the web page. Application Notes are sorted by date by default. Document Number: 001-12981 Rev. ** Page 6 of 37 CY8CLED08 and also add your own custom code to the project in the Project Manager. Acronyms Used The following table lists the acronyms that are used in this document. Acronym AC ADC API CPU CT DAC DC ECO EEPROM FSR GPIO GUI HBM ICE ILO IMO IO IPOR LSb LVD MSb PC PLL POR alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current external crystal oscillator electrically erasable programmable read-only memory full scale range general purpose IO graphical user interface human body model in-circuit emulator internal low speed oscillator internal main oscillator input/output imprecise power on reset least-significant bit low voltage detect most-significant bit program counter phase-locked loop power on reset precision power on reset Programmable System-on-Chip™ pulse width modulator switched capacitor slow IMO switch mode pump static random access memory Description Application Editor The Application Editor allows you to edit custom.c and custom.h as well as any C or assembly language source code that you add to your project. With PSoC Express you can create application software without writing a single line of assembly or C code, but you have a full featured application editor at your finger tips if you want it. Build Manager The Build Manager gives you the ability to build the application software, assign pins, and generate the data sheet, schematic, and BOM for your project. Board Monitor The Board Monitor is a debugging tool designed to be used while attached to a prototype board through a communication interface that allows you to monitor changes in the various design elements in real time. The default communication for the board monitor is I2C. It uses the CY3240-I2USB I2C to USB Bridge Debugging/Communication Kit. Tuners A Tuner is a visual interface for the Board Monitor that allows you to view the performance of the HB LED drivers on your test board while your program is running, and manually override values and see the results. Document Conventions Units of Measure A units of measure table is located in the Electrical Specifications section. Table 6 on page 13 lists all the abbreviations used to measure the PSoC devices. PPOR PSoC® PWM SC SLIMO SMP SRAM Numeric Naming Hexidecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexidecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal. Document Number: 001-12981 Rev. ** Page 7 of 37 CY8CLED08 Pin Information Pinouts 48-Pin Part Pinout SSOP Table 2. 48-Pin Part Pinout (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 IO IO IO IO IO IO IO IO IO IO IO IO IO Input IO IO IO IO IO IO IO IO IO IO Power Type Digital IO IO IO IO IO IO IO IO IO IO IO IO Power I I Analog I IO IO I Pin Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] Description Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. 48-Pin Device A, I, P0[7] A, IO, P0[5] A, IO, P0[3] A, I, P0[1] P2[7] P2[5] A, I, P2[3] A, I, P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss Direct switched capacitor block input. Direct switched capacitor block input. Switch Mode Pump (SMP) connection to external components required. I2C Serial Clock (SCL). I2C Serial Data (SDA). Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP SCLK*. Ground connection. Crystal Output (XTALout), I2C Serial Data (SDA), ISSP SDATA.* Optional External Clock Input (EXTCLK). 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Vdd P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6], External VRef P2[4], External AGND P2[2], A, I P2[0], A, I P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] P5[2] P5[0] P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA Pin No. 39 39 40 41 42 43 44 Digital IO IO IO IO IO IO IO IO IO IO Analog Pin Name P4[6] P4[6] Description I I P2[0] P2[2] P2[4] P2[6] Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VRef). Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. I IO IO I Power P0[0] P0[2] P0[4] P0[6] Vdd Active high external reset with internal pull down. 45 46 47 48 LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). Document Number: 001-12981 Rev. ** Page 8 of 37 CY8CLED08 48-Pin Part Pinout QFN Table 3. 48-Pin Part Pinout (QFN**) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO IO Power I IO IO I I IO IO I I I IO IO IO IO IO IO IO IO IO IO Input IO IO IO IO IO IO IO IO IO IO Power Type Digital IO IO IO IO IO IO Power I I P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] Direct switched capacitor block input. Direct switched capacitor block input. Switch Mode Pump (SMP) connection to external components required. I2C Serial Clock (SCL). I2C Serial Data (SDA). Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal Output (XTALout), I2C Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK). Active high external reset with internal pull down. Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VRef). Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. LEGEND: A = Analog, I = Input, and O = Output. * These are the ISSP pins, which are not High Z at POR (Power On Reset). ** The QFN package has a center pad that must be connected to ground (Vss). Document Number: 001-12981 Rev. ** I2C SCL, XTALin, P1[1] Vss I2C SDA, XTALout, P1[0] P1[2] EXTCLK, P1[4] P1[6] P5[0] P5[2] P5[1] I2C SCL, P1[7] I2C SDA, P1[5] P1[3] 13 14 15 16 17 18 19 20 21 22 23 24 A, I, P2[3] A, I, P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] 1 2 48 47 46 45 44 43 42 41 40 39 38 37 Vdd P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6], External VRef 36 35 34 33 32 31 30 29 28 27 26 25 P2[4], External AGND P2[2], A, I P2[0], A, I P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] Analog Pin Name Description 48-Pin PSoC Device 3 4 5 6 7 8 9 10 11 12 P2[5] P2[7] P0[1], A, I P0[3], A, IO P0[5], A, IO P0[7], A, I QFN (Top View) Page 9 of 37 CY8CLED08 Register Reference This chapter lists the registers of the CY8CLED08 EZ-Color device. Register Mapping Tables The device has a total register address space of 512 bytes. The register space is referred to as IO space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1. Note In the following register mapping tables, blank fields are reserved and should not be accessed. Register Conventions The register conventions specific to this section are listed in the following table. Register Mapping Tables Convention Description R W L C # Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific Table 4. Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F Access Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 Access I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 RW # RW # RW RW RW RW RW RW RC W RC DBB00DR0 DBB00DR1 DBB00DR2 DBB00CR0 DBB01DR0 20 21 22 23 24 # W RW # # AMX_IN 60 61 62 RW ARF_CR CMP_CR0 63 64 RW # A3 A4 Blank fields are Reserved and should not be accessed. # Access is bit specific. Document Number: 001-12981 Rev. ** Page 10 of 37 CY8CLED08 Table 4. Register Map Bank 0 Table: User Space (continued) Name DBB01DR1 DBB01DR2 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 DCB03DR1 DCB03DR2 DCB03CR0 DBB10DR0 DBB10DR1 DBB10DR2 DBB10CR0 DBB11DR0 DBB11DR1 DBB11DR2 DBB11CR0 DCB12DR0 DCB12DR1 DCB12DR2 DCB12CR0 DCB13DR0 DCB13DR1 DCB13DR2 DCB13CR0 Addr (0,Hex) 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Access W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # Name ASY_CR CMP_CR1 Addr (0,Hex) 65 66 67 68 69 6A 6B 6C 6D 6E 6F Access # RW Name Addr (0,Hex) A5 A6 A7 A8 A9 AA AB AC AD AE AF Access Name DEC_DL DEC_CR0 DEC_CR1 MUL_X MUL_Y MUL_DH MUL_DL ACC_DR1 ACC_DR0 ACC_DR3 ACC_DR2 Addr (0,Hex) E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 Access RC RW RW W W R R RW RW RW RW ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 ACB02CR3 ACB02CR0 ACB02CR1 ACB02CR2 ACB03CR3 ACB03CR0 ACB03CR1 ACB03CR2 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF RW RW RW RW RW RW RW CPU_F RW RW RW RW RW RW RW CPU_SCR1 CPU_SCR0 F7 F8 F9 FA FB FC FD FE FF RL # # Blank fields are Reserved and should not be accessed. # Access is bit specific. Table 5. Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Add (1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Blank fields are Reserved and should not be accessed. Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F Access Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW OSC_GO_EN OSC_CR4 OSC_CR3 GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU Name Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF RW RW RW RW RW RW RW Access # Access is bit specific. Document Number: 001-12981 Rev. ** Page 11 of 37 CY8CLED08 Table 5. Register Map Bank 1 Table: Configuration Space (continued) Name DBB00FN DBB00IN DBB00OU DBB01FN DBB01IN DBB01OU DCB02FN DCB02IN DCB02OU DCB03FN DCB03IN DCB03OU DBB10FN DBB10IN DBB10OU DBB11FN DBB11IN DBB11OU DCB12FN DCB12IN DCB12OU DCB13FN DCB13IN DCB13OU Add (1,Hex) 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F RW RW RW RW RW RW RW RW RW RW RW RW ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 ACB02CR3 ACB02CR0 ACB02CR1 ACB02CR2 ACB03CR3 ACB03CR0 ACB03CR1 ACB03CR2 RW RW RW RW RW RW RW RW RW AMD_CR1 ALT_CR0 ALT_CR1 CLK_CR2 Access RW RW RW Name CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 Addr (1,Hex) 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RW RW RW RW Access RW RW RW RW Name Addr (1,Hex) A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. RW RW RW RW RW RW RW CPU_SCR1 CPU_SCR0 RW RW RW RW RW RW RW CPU_F IMO_TR ILO_TR BDG_TR ECO_TR Access Name OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP Addr (1,Hex) E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF # # RL W W RW W Access RW RW RW RW R Blank fields are Reserved and should not be accessed. Document Number: 001-12981 Rev. ** Page 12 of 37 CY8CLED08 Electrical Specifications This section presents the DC and AC electrical specifications of the CY8CLED08 EZ-Color device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/ez-color. Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted. Specifications for devices running at greater than 12 MHz are valid for -40oC ≤ TA ≤ 70oC and TJ ≤ 82oC. Figure 4. Voltage versus CPU Frequency 5 .25 The following table lists the units of measure that are used in this section. Table 6. Units of Measure Symbol o Unit of Measure Symbol μW Unit of Measure C degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts dB fF Hz KB Kbit kHz kΩ MHz MΩ μA μF μH μs μV μVrms mA ms mV nA ns nV Ω 4.75 Vdd Voltage 3.00 93 kHz pA pF pp ppm ps sps σ CPU Frequency Absolute Maximum Ratings Table 7. Absolute Maximum Ratings Symbol Description Min Typ Max Units o lid ng Va rati n pe io O eg R 12 MHz 24 MHz V Notes TSTG Storage Temperature -55 25 +100 C Higher storage temperatures will reduce data retention time. Recommended storage temperature is +25oC ± 25oC. Extended duration storage temperatures above 65oC will degrade reliability. TA Vdd VIO VIOZ IMIO IMAIO ESD LU Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Maximum Current into any Port Pin Configured as Analog Driver Electro Static Discharge Voltage Latch-up Current -40 -0.5 Vss- 0.5 Vss - 0.5 -25 -50 2000 – – – – – – – – – +85 +6.0 Vdd + 0.5 Vdd + 0.5 +50 +50 – 200 o C V V V mA mA V mA Human Body Model ESD. Document Number: 001-12981 Rev. ** Page 13 of 37 CY8CLED08 Operating Temperature Table 8. Operating Temperature Symbol Description Min Typ Max Units o Notes TA TJ Ambient Temperature Junction Temperature -40 -40 – – +85 +100 C The temperature rise from ambient to junction is package specific. See “Thermal Impedances” on page 34. The user must limit the power consumption to comply with this requirement. oC DC Electrical Characteristics DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 9. DC Chip-Level Specifications Symbol Description Min Typ Max Units Notes Vdd IDD Supply Voltage Supply Current 3.00 – – 5 5.25 8 V mA Conditions are Vdd = 5.0V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40 oC ≤ TA ≤ 55 oC. Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55 oC < TA ≤ 85 oC. Conditions are with properly loaded, 1 μW max, 32.768 kHz crystal. Vdd = 3.3V, -40 oC ≤ TA ≤ 55 oC. Conditions are with properly loaded, 1 μW max, 32.768 kHz crystal. Vdd = 3.3V, 55 oC < TA ≤ 85 o IDD3 Supply Current – 3.3 6.0 mA ISB ISBH ISBXTL Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT.a Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT at high temperature.a Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal.a Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal at high temperature.a Reference Voltage (Bandgap) for Silicon A b Reference Voltage (Bandgap) for Silicon B b – – – 3 4 4 6.5 25 7.5 μA μA μA ISBXTLH – 5 26 μA C. VREF VREF 1.275 1.280 1.300 1.300 1.325 1.320 V V Trimmed for appropriate Vdd. Trimmed for appropriate Vdd. a. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar functions enabled. b. Refer to the “Ordering Information” on page 36. Document Number: 001-12981 Rev. ** Page 14 of 37 CY8CLED08 DC General Purpose IO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 10. DC GPIO Specifications Symbol Description Min Typ Max Units Notes RPU RPD VOH Pull up Resistor Pull down Resistor High Output Level 4 4 Vdd - 1.0 5.6 5.6 – 8 8 – kΩ kΩ V IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). Vdd = 3.0 to 5.25. Vdd = 3.0 to 5.25. Gross tested to 1 μA. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC. VOL Low Output Level – – 0.75 V VIL VIH VH IIL CIN COUT Input Low Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load on Pins as Input – 2.1 – – – – – 60 1 3.5 3.5 0.8 V V – – 10 10 mV nA pF pF Capacitive Load on Pins as Output – DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 11. 5V DC Operational Amplifier Specifications Symbol Description Min Typ Max Units Notes The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at 25°C and are for design guidance only. VOSOA Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High – – – – – – 0.0 0.5 1.6 1.3 1.2 7.0 20 4.5 – – 10 8 7.5 35.0 – 9.5 Vdd Vdd - 0.5 mV mV mV μV/oC TCVOSOA IEBOA CINOA VCMOA Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Common Mode Voltage Range (high power or high opamp bias) pA pF V Gross tested to 1 μA. Package and pin dependent. Temp = 25oC. The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. CMRROA Common Mode Rejection Ratio Power = Low Power = Medium Power = High 60 60 60 – – dB GOLOA Open Loop Gain Power = Low Power = Medium Power = High 60 60 80 Vdd - 0.2 Vdd - 0.2 Vdd - 0.5 – – dB Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. VOHIGHOA High Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High – – – – – – V V V Document Number: 001-12981 Rev. ** Page 15 of 37 CY8CLED08 Table 11. 5V DC Operational Amplifier Specifications (continued) Symbol Description Min Typ Max Units Notes VOLOWOA Low Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High – – – – – – – – – 60 – – – 150 300 600 1200 2400 4600 – 0.2 0.2 0.5 200 400 800 1600 3200 6400 – V V V μA μA μA μA μA μA ISOA Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High PSRROA Supply Voltage Rejection Ratio dB Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤ VIN ≤ Vdd. Table 12. 3.3V DC Operational Amplifier Specifications Symbol Description Min Typ Max Units Notes VOSOA Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High High Power is 5 Volts Only – – – – – 0.2 1.65 1.32 7.0 20 4.5 – 10 8 35.0 – 9.5 Vdd - 0.2 mV mV μV/oC TCVOSOA IEBOA CINOA VCMOA Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range pA pF V Gross tested to 1 μA. Package and pin dependent. Temp = 25oC. The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. CMRROA Common Mode Rejection Ratio Power = Low Power = Medium Power = High 50 50 50 – – dB GOLOA Open Loop Gain Power = Low Power = Medium Power = High 60 60 80 Vdd - 0.2 Vdd - 0.2 Vdd - 0.2 – – – – – – – – – 50 – – dB Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. VOHIGHOA High Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High is 5V only – – – – – – 150 300 600 1200 2400 4600 80 – – – 0.2 0.2 0.2 200 400 800 1600 3200 6400 – V V V V V V μA μA μA μA μA μA VOLOWOA Low Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High ISOA Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High PSRROA Supply Voltage Rejection Ratio dB Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤ VIN ≤ Vdd. Document Number: 001-12981 Rev. ** Page 16 of 37 CY8CLED08 DC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 13. DC Low Power Comparator Specifications Symbol Description Min Typ Max Units Notes VREFLPC ISLPC VOSLPC Low power comparator (LPC) reference voltage range LPC supply current LPC voltage offset 0.2 – – – 10 2.5 Vdd - 1 40 30 V μA mV DC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 14. 5V DC Analog Output Buffer Specifications Symbol Description Min Typ Max Units Notes VOSOB TCVOSOB VCMOB ROUTOB Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High – – 0.5 – – 0.5 x Vdd + 1.3 0.5 x Vdd + 1.3 3 +6 – 1 1 – – 12 – Vdd - 1.0 – – – – mV μV/°C V Ω Ω VOHIGHOB High Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High V V VOLOWOB Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High – – – – 0.5 x Vdd 1.3 0.5 x Vdd 1.3 V V ISOB Supply Current Including Bias Cell (No Load) Power = Low Power = High – – 60 1.1 2.6 64 5.1 8.8 – mA mA dB PSRROB Supply Voltage Rejection Ratio Document Number: 001-12981 Rev. ** Page 17 of 37 CY8CLED08 Table 15. 3.3V DC Analog Output Buffer Specifications Symbol Description Min Typ Max Units Notes VOSOB TCVOSOB VCMOB ROUTOB Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High – – 0.5 – – 3 +6 1 1 12 – Vdd - 1.0 – – – – mV μV/°C V Ω Ω VOHIGHOB High Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High 0.5 x Vdd + 1.0 – 0.5 x Vdd + 1.0 – V V VOLOWOB Low Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High – – – – 0.5 x Vdd - 1.0 0.5 x Vdd - 1.0 V V ISOB Supply Current Including Bias Cell (No Load) Power = Low Power = High – 60 0.8 2.0 64 2.0 4.3 – mA mA dB PSRROB Supply Voltage Rejection Ratio DC Switch Mode Pump Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 16. DC Switch Mode Pump (SMP) Specifications Symbol Description Min Typ Max Units Notes VPUMP 5V VPUMP 3V IPUMP 5V Output Voltage 3V Output Voltage Available Output Current VBAT = 1.5V, VPUMP = 3.25V VBAT = 1.8V, VPUMP = 5.0V 4.75 3.00 5.0 3.25 5.25 3.60 V V Configuration of footnote.a Average, neglecting ripple. SMP trip voltage is set to 5.0V. Configuration of footnote.a Average, neglecting ripple. SMP trip voltage is set to 3.25V. Configuration of footnote.a 8 5 1.8 1.0 1.1 – – – – – – 5 – – 5.0 3.3 – – mA mA V V V %VO SMP trip voltage is set to 3.25V. SMP trip voltage is set to 5.0V. Configuration of footnote.a SMP trip voltage is set to 5.0V. Configuration of footnote.a SMP trip voltage is set to 3.25V. Configuration of footnote.a Configuration of footnote.a VO is the “Vdd Value for PUMP Trip” specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 20 on page 21. Configuration of footnote.a VO is the “Vdd Value for PUMP Trip” specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 20 on page 21. Configuration of footnote.a Load is 5mA. Configuration of footnote.a Load is 5 mA. SMP trip voltage is set to 3.25V. VBAT5V VBAT3V VBATSTART ΔVPUMP_Line Input Voltage Range from Battery Input Voltage Range from Battery Minimum Input Voltage from Battery to Start Pump Line Regulation (over VBAT range) ΔVPUMP_Load Load Regulation – 5 – %VO ΔVPUMP_Ripple Output Voltage Ripple (depends on capacitor/load) Efficiency Switching Frequency Switching Duty Cycle – 35 – – 100 50 1.3 50 – – – – mVpp % MHz % E3 FPUMP DCPUMP a. L1 = 2 μH inductor, C1 = 10 μF capacitor, D1 = Schottky diode. Document Number: 001-12981 Rev. ** Page 18 of 37 CY8CLED08 Figure 5. Basic Switch Mode Pump Circuit D1 Vdd V PUMP L1 V BAT C1 SMP + Battery PSoC Vss DC Analog Reference Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high. Table 17. 5V DC Analog Reference Specifications Symbol Description Min Typ Max Units BG – – – – – – – – – – – – – – – – – Bandgap Voltage Reference AGND = Vdd/2a AGND = 2 x BandGapa a 1.28 Vdd/2 - 0.030 2 x BG - 0.043 P2[4] - 0.011 BG - 0.009 1.6 x BG - 0.018 Vdd/2)a -0.034 1.30 Vdd/2 2 x BG P2[4] BG 1.6 x BG 0.000 1.32 Vdd/2 + 0.007 2 x BG + 0.024 P2[4] + 0.011 BG + 0.009 1.6 x BG + 0.018 0.034 V V V V V V V V V V V V V V V V V V AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGapa AGND = 1.6 x BandGapa AGND Block to Block Variation (AGND = RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap Vdd/2 + BG - 0.1 3 x BG - 0.06 2 x BG + P2[6] - 0.06 P2[4] + BG - 0.06 P2[4] + P2[6] - 0.06 3.2 x BG - 0.06 Vdd/2 + BG - 0.01 3 x BG - 0.01 2 x BG + P2[6] - 0.01 P2[4] + BG - 0.01 P2[4] + P2[6] - 0.01 3.2 x BG - 0.01 Vdd/2 + BG + 0.1 3 x BG + 0.06 2 x BG + P2[6] + 0.06 P2[4] + BG + 0.06 P2[4] + P2[6] + 0.06 3.2 x BG + 0.06 RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) RefHi = 3.2 x BandGap RefLo = Vdd/2 – BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) RefLo = P2[4] – BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) Vdd/2 - BG - 0.051 BG - 0.06 2 x BG - P2[6] - 0.04 P2[4] - BG - 0.056 P2[4] - P2[6] - 0.056 Vdd/2 - BG + 0.01 BG + 0.01 2 x BG - P2[6] + 0.01 P2[4] - BG + 0.01 P2[4] - P2[6] + 0.01 Vdd/2 - BG + 0.06 BG + 0.06 2 x BG - P2[6] + 0.04 P2[4] - BG + 0.056 P2[4] - P2[6] + 0.056 a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Document Number: 001-12981 Rev. ** Page 19 of 37 CY8CLED08 Table 18. 3.3V DC Analog Reference Specifications Symbol Description Min Typ Max Units BG – – – – – – – – – – – – – – – – – Bandgap Voltage Reference AGND = Vdd/2a AGND = 2 x BandGapa AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGapa AGND = 1.6 x BandGapa AGND Block to Block Variation (AGND = RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) RefLo = P2[4] – BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) Vdd/2)a 1.28 Vdd/2 - 0.027 Not Allowed P2[4] - 0.008 BG - 0.009 1.6 x BG - 0.018 -0.034 Not Allowed Not Allowed Not Allowed Not Allowed P2[4] + P2[6] - 0.06 Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed P2[4] - P2[6] - 0.048 1.30 Vdd/2 1.32 Vdd/2 + 0.005 V V P2[4] BG 1.6 x BG 0.000 P2[4] + 0.009 BG + 0.009 1.6 x BG + 0.018 0.034 V V V mV P2[4] + P2[6] - 0.01 P2[4] + P2[6] + 0.057 V P2[4] - P2[6] + 0.01 P2[4] - P2[6] + 0.048 V a. AGND tolerance includes the offsets of the local buffer in the PSoC block. Note See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V. DC Analog PSoC Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 19. DC Analog PSoC Block Specifications Symbol Description Min Typ Max Units Notes RCT CSC Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switch Cap) – – 12.2 80 – – kΩ fF Document Number: 001-12981 Rev. ** Page 20 of 37 CY8CLED08 DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Note The bits PORLEV and VM in the table below refer to bits in the VLT_CR register. Table 20. DC POR and LVD Specifications Symbol Description Min Typ Max Units Notes Vdd Value for PPOR Trip (positive ramp) VPPOR0R VPPOR1R VPPOR2R VPPOR0 VPPOR1 VPPOR2 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for PPOR Trip (negative ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b PPOR Hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Vdd Value for PUMP Trip VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b 2.96 3.03 3.18 4.11 4.55 4.63 4.72 4.90 3.02 3.10 3.25 4.19 4.64 4.73 4.82 5.00 3.08 3.16 3.32 4.28 4.74 4.82 4.91 5.10 V V V V V V V V V 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 2.98a 3.08 3.20 4.08 4.57 4.74b 4.82 4.91 V V V V V V V V V – – – 92 0 0 – – – mV mV mV – 2.82 4.39 4.55 – V V V – 2.91 4.39 4.55 – V V V Vdd must be greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from Watchdog. a. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. b. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply. Document Number: 001-12981 Rev. ** Page 21 of 37 CY8CLED08 DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 21. DC Programming Specifications Symbol Description Min Typ Max Units Notes IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR Supply Current During Programming or Verify Input Low Voltage During Programming or Verify Input High Voltage During Programming or Verify Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify Output Low Voltage During Programming or Verify Output High Voltage During Programming or Verify Flash Endurance (per block) Flash Endurance (total)a – – 2.2 – – – Vdd - 1.0 50,000 1,800,000 10 5 – – – – – – – – – 25 0.8 – 0.2 1.5 mA V V mA mA Driving internal pull-down resistor. Driving internal pull-down resistor. Vss + 0.75 V Vdd – – – V – – Years Erase/write cycles per block. Erase/write cycles. Flash Data Retention a. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. Document Number: 001-12981 Rev. ** Page 22 of 37 CY8CLED08 AC Electrical Characteristics AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 22. AC Chip-Level Specifications Symbol Description Min Typ Max Units Notes FIMO FCPU1 FCPU2 F48M F24M F32K1 F32K2 FPLL Jitter24M2 TPLLSLEW TPLLSLEWSLOW Internal Main Oscillator Frequency CPU Frequency (5V Nominal) CPU Frequency (3.3V Nominal) Digital PSoC Block Frequency Digital PSoC Block Frequency Internal Low Speed Oscillator Frequency External Crystal Oscillator PLL Frequency 24 MHz Period Jitter (PLL) PLL Lock Time PLL Lock Time for Low Gain Setting External Crystal Oscillator Startup to 1% External Crystal Oscillator Startup to 100 ppm 23.4 0.93 0.93 0 0 15 – – – 0.5 0.5 – – 24 24 12 48 24 32 32.768 23.986 – – – 1700 2800 24.6a 24.6a,b 12.3 b,c MHz MHz MHz MHz MHz kHz kHz MHz ps ms ms ms ms Trimmed. Utilizing factory trim values. Trimmed. Utilizing factory trim values. Trimmed. Utilizing factory trim values. Refer to the AC Digital Block Specifications below. 49.2a,b,d 24.6b, d 64 – – 600 10 50 2620 3800 Accuracy is capacitor and crystal dependent. 50% duty cycle. Multiple (x732) of crystal frequency. TOS TOSACC The crystal oscillator frequency is within 100 ppm of its final value by the end of the Tosacc period. Correct operation assumes a properly loaded 1 uW maximum drive level 32.768 kHz crystal. 3.0V ≤ Vdd ≤ 5.5V, -40 o C ≤ TA ≤ 85 oC. Jitter32k TXRST DC24M Step24M Fout48M Jitter24M1 FMAX TRAMP 32 kHz Period Jitter External Reset Pulse Width 24 MHz Duty Cycle 24 MHz Trim Step Size 48 MHz Output Frequency 24 MHz Period Jitter (IMO) Maximum frequency of signal on row input or row output. Supply Ramp Time – 10 40 – 46.8 – – 0 100 – 50 50 48.0 600 – – 12.3 – – 60 – 49.2a,c ns μs % kHz MHz ps MHz μs Trimmed. Utilizing factory trim values. a. b. c. d. 4.75V < Vdd < 5.25V. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V. See the individual user module data sheets for information on maximum frequencies for user modules. Figure 6. PLL Lock Timing Diagram PLL Enable TPLLSLEW 24 MHz FPLL PLL Gain 0 Document Number: 001-12981 Rev. ** Page 23 of 37 CY8CLED08 Figure 7. PLL Lock for Low Gain Setting Timing Diagram PLL Enable TPLLSLEWLOW 24 MHz FPLL PLL Gain 1 Figure 8. External Crystal Oscillator Startup Timing Diagram 32K Select TOS 32 kHz F32K2 Figure 9. 24 MHz Period Jitter (IMO) Timing Diagram Jitter24M1 F 24M Figure 10. 32 kHz Period Jitter (ECO) Timing Diagram Jitter32k F 32K2 AC General Purpose IO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 23. AC GPIO Specifications Symbol Description Min Typ Max Units Notes FGPIO TRiseF TFallF TRiseS TFallS GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF 0 3 2 10 10 – – – 27 22 12 18 18 – – MHz ns ns ns ns Normal Strong Mode Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Document Number: 001-12981 Rev. ** Page 24 of 37 CY8CLED08 Figure 11. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS AC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Power = High and Opamp Bias = High is not supported at 3.3V. Table 24. 5V AC Operational Amplifier Specifications Symbol Description Min Typ Max Units Notes TROA Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High – – – – – – 3.9 0.72 0.62 μs μs μs TSOA Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High – – – 0.15 1.7 6.5 0.01 0.5 4.0 0.75 3.1 5.4 – – – – – – – – – – – – – 100 5.9 0.92 0.72 – – – – – – – – – – μs μs μs SRROA Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High V/μs V/μs V/μs V/μs V/μs V/μs MHz MHz MHz nV/rt-Hz SRFOA Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High BWOA Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High ENOA Noise at 1 kHz (Power = Medium, Opamp Bias = High) Document Number: 001-12981 Rev. ** Page 25 of 37 CY8CLED08 Table 25. 3.3V AC Operational Amplifier Specifications Symbol Description Min Typ Max Units Notes TROA Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High – – – – 3.92 0.72 μs μs TSOA Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High – – 0.31 2.7 0.24 1.8 0.67 2.8 – – – – – – – – – 100 5.41 0.72 – – – – – – – μs μs SRROA Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High V/μs V/μs V/μs V/μs MHz MHz nV/rt-Hz SRFOA Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High BWOA Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High ENOA Noise at 1 kHz (Power = Medium, Opamp Bias = High) When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor. Figure 12. Typical AGND Noise with P2[4] Bypass dBV/rtHz 10000 0 0.01 0.1 1.0 10 1000 100 0.001 0.01 0.1 Freq (kHz) 1 10 100 Document Number: 001-12981 Rev. ** Page 26 of 37 CY8CLED08 At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level. Figure 13. Typical Opamp Noise nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000 100 10 0.001 0.01 0.1 Freq (kHz) 1 10 100 AC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 26. AC Low Power Comparator Specifications Symbol Description Min Typ Max Units μs Notes ≥ 50 mV overdrive comparator reference set within VREFLPC. TRLPC LPC response time – – 50 Document Number: 001-12981 Rev. ** Page 27 of 37 CY8CLED08 AC Digital Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 27. AC Digital Block Specifications Function Description Min Typ Max Units Notes All Functions Timer Maximum Block Clocking Frequency (> 4.75V) Maximum Block Clocking Frequency (< 4.75V) Capture Pulse Width Maximum Frequency, No Capture Maximum Frequency, With Capture 50a – – 50a – – – – – – – – 49.2 24.6 – 49.2 24.6 – 49.2 24.6 ns MHz MHz ns MHz MHz 4.75V < Vdd < 5.25V. 3.0V < Vdd < 4.75V. 4.75V < Vdd < 5.25V. Counter Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input 4.75V < Vdd < 5.25V. Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency 20 50a 50 – – – – – 50a – – – – a – – – – – – – – – – – – – – – – 49.2 49.2 24.6 8.2 4.1 – 24.6 49.2 24.6 49.2 ns ns ns MHz MHz MHz MHz ns ns MHz MHz MHz MHz Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. Maximum data rate at 4.1 MHz due to 2 x over clocking. 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. CRCPRS Maximum Input Clock Frequency (PRS Mode) CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM SPIS Maximum Input Clock Frequency Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions Transmitter Maximum Input Clock Frequency Maximum Input Clock Frequency with Vdd ≥ 4.75V, 2 Stop Bits Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency with Vdd ≥ 4.75V, 2 Stop Bits a. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). Document Number: 001-12981 Rev. ** Page 28 of 37 CY8CLED08 AC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 28. 5V AC Analog Output Buffer Specifications Symbol Description Min Typ Max Units μs μs μs μs Notes TROB Rising Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High – – – – 0.65 0.65 0.65 0.65 0.8 0.8 – – – – – – – – – – 2.5 2.5 2.2 2.2 – – – – – – TSOB Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High SRROB Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High V/μs V/μs V/μs V/μs MHz MHz SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High 300 300 – – – – kHz kHz Table 29. 3.3V AC Analog Output Buffer Specifications Symbol Description Min Typ Max Units μs μs μs μs Notes TROB Rising Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High – – – – 0.5 0.5 0.5 0.5 0.7 0.7 200 200 – – – – – – – – – – – – 3.8 3.8 2.6 2.6 – – – – – – – – TSOB Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High SRROB Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High V/μs V/μs V/μs V/μs MHz MHz kHz kHz SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High Document Number: 001-12981 Rev. ** Page 29 of 37 CY8CLED08 AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 30. 5V AC External Clock Specifications Symbol Description Min Typ Max Units Notes FOSCEXT – – – Frequency High Period Low Period Power Up IMO to Switch 0.093 20.6 20.6 150 – – – – 24.6 5300 – – MHz ns ns μs Table 31. 3.3V AC External Clock Specifications Symbol Description Min Typ Max Units Notes FOSCEXT FOSCEXT – – – Frequency with CPU Clock divide by 1a Frequency with CPU Clock divide by 2 or greaterb High Period with CPU Clock divide by 1 Low Period with CPU Clock divide by 1 Power Up IMO to Switch 0.093 0.186 41.7 41.7 150 – – – – – 12.3 24.6 5300 – – MHz MHz ns ns μs a. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. b. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met. AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 32. AC Programming Specifications Symbol Description Min Typ Max Units Notes TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK 1 1 40 40 0 – – – – – – – – – 10 10 – – 20 20 – – 8 – – 45 50 ns ns ns ns MHz ms ms ns ns Vdd > 3.6 3.0 ≤ Vdd ≤ 3.6 Document Number: 001-12981 Rev. ** Page 30 of 37 CY8CLED08 AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 33. AC Characteristics of the I2C SDA and SCL Pins Standard Mode Symbol Description Min Max Fast Mode Min Max Units Notes FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C SCL Clock Frequency Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. LOW Period of the SCL Clock HIGH Period of the SCL Clock Set-up Time for a Repeated START Condition Data Hold Time Data Set-up Time Set-up Time for STOP Condition Bus Free Time Between a STOP and START Condition Pulse Width of spikes are suppressed by the input filter. 0 4.0 4.7 4.0 4.7 0 250 4.0 4.7 – 100 – – – – – – – – – 0 0.6 1.3 0.6 0.6 0 100a 0.6 1.3 0 400 – – – – – – – – 50 kHz μs μs μs μs μs ns μs μs ns a. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Figure 14. Definition for Timing for Fast/Standard Mode on the I2C Bus SDA TLOWI2C TSUDATI2C THDSTAI2C TSPI2C TBUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C Sr P S Document Number: 001-12981 Rev. ** Page 31 of 37 CY8CLED08 Packaging Information This section illustrates the packaging specifications for the CY8CLED08 EZ-Color device, along with the thermal impedances for each package and the typical package capacitance on crystal pins. Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161. Packaging Dimensions Figure 15. 48-Lead (300-Mil) SSOP Document Number: 001-12981 Rev. ** Page 32 of 37 CY8CLED08 Figure 16. 48-Lead (7x7 mm) QFN 001-12919 *A Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. Important Note Pinned vias for thermal conduction are not required for the low-power PSoC device. Document Number: 001-12981 Rev. ** Page 33 of 37 CY8CLED08 Thermal Impedances Table 34. Thermal Impedances per Package Package Typical θJA * Development Tool Selection This section presents the development tools available for all current PSoC device families including the CY8CLED08 EZ-Color family. 48 SSOP 48 QFN** * TJ = TA + POWER x θJA 69 oC/W 18 oC/W Software Tools PSoC Express™ As the newest addition to the PSoC development software suite, PSoC Express is the first visual embedded system design tool that allows a user to create an entire PSoC project and generate a schematic, BOM, and data sheet without writing a single line of code. Users work directly with application objects such as LEDs, switches, sensors, and fans. PSoC Express is available free of charge at http://www.cypress.com/psocexpress. PSoC Designer™ Utilized by thousands of PSoC developers, this robust software has been facilitating PSoC designs for half a decade. PSoC Designer is available free of charge at http://www.cypress.com under DESIGN RESOURCES >> Software and Drivers. PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free ofcharge at http://www.cypress.com/psocprogrammer. CY3202-C iMAGEcraft C Compiler CY3202 is the optional upgrade to PSoC Designer that enables the iMAGEcraft C compiler. It can be purchased from the Cypress Online Store. At http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items. ** To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane. Capacitance on Crystal Pins Table 35. Typical Package Capacitance on Crystal Pins Package Package Capacitance 48 SSOP 48 QFN 3.3 pF 2.3 pF Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Table 36. Solder Reflow Peak Temperature Package Minimum Peak Temperature* Maximum Peak Temperature 48 SSOP 48 QFN 220oC 240oC 260oC 260oC *Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. Hardware Tools In-Circuit Emulator A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of the USB port. The base unit is universal and will operate with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. I2C to USB Bridge The I2C to USB Bridge is a quick and easy link from any design or application’s I2C bus to a PC via USB for design testing, debugging and communication. Document Number: 001-12981 Rev. ** Page 34 of 37 CY8CLED08 PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer or PSoC Express. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free ofcharge at http://www.cypress.com/psocprogrammer. CY3202-C iMAGEcraft C Compiler CY3202 is the optional upgrade to PSoC Designer that enables the iMAGEcraft C compiler. It can be purchased from the Cypress Online Store. At http://www.cypress.com, click the Online Store shopping cart icon at the bottom of the web page, and click PSoC (Programmable System-on-Chip) to view a current list of available items. CY3210-PSoCEval1 The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: ■ ■ ■ ■ ■ ■ Evaluation Board with LCD Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2) PSoC Designer Software CD Getting Started Guide USB 2.0 Cable Device Programmers Evaluation Tools All evaluation tools can be purchased from the Cypress Online Store. CY3261A-RGB EZ-Color RGB Kit The CY3261A-RGB board is a preprogrammed HB LED color mix board with seven pre-set colors using the CY8CLED16 EZ-Color HB LED Controller. The board is accompanied by a CD containing the color selector software application, PSoC Express 3.0 Beta 2, PSoC Programmer, and a suite of documents, schematics, and firmware examples. The color selector software application can be installed on a host PC and is used to control the EZ-Color HB LED controller using the included USB cable. The application enables you to select colors via a CIE 1931 chart or by entering coordinates. The kit includes: ■ ■ ■ ■ All device programmers can be purchased from the Cypress Online Store. CY3216 Modular Programmer The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes: ■ ■ ■ ■ ■ ■ Modular Programmer Base 3 Programming Module Cards MiniProg Programming Unit PSoC Designer Software CD Getting Started Guide USB 2.0 Cable Training Board (CY8CLED16) One mini-A to mini-B USB Cable PSoC Express CD-ROM Design Files and Application Installation CD-ROM CY3207ISSP In-System Serial Programmer (ISSP) The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. Note: CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes: ■ ■ ■ ■ To program and tune this kit via PSoC Express 3.0 you must use a Mini Programmer Unit (CY3217 Kit) and a CY3240-I2CUSB kit. CY3210-MiniProg1 The CY3210-MiniProg1 kit allows a user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes: ■ ■ ■ ■ ■ ■ ■ CY3207 Programmer Unit PSoC ISSP Software CD 110 ~ 240V Power Supply, Euro-Plug Adapter USB 2.0 Cable MiniProg Programming Unit MiniEval Socket Programming and Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software CD Getting Started Guide USB 2.0 Cable Document Number: 001-12981 Rev. ** Page 35 of 37 CY8CLED08 Accessories (Emulation and Programming) Table 37. Emulation and Programming Accessories Part # Pin Package Flex-Pod Kita Foot Kitb Adapterc Third Party Tools Several tools have been specially designed by the following 3rd-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com under DESIGN RESOURCES >> Evaluation Boards. CY8CLED08-48PVXI CY8CLED08-48LFXI 48 SSOP CY3250-27XXX 48 QFN CY3250-27XXX QFN CY3250-48 Adapters SSOP-FK can be found at CY3250-48 http://www.e QFN-FK mulation.com. Build a PSoC Emulator into Your Board For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, see Application Note “Debugging - Build a PSoC Emulator into Your Board - AN2323” at http://www.cypress.com/an2323. The following table lists the CY8CLED08 EZ-Color devices’ key package features and ordering codes. a. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. b. Foot kit includes surface mount feet that can be soldered to the target PCB. c. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com. Ordering Information Key Device Features Table 38. Device Key Features and Ordering Information Analog Blocks Digital Blocks (Rows of 4) (Columns of 3) Switch Mode Pump Temperature Range Package Ordering Code 48 Pin (300 Mil) SSOP 48 Pin (300 Mil) SSOP (Tape and Reel) 48 Pin (7x7) QFN 48 Pin (7x7) QFN (Tape and Reel) CY8CLED08-48PVXI 16K 256 256 256 256 Yes Yes Yes Yes -40C to +85C -40C to +85C -40C to +85C -40C to +85C 8 8 8 8 12 12 12 12 44 44 44 44 12 12 12 12 4 4 4 4 Yes Yes Yes Yes CY8CLED08-48PVXIT 16K CY8CLED08-48LFXI CY8CLED08-48LFXIT 16K 16K Ordering Code Definitions CY 8 C LED xx - xx xxxx Package Type: Thermal Rating: PX = PDIP Pb-Free C = Commercial SX = SOIC Pb-Free I = Industrial PVX = SSOP Pb-Free E = Extended LFX/LKX = QFN Pb-Free AX = TQFP Pb-Free Pin Count Part Number LED Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress Document Number: 001-12981 Rev. ** Page 36 of 37 XRES Pin Digital IO Pins Analog Outputs Flash (Bytes) Analog Inputs RAM (Bytes) CY8CLED08 Document History Table 39. CY8CLED08 Data Sheet Revision History Document Title: CY8CLED08 EZ-Color HB LED Controller Description of Change Document Number: 001-12981 Revision ECN # Issue Date Origin of Change New document (revision **). ** 1148504 See ECN SFVTMP3 Distribution: External Public Posting: None © Cypress Semiconductor Corporation, 2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. PSoC Designer™, Programmable System-on-Chip™, and PSoC Express™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are property of the respective corporations. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress' product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-12981 Rev. ** Page 37 of 37