CY8CLED08_10

CY8CLED08 EZ-Color™ HB LED Controller Features ■ HB LED Controller ❐ Configurable Dimmers Support up to Eight Independent LED Channels ❐ 8 to 32 Bits of Resolution per Channel ❐ Dynamic Reconfiguration Enables LED Controller Plus Other Features: CapSense, Battery Charging, and Motor Control Visual Embedded Design ❐ LED-Based Drivers • Binning Compensation • Temperature Feedback • Optical Feedback • DMX512 PrISM Modulation Technology ❐ Reduces Radiated EMI ❐ Reduces Low Frequency Blinking Powerful Harvard Architecture Processor ❐ M8C Processor Speeds to 24 MHz ❐ 3.0 to 5.25V Operating Voltage ❐ Operating Voltages Down to 1.0V using On-Chip Switch Mode Pump (SMP) ❐ Industrial Temperature Range: -40°C to +85°C Flexible On-Chip Memory ❐ 16K Flash Program Storage 50,000 Erase/Write Cycles ❐ 256 bytes SRAM Data Storage ❐ In-System Serial Programming (ISSP) ❐ Partial Flash Updates ❐ Flexible Protection Modes ❐ EEPROM Emulation in Flash ■ ■ Advanced Peripherals (PSoC® Blocks) ❐ Eight Digital PSoC Blocks Provide: • 8 to 32-Bit Timers, Counters, and PWMs • Up to Two Full-Duplex UARTs • Multiple SPI Masters or Slaves • Connectable to all GPIO pins ❐ 12 Rail-to-Rail Analog PSoC Blocks Provide: • Up to 14-Bit ADCs • Up to 9-Bit DACs • Programmable Gain Amplifiers • Programmable Filters and Comparators ❐ Complex peripherals by Combining Blocks Programmable Pin Configurations ❐ 25 mA Sink, 10 mA Source on all GPIO ❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on all GPIO ❐ Up to 12 Analog Inputs on GPIO ❐ Four 30 mA Analog Outputs on GPIO ❐ Configurable interrupt on all GPIO Complete Development Tools ❐ Free Development Software • PSoC Designer™ ❐ Full Featured, In-Circuit Emulator and Programmer ❐ Full Speed Emulation ❐ Complex Breakpoint Structure ❐ 128 KBytes Trace Memory ■ ■ ■ ■ ■ Cypress Semiconductor Corporation Document Number: 001-12981 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 •408-943-2600 Revised January 15, 2010 [+] Feedback CY8CLED08 Logic Block Diagram Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Analog Drivers PSoC CORE System Bus Global Digital Interconnect SRAM 256 Bytes Interrupt Controller Global Analog Interconnect Flash 16K Sleep and Watchdog SROM CPU Core (M8C) Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) DIGITAL SYSTEM Digital Block Array ANALOG SYSTEM Analog Ref. Analog Block Array Analog Input Muxing Digital Clocks Multiply Accum. POR and LVD Decimator I 2C System Resets Internal Voltage Ref. Switch Mode Pump SYSTEM RESOURCES Document Number: 001-12981 Rev. *E Page 2 of 44 [+] Feedback CY8CLED08 Contents 1. EZ-Color™ Functional Overview ................................... 4 1.1 Target Applications .................................................. 4 1.2 The PSoC Core ....................................................... 4 1.3 The Digital System .................................................. 4 1.4 The Analog System ................................................. 5 1.1 Additional System Resources ................................. 6 1.2 EZ-Color Device Characteristics ............................. 6 2. Getting Started ................................................................ 6 2.1 Development Kits .................................................... 6 2.2 Technical Training Modules .................................... 6 2.3 Consultants ............................................................. 6 2.4 Technical Support ................................................... 6 2.5 Application Notes .................................................... 6 3. Development Tools ........................................................ 7 3.1 PSoC Designer Software Subsystems .................... 7 3.2 In-Circuit Emulator ................................................... 7 4. Document Conventions ................................................. 8 4.1 Acronyms Used ....................................................... 8 4.2 Units of Measure ..................................................... 8 4.3 Numeric Naming ...................................................... 8 5. Pin Information ............................................................... 9 5.1 Pinouts .................................................................... 9 6. Register Reference ....................................................... 12 6.1 Register Conventions ............................................ 12 6.2 Register Mapping Tables ...................................... 12 7. Electrical Specifications ...............................................15 7.1 Absolute Maximum Ratings ...................................16 7.2 Operating Temperature .........................................16 7.3 DC Electrical Characteristics ..................................17 7.4 AC Electrical Characteristics ..................................26 8. Packaging Information ..................................................35 8.1 Packaging Dimensions ...........................................35 8.1 Thermal Impedances .............................................38 8.2 Capacitance on Crystal Pins .................................38 8.3 Solder Reflow Peak Temperature ..........................38 9. Development Tool Selection ........................................39 9.1 Software Tools .......................................................39 9.2 Hardware Tools ......................................................39 9.3 Evaluation Tools .....................................................39 9.4 Device Programmers ..............................................40 9.5 Accessories (Emulation and Programming) ...........41 9.6 Third Party Tools ....................................................41 9.7 Build a PSoC Emulator into Your Board .................41 10. Ordering Information ...................................................42 10.1 Key Device Features ............................................42 10.2 Ordering Code Definitions ...................................42 11. Document History Page ..............................................43 12. Sales, Solutions, and Legal Information ...................44 12.1 Worldwide Sales and Design Support ..................44 12.2 Products ...............................................................44 Document Number: 001-12981 Rev. *E Page 3 of 44 [+] Feedback CY8CLED08 1. EZ-Color™ Functional Overview Cypress' EZ-Color family of devices offers the ideal control solution for High Brightness LED applications requiring intelligent dimming control. EZ-Color devices combine the power and flexibility of PSoC (Programmable System-on-Chip). Cypress' PrISM (precise illumination signal modulation) modulation technology provides lighting designers a fully customizable and integrated lighting solution platform. The EZ-Color family supports a range of independent LED channels from 4 channels at 32 bits of resolution each, up to 16 channels at 8 bits of resolution each. This enables lighting designers the flexibility to choose the LED array size and color quality. PSoC Designer software, with lighting specific drivers, can significantly cut development time and simplify implementation of fixed color points through temperature, optical, and LED binning compensation. EZ-Color's virtually limitless analog and digital customization enable simple integration of features in addition to intelligent lighting, such as battery charging, image stabilization, and motor control during the development process. These features, along with Cypress' best-in-class quality and design support, make EZ-Color the ideal choice for intelligent HB LED control applications. Resource), provide the flexibility to integrate almost any timing requirement into the EZ-Color device. EZ-Color GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. 1.3 The Digital System The Digital System is composed of 8 digital blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Figure 1-1. Digital System Block Diagram Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Digital Clocks From Core To System Bus To Analog System 1.1 Target Applications ■ ■ ■ ■ ■ ■ DIGITAL SYSTEM Digital PSoC Block Array Row Input Configuration LCD Backlight Large Signs General Lighting Architectural Lighting Camera/Cell Phone Flash Flashlights 8 8 Row Input Configuration Row 0 DBB00 DBB01 DCB02 4 DCB03 4 Row Output Configuration 8 8 Row Output Configuration Row 1 DBB10 DBB11 DCB12 4 DCB13 4 1.2 The PSoC Core The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose I/O). The M8C CPU core is a powerful processor with speeds up to 48 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with 17 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT). Memory encompasses 16K of Flash for program storage, 256 bytes of SRAM for data storage, and up to 2K of EEPROM emulated using the Flash. Program Flash uses four protection levels on blocks of 64 bytes, allowing customized software IP protection. The EZ-Color family incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to 2.5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] Digital peripheral configurations include the following: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ PrISM (8 to 32 bit) PWMs (8 to 32 bit) PWMs with Dead band (8 to 32 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) UART 8 bit with selectable parity (up to 2) SPI slave and master (up to 2) I2C slave and multi-master (1 available as a System Resource) Cyclical Redundancy Checker/Generator (8 to 32 bit) IrDA (up to 2) Generators (8 to 32 bit) Document Number: 001-12981 Rev. *E Page 4 of 44 [+] Feedback CY8CLED08 The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also enable signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by EZ-Color device family. This allows you the optimum choice of system resources for your application. Family resources are shown in the table titled EZ-Color Device Characteristics. Figure 1-2. Analog System Block Diagram P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6] P0[4] P0[2] P0[0] P2[6] 1.4 The Analog System The analog system is composed of 12 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common EZ-Color analog functions (most available as user modules) are as follows: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ P2[3] P2[4] P2[2] P2[0] P2[1] Analog-to-digital converters (up to 4, with 6- to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR) Filters (2, 4, 6, and 8 pole band-pass, low-pass, and notch) Amplifiers (up to 4, with selectable gain to 48x) Instrumentation amplifiers (up to 2, with selectable gain to 93x) Comparators (up to 4, with 16 selectable thresholds) DACs (up to 4, with 6- to 9-bit resolution) Multiplying DACs (up to 4, with 6- to 9-bit resolution) High current output drivers (four with 30 mA drive as a Core Resource) 1.3V reference (as a System Resource) DTMF Dialer Modulators Correlators Peak detectors Many other topologies possible Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap ASD20 ASC21 ASD22 ASC23 ACB00 ASC10 ACI0[1:0] ACI1[1:0] ACI2[1:0] ACI3[1:0] Array Input Configuration Block Array ACB01 ASD11 ACB02 ASC12 ACB03 ASD13 Analog Reference Analog blocks are provided in columns of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks, as shown in the figure below. M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 001-12981 Rev. *E Page 5 of 44 [+] Feedback CY8CLED08 1.1 Additional System Resources System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Additional resources include a multiplier, decimator, switch mode pump, low voltage detection, and power on reset. Statements describing the merits of each system resource are below. ■ ■ The decimator provides a custom hardware filter for digital signal processing applications including the creation of Delta Sigma ADCs. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3V reference provides an absolute reference for the analog system, including ADCs and DACs. An integrated switch mode pump (SMP) generates normal operating voltages from a single 1.2V battery cell, providing a low cost boost converter. ■ Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital blocks as clock dividers. Multiply accumulate (MAC) provides fast 8-bit multiplier with 32-bit accumulate, to assist in general math and digital filters. ■ ■ ■ ■ 1.2 EZ-Color Device Characteristics Depending on your EZ-Color device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. The following table lists the resources available for specific EZ-Color device groups. The device covered by this data sheet is shown in the highlighted row of the table Table 1-1. EZ-Color Device Characteristics CapSense No Yes No No [+] Feedback LED Channels Analog Columns Analog Outputs Analog Inputs Analog Blocks Digital Blocks Digital I/O Digital Rows SRAM Size Part Number CY8CLED02 CY8CLED04 CY8CLED08 CY8CLED16 2 4 8 16 16 56 44 44 1 1 2 4 4 4 8 16 8 48 12 12 0 2 4 4 2 2 4 4 4 6 12 12 256 Bytes 1K 256 Bytes 2K 2. Getting Started The quickest path to understanding the EZ-Color silicon is by reading this data sheet and using the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the EZ-Color integrated circuit and presents specific pin, register, and electrical specifications. For up-to-date Ordering, Packaging, and Electrical Specification information, reference the latest device data sheets on the web at http://www.cypress.com/ez-color. 2.3 Consultants Certified PSoC Consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC Consultant go to http://www.cypress.com, click on Design Support located at the center of the web page, and select CYPros Consultants. 2.4 Technical Support Application engineers take pride in fast and accurate response. They can be reached with a 4-hour guaranteed response at http://www.cypress.com/support. 2.1 Development Kits Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at http://www.cypress.com/store, click Lighting & Power Control to view a current list of available items. 2.5 Application Notes A long list of application notes will assist you in every aspect of your design effort. To view the application notes, go to the http://www.cypress.com web site and select Application Notes under the Documentation tab. 2.2 Technical Training Modules Free PSoC technical training modules are available for users new to PSoC. Training modules cover designing, debugging, advanced analog and CapSense. Go to http://www.cypress.com/techtrain. Document Number: 001-12981 Rev. *E Page 6 of 44 Flash Size 4K 16K 16K 32K CY8CLED08 3. Development Tools PSoC Designer is a Microsoft® Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE runs on Windows XP or Windows Vista. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built-in support for third-party assemblers and C compilers. PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family. 3.1.4 Code Generation Tools PSoC Designer supports multiple third party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours. Assemblers. The assemblers allow assembly code to merge seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. 3.1.5 Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write I/O registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. 3.1.6 Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. 3.1 PSoC Designer Software Subsystems 3.1.1 System-Level View A drag-and-drop visual embedded system design environment based on PSoC Designer. In the system level view you create a model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state based upon any or all other system devices. Based upon the design, PSoC Designer automatically selects one or more PSoC Mixed-Signal Controllers that match your system requirements. PSoC Designer generates all embedded code, then compiles and links it into a programming file for a specific PSoC device. 3.1.2 Chip-Level View The chip-level view is a more traditional Integrated Development Environment (IDE) based on PSoC Designer. Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time. 3.1.3 Hybrid Designs You can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. All views of the project share a common code editor, builder, and common debug, emulation, and programming tools. 3.2 In-Circuit Emulator A low cost, high functionality In-Circuit Emulator (ICE) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. Document Number: 001-12981 Rev. *E Page 7 of 44 [+] Feedback CY8CLED08 4. Document Conventions 4.1 Acronyms Used The following table lists the acronyms that are used in this document. Acronym AC ADC API CPU CT DAC DC ECO EEPROM FSR GPIO GUI HBM ICE ILO IMO I/O IPOR LSb LVD MSb PC PLL POR PPOR PSoC® PWM SC SLIMO SMP SRAM Description alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current external crystal oscillator electrically erasable programmable read-only memory full scale range general purpose I/O graphical user interface human body model in-circuit emulator internal low speed oscillator internal main oscillator input/output imprecise power on reset least-significant bit low voltage detect most-significant bit program counter phase-locked loop power on reset precision power on reset Programmable System-on-Chip pulse width modulator switched capacitor slow IMO switch mode pump static random access memory 4.2 Units of Measure A units of measure table is located in the Electrical Specifications section. Table 7-1 on page 15 lists all the abbreviations used to measure the devices. 4.3 Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (for example, 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal. Document Number: 001-12981 Rev. *E Page 8 of 44 [+] Feedback CY8CLED08 5. Pin Information 5.1 Pinouts 5.1.1 48-Pin Part Pinout SSOP Table 5-1. 48-Pin Part Pinout (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Type Digital I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power I I Analog I I/O I/O I Pin Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] Optional External Clock Input (EXTCLK). Pin No. 39 39 40 41 42 43 44 Active high external reset with internal pull down. 45 46 47 48 Digital I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power I I/O I/O I I I Analog Pin Name P4[6] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VRef). Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. Description Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP SCLK[1]. Ground connection. Crystal Output (XTALout), I2C Serial Data (SDA), ISSP SDATA[1]. I2C Serial Clock (SCL). I2C Serial Data (SDA). Switch Mode Pump (SMP) connection to external components required. Direct switched capacitor block input. Direct switched capacitor block input. Description Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Figure 5-1. 48-Pin Device A, I, P0[7] A, IO, P0[5] A, IO, P0[3] A, I, P0[1] P2[7] P2[5] A, I, P2[3] A, I, P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 SSOP 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Vdd P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6], External VRef P2[4], External AGND P2[2], A, I P2[0], A, I P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] P5[2] P5[0] P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA LEGEND: A = Analog, I = Input, and O = Output. Note 1. These are the ISSP pins, which are not High Z at POR. Document Number: 001-12981 Rev. *E Page 9 of 44 [+] Feedback CY8CLED08 5.1.2 48-Pin Part Pinout QFN Table 5-2. 48-Pin Part Pinout (QFN)[2] Pin No. Type Digital Analog Pin Name Description Figure 5-2. 48-Pin Device Vdd P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6], External VRef 36 35 34 33 32 31 30 29 28 27 26 25 P2[4], External AGND P2[2], A, I P2[0], A, I P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 I/O I/O I/O I/O I/O I/O Power I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power I/O I/O I/O I/O I/O I/O I I P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] Direct switched capacitor block input. Direct switched capacitor block input. Switch Mode Pump (SMP) connection to external components required. I2C Serial Clock (SCL). I2C Serial Data (SDA). Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP-SCLK[1]. Ground connection. Crystal Output (XTALout), I2C Serial Data (SDA), ISSP-SDATA[1]. Optional External Clock Input (EXTCLK). Active high external reset with internal pull down. I I P2[0] P2[2] P2[4] P2[6] Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VRef). Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. I I/O I/O I I I/O I/O I P0[0] P0[2] P0[4] P0[6] Vdd P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] LEGEND: A = Analog, I = Input, and O = Output. Note 2. The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. Document Number: 001-12981 Rev. *E I2C SCL, XTALin, P1[1] Vss I2C SDA, XTALout, P1[0] P1[2] EXTCLK, P1[4] P1[6] P5[0] P5[2] P5[1] I2C SCL, P1[7] I2C SDA, P1[5] P1[3] 13 14 15 16 17 18 19 20 21 22 23 24 A, I, P2[3] A, I, P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 P2[5] P2[7] P0[1], A, I P0[3], A, IO P0[5], A, IO P0[7], A, I QFN (Top View) Page 10 of 44 [+] Feedback CY8CLED08 5.0.1 28-Pin Part Pinout Table 5-3. 28-Pin Part Pinout (SSOP) Pin No. Type Digital Analog Pin Name Description Figure 5-3. 28-Pin Device A, I, P0[7] A, IO, P0[5] A, IO, P0[3] A, I, P0[1] P2[7] P2[5] A, I, P2[3] A, I,P2[1] SMP I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2CSCL, XTALin, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 I/O I/O I/O I/O I/O I/O I/O I/O Power I/O I/O I/O I/O Power I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O Power I I/O I/O I P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. I I P2[3] P2[1] SMP P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES Direct switched capacitor block input. Direct switched capacitor block input. Switch Mode Pump (SMP) connection to external components required. I2C Serial Clock (SCL). I2C Serial Data (SDA). Crystal Input (XTALin), I2C Serial Clock (SCL), ISSP-SCLK[1]. Ground connection. Crystal Output (XTALout), I2C Serial Data (SDA), ISSP-SDATA[1]. Optional External Clock Input (EXTCLK). Active high external reset with internal pull down. Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VRef). Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6], External VRef P2[4], External AGND P2[2], A, I P2[0], A, I XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2CSDA I I P2[0] P2[2] P2[4] P2[6] I I/O I/O I P0[0] P0[2] P0[4] P0[6] Vdd LEGEND: A = Analog, I = Input, and O = Output. Document Number: 001-12981 Rev. *E Page 11 of 44 [+] Feedback CY8CLED08 6. Register Reference This chapter lists the registers of the CY8CLED08 EZ-Color device. 6.1 Register Conventions The register conventions specific to this section are listed in the following table. Register Mapping Tables Convention R W L C # Description Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific 6.2 Register Mapping Tables The device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1. Note In the following register mapping tables, blank fields are reserved and should not be accessed. Table 6-1. Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F Access Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 Access I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 RW # RW # RW RW RW RW RW RW RC W RC RC RW DBB00DR0 DBB00DR1 DBB00DR2 DBB00CR0 DBB01DR0 DBB01DR1 DBB01DR2 20 21 22 23 24 25 26 # W RW # # W RW AMX_IN 60 61 62 RW ARF_CR CMP_CR0 ASY_CR CMP_CR1 63 64 65 66 RW # # RW A3 A4 A5 A6 Blank fields are Reserved and should not be accessed. # Access is bit specific. Document Number: 001-12981 Rev. *E Page 12 of 44 [+] Feedback CY8CLED08 Table 6-1. Register Map Bank 0 Table: User Space (continued) Name DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 DCB03DR1 DCB03DR2 DCB03CR0 DBB10DR0 DBB10DR1 DBB10DR2 DBB10CR0 DBB11DR0 DBB11DR1 DBB11DR2 DBB11CR0 DCB12DR0 DCB12DR1 DCB12DR2 DCB12CR0 DCB13DR0 DCB13DR1 DCB13DR2 DCB13CR0 Addr (0,Hex) 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F Access # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # Name Addr (0,Hex) 67 68 69 6A 6B 6C 6D 6E 6F Access Name Addr (0,Hex) A7 A8 A9 AA AB AC AD AE AF Access Name DEC_CR1 MUL_X MUL_Y MUL_DH MUL_DL ACC_DR1 ACC_DR0 ACC_DR3 ACC_DR2 Addr (0,Hex) E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 Access RW W W R R RW RW RW RW ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 ACB02CR3 ACB02CR0 ACB02CR1 ACB02CR2 ACB03CR3 ACB03CR0 ACB03CR1 ACB03CR2 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF RW RW RW RW RW RW RW CPU_F RW RW RW RW RW RW RW CPU_SCR1 CPU_SCR0 F7 F8 F9 FA FB FC FD FE FF RL # # Blank fields are Reserved and should not be accessed. # Access is bit specific. Table 6-2. Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Add (1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F DBB00FN DBB00IN DBB00OU 20 21 22 RW RW RW CLK_CR0 CLK_CR1 ABF_CR0 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 RW RW RW Access Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 # Access is bit specific. Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU Name Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 RW RW RW RW RW RW RW RW RW RW Access Blank fields are Reserved and should not be accessed. Document Number: 001-12981 Rev. *E Page 13 of 44 [+] Feedback CY8CLED08 Table 6-2. Register Map Bank 1 Table: Configuration Space (continued) Name DBB01FN DBB01IN DBB01OU DCB02FN DCB02IN DCB02OU DCB03FN DCB03IN DCB03OU DBB10FN DBB10IN DBB10OU DBB11FN DBB11IN DBB11OU DCB12FN DCB12IN DCB12OU DCB13FN DCB13IN DCB13OU Add (1,Hex) 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F RW RW RW RW RW RW RW RW RW RW RW RW ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 ACB02CR3 ACB02CR0 ACB02CR1 ACB02CR2 ACB03CR3 ACB03CR0 ACB03CR1 ACB03CR2 RW RW RW RW RW RW Access RW RW RW AMD_CR1 ALT_CR0 ALT_CR1 CLK_CR2 Name AMD_CR0 Addr (1,Hex) 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RW RW RW RW Access RW Name Addr (1,Hex) A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. RW RW RW RW RW RW RW CPU_SCR1 CPU_SCR0 RW RW RW RW RW RW RW CPU_F IMO_TR ILO_TR BDG_TR ECO_TR Access Name VLT_CR VLT_CMP Addr (1,Hex) E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF # # RL W W RW W Access RW R Blank fields are Reserved and should not be accessed. Document Number: 001-12981 Rev. *E Page 14 of 44 [+] Feedback CY8CLED08 7. Electrical Specifications This section presents the DC and AC electrical specifications of the CY8CLED08 EZ-Color device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/ez-color. Specifications are valid for -40°C ≤ TA ≤ 85°C and TJ ≤ 100°C, except where noted. Specifications for devices running at greater than 12 MHz are valid for -40°C ≤ TA ≤ 70°C and TJ ≤ 82°C. Figure 7-1. Voltage versus CPU Frequency 5.25 4.75 Vdd Voltage 3.00 93 kHz CPU Frequency The following table lists the units of measure that are used in this section. Table 7-1. Units of Measure Symbol °C dB fF Hz KB Kbit kHz kΩ MHz MΩ μA μF μH μs μV μVrms Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square Symbol μW mA ms mV nA ns nV Ω pA pF pp ppm ps sps σ V Unit of Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts Document Number: 001-12981 Rev. *E lid ng Va rati n pe io O eg R 12 MHz 24 MHz Page 15 of 44 [+] Feedback CY8CLED08 7.1 Absolute Maximum Ratings Table 7-2. Absolute Maximum Ratings Symbol TSTG Description Storage Temperature Min -55 Typ 25 Max +100 Units °C Notes Higher storage temperatures will reduce data retention time. Recommended storage temperature is +25°C ± 25°C. Extended duration storage temperatures above 65°C will degrade reliability. TA Vdd VIO VIOZ IMIO IMAIO ESD LU Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Maximum Current into any Port Pin Configured as Analog Driver Electro Static Discharge Voltage Latch up Current -40 -0.5 Vss- 0.5 Vss - 0.5 -25 -50 2000 – – – – – – – – – +85 +6.0 Vdd + 0.5 Vdd + 0.5 +50 +50 – 200 °C V V V mA mA V mA Human Body Model ESD. 7.2 Operating Temperature Table 7-3. Operating Temperature Symbol TA TJ Description Ambient Temperature Junction Temperature Min -40 -40 Typ – – Max +85 +100 Units °C °C Notes The temperature rise from ambient to junction is package specific. See “Thermal Impedances” on page 38. The user must limit the power consumption to comply with this requirement. Document Number: 001-12981 Rev. *E Page 16 of 44 [+] Feedback CY8CLED08 7.3 DC Electrical Characteristics 7.3.1 DC Chip Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 7-4. DC Chip Level Specifications Symbol Vdd IDD Description Supply Voltage Supply Current Min 3.00 – Typ – 5 Max 5.25 8 Units V mA Notes Conditions are Vdd = 5.0V, TA = 25 °C, CPU = 3 MHz, SYSCLK doubler disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. Conditions are Vdd = 3.3V, TA = 25 °C, CPU = 3 MHz, SYSCLK doubler disabled. VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 93.75 kHz. Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40 °C ≤ TA ≤ 55 °C. Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55 °C < TA ≤ 85 °C. Conditions are with properly loaded, 1 μW max, 32.768 kHz crystal. Vdd = 3.3V, -40 °C ≤ TA ≤ 55 °C. Conditions are with properly loaded, 1 μW max, 32.768 kHz crystal. Vdd = 3.3V, 55 °C < TA ≤ 85 °C. Trimmed for appropriate Vdd. Trimmed for appropriate Vdd. IDD3 Supply Current – 3.3 6.0 mA ISB Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT.[3] Sleep (Mode) Current with POR, LVD, Sleep Timer, and WDT at high temperature.[3] Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal.[3] – 3 6.5 μA μA μA ISBH – 4 25 ISBXTL – 4 7.5 ISBXTLH Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and external crystal at high temperature.[3] Reference Voltage (Bandgap) for Silicon A [4] Reference Voltage (Bandgap) for Silicon B [4] – 5 26 μA VREF VREF 1.275 1.280 1.300 1.300 1.325 1.320 V V Notes 3. Standby current includes all functions (POR, LVD, WDT, Sleep Time) needed for reliable system operation. This should be compared with devices that have similar functions enabled. 4. Refer to the “Ordering Information” on page 42. Document Number: 001-12981 Rev. *E Page 17 of 44 [+] Feedback CY8CLED08 7.4 DC General Purpose I/O Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 7-5. DC GPIO Specifications Symbol RPU RPD VOH Description Pull up Resistor Pull down Resistor High Output Level Min 4 4 Vdd - 1.0 Typ 5.6 5.6 – Max 8 8 – Units kΩ kΩ V Notes VOL Low Output Level – – 0.75 V IOH High Level Source Current 10 – – mA IOL VIL VIH VH IIL CIN COUT Low Level Sink Current Input Low Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output 25 – 2.1 – – – – – – – 60 1 3.5 3.5 – 0.8 – – 10 10 mA V V mV nA pF pF IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). VOH = Vdd-1.0V. See the limitations of the total current in the Note for VOH. VOL = 0.75V. See the limitations of the total current in the Note for VOL. Vdd = 3.0 to 5.25. Vdd = 3.0 to 5.25. Gross tested to 1 μA. Package and pin dependent. Temp = 25°C. Package and pin dependent. Temp = 25°C. 7.4.1 DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Cap PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 7-6. 5V DC Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Min – – – – – – Typ 1.6 1.3 1.2 7.0 20 4.5 Max 10 8 7.5 35.0 – 9.5 Units mV mV mV μV/°C pA pF Gross tested to 1 μA. Package and pin dependent. Temp = 25°C. Notes TCVOSOA IEBOA CINOA Document Number: 001-12981 Rev. *E Page 18 of 44 [+] Feedback CY8CLED08 Table 7-6. 5V DC Operational Amplifier Specifications (continued) Symbol VCMOA Description Common Mode Voltage Range Common Mode Voltage Range (high power or high opamp bias) Min 0.0 0.5 Typ – – Max Vdd Vdd 0.5 Units V Notes The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. CMRROA GOLOA Common Mode Rejection Ratio Power = Low Power = Medium Power = High Open Loop Gain Power = Low Power = Medium Power = High High Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High Low Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High Supply Voltage Rejection Ratio – 60 60 60 – 60 60 80 Vdd - 0.2 Vdd - 0.2 Vdd - 0.5 – – – – dB – dB VOHIGHOA – – – V V V VOLOWOA – – – – – – 0.2 0.2 0.5 V V V μA μA μA μA μA μA dB Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd 1.25V) ≤ VIN ≤ Vdd. ISOA – – – – – – 60 150 300 600 1200 2400 4600 – 200 400 800 1600 3200 6400 – PSRROA Table 7-7. 3.3V DC Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High High Power is 5 Volts Only Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Common Mode Voltage Range Min – – – – – 0.2 Typ 1.65 1.32 7.0 20 4.5 – Max 10 8 35.0 – 9.5 Vdd 0.2 Units mV mV μV/°C pA pF V Gross tested to 1 μA. Package and pin dependent. Temp = 25°C. The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Notes TCVOSOA IEBOA CINOA VCMOA Document Number: 001-12981 Rev. *E Page 19 of 44 [+] Feedback CY8CLED08 Table 7-7. 3.3V DC Operational Amplifier Specifications (continued) Symbol CMRROA Description Common Mode Rejection Ratio Power = Low Power = Medium Power = High Open Loop Gain Power = Low Power = Medium Power = High High Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High is 5V only Min 50 50 50 – 60 60 80 Vdd 0.2 Vdd 0.2 Vdd 0.2 – – – – – – – – – V V V – dB Typ – Max – Units dB Notes Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. Specification is applicable at high power. For all other bias modes (except high power, high opamp bias), minimum is 60 dB. GOLOA VOHIGHOA VOLOWOA Low Output Voltage Swing (internal signals) Power = Low Power = Medium Power = High Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High Supply Voltage Rejection Ratio – – – 0.2 0.2 0.2 V V V ISOA – – – – – – 50 150 300 600 1200 2400 4600 80 200 400 800 1600 3200 6400 – μA μA μA μA μA μA dB Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd 1.25V) ≤ VIN ≤ Vdd. PSRROA 7.4.2 DC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 7-8. DC Low Power Comparator Specifications Symbol VREFLPC ISLPC VOSLPC Description Low power comparator (LPC) reference voltage range LPC supply current LPC voltage offset Min 0.2 – – Typ – 10 2.5 Max Vdd - 1 40 30 Units V μA mV Notes Document Number: 001-12981 Rev. *E Page 20 of 44 [+] Feedback CY8CLED08 7.4.3 DC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 7-9. 5V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High High Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High Supply Current Including Bias Cell (No Load) Power = Low Power = High Supply Voltage Rejection Ratio Min – – 0.5 – – 0.5 x Vdd + 1.3 0.5 x Vdd + 1.3 Typ 3 +6 – 1 1 – – Max 12 – Vdd - 1.0 – – – – Units mV μV/°C V Ω Ω V V Notes VOHIGHOB VOLOWOB – – – – 0.5 x Vdd - 1.3 0.5 x Vdd - 1.3 V V ISOB PSRROB – – 60 1.1 2.6 64 5.1 8.8 – mA mA dB Table 7-10. 3.3V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common Mode Input Voltage Range Output Resistance Power = Low Power = High High Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High Low Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High Supply Current Including Bias Cell (No Load) Power = Low Power = High Supply Voltage Rejection Ratio Min – – 0.5 – – 0.5 x Vdd + 1.0 0.5 x Vdd + 1.0 Typ 3 +6 1 1 – – Max 12 – Vdd - 1.0 – – – – Units mV μV/°C V Ω Ω V V Notes VOHIGHOB VOLOWOB – – – – 0.5 x Vdd - 1.0 0.5 x Vdd - 1.0 V V ISOB – 60 0.8 2.0 64 2.0 4.3 – mA mA dB PSRROB Document Number: 001-12981 Rev. *E Page 21 of 44 [+] Feedback CY8CLED08 7.4.4 DC Switch Mode Pump Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 7-11. DC Switch Mode Pump (SMP) Specifications Symbol VPUMP 5V Description 5V Output Voltage Min 4.75 Typ 5.0 Max 5.25 Units V Notes Configuration of footnote.[5] Average, neglecting ripple. SMP trip voltage is set to 5.0V. Configuration of footnote.[5] Average, neglecting ripple. SMP trip voltage is set to 3.25V. Configuration of footnote.[5] SMP trip voltage is set to 3.25V. SMP trip voltage is set to 5.0V. Configuration of footnote.[5] SMP trip voltage is set to 5.0V. Configuration of footnote.[5] SMP trip voltage is set to 3.25V. Configuration of footnote.[5] Configuration of footnote.[5] VO is the “Vdd Value for PUMP Trip” specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 7-15 on page 24. Configuration of footnote.[5] VO is the “Vdd Value for PUMP Trip” specified by the VM[2:0] setting in the DC POR and LVD Specification, Table 7-15 on page 24. Configuration of footnote.[5] Load is 5 mA. Configuration of footnote.[5] Load is 5 mA. SMP trip voltage is set to 3.25V. VPUMP 3V 3V Output Voltage 3.00 3.25 3.60 V IPUMP VBAT5V VBAT3V VBATSTART ΔVPUMP_Line Available Output Current VBAT = 1.5V, VPUMP = 3.25V VBAT = 1.8V, VPUMP = 5.0V Input Voltage Range from Battery Input Voltage Range from Battery Minimum Input Voltage from Battery to Start Pump Line Regulation (over VBAT range) 8 5 1.8 1.0 1.1 – – – – – – 5 – – 5.0 3.3 – – mA mA V V V %VO ΔVPUMP_Load Load Regulation – 5 – %VO ΔVPUMP_Ripple Output Voltage Ripple (depends on capacitor/load) E3 Efficiency – 35 100 50 – – mVpp % FPUMP DCPUMP Switching Frequency Switching Duty Cycle – – 1.3 50 – – MHz % Figure 7-2. Basic Switch Mode Pump Circuit D1 Vdd VPUMP L1 VBAT C1 SMP + Battery EZ-Color Vss Note 5. L1 = 2 μH inductor, C1 = 10 μF capacitor, D1 = Schottky diode. Document Number: 001-12981 Rev. *E Page 22 of 44 [+] Feedback CY8CLED08 7.3.7 DC Analog Reference Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high. Table 7-12. 5V DC Analog Reference Specifications Symbol BG – – – – – – – – – – – – – – – – – AGND = Vdd/2[6] AGND = 2 x BandGap[6] AGND = P2[4] (P2[4] = Vdd/2)[6] AGND = BandGap[6] AGND = 1.6 x BandGap[6] AGND Block to Block Variation (AGND = Vdd/2)[6] RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) RefHi = 3.2 x BandGap RefLo = Vdd/2 – BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) RefLo = P2[4] – BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) Description Bandgap Voltage Reference Min 1.28 Vdd/2 - 0.030 2 x BG - 0.043 P2[4] - 0.011 BG - 0.009 1.6 x BG - 0.018 -0.034 Vdd/2 + BG - 0.1 3 x BG - 0.06 P2[4] + BG - 0.06 P2[4] + P2[6] - 0.06 3.2 x BG - 0.06 Vdd/2 - BG - 0.051 BG - 0.06 P2[4] - BG - 0.056 P2[4] - P2[6] - 0.056 Typ 1.30 Vdd/2 2 x BG P2[4] BG 1.6 x BG 0.000 Vdd/2 + BG - 0.01 3 x BG - 0.01 P2[4] + BG - 0.01 P2[4] + P2[6] - 0.01 3.2 x BG - 0.01 Vdd/2 - BG + 0.01 BG + 0.01 P2[4] - BG + 0.01 P2[4] - P2[6] + 0.01 Max 1.32 Vdd/2 + 0.007 2 x BG + 0.024 P2[4] + 0.011 BG + 0.009 1.6 x BG + 0.018 0.034 Vdd/2 + BG + 0.1 3 x BG + 0.06 P2[4] + BG + 0.06 P2[4] + P2[6] + 0.06 3.2 x BG + 0.06 Vdd/2 - BG + 0.06 BG + 0.06 P2[4] - BG + 0.056 P2[4] - P2[6] + 0.056 Units V V V V V V V V V V V V V V V V V V 2 x BG + P2[6] - 0.06 2 x BG + P2[6] - 0.01 2 x BG + P2[6] + 0.06 2 x BG - P2[6] - 0.04 2 x BG - P2[6] + 0.01 2 x BG - P2[6] + 0.04 Table 7-13. 3.3V DC Analog Reference Specifications Symbol BG – – – – – – – – – – – – – – – – – Description Bandgap Voltage Reference AGND = Vdd/2[6] AGND = 2 x BandGap[6] AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGap[6] AGND = 1.6 x BandGap[6] AGND Block to Block Variation (AGND = Vdd/2)[6] RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) RefLo = P2[4] – BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) Min 1.28 Vdd/2 - 0.027 P2[4] - 0.008 BG - 0.009 1.6 x BG - 0.018 -0.034 Typ Max 1.30 1.32 Vdd/2 Vdd/2 + 0.005 Not Allowed P2[4] P2[4] + 0.009 BG BG + 0.009 1.6 x BG 1.6 x BG + 0.018 0.000 0.034 Not Allowed Not Allowed Not Allowed Not Allowed P2[4] + P2[6] - 0.01 P2[4] + P2[6] + 0.057 Not Allowed Not Allowed Units V V V V V mV P2[4] + P2[6] - 0.06 V Not Allowed Not Allowed Not Allowed P2[4] - P2[6] - 0.048 P2[4] - P2[6] + 0.01 P2[4] - P2[6] + 0.048 V Note 6. AGND tolerance includes the offsets of the local buffer in the PSoC block.See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V. Document Number: 001-12981 Rev. *E Page 23 of 44 [+] Feedback CY8CLED08 7.3.8 DC Analog PSoC Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 7-14. DC Analog PSoC Block Specifications Symbol RCT CSC Description Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switched Capacitor) Min – – Typ 12.2 80 Max – – Units kΩ fF Notes 7.3.9 DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Note The bits PORLEV and VM in the following table refer to bits in the VLT_CR register. Table 7-15. DC POR and LVD Specifications Symbol Description Min Typ 2.91 4.39 4.55 Max Units V V V Notes Vdd must be greater than or equal to 2.5V during startup, reset from the XRES pin, or reset from Watchdog. Vdd Value for PPOR Trip (positive VPPOR0R ramp) VPPOR1R PORLEV[1:0] = 00b VPPOR2R PORLEV[1:0] = 01b PORLEV[1:0] = 10b VPPOR0 VPPOR1 VPPOR2 Vdd Value for PPOR Trip (negative ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b PPOR Hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Vdd Value for PUMP Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b – – – 2.82 4.39 4.55 – V V V VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 – – – 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 92 0 0 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 – – – 2.98[7] 3.08 3.20 4.08 4.57 4.74[8] 4.82 4.91 mV mV mV V V V V V V V V V V V V V V V V V VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 2.96 3.03 3.18 4.11 4.55 4.63 4.72 4.90 3.02 3.10 3.25 4.19 4.64 4.73 4.82 5.00 3.08 3.16 3.32 4.28 4.74 4.82 4.91 5.10 Notes 7. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. 8. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply. Document Number: 001-12981 Rev. *E Page 24 of 44 [+] Feedback CY8CLED08 7.3.10 DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 7-16. DC Programming Specifications Symbol IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR Description Supply Current During Programming or Verify Input Low Voltage During Programming or Verify Input High Voltage During Programming or Verify Input Current when Applying Vilp to P1[0] or P1[1] During Programming or Verify Input Current when Applying Vihp to P1[0] or P1[1] During Programming or Verify Output Low Voltage During Programming or Verify Output High Voltage During Programming or Verify Flash Endurance (per block) Flash Endurance (total)[10] Flash Data Retention Min – – 2.2 – – – Vdd - 1.0 50,000[9] 1,800,000 10 Typ 5 – – – – – – – – – Max 25 0.8 – 0.2 1.5 Vss + 0.75 Vdd – – – Units mA V V mA mA V V – – Years Erase/write cycles per block. Erase/write cycles. Driving internal pull down resistor. Driving internal pull down resistor. Notes Notes 9. The 50,000 cycle Flash endurance per block will only be guaranteed if the Flash is operating within one voltage range. Voltage ranges are 3.0V to 3.6V and 4.75V to 5.25V. 10. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. Document Number: 001-12981 Rev. *E Page 25 of 44 [+] Feedback CY8CLED08 7.4 AC Electrical Characteristics 7.4.1 AC Chip Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 7-17. AC Chip Level Specifications Symbol FIMO FCPU1 FCPU2 F48M F24M F32K1 F32K_U Description Internal Main Oscillator Frequency CPU Frequency (5V Nominal) CPU Frequency (3.3V Nominal) Digital PSoC Block Frequency Digital PSoC Block Frequency Internal Low Speed Oscillator Frequency Internal Low Speed Oscillator Untrimmed Frequency Min 23.4 0.093 0.093 0 0 15 5 Typ 24 24 12 48 24 32 – Max 24.6[11] 24.6[11,12] 12.3[12,13] 49.2[11,12,14] 24.6[12, 14] 64 – Units MHz MHz MHz MHz MHz kHz kHz Notes Trimmed. Using factory trim values. Trimmed. Using factory trim values. Trimmed. Using factory trim values. Refer to the AC Digital Block Specifications below. After a reset and before the m8c starts to run, the ILO is not trimmed. See the System Resets section of the PSoC Technical Reference Manual for details on timing this. Accuracy is capacitor and crystal dependent. 50% duty cycle. Multiple (x732) of crystal frequency. DCILO F32K2 Internal Low Speed Oscillator Duty Cycle External Crystal Oscillator 20 – 50 32.768 80 – % kHz FPLL PLL Frequency – – 0.5 0.5 – – 23.986 – – – 1700 2800 – 600 10 50 2620 3800 MHz ps ms ms ms ms Jitter24M2 24 MHz Period Jitter (PLL) TPLLSLEW PLL Lock Time TPLLSLEWSL PLL Lock Time for Low Gain Setting OW TOS TOSACC External Crystal Oscillator Startup to 1% External Crystal Oscillator Startup to 100 ppm The crystal oscillator frequency is within 100 ppm of its final value by the end of the Tosacc period. Correct operation assumes a properly loaded 1 μW maximum drive level 32.768 kHz crystal. 3.0V ≤ Vdd ≤ 5.5V, -40 °C ≤ TA ≤ 85 °C. Jitter32k TXRST DC24M Step24M 32 kHz Period Jitter External Reset Pulse Width 24 MHz Duty Cycle 24 MHz Trim Step Size – 10 40 – 100 – 50 50 – 60 – ns μs % kHz Notes 11. 4.75V < Vdd < 5.25V. 12. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 13. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V. 14. See the individual user module data sheets for information on maximum frequencies for user modules. Document Number: 001-12981 Rev. *E Page 26 of 44 [+] Feedback CY8CLED08 Table 7-17. AC Chip Level Specifications (continued) Symbol Fout48M Jitter24M1 FMAX SRPOWER_ UP Description 48 MHz Output Frequency 24 MHz Period Jitter (IMO) Maximum frequency of signal on row input or row output. Power Supply Slew Rate Time from End of POR to CPU Executing Code Min 46.8 – – – – Typ 48.0 600 – – 16 Max 49.2[11,13] Units MHz ps MHz V/ms ms Notes Trimmed. Utilizing factory trim values. 12.3 250 100 TPOWERUP Vdd slew rate during power up. Power up from 0V. See the System Resets section of the PSoC Technical Reference Manual. Figure 7-3. PLL Lock Timing Diagram PLL Enable TPLLSLEW 24 MHz FPLL PLL Gain 0 Figure 7-4. PLL Lock for Low Gain Setting Timing Diagram PLL Enable TPLLSLEWLOW 24 MHz FPLL PLL Gain 1 Figure 7-5. External Crystal Oscillator Startup Timing Diagram 32K Select TOS 32 kHz F32K2 Figure 7-6. 24 MHz Period Jitter (IMO) Timing Diagram Jitter24M1 F 24M Document Number: 001-12981 Rev. *E Page 27 of 44 [+] Feedback CY8CLED08 Figure 7-7. 32 kHz Period Jitter (ECO) Timing Diagram Jitter32k F 32K2 7.5 AC General Purpose I/O Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 7-18. AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF Min 0 3 2 10 10 Typ – – – 27 22 Max 12 18 18 – – Units MHz ns ns ns ns Notes Normal Strong Mode Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 4.5 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Figure 1. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS 7.5.1 AC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Power = High and Opamp Bias = High is not supported at 3.3V. Table 7-19. 5V AC Operational Amplifier Specifications Symbol TROA Description Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Min Typ Max Units μs μs μs μs μs μs Notes – – – – – – 3.9 0.72 0.62 TSOA – – – 0.15 1.7 6.5 – – – – – – 5.9 0.92 0.72 – – – SRROA V/μs V/μs V/μs Document Number: 001-12981 Rev. *E Page 28 of 44 [+] Feedback CY8CLED08 Table 7-19. 5V AC Operational Amplifier Specifications (continued) Symbol SRFOA Description Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Noise at 1 kHz (Power = Medium, Opamp Bias = High) Min Typ Max Units Notes 0.01 0.5 4.0 0.75 3.1 5.4 – – – – – – – 100 – – – – – – – V/μs V/μs V/μs MHz MHz MHz nV/rt-Hz BWOA ENOA Table 7-20. 3.3V AC Operational Amplifier Specifications Symbol TROA Description Rising Settling Time from 80% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Falling Settling Time from 20% of ΔV to 0.1% of ΔV (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Rising Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Falling Slew Rate (20% to 80%)(10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Noise at 1 kHz (Power = Medium, Opamp Bias = High) Min Typ Max Units μs μs μs μs Notes – – – – 3.92 0.72 TSOA – – 0.31 2.7 0.24 1.8 0.67 2.8 – – – – – – – – – 100 5.41 0.72 – – – – – – – SRROA V/μs V/μs V/μs V/μs MHz MHz nV/rt-Hz SRFOA BWOA ENOA When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor. Figure 7-8. Typical AGND Noise with P2[4] Bypass dBV/rtHz 10000 0 0.01 0.1 1.0 10 1000 100 0.001 0.01 0.1 Freq (kHz) 1 10 100 Document Number: 001-12981 Rev. *E Page 29 of 44 [+] Feedback CY8CLED08 At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level. Figure 7-9. Typical Opamp Noise nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000 100 10 0.001 0.01 0.1 Freq (kHz) 1 10 100 7.4.4 AC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 7-21. AC Low Power Comparator Specifications Symbol TRLPC Description LPC response time Min – Typ – Max 50 Units μs Notes ≥ 50 mV overdrive comparator reference set within VREFLPC. 7.4.5 AC Digital Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 7-22. AC Digital Block Specifications Function Description Min Typ Max Units Notes All Functions Timer Maximum Block Clocking Frequency (> 4.75V) Maximum Block Clocking Frequency (< 4.75V) Capture Pulse Width Maximum Frequency, No Capture Maximum Frequency, With Capture 50[15] – – 50[15] – – 20 50[15] 50[15] – – – – – – – – – – – 49.2 24.6 – 49.2 24.6 – 49.2 24.6 – – – 49.2 ns MHz MHz ns MHz MHz ns ns ns MHz 4.75V < Vdd < 5.25V. 3.0V < Vdd < 4.75V. 4.75V < Vdd < 5.25V. Counter Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input 4.75V < Vdd < 5.25V. Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency 4.75V < Vdd < 5.25V. Document Number: 001-12981 Rev. *E Page 30 of 44 [+] Feedback CY8CLED08 Table 7-22. AC Digital Block Specifications (continued) Function Description Min Typ Max Units Notes CRCPRS (PRS Mode) CRCPRS (CRC Mode) SPIM Maximum Input Clock Frequency Maximum Input Clock Frequency Maximum Input Clock Frequency – – – – – – 49.2 24.6 8.2 MHz MHz MHz 4.75V < Vdd < 5.25V. Maximum data rate at 4.1 MHz due to 2 x over clocking. SPIS Transmitter Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions Maximum Input Clock Frequency Maximum Input Clock Frequency with Vdd ≥ 4.75V, 2 Stop Bits – 50[15] – – – – – – 4.1 – 24.6 49.2 ns ns MHz MHz Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency with Vdd ≥ 4.75V, 2 Stop Bits – – – – 24.6 49.2 MHz MHz 7.4.6 AC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 7-23. 5V AC Analog Output Buffer Specifications Symbol TROB Description Rising Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High Min Typ Max Units μs μs μs μs Notes – – – – 0.65 0.65 0.65 0.65 0.8 0.8 300 300 – – – – – – – – – – – – 2.5 2.5 2.2 2.2 – – – – – – – – TSOB SRROB V/μs V/μs V/μs V/μs MHz MHz kHz kHz SRFOB BWOB BWOB Note 15. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). Document Number: 001-12981 Rev. *E Page 31 of 44 [+] Feedback CY8CLED08 Table 7-24. 3.3V AC Analog Output Buffer Specifications Symbol Description Rising Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High Min Typ Max Units μs μs μs μs Notes TROB – – – – 0.5 0.5 0.5 0.5 – – – – – – – – 3.8 3.8 2.6 2.6 – – – – TSOB SRROB V/μs V/μs V/μs V/μs SRFOB BWOB 0.7 0.7 – – – – MHz MHz BWOB 200 200 – – – – kHz kHz 7.4.7 AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 7-25. 5V AC External Clock Specifications Symbol Description Min Typ Max Units Notes FOSCEXT – – – Frequency High Period Low Period Power Up IMO to Switch 0.093 20.6 20.6 150 – – – – 24.6 5300 – – MHz ns ns μs Table 7-26. 3.3V AC External Clock Specifications Symbol Description Min Typ Max Units Notes FOSCEXT FOSCEXT – – – Frequency with CPU Clock divide by 1[16] 0.093 0.186 41.7 41.7 150 – – – – – 12.3 24.6 5300 – – MHz MHz ns ns μs Frequency with CPU Clock divide by 2 or greater[17] High Period with CPU Clock divide by 1 Low Period with CPU Clock divide by 1 Power Up IMO to Switch Notes 16. Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. 17. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met. Document Number: 001-12981 Rev. *E Page 32 of 44 [+] Feedback CY8CLED08 7.4.8 AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 7-27. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 TERASEALL Description Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Data Out Delay from Falling Edge of SCLK Flash Erase Time (Bulk) Min 1 1 40 40 0 – – – – – Typ – – – – – 10 10 – – 95 Max 20 20 – – 8 – – 45 50 – Units ns ns ns ns MHz ms ms ns ns ms Notes TPROGRAM_HOT Flash Block Erase + Flash Block Write Time TPROGRAM_COLD Flash Block Erase + Flash Block Write Time – – – – 80[18] ms 160[18] ms Vdd > 3.6 3.0 ≤ Vdd ≤ 3.6 Erase all blocks and protection fields at once. 0°C ≤ TJ ≤ 100°C -40°C ≤ TJ ≤ 0°C Note 18. For the full industrial range, the user must employ a Temperature Sensor User Module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. Document Number: 001-12981 Rev. *E Page 33 of 44 [+] Feedback CY8CLED08 7.4.9 AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 7-28. AC Characteristics of the I2C SDA and SCL Pins Symbol Description Standard-Mode Min Max 0 100 4.0 – Fast-Mode Min Max 0 400 0.6 – Units Notes FSCLI2C SCL Clock Frequency THDSTAI2C Hold Time (repeated) START Condition. After this period, the first clock pulse is generated. TLOWI2C LOW Period of the SCL Clock THIGHI2C HIGH Period of the SCL Clock TSUSTAI2C Set-up Time for a Repeated START Condition THDDATI2C Data Hold Time TSUDATI2C Data Set Up Time TSUSTOI2C Set-up Time for STOP Condition TBUFI2C Bus Free Time Between a STOP and START Condition TSPI2C Pulse Width of spikes are suppressed by the input filter. kHz μs μs μs μs μs ns μs μs 4.7 4.0 4.7 0 250 4.0 4.7 – – – – – – – – – 1.3 0.6 0.6 0 100[19] 0.6 1.3 0 – – – – – – – 50 ns Figure 7-10. Definition for Timing for Fast-/Standard-Mode on the I2C Bus SDA TLOWI2C TSUDATI2C THDSTAI2C TSPI2C TBUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C Sr P S Note 19. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 001-12981 Rev. *E Page 34 of 44 [+] Feedback CY8CLED08 8. Packaging Information This section illustrates the packaging specifications for the CY8CLED08 EZ-Color device, along with the thermal impedances for each package and the typical package capacitance on crystal pins. Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161. 8.1 Packaging Dimensions Figure 8-1. 28-Pin (210-Mil) SSOP 51-85079 *D Document Number: 001-12981 Rev. *E Page 35 of 44 [+] Feedback CY8CLED08 Figure 8-2. 48-Pin (300-Mil) SSOP 51-85061 *C Figure 8-3. 48-Pin (7x7 mm) QFN (Punched) TOP VIEW SIDE VIEW 0.08 6.90 7.10 6.70 6.80 N 1 2 0.80 DIA. 6.90 7.10 1.00 MAX. 0.05 MAX. 0.80 MAX. 0.20 REF. C BOTTOM VIEW 5.1 0.23±0.05 N PIN1 ID 0.20 R. 1 2 0.45 6.70 6.80 5.1 SOLDERABLE EXPOSED PAD 5.45 5.55 0.30-0.45 0°-12° C SEATING PLANE 5.45 5.55 0.50 0.42±0.18 (4X) NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED METAL. 2. REFERENCE JEDEC#: MO-220 3. PACKAGE WEIGHT: 0.13g 4. ALL DIMENSIONS ARE IN MM [MIN/MAX] 5. PACKAGE CODE PART # LF48A LY48A DESCRIPTION STANDARD LEAD FREE 001-12919 *B Document Number: 001-12981 Rev. *E Page 36 of 44 [+] Feedback CY8CLED08 Figure 8-4. 48-Pin (7x7x1.0 mm) QFN (Sawn) TOP VIEW SIDE VIEW 7.00±0.100 0.900±0.100 BOTTOM VIEW 48 1 PIN 1 DOT LASER MARK 37 36 0.200 REF. 0.25 +0.05 -0.07 5.100 REF 0.50 PITCH 37 36 PIN1 ID R 0.20 1 0.45 7.00±0.100 5.100 REF SOLDERABLE EXPOSED PAD 25 12 24 13 5.500±0.100 12 13 24 25 0.020 +0.025 -0.00 0.40±0.10 SEATING PLANE C NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED METAL. 2. REFERENCE JEDEC#: MO-220 3. PACKAGE WEIGHT: 0.13g 4. ALL DIMENSIONS ARE IN MILLIMETERS 0.08 5.500±0.100 001-13191 *E Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. Important Note Pinned vias for thermal conduction are not required for the low-power device. Document Number: 001-12981 Rev. *E Page 37 of 44 [+] Feedback CY8CLED08 8.1 Thermal Impedances Table 8-1. Thermal Impedances per Package Package Typical θJA[20] 48 SSOP 48 QFN[21] 28 SSOP 69 °C/W 18 °C/W 95 °C/W 8.2 Capacitance on Crystal Pins Table 8-2. Typical Package Capacitance on Crystal Pins Package 48 SSOP 48 QFN 28 SSOP Package Capacitance 3.3 pF 2.3 pF 2.8 pF 8.3 Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Table 8-3. Solder Reflow Peak Temperature Package Minimum Peak Temperature[22] Maximum Peak Temperature 48 SSOP 48 QFN 28 SSOP 220°C 240°C 240°C 260°C 260°C 260°C Notes 20. TJ = TA + POWER x θJA 21. To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane. 22. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5°C with Sn-Pb or 245 ± 5°C with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications. Document Number: 001-12981 Rev. *E Page 38 of 44 [+] Feedback CY8CLED08 9. Development Tool Selection This section presents the development tools available for all current PSoC based devices including the CY8CLED08 EZ-Color family. 9.3 Evaluation Tools All evaluation tools can be purchased from the Cypress Online Store. 9.3.1 CY3261A-RGB EZ-Color RGB Kit 9.1 Software Tools 9.1.1 PSoC Designer™ At the core of the PSoC development software suite is PSoC Designer, used to generate PSoC firmware applications. PSoC Designer is available free of charge at http://www.cypress.com/psocdesigner and includes a free C compiler. 9.1.2 PSoC Programmer Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free ofcharge at http://www.cypress.com/psocprogrammer. The CY3261A-RGB board is a preprogrammed HB LED color mix board with seven pre-set colors using the CY8CLED16 EZ-Color HB LED Controller. The board is accompanied by a CD containing the color selector software application, PSoC Designer, PSoC Programmer, and a suite of documents, schematics, and firmware examples. The color selector software application can be installed on a host PC and is used to control the EZ-Color HB LED controller using the included USB cable. The application enables you to select colors via a CIE 1931 chart or by entering coordinates. The kit includes: ■ ■ ■ ■ Training Board (CY8CLED16) One mini-A to mini-B USB Cable PSoC Designer CD-ROM Design Files and Application Installation CD-ROM 9.2 Hardware Tools 9.2.1 In-Circuit Emulator To program and tune this kit via PSoC Designer you must use a Mini Programmer Unit (CY3217 Kit) and a CY3240-I2CUSB kit. 9.3.2 CY3263-ColorLock Evaluation Board ■ A low cost, high functionality ICE (In-Circuit Emulator) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of the USB port. The base unit is universal and will operate with all PSoC based devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. 9.2.2 I2C to USB Bridge The I2C to USB Bridge is a quick and easy link from any design or application’s I2C bus to a PC via USB for design testing, debugging and communication. 9.2.3 PSoC Programmer Tools CD, which includes: ❐ PSoC Programmer ❐ .NET Framework 2.0 (for Windows 2000 and Windows XP) ❐ PSoC Designer ❐ ColorLock Express Pack ❐ CY3263-ColorLock EZ-Color Kit CD ❐ ColorLock Monitor Application ❐ Kit Documents (Quick Start, Kit Guide, Release Note, Application Note, Data Sheets, Schematics, and Layouts) ❐ Firmware Retractable USB Cable (A to Mini-B) PSoC MiniProg Programmer Power Supply Adapter ■ ■ ■ Flexible enough to be used on the bench in development, yet suitable for factory programming, PSoC Programmer works either as a standalone programming application or it can operate directly from PSoC Designer. PSoC Programmer software is compatible with both PSoC ICE-Cube In-Circuit Emulator and PSoC MiniProg. PSoC programmer is available free ofcharge at http://www.cypress.com/psocprogrammer. Document Number: 001-12981 Rev. *E Page 39 of 44 [+] Feedback CY8CLED08 9.3.3 CY3265-RGB EZ-Color Evaluation Kit 9.3.5 CY3210-PSoCEval1 The CY3265-RGB evaluation board demonstrates the ability of the EZ-Color device to use real-time temperature feedback to control three primary, high brightness LEDs and create accurate, mixed-color output. There are three variations of the kit available, depending on the LED manufacturer of the LEDs on the board: CY3265C-RGB (Cree LEDs), CY3265N-RGB (Nichia LEDs), or CY3265O-RGB (OSRAM LEDs). The kit includes: ■ ■ The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: ■ ■ ■ ■ ■ ■ Evaluation Board with LCD Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2) PSoC Designer Software CD Getting Started Guide USB 2.0 Cable CY3265C-RGB Evaluation Board Tools CD, which includes: ❐ PSoC Programmer ❐ PSoC Designer ❐ .NET Framework 2.0 (Windows XP 32 bit) Kit Documents (Quick Start, Kit Guide, Release Note, Application Note, Data Sheets, Schematics, and Layouts) Firmware Blue PCA Enclosure/Case 12V 1A Power Supply Retractable USB Cable (A to Mini-B) PSoC MiniProg Programmer Quick Start Guide ■ ■ ■ ■ ■ ■ 9.4 Device Programmers All device programmers can be purchased from the Cypress Online Store. 9.4.1 CY3216 Modular Programmer 9.3.4 CY3210-MiniProg1 The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes: ■ ■ ■ ■ ■ ■ The CY3210-MiniProg1 kit allows a user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes: ■ ■ ■ ■ ■ ■ ■ Modular Programmer Base 3 Programming Module Cards MiniProg Programming Unit PSoC Designer Software CD Getting Started Guide USB 2.0 Cable MiniProg Programming Unit MiniEval Socket Programming and Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software CD Getting Started Guide USB 2.0 Cable 9.4.2 CY3207ISSP In-System Serial Programmer (ISSP) The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production-programming environment. Note CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes: ■ ■ ■ ■ CY3207 Programmer Unit PSoC ISSP Software CD 110 ~ 240V Power Supply, Euro-Plug Adapter USB 2.0 Cable Document Number: 001-12981 Rev. *E Page 40 of 44 [+] Feedback CY8CLED08 9.5 Accessories (Emulation and Programming) Table 1. Emulation and Programming Accessories Part # Pin Package Flex-Pod Kit[23] Foot Kit[24] Adapter[25] CY8CLED08-48PVXI CY8CLED08-48LFXI/ CY8CLED08-48LTXI CY8CLED08-28PVXI 48 SSOP 48 QFN 28 SSOP CY3250-LED08 CY3250-LED08QFN CY3250-LED08 CY3250-48SSOP-FK CY3250-48QFN-FK CY3250-28SSOP-FK Adapters can be found at http://www.emulation.com. 9.6 Third Party Tools Several tools have been specially designed by the following third-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com under Design Support >> Development Kits/Boards. 9.7 Build a PSoC Emulator into Your Board For details on how to emulate your circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, see Application Note “Debugging - Build a PSoC Emulator into Your Board - AN2323”. Notes 23. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. 24. Foot kit includes surface mount feet that can be soldered to the target PCB. 25. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com. Document Number: 001-12981 Rev. *E Page 41 of 44 [+] Feedback CY8CLED08 10. Ordering Information 10.1 Key Device Features The following table lists the CY8CLED08 EZ-Color devices’ key package features and ordering codes. Table 2. Device Key Features and Ordering Information Analog Blocks (Columns of 3) Digital Blocks (Rows of 4) Switch Mode Pump Temperature Range Digital I/O Pins XRES Pin Analog Outputs Package Ordering Code 48 Pin (300 Mil) SSOP 48 Pin (300 Mil) SSOP (Tape and Reel) 48 Pin (7x7) QFN (Punched) 48 Pin (7x7) QFN (Tape and Reel) (Punched) 28 Pin (210 Mil) SSOP 28 Pin (210 Mil) SSOP (Tape and Reel) 48 Pin (7x7) QFN (Sawn) 48 Pin (7x7) QFN (Tape and Reel) (Sawn) CY8CLED08-48PVXI CY8CLED08-48PVXIT CY8CLED08-48LFXI CY8CLED08-48LFXIT CY8CLED08-28PVXI CY8CLED08-28PVXIT CY8CLED08-48LTXI CY8CLED08-48LTXIT 16K 16K 16K 16K 16K 16K 16K 16K 256 256 256 256 256 256 256 256 Yes Yes Yes Yes Yes Yes Yes Yes -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C 8 8 8 8 8 8 8 8 12 12 12 12 12 12 12 12 44 44 44 44 24 24 44 44 12 12 12 12 12 12 12 12 Analog Inputs Flash (Bytes) RAM (Bytes) 4 4 4 4 4 4 4 4 Yes Yes Yes Yes Yes Yes Yes Yes 10.2 Ordering Code Definitions CY 8 C LED xx - xx xxxx Package Type: Thermal Rating: PX = PDIP Pb-Free C = Commercial SX = SOIC Pb-Free I = Industrial PVX = SSOP Pb-Free E = Extended LFX/LKX = QFN Pb-Free AX = TQFP Pb-Free Pin Count Part Number LED Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress Document Number: 001-12981 Rev. *E Page 42 of 44 [+] Feedback CY8CLED08 11. Document History Page Document Title: CY8CLED08 EZ-ColorTM HB LED Controller Document Number: 001-12981 Revision ECN Orig. of Change Submission Date Description of Change ** *A *B *C 1148504 SFVTMP3 1391163 2763950 2794355 AESA DPT XBM 06/13/2007 See ECN 10/01/0209 10/28/2009 New document (revision **). Added 28 pin SSOP Added 48QFN package diagram (Sawn) Saw Marketing part number in ordering information. Added “Contents” on page 3 Updated “Development Tools” on page 7. Corrected FCPU1 and FCPU2 parameters in “AC Chip Level Specifications” on page 26. Corrected package diagram for 28-Pin (210-Mil) SSOP (Figure 8-1.) Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as follows: Replaced TRAMP (time) with SRPOWER_UP (slew rate) specification. Added note to Flash Endurance specification. Added IOH, IOL, DCILO, F32K_U, TPOWERUP, TERASEALL, TPROGRAM_HOT, and TPROGRAM_COLD specifications. Corrected the Pod Kit part numbers. Updated Development Tool Selection. Updated copyright and Sales, Solutions, and Legal Information URLs. Updated 28-Pin (210-Mil) SSOP package diagram. *D *E 2819954 2850593 CGX FRE 12/02/2009 01/14/2010 Document Number: 001-12981 Rev. *E Page 43 of 44 [+] Feedback CY8CLED08 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC® Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2007-2009, 2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-12981 Rev. *E Revised January 15, 2010 Page 44 of 44 PSoC Designer™ and EZ-Color™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All other products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback