CY8CLED16

CY8CLED16 EZ-Color™ HB-LED Controller Features ■ HB LED Controller ❐ Configurable Dimmers Support up to 16 Independent LED Channels ❐ 8 to 32 Bits of Resolution per Channel ❐ Dynamic Reconfiguration Enables LED Controller Plus Other Features: CapSense, Battery Charging, and Motor Control Visual Embedded Design ❐ LED-Based Drivers • Binning compensation • Temperature Feedback • Optical Feedback • DMX512 PrISM Modulation Technology ❐ Reduces Radiated EMI ❐ Reduces Low Frequency Blinking Powerful Harvard Architecture Processor ❐ M8C Processor Speeds to 24 MHz ❐ 3.0 to 5.25V Operating Voltage ❐ Operating Voltages Down to 1.0V using On-Chip Switch Mode Pump (SMP) ❐ Industrial Temperature Range: -40°C to +85°C Programmable Pin Configurations ❐ 25 mA Sink, 10 mA Source on all GPIO ❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on all GPIO ❐ Up to Eight Analog Inputs on GPIO ❐ Configurable Interrupt on all GPIO ■ ■ Advanced Peripherals (PSoC® Blocks) ❐ 16 Digital PSoC Blocks Provide: • 8 to 32-Bit Timers, Counters, and PWMs • Up to 4 Full-Duplex UARTs • Multiple SPI Masters or Slaves • Connectable to all GPIO Pins ❐ 12 Rail-to-Rail Analog PSoC Blocks Provide: • Up to 14-Bit ADCs • Up to 9-Bit DACs • Programmable Gain Amplifiers • Programmable Filters and Comparators ❐ Complex Peripherals by Combining Blocks Flexible On-Chip Memory ❐ 32K Flash Program Storage 50,000 Erase/Write Cycles ❐ 2K SRAM Data Storage ❐ In-System Serial Programming (ISSP) ❐ Partial Flash Updates ❐ Flexible Protection Modes ❐ EEPROM Emulation in Flash Complete Development Tools ❐ Free Development Software • PSoC Designer™ ❐ Full-Featured, In-Circuit Emulator and Programmer ❐ Full Speed Emulation ❐ Complex Breakpoint Structure ❐ 128 KBytes Trace Memory ■ ■ ■ ■ ■ EZ-Color HB LED Controller Preliminary Data Sheet Cypress Semiconductor Corporation Document Number: 001-13105 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised January 15, 2010 [+] Feedback CY8CLED16 Logic Block Diagram Analog Drivers Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 SYSTEM BUS Global Digital Interconnect SRAM 2K Interrupt Controller Global Analog Interconnect Flash 32K SROM PSoC CORE Sleep and Watchdog CPU Core (M8C) Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) DIGITAL SYSTEM Digital Block Array ANALOG SYSTEM Analog Ref. Analog Block Array Analog Input Muxing Digital Clocks Two Multiply Accums. POR and LVD Decimator I 2C System Resets Internal Voltage Ref. Switch Mode Pump SYSTEM RESOURCES Document Number: 001-13105 Rev. *C Page 2 of 43 [+] Feedback CY8CLED16 Contents EZ-Color™ Functional Overview....................................... 4 Target Applications........................................................ 4 The PSoC Core ............................................................. 4 The Digital System ........................................................ 4 The Analog System ....................................................... 5 Additional System Resources ....................................... 6 EZ-Color Device Characteristics ................................... 6 Getting Started.................................................................... 6 Application Notes .......................................................... 6 Development Kits .......................................................... 6 Training ......................................................................... 6 Cypros Consultants ....................................................... 6 Solutions Library............................................................ 6 Technical Support ......................................................... 6 Development Tools ............................................................ 7 PSoC Designer Software Subsystems.......................... 7 In-Circuit Emulator......................................................... 7 Document Conventions ..................................................... 8 Acronyms Used ............................................................. 8 Units of Measure ........................................................... 8 Numeric Naming............................................................ 8 Pin Information ................................................................... 9 Pinouts .......................................................................... 9 Register Reference........................................................... 12 Register Conventions .................................................. 12 Register Mapping Tables ............................................ 12 Electrical Specifications ................................................... 15 Absolute Maximum Ratings.......................................... 16 Operating Temperature ................................................ 16 DC Electrical Characteristics........................................ 17 AC Electrical Characteristics ........................................ 27 Packaging Information...................................................... 36 Packaging Dimensions................................................. 36 Thermal Impedances.................................................... 38 Capacitance on Crystal Pins ........................................ 38 Solder Reflow Peak Temperature ................................ 38 Development Tool Selection ............................................ 39 Software ........................................................................39 Evaluation Tools........................................................... 39 Device Programmers.................................................... 40 Accessories (Emulation and Programming) ................. 40 Third Party Tools .......................................................... 40 Build a PSoC Emulator into Your Board....................... 40 Ordering Information......................................................... 41 Key Device Features .................................................... 41 Ordering Code Definitions ............................................ 41 Document History Page .................................................... 42 Sales, Solutions, and Legal Information ......................... 43 Worldwide Sales and Design Support.......................... 43 Products ....................................................................... 43 Document Number: 001-13105 Rev. *C Page 3 of 43 [+] Feedback CY8CLED16 EZ-Color™ Functional Overview Cypress's EZ-Color family of devices offers the ideal control solution for High Brightness LED applications requiring intelligent dimming control. EZ-Color devices combine the power and flexibility of PSoC (Programmable System-on-Chip); with Cypress's PrISM (precise illumination signal modulation) modulation technology providing lighting designers a fully customizable and integrated lighting solution platform. The EZ-Color family supports a range of independent LED channels from 4 channels at 32 bits of resolution each, up to 16 channels at 8 bits of resolution each. This enables lighting designers the flexibility to choose the LED array size and color quality. PSoC Designer software, with lighting specific drivers, can significantly cut development time and simplify implementation of fixed color points through temperature, optical, and LED binning compensation. EZ-Color's virtually limitless analog and digital customization allow for simple integration of features in addition to intelligent lighting, such as Battery Charging, Image Stabilization, and Motor Control during the development process. These features, along with Cypress' best-in-class quality and design support, make EZ-Color the ideal choice for intelligent HB LED control applications. to 2.5% over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for use by the digital system. A low power 32 kHz ILO (internal low speed oscillator) is provided for the Sleep timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the EZ-Color device. EZ-Color GPIOs provide connection to the CPU, digital and analog resources of the device. Each pin’s drive mode may be selected from eight options, allowing great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. The Digital System The Digital System is composed of 16 digital PSoC blocks. Each block is an 8-bit resource that can be used alone or combined with other blocks to form 8, 16, 24, and 32-bit peripherals, which are called user module references. Digital peripheral configurations include those listed below. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Target Applications ■ ■ ■ ■ ■ ■ PrISM (8 to 32 bit) PWMs (8 to 32 bit) PWMs with Dead band (8 to 32 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) UART 8 bit with selectable parity (up to 4) SPI master and slave (up to 4 each) I2C slave and multi-master (1 available as a System Resource) Cyclical Redundancy Checker/Generator (8 to 32 bit) IrDA (up to 4) Generators (8 to 32 bit) LCD Backlight Large Signs General Lighting Architectural Lighting Camera/Cell Phone Flash Flashlights The PSoC Core The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose I/O). The M8C CPU core is a powerful processor with speeds up to 48 MHz, providing a four MIPS 8-bit Harvard architecture microprocessor. The CPU utilizes an interrupt controller with 25 vectors, to simplify programming of real time embedded events. Program execution is timed and protected using the included Sleep and Watch Dog Timers (WDT). Memory encompasses 32 KB of Flash for program storage, 2 KB of SRAM for data storage, and up to 2 KB of EEPROM emulated using the Flash. Program Flash utilizes four protection levels on blocks of 64 bytes, allowing customized software IP protection. The EZ-Color family incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also allow for signal multiplexing and for performing logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Digital blocks are provided in rows of four, where the number of blocks varies by EZ-Color device family. This allows you the optimum choice of system resources for your application. Family resources are shown in Table 1, “EZ-Color Device Characteristics,” on page 6. Document Number: 001-13105 Rev. *C Page 4 of 43 [+] Feedback CY8CLED16 Figure 1. Digital System Block Diagram Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 ■ ■ ■ DTMF Dialer Modulators Correlators Peak Detectors Many other topologies possible Digital Clocks From Core To System Bus To Analog System ■ ■ DIGITAL SYSTEM Digital PSoC Block Array Row Input Configuration Analog blocks are provided in columns of three, which includes one CT (Continuous Time) and two SC (Switched Capacitor) blocks, as shown in the figure below. 4 Row 0 DBB00 DBB01 DCB02 Figure 2. Analog System Block Diagram P0[7] 8 Row Output Configuration DCB03 4 P0[6] P0[4] P0[2] P0[0] AGNDIn RefIn P2[6] 8 8 Row Input Configuration P0[5] 8 Row 1 DBB10 DBB11 DCB12 4 DCB13 4 Row Output Configuration P0[3] P0[1] Row Input Configuration Row 2 DBB20 DBB21 DCB22 4 DCB23 4 P2[3] Row Output Configuration P2[4] P2[2] P2[0] P2[1] Row Input Configuration Row 3 DBB30 DBB31 DCB32 4 DCB33 4 Row Output Configuration GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] Array Input Configuration ACI0[1:0] ACI1[1:0] ACI2[1:0] ACI3[1:0] The Analog System The Analog System is composed of 12 configurable blocks, each comprised of an opamp circuit allowing the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common EZ-Color analog functions (most available as user modules) are listed below. ■ ■ ■ ■ ■ ■ ■ ■ ■ Block Array ACB00 ASC10 ASD20 ACB01 ASD11 ASC21 ACB02 ASC12 ASD22 ACB03 ASD13 ASC23 Analog-to-digital converters (up to 4, with 6- to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR) Filters (2, 4, 6, or 8 pole band-pass, low-pass, and notch) Amplifiers (up to 4, with selectable gain to 48x) Instrumentation amplifiers (up to 2, with selectable gain to 93x) Comparators (up to 4, with 16 selectable thresholds) DACs (up to 4, with 6- to 9-bit resolution) Multiplying DACs (up to 4, with 6- to 9-bit resolution) High current output drivers (four with 40 mA drive as a Core Resource) 1.3V reference (as a System Resource) Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 001-13105 Rev. *C Page 5 of 43 [+] Feedback CY8CLED16 Additional System Resources System Resources, some of which have been previously listed, provide additional capability useful to complete systems. Resources include a multiplier, decimator, switch mode pump, low voltage detection, and power on reset. Statements describing the merits of each system resource are presented below. ■ ■ The decimator provides a custom hardware filter for digital signal, processing applications including the creation of Delta Sigma ADCs. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are all supported. Low Voltage Detection (LVD) interrupts can signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3 voltage reference provides an absolute reference for the analog system, including ADCs and DACs. An integrated switch mode pump (SMP) generates normal operating voltages from a single 1.2V battery cell, providing a low cost boost converter. ■ ■ Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks can be generated using digital PSoC blocks as clock dividers. Multiply accumulate (MAC) provides fast 8-bit multiplier with 32-bit accumulate, to assist in general math and digital filters. ■ ■ ■ EZ-Color Device Characteristics Depending on your EZ-Color device characteristics, the digital and analog systems can have 16, 8, or 4 digital blocks and 12, 6, or 4 analog blocks. The following table lists the resources available for specific EZ-Color device groups. The device covered by this data sheet is shown in the highlighted row of the table. Table 1. EZ-Color Device Characteristics CapSense No Yes No No Page 6 of 43 [+] Feedback LED Channels Analog Columns Analog Outputs Analog Inputs Analog Blocks Digital Blocks Digital I/O Digital Rows SRAM Size Part Number CY8CLED02 CY8CLED04 CY8CLED08 CY8CLED16 2 4 8 16 16 56 44 44 1 1 2 4 4 4 8 16 8 48 12 12 0 2 4 4 2 2 4 4 4 6 12 12 256 Bytes 1K 256 Bytes 2K Getting Started The quickest way to understand the device is to read this data sheet and then use the PSoC Designer Integrated Development Environment (IDE). This data sheet is an overview of the EZ-Color integrated circuit and presents specific pin, register, and electrical specifications. For in depth information, along with detailed programming information, see the PSoC Programmable System-on-Chip Technical Reference Manual. For up-to-date ordering, packaging, and electrical specification information, see the latest device data sheets on the web at http://www.cypress.com/ez-color. Training Free technical training (on demand, webinars, and workshops) is available online at www.cypress.com/training. The training covers a wide variety of topics and skill levels to assist you in your designs. Cypros Consultants Certified PSoC Consultants offer everything from technical assistance to completed designs. To contact or become a PSoC Consultant go to www.cypress.com/cypros. Solutions Library Visit our growing library of solution focused designs at www.cypress.com/solutions. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. Application Notes A long list of application notes will assist you in every aspect of your design effort. To view the application notes, go to the http://www.cypress.com web site and select Application Notes under the Documentation tab. Technical Support For assistance with technical issues, search KnowledgeBase articles and forums at www.cypress.com/support. If you cannot find an answer to your question, call technical support at 1-800-541-4736. Development Kits Development Kits are available from the following distributors: Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store contains development kits, C compilers, and all accessories for PSoC development. Go to the Cypress Online Store web site at http://www.cypress.com/store, click Lighting & Power Control to view a current list of available items. Document Number: 001-13105 Rev. *C Flash Size 4K 16K 16K 32K CY8CLED16 Development Tools PSoC Designer is a Microsoft® Windows-based, integrated development environment for the Programmable System-on-Chip (PSoC) devices. The PSoC Designer IDE runs on Windows XP or Windows Vista. This system provides design database management by project, an integrated debugger with In-Circuit Emulator, in-system programming support, and built-in support for third-party assemblers and C compilers. PSoC Designer also supports C language compilers developed specifically for the devices in the PSoC family. Code Generation Tools PSoC Designer supports multiple third party C compilers and assemblers. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range of debugging tools. The choice is yours. Assemblers. The assemblers allow assembly code to merge seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all the features of C tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger The PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow the designer to read and program and read and write data memory, read and write I/O registers, read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also allows the designer to create a trace buffer of registers and memory locations of interest. Online Help System The online help system displays online, context-sensitive help for the user. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer in getting started. PSoC Designer Software Subsystems System Level View A drag-and-drop visual embedded system design environment based on PSoC Designer. In the system level view you create a model of your system inputs, outputs, and communication interfaces. You define when and how an output device changes state based upon any or all other system devices. Based upon the design, PSoC Designer automatically selects one or more PSoC Mixed-Signal Controllers that match your system requirements. PSoC Designer generates all embedded code, then compiles and links it into a programming file for a specific PSoC device. Chip Level View The chip-level view is a more traditional Integrated Development Environment (IDE) based on PSoC Designer. Choose a base device to work with and then select different onboard analog and digital components called user modules that use the PSoC blocks. Examples of user modules are ADCs, DACs, Amplifiers, and Filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The device editor also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic configuration allows for changing configurations at run time. Hybrid Designs You can begin in the system-level view, allow it to choose and configure your user modules, routing, and generate code, then switch to the chip-level view to gain complete control over on-chip resources. All views of the project share a common code editor, builder, and common debug, emulation, and programming tools. In-Circuit Emulator A low cost, high functionality In-Circuit Emulator (ICE) is available for development support. This hardware has the capability to program single devices. The emulator consists of a base unit that connects to the PC by way of a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full speed (24 MHz) operation. Document Number: 001-13105 Rev. *C Page 7 of 43 [+] Feedback CY8CLED16 Document Conventions Acronyms Used The following table lists the acronyms that are used in this document. Acronym AC ADC API CPU CT DAC DC ECO EEPROM FSR GPIO GUI HBM ICE ILO IMO I/O IPOR LSb LVD MSb PC PLL POR PPOR PSoC® PWM SC SLIMO SMP SRAM alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current external crystal oscillator electrically erasable programmable read-only memory full scale range general purpose I/O graphical user interface human body model in-circuit emulator internal low speed oscillator internal main oscillator input/output imprecise power on reset least-significant bit low voltage detect most-significant bit program counter phase-locked loop power on reset precision power on reset Programmable System-on-Chip pulse width modulator switched capacitor slow IMO switch mode pump static random access memory Description Units of Measure A units of measure table is located in the Electrical Specifications section. Table 7 on page 15 lists all the abbreviations used to measure the devices. Numeric Naming Hexadecimal numbers are represented with all letters in uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or ‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’ prefix, the C coding convention. Binary numbers have an appended lowercase ‘b’ (e.g., 01010100b’ or ‘01000011b’). Numbers not indicated by an ‘h’, ‘b’, or 0x are decimal. Document Number: 001-13105 Rev. *C Page 8 of 43 [+] Feedback CY8CLED16 Pin Information Pinouts The CY8CLED16 device is available in three packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, SMP, and XRES are not capable of Digital I/O. 28-Pin Part Pinout Table 2. 28-Pin Part Pinout (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Type Digital Analog I/O I I/O I/O I/O I/O I/O I I/O I/O I/O I I/O I Power I/O I/O I/O I/O Power I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O Power I I Pin Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] SMP P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Description Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Figure 3. 28-Pin Device A, I, P0[7] A, IO, P0[5] A, IO, P0[3] A, I, P0[1] P2[7] P2[5] A, I, A, I, P2[3] P2[1] SMP I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss Direct switched capacitor block input. Direct switched capacitor block input. Switch Mode Pump (SMP) connection to external components required. I2C Serial Clock (SCL). I2C Serial Data (SDA). Crystal (XTALin), I2C Serial Clock (SCL), ISSP-SCLK[1]. Ground connection. Crystal (XTALout), I2C Serial Data (SDA), ISSP-SDATA[1]. Optional External Clock Input (EXTCLK). Active high external reset with internal pull down. Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VREF). Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6], External VREF P2[4], External AGND P2[2], A, I P2[0], A, I XRES P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA I I/O I/O I LEGEND: A = Analog, I = Input, and O = Output. Note 1. These are the ISSP pins, which are not High Z at POR. Document Number: 001-13105 Rev. *C Page 9 of 43 [+] Feedback CY8CLED16 48-Pin Part Pinouts Table 3. 48-Pin Part Pinout (SSOP) Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 Type Digital Analog I/O I I/O I/O I/O I/O I/O I I/O I/O I/O I I/O I I/O I/O I/O I/O Power I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Pin Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd Description Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Figure 4. 48-Pin Device A, I, P0[7] A, IO, P0[5] A, IO, P0[3] A, I, P0[1] P2[7] P2[5] A, I, P2[3] A, I, P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Direct switched capacitor block input. Direct switched capacitor block input. SSOP Switch Mode Pump (SMP) connection to external components required. I2C Serial Clock (SCL). I2C Serial Data (SDA). Crystal (XTALin), I2C Serial Clock (SCL), ISSP-SCLK[1]. Ground connection. Crystal (XTALout), I2C Serial Data (SDA), ISSP-SDATA[1]. Optional External Clock Input (EXTCLK). 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 Vdd P0[6], A, I P0[4], A, IO P0[2], A, IO P0[0], A, I P2[6], External VREF P2[4], External AGND P2[2], A, I P2[0], A, I P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] P5[2] P5[0] P1[6] P1[4], EXTCLK P1[2] P1[0], XTALout, I2C SDA Active high external reset with internal pull down. I I I I/O I/O I Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VREF). Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. LEGEND: A = Analog, I = Input, and O = Output. Document Number: 001-13105 Rev. *C Page 10 of 43 [+] Feedback CY8CLED16 Table 4. 48-Pin Part Pinout (QFN)[2] Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power I I/O I/O I I I/O I/O I I I I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power Type Digital I/O I/O I/O I/O I/O I/O Power Analog I I Pin Name P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Vdd P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VREF). Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Supply voltage. Analog column mux input. Analog column mux input and column output. Analog column mux input and column output. Analog column mux input. Active high external reset with internal pull down. Optional External Clock Input (EXTCLK). Crystal (XTALin), I2C Serial Clock (SCL), ISSP-SCLK[1]. Ground connection. Crystal (XTALout), I2C Serial Data (SDA), ISSP-SDATA[1]. I2C Serial Clock (SCL). I2C Serial Data (SDA). I2C SCL, XTALin, P1[1] Vss I2C SDA, XTALout, P1[0] P1[2] EXTCLK, P1[4] P1[6] P5[1] I2C SCL, P1[7] I2C SDA, P1[5] P1[3] P5[0] P5[2] Description Direct switched capacitor block input. Direct switched capacitor block input. Figure 5. 48-Pin Device P0[0], A, I P2[6], External VREF 38 37 36 35 34 33 32 31 30 29 28 27 26 25 P2[4], External AGND P2[2], A, I P2[0], A, I P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] P0[3], A, IO P0[5], A, IO P0[7], A, I 45 44 43 48 47 46 Switch Mode Pump (SMP) connection to external components required. 13 14 15 16 LEGEND: A = Analog, I = Input, and O = Output. Note 2. The center pad on the QFN package should be connected to ground (Vss) for best mechanical, thermal, and electrical performance. If not connected to ground, it should be electrically floated and not connected to any other signal. Document Number: 001-13105 Rev. *C 17 18 19 20 21 22 23 24 A, I, P2[3] A, I, P2[1] P4[7] P4[5] P4[3] P4[1] SMP P3[7] P3[5] P3[3] P3[1] P5[3] 1 2 3 4 5 6 MLF (Top View) 7 8 9 10 11 12 42 41 40 39 Vdd P0[6], A, I P0[4], A, IO P0[2], A, IO P2[5] P2[7] P0[1], A, I Page 11 of 43 [+] Feedback CY8CLED16 Register Reference Register Conventions Abbreviations Used The register conventions specific to this section are listed in the following table. Convention R W L C # Description Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific Register Mapping Tables This chapter lists the registers of the CY8CLED16 EZ-Color device. The device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1. Note In the following register mapping tables, blank fields are reserved and should not be accessed. Table 5. Register Map Bank 0 Table: User Space Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 PRT6DR PRT6IE PRT6GS PRT6DM2 PRT7DR PRT7IE PRT7GS PRT7DM2 DBB00DR0 DBB00DR1 DBB00DR2 DBB00CR0 DBB01DR0 DBB01DR1 Addr (0,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # W RW # # W Name DBB20DR0 DBB20DR1 DBB20DR2 DBB20CR0 DBB21DR0 DBB21DR1 DBB21DR2 DBB21CR0 DCB22DR0 DCB22DR1 DCB22DR2 DCB22CR0 DCB23DR0 DCB23DR1 DCB23DR2 DCB23CR0 DBB30DR0 DBB30DR1 DBB30DR2 DBB30CR0 DBB31DR0 DBB31DR1 DBB31DR2 DBB31CR0 DCB32DR0 DCB32DR1 DCB32DR2 DCB32CR0 DCB33DR0 DCB33DR1 DCB33DR2 DCB33CR0 AMX_IN Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D Access # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # RW Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 Acces RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI3RI RDI3SYN RDI3IS RDI3LT0 RDI3LT1 RDI3RO0 RDI3RO1 CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED Acces RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W RC RC RW RW W W R R RW RW ARF_CR CMP_CR0 ASY_CR RW # # RW DBB01DR2 26 RW CMP_CR1 DBB01CR0 27 # DCB02DR0 28 # DCB02DR1 29 W DCB02DR2 2A RW DCB02CR0 2B # DCB03DR0 2C # TMP_DR0 DCB03DR1 2D W TMP_DR1 Blank fields are Reserved and should not be accessed. RW RW A6 A7 MUL1_X A8 MUL1_Y A9 MUL1_DH AA MUL1_DL AB ACC1_DR1 AC ACC1_DR0 AD # Access is bit specific. W W R R RW RW Document Number: 001-13105 Rev. *C Page 12 of 43 [+] Feedback CY8CLED16 Table 5. Register Map Bank 0 Table: User Space (continued) Name Addr (0,Hex) Access Name DCB03DR2 2E RW TMP_DR2 DCB03CR0 2F # TMP_DR3 DBB10DR0 30 # ACB00CR3 DBB10DR1 31 W ACB00CR0 DBB10DR2 32 RW ACB00CR1 DBB10CR0 33 # ACB00CR2 DBB11DR0 34 # ACB01CR3 DBB11DR1 35 W ACB01CR0 DBB11DR2 36 RW ACB01CR1 DBB11CR0 37 # ACB01CR2 DCB12DR0 38 # ACB02CR3 DCB12DR1 39 W ACB02CR0 DCB12DR2 3A RW ACB02CR1 DCB12CR0 3B # ACB02CR2 DCB13DR0 3C # ACB03CR3 DCB13DR1 3D W ACB03CR0 DCB13DR2 3E RW ACB03CR1 DCB13CR0 3F # ACB03CR2 Blank fields are Reserved and should not be accessed. Addr (0,Hex) 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Addr (0,Hex) AE AF B0 B1 B2 B3 B4 B5 B6 B7 RDI1RI B8 RDI1SYN B9 RDI1IS BA RDI1LT0 BB RDI1LT1 BC RDI1RO0 BD RDI1RO1 BE BF # Access is bit specific. Name ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 Acces Name RW ACC0_DR3 RW ACC0_DR2 RW RW RW RW RW RW RW CPU_F RW RW RW RW RW RW RW CPU_SCR1 CPU_SCR0 Addr (0,Hex) EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Acces RW RW RL # # Table 6. Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 PRT6DM0 PRT6DM1 PRT6IC0 PRT6IC1 PRT7DM0 PRT7DM1 PRT7IC0 PRT7IC1 DBB00FN DBB00IN DBB00OU DBB01FN DBB01IN DBB01OU DCB02FN DCB02IN Addr(1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 RW RW RW RW RW AMD_CR1 ALT_CR0 ALT_CR1 CLK_CR2 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 DCB33FN DCB33IN DCB33OU DCB32FN DCB32IN DCB32OU DBB31FN DBB31IN DBB31OU DBB30FN DBB30IN DBB30OU DCB23FN DCB23IN DCB23OU DCB22FN DCB22IN DCB22OU DBB21FN DBB21IN DBB21OU Name DBB20FN DBB20IN DBB20OU Addr(1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Access RW RW RW Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 Addr(1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 # Access is bit specific. DEC_CR2 IMO_TR ILO_TR Acces s RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU RDI3RI RDI3SYN RDI3IS RDI3LT0 RDI3LT1 RDI3RO0 RDI3RO1 Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 Addr(1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 RW W W RW RW RW RW RW RW RW R RW RW RW RW RW RW RW RW RW RW RW Acces s RW RW RW RW RW RW RW Blank fields are Reserved and should not be accessed. Document Number: 001-13105 Rev. *C Page 13 of 43 [+] Feedback CY8CLED16 Table 6. Register Map Bank 1 Table: Configuration Space (continued) Name DCB02OU DCB03FN DCB03IN DCB03OU DBB10FN DBB10IN DBB10OU DBB11FN DBB11IN DBB11OU DCB12FN DCB12IN DCB12OU DCB13FN DCB13IN DCB13OU Addr(1,Hex) 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 ACB02CR3 ACB02CR0 ACB02CR1 ACB02CR2 ACB03CR3 ACB03CR0 ACB03CR1 ACB03CR2 Access RW Name Addr(1,Hex) 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 Access Name Addr(1,Hex) AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 BA BB BC BD BE BF # Access is bit specific. RW RW RW RW RW RW RW CPU_SCR1 CPU_SCR0 FLS_PR1 RW RW RW RW RW RW RW CPU_F Acces s Name BDG_TR ECO_TR Addr(1,Hex) EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF # # RW RL Acces s RW W Blank fields are Reserved and should not be accessed. Document Number: 001-13105 Rev. *C Page 14 of 43 [+] Feedback CY8CLED16 Electrical Specifications This section presents the DC and AC electrical specifications of the CY8CLED16 EZ-Color device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com/ez-color. Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted. Refer to Table 21 for the electrical specifications on the internal main oscillator (IMO) using SLIMO mode. Figure 6. Voltage versus CPU Frequency, and IMO Frequency Trim Options SLIMO Mode=1 4.75 Vdd Voltage 3.00 93 kHz CPU Frequency 4.75 Vdd Voltage SLIMO Mode = 0 5.25 5.25 SLIMO Mode=0 The following table lists the units of measure that are used in this chapter. Table 7. Units of Measure Symbol oC dB fF Hz KB Kbit kHz kΩ MHz MΩ μA μF μH μs μV μVrms Unit of Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square Symbol μW mA ms mV nA ns nV Ω pA pF pp ppm ps sps σ V Unit of Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts ohm picoampere picofarad peak-to-peak parts per million picosecond samples per second sigma: one standard deviation volts Document Number: 001-13105 Rev. *C lid ng Va rati n e io Op Reg 12 MHz 24 MHz 3.60 SLIMO Mode=1 SLIMO Mode=0 3.00 93 kHz 6 MHz IMO Frequency 12 MHz 24 MHz Page 15 of 43 [+] Feedback CY8CLED16 Absolute Maximum Ratings Symbol TSTG Description Storage Temperature Min -55 Typ 25 Max +100 Units oC Notes Higher storage temperatures will reduce data retention time. Recommended storage temperature is +25oC ± 25oC. Extended duration storage temperatures above 65oC will degrade reliability. TA Vdd VIO VIOZ IMIO IMAIO ESD LU Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tri-state Maximum Current into any Port Pin Maximum Current into any Port Pin Configured as Analog Driver Electro Static Discharge Voltage Latch up Current -40 -0.5 Vss 0.5 Vss 0.5 -25 -50 2000 – – – – – – – – – +85 +6.0 Vdd + 0.5 Vdd + 0.5 +50 +50 – 200 o C V V V mA mA V mA Human Body Model ESD. Operating Temperature Symbol TA TJ Description Ambient Temperature Junction Temperature Min -40 -40 Typ – – Max +85 +100 Units oC oC Notes The temperature rise from ambient to junction is package specific. See “Thermal Impedances per Package” on page 38. The user must limit the power consumption to comply with this requirement. Document Number: 001-13105 Rev. *C Page 16 of 43 [+] Feedback CY8CLED16 DC Electrical Characteristics DC Chip Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 8. DC Chip Level Specifications Symbol Vdd IDD Description Supply Voltage Supply Current Min 3.00 – Typ – 8 Max 5.25 14 Units V mA Notes See DC POR and LVD specifications, Table 3-15 on page 27. Conditions are 5.0V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz. Conditions are Vdd = 3.3V, TA = 25 oC, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz. Conditions are Vdd = 3.3V, TA = 25 o C, CPU = 0.75 MHz, SYSCLK doubler disabled, VC1 = 0.375 MHz, VC2 = 23.44 kHz, VC3 = 0.09 kHz. Conditions are with internal slow speed oscillator, Vdd = 3.3V, -40 oC ≤ TA ≤ 55 oC. Conditions are with internal slow speed oscillator, Vdd = 3.3V, 55 oC < TA ≤ 85 oC. Conditions are with properly loaded, 1 μW max, 32.768 kHz crystal. Vdd = 3.3V, -40 oC ≤ TA ≤ 55 oC. Conditions are with properly loaded, 1 μW max, 32.768 kHz crystal. Vdd = 3.3V, 55 oC < TA ≤ 85 oC. Trimmed for appropriate Vdd. IDD3 Supply Current – 5 9 mA IDDP Supply current when IMO = 6 MHz using SLIMO mode. – 2 3 mA ISB ISBH ISBXTL ISBXTLH VREF Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and internal slow oscillator active. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, internal slow oscillator, and 32 kHz crystal oscillator active. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, and 32 kHz crystal oscillator active. Reference Voltage (Bandgap) – 3 10 μA μA μA μA – 4 25 – 4 12 – 5 27 1.28 1.3 1.32 V Document Number: 001-13105 Rev. *C Page 17 of 43 [+] Feedback CY8CLED16 DC General Purpose I/O Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 9. DC GPIO Specifications Symbol RPU RPD VOH Description Pull up Resistor Pull down Resistor High Output Level Min 4 4 Vdd 1.0 Typ 5.6 5.6 – Max 8 8 – Units kΩ kΩ V Notes VOL Low Output Level – – 0.75 V IOH IOL VIL VIH VH IIL CIN COUT High Level Source Current Low Level Sink Current Input Low Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output 10 25 – 2.1 – – – – – – – – 60 1 3.5 3.5 – – 0.8 – – 10 10 mA mA V V mV nA pF pF IOH = 10 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget. IOL = 25 mA, Vdd = 4.75 to 5.25V (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 150 mA maximum combined IOL budget. VOH = Vdd-1.0V. See the limitations of the total current in the Note for VOH. VOL = 0.75V. See the limitations of the total current in the Note for VOL. Vdd = 3.0 to 5.25. Vdd = 3.0 to 5.25. Gross tested to 1 μA. Package and pin dependent. Temp = 25oC. Package and pin dependent. Temp = 25oC. Document Number: 001-13105 Rev. *C Page 18 of 43 [+] Feedback CY8CLED16 DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 10. 5V DC Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Min – – – – – – 0.0 0.5 60 80 Vdd - .01 – – – – – – – 67 Typ 1.6 1.3 1.2 7.0 200 4.5 – – – – – – 150 300 600 1200 2400 4600 80 Max 10 8 7.5 35.0 – 9.5 Vdd Vdd - 0.5 – – – 0.1 200 400 800 1600 3200 6400 – Units mV mV mV μV/oC pA pF V V dB dB V V μA μA μA μA μA μA dB Gross tested to 1 μA. Package and pin dependent. Temp = 25 oC. Notes TCVOSOA Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) IEBOA CINOA Input Capacitance (Port 0 Analog Pins) VCMOA Common Mode Voltage Range. All Cases, except highest. Power = High, Opamp Bias = High CMRROA Common Mode Rejection Ratio GOLOA Open Loop Gain VOHIGHO High Output Voltage Swing (internal signals) A VOLOWOA Low Output Voltage Swing (internal signals) Supply Current (including associated AGND buffer) ISOA Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High PSRROA Supply Voltage Rejection Ratio Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤ VIN ≤ Vdd. Document Number: 001-13105 Rev. *C Page 19 of 43 [+] Feedback CY8CLED16 Table 11. 3.3V DC Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = High High Power is 5 Volts Only Average Input Offset Voltage Drift Input Leakage Current (Port 0 Analog Pins) Input Capacitance (Port 0 Analog Pins) Min – – – – – Typ 1.65 1.32 7.0 200 4.5 Max 10 8 35.0 – 9.5 Units mV mV μV/oC pA pF Gross tested to 1 μA. Package and pin dependent. Temp = 25 o C. Notes TCVOSOA IEBOA CINOA VCMOA CMRROA GOLOA VOLOWOA ISOA Common Mode Voltage Range Common Mode Rejection Ratio Open Loop Gain Low Output Voltage Swing (internal signals) Supply Current (including associated AGND buffer) Power = Low, Opamp Bias = Low Power = Low, Opamp Bias = High Power = Medium, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = Low Power = High, Opamp Bias = High Supply Voltage Rejection Ratio 0 60 80 Vdd - .01 – – – – – – – 54 – – – – – 150 300 600 1200 2400 – 80 Vdd – – – .01 200 400 800 1600 3200 – – V dB dB V V μA μA μA μA μA Not Allowed dB Vss ≤ VIN ≤ (Vdd - 2.25) or (Vdd - 1.25V) ≤ VIN ≤ Vdd VOHIGHOA High Output Voltage Swing (internal signals) PSRROA DC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 12. DC Low Power Comparator Specifications Symbol VREFLPC ISLPC VOSLPC Description Low power comparator (LPC) reference voltage range LPC supply current LPC voltage offset Min 0.2 – – Typ – 10 2.5 Max Vdd - 1 40 30 Units V μA mV Notes Document Number: 001-13105 Rev. *C Page 20 of 43 [+] Feedback CY8CLED16 DC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 13. 5V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High High Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High Supply Current Including Bias Cell (No Load) Power = Low Power = High Supply Voltage Rejection Ratio Min – – 0.5 – – 0.5 x Vdd + 1.3 0.5 x Vdd + 1.3 Typ 3 +6 – – – – – Max 12 – Vdd - 1.0 1 1 – – Units mV μV/°C V W W V V Notes VOHIGHOB VOLOWOB – – – – 0.5 x Vdd - 1.3 0.5 x Vdd - 1.3 V V ISOB PSRROB – – 40 1.1 2.6 64 2 5 – mA mA dB Table 14. 3.3V DC Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB VOHIGHOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High High Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High Low Output Voltage Swing (Load = 1k ohms to Vdd/2) Power = Low Power = High Supply Current Including Bias Cell (No Load) Power = Low Power = High Supply Voltage Rejection Ratio Min – – 0.5 – – 0.5 x Vdd + 1.0 0.5 x Vdd + 1.0 Typ 3 +6 – – – – Max 12 – Vdd - 1.0 10 10 – – Units mV μV/°C V W W V V Notes VOLOWOB – – – – 0.5 x Vdd - 1.0 0.5 x Vdd - 1.0 V V ISOB PSRROB – 60 0.8 2.0 64 1 5 – mA mA dB Document Number: 001-13105 Rev. *C Page 21 of 43 [+] Feedback CY8CLED16 DC Switch Mode Pump Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 15. DC Switch Mode Pump (SMP) Specifications Symbol Description Min Typ Max Units Notes VPUMP 5V VPUMP 3V IPUMP VBAT5V VBAT3V VBATSTART ΔVPUMP_Line 5V Output Voltage at Vdd from Pump 4.75 5.0 5.25 V Configuration of footnote.[3] Average, neglecting ripple. SMP trip voltage is set to 5.0V. Configuration of footnote.[3] Average, neglecting ripple. SMP trip voltage is set to 3.25V. Configuration of footnote.[3] SMP trip voltage is set to 3.25V. SMP trip voltage is set to 5.0V. Configuration of footnote.[3] SMP trip voltage is set to 5.0V. Configuration of footnote.[3] SMP trip voltage is set to 3.25V. Configuration of footnote.[3] 0oC ≤ TA ≤ 100. 1.25V at TA = -40oC. Configuration of footnote.[3] VO is the “Vdd Value for PUMP Trip” specified by the VM[2:0] setting in Table 19, “DC POR, SMP, and LVD Specifications,” on page 25. Configuration of footnote.[3] VO is the “Vdd Value for PUMP Trip” specified by the VM[2:0] setting in Table 19, “DC POR, SMP, and LVD Specifications,” on page 25. Configuration of footnote.[3] Load is 5 mA. Configuration of footnote.[3] Load is 5 mA. SMP trip voltage is set to 3.25V. 3V Output Voltage at Vdd from Pump 3.00 3.25 3.60 V Available Output Current VBAT = 1.5V, VPUMP = 3.25V VBAT = 1.8V, VPUMP = 5.0V Input Voltage Range from Battery Input Voltage Range from Battery Minimum Input Voltage from Battery to Start Pump Line Regulation (over VBAT range) 8 5 1.8 1.0 1.2 – – – – – – 5 – – 5.0 3.3 – – mA mA V V V %VO ΔVPUMP_Load Load Regulation – 5 – %VO ΔVPUMP_Rippl Output Voltage Ripple (depends on capacitor/load) e E3 Efficiency – 35 100 50 – – mVpp % FPUMP DCPUMP Switching Frequency Switching Duty Cycle – – 1.4 50 – – MHz % Note 3. L1 = 2 mH inductor, C1 = 10 mF capacitor, D1 = Schottky diode. See Figure 7. Document Number: 001-13105 Rev. *C Page 22 of 43 [+] Feedback CY8CLED16 Figure 7. Basic Switch Mode Pump Circuit D1 Vdd V PUMP L1 V BAT C1 SMP + Battery EZ-Color Vss DC Analog Reference Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high. Table 16. 5V DC Analog Reference Specifications Symbol Description VBG5 Bandgap Voltage Reference 5V – AGND = Vdd/2[4] – – – – – – – – – – AGND = 2 x BandGap[4] AGND = P2[4] (P2[4] = Vdd/2)[4] AGND = BandGap[4] AGND = 1.6 x BandGap[4] AGND Block to Block Variation (AGND = Vdd/2)[4] RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 1.3V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) Min 1.28 Vdd/2 0.02 2.52 P2[4] 0.013 1.27 2.03 -0.034 Vdd/2 + 1.21 3.75 P2[6] + 2.478 P2[4] + 1.218 P2[4] + P2[6] 0.058 2.50 4.02 Vdd/2 1.369 Typ Max 1.30 1.32 Vdd/2 Vdd/2 + 0.02 2.60 2.72 P2[4] P2[4] + 0.013 1.3 1.34 2.08 2.13 0.000 0.034 Vdd/2 + Vdd/2 + 1.3 1.382 3.9 4.05 P2[6] + P2[6] + 2.6 2.722 P2[4] + P2[4] + 1.3 1.382 P2[4] + P2[4] + P2[6] P2[6] + 0.058 2.60 2.70 4.16 4.29 Vdd/2 - Vdd/2 1.30 1.231 Units V V V V V V V V V V V V – – – RefHi = 2 x BandGap RefHi = 3.2 x BandGap RefLo = Vdd/2 – BandGap V V V Document Number: 001-13105 Rev. *C Page 23 of 43 [+] Feedback CY8CLED16 Table 16. 5V DC Analog Reference Specifications (continued) Symbol Description – RefLo = BandGap – RefLo = 2 x BandGap - P2[6] (P2[6] = 1.3V) – – RefLo = P2[4] – BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 1.3V) Min 1.20 2.489 P2[6] P2[4] 1.368 P2[4] P2[6] 0.042 Typ Max 1.30 1.40 2.6 - 2.711 P2[6] P2[6] P2[4] - P2[4] 1.30 1.232 P2[4] - P2[4] P2[6] P2[6] + 0.042 Units V V V V Table 17. 3.3V DC Analog Reference Specifications Symbol VBG33 – – – – – – – – – – – Description Bandgap Voltage Reference 3.3V AGND = Vdd/2[4] AGND = 2 x BandGap[4] AGND = P2[4] (P2[4] = Vdd/2) AGND = BandGap[4] AGND = 1.6 x BandGap[4] AGND Block to Block Variation (AGND = Vdd/2)[4] RefHi = Vdd/2 + BandGap RefHi = 3 x BandGap RefHi = 2 x BandGap + P2[6] (P2[6] = 0.5V) RefHi = P2[4] + BandGap (P2[4] = Vdd/2) RefHi = P2[4] + P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) Min Typ 1.28 1.30 Vdd/2 - Vdd/2 0.02 Not Allowed P2[4] - P2[4] 0.009 1.27 1.30 2.03 2.08 -0.034 0.000 Not Allowed Not Allowed Not Allowed Not Allowed P2[4] + P2[4] + P2[6] - P2[6] 0.042 2.50 2.60 Not Allowed Not Allowed Not Allowed Not Allowed Not Allowed P2[4] - P2[4] P2[6] - P2[6] 0.036 Max 1.32 Vdd/2 + 0.02 P2[4] + 0.009 1.34 2.13 0.034 Units V V V V V mV – – – – – – – RefHi = 2 x BandGap RefHi = 3.2 x BandGap RefLo = Vdd/2 - BandGap RefLo = BandGap RefLo = 2 x BandGap - P2[6] (P2[6] = 0.5V) RefLo = P2[4] – BandGap (P2[4] = Vdd/2) RefLo = P2[4]-P2[6] (P2[4] = Vdd/2, P2[6] = 0.5V) P2[4] + V P2[6] + 0.042 2.70 V P2[4] - V P2[6] + 0.036 Note 4. AGND tolerance includes the offsets of the local buffer in the PSoC block. Bandgap voltage is 1.3V ± 0.02V. Document Number: 001-13105 Rev. *C Page 24 of 43 [+] Feedback CY8CLED16 DC Analog PSoC Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 18. DC Analog PSoC Block Specifications Symbol RCT CSC Description Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switched Capacitor) Min – – Typ 12.2 80 Max – – Units kΩ fF Notes DC POR, SMP, and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 19. DC POR, SMP, and LVD Specifications Symbol VPPOR0R VPPOR1R VPPOR2R VPPOR0 VPPOR1 VPPOR2 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Description Vdd Value for PPOR Trip (positive ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for PPOR Trip (negative ramp) PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b PPOR Hysteresis PORLEV[1:0] = 00b PORLEV[1:0] = 01b PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Vdd Value for SMP Trip VM[2:0] = 000b VM[2:0] = 001b VM[2:0] = 010b VM[2:0] = 011b VM[2:0] = 100b VM[2:0] = 101b VM[2:0] = 110b VM[2:0] = 111b Min Typ 2.91 4.39 4.55 2.82 4.39 4.55 92 0 0 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 Max Units V V V V V V mV mV mV V V V V V V V V V V V V V V V V V V Notes – – – – – – – 2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 – – – 2.98[5] 3.08 3.20 4.08 4.57 4.74[6] 4.82 4.91 VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 2.96 3.03 3.18 4.11 4.55 4.63 4.72 4.90 3.02 3.10 3.25 4.19 4.64 4.73 4.82 5.00 3.08 3.16 3.32 4.28 4.74 4.82 4.91 5.10 Notes 5. Always greater than 50 mV above PPOR (PORLEV = 00) for falling supply. 6. Always greater than 50 mV above PPOR (PORLEV = 10) for falling supply. Document Number: 001-13105 Rev. *C Page 25 of 43 [+] Feedback CY8CLED16 DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 20. DC Programming Specifications Symbol IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR Description Min Supply Current During Programming or – Verify Input Low Voltage During Programming or – Verify Input High Voltage During Programming or 2.2 Verify Input Current when Applying Vilp to P1[0] or – P1[1] During Programming or Verify Input Current when Applying Vihp to P1[0] or – P1[1] During Programming or Verify Output Low Voltage During Programming or – Verify Output High Voltage During Programming or Vdd - 1.0 Verify Flash Endurance (per block) 50,000[7] [8] Flash Endurance (total) 1,800,00 0 Flash Data Retention 10 Typ 10 – – – – – – – – – Max 30 0.8 – 0.2 1.5 Vss + 0.75 Vdd – – – Units mA V V mA mA V V – – Years Erase/write cycles per block. Erase/write cycles. Driving internal pull down resistor. Driving internal pull down resistor. Notes Notes 7. The 50,000 cycle Flash endurance per block will only be guaranteed if the Flash is operating within one voltage range. Voltage ranges are 3.0V to 3.6V and 4.75V to 5.25V. 8. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. Document Number: 001-13105 Rev. *C Page 26 of 43 [+] Feedback CY8CLED16 AC Electrical Characteristics AC Chip Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Note See the individual user module data sheets for information on maximum frequencies for user modules. Table 21. AC Chip Level Specifications Symbol FIMO24 Description Min Internal Main Oscillator Frequency for 24 23.4 MHz Typ 24 Max Units 24.6[9,10,11] MHz Notes Trimmed for 5V or 3.3V operation using factory trim values. See the figure on page 19. SLIMO Mode = 0. Trimmed for 5V or 3.3V operation using factory trim values. See the figure on page 19. SLIMO Mode = 1. FIMO6 Internal Main Oscillator Frequency for 6 5.5 MHz 6 6.5[9,10,11] MHz FCPU1 FCPU2 F48M F24M F32K1 F32K_U CPU Frequency (5V Nominal) CPU Frequency (3.3V Nominal) Digital PSoC Block Frequency 0.093 0.093 0 24 12 48 24 32 – 24.6[9,10] 12.3[10,11] 49.2[9,10,12] 24.6[10,12] 64 – MHz MHz MHz MHz kHz kHz Refer to the AC Digital Block Specifications below. Digital PSoC Block Frequency 0 Internal Low Speed Oscillator Frequency 15 Internal Low Speed Oscillator Untrimmed 5 Frequency After a reset and before the m8c starts to run, the ILO is not trimmed. See the System Resets section of the PSoC Technical Reference Manual for details on timing this. Accuracy is capacitor and crystal dependent. 50% duty cycle. A multiple (x732) of crystal frequency. DCILO F32K2 FPLL Jitter24M2 TPLLSLEW TPLLSLEWL OW Internal Low Speed Oscillator Duty Cycle 20 External Crystal Oscillator – PLL Frequency 24 MHz Period Jitter (PLL) PLL Lock Time PLL Lock Time for Low Gain Setting – – 0.5 0.5 50 32.768 – 23.986 – – – – 250 300 600 10 50 500 600 80 % kHz MHz ps ms ms ms ms TOS TOSACC External Crystal Oscillator Startup to 1% – External Crystal Oscillator Startup to 100 – ppm The crystal oscillator frequency is within 100 ppm of its final value by the end of the Tosacc period. Correct operation assumes a properly loaded 1 μW maximum drive level 32.768 kHz crystal. 3.0V ≤ Vdd ≤ 5.5V, -40 oC ≤ TA ≤ 85 oC. Jitter32k TXRST DC24M 32 kHz Period Jitter External Reset Pulse Width 24 MHz Duty Cycle – 10 40 100 – 50 – 60 ns μs % Notes 9. 4.75V < Vdd < 5.25V. 10. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 11. 3.0V < Vdd < 3.6V. See Application Note AN2012 “Adjusting PSoC Microcontroller Trims for Dual Voltage-Range Operation” for information on trimming for operation at 3.3V. 12. See the individual user module data sheets for information on maximum frequencies for user modules Document Number: 001-13105 Rev. *C Page 27 of 43 [+] Feedback CY8CLED16 Table 21. AC Chip Level Specifications (continued) Symbol Step24M Fout48M Jitter24M1 FMAX SRPOWER_ UP Description 24 MHz Trim Step Size 48 MHz Output Frequency 24 MHz Period Jitter (IMO) Maximum frequency of signal on row input or row output. Power Supply Slew Rate Time from End of POR to CPU Executing Code Min – 46.8 – – – – Typ 50 48.0 600 – – 16 Max – 49.2[9, 11] Units kHz MHz ps MHz V/ms ms Notes Trimmed. Utilizing factory trim values. 12.3 250 100 Vdd slew rate during power up. Power up from 0V. See the System Resets section of the PSoC Technical Reference Manual. TPOWERUP Figure 8. PLL Lock Timing Diagram PLL Enable TPLLSLEW 24 MHz FPLL PLL Gain 0 Figure 9. PLL Lock for Low Gain Setting Timing Diagram PLL Enable TPLLSLEWLOW 24 MHz FPLL PLL Gain 1 Figure 10. External Crystal Oscillator Startup Timing Diagram 32K Select TOS 32 kHz F32K2 Figure 11. 24 MHz Period Jitter (IMO) Timing Diagram Jitter24M1 F 24M Document Number: 001-13105 Rev. *C Page 28 of 43 [+] Feedback CY8CLED16 Figure 12. 32 kHz Period Jitter (ECO) Timing Diagram Jitter32k F 32K2 AC General Purpose I/O Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 22. AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF Min 0 3 2 10 10 – – – 27 22 Typ Max 12.3 18 18 – – Units MHz ns ns ns ns Notes Normal Strong Mode Vdd = 4.75 to 5.25V, 10% - 90% Vdd = 4.75 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Vdd = 3 to 5.25V, 10% - 90% Figure 13. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS Document Number: 001-13105 Rev. *C Page 29 of 43 [+] Feedback CY8CLED16 AC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Power = High and Opamp Bias = High is not supported at 3.3V. Table 23. 5V AC Operational Amplifier Specifications Symbol TROA Description Rising Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Falling Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Falling Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Noise at 1 kHz (Power = Medium, Opamp Bias = High) Min – – – – – – 0.15 1.7 6.5 0.01 0.5 4.0 0.75 3.1 5.4 – – – – – – – – – – – – – – – – 100 Typ Max 3.9 0.72 0.62 5.9 0.92 0.72 – – – – – – – – – – Units μs μs μs μs μs μs V/μs V/μs V/μs V/μs V/μs V/μs MHz MHz MHz nV/rt-Hz Notes TSOA SRROA SRFOA BWOA ENOA Table 24. 3.3V AC Operational Amplifier Specifications Symbol TROA TSOA SRROA SRFOA BWOA ENOA Description Rising Settling Time to 0.1% of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Falling Settling Time to 0.1% of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Falling Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Noise at 1 kHz (Power = Medium, Opamp Bias = High) Min – – – – 0.31 2.7 0.24 1.8 0.67 2.8 – – – – – – – – – – – 100 Typ Max 3.92 0.72 5.41 0.72 – – – – – – – Units μs μs μs μs V/μs V/μs V/μs V/μs MHz MHz nV/rt-Hz Notes Document Number: 001-13105 Rev. *C Page 30 of 43 [+] Feedback CY8CLED16 When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor. Figure 14. Typical AGND Noise with P2[4] Bypass dBV/rtHz 10000 0 0.01 0.1 1.0 10 1000 100 0.001 0.01 0.1 Freq (kHz) 1 10 100 At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level. Figure 15. Typical Opamp Noise nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000 100 10 0.001 0.01 0.1 Freq (kHz) 1 10 100 Document Number: 001-13105 Rev. *C Page 31 of 43 [+] Feedback CY8CLED16 AC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, or 2.4V to 3.0V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 25. AC Low Power Comparator Specifications Symbol TRLPC Description LPC response time Min – – Typ Max 50 Units μs Notes ≥ 50 mV overdrive comparator reference set within VREFLPC. AC Digital Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 26. AC Digital Block Specifications Function All Functions Description Maximum Block Clocking Frequency (> 4.75V) Maximum Block Clocking Frequency (< 4.75V) Timer Capture Pulse Width Maximum Frequency, No Capture Maximum Frequency, With Capture Counter Enable Pulse Width Maximum Frequency, No Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS (PRS Mode) CRCPRS (CRC Mode) SPIM SPIS Maximum Input Clock Frequency Maximum Input Clock Frequency Maximum Input Clock Frequency Maximum Input Clock Frequency Width of SS_ Negated Between Transmissions Transmitter Maximum Input Clock Frequency Vdd ≥ 4.75V, 2 Stop Bits 20 50[13] 50[13] – – – – – 50 – – Receiver Maximum Input Clock Frequency Vdd ≥ 4.75V, 2 Stop Bits – – [13] Min Typ Max 49.2 24.6 Units MHz MHz ns MHz MHz ns MHz MHz ns ns ns MHz MHz MHz MHz ns ns MHz MHz MHz MHz Notes 4.75V < Vdd < 5.25V. 3.0V < Vdd < 4.75V. 50[13] – – 50[13] – – – – – – – – – – – – – – – – – – – – – – 49.2 24.6 – 49.2 24.6 – – – 49.2 49.2 24.6 8.2 4.1 – 24.6 49.2 24.6 49.2 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. 4.75V < Vdd < 5.25V. Maximum data rate at 4.1 MHz due to 2 x over clocking. Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. Maximum data rate at 3.08 MHz due to 8 x over clocking. Maximum data rate at 6.15 MHz due to 8 x over clocking. Note 13. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). Document Number: 001-13105 Rev. *C Page 32 of 43 [+] Feedback CY8CLED16 AC Analog Output Buffer Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 27. 5V AC Analog Output Buffer Specifications Symbol Description TROB Rising Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High TSOB Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High SRROB Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High Min – – – – Typ 4 4 Max Units μs μs μs μs V/μs V/μs V/μs V/μs Notes – – – – 3.4 3.4 0.5 0.5 – – – – 0.55 0.55 – – – – 0.8 0.8 – – – – MHz MHz 300 300 – – – – kHz kHz Table 28. 3.3V AC Analog Output Buffer Specifications Symbol Description TROB Rising Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High TSOB Falling Settling Time to 0.1%, 1V Step, 100pF Load Power = Low Power = High SRROB Rising Slew Rate (20% to 80%), 1V Step, 100pF Load Power = Low Power = High SRFOB Falling Slew Rate (80% to 20%), 1V Step, 100pF Load Power = Low Power = High BWOB Small Signal Bandwidth, 20mVpp, 3dB BW, 100pF Load Power = Low Power = High BWOB Large Signal Bandwidth, 1Vpp, 3dB BW, 100pF Load Power = Low Power = High 200 200 – – – – kHz kHz Min – – – – Typ Max 4.7 4.7 Units μs μs μs μs V/μs V/μs V/μs V/μs Notes – – – – 4 4 .36 .36 – – – – .4 .4 – – – – 0.7 0.7 – – – – MHz MHz Document Number: 001-13105 Rev. *C Page 33 of 43 [+] Feedback CY8CLED16 AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 29. 5V AC External Clock Specifications Symbol FOSCEXT – – – Frequency High Period Low Period Power Up IMO to Switch Description Min 0.093 20.6 20.6 150 – – – – Typ Max 24.6 5300 – – Units MHz ns ns μs Notes Table 30. 3.3V AC External Clock Specifications Symbol FOSCEXT Description Frequency with CPU Clock Divide by 1 Min 0.093 – Typ Max 12.3 Units MHz Notes Maximum CPU frequency is 12 MHz at 3.3V. With the CPU clock divider set to 1, the external clock must adhere to the maximum frequency and duty cycle requirements. If the frequency of the external clock is greater than 12 MHz, the CPU clock divider must be set to 2 or greater. In this case, the CPU clock divider will ensure that the fifty percent duty cycle requirement is met. FOSCEXT Frequency with CPU Clock Divide by 2 or Greater 0.186 – 24.6 MHz – – – High Period with CPU Clock Divide 41.7 by 1 Low Period with CPU Clock Divide 41.7 by 1 Power Up IMO to Switch 150 – – – 5300 – – ns ns μs AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 31. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 Description Rise Time of SCLK Fall Time of SCLK Data Set up Time to Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time 1 1 40 0 – – Min – – – – – 10 40 – – – 80 Typ Max 20 20 – – 8 – – 45 50 – Units ns ns ns ns MHz ms ms ns ns ms Vdd > 3.6 3.0 ≤ Vdd ≤ 3.6 Erase all blocks and protection fields at once. Notes Data Hold Time from Falling Edge of SCLK 40 Data Out Delay from Falling Edge of SCLK – Data Out Delay from Falling Edge of SCLK – TERASEALL Flash Erase Time (Bulk) Note 14. For the full industrial range, the user must employ a Temperature Sensor User Module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. Document Number: 001-13105 Rev. *C Page 34 of 43 [+] Feedback CY8CLED16 Table 31. AC Programming Specifications (continued) TPROGRAM_ Flash Block Erase + Flash Block Write Time HOT – – – – 100[14] ms 200[14] ms 0°C ≤ TJ ≤ 100°C -40°C ≤ TJ ≤ 0°C TPROGRAM_ Flash Block Erase + Flash Block Write Time COLD AC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C ≤ TA ≤ 85°C, or 3.0V to 3.6V and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V and 3.3V at 25°C and are for design guidance only. Table 32. AC Characteristics of the I2C SDA and SCL Pins Standard-Mode Fast-Mode Min Max Min Max 0 100 0 400 FSCLI2C SCL Clock Frequency THDSTAI Hold Time (repeated) START Condition. After 4.0 – 0.6 – this period, the first clock pulse is generated. 2C TLOWI2C LOW Period of the SCL Clock 4.7 – 1.3 – THIGHI2 HIGH Period of the SCL Clock 4.0 – 0.6 – Symbol Description C Units kHz μs μs μs μs μs ns μs μs ns Notes TSUSTAI 2C THDDATI 2C TSUDATI 2C Set-up Time for a Repeated START Condition 4.7 Data Hold Time Data Set-up Time Set-up Time for STOP Condition 0 250 4.0 – – – – – – 0.6 0 100[15] 0.6 1.3 0 – – – – – 50 TSUSTOI 2C TBUFI2C TSPI2C Bus Free Time Between a STOP and START 4.7 Condition Pulse Width of spikes are suppressed by the – input filter. Figure 16. Definition for Timing for Fast-/Standard-Mode on the I2C Bus SDA TLOWI2C TSUDATI2C THDSTAI2C TSPI2C TBUFI2C SCL S THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C Sr P S Note 15. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT ≥ 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released. Document Number: 001-13105 Rev. *C Page 35 of 43 [+] Feedback CY8CLED16 Packaging Information This section illustrates the packaging specifications for the CY8CLED16 EZ-Color device, along with the thermal impedances for each package and the typical package capacitance on crystal pins. Important Note Emulation tools may require a larger area on the target PCB than the chip’s footprint. For a detailed description of the emulation tools’ dimensions, refer to the document titled PSoC Emulator Pod Dimensions at http://www.cypress.com/design/MR10161. Packaging Dimensions Figure 0-1. 28-Pin (210-Mil) SSOP 51-85079 *D Document Number: 001-13105 Rev. *C Page 36 of 43 [+] Feedback CY8CLED16 Figure 17. 48-Pin (300-Mil) SSOP 51-85061-C 51-85061 *C Figure 18. 48-Pin (7x7 mm) QFN (Punched) TOP VIEW SIDE VIEW 0.08 6.90 7.10 6.70 6.80 N 1 2 0.80 DIA. 6.90 7.10 1.00 MAX. 0.05 MAX. 0.80 MAX. 0.20 REF. C BOTTOM VIEW 5.1 0.23±0.05 N PIN1 ID 0.20 R. 1 2 0.45 6.70 6.80 5.1 SOLDERABLE EXPOSED PAD 5.45 5.55 0.30-0.45 0°-12° C SEATING PLANE 5.45 5.55 0.50 0.42±0.18 (4X) NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED METAL. 2. REFERENCE JEDEC#: MO-220 3. PACKAGE WEIGHT: 0.13g 4. ALL DIMENSIONS ARE IN MM [MIN/MAX] 5. PACKAGE CODE PART # LF48A LY48A DESCRIPTION STANDARD LEAD FREE 001-12919 *B Document Number: 001-13105 Rev. *C Page 37 of 43 [+] Feedback CY8CLED16 Figure 19. 48-Pin (7x7x1.0 mm) QFN (Sawn) TOP VIEW SIDE VIEW 7.00±0.100 0.900±0.100 BOTTOM VIEW 48 1 PIN 1 DOT LASER MARK 37 36 0.200 REF. 0.25 +0.05 -0.07 5.100 REF 0.50 PITCH 37 36 PIN1 ID R 0.20 1 0.45 7.00±0.100 5.100 REF SOLDERABLE EXPOSED PAD 25 12 24 13 5.500±0.100 12 13 24 25 0.020 +0.025 -0.00 0.40±0.10 SEATING PLANE C NOTES: 1. HATCH AREA IS SOLDERABLE EXPOSED METAL. 2. REFERENCE JEDEC#: MO-220 3. PACKAGE WEIGHT: 0.13g 4. ALL DIMENSIONS ARE IN MILLIMETERS 0.08 5.500±0.100 001-13191 *E Important Note For information on the preferred dimensions for mounting QFN packages, see the following Application Note at http://www.amkor.com/products/notes_papers/MLFAppNote.pdf. Important Note Pinned vias for thermal conduction are not required for the low-power device. Thermal Impedances Table 33. Thermal Impedances per Package Package 28 SSOP 48 SSOP 48 QFN[17] Typical θJA [16] 94 oC/W 69 oC/W 28 oC/W Solder Reflow Peak Temperature Following is the minimum solder reflow peak temperature to achieve good solderability. Table 35. Solder Reflow Peak Temperature Package 28 SSOP Minimum Peak Temperature[18] 240oC 220oC 220oC Maximum Peak Temperature 260oC 260oC 260oC Capacitance on Crystal Pins Table 34. Typical Package Capacitance on Crystal Pins Package 28 SSOP 48 SSOP 48 QFN Package Capacitance 2.8 pF 3.3 pF 1.8 pF 48 SSOP 48 QFN Notes 16. TJ = TA + POWER x θJA 17. To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane. 18. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu paste. Refer to the solder manufacturer specifications Document Number: 001-13105 Rev. *C Page 38 of 43 [+] Feedback CY8CLED16 Development Tool Selection Software PSoC Designer™ At the core of the PSoC development software suite is PSoC Designer, used to generate PSoC firmware applications. PSoC Designer is available free of charge at http://www.cypress.com/psocdesigner and includes a free C compiler. PSoC Programmer PSoC Programmer is flexible and used on the bench in development. It is also suitable for factory programming. PSoC Programmer works either as a standalone programming application or operates directly from PSoC Designer. PSoC Programmer software is compatible with both PSoC ICE Cube In-Circuit Emulator and PSoC MiniProg. It is available free of charge at http://www.cypress.com/psocprogrammer. CY3265-RGB EZ-Color Evaluation Kit The CY3265-RGB evaluation board demonstrates the ability of the EZ-Color device to use real-time temperature feedback to control three primary, high brightness LEDs and create accurate, mixed-color output. There are three variations of the kit available, depending on the LED manufacturer of the LEDs on the board: CY3265C-RGB (Cree LEDs), CY3265N-RGB (Nichia LEDs), or CY3265O-RGB (OSRAM LEDs). The kit includes: ■ ■ CY3265C-RGB Evaluation Board Tools CD, which includes: ❐ PSoC Programmer ❐ PSoC Designer ❐ .NET Framework 2.0 (Windows XP 32 bit) Kit Documents (Quick Start, Kit Guide, Release Note, Application Note, Data Sheets, Schematics, and Layouts) Firmware Blue PCA Enclosure/Case 12V 1A Power Supply Retractable USB Cable (A to Mini-B) PSoC MiniProg Programmer Quick Start Guide ■ ■ ■ ■ ■ ■ Evaluation Tools All evaluation tools are sold at the Cypress Online Store. CY3261A-RGB EZ-Color RGB Kit The CY3261A-RGB board is a preprogrammed HB LED color mix board with seven pre-set colors using the CY8CLED16 EZ-Color HB LED Controller. The board is accompanied by a CD containing the color selector software application, PSoC Designer, PSoC Programmer, and a suite of documents, schematics, and firmware examples. The color selector software application can be installed on a host PC and is used to control the EZ-Color HB LED controller using the included USB cable. The application enables you to select colors via a CIE 1931 chart or by entering coordinates. The kit includes: ■ ■ ■ ■ CY3210-MiniProg1 The CY3210-MiniProg1 kit enables the user to program PSoC devices via the MiniProg1 programming unit. The MiniProg is a small, compact prototyping programmer that connects to the PC via a provided USB 2.0 cable. The kit includes: ■ ■ ■ ■ ■ ■ ■ MiniProg Programming Unit MiniEval Socket Programming and Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software CD Getting Started Guide USB 2.0 Cable Training Board (CY8CLED16) One mini-A to mini-B USB Cable PSoC Designer CD-ROM Design Files and Application Installation CD-ROM To program and tune this kit via PSoC Designer you must use a Mini Programmer Unit (CY3217 Kit) and a CY3240-I2CUSB kit. CY3263-ColorLock Evaluation Board ■ Tools CD, which includes: ❐ PSoC Programmer ❐ .NET Framework 2.0 (for Windows 2000 and Windows XP) ❐ PSoC Designer ❐ ColorLock Express Pack ❐ CY3263-ColorLock EZ-Color Kit CD ❐ ColorLock Monitor Application ❐ Kit Documents (Quick Start, Kit Guide, Release Note, Application Note, Data Sheets, Schematics, and Layouts) ❐ Firmware Retractable USB Cable (A to Mini-B) PSoC MiniProg Programmer Power Supply Adapter CY3210-PSoCEval1 The CY3210-PSoCEval1 kit features an evaluation board and the MiniProg1 programming unit. The evaluation board includes an LCD module, potentiometer, LEDs, and plenty of breadboarding space to meet all of your evaluation needs. The kit includes: ■ ■ ■ ■ ■ ■ Evaluation Board with LCD Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2) PSoC Designer Software CD Getting Started Guide USB 2.0 Cable ■ ■ ■ Document Number: 001-13105 Rev. *C Page 39 of 43 [+] Feedback CY8CLED16 Device Programmers All device programmers are purchased from the Cypress Online Store. CY3216 Modular Programmer The CY3216 Modular Programmer kit features a modular programmer and the MiniProg1 programming unit. The modular programmer includes three programming module cards and supports multiple Cypress products. The kit includes: ■ ■ ■ ■ ■ ■ CY3207ISSP In-System Serial Programmer (ISSP) The CY3207ISSP is a production programmer. It includes protection circuitry and an industrial case that is more robust than the MiniProg in a production programming environment. Note that CY3207ISSP needs special software and is not compatible with PSoC Programmer. The kit includes: ■ ■ ■ ■ CY3207 Programmer Unit PSoC ISSP Software CD 110 ~ 240V Power Supply, Euro-Plug Adapter USB 2.0 Cable Modular Programmer Base Three Programming Module Cards MiniProg Programming Unit PSoC Designer Software CD Getting Started Guide USB 2.0 Cable Accessories (Emulation and Programming) Table 36. Emulation and Programming Accessories Part No. CY8CLED16-28PVXI CY8CLED16-48PVXI CY8CLED16-48LFXI Pin Package 28 SSOP 48 SSOP 48 QFN Flex-Pod Kit[19] CY3250-LED16 CY3250-LED16 CY3250-LED16QFN Foot Kit[20] Adapter[21] CY3250-28SSOP-FK Adapters can be found at CY3250-48SSOP-FK http://www.emulation.com. CY3250-48QFN-FK Third Party Tools Several tools have been specially designed by the following third-party vendors to accompany PSoC devices during development and production. Specific details for each of these tools can be found at http://www.cypress.com under Design Support >> Development Kits/Boards. Build a PSoC Emulator into Your Board For details on emulating the circuit before going to volume production using an on-chip debug (OCD) non-production PSoC device, refer to application note AN2323 “Build a PSoC Emulator into Your Board”. Notes 19. Flex-Pod kit includes a practice flex-pod and a practice PCB, in addition to two flex-pods. 20. Foot kit includes surface mount feet that can be soldered to the target PCB. 21. Programming adapter converts non-DIP package to DIP footprint. Specific details and ordering information for each of the adapters can be found at http://www.emulation.com. Document Number: 001-13105 Rev. *C Page 40 of 43 [+] Feedback CY8CLED16 Ordering Information Key Device Features The following table lists the CY8CLED16 EZ-Color devices’ key package features and ordering codes. Table 37. Device Key Features and Ordering Information Analog PSoC Blocks Switch Mode Pump Temperature Range Digital PSoC Blocks Digital I/O Pins XRES Pin Ordering Code Package Analog Outputs Flash (Bytes) RAM (Bytes) Analog Inputs 28 Pin (210 Mil) SSOP 28 Pin (210 Mil) SSOP (Tape and Reel) 48 Pin (300 Mil) SSOP 48 Pin (300 Mil) SSOP (Tape and Reel) 48 Pin QFN (Punched) 48 Pin QFN (Tape and Reel) (Punched) 48 Pin QFN (Sawn) 48 Pin QFN (Tape and Reel) (Sawn) CY8CLED16-28PVXI CY8CLED16-28PVXIT CY8CLED16-48PVXI CY8CLED16-48PVXIT CY8CLED16-48LFXI CY8CLED16-48LFXIT CY8CLED16-48LTXI CY8CLED16-48LTXIT 32K 32K 32K 32K 32K 32K 32K 32K 2K 2K 2K 2K 2K 2K 2K 2K Yes Yes Yes Yes Yes Yes Yes Yes -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C 16 16 16 16 16 16 16 16 12 12 12 12 12 12 12 12 24 24 44 44 44 44 44 44 12 12 12 12 12 12 12 12 4 4 4 4 4 4 4 4 Yes Yes Yes Yes Yes Yes Yes Yes Ordering Code Definitions CY 8 C LED xx - xx xxxx Package Type: Thermal Rating: PX = PDIP Pb-Free C = Commercial SX = SOIC Pb-Free I = Industrial PVX = SSOP Pb-Free E = Extended LFX/LKX = QFN Pb-Free AX = TQFP Pb-Free Pin Count Part Number LED Family Code Technology Code: C = CMOS Marketing Code: 8 = Cypress PSoC Company ID: CY = Cypress Document Number: 001-13105 Rev. *C Page 41 of 43 [+] Feedback CY8CLED16 Document History Page Document Title: CY8CLED16 EZ-Color™ HB LED Controller Document Number: 001-13105 Revision ** *A *B ECN No 1148504 2763950 2794355 Origin of Change SFVTMP3 DPT XBM Submission Date See ECN 09/29/2009 10/28/2009 Description of Change New document (revision **). Added 48QFN package diagram (Sawn). Added Saw Marketing part number in ordering information. Added “Contents” on page 3 Updated “Development Tools” on page 7. Corrected FCPU1 and FCPU2 parameters in “AC Chip Level Specifications” on page 27. Updated DC GPIO, AC Chip-Level, and AC Programming Specifications as follows: Replaced TRAMP (time) with SRPOWER_UP (slew rate) specification. Added note to Flash Endurance specification. Added IOH, IOL, DCILO, F32K_U, TPOWERUP, TERASEALL, TPROGRAM_HOT, and TPROGRAM_COLD specifications. Corrected the Pod Kit part numbers. Updated Development Tool Selection. Updated copyright and Sales, Solutions, and Legal Information URLs. Updated 28-Pin SSOP 48-Pin QFN (Punched), 48-Pin QFN (Sawn) package diagrams. Removed Preliminary for Final status. *C 2850593 FRE 01/14/2010 Document Number: 001-13105 Rev. *C Page 42 of 43 [+] Feedback CY8CLED16 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control Memory Optical & Image Sensing PSoC Touch Sensing USB Controllers Wireless/RF cypress.com/go/automotive cypress.com/go/clocks cypress.com/go/interface cypress.com/go/powerpsoc cypress.com/go/plc cypress.com/go/memory cypress.com/go/image cypress.com/go/psoc cypress.com/go/touch cypress.com/go/USB cypress.com/go/wireless PSoC® Solutions psoc.cypress.com/solutions PSoC 1 | PSoC 3 | PSoC 5 © Cypress Semiconductor Corporation, 2008-2009, 2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign), United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without the express written permission of Cypress. Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. Use may be limited by and subject to the applicable Cypress software license agreement. Document Number: 001-13105 Rev. *C Revised January 15, 2010 Page 43 of 43 PSoC Designer™ and EZ-Color™ are trademarks and PSoC® is a registered trademark of Cypress Semiconductor Corporation. Purchase of I2C components from Cypress or one of its sublicensed Associated Companies conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips. As from October 1st, 2006 Philips Semiconductors has a new trade name - NXP Semiconductors. All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback