CY8CLED16P01

CY8CLED16P01 Powerline Communication Solution Features ■ Powerline Communication Solution ❐ Integrated Powerline Modem PHY ❐ Frequency Shift Keying Modulation ❐ Configurable baud rates up to 2400 bps ❐ Powerline Optimized Network Protocol ❐ Integrates Data Link, Transport, and Network Layers ❐ Supports Bidirectional Half Duplex Communication ❐ 8-bit CRC Error Detection to Minimize Data Loss 2 ❐ I C enabled Powerline Application Layer 2 ❐ Supports I C Frequencies of 50, 100, and 400 kHz ❐ Reference Designs for 110V/240V AC and 12V/24V AC/DC Powerlines ❐ Reference Designs comply with CENELEC EN 50065-1:2001 and FCC Part 15 ■ HB LED Controller ❐ Configurable Dimmers Support up to 16 Independent LED Channels ❐ 8 to 32 Bits of Resolution per Channel ❐ PrISM™ Modulation technology to reduce radiated EMI and Low Frequency Blinking ❐ Additional communication interfaces for lighting control such as DALI, DMX512 etc. ■ Powerful Harvard Architecture Processor ❐ M8C Processor Speeds to 24 MHz ❐ Two 8x8 Multiply, 32-Bit Accumulate ® ■ Programmable System Resources (PSoC Blocks) ❐ 12 Rail-to-Rail Analog PSoC Blocks provide: • Up to 14-Bit ADCs • Up to 9-Bit DACs • Programmable Gain Amplifiers • Programmable Filters and Comparators 16 Digital PSoC Blocks provide: • 8 to 32-Bit Timers, Counters, and PWMs • CRC and PRS Modules • Up to Four Full Duplex UARTs • Multiple SPITM Masters or Slaves • Connectable to all GPIO Pins ❐ Complex Peripherals by Combining Blocks ■ Flexible On-Chip Memory ❐ 32 KB Flash Program Storage 50,000 Erase or Write Cycles ❐ 2 KB SRAM Data Storage ❐ EEPROM Emulation in Flash ■ Programmable Pin Configurations ❐ 25 mA Sink, 10 mA Source on all GPIOs ❐ Pull Up, Pull Down, High Z, Strong, or Open-drain Drive Modes on all GPIOs ❐ Up to 12 Analog Inputs on GPIO ❐ Configurable Interrupt on all GPIO ■ ❐ Additional System Resources 2 ❐ I C Slave, Master, and Multi-Master to 400 kHz ❐ Watchdog and Sleep Timers ❐ User-Configurable Low Voltage Detection ❐ Integrated Supervisory Circuit ❐ On-Chip Precision Voltage Reference Complete Development Tools ❐ Free Development Software (PSoC Designer™) ❐ Full Featured In-Circuit Emulator (ICE) and Programmer ❐ Full Speed Emulation ❐ Complex Breakpoint Structure ❐ 128 KB Trace Memory ❐ Complex Events ❐ C Compilers, Assembler, and Link ■ Logic Block Diagram Powerline Communication Solution Embedded Application Modulation Technology PrISM, PWM etc. Powerline Network Protocol Digital and Analog Peripherals Physical Layer FSK Modem Additional System Resources MAC, Decimator, I2C, SPI, UART etc. Additional Communication Interface DALI, DMX512 PLC Core PSoC Core Powerline Transceiver Packet HB LED Controller AC/DC Powerline Coupling Circuit (110V/240V AC, 12V/24V AC/DC etc.) Powerline Cypress Semiconductor Corporation Document Number: 001-49263 Rev. *J • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 17, 2011 CY8CLED16P01 Programmable System Resources CY8CLED16P01 1. Contents PLC Functional Overview ................................................ 3 Robust Communication using Cypress’s PLC Solution 3 Powerline Modem PHY ............................................... 3 Network Protocol ......................................................... 4 High Brightness (HB) LED Controller ............................. 8 LED Dimming Modulation ............................................ 8 Color Mixing Algorithm ................................................ 9 LED Temperature Compensation ................................ 9 ColorLock Algorithm .................................................... 9 Digital Communication .............................................. 10 Other Functions ......................................................... 10 PSoC Core ....................................................................... 11 Programmable System Resources ............................ 12 Additional System Resources ................................... 14 Getting Started ................................................................ 14 Application Notes ...................................................... 14 Development Kits ...................................................... 14 Training ..................................................................... 14 CYPros Consultants .................................................. 14 Solutions Library ........................................................ 14 Technical Support ..................................................... 14 Development Tools ........................................................ 15 PSoC Designer Software Subsystems ...................... 15 In-Circuit Emulator (ICE) ........................................... 15 Designing with PSoC Designer ..................................... 16 Select Components ................................................... 16 Configure Components ............................................. 16 Organize and Connect .............................................. 16 Generate, Verify, and Debug ..................................... 16 PLC User Modules .................................................... 17 Intelligent Lighting User Modules .............................. 17 Pin Information ............................................................... 18 28-Pin Part Pinout ..................................................... 18 48-Pin Part Pinout ..................................................... 19 100-Pin Part Pinout (On-Chip Debug) ....................... 20 Register Reference ......................................................... 22 Register Conventions ................................................ 22 Register Mapping Tables .......................................... 22 Electrical Specifications ................................................ 25 Absolute Maximum Ratings ....................................... 25 Operating Temperature ............................................. 25 DC Electrical Characteristics ..................................... 26 AC Electrical Characteristics ..................................... 35 Packaging Information ................................................... 43 Packaging Dimensions .............................................. 43 Thermal Impedances ................................................. 46 Capacitance on Crystal Pins ..................................... 46 Solder Reflow Peak Temperature ............................. 46 Development Tool Selection ......................................... 47 Software .................................................................... 47 Development Kits ...................................................... 47 Evaluation Kits ........................................................... 48 Device Programmers ................................................. 48 Ordering Information ...................................................... 49 Ordering Code Definitions ......................................... 49 Acronyms ........................................................................ 50 Acronyms Used ......................................................... 50 Reference Documents .................................................... 51 Document Conventions ................................................. 51 Glossary .......................................................................... 52 Document History Page ................................................. 57 Sales, Solutions, and Legal Information ...................... 58 Products .................................................................... 58 PSoC Solutions ......................................................... 58 Document Number: 001-49263 Rev. *J Page 2 of 58 CY8CLED16P01 2. PLC Functional Overview The CY8CLED16P01 is an integrated Powerline Communication (PLC) chip with the Powerline Modem PHY and Network Protocol Stack running on the same device. Apart from the PLC core, the CY8CLED16P01 also offers Cypress's revolutionary PSoC technology that enables system designers to integrate multiple functions on the same chip. Figure 2-2. Physical Layer FSK Modem Block Diagram Network Protocol Digital Receiver Digital Transmitter Logic ‘1’ or Logic ‘0’ Modulator Square Wave at FSK Frequencies Hysteresis Comparator Low Pass Filter External Low Pass Filter Powerline Modem PHY 2.1 Robust Communication using Cypress’s PLC Solution Powerlines are available everywhere in the world and are a widely available communication medium for PLC technology. The pervasiveness of powerlines also makes it difficult to predict the characteristics and operation of PLC products. Because of the variable quality of powerlines around the world, implementing robust communication has been an engineering challenge for years. The Cypress PLC solution enables secure and reliable communications. Cypress PLC features that enable robust communication over powerlines include: ■ Local Oscillator Correlator IF Band Pass Filter Mixer Local Oscillator Transmitter Programmable Gain Amplifier Receiver HF Band Pass Filter RX Amplifier Integrated Powerline PHY modem with optimized filters and amplifiers to work with lossy high voltage and low voltage powerlines. Powerline optimized network protocol that supports bidirectional communication with acknowledgement-based signaling. In case of data packet loss due to bursty noise on the powerline, the transmitter has the capability to retransmit data. The Powerline Network Protocol also supports an 8-bit CRC for error detection and data packet retransmission. A Carrier Sense Multiple Access (CSMA) scheme is built into the network protocol that minimizes collisions between packet transmissions on the powerline and supports multiple masters and reliable communication on a bigger network. Coupling Circuit ■ 2.2.1 Transmitter Section Digital data from the network layer is serialized by the digital transmitter and fed as input to the modulator. The modulator divides the local oscillator frequency by a definite factor depending on whether the input data is high level logic ‘1’ or low level logic ‘0’. It then generates a square wave at 133.3 kHz (logic ‘0’) or 131.8 kHz (logic ‘1’), which is fed to the Programmable Gain Amplifier to generate FSK modulated signals. This enables tunable amplification of the signal depending on the noise in the channel. The logic ‘1’ frequency can also be configured as 130.4 kHz for wider FSK deviation. 2.2.2 Receiver Section The incoming FSK signal from the powerline is input to a high frequency (HF) band pass filter that filters out-of-band frequency components and outputs a filtered signal within the desired spectrum of 125 kHz to 140 kHz for further demodulation. The mixer block multiplies the filtered FSK signals with a locally generated signal to produce heterodyned frequencies. The intermediate frequency (IF) band pass filters further remove out-of-band noise as required for further demodulation. This signal is fed to the correlator, which produces a DC component (consisting of logic ‘1’ and ‘0’) and a higher frequency component. The output of the correlator is fed to a low pass filter (LPF) that outputs only the demodulated digital data at 2400 baud and suppresses all other higher frequency components generated in the correlation process. The output of the LPF is digitized by the hysteresis comparator. This eliminates the effects of correlator delay and false logic triggers due to noise. The digital receiver deserializes this data and outputs to the network layer for interpretation. ■ ■ 2.2 Powerline Modem PHY Figure 2-1. Physical Layer FSK Modem Powerline Communication Solution Embedded Application Modulation Technology PrISM, PWM etc. Powerline Network Protocol Digital and Analog Peripherals Physical Layer FSK Modem Additional System Resources MAC, Decimator, I2C, SPI, UART etc. Additional Communication Interface DALI, DMX512 PLC Core PSoC Core Powerline Transceiver Packet HB LED Controller The physical layer of the Cypress PLC solution is implemented using an FSK modem that enables half duplex communication on any high voltage and low voltage powerline. This modem supports raw data rates up to 2400 bps. A block diagram is shown in Figure 2-2. Document Number: 001-49263 Rev. *J CY8CLED16P01 Programmable System Resources Page 3 of 58 CY8CLED16P01 2.2.3 Coupling Circuit Reference Design The coupling circuit couples low voltage signals from the CY8CLED16P01 to the powerline. The topology of this circuit is determined by the voltage on the powerline and design constraints mandated by powerline usage regulations. Cypress provides reference designs for a range of powerline voltages including 110V/240V AC and 12V/24V AC/DC. The CY8CLED16P01 is capable of data communication over other AC/DC Powerlines as well with the appropriate external coupling circuit. The 110V AC and 240V AC designs are compliant to the following powerline usage regulations: ■ ■ 2.3.1 CSMA and Timing Parameters ■ CSMA – The protocol provides the random selection of a period between 85 and 115 ms (out of seven possible values in this range). Within this period, the Band-In-Use (BIU) detector must indicate that the line is not in use, before attempting a transmission. BIU – A Band-In-Use detector, as defined under CENELEC EN 50065-1, is active whenever a signal that exceeds 86 dBVrms anywhere in the range 131.5 kHz to 133.5 kHz is present for at least 4 ms. This threshold can be configured for different end-system applications not requiring CENELEC compliance.The modem tries to retransmit after every 85 to 115 ms when the band is in use. The transmitter times out after 1.1 seconds to 3 seconds (depending on the noise on the Powerline) and generates an interrupt to indicate that the transmitter was unable to acquire the powerline. ■ FCC Part 15 for North America EN 50065-1:2001 for Europe 2.3 Network Protocol Cypress’s powerline optimized network protocol performs the functions of the data link, network, and transport layers in an ISO/OSI-equivalent model. Figure 2-3. Powerline Network Protocol 2.3.2 Powerline Transceiver Packet The powerline network protocol defines a Powerline Transceiver (PLT) packet structure, which is used for data transfers between nodes across the powerline. Packet formation and data transmission across the powerline network is implemented internally in the CY8CLED16P01. A PLT packet is divided into a variable length header (minimum 6 bytes to maximum 20 bytes, depending on address type), variable length payload (minimum 0 bytes to maximum 31 bytes), and a packet CRC byte. This packet (preceded by a one byte preamble "0xAB") is then transmitted by the powerline modem PHY and the external coupling circuit across the powerline. The format of the PLT packet is shown in the following table. Table 2-1. Powerline Transceiver (PLT) Packet Structure Byte Offset 7 6 5 4 0x00 0x01 0x02 0x03 0x04 0x05 0x06 Payload (0 to 31 Bytes) Powerline Transceiver Packet CRC RSVD Seq Num SA Type Bit Offset 3 2 1 0 Powerline Communication Solution Embedded Application Modulation Technology PrISM, PWM etc. Powerline Network Protocol Digital and Analog Peripherals Physical Layer FSK Modem Additional System Resources MAC, Decimator, I2C, SPI, UART etc. Additional Communication Interface DALI, DMX512 PLC Core PSoC Core Powerline Transceiver Packet HB LED Controller CY8CLED16P01 Programmable System Resources The network protocol implemented on the CY8CLED16P01 supports the following features: ■ ■ ■ ■ ■ ■ ■ ■ ■ DA Type Service RSVD RSVD Response RSVD Type Bidirectional half duplex communication Master-slave or peer-to-peer network topologies Multiple masters on powerline network 8-bit logical addressing supports up to 256 powerline nodes 16-bit extended logical addressing supports up to 65536 powerline nodes 64-bit physical addressing supports up to 264 powerline nodes Individual, broadcast or group mode addressing Carrier Sense Multiple Access (CSMA) Full control over transmission parameters ❐ Acknowledged ❐ Unacknowledged ❐ Repeated Transmit Destination Address (8-Bit Logical, 16-Bit Extended Logical or 64-Bit Physical) Source Address (8-Bit Logical, 16-Bit Extended Logical or 64-Bit Physical) Command Payload Length Powerline Packet Header CRC Document Number: 001-49263 Rev. *J Page 4 of 58 CY8CLED16P01 2.3.3 Packet Header The packet header contains the first 6 bytes of the packet when 1-byte logical addressing is used. When 8-byte physical addressing is used, the source and destination addresses each contain 8 bytes. In this case, the header can consist of a maximum of 20 bytes. Unused fields marked RSVD are for future expansion and are transmitted as bit 0. Table 2-2 describes the PLT packet header fields in detail. Table 2-2. Powerline Transceiver (PLT) Packet Header Field Name SA Type DA Type No. of Bits 1 2 Tag Source Address Type Description 0 – Logical Addressing 1 – Physical Addressing ■ ■ Physical addressing: Every CY8CLED16P01 has a unique 64-bit physical address. Group addressing: This is explained in the next section. 2.3.8 Group Membership Group membership enables the user to multicast messages to select groups. The CY8CLED16P01 supports two types of group addressing: ■ Single Group Membership – The network protocol supports up to 256 different groups on the network in this mode. In this mode, each PLC node can only be part of a single group. For example, multiple PLC nodes can be part of Group 131. Multiple Group Membership – The network protocol supports eight different groups in this mode and each PLC node can be a part of multiple groups. For example, a single PLC node can be a part of Group 3, Group 4, and Group 7 at the same time. ■ Service Type Response 1 1 Seq Num Header CRC 4 4 00 – Logical Addressing Destination 01 – Group Addressing Address 10 – Physical Addressing Type 11 – Invalid 0 – Unacknowledged Messaging 1 – Acknowledged Messaging Response 0 - Not an acknowledgement or response packet 1 - Acknowledgement or response packet 4-bit unique identifier for each Sequence packet between source and destiNumber nation. 4-bit CRC value. This enables the receiver to suspend receiving the rest of the packet if its header is corrupted Both of these membership modes can also be used together for group membership. For example, a single PLC node can be a part of Group 131 and also multiple groups such as Group 3, Group 4, and Group 7. The group membership ID for broadcasting messages to all nodes in the network is 0x00. The service type is always set to Unacknowledgment Mode in Group Addressing Mode. This is to avoid acknowledgment flooding on the powerline during multicast. 2.3.9 Remote Commands In addition to sending normal data over the Powerline, the CY8CPLC10 can also send (and request) control information to (and from) another node on the network. The type of remote command to transmit is set by the TX_CommandID register and when received, is stored in the RX_CommandID register. When a control command (Command ID = 0x01 - 0x08 and 0x0C - 0x0F) is received, the protocol will automatically process the packet (if Lock_Configuration is '0'), respond to the initiator, and notify the host of the successful transmission and reception. When the send data command (ID 0x09) or request for data command (ID 0x0A) is received, the protocol will reply with an acknowledgment packet (if TX_Service_Type = '1'), and notify the host of the new received data. If the initiator doesn't receive the acknowledgment packet within 500ms, it will notify the host of the no acknowledgment received condition. When a response command (ID 0x0B) is received by the initiator within 1.5s of sending the request for data command, the protocol will notify the host of the successful transmission and reception. If the response command is not received by the initiator within 1.5s, it will notify the host of the no response received condition. The host is notified by updating the appropriate values in the INT_Status register (including Status_Value_Change). The command IDs 0x30-0xff can be used for custom commands that would be processed by the external host (e.g. set an LED color, get a temperature/voltage reading). The available remote commands are described in Table 2-3 on page 6 with the respective Command IDs. 2.3.4 Payload The packet payload has a length of 0 to 31 bytes. Payload content is user defined and can be read or written through I2C. 2.3.5 Packet CRC The last byte of the packet is an 8-bit CRC value used to check packet data integrity. This CRC calculation includes the header and payload portions of the packet and is in addition to the powerline packet header CRC. 2.3.6 Sequence Numbering The sequence number is increased for every new unique packet transmitted. If in acknowledged mode and an acknowledgment is not received for a given packet, that packet will be re-transmitted (if TX_Retry > 0) with the same sequence number. If in unacknowledged mode, the packet will be transmitted (TX_Retry + 1) times with the same sequence number. If the receiver receives consecutive packets from the same source address with the same sequence number and packet CRC, it does not notify the host of the reception of the duplicate packet. If in acknowledged mode, it still sends an acknowledgment so that the transmitter knows that the packet was received. 2.3.7 Addressing The CY8CLED16P01 has three modes of addressing: ■ Logical addressing: Every CY8CLED16P01 node can have either a 8-bit logical address or a 16-bit logical address. The logical address of the PLC Node is set by the local application or by a remote node on the Powerline. Document Number: 001-49263 Rev. *J Page 5 of 58 CY8CLED16P01 Table 2-3. Remote Commands Cmd ID 0x01 Command Name SetRemote_TXEnable Description Payload (TX Data) Response (RX Data) If Remote Lock Config = 0, Response = 00 (Success) If Remote Lock Config = 1, Response = 01 (Denied) If Remote Lock Config = 0, Response = 00 (Success) If Remote Lock Config = 1, Response = 01 (Denied) If Remote Lock Config = 0, Response = 00 (Success) If Remote Lock Config = 1, Response = 01 (Denied) Sets the TX Enable bit in the 0 - Disable Remote TX PLC Mode Register. Rest of the 1 - Enable Remote TX PLC Mode register is unaffected Set the Addressing to Extended Addressing Mode 0 - Disable Extended Addressing 1 - Enable Extended Addressing If Ext Address = 0, Payload = 8-bit Logical Address If Ext Address = 1, Payload = 16-bit Logical Address 0x03 SetRemote_ExtendedAddr 0x04 SetRemote_LogicalAddr Assigns the specified logical address to the remote PLC node 0x05 GetRemote_LogicalAddr Get the Logical Address of the None remote PLC node If Remote TX Enable = 0, Response = None If Remote TX Enable = 1, {If Ext Address = 0, Response = 8-bit Logical Address If Ext Address = 1, Response = 16-bit Logical Address} If Remote TX Enable = 0, Response = None If Remote TX Enable = 1, Response = 64-bit Physical Address If Remote TX Enable = 0, Response = None If Remote TX Enable = 1, Response = Remote PLC Mode register If TX Enable = 0, Response = None If TX Enable = 1, Response = Remote Version register If Local Service Type = 0, Response = None If Local Service Type = 1, Response = Ack If Local Service Type = 1, Response = Ack Then, the remote node host must send a ResponseRemote_Data command. The response must be completely transmitted within 1.5s of receiving the request. Otherwise, the requesting node will time out. None 0x06 GetRemote_PhysicalAddr Get the Physical Address of the None remote PLC node 0x07 GetRemote_State Request PLC_Mode Register content from a Remote PLC node None 0x08 GetRemote_Version Get the Version Number of the None Remote Node 0x09 SendRemote_Data Transmit data to a Remote Node. Payload = Local TX Data 0x0A RequestRemote_Data Request data from a Remote Node Payload = Local TX Data 0x0B 0x0C ResponseRemote_Data SetRemote_BIU Transmit response data to a Remote Node. Payload = Local TX Data Enables/Disables BIU function- 0 - Enable Remote BIU If Remote Lock Config = 0, ality at the remote node 1 - Disable Remote BIU Response = 00 (Success) If Remote Lock Config = 1, Response = 01 (Denied) Document Number: 001-49263 Rev. *J Page 6 of 58 CY8CLED16P01 Table 2-3. Remote Commands (continued) Cmd ID 0x0D Command Name SetRemote_ThresholdValue Description Payload (TX Data) Response (RX Data) If Remote Lock Config = 0, Response = 00 (Success) If Remote Lock Config = 1, Response = 01 (Denied) If Remote Lock Config = 0, Response = 00 (Success) If Remote Lock Config = 1, Response = 01 (Denied) Sets the Threshold Value at the 3-bit Remote Remote node Threshold Value 0x0E SetRemote_GroupMembership Sets the Group Membership of Byte0 - Remote SIngle the Remote node Group Membership Address Byte1- Remote Multiple Group Membership Address GetRemote_GroupMembership Gets the Group Membership of None the Remote node 0x0F If Remote TX Enable = 0, Response = None If Remote TX Enable = 1, Response = Byte0 - Remote SIngle Group Membership Address Byte1- Remote Multiple Group Membership Address 0x10 0x2F 0x30 0xFF Reserved User Defined Command Set Document Number: 001-49263 Rev. *J Page 7 of 58 CY8CLED16P01 3. High Brightness (HB) LED Controller Figure 3-1. CY8CLED16P01: HB LED Controller 3.1 LED Dimming Modulation The LED Dimming modulators are an important part of any HB LED application. All EZ-Color controllers are capable of three primary types of LED dimming modulations. These are: ■ Powerline Communication Solution Embedded Application Modulation Technology PrISM, PWM etc. Pulse Width Modulation (PWM) Precise Illumination Signal Modulation (PrISM) Delta Sigma Modulated PWM (DSPWM) Powerline Network Protocol CY8CLED16P01 Programmable System Resources Digital and Analog Peripherals ■ ■ Physical Layer FSK Modem Additional System Resources MAC, Decimator, I2C, SPI, UART etc. Additional Communication Interface DALI, DMX512 PLC Core PSoC Core Powerline Transceiver Packet HB LED Controller PWM is among the most commonly used and conventional methods of modulation. It is straightforward to use and effective in practice. There are two additional techniques of modulation supported by EZ-Color that are superior to using the PWM alone: ■ PrISM is a modulation technique that is developed and patented by Cypress. It results in reduced EMI as compared to the PWM technique while still providing adequate dimming control for LEDs. The HB LED Controller is based on Cypress's EZ-Color™ technology. EZ-Color offers the ideal control solution for high brightness (HB) LED applications requiring intelligent dimming control. EZ-Color devices combine the power and flexibility of PSoC (Programmable System-on-Chip) with Cypress's PrISM™ (Precise Illumination Signal Modulation) modulation technology providing lighting designers a fully customizable and integrated lighting solution platform. The CY8CLED16P01 supports up to 16 independent LED channels with up to 32 bits of resolution per channel, giving lighting designers the flexibility to choose the LED array size and color quality. PSoC Designer software, with lighting-specific user modules, significantly cuts development time and simplifies implementation of fixed color points through temperature and LED binning compensation. EZ-Color's virtually limitless analog and digital customization enable simple integration of features in addition to intelligent lighting, such as battery charging, image stabilization, and motor control during the development process. These features, along with Cypress's best-in-class quality and design support, make EZ-Color the ideal choice for intelligent HB LED control applications. The list of functions that EZ-Color devices implement are: ■ ■ LED Dimming Modulation Pulse Density Modulation Techniques ❐ DMX512 ❐ DALI Digital Communication for Lighting LED Temperature Compensation 3- and 4-Channel Color Mixing ❐ Including LED Binning Compensation Optical Feedback Algorithms The Delta Sigma Modulated PWM technique provides higher resolution while using the same hardware resources as a conventional PWM. LED dimming modulators use digital block resources. Digital blocks are configurable 8-bit digital peripherals. There are two types of digital blocks in the CY8CLED16P01: basic and communication. Usually, there are equal numbers of each. Any communication functions must be implemented using communication blocks but basic, noncommunication functions are implemented using either kind of block. PWM and DSPWM modulators can have a dimming resolution of up to 16 bits. A PrISM modulator can theoretically have a dimming resolution of up to 32 bits, but the maximum recommended resolution for these modulators is 13 bits. This is because the output signal of a PrISM modulator has a frequency output range that increases with the resolution of the modulator. This increase in frequency output range is undesirable as it goes beyond the switching frequency of the current driver. Therefore, a resolution of 13 bits or lower is recommended for a PrISM modulator. Refer to application note AN47372, PrISM Technology for LED Dimming on http://www.cypress.com, for details. To determine the number of digital blocks used by one PWM or PrISM modulator, use Equation 1. Note that a partial digital block cannot be used, so the result must always be rounded up. In Equation 1, n is the dimming resolution of the modulator. The resolution of dimming is determined by the color accuracy needed for the end application. ■ ■ ■ ■ DigBlocksPWM ,PRISM  n 8 Equation 1 ■ Document Number: 001-49263 Rev. *J Page 8 of 58 CY8CLED16P01 Equations 2 and 3 are used to determine how many digital blocks are needed by a DSPWM. The total dimming resolution of a DSPWM modulator is the total of the hardware PWM modulation resolution and extra resolution added by Delta Sigma modulation in the software. Equation 3 shows that the number of digital blocks needed is only determined by the hardware resolution. If the dimming resolution is increased, the number of digital blocks needed should be calculated accordingly. 3.3 LED Temperature Compensation Many HB LED systems need to measure analog signals. One or more thermistors are often present to measure temperatures of the system and the LEDs. The CY8CLED16P01 measures an analog signal with an analog-to-digital converter (ADC). The device can implement a variety of flexible ADC implementations. The ADCs cover a wide range of resolutions and techniques and use varied number of digital and analog block resources. For help in selecting from this multitude of ADCs, refer to application note AN2239, Analog – ADC Selection on http://www.cypress.com. When designing with an EZ-Color device, the number of digital and analog blocks used by an ADC must be factored into the total number of digital and analog blocks that are used. In a typical case, such as the 3-channel color mixing firmware IP developed by Cypress, the simple 8-bit incremental ADC is used. This module occupies one digital and one switched capacitor analog block. Analog blocks come in two types: continuous time and switched capacitor blocks. The former enables continuous time functions such as comparators and programmable gain amplifiers. The switched capacitor blocks enable functions such as ADCs and filters. Temperature sensors with an I2C interface can also be used instead of raw thermistors, thereby eliminating the need for ADCs and complicated processing. DigBlocksDSPWM  nHW 8 Equation 2 nTotal  nSW  nHW Equation 3 These equations show that more dimming resolution is achieved with a DSPWM modulator than with a PWM or PrISM modulator. A DSPWM modulator requires more code space and execution time to use. Equations 1, 2, and 3 determine the number of digital blocks required by one modulator. The total number of blocks for all modulators is determined by adding up the digital blocks needed by each modulator used in the device. The CY8CLED16P01 device has a variety of LED dimming configurations. Because it has 16 digital blocks, it can implement eight 16-bit PWM modulators, eight 12-bit PrISM modulators, or sixteen 12-bit DSPWM modulators (assuming the software resolution is 4 bits). As another example, it can implement four 10-bit PrISM modulators and still have 8 digital blocks left over to implement other digital functions. The CY8CLED16P01 is a one-device solution for powerline communication and HB LED control. For an application that runs powerline communication and HB LED control simultaneously, the CY8CLED16P01 can implement four 16-bit PWM modulators, four 12-bit PrISM modulators, or eight 12-bit DSPWM modulators (assuming the software resolution is 4 bits). 3.4 ColorLock Algorithm ColorLock functionality uses feedback from an optical sensor in the system to adjust the LED dimming modulators correctly to “lock on” to a target color. This is similar to the concept of temperature compensation because it compensates for change in color. Instead of indirectly measuring change in color through temperature, it senses actual change in color and compensates for it. The ColorLock algorithm implemented by Cypress requires the use of 10 digital blocks. Due to a 9-bit PrISM implementation, 6 digital blocks are used for dimming as in Equation 1. A 16-bit PWM and two 8-bit timers are also used to form the frame generator, pulse counter, and debounce counter. 3.2 Color Mixing Algorithm Code algorithms to implement color mixing functionality work well with EZ-Color controllers. Color mixing algorithms convert a set of color coordinates that specify a color into the appropriate 8-bit dimming values for the LED dimming modulators. This enables the EZ-Color controller to be communicated on a higher level and maintain desired color and brightness levels. The basic 3-channel color mixing firmware performing 8-bit LED dimming requires three 8-bit dimming blocks. The discussion on LED dimming modulation implies that it consumes three digital blocks. The addition of a simple temperature compensation algorithm using a thermistor consumes an additional digital block and analog block (for the ADC). Document Number: 001-49263 Rev. *J Page 9 of 58 CY8CLED16P01 3.5 Digital Communication Most HB LED-based lighting systems require some form of digital communication to send and receive data to and from the light fixtures to control them. The CY8CLED16P01 is a one-device solution for HB LED lighting control and powerline communication. However, the CY8CLED16P01 supports several other data communication protocols, apart from powerline communication. These are listed in Table 3-1. Some of the hardware is dedicated for a protocol and does not use any digital blocks. Some protocols use digital blocks to implement the communication. A DMX512 protocol receiver can be implemented using two digital blocks. This is a standard protocol that is common in stage and concert lighting systems. The receiver has a software programmable address and programmable number of channels that it can control. A typical DMX512 receiver implementation (developed by Cypress) controlling three LED channels consumes five digital blocks (three for the LED modulators). Table 3-1. Digital Communication Resource Usage Data Protocol DMX512 (Receiver) DALI (Slave) I2 C Master or Slave Digital Blocks 2 3 0 1 1 Communication Digital Blocks 1 0 0 1 1 Apart from these specific lighting communication protocols, the industry standard communication protocols such as I2C, UART, and SPI can be implemented in any of the devices in the family. As examples, SPI can be used to interface to external WUSB devices, while I2C can be used to interface to external microcontrollers. Table 3-1 also shows the number of digital block resources that each type of communication block consumes. 3.6 Other Functions The CY8CLED16P01 is capable of functions other than those previously discussed. Most functions that can be implemented with a standard microcontroller can be also implemented with the CY8CLED16P01. Similar to regular PSoC devices, the CY8CLED16P01 also has dynamic reconfiguration ability. This is a technique that enables the device’s digital and analog resources to be reused for different functions that may not be available simultaneously. For instance, consider the application to remotely control LED color/intensity (with current feedback) over powerlines using the CY8CLED16P01 for both PLC and LED color control. The PLC functionality and the current feedback do not necessarily need to happen at the same time. Therefore, the digital and analog blocks that implement the PLC functionality can dynamically reconfigure into resources that implement current feedback. By doing this, the CY8CLED16P01 device gets more functionality out of a fixed number of resources than would otherwise be possible. The only constraint on this technique is the amount of Flash and SRAM size required for the code to implement these functions. For more details on dynamic reconfiguration, refer to application note AN2104, PSoC Dynamic Reconfiguration. Half Duplex UART SPI Master or Slave DALI is another lighting communication protocol that is common for large commercial buildings. The DALI slave can be implemented in EZ-Color consuming six digital blocks (three for the DALI slave and three to modulate 3 LED channels). The three blocks used to implement DALI need not be communication blocks as the Manchester encoding is performed in the software. Document Number: 001-49263 Rev. *J Page 10 of 58 CY8CLED16P01 4. PSoC Core The CY8CLED16P01 is based on the Cypress PSoC® 1 architecture. The PSoC platform consists of many Programmable System-on-chip Controller devices. These devices are designed to replace multiple traditional MCU-based system components with one, low cost single-chip programmable device. PSoC devices include configurable blocks of analog and digital logic, and programmable interconnects. This architecture enables the user to create customized peripheral configurations that match the requirements of each individual application. Additionally, a fast CPU, Flash program memory, SRAM data memory, and configurable I/Os are included in a range of convenient pinouts and packages. The PSoC architecture, as shown in Figure 4-1., consists of four main areas: PSoC Core, Digital System, Analog System, and System Resources. Configurable global busing enables all the device resources to be combined into a complete custom system. The CY8CLED16P01 family can have up to five I/O ports that connect to the global digital and analog interconnects, providing access to 16 digital blocks and 12 analog blocks. The PSoC Core is a powerful engine that supports a rich feature set. The core includes a CPU, memory, clocks, and configurable GPIO (General Purpose I/O). Figure 4-1. PSoC Architecture Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Analog Drivers The M8C CPU core is a powerful processor with speeds up to 24 MHz, providing a 4 MIPS 8-bit Harvard architecture microprocessor. The CPU uses an interrupt controller with 25 vectors, to simplify programming of realtime embedded events. Program execution is timed and protected using the included Sleep and Watchdog timers (WDT). Memory encompasses 32 KB of Flash for program storage, 2 KB of SRAM for data storage, and up to 2 KB of EEPROM emulated using Flash. Program Flash uses four protection levels on blocks of 64 bytes, enabling customized software IP protection. The PSoC device incorporates flexible internal clock generators, including a 24 MHz IMO (internal main oscillator) accurate to 2.5 percent over temperature and voltage. The 24 MHz IMO can also be doubled to 48 MHz for the digital system use. A low power 32 kHz ILO (internal low speed oscillator) is provided for the sleep timer and WDT. If crystal accuracy is desired, the ECO (32.768 kHz external crystal oscillator) is available for use as a Real Time Clock (RTC) and can optionally generate a crystal-accurate 24 MHz system clock using a PLL. When operating the Powerline Transceiver (PLT) user module, the ECO must be selected to ensure accurate protocol timing. The clocks, together with programmable clock dividers (as a System Resource), provide the flexibility to integrate almost any timing requirement into the PSoC device. PSoC GPIOs provide connection to the CPU, digital, and analog resources of the device. Each pin’s drive mode may be selected from eight options, enabling great flexibility in external interfacing. Every pin also has the capability to generate a system interrupt on high level, low level, and change from last read. SYSTEM BUS Global Digital Interconnect SRAM 2K Interrupt Controller Global Analog Interconnect Flash 32K SROM PSoC CORE Sleep and Watchdog CPU Core (M8C) Multiple Clock Sources (Includes IMO, ILO, PLL, and ECO) DIGITAL SYSTEM Digital Block Array ANALOG SYSTEM Analog Ref. Analog Block Array Analog Input Muxing Digital Clocks Two Multiply Accums. POR and LVD Decimator I2 C System Resets Internal Voltage Ref. SYSTEM RESOURCES Document Number: 001-49263 Rev. *J Page 11 of 58 CY8CLED16P01 4.1 Programmable System Resources Figure 4-2. Programmable System Resources Figure 4-3. Digital System Block Diagram Port 7 Port 6 Port 5 Port 4 Port 3 Port 2 Port 1 Port 0 Powerline Communication Solution Embedded Application Modulation Technology PrISM, PWM etc. Digital Clocks FromCore CY8CLED16P01 To System Bus ToAnalog System Programmable System Resources Powerline Network Protocol Digital and Analog Peripherals DIGITAL SYSTEM Digital PSoC Block Array Row Input Configuration Physical Layer FSK Modem Additional System Resources MAC, Decimator, I2C, SPI, UART etc. Additional Communication Interface DALI, DMX512 Row 0 DBB00 DBB01 DCB02 4 DCB03 4 Row Output Configuration PLC Core PSoC Core Powerline Transceiver Packet HB LED Controller 8 8 8 4.1.1 The Digital System The digital system contains 16 digital PSoC blocks. Each block is an 8-bit resource that can be used alone, or combined with other blocks to form 8-, 16-, 24-, and 32-bit peripherals called user modules. Digital peripheral configurations include: ■ ■ ■ ■ ■ ■ Row Input Configuration Row 1 DBB10 DBB11 DCB12 4 DCB13 4 8 Row Output Configuration Row Input Configuration PWMs (8 to 32 bit) PWMs with Dead Band (8 to 32 bit) Counters (8 to 32 bit) Timers (8 to 32 bit) Row 2 DBB20 DBB21 DCB22 4 DCB23 4 Row Output Configuration Row Input Configuration UART 8 bit with selectable parity (up to four) SPI master and slave (up to four each) slave and multi-master (one available as a System Resource) Cyclical Redundancy Checker and Generator (8 to 32 bit) IrDA (up to 4) Pseudo Random Sequence Generators (8 to 32 bit) Row 3 DBB30 DBB31 DCB32 4 DCB33 4 Row Output Configuration 2 ■I C ■ ■ ■ GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0] The digital blocks can be connected to any GPIO through a series of global buses that can route any signal to any pin. The buses also enable signal multiplexing and perform logic operations. This configurability frees your designs from the constraints of a fixed peripheral controller. Document Number: 001-49263 Rev. *J Page 12 of 58 CY8CLED16P01 4.1.2 The Analog System Figure 4-4. Analog System Block Diagram P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6] P0[4] P0[2] P0[0] P2[6] The analog system contains 12 configurable blocks, each containing an opamp circuit, enabling the creation of complex analog signal flows. Analog peripherals are very flexible and can be customized to support specific application requirements. Some of the more common PSoC analog functions (most available as user modules) are: ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Analog-to-digital converters (up to 4, with 6- to 14-bit resolution, selectable as Incremental, Delta Sigma, and SAR) Filters (2, 4, 6, or 8 pole band pass, low pass, and notch) Amplifiers (up to 4, with selectable gain to 48x) P2[3] P2[4] P2[2] P2[0] P2[1] Instrumentation amplifiers (up to 2, with selectable gain to 93x) Comparators (up to 4, with 16 selectable thresholds) DACs (up to 4, with 6- to 9-bit resolution) Multiplying DACs (up to 4, with 6- to 9-bit resolution) High current output drivers (4 with 40 mA drive as a Core Resource) 1.3V reference (as a System Resource) DTMF Dialer Modulators Block Array ACI0[1:0] Array Input Configuration ACI1[1:0] ACI2[1:0] ACI3[1:0] Correlators Peak detectors Many other topologies possible ACB00 ASC10 ASD20 ACB01 ASD11 ASC21 ACB02 ASC12 ASD22 ACB03 ASD13 ASC23 Analog blocks are provided in columns of three, which includes one CT (continuous time) and two SC (switched capacitor) blocks, as shown in the Figure 4-4. on page 13. Analog Reference Interface to Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap M8C Interface (Address Bus, Data Bus, Etc.) Document Number: 001-49263 Rev. *J Page 13 of 58 CY8CLED16P01 4.2 Additional System Resources Figure 4-5. Additional System Resources 5. Getting Started The quickest way to understand Cypress’s Powerline Communication offering is to read this data sheet and then use the PSoC Designer Integrated Development Environment (IDE). The latest version of PSoC Designer can be downloaded from http://www.cypress.com. This data sheet is an overview of the CY8CLED16P01 integrated circuit and presents specific pin, register, and electrical specifications. For in depth information, along with detailed programming details, see the PLC Technical Reference Manual. For up to date ordering, packaging, and electrical specification information, see the latest PLC device data sheets on the web at http://www.cypress.com. Powerline Communication Solution Embedded Application Modulation Technology PrISM, PWM etc. Powerline Network Protocol Digital and Analog Peripherals Physical Layer FSK Modem Additional System Resources MAC, Decimator, I2C, SPI, UART etc. Additional Communication Interface DALI, DMX512 PLC Core PSoC Core Powerline Transceiver Packet HB LED Controller CY8CLED16P01 Programmable System Resources Application Notes Cypress application notes are an excellent introduction to the wide variety of possible PSoC designs. System Resources, some of which have been previously described, provide additional capability useful to complete systems. Resources include a multiplier, decimator, low voltage detection, and power on reset. The following statements describe the merits of each system resource. ■ Development Kits PSoC Development Kits are available online from and through a growing number of regional and global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and Newark. Digital clock dividers provide three customizable clock frequencies for use in applications. The clocks can be routed to both the digital and analog systems. Additional clocks are generated using digital PSoC blocks as clock dividers. Multiply accumulate (MAC) provides a fast 8-bit multiplier with 32-bit accumulate, to assist in general math and digital filters. The decimator provides a custom hardware filter for digital signal processing applications including the creation of Delta Sigma ADCs. The I2C module provides 100 and 400 kHz communication over two wires. Slave, master, and multi-master modes are supported. Low Voltage Detection (LVD) interrupts signal the application of falling voltage levels, while the advanced POR (Power On Reset) circuit eliminates the need for a system supervisor. An internal 1.3V reference provides an absolute reference for the analog system, including ADCs and DACs. Training Free PSoC technical training (on demand, webinars, and workshops), which is available online via www.cypress.com, covers a wide variety of topics and skill levels to assist you in your designs. ■ ■ CYPros Consultants Certified PSoC consultants offer everything from technical assistance to completed PSoC designs. To contact or become a PSoC consultant go to the CYPros Consultants web site. ■ ■ Solutions Library Visit our growing library of solution focused designs. Here you can find various application designs that include firmware and hardware design files that enable you to complete your designs quickly. ■ Technical Support Technical support – including a searchable Knowledge Base articles and technical forums – is also available online. If you cannot find an answer to your question, call our Technical Support hotline at 1-800-541-4736. Document Number: 001-49263 Rev. *J Page 14 of 58 CY8CLED16P01 6. Development Tools PSoC Designer™ is the revolutionary integrated design environment (IDE) that you can use to customize PSoC to meet your specific application requirements. PSoC Designer software accelerates system design and time to market. Develop your applications using a library of precharacterized analog and digital peripherals (called user modules) in a drag-and-drop design environment. Then, customize your design by leveraging the dynamically generated application programming interface (API) libraries of code. Finally, debug and test your designs with the integrated debug environment, including in-circuit emulation and standard software debug features. PSoC Designer includes: ■ ■ ■ ■ ■ ■ ■ of debugging tools. You can develop your design in C, assembly, or a combination of the two. Assemblers. The assemblers allow you to merge assembly code seamlessly with C code. Link libraries automatically use absolute addressing or are compiled in relative mode, and linked with other software modules to get absolute addressing. C Language Compilers. C language compilers are available that support the PSoC family of devices. The products allow you to create complete C programs for the PSoC family devices. The optimizing C compilers provide all of the features of C, tailored to the PSoC architecture. They come complete with embedded libraries providing port and bus operations, standard keypad and display support, and extended math functionality. Debugger Application editor graphical user interface (GUI) for device and user module configuration and dynamic reconfiguration Extensive user module catalog Integrated source-code editor (C and assembly) Free C compiler with no size restrictions or time limits Built-in debugger In-circuit emulation Built-in support for communication interfaces: 2 ❐ Hardware and software I C slaves and masters ❐ Full-speed USB 2.0 ❐ Up to four full-duplex universal asynchronous receiver/transmitters (UARTs), SPI master and slave, and wireless PSoC Designer supports the entire library of PSoC 1 devices and runs on Windows XP, Windows Vista, and Windows 7. PSoC Designer has a debug environment that provides hardware in-circuit emulation, allowing you to test the program in a physical system while providing an internal view of the PSoC device. Debugger commands allow you to read and program and read and write data memory, and read and write I/O registers. You can read and write CPU registers, set and clear breakpoints, and provide program run, halt, and step control. The debugger also lets you to create a trace buffer of registers and memory locations of interest. Online Help System PSoC Designer Software Subsystems Design Entry The online help system displays online, context-sensitive help. Designed for procedural and quick reference, each functional subsystem has its own context-sensitive help. This system also provides tutorials and links to FAQs and an Online Support Forum to aid the designer. In-Circuit Emulator In the chip-level view, choose a base device to work with. Then select different onboard analog and digital components that use the PSoC blocks, which are called user modules. Examples of user modules are analog-to-digital converters (ADCs), digital-to-analog converters (DACs), amplifiers, and filters. Configure the user modules for your chosen application and connect them to each other and to the proper pins. Then generate your project. This prepopulates your project with APIs and libraries that you can use to program your application. The tool also supports easy development of multiple configurations and dynamic reconfiguration. Dynamic reconfiguration makes it possible to change configurations at run time. In essence, this lets you to use more than 100 percent of PSoC's resources for an application. Code Generation Tools A low-cost, high-functionality in-circuit emulator (ICE) is available for development support. This hardware can program single devices. The emulator consists of a base unit that connects to the PC using a USB port. The base unit is universal and operates with all PSoC devices. Emulation pods for each device family are available separately. The emulation pod takes the place of the PSoC device in the target board and performs full-speed (24 MHz) operation. The code generation tools work seamlessly within the PSoC Designer interface and have been tested with a full range Document Number: 001-49263 Rev. *J Page 15 of 58 CY8CLED16P01 7. Designing with PSoC Designer The development process for the PSoC device differs from that of a traditional fixed-function microprocessor. The configurable analog and digital hardware blocks give the PSoC architecture a unique flexibility that pays dividends in managing specification change during development and lowering inventory costs. These configurable resources, called PSoC blocks, have the ability to implement a wide variety of user-selectable functions. The PSoC development process is: 1. Select user modules. 2. Configure user modules. 3. Organize and connect. 4. Generate, verify, and debug. Organize and Connect Build signal chains at the chip level by interconnecting user modules to each other and the I/O pins. Perform the selection, configuration, and routing so that you have complete control over all on-chip resources. Generate, Verify, and Debug When you are ready to test the hardware configuration or move on to developing code for the project, perform the “Generate Configuration Files” step. This causes PSoC Designer to generate source code that automatically configures the device to your specification and provides the software for the system. The generated code provides APIs with high-level functions to control and respond to hardware events at run time, and interrupt service routines that you can adapt as needed. A complete code development environment lets you to develop and customize your applications in C, assembly language, or both. The last step in the development process takes place inside PSoC Designer's Debugger (accessed by clicking the Connect icon). PSoC Designer downloads the HEX image to the ICE where it runs at full-speed. PSoC Designer debugging capabilities rival those of systems costing many times more. In addition to traditional single-step, run-to-breakpoint, and watch-variable features, the debug interface provides a large trace buffer. It lets you to define complex breakpoint events that include monitoring address and data bus values, memory locations, and external signals. Select User Modules PSoC Designer provides a library of prebuilt, pretested hardware peripheral components called “user modules.” User modules make selecting and implementing peripheral devices, both analog and digital, simple. Configure User Modules Each user module that you select establishes the basic register settings that implement the selected function. They also provide parameters and properties that allow you to tailor their precise configuration to your particular application. For example, a PWM User Module configures one or more digital PSoC blocks, one for each eight bits of resolution. Using these parameters, you can establish the pulse width and duty cycle. Configure the parameters and properties to correspond to your chosen application. Enter values directly or by selecting values from drop-down menus. All of the user modules are documented in datasheets that may be viewed directly in PSoC Designer or on the Cypress website. These user module datasheets explain the internal operation of the user module and provide performance specifications. Each datasheet describes the use of each user module parameter, and other information that you may need to successfully implement your design. Document Number: 001-49263 Rev. *J Page 16 of 58 CY8CLED16P01 7.1 PLC User Modules Powerline Transceiver (PLT) User Module (UM) enables data communication over powerlines up to baud rates of 2400 bps. This UM also exposes all the APIs from the network protocol for ease of application development. The UM, when instantiated, provides the user with three implementation modes: ■ ■ FSK Modem + Network Stack – This mode allows the user to use the Cypress network protocol for PLC and build any application with the APIs provided by the network protocol. FSK Modem + Network Stack + I2C – This mode allows the user to interface the CY8CLEDP01 with any other microcontroller or PSoC device. Users can also split the application between the PLC device and the external microcontroller. If the external microcontroller is a PSoC device, then the I2C UMs can be used to interface it with the PLC device. ■ FSK Modem Only – This mode enables the user to use the raw FSK modem and build any network protocol or application with the help of the APIs generated by the modem PHY. Figure 7-1. shows the starting window for the PLT UM with the three implementation modes from which the user can choose. Figure 7-1. PLT User Module Refer to the application note AN55403 - "Estimating CY8CPLC20/CY8CLED16P01 Power Consumption" at http://www.cypress.com to determine the power consumption estimate of the CY8CLED16P01 chip with the PLT User Module, loaded along with the other User Modules. 7.6 Intelligent Lighting User Modules The CY8CLED16P01 has the intelligent lighting control user modules along with the PLC user modules. These user modules enable the user to do the following: ■ ■ ■ ■ ■ Control multiple channels, anywhere between 1 and 16. Enable temperature compensation and color feedback Provide algorithms for high CRI Control color with 1931 or 1976 gamuts and through CCT Provide additional communication interfaces such as DALI and DMX512 Document Number: 001-49263 Rev. *J Page 17 of 58 CY8CLED16P01 8. Pin Information The CY8CLED16P01 PLC device is available in a variety of packages which are listed and illustrated in the following tables. Every port pin (labeled with a “P”) is capable of Digital I/O. However, Vss, Vdd, and XRES are not capable of Digital I/O. 8.1 28-Pin Part Pinout Table 8-1. 28-Pin Part Pinout (SSOP) Pin No. 1 2 3 4 5 Type Digital Analog I/O I Reserved O I/O I O Pin Name P0[7] RSVD FSK_OUT P0[1] TX_SHUT DOWN Description Analog Column Mux Input Reserved Analog FSK Output Analog Column Mux Input Output to disable PLC transmit circuitry in receive mode Logic ‘0’ - When the Modem is transmitting Logic ‘1’ - When the Modem is not transmitting Direct switched capacitor block input Direct switched capacitor block input Reserved I2C Serial Clock (SCL) I2C Serial Data (SDA) XTAL_STABILITY. Connect a 0.1 µF capacitor between the pin and Vss. Crystal (XTALin)[2], ISSP-SCLK[1], I2C SCL Ground connection. Crystal (XTALout)[2], ISSP-SDATA[1], I2C SDA Optional External Clock Input (EXTCLK)[2] Figure 8-1. CY8CLED16P01 28-Pin PLC Device A, I , P0[7] RSVD FSK_OUT A, I , P0[1] TX_ SHUTDOWN P2[5] A, I , P2[3] A , I,P2[1] RSVD I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 I/O I/O I I/O I Reserved I/O I/O I/O I/O Power I/O I/O I/O I/O Input O I Analog Ground I/O Reserved I/O I/O I/O I/O I Power P2[5] P2[3] P2[1] RSVD P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] XRES 1 2 3 4 5 6 7 8 9 10 11 12 13 14 SSOP 28 27 26 25 24 23 22 21 20 19 18 17 16 15 Vdd FSK_IN P0[4] , A , IO P0[2],A,IO RSVD P2[6] , External VREF AGND RXCOMP _IN RXCOMP _OUT XRES P1[6] P1[4] , EXTCLK P1[2] P1[0] , XTALout, I2C SDA Active high external reset with internal pull down RXCOMP_ Analog Output to external Low Pass OUT Filter Circuitry RXCOMP_ Analog Input from the external Low IN Pass Filter Circuitry AGND Analog Ground. Connect a 1.0 µF capacitor between the pin and Vss. P2[6] External Voltage Reference (VREF) RSVD Reserved P0[2] Analog column mux input and column output P0[4] Analog column mux input and column output FSK_IN Analog FSK Input Vdd Supply Voltage LEGEND: A = Analog, I = Input, O = Output, and RSVD = Reserved (should be left unconnected). Notes 1. These are the ISSP pins, which are not High Z at POR (Power On Reset). See the PSoC Technical Reference Manual for details. 2. When using the PLT user module, the external crystal is always required for protocol timing. For the FSK modem, either the PLL Mode should be enabled or the external 24MHz on P1[4] should be selected. The IMO should not be used. Document Number: 001-49263 Rev. *J Page 18 of 58 CY8CLED16P01 8.2 48-Pin Part Pinout Table 8-2. 48-Pin Part Pinout (QFN )[3] Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 Type Digital Analog I/O I I/O I I/O I/O I/O I/O Reserved I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Power I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Input I/O I/O I/O I/O O I Analog Ground I/O Reserved Pin Name P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] RSVD P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] Vss P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] RXCOMP_ OUT RXCOMP_ IN AGND P2[6] RSVD Description Direct switched capacitor block input Direct switched capacitor block input Figure 8-2. CY8CLED16P01 48-Pin PLC Device Vdd FSK_IN P0[4], A, IO P0[2], A, IO RSVD P2[6], External VREF 36 35 34 33 32 31 30 29 28 27 26 25 AGND RXCOMP _IN RXCOMP OUT _ P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] Reserved Optional External Clock Input (EXTCLK)[2] Active high external reset with internal pull down Analog Output to external Low Pass Filter Circuitry Analog Input from external Low Pass Filter Circuitry Analog Ground. Connect a 1.0 µF capacitor between the pin and Vss. External Voltage Reference (VREF) Reserved I/O I/O Power I/O I/O I/O I I P0[2] P0[4] FSK_IN Vdd P0[7] RSVD FSK_OUT] P0[1] TX_SHUT DOWN Analog column mux input and column output Analog column mux input and column output Analog FSK Input Supply Voltage Analog column mux input Reserved Analog FSK Output Analog column mux input Output to disable transmit circuitry in receive mode Logic ‘0’ - When the Modem is transmitting Logic ‘1’ - When the Modem is not transmitting Reserved I/O O O I 48 I/O P2[5] LEGEND: A = Analog, I = Input, O = Output, and RSVD = Reserved (should be left unconnected). Note 3. The QFN package has a center pad that must be connected to ground (Vss). Document Number: 001-49263 Rev. *J P5[1] I2C SCL, P1[7] I2C SDA, P1[5] P1[3] I2C SCL, XTALin, P1[1] Vss I2C SDA, XTALout, P1[0] P1[2] EXTCLK, P1[4] P1[6] P5[0] P5[2] I2C Serial Clock (SCL) I2C Serial Data (SDA) XTAL_STABILITY. Connect a 1.0 µF capacitor between the pin and Vss. Crystal (XTALin)[2], I2C Serial Clock (SCL), ISSP-SCLK[1] Ground connection. Crystal (XTALout)[2], I2C Serial Data (SDA), ISSP-SDATA[1] A , I , P2[3] 1 A , I , P2[1] 2 P4[7] 3 P4[5] 4 P4[3] 5 P4[1] 6 RSVD 7 P3[7] 8 P3[5] 9 P3[3] 10 P3[1] 11 P5[3] 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 P2[5] TX_SHUTDOWN P0[1], A, I FSK_OUT RSVD P0[7], A, I QFN ( Top View ) Page 19 of 58 CY8CLED16P01 8.3 100-Pin Part Pinout (On-Chip Debug) The 100-pin TQFP part is for the CY8CLED16P01-OCD On-Chip Debug PLC device. Note that the OCD parts are only used for in-circuit debugging. OCD parts are not available for production. Table 8-3. 100-Pin OCD Part Pinout (TQFP) Analog Pin No. 1 2 3 4 Name NC NC P0[1] TX_SHUTD OWN P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] OCDE OCDO RSVD Vss P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] NC NC NC P1[5] P1[3] P1[1] NC Vdd NC Vss NC P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] P1[0] P1[2] P1[4] P1[6] NC NC NC Description No Connection No Connection Analog Column Mux Input Output to disable transmit circuitry in receive mode Logic ‘0’ - When the Modem is transmitting Logic ‘1’ - When the Modem is not transmitting Direct switched capacitor block input Direct switched capacitor block input Analog Digital Digital Pin No. 51 52 53 54 Name NC P5[0] P5[2] P5[4] No Connection Description I/O O I I/O I/O I/O 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 I/O I/O I/O I/O I/O I/O I/O I I Reserved Power I/O I/O I/O I/O I/O I/O I/O I/O I/O OCD even data I/O OCD odd data output Reserved Ground Connection 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 I/O I/O I/O I/O I/O Input I/O I/O Power I/O I/O O I Ground P5[6] P3[0] P3[2] P3[4] P3[6] HCLK CCLK XRES P4[0] P4[2] Vss P4[4] P4[6] RXCOMP_OUT RXCOMP_IN AGND NC P2[6] NC RSVD NC NC OCD high speed clock output OCD CPU clock output Active high pin reset with internal pull down Ground Connection I/O Reserved I2C Serial Clock (SCL) No Connection No Connection No Connection I2C Serial Data (SDA) XTAL_STABILITY. Connect a 0.1 uF capacitor between the pin and VSS. Crystal (XTALin)[2], I2C Serial Clock (SCL), TC SCLK No Connection Supply Voltage No Connection Ground Connection No Connection Analog Output to external Low Pass Filter Circuitry Analog Input from external Low Pass Filter Circuitry Analog Ground. Connect a 1.0 µF capacitor between the pin and Vss. No Connection External Voltage Reference (VREF) input No Connection Reserved No Connection No Connection I/O I/O I/O I/O P0[2] NC P0[4] NC Analog column mux input and column output No Connection Analog column mux input and column output, VREF No Connection Analog FSK Input Supply Voltage Supply Voltage Ground Connection Ground Connection I/O I/O I/O Power Power I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I Power Power Power Power I/O I/O I/O I/O I/O I/O I/O I/O Crystal (XTALout)[2], I2C Serial Data (SDA), TC SDATA Optional External Clock Input (EXTCLK)[2] No Connection No Connection No Connection FSK_IN Vdd Vdd Vss Vss P6[0] P6[1] P6[2] P6[3] P6[4] P6[5] P6[6] P6[7] NC P0[7] NC RSVD NC FSK_OUT NC No Connection Analog Column Mux Input No Connection Reserved No Connection Analog FSK Output No Connection I/O I Reserved O LEGEND A = Analog, I = Input, O = Output, NC = No Connection, TC/TM: Test, TC/TM: Test, RSVD = Reserved (should be left unconnected). Document Number: 001-49263 Rev. *J Page 20 of 58 CY8CLED16P01 Figure 8-3. CY8CLED16P01-OCD 100 NC 99 FSK_OUT 98 NC 97 RSVD 96 NC 95 P0[7], AI 94 NC 93 P6[7] 92 P6[6] 91 P6[5] 90 P6[4] 89 P6[3] 88 P6[2] 87 P6[1] 86 P6[0] 85 Vss 84 Vss 83 Vdd 82 Vdd 81 FSK_IN 80 NC 79 P0[4], A, IO 78 NC 77 P0[2], A, IO 76 NC 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 NC RSVD NC P2[6] , External VREF NC AGND RXCOMP _IN RXCOMP OUT _ P4[6] P4[4] Vss P4[2] P4[0] XRES CCLK HCLK P3[6] P3[4] P3[2] P3[0] P5[6] P5[4] P5[2] P5[0] NC 26 27 28 29 30 31 32 33 34 35 NC NC I2C SDA, P1[5] P1[3] XTALin, I2C SCL, P1[1] NC Vdd NC Vss NC P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] XTALout, I2C SDA, P1[0] P1[2] EXTCLK, P1[4] P1[6] NC Not for Production Document Number: 001-49263 Rev. *J NC NC 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC AI , P0[1] TX_ SHUTDOWN P2[5] AI , P2[3] AI , P2[1] P4[7] P4[5] P4[3] P4[1] OCDE OCDO RSVD Vss P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] I2 C SCL, P1[7] NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 OCD TQFP Page 21 of 58 CY8CLED16P01 9. Register Reference This section lists the registers of the CY8CLED16P01 PLC device. For detailed register information, refer to the PLC Technical Reference Manual. 9.2 Register Mapping Tables The CY8CLEDP01 device has a total register address space of 512 bytes. The register space is referred to as I/O space and is divided into two banks. The XOI bit in the Flag register (CPU_F) determines which bank the user is currently in. When the XOI bit is set the user is in Bank 1. Note In the following register mapping tables, blank fields are reserved and should not be accessed. 9.1 Register Conventions The register conventions specific to this section are listed in the following table. Convention Description R W L C # Read register or bit(s) Write register or bit(s) Logical register or bit(s) Clearable register or bit(s) Access is bit specific Document Number: 001-49263 Rev. *J Page 22 of 58 CY8CLED16P01 Table 9-1. Register Map Bank 0 Table: User Space Name Addr (0,Hex) Access Name PRT0DR 00 RW DBB20DR0 PRT0IE 01 RW DBB20DR1 PRT0GS 02 RW DBB20DR2 PRT0DM2 03 RW DBB20CR0 PRT1DR 04 RW DBB21DR0 PRT1IE 05 RW DBB21DR1 PRT1GS 06 RW DBB21DR2 PRT1DM2 07 RW DBB21CR0 PRT2DR 08 RW DCB22DR0 PRT2IE 09 RW DCB22DR1 PRT2GS 0A RW DCB22DR2 PRT2DM2 0B RW DCB22CR0 PRT3DR 0C RW DCB23DR0 PRT3IE 0D RW DCB23DR1 PRT3GS 0E RW DCB23DR2 PRT3DM2 0F RW DCB23CR0 PRT4DR 10 RW DBB30DR0 PRT4IE 11 RW DBB30DR1 PRT4GS 12 RW DBB30DR2 PRT4DM2 13 RW DBB30CR0 PRT5DR 14 RW DBB31DR0 PRT5IE 15 RW DBB31DR1 PRT5GS 16 RW DBB31DR2 PRT5DM2 17 RW DBB31CR0 PRT6DR 18 RW DCB32DR0 PRT6IE 19 RW DCB32DR1 PRT6GS 1A RW DCB32DR2 PRT6DM2 1B RW DCB32CR0 PRT7DR 1C RW DCB33DR0 PRT7IE 1D RW DCB33DR1 PRT7GS 1E RW DCB33DR2 PRT7DM2 1F RW DCB33CR0 DBB00DR0 20 # AMX_IN DBB00DR1 21 W DBB00DR2 22 RW DBB00CR0 23 # ARF_CR DBB01DR0 24 # CMP_CR0 DBB01DR1 25 W ASY_CR DBB01DR2 26 RW CMP_CR1 DBB01CR0 27 # DCB02DR0 28 # DCB02DR1 29 W DCB02DR2 2A RW DCB02CR0 2B # DCB03DR0 2C # TMP_DR0 DCB03DR1 2D W TMP_DR1 DCB03DR2 2E RW TMP_DR2 DCB03CR0 2F # TMP_DR3 DBB10DR0 30 # ACB00CR3 DBB10DR1 31 W ACB00CR0 DBB10DR2 32 RW ACB00CR1 DBB10CR0 33 # ACB00CR2 DBB11DR0 34 # ACB01CR3 DBB11DR1 35 W ACB01CR0 DBB11DR2 36 RW ACB01CR1 DBB11CR0 37 # ACB01CR2 DCB12DR0 38 # ACB02CR3 DCB12DR1 39 W ACB02CR0 DCB12DR2 3A RW ACB02CR1 DCB12CR0 3B # ACB02CR2 DCB13DR0 3C # ACB03CR3 DCB13DR1 3D W ACB03CR0 DCB13DR2 3E RW ACB03CR1 DCB13CR0 3F # ACB03CR2 Blank fields are Reserved and should not be accessed. Addr (0,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Access # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # # W RW # RW Addr (0,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 MUL1_X A8 MUL1_Y A9 MUL1_DH AA MUL1_DL AB ACC1_DR1 AC ACC1_DR0 AD ACC1_DR3 AE ACC1_DR2 AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 RDI1RI B8 RDI1SYN B9 RDI1IS BA RDI1LT0 BB RDI1LT1 BC RDI1RO0 BD RDI1RO1 BE BF # Access is bit specific. Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI3RI RDI3SYN RDI3IS RDI3LT0 RDI3LT1 RDI3RO0 RDI3RO1 CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 Addr (0,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW # RW # RW RW RW RW RW RW RW RW RC W RC RC RW RW W W R R RW RW RW RW RW # # RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW W W R R RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW CPU_F RL CPU_SCR1 CPU_SCR0 # # Document Number: 001-49263 Rev. *J Page 23 of 58 CY8CLED16P01 Table 9-2. Register Map Bank 1 Table: Configuration Space Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 PRT6DM0 PRT6DM1 PRT6IC0 PRT6IC1 PRT7DM0 PRT7DM1 PRT7IC0 PRT7IC1 DBB00FN DBB00IN DBB00OU Addr (1,Hex) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name DBB20FN DBB20IN DBB20OU DBB21FN DBB21IN DBB21OU DCB22FN DCB22IN DCB22OU DCB23FN DCB23IN DCB23OU DBB30FN DBB30IN DBB30OU DBB31FN DBB31IN DBB31OU DCB32FN DCB32IN DCB32OU DCB33FN DCB33IN Addr (1,Hex) 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77 78 79 7A 7B 7C 7D 7E 7F Access Name RW ASC10CR0 RW ASC10CR1 RW ASC10CR2 ASC10CR3 RW ASD11CR0 RW ASD11CR1 RW ASD11CR2 ASD11CR3 RW ASC12CR0 RW ASC12CR1 RW ASC12CR2 ASC12CR3 RW ASD13CR0 RW ASD13CR1 RW ASD13CR2 ASD13CR3 RW ASD20CR0 RW ASD20CR1 RW ASD20CR2 ASD20CR3 RW ASC21CR0 RW ASC21CR1 RW ASC21CR2 ASC21CR3 RW ASD22CR0 RW ASD22CR1 RW ASD22CR2 ASD22CR3 RW ASC23CR0 RW ASC23CR1 RW RW RW RW RW ASC23CR2 ASC23CR3 Addr (1,Hex) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98 99 9A 9B 9C 9D Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI3RI RDI3SYN RDI3IS RDI3LT0 RDI3LT1 RDI3RO0 RDI3RO1 GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU Addr (1,Hex) C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF Access RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 1E RW DCB33OU 1F RW 20 RW CLK_CR0 21 RW CLK_CR1 22 RW ABF_CR0 23 AMD_CR0 DBB01FN 24 RW DBB01IN 25 RW DBB01OU 26 RW AMD_CR1 27 ALT_CR0 DCB02FN 28 RW ALT_CR1 DCB02IN 29 RW CLK_CR2 DCB02OU 2A RW 2B DCB03FN 2C RW TMP_DR0 DCB03IN 2D RW TMP_DR1 DCB03OU 2E RW TMP_DR2 2F TMP_DR3 DBB10FN 30 RW ACB00CR3 DBB10IN 31 RW ACB00CR0 DBB10OU 32 RW ACB00CR1 33 ACB00CR2 DBB11FN 34 RW ACB01CR3 DBB11IN 35 RW ACB01CR0 DBB11OU 36 RW ACB01CR1 37 ACB01CR2 DCB12FN 38 RW ACB02CR3 DCB12IN 39 RW ACB02CR0 DCB12OU 3A RW ACB02CR1 3B ACB02CR2 DCB13FN 3C RW ACB03CR3 DCB13IN 3D RW ACB03CR0 DCB13OU 3E RW ACB03CR1 3F ACB03CR2 Blank fields are Reserved and should not be accessed. RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF RDI0RI B0 RDI0SYN B1 RDI0IS B2 RDI0LT0 B3 RDI0LT1 B4 RDI0RO0 B5 RDI0RO1 B6 B7 RDI1RI B8 RDI1SYN B9 RDI1IS BA RDI1LT0 BB RDI1LT1 BC RDI1RO0 BD RDI1RO1 BE BF # Access is bit specific. OSC_GO_E N OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP RW RW RW RW RW RW RW R DEC_CR2 IMO_TR ILO_TR BDG_TR ECO_TR RW W W RW W RW RW RW RW RW RW RW CPU_F RW RW RW RW RW RW RW RL FLS_PR1 RW CPU_SCR1 CPU_SCR0 # # Document Number: 001-49263 Rev. *J Page 24 of 58 CY8CLED16P01 10. Electrical Specifications This section presents the DC and AC electrical specifications of the CY8CLED16P01 device. For the most up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com. Specifications are valid for -40°C  TA  85°C and TJ  100°C, except where noted. 10.1 Absolute Maximum Ratings Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. Table 10-1. Absolute Maximum Ratings Symbol TSTG Description Storage Temperature Min –55 Typ 25 Max +100 Units °C Notes Higher storage temperatures reduce data retention time. Recommended storage temperature is +25°C ± 25°C. Extended duration storage temperatures above 65°C degrade reliability. TBAKETEMP Bake Temperature – 125 TBAKETIME Bake Time TA Vdd VIO VIOZ IMIO IMAIO ESD LU Ambient Temperature with Power Applied Supply Voltage on Vdd Relative to Vss DC Input Voltage DC Voltage Applied to Tristate Maximum Current into any Port Pin Maximum Current into any Port Pin Configured as Analog Driver Electro Static Discharge Voltage Latch-up Current See package label –40 –0.5 Vss – 0.5 Vss – 0.5 –25 -50 2000 – – See package label 72 C Hours – – – – – – – – +85 +6.0 Vdd + 0.5 Vdd + 0.5 +50 +50 – 200 °C V V V mA mA V mA Human Body Model ESD 10.2 Operating Temperature Table 10-2. Operating Temperature Symbol TA TJ Description Ambient Temperature Junction Temperature Min -40 -40 Typ – – Max +85 +100 Units C C Notes The temperature rise from ambient to junction is package specific. See Thermal Impedances on page 46.The user must limit the power consumption to comply with this requirement. Document Number: 001-49263 Rev. *J Page 25 of 58 CY8CLED16P01 10.3 DC Electrical Characteristics 10.3.1 DC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 10-3. DC Chip-Level Specifications Symbol Description Vdd Supply Voltage IDD Supply Current Min 4.75 – Typ – 8 Max 5.25 14 Units V mA Notes VREF Reference Voltage (Bandgap) 1.28 1.3 1.32 V Conditions are 5.0V, TA = 25°C, CPU = 3 MHz, SYSCLK doubler disabled, VC1 = 1.5 MHz, VC2 = 93.75 kHz, VC3 = 0.366 kHz. Trimmed for appropriate Vdd. 10.3.2 DC GPIO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature range: 4.75V to 5.25V and -40°C  TA  85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 10-4. DC GPIO Specifications Symbol RPU RPD VOH Description Pull Up Resistor Pull Down Resistor High Output Level Min 4 4 Vdd 1.0 Typ 5.6 5.6 – Max 8 8 – Units k k V Notes VOL Low Output Level – – 0.75 V IOH IOL VIL VIH VH IIL CIN COUT High Level Source Current Low Level Sink Current Input Low Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load on Pins as Input Capacitive Load on Pins as Output 10 25 – 2.1 – – – – – – – – 60 1 3.5 3.5 – – 0.8 – – 10 10 mA mA V V mV nA pF pF IOH = 10 mA, (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 80 mA maximum combined IOH budget. IOL = 25 mA, (8 total loads, 4 on even port pins (for example, P0[2], P1[4]), 4 on odd port pins (for example, P0[3], P1[5])). 150 mA maximum combined IOL budget. VOH = Vdd-1.0V. See the limitations of the total current in the Note for VOH. VOL = 0.75V. See the limitations of the total current in the Note for VOL. Gross tested to 1 A. Package and pin dependent. Temp = 25°C. Package and pin dependent. Temp = 25°C. Document Number: 001-49263 Rev. *J Page 26 of 58 CY8CLED16P01 10.3.3 DC Operational Amplifier Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. The Operational Amplifier is a component of both the Analog Continuous Time PSoC blocks and the Analog Switched Capacitor PSoC blocks. The guaranteed specifications are measured in the Analog Continuous Time PSoC block. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 10-5. 5-V DC Operational Amplifier Specifications Symbol VOSOA Description Input offset voltage (absolute value) Power = Low, Opamp bias = Low Power = Low, Opamp bias = High Power = Medium, Opamp bias = Low Power = Medium, Opamp bias = High Power = High, Opamp bias = Low Power = High, Opamp bias = High Average input offset voltage drift Input leakage current (port 0 analog pins) Input capacitance (port 0 analog pins) Common mode voltage range (All cases, except Power = High, Opamp bias = High) Common mode voltage range (Power = High, Opamp bias = High) Min – – – – – – – – – 0 Typ 1.6 1.6 1.6 1.6 1.6 1.6 4 200 4.5 – Max 10 10 10 10 10 10 23 – 9.5 VDD VDD – 0.5 Unit mV mV mV mV mV mV µV/°C pA pF V Gross tested to 1 µA Package and pin dependent. Temp = 25 °C The common-mode input voltage range is measured through an analog output buffer. The specification includes the limitations imposed by the characteristics of the analog output buffer. Notes TCVOSOA I EBOA CINOA V CMOA 0.5 – V CMRROA GOLOA Common mode rejection ratio Open loop gain 60 80 VDD – 0.01 – – – – – – – – 0.1 dB dB V V VOHIGHOA High output voltage swing (internal signals) VOLOWOA Low output voltage swing (internal signals) ISOA Supply current (including associated AGND buffer) Power = Low, Opamp bias = Low Power = Low, Opamp bias = High Power = Medium, Opamp bias = Low Power = Medium, Opamp bias = High Power = High, Opamp bias = Low Power = High, Opamp bias = High Supply voltage rejection ratio – – – – – – 67 150 300 600 1200 2400 4600 80 200 400 800 1600 3200 6400 – µA µA µA µA µA µA dB VSS  VIN  (VDD – 2.25) or (VDD – 1.25 V)  VIN  VDD. PSRROA 10.3.4 DC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 10-6. DC Low Power Comparator Specifications Symbol Description VREFLPC Low Power Comparator (LPC) Reference Voltage Range LPC Supply Current ISLPC VOSLPC LPC Voltage Offset Min 0.2 Typ – Max Vdd - 1 Units V A mV Notes – – 10 2.5 40 30 Document Number: 001-49263 Rev. *J Page 27 of 58 CY8CLED16P01 10.3.5 DC Analog Output Buffer Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 10-7. DC Analog Output Buffer Specifications Symbol CL Description Load capacitance Min – Typ – Max 200 Units pF Notes This specification applies to the external circuit driven by the analog output buffer. VOSOB TCVOSOB VCMOB ROUTOB VOHIGHOB VOLOWOB ISOB PSRROB Input Offset Voltage (Absolute Value) Power = Low, Opamp bias = Low Power = Low, Opamp bias = High Power = High, Opamp bias = Low Power = High, Opamp bias = High Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power = Low Power = High High Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High Low Output Voltage Swing (Load = 32 ohms to Vdd/2) Power = Low Power = High Supply Current Including Bias Cell (No Load) Power = Low Power = High Supply Voltage Rejection Ratio – – – – – 0.5 – – 3.2 3.2 3.2 3.2 5.5 – – – 18 18 18 18 26 Vdd - 1.0 1 1 mV mV mV mV V/°C V W W 0.5 × Vdd + 1.3 0.5 × Vdd + 1.3 – – – – V V – – – – 40 – – 1.1 2.6 64 0.5 × Vdd - 1.3 0.5 × Vdd - 1.3 2 5 – V V mA mA dB Document Number: 001-49263 Rev. *J Page 28 of 58 CY8CLED16P01 10.3.6 DC Analog Reference Specifications Table 10-8 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. The guaranteed specifications are measured through the Analog Continuous Time PSoC blocks. The power levels for AGND refer to the power of the Analog Continuous Time PSoC block. The power levels for RefHi and RefLo refer to the Analog Reference Control register. The limits stated for AGND include the offset error of the AGND buffer local to the Analog Continuous Time PSoC block. Reference control power is high. Note Avoid using P2[4] for digital signaling when using an analog resource that depends on the Analog Reference. Some coupling of the digital signal may appear on the AGND. Table 10-8. 5-V DC Analog Reference Specifications Reference ARF_CR[5:3] Reference Power Settings RefPower = High Opamp bias = High Symbol VREFHI VAGND VREFLO RefPower = High Opamp bias = Low 0b000 VREFHI VAGND VREFLO RefPower = Med Opamp bias = High VREFHI VAGND VREFLO RefPower = Med Opamp bias = Low VREFHI VAGND VREFLO Reference Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Description VDD/2 + Bandgap VDD/2 VDD/2 – Bandgap VDD/2 + Bandgap VDD/2 VDD/2 – Bandgap VDD/2 + Bandgap VDD/2 VDD/2 – Bandgap VDD/2 + Bandgap VDD/2 VDD/2 – Bandgap Min VDD/2 + 1.228 VDD/2 – 0.078 VDD/2 – 1.336 VDD/2 + 1.224 VDD/2 – 0.056 VDD/2 – 1.338 VDD/2 + 1.226 VDD/2 – 0.057 VDD/2 – 1.337 VDD/2 + 1.226 VDD/2 – 0.047 VDD/2 – 1.338 Typ Max Unit V V V V V V V V V V V V VDD/2 + 1.290 VDD/2 + 1.352 VDD/2 – 0.007 VDD/2 – 1.295 VDD/2 – 0.005 VDD/2 – 1.298 VDD/2 – 0.006 VDD/2 – 1.298 VDD/2 – 0.004 VDD/2 – 1.299 VDD/2 + 0.063 VDD/2 – 1.250 VDD/2 + 0.043 VDD/2 – 1.255 VDD/2 + 0.044 VDD/2 – 1.256 VDD/2 + 0.035 VDD/2 – 1.258 VDD/2 + 1.293 VDD/2 + 1.356 VDD/2 + 1.293 VDD/2 + 1.356 VDD/2 + 1.294 VDD/2 + 1.359 Document Number: 001-49263 Rev. *J Page 29 of 58 CY8CLED16P01 Table 10-8. 5-V DC Analog Reference Specifications (continued) Reference ARF_CR[5:3] Reference Power Settings RefPower = High Opamp bias = High Symbol VREFHI Reference Ref High Description P2[4] + P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] P2[4] – P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] + P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] P2[4] – P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] + P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] P2[4] – P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] + P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) P2[4] P2[4] – P2[6] (P2[4] = VDD/2, P2[6] = 1.3 V) VDD VDD/2 VSS VDD VDD/2 VSS VDD VDD/2 VSS VDD VDD/2 VSS Min P2[4] + P2[6] – 0.085 P2[4] P2[4] – P2[6] – 0.022 P2[4] + P2[6] – 0.077 P2[4] P2[4] – P2[6] – 0.022 P2[4] + P2[6] – 0.070 P2[4] P2[4] – P2[6] – 0.022 P2[4] + P2[6] – 0.070 P2[4] P2[4] – P2[6] – 0.022 VDD – 0.037 VDD/2 – 0.061 VSS VDD – 0.039 VDD/2 – 0.049 VSS VDD – 0.037 VDD/2 – 0.054 VSS VDD – 0.042 VDD/2 – 0.046 VSS Typ P2[4] + P2[6] – 0.016 P2[4] Max P2[4] + P2[6] + 0.044 P2[4] Unit V VAGND VREFLO AGND Ref Low – V P2[4] – P2[6] + P2[4] – P2[6] + 0.010 0.055 P2[4] + P2[6] – 0.010 P2[4] P2[4] + P2[6] + 0.051 P2[4] RefPower = High Opamp bias = Low VREFHI Ref High V VAGND VREFLO 0b001 AGND Ref Low – V P2[4] – P2[6] + P2[4] – P2[6] + 0.005 0.039 P2[4] + P2[6] – 0.010 P2[4] P2[4] + P2[6] + 0.050 P2[4] RefPower = Med Opamp bias = High VREFHI Ref High V VAGND VREFLO AGND Ref Low – V P2[4] – P2[6] + P2[4] – P2[6] + 0.005 0.039 P2[4] + P2[6] – 0.007 P2[4] P2[4] + P2[6] + 0.054 P2[4] RefPower = Med Opamp bias = Low VREFHI Ref High V VAGND VREFLO AGND Ref Low – V P2[4] – P2[6] + P2[4] – P2[6] + 0.002 0.032 VDD – 0.009 VDD/2 – 0.006 VSS + 0.007 VDD – 0.006 VDD/2 – 0.005 VSS + 0.005 VDD – 0.007 VDD/2 – 0.005 VSS + 0.006 VDD – 0.005 VDD/2 – 0.004 VSS + 0.004 VDD VDD/2 + 0.047 VSS + 0.028 VDD VDD/2 + 0.036 VSS + 0.019 VDD VDD/2 + 0.041 VSS + 0.024 VDD VDD/2 + 0.034 VSS + 0.017 RefPower = High Opamp bias = High VREFHI VAGND VREFLO VREFHI VAGND VREFLO VREFHI VAGND VREFLO VREFHI VAGND VREFLO Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low V V V V V V V V V V V V RefPower = High Opamp bias = Low 0b010 RefPower = Med Opamp bias = High RefPower = Med Opamp bias = Low Document Number: 001-49263 Rev. *J Page 30 of 58 CY8CLED16P01 Table 10-8. 5-V DC Analog Reference Specifications (continued) Reference ARF_CR[5:3] Reference Power Settings RefPower = High Opamp bias = High Symbol VREFHI VAGND VREFLO RefPower = High Opamp bias = Low 0b011 VREFHI VAGND VREFLO RefPower = Med Opamp bias = High VREFHI VAGND VREFLO RefPower = Med Opamp bias = Low VREFHI VAGND VREFLO RefPower = High Opamp bias = High VREFHI Reference Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High Description 3 × Bandgap 2 × Bandgap Bandgap 3 × Bandgap 2 × Bandgap Bandgap 3 × Bandgap 2 × Bandgap Bandgap 3 × Bandgap 2 × Bandgap Bandgap 2 × Bandgap + P2[6] (P2[6] = 1.3 V) 2 × Bandgap 2 × Bandgap – P2[6] (P2[6] = 1.3 V) 2 × Bandgap + P2[6] (P2[6] = 1.3 V) 2 × Bandgap 2 × Bandgap – P2[6] (P2[6] = 1.3 V) 2 × Bandgap + P2[6] (P2[6] = 1.3 V) 2 × Bandgap 2 × Bandgap – P2[6] (P2[6] = 1.3 V) 2 × Bandgap + P2[6] (P2[6] = 1.3 V) 2 × Bandgap 2 × Bandgap – P2[6] (P2[6] = 1.3 V) Min 3.788 2.500 1.257 3.792 2.518 1.256 3.795 2.516 1.256 3.792 2.522 1.255 2.495 – P2[6] Typ 3.891 2.604 1.306 3.893 2.602 1.302 3.894 2.603 1.303 3.895 2.602 1.301 2.586 – P2[6] Max 3.986 3.699 1.359 3.982 2.692 1.354 3.993 2.698 1.353 3.986 2.685 1.350 2.657 – P2[6] Unit V V V V V V V V V V V V V VAGND VREFLO AGND Ref Low 2.502 2.531 – P2[6] 2.604 2.611 – P2[6] 2.719 2.681 – P2[6] V V RefPower = High Opamp bias = Low VREFHI Ref High 2.500 – P2[6] 2.591 – P2[6] 2.662 – P2[6] V VAGND VREFLO 0b100 AGND Ref Low 2.519 2.530 – P2[6] 2.602 2.605 – P2[6] 2.693 2.666 – P2[6] V V RefPower = Med Opamp bias = High VREFHI Ref High 2.503 – P2[6] 2.592 – P2[6] 2.662 – P2[6] V VAGND VREFLO AGND Ref Low 2.517 2.529 – P2[6] 2.603 2.606 – P2[6] 2.698 2.665 – P2[6] V V RefPower = Med Opamp bias = Low VREFHI Ref High 2.505 – P2[6] 2.594 – P2[6] 2.665 – P2[6] V VAGND VREFLO AGND Ref Low 2.525 2.528 – P2[6] 2.602 2.603 – P2[6] 2.685 2.661 – P2[6] V V Document Number: 001-49263 Rev. *J Page 31 of 58 CY8CLED16P01 Table 10-8. 5-V DC Analog Reference Specifications (continued) Reference ARF_CR[5:3] Reference Power Settings RefPower = High Opamp bias = High Symbol VREFHI VAGND VREFLO RefPower = High Opamp bias = Low VREFHI VAGND VREFLO 0b101 RefPower = Med Opamp bias = High VREFHI VAGND VREFLO RefPower = Med Opamp bias = Low VREFHI VAGND VREFLO RefPower = High Opamp bias = High VREFHI VAGND VREFLO RefPower = High Opamp bias = Low 0b110 VREFHI VAGND VREFLO RefPower = Med Opamp bias = High VREFHI VAGND VREFLO RefPower = Med Opamp bias = Low VREFHI VAGND VREFLO RefPower = High Opamp bias = High VREFHI VAGND VREFLO RefPower = High Opamp bias = Low 0b111 VREFHI VAGND VREFLO RefPower = Med Opamp bias = High VREFHI VAGND VREFLO RefPower = Med Opamp bias = Low VREFHI VAGND VREFLO Reference Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Ref High AGND Ref Low Description P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] – Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] – Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] – Bandgap (P2[4] = VDD/2) P2[4] + Bandgap (P2[4] = VDD/2) P2[4] P2[4] – Bandgap (P2[4] = VDD/2) 2 × Bandgap Bandgap VSS 2 × Bandgap Bandgap VSS 2 × Bandgap Bandgap VSS 2 × Bandgap Bandgap VSS 3.2 × Bandgap 1.6 × Bandgap VSS 3.2 × Bandgap 1.6 × Bandgap VSS 3.2 × Bandgap 1.6 × Bandgap VSS 3.2 × Bandgap 1.6 × Bandgap VSS Min P2[4] + 1.222 P2[4] P2[4] – 1.331 P2[4] + 1.226 P2[4] P2[4] – 1.331 P2[4] + 1.227 P2[4] P2[4] – 1.331 P2[4] + 1.228 P2[4] P2[4] – 1.332 2.535 1.227 VSS 2.530 1.244 VSS 2.532 1.239 VSS 2.528 1.249 VSS 4.041 1.998 VSS 4.047 2.012 VSS 4.049 2.008 VSS 4.047 2.016 VSS Typ P2[4] + 1.290 P2[4] P2[4] – 1.295 P2[4] + 1.293 P2[4] P2[4] – 1.298 P2[4] + 1.294 P2[4] P2[4] – 1.298 P2[4] + 1.295 P2[4] P2[4] – 1.299 2.598 1.305 VSS + 0.009 2.598 1.303 VSS + 0.005 2.598 1.304 VSS + 0.006 2.598 1.302 VSS + 0.004 4.155 2.083 VSS + 0.010 4.153 2.082 VSS + 0.006 4.154 2.083 VSS + 0.006 4.154 2.081 VSS + 0.004 Max P2[4] + 1.343 P2[4] P2[4] – 1.254 P2[4] + 1.347 P2[4] P2[4] – 1.259 P2[4] + 1.347 P2[4] P2[4] – 1.259 P2[4] + 1.349 P2[4] P2[4] – 1.260 2.644 1.398 VSS + 0.038 2.643 1.370 VSS + 0.024 2.644 1.380 VSS + 0.026 2.645 1.362 VSS + 0.018 4.234 2.183 VSS + 0.038 4.236 2.157 VSS + 0.024 4.238 2.165 VSS + 0.026 4.238 2.150 VSS + 0.018 Unit V – V V – V V – V V – V V V V V V V V V V V V V V V V V V V V V V V V V Document Number: 001-49263 Rev. *J Page 32 of 58 CY8CLED16P01 10.3.7 DC Analog PSoC Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 10-9. DC Analog PSoC Block Specifications Symbol RCT CSC Description Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switch Cap) Min – – Typ 12.2 80 Max – – Units k fF Notes 10.3.8 DC POR and LVD Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C = TA = 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 10-10. DC POR and LVD Specifications Symbol Description Min Typ Max Units Notes Vdd Value for PPOR Trip (positive ramp) VPPOR2R PORLEV[1:0] = 10b VPPOR2 VPH2 VLVD6 VLVD7 Vdd Value for PPOR Trip (negative ramp) PORLEV[1:0] = 10b PPOR Hysteresis PORLEV[1:0] = 10b Vdd Value for LVD Trip VM[2:0] = 110b VM[2:0] = 111b – – – 4.63 4.72 4.55 4.55 0 4.73 4.81 – – – 4.82 4.91 V V mV V V Document Number: 001-49263 Rev. *J Page 33 of 58 CY8CLED16P01 10.3.9 DC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 10-11. DC Programming Specifications Symbol VDDP Description VDD for programming and erase Min 4.5 Typ 5 Max 5.5 Units V Notes This specification applies to the functional requirements of external programmer tools. This specification applies to the functional requirements of external programmer tools. This specification applies to the functional requirements of external programmer tools. This specification applies to this device when it is executing internal flash writes. VDDLV Low VDD for verify 4.7 4.8 4.9 V VDDHV High VDD for verify 5.1 5.2 5.3 V VDDIWRITE Supply voltage for flash write operation 4.75 5,0 5.25 V IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR Supply Current During Programming or Verify – Input Low Voltage During Programming or – Verify Input High Voltage During Programming or 2.2 Verify Input Current when Applying VILP to P1[0] or – P1[1] During Programming or Verify Input Current when Applying VIHP to P1[0] or – P1[1] During Programming or Verify Output Low Voltage During Programming or – Verify Output High Voltage During Programming or Vdd - 1.0 Verify Flash Endurance (per block) 50,000 Flash Endurance (total)[5] Flash Data Retention 1,800,000 10 10 – – – – – – – – – 30 0.8 – 0.2 1.5 Vss + 0.75 Vdd – – – mA V V mA mA V V – – Years Erase/write cycles per block Erase/write cycles Driving internal pull down resistor Driving internal pull down resistor DC I2C Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 10-12. DC I2C Specifications Parameter VILI2C[4] VIHI2C[4] Input low level Input high level Description Min – 0.7 × VDD Typ – – Max 0.25 × VDD – Units V V Notes 4.75 V  VDD 5.25 V 4.75 V VDD 5.25 V Note 4. All GPIOs meet the DC GPIO VIL and VIH specifications found in the DC GPIO specifications sections.The I2C GPIO pins also meet the mentioned specs. Document Number: 001-49263 Rev. *J Page 34 of 58 CY8CLED16P01 10.4 AC Electrical Characteristics 10.4.1 AC Chip-Level Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Note See the individual user module data sheets for information on maximum frequencies for user modules. Table 10-13. AC Chip-Level Specifications Symbol Description Internal Main Oscillator Frequency for 24 MHz Min 23.4 Typ 24 Max 24.6 Units MHz Notes Trimmed for 5V operation using factory trim values. SLIMO Mode = 0. Trimmed for 5V operation using factory trim values. SLIMO Mode = 1. SLIMO Mode = 0. Refer to the AC Digital Block Specifications below. FIMO24 FIMO6 Internal Main Oscillator Frequency for 6 MHz 5.5 6 6.5[6] 24.6[6] 49.2[6, 7] 64 – MHz FCPU1 F48M F32K1 F32K2 CPU Frequency (5V Nominal) Digital PSoC Block Frequency Internal Low Speed Oscillator Frequency External Crystal Oscillator 0.0914 0 15 – 24 48 32 32.768 MHz MHz kHz kHz F32K_U Internal Low Speed Oscillator (ILO) Untrimmed Frequency 5 – 100 kHz FPLL TPLLSLEW TPLLSLEWLOW TOS TOSACC PLL Frequency PLL Lock Time PLL Lock Time for Low Gain Setting External Crystal Oscillator Startup to 1% External Crystal Oscillator Startup to 100 ppm – 0.5 0.5 – – 23.986 – – 250 300 – 10 50 500 600 MHz ms ms ms ms Accuracy is capacitor and crystal dependent. 50% duty cycle. After a reset and before the m8c starts to run, the ILO is not trimmed. See the System Resets section of the PSoC Technical Reference Manual for details on timing this. A multiple (x732) of crystal frequency. The crystal oscillator frequency is within 100 ppm of its final value by the end of the TOSACC period. Correct operation assumes a properly loaded 1 W maximum drive level 32.768 kHz crystal. -40°C  TA  85°C. Vdd slew rate during power up. Power up from 0V. See the System Resets section of the PSoC Technical Reference Manual. TXRST External Reset Pulse Width SRPOWER_UP Power Supply Slew Rate TPOWERUP Time from End of POR to CPU Executing Code 10 – – – – 16 – 250 100 s V/ms ms DC24M 24 MHz Duty Cycle 40 50 60 % Notes 5. A maximum of 36 x 50,000 block endurance cycles is allowed. This may be balanced between operations on 36x1 blocks of 50,000 maximum cycles each, 36x2 blocks of 25,000 maximum cycles each, or 36x4 blocks of 12,500 maximum cycles each (to limit the total number of cycles to 36x50,000 and that no single block ever sees more than 50,000 cycles). For the full industrial range, the user must employ a temperature sensor user module (FlashTemp) and feed the result to the temperature argument before writing. Refer to the Flash APIs Application Note AN2015 at http://www.cypress.com under Application Notes for more information. 6. Accuracy derived from Internal Main Oscillator with appropriate trim for Vdd range. 7. See the individual user module data sheets for information on maximum frequencies for user modules. 8. Refer to Cypress Jitter Specifications application note, Understanding Datasheet Jitter Specifications for Cypress Timing Products – AN5054 for more information. Document Number: 001-49263 Rev. *J Page 35 of 58 CY8CLED16P01 Table 10-13. AC Chip-Level Specifications (continued) Symbol DCILO Step24M Fout48M Description Internal Low Speed Oscillator Duty Cycle 24 MHz Trim Step Size 48 MHz Output Frequency Min 20 – 46.8 Typ 50 50 48.0 Max 80 – 49.2 Units % kHz MHz Notes Trimmed using factory trim values. FMAX tjit_IMO [8] tjit_PLL [8] Maximum frequency of signal on row input or row output. 24 MHz IMO cycle-to-cycle jitter (RMS) 24 MHz IMO long term N cycle-to-cycle jitter (RMS) 24 MHz IMO period jitter (RMS) 24 MHz IMO cycle-to-cycle jitter (RMS) 24 MHz IMO long term N cycle-to-cycle jitter (RMS) 24 MHz IMO period jitter (RMS) – – – – – – – – 200 300 100 200 300 100 12.3 700 900 400 800 1200 700 MHz ps ps ps ps ps ps N = 32 N = 32 Figure 10-1. PLL Lock Timing Diagram PLL Enable TPLLSLEW 24 MHz FPLL PLL Gain 0 Figure 10-2. PLL Lock for Low Gain Setting Timing Diagram PLL Enable TPLLSLEWLOW 24 MHz FPLL PLL Gain 1 Figure 10-3. External Crystal Oscillator Startup Timing Diagram 32K Select TOS 32 kHz F32K2 Document Number: 001-49263 Rev. *J Page 36 of 58 CY8CLED16P01 10.4.2 AC GPIO Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 10-14. AC GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload = 50 pF Fall Time, Normal Strong Mode, Cload = 50 pF Rise Time, Slow Strong Mode, Cload = 50 pF Fall Time, Slow Strong Mode, Cload = 50 pF Min 0 3 2 10 10 Typ – – – 27 22 Max 12.3 18 18 – – Units MHz ns ns ns ns Notes Normal Strong Mode 10% - 90% 10% - 90% 10% - 90% 10% - 90% Figure 10-4. GPIO Timing Diagram 90% GPIO Pin Output Voltage 10% TRiseF TRiseS TFallF TFallS 10.4.3 AC Operational Amplifier Specifications Table 10-15 lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Settling times, slew rates, and gain bandwidth are based on the Analog Continuous Time PSoC block. Table 10-15. 5V AC Operational Amplifier Specifications Symbol TROA Description Rising Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Falling Settling Time to 0.1% for a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Rising Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Falling Slew Rate (20% to 80%) of a 1V Step (10 pF load, Unity Gain) Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Min Typ Max Units s s s s s s Notes – – – – – – 3.9 0.72 0.62 TSOA – – – – – – 5.9 0.92 0.72 SRROA 0.15 1.7 6.5 – – – – – – V/s V/s V/s V/s V/s V/s SRFOA 0.01 0.5 4.0 – – – – – – Document Number: 001-49263 Rev. *J Page 37 of 58 CY8CLED16P01 Table 10-15. 5V AC Operational Amplifier Specifications (continued) Symbol BWOA Description Gain Bandwidth Product Power = Low, Opamp Bias = Low Power = Medium, Opamp Bias = High Power = High, Opamp Bias = High Noise at 1 kHz (Power = Medium, Opamp Bias = High) Min Typ Max Units Notes ENOA 0.75 3.1 5.4 – – – – 100 – – – – MHz MHz MHz nV/rt-Hz When bypassed by a capacitor on P2[4], the noise of the analog ground signal distributed to each block is reduced by a factor of up to 5 (14 dB). This is at frequencies above the corner frequency defined by the on-chip 8.1k resistance and the external capacitor. Figure 10-5. Typical AGND Noise with P2[4] Bypass   nV/rtHz 10000 0 0.01 0.1 1.0 10 1000 100 0.001 0.01 0.1 Freq (kHz) 1 10 100 At low frequencies, the opamp noise is proportional to 1/f, power independent, and determined by device geometry. At high frequencies, increased power level reduces the noise spectrum level. Figure 10-6. Typical Opamp Noise nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000 100 10 0.001 0.01 0.1 Freq (kHz) 1 10 100 Document Number: 001-49263 Rev. *J Page 38 of 58 CY8CLED16P01 10.4.4 AC Low Power Comparator Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 10-16. AC Low Power Comparator Specifications Symbol TRLPC Description LPC response time Min – Typ – Max 50 Units s Notes  50 mV overdrive comparator reference set within VREFLPC. 10.4.5 AC Digital Block Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 10-17. AC Digital Block Specifications Function All functions Timer Description Block input clock frequency VDD  4.75 V Input clock frequency No capture, VDD 4.75 V With capture Capture pulse width Counter Input clock frequency No enable input, VDD  4.75 V With enable input Enable input pulse width Dead Band Kill pulse width Asynchronous restart mode Synchronous restart mode Disable mode Input clock frequency VDD  4.75 V CRCPRS (PRS Mode) CRCPRS (CRC Mode) SPIM SPIS Input clock frequency VDD  4.75 V Input clock frequency Input clock frequency Input clock (SCLK) frequency Width of SS_negated between transmissions Transmitter Input clock frequency VDD  4.75 V, 2 stop bits VDD  4.75 V, 1 stop bit Receiver Input clock frequency VDD  4.75 V, 2 stop bits VDD  4.75 V, 1 stop bit – – – – 49.2 24.6 MHz MHz – – – – 49.2 24.6 MHz MHz The baud rate is equal to the input clock frequency divided by 8 – – – – 50 [9] Min – – – 50[9] – – 50[9] 20 50[9] 50[9] – Typ – – – – – – – – – – – – – – – – Max 49.2 49.2 24.6 – 49.2 24.6 – – – – 49.2 49.2 24.6 8.2 4.1 – Unit MHz MHz MHz ns MHz MHz ns ns ns ns MHz MHz MHz MHz MHz ns Notes The SPI serial clock (SCLK) frequency is equal to the input clock frequency divided by 2 The input clock is the SPI SCLK in SPIS mode The baud rate is equal to the input clock frequency divided by 8 Note 9. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period). Document Number: 001-49263 Rev. *J Page 39 of 58 CY8CLED16P01 10.4.6 AC Analog Output Buffer Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 10-18. 5V AC Analog Output Buffer Specifications Symbol TROB Description Rising Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High Falling Settling Time to 0.1%, 1V Step, 100 pF Load Power = Low Power = High Rising Slew Rate (20% to 80%), 1V Step, 100 pF Load Power = Low Power = High Falling Slew Rate (80% to 20%), 1V Step, 100 pF Load Power = Low Power = High Small Signal Bandwidth, 20mVpp, 3 dB BW, 100 pF Load Power = Low Power = High Large Signal Bandwidth, 1Vpp, 3 dB BW, 100 pF Load Power = Low Power = High Min Typ Max Units s s s s Notes – – – – 4 4 TSOB – – – – 3.4 3.4 SRROB 0.5 0.5 – – – – V/s V/s V/s V/s SRFOB 0.55 0.55 – – – – BWOB 0.8 0.8 – – – – MHz MHz BWOB 300 300 – – – – kHz kHz 10.4.7 AC External Clock Specifications The following tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 10-19. 5V AC External Clock Specifications Symbol Description Min Typ Max Units Notes FOSCEXT – – – Frequency High Period Low Period Power Up IMO to Switch 0.093 20.6 20.6 150 – – – – 24.6 5300 – – MHz ns ns µs Document Number: 001-49263 Rev. *J Page 40 of 58 CY8CLED16P01 10.4.8 AC Programming Specifications The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V and -40°C  TA  85°C. Typical parameters apply to 5V at 25°C and are for design guidance only. Table 10-20. AC Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TERASEALL Description Rise Time of SCLK Fall Time of SCLK Data Setup Time to Falling Edge of SCLK Data Hold Time from Falling Edge of SCLK Frequency of SCLK Flash Erase Time (Block) Flash Block Write Time Data Out Delay from Falling Edge of SCLK Flash Erase Time (Bulk) Min 1 1 40 40 0 – – – – – – Typ – – – – – 10 40 – 80 – – Max 20 20 – – 8 – – 45 – 100[10] 200[10] Units ns ns ns ns MHz ms ms ns ms ms ms Notes TPROGRAM_HOT Flash Block Erase + Flash Block Write Time TPROGRAM_COLD Flash Block Erase + Flash Block Write Time Erase all Blocks and protection fields at once 0°C