CY8CLEDAC01
AC/DC Digital Current-Mode Controller
for LED Lighting
Features
Description
■
AC offline input range from 80 to 277 VAC
■
Constant current control with primary-side feedback
■
Energy star compliant for LED lighting
■
Up to 30 W output power range for universal inputs
■
High efficiency (typically > 85 percent)
■
Tight LED current regulation (typically < ± 2.5 percent)
■
Supports up to 130 kHz switching frequency
■
Primary-side sensing eliminates opto-isolators
■
Quasi-resonant operation for highest efficiency and low EMI
■
No external compensation components required
■
Low startup current (typically 10A)
■
Built-in soft start
■
Multiple protection features
❐ Current-sense resistor short protection (CSSP)
❐ Over-temperature protection (OTP)
❐ Output over-voltage protection (OVP)
❐ Peak current limit protection (PCLP)
❐ Output short circuit protection (OSCP)
❐ Single-point fault protection
■
The CY8CLEDAC01 is a digital current-mode controller incorporating proprietary primary side control technology. This new
technology eliminates the cost and complexity in traditional
designs which use opto-isolated feedback and secondary-side
regulation.
The CY8CLEDAC01 uses an advance digital control algorithm
to reduce system design time and improve reliability. The control
algorithm has cycle-by-cycle adaptive digital regulation; this
enables accurate secondary-side constant-current operation
without the need for secondary-side sense and control circuits.
The cycle-by-cycle adaptive digital regulation features fast
dynamic response and tight output regulation using critical
discontinuous conduction mode (CDCM) when driving LED
loads. The control algorithm for cycle-by-cycle regulation has
internal compensation for guaranteed system phase and gain
margins; requiring no external components for loop compensation.
The CY8CLEDAC01 has full featured circuit protection not
normally available with other primary-side control solutions. The
built-in protection features include over-voltage protection,
output short circuit protection, peak current limit protection, and
current-sense resistor short protection, over-temperature
protection.
The CY8CLEDAC01 also operates as a voltage-mode controller
with all the current-mode controller features, allowing it to
operate as a AC-to-DC front-end for intelligent LED controllers
such as Cypress’s PowerPSoC® family.
Applications
❐ Offline LED driver
❐ LED replacement lamps
❐ LED luminaires
❐ Pre-regulator for intelligent DC-to-DC LED controllers
Figure 1. Simplified Application Diagram
ISOLATED FLYBACK
CONVERSION
OPTIONAL POWER
FACTOR CIRCUIT
EMI FILTER
+
AC
+
AC
_
AC Input
+
+
LED
CY8CLEDAC01
NTC
Cypress Semiconductor Corporation
Document Number: 001-54122 Rev. *C
•
1
NC
+
VCC 8
OUTPUT 7
2
VSENSE
3
VIN
ISENSE 6
4
SD
GND
5
CONTROLLER
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised October 26, 2010
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CY8CLEDAC01
Contents
Features ............................................................................. 1
Description ........................................................................ 1
Contents ............................................................................ 2
Logic Block Diagram ........................................................ 3
Functional Description ..................................................... 3
Overview ..................................................................... 3
Constant Current Operation ........................................ 4
Valley Mode Switching ................................................ 4
Protection Features ..................................................... 4
Understanding Primary Feedback ............................... 5
Constant Voltage Operation ........................................ 6
Dynamic Load Transient ............................................. 6
Variable Frequency Operation .................................... 6
Internal Loop Compensation ....................................... 6
PFM Mode at Light Load ............................................. 6
Pin Information ................................................................. 7
Document Number: 001-54122 Rev. *C
Electrical Specifications .................................................. 8
Absolute Maximum Ratings ......................................... 8
Electrical Characteristics ................................................. 9
Typical Performance Characteristics ........................... 10
Ordering Information ...................................................... 12
Ordering Code Definitions ............................................. 12
Packaging Information ................................................... 13
Physical Package Dimensions .................................. 13
Acronyms ........................................................................ 14
Document Conventions ................................................. 14
Units of Measure ....................................................... 14
Document History Page ................................................. 15
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC Solutions ......................................................... 15
Page 2 of 15
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CY8CLEDAC01
Logic Block Diagram
Figure 2. Logic Block Diagram
VIN
3
8
Enable
Startup
ADC
VIN_A
0.2 ~ 2V
VGATE
ISD
SD
Gate
Driver
VSD-TH
+
Digital Logic
Control
VOCP
RSD
8.33kohm
Signal
Conditioning
IPEAK
VVMS
5
ISENSE
+
GND
2
6
1.1V
VFB
VSENSE
OUTPUT
60kohm
SDMODE
4
7
+
ZVin
5kohm
VCC
DAC
0 ~ 1V
VIPK
Functional Description
Overview
The digital logic control block is the main block. All other blocks
are inputs or outputs for the control block.
The control block receives signals to determine the input voltage
(VIN), output voltage (VSENSE), temperature (SD), output
operation (VCC), and output current (ISENSE).
The control block has three output controls; SDMODE (shutdown
mode control), DAC VIPK (current control), and VGATE (gate drive
control).
The control block does not start operation until VCC has charged
to the startup threshold (VCCST) as shown in Figure 3 on page 4.
VCC is charged through a diode connection from VIN. VIN
receives a voltage from a rectified main power input. When VCC
is charged to VCCST, the startup block enables the VIN scaling
resistance (ZVin) and the control block. The startup block also
monitors the VCC level and resets the system when VCC
decreases to a brown-out level (VCCUVL). The reset initiates a
startup sequence where VCC is charged to VCCST level through
a diode connection from VIN.
Document Number: 001-54122 Rev. *C
When the ZVin resistor is enabled, a voltage VIN_A is measurable
by an ADC. The output of the ADC is provided to the control block
for auto-calculation of the VINtON product where tON is the on
time for the flyback MOSFET. After the voltage on VIN_A is above
the startup low voltage threshold (VINSTLOW), the
CY8CLEDAC01 commences an adaptive soft start function. The
soft start control algorithm is applied at startup, during which the
initial output pulses are small and gradually increase until the full
pulse width is achieved.
The VSENSE pin connects to the Signal Conditioning block. The
Signal Conditioning block provides two inputs to the control
block: VFB (Voltage Feed Back) and VVMS (Voltage Valley Mode
Switch). VFB provides over-voltage protection and VCC
measurement. VVMS is the valley switch detection. VFB is
monitored by the control block to determine if the output is
over-voltage. When the control block detects an over-voltage
condition, it enters a shutdown mode and wait for POR to
re-initialize the system. VVMS is monitored by the control block to
determine when the power in the flyback MOSFET is at a
minimum or in a 'valley'. The control block starts the next cycle
at the 'valley' for maximum efficiency and minimum switching
EMI.
Page 3 of 15
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CY8CLEDAC01
The SD pin connects to two blocks; a switched current source
(ISD) and an analog comparator. These two blocks work together
for OTP and optional OVP. For an OTP implementation, the SD
pin can be connected to an external NTC component. The
current source causes a voltage to be developed at the SD pin
which causes the analog comparator's output to be high or low
depending upon a 1 V comparator reference. If the voltage
across the NTC is less than 1 V, the control block enters a
shutdown mode and wait for POR to reinitialize the system.
The ISENSE pin connects to circuitry composed of three blocks:
DAC VIPK, IPEAK comparator, and VOCP comparator. These three
blocks work together for soft-start control, peak current
detection, and over-current protection. The DAC VIPK controls
soft-start, minimizing stress associated with system startup. The
IPEAK comparator monitors the voltage at the ISENSE pin. The
voltage is generated by current flowing through a small external
resistor (RISENSE - not shown). When the ISENSE voltage reaches
1 V, the IPEAK comparator asserts a high to the control block. The
control block shuts off the output and waits for VVMS detection; it
then starts the next cycle. The VOCP comparator provides
primary side over-current protection. When the voltage on
ISENSE reaches 1.1 V, the VOCP signal gets asserted. When
over-current is detected, the control block enters a shutdown
mode and waits for POR to re initialize the system.
The OUTPUT pin connects to the Gate Driver block. The Gate
Driver connects to the OUTPUT pin that in turn connects to the
flyback MOSFET gate pin (not shown). The OUTPUT pin is a
digital control pin that switches between a high level (approximately VCC) and a low level (approximately ground). The
duration for high (tON)and low (tOFF) of the Gate Driver is a
function of the control block operating upon its inputs: VINtON,
VFB, VVMS, SD, IPEAK, VOCP, and VCC.
Figure 3. Device Startup Sequence
current is detected by the ISENSE pin through a resistor from the
MOSFET source to ground.
Valley Mode Switching
To reduce EMI and switching losses in the MOSFET, the
CY8CLEDAC01 employs valley mode switching when operating
in CDCM by switching at the lowest MOSFET VDS (see
Figure 4). It detects valleys in the MOSFET drain voltage
indirectly through the VSENSE pin. This voltage is provided by the
auxiliary winding of the flyback transformer and represents a
copy of the secondary side characteristics (see Figure 7 on page
6).
Figure 4. Valley Mode Switching
Turning on at the lowest VDS generates lowest dV/dt; thus valley
mode switching minimizes switching losses and reduces EMI. To
limit the switching frequency range, the CY8CLEDAC01 can skip
valleys (second cycle in Figure 4) when the switching frequency
becomes too high.
The CY8CLEDAC01 supports valley mode switching in both CC
and constant voltage (CV) modes of operation. This feature is
superior to other quasi-resonant technologies which only support
valley mode switching during constant voltage operation.
Protection Features
The CY8CLEDAC01 has full featured circuit protection not
normally available with other primary-side control solutions.
The built-in protection features include OVP, OSCP, PCLP,
CSSP, and OTP.
In an event a protection is triggered, VCC discharges below
VCCUVL and causes a POR except in case of PCLP. The
controller now initiates a new soft start cycle and continues to
attempt start-up. It is unable to start up until the fault condition is
removed.
Current Sense Resistor Short Protection (CSSP)
Constant Current Operation
Constant current (CC) mode is the normal operating mode for
LED lighting applications. CY8CLEDAC01 operates in CC mode
when VSENSE is set below VSENSENOM. During this mode, the
CY8CLEDAC01 regulates the output current at a constant level
regardless of the output voltage. It operates in critical discontinuous conduction mode (CDCM) while in CC mode.
To achieve CC regulation, the CY8CLEDAC01 senses the load
current indirectly through the primary current. The primary
Document Number: 001-54122 Rev. *C
If the ISENSE sense resistor is shorted, there is a potential danger
of an over-current condition not being detected. The
CY8CLEDAC01 has a separate circuit to detect this fault. This
protection mode is triggered if the ISENSE voltage is below 0.15V
in CC mode and only at heavy loads in CV mode.
Over-Temperature Protection (OTP) and/or Output Over-Voltage
Protection (OVP)
The shutdown (SD) pin along with an external NTC provides
over-temperature protection. The SD pin also provides optional
over-voltage protection by sensing a scaled auxiliary winding
voltage from the flyback transformer using external components.
The CY8CLEDAC01 switches between monitoring an
Page 4 of 15
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CY8CLEDAC01
over-temperature fault and an over-voltage fault on the SD pin
by using the SDMODE control signal (shown in Figure 2 on page
3). For an over-temperature fault the voltage on the NTC is
detected by connecting an internal current source to the pin. For
an over-voltage fault the voltage on the SD pin is checked using
an internal pulldown resistance RSD. The measurements are
made during the last VGATE cycle in the measurement window to
allow transients to settle.(shown in Figure 5)
secondary capacitor CO. When Q1 turns off, D1 conducts and
the stored energy Eg(t) is delivered to the output.
Figure 6. Simplified Flyback Converter
iin(t)
id(t)
ig(t)
vin(t)
AC
+
AC
_
Vo
D1
vg(t)
LP
NP
LS
NS
+
Co
Figure 5. SD Detection
Ts(t)
OVP
Detection
OTP
Detection
Io
Q1
LAUX
NAUX
VGATE
SDMODE
Connected to RSD
Connected to ISD
When SDMODE is high and the voltage across the NTC is lower
than 1 V during normal operation or 1.2 V during start-up an OTP
is triggered. When SDMODE is low and the sensed voltage on the
SD pin is higher than 1 V an OVP fault is triggered.
Output Over-Voltage Protection (OVP)
The CY8CLEDAC01 includes a function that protects against an
output over-voltage. The output voltage is monitored by the
VSENSE pin. The protection is triggered if the voltage at this pin
exceeds the over-voltage threshold VSENSEMAX.
Peak Current Limit Protection (PCLP)
The ISENSE pin of the CY8CLEDAC01 monitors the primary peak
current. This enables cycle-by-cycle peak current control and
limiting. When the primary peak current multiplied by the sense
resistor value is greater than 1.1 V, an over-current condition is
detected and the IC immediately turns off the MOSFET driver.
During the next switching cycle, the driver sends out a regular
switching pulse and turns off again if the OCP threshold is still
reached. Normal switching resumes if the fault is removed and
the OCP threshold is not reached.
Output Short Circuit Protection (OSCP)
The CY8CLEDAC01 includes a function that protects against an
output short circuit. The output voltage is monitored by the
VSENSE pin. The protection is triggered if the voltage at this pin
is below 0.22V.
Note When the VSENSE is at this level, the controller is by default
operating in CC mode and hence an over current condition
cannot happen.
Single Point Fault Protection
The CY8CLEDAC01 detect a short on any of the following pins
ISENSE, VSENSE, VCC, OUTPUT, and SD. Therefore, any single
point fault is protected against.
Understanding Primary Feedback
Figure 6 illustrates a simplified flyback converter. When the
switch Q1 conducts during tON(t), the current ig(t) is directly
drawn from rectified sinusoid vg(t). The energy Eg(t) is stored in
the magnetizing inductance LP. The rectifying diode D1 is
reverse biased and the load current IO is supplied by the
Document Number: 001-54122 Rev. *C
When operating in CC mode, to tightly regulate output current,
information about the load current needs to be accurately
sensed. To achieve CC regulation, this information can be
derived indirectly by sensing the primary current.
When operating in CV mode, to tightly regulate output voltage,
information about the output voltage and load current needs to
be accurately sensed. In the DCM flyback converter, this information can be read through the auxiliary winding.
During the Q1 on time, the load current is supplied from the
output filter capacitor CO. The voltage across LP is vg(t),
assuming the voltage dropped across Q1 is zero. The current in
Q1 ramps up linearly at a rate of:
Equation 1
dig (t )
dt
v g (t )
LP
At the end of on time, the current has ramped up to:
Equation 2
ig _ peak (t )
vg (t ) tON
LP
This current represents a stored energy of:
Equation 3
Eg
LP
i g _ peak (t ) 2
2
When Q1 turns off, ig(t) in LP forces a reversal of polarities on all
windings. Ignoring the commutation time caused by the leakage
inductance LKP at the instant of turn-off, the primary current
transfers to the secondary at a peak amplitude of:
Equation 4
i d (t )
NP
i g _ peak (t )
NS
Assuming the secondary winding is master and the auxiliary
winding is slave, the auxiliary voltage is given by:
Page 5 of 15
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CY8CLEDAC01
Equation 5
VAUX
N AUX
(VO V)
NS
and reflects the output voltage as shown in Figure 7.
Figure 7. Auxiliary Voltage Waveforms
VDROP(sense) is the drop in voltage before the VSENSE signal is
able to show a significant drop in output voltage. This is determined by Vmin or the reference voltage at which a load transient
is detected. The smaller the Vmin is, the smaller is the drop in
voltage.
Equation 6
VDROP ( sense ) VSENSE (nom) VSENSE (min)
VOUT ( design )
VSENSE ( nom )
Remember that a smaller Vmin is less tolerant of noise and can
lead to signal distortion in VSENSE.
The final drop in voltage is due to the time from when VSENSE
drops Vmin to when the next VSENSE signal appears. In the worst
case condition this is how much voltage drops during the longest
switching period.
Equation 7
VDROP ( IC )
I OUT TP ( NoLoad )
COUT
A larger output capacitance in this case greatly reduces the
VDROP(IC).
The voltage at the load differs from the secondary voltage by a
diode drop and IR losses. The diode drop is a function of current,
as are IR losses. Thus, if the secondary voltage is always read
at a constant secondary current, the difference between the
output voltage and the secondary voltage is a fixed V. Further,
if the voltage can be read when the secondary current is small;
for example, at the knee of the auxiliary waveform (see Figure
7), then V is also small. With the CY8CLEDAC01, V can be
ignored.
An internal circuit checks for the falling edge of VSENSE on every
switching cycle. If the falling edge of VSENSE is not detected, the
off-time is extended until the falling edge of VSENSE is detected.
The maximum allowed transformer reset time for the
CY8CLEDAC01 is 75 µs.
The real time waveform analyzer in the CY8CLEDAC01 reads
the auxiliary waveform information cycle by cycle. The part then
generates a feedback voltage VFB. The VFB signal precisely
represents the output voltage and is used to regulate the output
voltage.
The CY8CLEDAC01 incorporates an internal digital error
amplifier with no requirement for external loop compensation.
For a typical power supply design, the loop stability is guaranteed
to provide at least 45 degrees of phase margin and -20 dB of gain
margin.
Constant Voltage Operation
PFM Mode at Light Load
The CY8CLEDAC01 also features a CV mode. It operates in CV
mode when VSENSE is set between VSENSENOM and VSENSEMAX.
After soft start is completed, the digital control block measures
the output conditions. It determines output power levels and
adjusts the control system according to a light load or a heavy
load. It uses CDCM or pulse width modulation (PWM) at high
output power levels and switches to pulse frequency modulation
(PFM) at light loads to minimize power dissipation. The PWM
switching frequency is between 30 kHz and 130 kHz, depending
on the line and load conditions.
The CY8CLEDAC01 normally operates in a fixed frequency
PWM or Critical Discontinuous Conduction Mode when IOUT is
greater than approximately 10 percent of the specified maximum
load current. As the output load IOUT is reduced, the on-time tON
is decreased. The moment the load current drops below 10
percent of nominal, the controller transitions to pulse frequency
modulation (PFM) mode. Thereafter, the on-time is modulated by
the line voltage and the off-time is modulated by the load current.
The device automatically returns to PWM mode when the load
current increases.
Variable Frequency Operation
Internal Loop Compensation
Dynamic Load Transient
There are two components that compose the voltage drop during
a load transient event.
Document Number: 001-54122 Rev. *C
Page 6 of 15
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CY8CLEDAC01
Pin Information
Figure 8. Pin Diagram - 8-Pin SOIC CY8CLEDAC01
NC
1
8
VCC
VSENSE
2
7
OUTPUT
PAD
VIN
3
6
ISENSE
SD
4
5
GND
Table 1. Pin Description - 8-Pin SOIC CY8CLEDAC01
Pin No.
1
2
Name
NC
VSENSE
Type
Analog Input
3
VIN
Analog Input
4
SD
Analog Input
5
6
7
8
GND
ISENSE
OUTPUT
VCC
Ground
Analog Input
Output
Power Input
–
PAD
Exposed Pad
Document Number: 001-54122 Rev. *C
Description
No connection
Sense signal input from auxiliary winding. This provides the secondary voltage
feedback used for output regulation.
Sense signal input from the rectified line voltage. VIN is used for line regulation. The
input line voltage is scaled down using a resistor network, and is used for input
under-voltage and over-voltage protection. This pin also provides the supply current
to the IC during startup.
External shutdown control. This pin should be pulled down to GND using a 20k
resistor if shutdown control is not required.
Ground
Primary current sense. Used for cycle by cycle peak current control.
Gate drive for external MOSFET switch
Power supply for the controller during normal operation. The controller starts up
when VCC reaches 12V (typical) and shuts down when the VCC voltage is below 6V
(typical). A decoupling capacitor should be connected between the VCC pin and
GND.
Connect exposed pad electrically to GND
Page 7 of 15
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CY8CLEDAC01
Electrical Specifications
This section presents the DC and AC electrical specifications of the CY8CLEDAC01, of the PowerPSoC device family. For the most
up to date electrical specifications, confirm that you have the most recent data sheet by going to the web at
http://www.cypress.com/powerpsoc. Specifications are valid for -40 C TA 85 C and TJ 125 C, except where noted.
Absolute Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the device. Not all user guidelines are production tested
Symbol
VCC
ICC
PD
TJ,max
TSTG
TLEAD
JA
VESD
ILU
Description
DC supply voltage range
DC supply current at VCC pin
Output pin voltage
VSENSE pin voltage
VIN pin voltage
ISENSE pin voltage
SD pin voltage
Power Dissipation
Maximum Junction Temperature
Storage Temperature
Lead Temperature
Thermal Resistance Junction-to-ambient
ESD Voltage Rating
Latch Up Current
Document Number: 001-54122 Rev. *C
Min
–0.3
–
–0.3
–0.7
–0.3
–0.3
–0.3
–
–
–65
–
–
–
–100
Typ
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Max
18
20
18
4.0
18
4.0
18
526
125
150
260
160
2000
100
Units
V
mA
V
V
V
V
V
mW
C
C
C
C/W
V
mA
Notes
pin 8, ICC = 20 mA max
pin 8
pin 7
pin 2, ISENSE < 10 mA
pin 3
pin 6
pin 4
TA < 25 C
During IR reflow for < 15 seconds
as per JEDEC JESD22-A114
as per JEDEC JESD78
Page 8 of 15
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CY8CLEDAC01
Electrical Characteristics
VCC=12V; –40C TA 85C unless otherwise specified[1]
Symbol
Description
Min
Typ
Max
Units
Notes
VIN Section (pin 3)
VINSTLOW
IINST
ZIN
Startup low voltage threshold
335
369
406
mV
TA= 25C positive edge
Startup current
–
10
15
A
VIN = 10V, CVCC=10 F
Input impedance
–
5
–
k
After startup
VSENSE Section (pin 2)
–
–
1
A
VSENSE = 2V
VSENSENOM
Nominal voltage threshold
1.523
1.538
1.553
V
TA = 25C negative edge
VSENSEMAX
Output OVP threshold
1.790
1.846
1.900
V
TA = 25C negative edge
IBVS
Input leakage current
OUTPUT Section (pin 7)
RDS(ON)LO
Output low level ON-Resistance
–
40
–
ISINK = 5 mA
RDS(ON)-HP
Output high level ON-Resistance
–
102
–
ISOURCE = 5 mA
tR
Rise time[2]
–
200
300
ns
TA= 25 C; CL = 330 pF; 10 percent to
90 percent
tF
Fall time[2]
–
40
60
ns
TA= 25 C; CL=330 pF; 10 percent to
90 percent
Maximum switching frequency[3]
–
130
140
kHz
–
–
16
V
FSWMAX
Any combination of line and loads
VCC Section (pin 8)
VCCMAX
Maximum operating voltage
VCCST
Startup threshold
10.8
12
13.2
V
VCC rising
VCCUVL
Under-voltage lockout threshold
5.5
6.0
6.6
V
VCC falling
–
3.5
–
mA
ICC
Operating current
CL= 330 pF; VSENSE = 1.5 V
ISENSE Section (pin 6)
VPEAK
Peak limit threshold
VRSNS
ISENSE short protection reference
–
0.15
1.1
–
V
V
VREGTH
CC regulation threshold limit
–
1.0
–
V
0.95
1.0
1.05
V
–
1.2
–
V
SD Section (pin 4)
VSDTH
VSDTHST
Shutdown threshold
Shutdown threshold in startup
IBVSD
Input leakage current
–
–
1.0
A
RSD
Pull-down resistance
7.916
8.333
8.750
k
ISD
Pull-up current source
96
107
118
A
VSD = 1.0 V
Notes
1. Adjust VCC above the startup threshold before setting at 12 V.
2. These parameters are not 100 percent tested, guaranteed by design and characterization.
3. Operating frequency varies based on the line and load conditions, see Functional Description on page 3 for more details.
Document Number: 001-54122 Rev. *C
Page 9 of 15
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CY8CLEDAC01
Typical Performance Characteristics
Figure 9. VCC Supply Current versus VCC
Figure 10. Switching Frequency Percent Change versus
Temperature
Figure 11. Startup Threshold versus Temperature
Figure 12. Internal Reference versus Temperature
Document Number: 001-54122 Rev. *C
Page 10 of 15
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CY8CLEDAC01
Figure 13. TON Compensation Chart
Note
IOUT refers to the difference in constant current limit between 264 VAC and 90 VAC when no RDLY and CDLY are applied.
4.
Document Number: 001-54122 Rev. *C
Page 11 of 15
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CY8CLEDAC01
Ordering Information
Ordering Code
No. of Pins
Package
Temperature Range
CY8CLEDAC01
8
SOIC
–40 C to 85 C
Ordering Code Definitions
CY 8 C LED
AC
01
01 = Non Dimmable
AC = Offline
Family Code: LED = LED Applications
Technology Code: C = CMOS
Marketing Code: 8 = PowerPSoC Family
Company ID: CY = Cypress
Document Number: 001-54122 Rev. *C
Page 12 of 15
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CY8CLEDAC01
Packaging Information
Physical Package Dimensions
Figure 14. 8-Pin Small Outline (SOIC) Package
001-54263 *A
Document Number: 001-54122 Rev. *C
Page 13 of 15
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CY8CLEDAC01
Acronyms
Table 2. Acronyms Used in this Document
Acronym
Description
CDCM
critical discontinuous conduction mode
CSSP
current-sense resistor short protection
CV
constant voltage
OSCP
output short circuit protection
OTP
over-temperature protection
OVP
output over-voltage protection
PCLP
Peak current limit protection
PFM
pulse frequency modulation
PWM
pulse width modulation
Document Conventions
Units of Measure
Table 3. Units of Measure
Symbol
C
dB
Hz
pp
V
KB
ppm
sps
W
A
Unit of Measure
degrees Celsius
decibels
Hertz
peak-to-peak
sigma:one standard deviation
volts
ohms
1024 bytes
parts per million
samples per second
watts
amperes
Document Number: 001-54122 Rev. *C
Symbol
kbit
kHz
k
MHz
M
A
F
H
s
V
Vrms
W
Unit of Measure
1024 bits
kilohertz
kilohms
megahertz
megaohms
microamperes
microfarads
microhenrys
microseconds
microvolts
microvolts
root-mean-square
microwatts
Symbol
mA
ms
mV
mA
nA
ns
nV
pA
pF
ps
fF
Unit of Measure
milliampere
millisecond
millivolts
milliwatts
nanoamperes
nanoseconds
nanovolts
picoamperes
picofarads
picoseconds
femtofarads
Page 14 of 15
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CY8CLEDAC01
Document History Page
Document Title: CY8CLEDAC01 AC/DC Digital Current-Mode Controller for LED Lighting
Document Number: 001-54122
Revision ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
2721319
KJV/AESA
06/19/2009
New data sheet
*A
2829351 KJV/PYRS
12/16/2009
Added Contents. Updated text in Features, Description, and Functional
Description sections. Updated Electrical Specifications
*B
2901104
KJV/VED
03/29/2010
Release to web.
*C
3071772
KJV
10/26/2010
Updated “Pin Information” on page 7. Updated “Packaging Information” on
page 13. Updated Template.
Sales, Solutions, and Legal Information
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© Cypress Semiconductor Corporation, 2009-2010. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-54122 Rev. *C
Revised October 26, 2010
Page 15 of 15
PowerPSoC® and PSoC® are registered trademarks and PSoC Designer™ is a trademark of Cypress Semiconductor Corp. All other trademarks or registered trademarks referenced herein are
property of the respective corporations.
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