CY90F952JDSPMC-GS-UJE1

Please note that Cypress is an Infineon Technologies Company. The document following this cover page is marked as “Cypress” document as this is the company that originally developed the product. Please note that Infineon will continue to offer the product to new and existing customers as part of the Infineon product portfolio. Continuity of document content The fact that Infineon offers the following product as part of the Infineon product portfolio does not lead to any changes to this document. Future revisions will occur when appropriate, and any changes will be set out on the document history page. Continuity of ordering part numbers Infineon continues to support existing part numbers. Please continue to use the ordering part numbers listed in the datasheet for ordering. www.infineon.com CY90F952JDS/F952MDS CY90V950AJAS/V950AMAS F2MC-16LX CY90950 Series 16-bit Microcontrollers The CY90950-series with 2 FULL-CAN interfaces and Flash ROM is especially designed for automotive and other industrial applications. Its main feature are the on-board CAN Interfaces, which conform to V2.0 Part A and Part B, while supporting a very flexible message buffer scheme and so offering more functions than a normal FULL-CAN approach. With the new 0.18m CMOS technology, Cypress now offers on-chip Flash ROM program memory 256 Kbytes. The power to the MCU core (1.8 V) is supplied by a built-in regulator circuit, giving these microcontrollers superior performance in terms of power consumption and tolerance to EMI. Features CPU ■ ■ ■ ■ Instruction system best suited to controller - Wide choice of data types (bit, byte, word, and long word) - Wide choice of addressing modes (23 types) - Enhanced functionality with signed multiply and divide instructions and the RETI instruction - Enhanced high-precision computing with 32-bit accumulator Instruction system compatible with high-level language (C language) and multitask - Employing system stack pointer - Various enhanced pointer indirect instructions - Barrel shift instructions Increased processing speed 4-byte instruction queue 8-bit D/A converter: 2 channels Program patch function Detects address matches against 6 address pointers Timer ■ Time-base timer, watch timer, watchdog timer: 1 channel ■ 8/16-bit PPG timer: 8-bit16 channels, or 16-bit8 channels ■ 16-bit reload timer: 4 channels ■ 16-bit input/output timer - 16-bit free-run timer: 2 channels (FRT0: ICU 0/1/2/3, OCU 0/1/2/3, FRT1: ICU 4/5/6/7, OCU 4/5/6/7) - 16-bit input capture: (ICU): 8 channels - 16-bit output compare: (OCU): 8 channels Serial interface ■ ■ UART (LIN/SCI): 7 channels - Equipped with full-duplex double buffer - Clock-asynchronous or clock-synchronous serial transmission is available I2C interface: 2 channels Up to 400 kbps transfer rate Interrupt controller ■ Powerful 8-level, 34-condition interrupt feature ■ Up to 16 external interrupts are supported ■ Automatic data transfer function independent of CPU Expanded intelligent I/O service function (EI2OS): up to 16 channels DMA function: up to 16 channels I/O ports ■ General-purpose input/output port (CMOS output) : 82 ports 8/10-bit A/D converter: 24 channels Conversion time: 3 s (at 32-MHz machine clock, including sampling time) FULL-CAN controller ■ 2 channels ■ Compliant with Ver2.0A and Ver2.0B CAN specifications ■ 16 built-in message buffers ■ CAN wake-up function Low power consumption (standby) mode ■ Sleep mode (a mode that halts CPU operating clock) ■ Timebase timer mode (a mode where only the oscillation clock, sub clock, timebase timer and watch timer operate) ■ Watch mode (a mode that operates sub clock and clock timer only) ■ Stop mode (a mode that stops oscillation clock and sub clock) ■ CPU intermittent operation mode ■ Resolution is selectable between 8-bit and 10-bit. Technology ■ Activation by external trigger input is allowed. 0.18 m CMOS technology Cypress Semiconductor Corporation Document Number: 002-04500 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised April 10, 2018 CY90950 Series Contents Product Lineup ................................................................ 3 Pin Assignments .............................................................. 5 Pin Description ................................................................. 7 I/O Circuit Types ............................................................. 14 Handling Devices............................................................ 19 Block Diagrams .............................................................. 22 Memory Map.................................................................... 24 I/O Map ........................................................................... 25 CAN Controllers.............................................................. 35 Interrupt Factors, Interrupt Vectors, Interrupt Control Register ........................................................................... 42 Electrical Characteristics............................................... 44 Absolute Maximum Ratings....................................... 44 Document Number: 002-04500 Rev. *C Recommended Operating Conditions ....................... 46 DC Characteristics .................................................... 47 AC Characteristics..................................................... 49 A/D Converter............................................................ 69 Definition of A/D Converter Terms ........................... 70 Notes on A/D Converter Section ............................... 72 Flash Memory Program/Erase Characteristics ......... 74 D/A Converter ................................................................... 74 Ordering Information...................................................... 75 Package Dimensions...................................................... 76 Major Changes................................................................ 78 Document History .......................................................... 79 Sales, Solutions, and Legal Information ...................... 80 Page 2 of 80 CY90950 Series 1. Product Lineup Part Number CY90V950AJAS CY90V950AMAS CY90F952JDS CY90F952MDS Parameter Type Evaluation products Flash memory products 2 CPU System clock F MC-16LX CPU On-chip PLL clock multiplier (1, 2, 3, 4, 6, 8, 1/2 when PLL stops) Minimum instruction execution time : 31.25 ns (4 MHz osc. PLL8) ROM External Main 256 Kbytes Satellite 32 Kbytes RAM 30 Kbytes 16 Kbytes Yes  Emulator-specific power supply*1 FPGA data*2 Adaptor board*2   Rev 050617 CY2147-20 Rev.04C or later Clock supervisor Yes No Yes No Clock calibration unit Yes No Yes No No (CPU operation detection reset only) No Yes No Low-voltage/CPU operation detection reset Technology 0.35 m CMOS with built-in power supply regulator Operating voltage range 5 V  10 Operating ambient temperature Package 0.18 m CMOS with built-in power supply regulator  Flash memory with Charge pump for programming voltage 3.0 V to 5.5 V 4.0 V to 5.5 V 4.5 V to 5.5 V : When normal operating : When Flash programming : When using the external bus  40C to 105C PGA-299 QFP-100, LQFP-100 7 channels UART Wide range of baud rate settings using a dedicated reload timer Special synchronous options for adapting to different synchronous serial protocols LIN functionality working either as master or slave LIN device I2C (400 kbps) 2 channels 24 input channels A/D Converter 10-bit or 8-bit resolution Conversion time : Min 3 s include sample time (per one channel) 16-bit Reload Timer (4 channels) Operation clock frequency : fsys/21, fsys/23, fsys/25 (fsys  Machine clock frequency) Supports External Event Count function 16-bit I/O Timer (2 channels) Generates an interrupt signal on overflow Supports Timer Clear when the output compare finds a match Operation clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24, fsys/25, fsys/26, fsys/27 (fsys  Machine clock freq.) I/O Timer 0 (clock input FRCK0) corresponds to ICU0/1/2/3, OCU 0/1/2/3 I/O Timer 1 (clock input FRCK1) corresponds to ICU4/5/6/7, OCU 4/5/6/7 16-bit Output Compare (8 channels) Generates an interrupt signal when one of the 16-bit I/O timer matches the output compare register A pair of compare registers can be used to generate an output signal. 16-bit Input Capture (8 channels) Holds free-run timer on rising edge, falling edge or rising & falling edge Signals an interrupt upon external event Document Number: 002-04500 Rev. *C Page 3 of 80 CY90950 Series Part Number CY90V950AJAS CY90V950AMAS CY90F952JDS CY90F952MDS Parameter 8/16-bit Programmable Pulse Generator 8 channels (16-bit) /16 channels (8-bit) Sixteen 8-bit reload counters Sixteen 8-bit reload registers for L pulse width Sixteen 8-bit reload registers for H pulse width Supports 8-bit and 16-bit operation modes A pair of 8-bit reload counters can be configured as one 16-bit reload counter or as 8-bit prescaler plus 8-bit reload counter Operating clock freq. : fsys, fsys/21, fsys/22, fsys/23, fsys/24 or 128 s@fosc  4 MHz (fsys  Machine clock frequency, fosc  Oscillation clock frequency) 3 channels CAN Interface External Interrupt (16 channels) 2 channels Conforms to CAN Specification Version 2.0 Part A and B Automatic re-transmission in case of error Automatic transmission in response to Remote Frames Prioritized 16 message buffers for data and ID’s Supports multiple messages Flexible configuration of acceptance filtering : Full bit compare/Full bit mask/Two partial bit masks Supports up to 1 Mbps Can be used rising edge, falling edge, starting up by H/L level input, external interrupt, expanded intelligent I/O services (EI2OS) and DMA D/A converter Sub clock I/O Ports 2 channels Yes No Yes No Virtually all external pins can be used as general purpose I/O port All ports are push-pull outputs Bit-wise settable as input/output or peripheral signal Can be configured 8 as CMOS schmitt trigger/ automotive inputs (in blocks of 8 pins) TTL input level settable for external bus (32-pin only for external bus) Flash Memory  Supports automatic programming, Embedded Algorithm Write/Erase/Erase-Suspend/Resume commands A flag indicating completion of the algorithm Boot block configuration Erase can be performed on each block Block protection with external programming voltage Flash Security Feature for protecting the content of the Flash *1 : It is setting of Jumper switch (TOOL VCC) when Emulator (CY2147-01) is used. Please refer to the Emulator hardware manual for details. *2 : Customers considering the use of other FPGA data and the adaptor boards should consult with sales representatives. Document Number: 002-04500 Rev. *C Page 4 of 80 CY90950 Series 2. Pin Assignments ■ CY90F952JDS, CY90F952MDS MD0 RST 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 76 50 77 49 78 48 47 79 46 80 45 81 44 82 43 83 42 84 41 85 40 86 39 87 38 88 37 89 36 90 35 91 34 92 33 93 32 94 31 95 30 96 29 97 98 28 99 27 100 26 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 MD1 MD2 P75/AN21/INT5 P74/AN20/INT4 P73/AN19/INT3 P72/AN18/INT2 P71/AN17/INT1 P70/AN16/INT0 Vss P67/AN7/PPGE(F) P66/AN6/PPGC(D) P65/AN5/PPGA(B) P64/AN4/PPG8(9) P63/AN3/PPG6(7) P62/AN2/PPG4(5) P61/AN1/PPG2(3) P60/AN0/PPG0(1) AVss AVRL AVRH AVcc P57/AN15/DA1 P56/AN14/DA0 P55/AN13 P54/AN12/TOT3 P32/WRL/WR/INT10R P33/WRH P34/HRQ/OUT4 P35/HAK/OUT5 P36/RDY/OUT6 P37/CLK/OUT7 P40 P41 Vcc Vss C P42/IN6/RX1/INT9R P43/IN7/TX1 P44/SDA0/FRCK0 P45/SCL0/FRCK1 P46/SDA1 P47/SCL1 P50/AN8/SIN2 P51/AN9/SOT2 P52/AN10/SCK2 P53/AN11/TIN3 LQFP - 100 P26/A22/IN2 P27/A23/IN3 P30/ALE/IN4 P31/RD/IN5 P01/AD01/INT9 P02/AD02/INT10 P03/AD03/INT11 P04/AD04/INT12 P05/AD05/INT13 P06/AD06/INT14 P07/AD07/INT15 P10/AD08/TIN1 P11/AD09/TOT1 P12/AD10/SIN3/INT11R P13/AD11/SOT3 P14/AD12/SCK3 Vcc Vss X1 X0 P15/AD13/SIN4 P16/AD14/SOT4 P17/AD15/SCK4 P20/A16/PPG9(8) P21/A17/PPGB(A) P22/A18/PPGD(C) P23/A19/PPGF(E) P24/A20/IN0 P25/A21/IN1 P81/TOT0/CKOT/INT13R P80/TIN0/ADTG/INT12R P77/AN23/INT7 P76/AN22/INT6 P00/AD00/INT8 PA1/TX0 PA0/RX0/INT8R P97/OUT3 P96/OUT2/SCK6 P95/OUT1/SOT6 P94/OUT0/SIN6 P93/PPG7(6) P92/PPG5(4)/SCK5 P91/PPG3(2)/SOT5 P90/PPG1(0)/SIN5 Vss Vcc P87/SCK1 P86/SOT1 P85/SIN1 P84/SCK0/INT15R P83/SOT0/TOT2 P82/SIN0/TIN2/INT14R (TOP VIEW) (LQI100) Document Number: 002-04500 Rev. *C Page 5 of 80 CY90950 Series MD2 RST 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 81 82 49 83 48 84 47 85 46 86 45 87 44 88 43 89 42 90 41 91 40 92 39 93 38 94 37 95 36 96 35 97 34 98 33 99 32 100 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 P75/AN21/INT5 P74/AN20/INT4 P73/AN19/INT3 P72/AN18/INT2 P71/AN17/INT1 P70/AN16/INT0 Vss P67/AN7/PPGE(F) P66/AN6/PPGC(D) P65/AN5/PPGA(B) P64/AN4/PPG8(9) P63/AN3/PPG6(7) P62/AN2/PPG4(5) P61/AN1/PPG2(3) P60/AN0/PPG0(1) AVss AVRL AVRH AVcc P57/AN15/DA1 P36/RDY/OUT6 P37/CLK/OUT7 P40 P41 Vcc Vss C P42/IN6/RX1/INT9R P43/IN7/TX1 P44/SDA0/FRCK0 P45/SCL0/FRCK1 P46/SDA1 P47/SCL1 P50/AN8/SIN2 P51/AN9/SOT2 P52/AN10/SCK2 P53/AN11/TIN3 P54/AN12/TOT3 P55/AN13 P56/AN14/DA0 P34/HRQ/OUT4 P35/HAK/OUT5 P31/RD/IN5 P32/WRL/WR/INT10R P33/WRH QFP - 100 P24/A20/IN0 P25/A21/IN1 P26/A22/IN2 P27/A23/IN3 P30/ALE/IN4 P04/AD04/INT12 P05/AD05/INT13 P06/AD06/INT14 P07/AD07/INT15 P10/AD08/TIN1 P11/AD09/TOT1 P12/AD10/SIN3/INT11R P13/AD11/SOT3 P14/AD12/SCK3 Vcc Vss X1 X0 P15/AD13/SIN4 P16/AD14/SOT4 P17/AD15/SCK4 P20/A16/PPG9(8) P21/A17/PPGB(A) P22/A18/PPGD(C) P23/A19/PPGF(E) MD0 MD1 P03/AD03/INT11 P02/AD02/INT10 P01/AD01/INT9 P00/AD00/INT8 PA1/TX0 PA0/RX0/INT8R P97/OUT3 P96/OUT2/SCK6 P95/OUT1/SOT6 P94/OUT0/SIN6 P93/PPG7(6) P92/PPG5(4)/SCK5 P91/PPG3(2)/SOT5 P90/PPG1(0)/SIN5 Vss Vcc P87/SCK1 P86/SOT1 P85/SIN1 P84/SCK0/INT15R P83/SOT0/TOT2 P82/SIN0/TIN2/INT14R P81/TOT0/CKOT/INT13R P80/TIN0/ADTG/INT12R P77/AN23/INT7 P76/AN22/INT6 (TOP VIEW) (PQH100) Document Number: 002-04500 Rev. *C Page 6 of 80 CY90950 Series 3. Pin Description Pin No. Pin Name LQFP100*1 QFP100*2 90 92 X1 91 93 X0 52 54 RST I/O Circuit Type*3 A E 77 to 84 AD00 to AD07 G INT8 to INT15 84 85 G I/O pin of the external address/data bus (AD08). This function is enabled when the external bus is enabled. TIN1 Event input pin for the reload timer 1 P11 General purpose I/O port The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. G TOT1 AD10 Output pin for the reload timer 1 N SIN3 External interrupt request input pin for INT11R General purpose I/O port The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. P13 G AD11 I/O pin of the external address/data bus (AD11). This function is enabled when the external bus is enabled. SOT3 Serial data output pin for UART3 General purpose I/O port The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. P14 87 I/O pin of the external address/data bus (AD10). This function is enabled when the external bus is enabled. Serial data input pin for UART3 INT11R 88 I/O pin of the external address/data bus (AD09). This function is enabled when the external bus is enabled. General purpose I/O port The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. P12 86 I/O pins for 8 lower bits of the external address/data bus. This function is enabled when the external bus is enabled. AD08 86 87 Reset input pin General purpose I/O port The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. AD09 85 Oscillation input pin External interrupt request input pins for INT8 to INT15. P10 83 Oscillation output pin General purpose I/O ports The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. P00 to P07 75 to 82 Function 89 G AD12 I/O pin of the external address/data bus (AD12). This function is enabled when the external bus is enabled. SCK3 Clock I/O pin for UART3 Document Number: 002-04500 Rev. *C Page 7 of 80 CY90950 Series Pin No. LQFP100*1 QFP100*2 Pin Name I/O Circuit Type*3 General purpose I/O port The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. P15 92 93 94 N AD13 I/O pin of the external address/data bus (AD13). This function is enabled when the external bus is enabled. SIN4 Serial data input pin for UART4 P16 General purpose I/O port The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. 95 G AD14 I/O pin of the external address/data bus (AD14). This function is enabled when the external bus is enabled. SOT4 Serial data output pin for UART4 General purpose I/O port The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. P17 94 96 G AD15 I/O pin of the external address/data bus (AD15). This function is enabled when the external bus is enabled. SCK4 Clock I/O pin for UART4 General purpose I/O ports The register can be set to select whether to use a pull-up resistor.In external bus mode, the pin is enabled as a general-purpose I/O port when the corresponding bit in the external address output control register (HACR) is 1. P20 to P23 95 to 98 97 to 100 G A16 to A19 PPG9, PPGB, PPGD, PPGF 1 to 4 General purpose I/O ports The register can be set to select whether to use a pull-up resistor. In external bus mode, the pin is enabled as a general-purpose I/O port when the corresponding bit in the external address output control register (HACR) is 1. G A20 to A23 A20 to A23 for output pins of the external address/data bus. When the corresponding bit in the external address output control register (HACR) is 0, the pins are enabled as high address output pins (A20 to A23). IN0 to IN3 Data sample input pins for input capture ICU0 to ICU3. General purpose I/O port The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. P30 3 A16 to A19 for output pins of the external address/data bus. When the corresponding bit in the external address output control register (HACR) is 0, the pins are enabled as high address output pins (A16 to A19). Output pins for PPGs P24 to P27 99, 100, 1, 2 Function 5 G ALE Address latch enable output pin. This function is enabled when the external bus is enabled. IN4 Data sample input pin for input capture ICU4. Document Number: 002-04500 Rev. *C Page 8 of 80 CY90950 Series Pin No. LQFP100*1 QFP100*2 Pin Name I/O Circuit Type*3 General purpose I/O port The register can be set to select whether to use a pull-up resistor. This function is enabled in single-chip mode. P31 4 5 6 G RD External read strobe output pin for data bus. This function is enabled when the external bus is enabled. IN5 Data sample input pin for input capture ICU5. P32 General purpose I/O port The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or when the WR/WRL pin output is disabled. 7 G WRL/ WR INT10R 7 8 G Write strobe output pin for the upper 8 bits of the external data bus. This function is enabled when the external bus is enabled, when the external bus 16-bit mode is selected, and when the WRH output pin is enabled. P34 General purpose I/O port The register can be set to select whether to use a pull-up resistor.This function is enabled either in single-chip mode or when the hold function is disabled. 9 G HRQ Hold request input pin. This function is enabled when both the external bus and the hold function are enabled. OUT4 Waveform output pin for output compare OCU4. General purpose I/O port The register can be set to select whether to use a pull-up resistor.This function is enabled either in single-chip mode or when the hold function is disabled. 10 G HAK OUT5 11 Hold acknowledge output pin. This function is enabled when both the external bus and the hold function are enabled. Waveform output pin for output compare OCU5. P36 9 General purpose I/O port The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or when the WRH pin output is disabled. WRH P35 8 Write strobe output pin for the external data bus. This function is enabled when both the external bus and the WR/WRL pin output are enabled. WRL is used to write-strobe 8 lower bits of the data bus in 16-bit access while WR is used to write-strobe 8 bits of the data bus in 8-bit access. External interrupt request input pin for INT10R. P33 6 Function G General purpose I/O port The register can be set to select whether to use a pull-up resistor. This function is enabled either in single-chip mode or when the external ready function is disabled. RDY Ready input pin. This function is enabled when both the external bus and the external ready function are enabled. OUT6 Waveform output pin for output compare OCU6. Document Number: 002-04500 Rev. *C Page 9 of 80 CY90950 Series Pin No. LQFP100*1 QFP100*2 Pin Name I/O Circuit Type*3 P37 10 12 G OUT7 13, 14 P40, P41 Waveform output pin for output compare OCU7. F P42 16 18 IN6 RX1 F IN7 F SDA0 General purpose I/O port H FRCK0 21 SCL0 General purpose I/O port H FRCK1 20 22 21 23 P46 SDA1 P47 SCL1 23 24 25 AN8 H H O 25 26 27 28 Serial data I/O pin for I2C 1 General purpose I/O port Serial clock I/O pin for I2C 1 Analog input pin for the A/D converter SIN2 Serial data input pin for UART2 P51 General purpose I/O port AN9 I AN10 Analog input pin for the A/D converter Serial data output pin for UART2 P52 26 General purpose I/O port General purpose I/O port SOT2 24 Serial clock I/O pin for I2C 0 Input pin for the 16-bit I/O Timer1 P50 22 Serial data I/O pin for I2C 0 Input pin for the 16-bit I/O Timer 0 P45 19 Data sample input pin for input capture ICU7. TX Output pin for CAN1 P44 20 RX input pin for CAN1 Interface General purpose I/O port TX1 18 Data sample input pin for input capture ICU6. External interrupt request input pin for INT9R. P43 19 General purpose I/O ports General purpose I/O port INT9R 17 General purpose I/O port The register can be set to select whether to use a pull-up resistor.This function is enabled either in single-chip mode or when the clock output is disabled. Clock output pin. This function is enabled when both the external bus and clock output are enabled. CLK 11, 12 Function General purpose I/O port I Analog input pin for the A/D converter SCK2 Clock I/O pin for UART2 P53 General purpose I/O port AN11 I Analog input pin for the A/D converter TIN3 Event input pin for the reload timer 3 P54 General purpose I/O port AN12 TOT3 Document Number: 002-04500 Rev. *C I Analog input pin for the A/D converter Output pin for the reload timer 3 Page 10 of 80 CY90950 Series Pin No. LQFP100*1 QFP100*2 27 29 Pin Name P55 AN13 I/O Circuit Type*3 I P56, P57 28, 29 30, 31 AN14, AN15 36 to 43 J 45 to 50, 55, 56 General purpose I/O ports AN0 to AN7 Analog input pins for the A/D converter PPG0, PPG2, PPG4, PPG6, PPG8, PPGA, PPGC, PPGE I Output pins for PPGs AN16 to AN23 General purpose I/O ports I TIN0 ADTG General purpose I/O port F INT12R 58 TOT0 CKOT F SIN0 TIN2 M SOT0 F SCK0 General purpose I/O port F INT15R 60 62 61 63 P85 SIN1 P86 SOT1 Document Number: 002-04500 Rev. *C Serial data output pin for UART 0 Output pin for the reload timer 2 P84 61 Event input pin for the reload timer 2 General purpose I/O port TOT2 59 Serial data input pin for UART0 External interrupt request input pin for INT14R P83 60 Output pin for the clock monitor General purpose I/O port INT14R 58 Output pin for the reload timer 0 External interrupt request input pin for INT13R P82 59 Trigger input pin for the A/D converter General purpose I/O port INT13R 57 Event input pin for the reload timer 0 External interrupt request input pin for INT12R P81 56 Analog input pins for the A/D converter External interrupt request input pins for INT0 to INT7 P80 57 Analog input pins for the A/D converter P60 to P67 INT0 to INT7 55 Analog input pin for the A/D converter Analog output pins for the D/A converter P70 to P77 43 to 48, 53, 54 General purpose I/O port General purpose I/O ports DA0,DA1 34 to 41 Function Clock I/O pin for UART0 External interrupt request input pin for INT15R M F General purpose I/O port Serial data input pin for UART1 General purpose I/O port Serial data output pin for UART1 Page 11 of 80 CY90950 Series Pin No. LQFP100*1 QFP100*2 62 64 Pin Name P87 SCK1 I/O Circuit Type*3 F P90 65 66 67 68 PPG1 M 70 P91 General purpose I/O port PPG3 F PPG5 P93 PPG7 70 71 72 OUT0 Serial data output pin for UART5 F F 72 74 M 75 Serial data input pin for UART6 P95 General purpose I/O port OUT1 F OUT2 76 30 32 Waveform output pin for output compare for OCU1.This function is enabled when the waveform output is enabled. Serial data output pin for UART6 General purpose I/O port F Waveform output pin for output compare for OCU2. This function is enabled when the waveform output is enabled. SCK6 Clock I/O pin for UART6 P97 General purpose I/O port OUT3 F RX0 PA1 TX0 AVCC Waveform output pin for output compare for OCU3. This function is enabled when the waveform output is enabled. General purpose I/O port F INT8R 74 Waveform output pin for output compare for OCU0. This function is enabled when the waveform output is enabled. SIN6 PA0 73 General purpose I/O port Output pin for PPGs General purpose I/O port P96 73 Output pin for PPGs Clock I/O pin for UART5 SOT6 71 Output pin for PPGs General purpose I/O port P94 69 Output pin for PPGs Serial data input pin for UART5 SCK5 68 Clock I/O pin for UART1 SIN5 P92 69 General purpose I/O port General purpose I/O port SOT5 67 Function RX input pin for CAN0 Interface. Outputs generated by other functions must be stopped when using the CAN functions. External interrupt request input pin for INT8R F General purpose I/O port TX Output pin for CAN0 K VCC power input pin for the Analog circuit 31 33 AVRH L Reference voltage input pin for the A/D Converter. This power supply must be turned on or off while a voltage higher than or equal to AVRH is applied to AVCC. 32 34 AVRL K Lower reference voltage input pin for the A/D Converter 33 35 AVSS K VSS power input pin for the Analog circuit 50, 51 52, 53 MD1, MD0 C Input pins for specifying the operating mode Document Number: 002-04500 Rev. *C Page 12 of 80 CY90950 Series Pin No. Pin Name I/O Circuit Type*3 D LQFP100*1 QFP100*2 49 51 MD2 13, 63, 88 15, 65, 90 VCC 14, 42, 64, 89 16, 44, 66, 91 VSS   15 17 C K Function Input pin for specifying the operating mode Power (3.5 V to 5.5 V) input pins Power (0 V) input pins This is the power supply stabilization capacitor. This pin should be connected to a ceramic capacitor with a capacitance greater than or equal to 0.1 F. *1 : LQI100 *2 : PQH100 *3 : For I/O circuit type, refer to “I/O Circuit Types”. Document Number: 002-04500 Rev. *C Page 13 of 80 CY90950 Series 4. I/O Circuit Types Type Circuit Remarks A X1 X out Oscillation circuit High-speed oscillation feedback resistor = approx. 1 M (Flash memory product) X0 Standby control signal X1 X out Oscillation circuit High-speed oscillation feedback resistor = approx. 1 M (Evaluation product) X0 Standby control signal B X1A Xout Oscillation circuit Low-speed oscillation feedback resistor = approx. 10 M X0A Standby control signal C R CMOS hysteresis inputs D Pull-up control R Pout Evaluation products: CMOS hysteresis input Flash memory products: CMOS input pin Evaluation products: • CMOS hysteresis input • Pull-down resistor value: approx. 50 k Flash memory products: • CMOS input • No pull-down Nout Document Number: 002-04500 Rev. *C Page 14 of 80 CY90950 Series Type Circuit Remarks E • CMOS hysteresis input • Pull-up resistor value: approx. 50 k Pull-up Resistor R CMOS hysteresis inputs F P-ch Pout N-ch Nout • CMOS level output (IOL = 4 mA, IOH  4 mA) • CMOS hysteresis input (VIH 0.8 VCC VIL 0.2 VCC) (with function to disconnect input during standby) • Automotive input (with function to disconnect input during standby) R CMOS hysteresis input Automotive input Standby control for input shutdown G Pull-up control P-ch P-ch N-ch Pout Nout R • CMOS level output (IOL = 4 mA, IOH  4 mA) • CMOS hysteresis input (VIH 0.8 VCC VIL 0.2 VCC) (with function to disconnect input during standby) • Automotive input (with function to disconnect input during standby) • TTL input (with function to disconnect input during standby) • Programmable pull-up resistor: 50 k approx. CMOS hysteresis input Automotive input TTL input Standby control for input shutdown Document Number: 002-04500 Rev. *C Page 15 of 80 CY90950 Series Type Circuit Remarks H P-ch Pout N-ch Nout R CMOS hysteresis input • CMOS level output (IOL = 3 mA, IOH  3 mA) • CMOS hysteresis input (VIH 0.8 VCC VIL 0.2 VCC) (with function to disconnect input during standby) • Automotive input (with function to disconnect input during standby) • CMOS hysteresis input (VIH 0.7 VCC VIL 0.3 VCC) (with function to disconnect input during standby) Automotive input Standby control for input shutdown I P-ch Pout N-ch Nout R • CMOS level output (IOL = 4 mA, IOH  4 mA) • CMOS hysteresis input (VIH 0.8 VCC VIL 0.2 VCC) (with function to disconnect input during standby) • Automotive input (with function to disconnect input during standby) • A/D converter analog input CMOS hysteresis input Automotive input Standby control for input shutdown Analog input J P-ch Pout N-ch Nout R CMOS hysteresis input • CMOS level output (IOL = 4 mA, IOH  4 mA) • D/A analog output • CMOS hysteresis input (VIH 0.8 VCC VIL 0.2 VCC) (with function to disconnect input during standby) • Automotive input (with function to disconnect input during standby) • A/D converter analog input • D/A converter analog output Automotive input Standby control for input shutdown Analog input Analog output Document Number: 002-04500 Rev. *C Page 16 of 80 CY90950 Series Type Circuit Remarks K Power supply input protection circuit P-ch N-ch L ANE P-ch AVR N-ch A/D converter reference voltage power supply input pin, with the protection circuit Flash memory devices do not have a protection circuit against VCC for pin AVRH ANE M P-ch Pout N-ch Nout R CMOS hysteresis input • CMOS level output (IOL = 4 mA, IOH  4 mA) • CMOS hysteresis input (VIH 0.8 VCC VIL 0.2 VCC) (with function to disconnect input during standby) • Automotive input (with function to disconnect input during standby) • CMOS hysteresis input (VIH 0.7 VCC VIL 0.3 VCC) (with function to disconnect input during standby) Automotive input CMOS hysteresis input Standby control for input shutdown Document Number: 002-04500 Rev. *C Page 17 of 80 CY90950 Series Type Circuit N Remarks Pull-up control P-ch P-ch Pout N-ch Nout R CMOS hysteresis input • CMOS level output (IOL = 4 mA, IOH  4 mA) • CMOS hysteresis input (VIH 0.8 VCC VIL 0.2 VCC) (with function to disconnect input during standby) • Automotive input (with function to disconnect input during standby) • TTL input (with function to disconnect input during standby) • CMOS hysteresis input (VIH 0.7 VCC VIL 0.3 VCC) (with function to disconnect input during standby) • Programmable pull-up resistor: 50 k approx Automotive input CMOS hysteresis input TTL input Standby control for input shutdown O P-ch Pout N-ch Nout R CMOS hysteresis input • CMOS level output (IOL = 4 mA, IOH  4 mA) • CMOS hysteresis input (VIH 0.8 VCC VIL 0.2 VCC) (with function to disconnect input during standby) • Automotive input (with function to disconnect input during standby) • CMOS hysteresis input (VIH 0.7 VCC VIL 0.3 VCC) (with function to disconnect input during standby) • A/D converter analog input Automotive input CMOS hysteresis input Standby control for input shutdown Analog input Document Number: 002-04500 Rev. *C Page 18 of 80 CY90950 Series 5. Handling Devices ■ Preventing Latch-up CMOS IC chips may suffer latch-up under the following conditions: • A voltage higher than VCC or lower than VSS is applied to an input or output pin. • A voltage higher than the rated voltage is applied between VCC and VSS pins. • The AVCC power supply is applied before the VCC voltage. Latch-up may increase the power supply current drastically, causing thermal damage to the device. For the same reason, also be careful not to let the analog power-supply voltage (AVCC, AVRH) exceed the digital power-supply voltage. ■ Handling Unused Pins Leaving unused input pins open may result in misbehavior or latch-up and possible permanent damage to the device. Therefore they must be pulled up or pulled down through resistors. In this case those resistors should be more than 2 k. Unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. ■ Power Supply Pins (VCC/VSS) • If there are multiple VCC and VSS pins, that are designed to be set to the same potential are connected the inside of the device to prevent malfunctions such as latch-up. To reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output current, be sure to connect the VCC and VSS pins to the power supply and ground externally. Connect VCC and VSS pins to the device from the current supply source at a low impedance. • As a measure against power supply noise, connect a capacitor of about 0.1 F as a bypass capacitor between VCC and VSS pins in the vicinity of VCC and VSS pins of the device Vcc Vss Vcc Vss Vss Vcc CY90950 Series Vcc Vss Vss ■ Vcc Mode Pins (MD0 to MD2) Connect the mode pins directly to VCC or VSS pins. To prevent the device unintentionally entering test mode due to noise, lay out the printed circuit board so as to minimize the distance from the mode pins to VCC or VSS pins and to provide a low-impedance connection. ■ Sequence for Turning On the Power Supply to the A/D Converter and Analog Inputs Make sure to turn on the A/D converter power supply (AVCC, AVRH, AVRL) and analog inputs (AN0 to AN23) after turning-on the digital power supply (VCC). Turn-off the digital power after turning off the A/D converter supply and analog inputs. In this case, make sure that the voltage does not exceed AVRH or AVCC (turning on/off the analog and digital power supplies simultaneously is acceptable). ■ Pin connection when A/D Converter is Not Used Connect unused pins of A/D converter to AVCC  VCC, AVSS  AVRH  AVRL  VSS. Document Number: 002-04500 Rev. *C Page 19 of 80 CY90950 Series ■ Crystal Oscillator Circuit The X0, X1 pins may be possible causes of abnormal operation. Make sure to provide bypass capacitors via the shortest distance from X0, X1 pins and crystal oscillator (or ceramic oscillator) and ground lines, and make sure, to the utmost effort, that the oscillation circuit lines do not cross the lines of other circuits. It is highly recommended to provide a printed circuit board art work surrounding X0, X1 pins with a ground area for stabilizing the operation. For each of the mass-production products, request an oscillator evaluation from the manufacturer of the oscillator you are using. ■ Pull-up/down Resistors The CY90950 Series does not support internal pull-up/down resistors (except for the pull-up resistors built into ports 0 to 3). Use external components where needed. ■ Using External Clock The external clock inputs can not be used. ■ Notes on Operation in PLL Clock Mode If PLL clock mode is selected, the microcontroller attempt to be working with the self-oscillating circuit even when there is no external oscillator or the external clock input is stopped. Performance of this operation, however, cannot be guaranteed. ■ Notes on Power-On To prevent the internal regulator circuit from malfunctioning, set the voltage rise time during power-on to 50 s or more (0.2 V to 2.7 V) . ■ Stabilization of Power Supply Voltage A sudden change in the supply voltage may cause the device to malfunction even within the specified VCC supply voltage operating range. Therefore, the VCC supply voltage should be stabilized. Stabilize the power supply voltage as follows as a standard level of stabilization. • VCC ripple variations (peak-to-peak value) at commercial frequencies (50 Hz/60 Hz) fall below 10 of the standard VCC supply voltage • The coefficient of fluctuation does not exceed 0.1 V/ms at instantaneous power switching. ■ Initialization In the device, there are internal registers which are initialized only by a power-on reset. To initialize these registers, turn on the power again. ■ Port 0 to Port 3 Output During Power-on (External-bus Mode) As shown below, when the power is turned on in External-Bus mode, there is a possibility that output signal of Port 0 to Port 3 might be unstable irrespective of the reset input. 1/2VCC VCC Port0 to Port3 Port0 to Port3 outputs might be unstable Document Number: 002-04500 Rev. *C Port0 to Port3 outputs = Hi-Z Page 20 of 80 CY90950 Series ■ Notes on Using the CAN Function To use the CAN function, please set the DIRECT bit of the CAN Direct Mode Register (CDMR) to 1. If the DIRECT bit is set to '0' (initial value) only CY90V950AJAS and CY90V950AMAS, wait states will be performed when accessing CAN registers. Note : Please refer to the Hardware Manual of the CY90950 series for detail of CAN Direct Mode Register. ■ Flash Security Function A security bit is located in the area of the Flash memory. If protection code 01H is written in the security bit, the Flash memory is in the protected state by security. Therefore please do not write 01H in this address if you do not use the security function. Refer to following table for the address of the security bit. CY90F952JDS, CY90F952MDS Document Number: 002-04500 Rev. *C Flash Memory Size Address of the Security Bit Embedded 2 Mbits Flash Memory FC0001H Page 21 of 80 CY90950 Series 6. Block Diagrams ■ CY90V950AJAS,CY90V950AMAS X0,X1 Clock Controller RST CR oscillation circuit* 16LX CPU Clock calibration unit* I/O Timer 0 FRCK0 Input Capture 8 channels IN7 to IN0 RAM 30 Kbytes Output Compare 8 channels OUT7 to OUT0 Prescaler 7 channels I/O Timer 1 UART 7 channels CAN Controller 3 channels CPU Operation detection circuit* AVCC AVSS AN23 to AN0 AVRH AVRL ADTG DA01, DA00 16-bit Reload Timer 4 channels 8/10-bit A/D converter 24 channels 8-bit D/A converter 2 channels RX2 to RX0 TX2 to TX0 TIN3 to TIN0 TOT3 to TOT0 AD15 to AD00 F2MC-16 Bus SOT6 to SOT0 SCK6 to SCK0 SIN6 to SIN0 FRCK1 A23 to A16 ALE External Bus Interface RD WR/WRL WRH HRQ PPGF to PPG0 SDA1, SDA0 SCL1, SCL0 HAK 8/16-bit PPG 16 channels I2C Interface 2 channels DMAC * : Only for CY90V950AJAS Document Number: 002-04500 Rev. *C RDY CLK DTP/External Interrupt 16 channels Clock Monitor INT15 to INT8 (INT15R to INT8R) INT7 to INT0 CKOT Page 22 of 80 CY90950 Series ■ CY90F952JDS, CY90F952MDS X0,X1 Clock Controller RST CR oscillation circuit* 16LX CPU Clock calibration unit* Low voltage detection circuit CPU operation detection circuit* RAM 16 Kbytes Flash 256 Kbytes +32 Kbytes AN23 to AN16 AVRH AVRL ADTG UART 7 channels 8/10-bit A/D converter 16/24 channels DA01, DA00 8-bit D/A converter 2 channels PPGF to PPG0 8/16-bit PPG 16 channels SDA1, SDA0 SCL1, SCL0 I2C Interface 2 channels DMAC Input Capture 8 channels IN7 to IN0 Output Compare 8 channels OUT7 to OUT0 CAN Controller 2 channels 16-bit Reload Timer 4 channels FRCK1 RX0, RX1 TX0, TX1 TIN3 to TIN0 TOT3 to TOT0 AD15 to AD00 F2MC-16 Bus AVCC AVSS AN15 to AN0 FRCK0 I/O Timer 1 Prescaler 7 channels SOT6 to SOT0 SCK6 to SCK0 SIN6 to SIN0 I/O Timer 0 A23 to A16 ALE External Bus Interface RD WR/WRL WRH HRQ HAK RDY CLK DTP/External Interrupt 16 channels Clock Monitor INT15 to INT8 (INT15R to INT8R) INT7 to INT0 CKOT * : Only for devices with a J suffix in the part number Document Number: 002-04500 Rev. *C Page 23 of 80 CY90950 Series 7. Memory Map CY90V950AJAS, CY90V950AMAS FFFFFFH FFFFFFH ROM (FF bank) FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H FBFFFFH FB0000H FAFFFFH FA0000H F9FFFFH F90000H F8FFFFH F80000H 00FFFFH 008000H 007FFFH 007900H 0078FFH CY90F952JDS, CY90F952MDS ROM (FE bank) ROM (FD bank) ROM (FC bank) ROM (FF bank) FF0000H FEFFFFH FE0000H FDFFFFH FD0000H FCFFFFH FC0000H ROM (FE bank) ROM (FD bank) ROM (FC bank) ROM (FB bank) ROM (FA bank) ROM (F9 bank) F77FFFH F70000H F6FFFFH External access area ROM (F8 bank) External access area ROM (image of FF bank) Peripheral RAM 30 Kbytes ROM (Satellite) 00FFFFH 008000H 007FFFH ROM (image of FF bank) Peripheral 007900H 003FFFH RAM 16 Kbytes 000100H 0000EFH 000000H 000100H External access area Peripheral 0000EFH 000000H External access area Peripheral : Not accessible Note: An image of the data in the FF bank of ROM is visible in the upper part of bank 00, which makes it possible for the C compiler to use the small memory model. The lower 16 bits of addresses in the FF bank are the same as the lower 16 bits of addresses in the 00 bank so that tables stored in the ROM can be accessed without using the far specifier in the pointer declaration. For example, when the address 00C000H is accessed, the data at FFC000H in ROM is actually accessed. The ROM area in bank FF exceeds 32 Kbytes, and its entire image cannot be shown in bank 00. As a result, the image between FF8000H and FFFFFFH is visible in bank 00, while the image between FF0000H and FF7FFFH is visible only in bank FF. Document Number: 002-04500 Rev. *C Page 24 of 80 CY90950 Series 8. I/O Map Address Register Abbreviation Access Resource Name Initial Value 000000H Port 0 Data Register PDR0 R/W Port 0 XXXXXXXXB 000001H Port 1 Data Register PDR1 R/W Port 1 XXXXXXXXB 000002H Port 2 Data Register PDR2 R/W Port 2 XXXXXXXXB 000003H Port 3 Data Register PDR3 R/W Port 3 XXXXXXXXB 000004H Port 4 Data Register PDR4 R/W Port 4 XXXXXXXXB 000005H Port 5 Data Register PDR5 R/W Port 5 XXXXXXXXB 000006H Port 6 Data Register PDR6 R/W Port 6 XXXXXXXXB 000007H Port 7 Data Register PDR7 R/W Port 7 XXXXXXXXB 000008H Port 8 Data Register PDR8 R/W Port 8 XXXXXXXXB 000009H Port 9 Data Register PDR9 R/W Port 9 XXXXXXXXB 00000AH Port A Data Register PDRA R/W Port A 111111XXB 00000BH Analog Input Enable Register 5 ADER5 R/W Port 5, A/D 11111111B 00000CH Analog Input Enable Register 6 ADER6 R/W Port 6, A/D 11111111B 00000DH Analog Input Enable Register 7 ADER7 R/W Port 7, A/D 11111111B 00000EH Input Level Select Register 0 ILSR0 R/W Port 0 to 7 XXXXXXXXB XXXX0XXXB 00000FH Input Level Select Register 1 ILSR1 R/W Port 0 to 3, Port 8 to A 000010H Port 0 Direction Register DDR0 R/W Port 0 00000000B 000011H Port 1 Direction Register DDR1 R/W Port 1 00000000B 000012H Port 2 Direction Register DDR2 R/W Port 2 00000000B 000013H Port 3 Direction Register DDR3 R/W Port 3 00000000B 000014H Port 4 Direction Register DDR4 R/W Port 4 00000000B 000015H Port 5 Direction Register DDR5 R/W Port 5 00000000B 000016H Port 6 Direction Register DDR6 R/W Port 6 00000000B 000017H Port 7 Direction Register DDR7 R/W Port 7 00000000B 000018H Port 8 Direction Register DDR8 R/W Port 8 00000000B 000019H Port 9 Direction Register DDR9 R/W Port 9 00000000B 00001AH Port A Direction Register DDRA R/W Port A 00000100B 00001CH Port 0 Pull-up Control Register PUCR0 R/W Port 0 00000000B 00001DH Port 1 Pull-up Control Register PUCR1 R/W Port 1 00000000B 00001EH Port 2 Pull-up Control Register PUCR2 R/W Port 2 00000000B 00001FH Port 3 Pull-up Control Register PUCR3 R/W Port 3 00000000B 000020H Serial Mode Register 0 SMR0 W, R/W 000021H Serial Control Register 0 SCR0 W, R/W 00000000B RDR0/TDR0 R/W 00000000B/ 11111111B SSR0 R, R/W R, W, R/W 00001BH Reserved 00000000B 000022H Reception/Transmission Data Register 0 000023H Serial Status Register 0 000024H Extended Communication Control Register 0 ECCR0 000025H Extended Status/Control Register 0 ESCR0 R/W 00000X00B 000026H Baud Rate Generator Register 00 BGR00 R, R/W 00000000B 000027H Baud Rate Generator Register 01 BGR01 R, R/W 00000000B Document Number: 002-04500 Rev. *C UART0 00001000B 000000XXB Page 25 of 80 CY90950 Series Address Register Abbreviation Access Resource Name Initial Value 000028H Serial Mode Register 1 SMR1 W, R/W 00000000B 000029H Serial Control Register 1 SCR1 W, R/W 00000000B 00002AH Reception/Transmission Data Register 0 RDR1/TDR1 R/W 00000000B/ 11111111B 00002BH Serial Status Register 1 SSR1 R, R/W 00002CH Extended Communication Control Register 1 ECCR1 R, W, R/W 00002DH Extended Status/Control Register 1 ESCR1 R/W 00000X00B 00002EH Baud Rate Generator Register 10 BGR10 R, R/W 00000000B 00002FH Baud Rate Generator Register 11 BGR11 R, R/W 00000000B 000030H PPG0 Operation Mode Control Register PPGC0 W, R/W 000031H PPG1 Operation Mode Control Register PPGC1 W, R/W 000032H PPG0/PPG1 Count Clock Select Register PPG01 R/W 000033H UART1 00001000B 000000XXB 16-bit PPG0/PPG1 01000111B 01000001B 00000010B Reserved 000034H PPG2 Operation Mode Control Register PPGC2 W, R/W 000035H PPG3 Operation Mode Control Register PPGC3 W, R/W 000036H PPG2/PPG3 Count Clock Select Register PPG23 R/W 000037H 16-bit PPG2/PPG3 01000111B 01000001B 00000010B Reserved 000038H PPG4 Operation Mode Control Register PPGC4 W, R/W 000039H PPG5 Operation Mode Control Register PPGC5 W, R/W 00003AH PPG4/PPG5 Clock Select Register PPG45 R/W 00003BH Address Detect Control Register 1 PACSR1 R/W 00003CH PPG6 Operation Mode Control Register PPGC6 W, R/W 00003DH PPG7 Operation Mode Control Register PPGC7 W, R/W 00003EH PPG6/PPG7 Count Clock Select Register PPG67 R/W 000040H PPG8 Operation Mode Control Register PPGC8 000041H PPG9 Operation Mode Control Register PPGC9 W, R/W 000042H PPG8/PPG9 Count Clock Select Register PPG89 R/W 000044H PPGA Operation Mode Control Register PPGCA 000045H PPGB Operation Mode Control Register PPGCB W, R/W 000046H PPGA/PPGB Count Clock Select Register PPGAB R/W 000048H PPGC Operation Mode Control Register PPGCC 000049H PPGD Operation Mode Control Register PPGCD W, R/W 00004AH PPGC/PPGD Count Clock Select Register PPGCD R/W 00004CH PPGE Operation Mode Control Register PPGCE 00004DH PPGF Operation Mode Control Register PPGCF W, R/W 00004EH PPGE/PPGF Count Clock Select Register PPGEF R/W 00003FH 16-bit PPG4/PPG5 01000111B 01000001B 00000010B Address Match Detection 1 16-bit PPG6/PPG7 11000000B 01000111B 01000001B 00000010B Reserved 000043H W, R/W 16-bit PPG8/PPG9 01000111B 01000001B 00000010B Reserved 000047H W, R/W 16-bit PPGA/PPGB 01000111B 01000001B 00000010B Reserved 00004BH W, R/W 16-bit PPGC/PPGD 01000111B 01000001B 00000010B Reserved 00004FH Document Number: 002-04500 Rev. *C W, R/W 16-bit PPGE/PPGF 01000111B 01000001B 00000010B Reserved Page 26 of 80 CY90950 Series Address Register Abbreviation Access Resource Name Initial Value 000050H Input Capture Control Status 0/1 ICS01 R/W 000051H Input Capture Edge 0/1 ICE01 R/W, R 000052H Input Capture Control Status 2/3 ICS23 R/W 000053H Input Capture Edge 2/3 ICE23 R 000054H Input Capture Control Status 4/5 ICS45 R/W 000055H Input Capture Edge 4/5 ICE45 R 000056H Input Capture Control Status 6/7 ICS67 R/W 000057H Input Capture Edge 6/7 ICE67 R/W, R 000058H Output Compare Control Status 0 OCS0 R/W 000059H Output Compare Control Status 1 OCS1 R/W 00005AH Output Compare Control Status 2 OCS2 R/W 00005BH Output Compare Control Status 3 OCS3 R/W 00005CH Output Compare Control Status 4 OCS4 R/W 00005DH Output Compare Control Status 5 OCS5 R/W 00005EH Output Compare Control Status 6 OCS6 R/W 00005FH Output Compare Control Status 7 OCS7 R/W 000060H Timer Control Status 0 TMCSR0 R/W 000061H Timer Control Status 0 TMCSR0 R/W 000062H Timer Control Status 1 TMCSR1 R/W 000063H Timer Control Status 1 TMCSR1 R/W 000064H Timer Control Status 2 TMCSR2 R/W 000065H Timer Control Status 2 TMCSR2 R/W 000066H Timer Control Status 3 TMCSR3 R/W 000067H Timer Control Status 3 TMCSR3 R/W 000068H A/D Control Status 0 ADCS0 R/W 00011110B 000069H A/D Control Status 1 ADCS1 R/W 00000001B 00006AH A/D Data 0 ADCR0 R 00006BH A/D Data 1 ADCR1 R 00006CH ADC Setting 0 ADSR0 R/W 00000000B 00006DH ADC Setting 1 ADSR1 R/W 00000000B 00006EH Low Voltage/CPU OPeration Detection Reset Control Register LVRC R/W Low Voltage/CPU Operation Detection Reset 00111000B 00006FH ROM Mirror Function Setting ROMM W ROM Mirror 11111101B 000070H to 00008FH Reserved for CAN Controller 000090H to 00009AH Reserved 00009BH DMA Descriptor Channel Specified Register DCSR R/W 00009CH DMA Status Register L DSRL R/W 00009DH DMA Status Register H DSRH R/W 00009EH Address Detect Control Register 0 PACSR0 R/W Document Number: 002-04500 Rev. *C Input Capture 0/1 Input Capture 2/3 Input Capture 4/5 Input Capture 6/7 Output Compare 0/1 Output Compare 2/3 Output Compare 4/5 Output Compare 6/7 00000000B 111010XXB 00000000B 111111XXB 00000000B 111100XXB 00000000B 111000XXB 00001100B 01100000B 00001100B 01100000B 00001100B 01100000B 00001100B 01100000B 00000000B 16-bit reload timer 0 11110000B 16-bit reload timer 1 11110000B 16-bit reload timer 2 11110000B 16-bit reload timer 3 11110000B A/D Converter 00000000B 00000000B 00000000B 00000000B 11111100B 00000000B DMA 00000000B 00000000B Address Match Detection 0 11000000B Page 27 of 80 CY90950 Series Address Register Abbreviation Access Resource Name Initial Value 00009FH Delayed Interrupt Trigger/Release Register DIRR R/W Delayed Interrupt Generation Module 11111110B 0000A0H Low-power Mode Control Register LPMCR W, R/W Low Power Control Circuit 00011000B 0000A1H Clock Selection Register CKSCR R, R/W Low Power Control Circuit 11111100B DMA 00000000B 0000A2H, 0000A3H Reserved 0000A4H DMA Stop Status Register DSSR R/W 0000A5H Automatic Ready Function Select Register ARSR W 0000A6H External Address Output Control Register HACR W 0000A7H Bus Control Signal Selection Register ECSR W 0000A8H Watchdog Control Register WDTC 0000A9H Time Base Timer Control Register 0000AAH Watch Timer Control Register 0000ABH 00111100B External Memory Access 00000000B R, W Watchdog Timer X1XXX111B TBTC W, R/W Time Base Timer 11100100B WTC R, R/W Watch Timer 1X001000B 00000001B Reserved 0000ACH DMA Enable Register L DERL R/W 0000ADH DMA Enable Register H DERH R/W 0000AEH Flash Control Status Register (Flash memory devices only) FMCS R, R/W 0000B0H Interrupt Control Register 00 ICR00 W, R/W 00000111B 0000B1H Interrupt Control Register 01 ICR01 W, R/W 00000111B 0000B2H Interrupt Control Register 02 ICR02 W, R/W 00000111B 0000B3H Interrupt Control Register 03 ICR03 W, R/W 00000111B 0000B4H Interrupt Control Register 04 ICR04 W, R/W 00000111B 0000B5H Interrupt Control Register 05 ICR05 W, R/W 00000111B 0000B6H Interrupt Control Register 06 ICR06 W, R/W 00000111B 0000B7H Interrupt Control Register 07 ICR07 W, R/W 0000B8H Interrupt Control Register 08 ICR08 W, R/W 0000AFH DMA Flash Memory 00000000B 00000000B 000X0000B Reserved Interrupt Control 00000111B 00000111B 0000B9H Interrupt Control Register 09 ICR09 W, R/W 00000111B 0000BAH Interrupt Control Register 10 ICR10 W, R/W 00000111B 0000BBH Interrupt Control Register 11 ICR11 W, R/W 00000111B 0000BCH Interrupt Control Register 12 ICR12 W, R/W 00000111B 0000BDH Interrupt Control Register 13 ICR13 W, R/W 00000111B 0000BEH Interrupt Control Register 14 ICR14 W, R/W 00000111B 0000BFH Interrupt Control Register 15 ICR15 W, R/W 00000111B 0000C0H D/A Converter Data 0 DAT0 R/W XXXXXXXXB 0000C1H D/A Converter Data 1 DAT1 R/W 0000C2H D/A Control 0 DACR0 R/W 0000C3H D/A Control 1 DACR1 R/W Document Number: 002-04500 Rev. *C D/A Converter XXXXXXXXB 00000000B 00000000B Page 28 of 80 CY90950 Series Address Register Abbreviation 0000C4H, 0000C5H Access Resource Name Initial Value DTP/External Interrupt 0 Reserved 0000C6H External Interrupt Enable 0 ENIR0 R/W 00000000B 0000C7H External Interrupt Source 0 EIRR0 R/W XXXXXXXXB 0000C8H Detection Level Setting 0 ELVR0 R/W 0000C9H Detection Level Setting 0 ELVR0 R/W 0000CAH External Interrupt Enable 1 ENIR1 R/W 00000000B 0000CBH External Interrupt Source 1 EIRR1 R/W XXXXXXXXB 0000CCH Detection Level Setting 1 ELVR1 R/W 0000CDH Detection Level Setting 1 ELVR1 R/W 0000CEH External Interrupt Source Select EISSR R/W 0000CFH PLL/Sub clock Control Register PSCCR W 0000D0H DMA Buffer Address Pointer L Register BAPL R/W XXXXXXXXB 0000D1H DMA Buffer Address Pointer M Register BAPM R/W XXXXXXXXB 0000D2H DMA Buffer Address Pointer H Register 0000D3H DMA Control Register 0000D4H 00000000B 00000000B DTP/External Interrupt 1 00000000B 00000000B 00000000B PLL 11110000B BAPH R/W XXXXXXXXB DMACS R/W XXXXXXXXB I/O Register Address Pointer L Register IOAL R/W 0000D5H I/O Register Address Pointer H Register IOAH R/W 0000D6H Data Counter L Register DCTL R/W XXXXXXXXB 0000D7H Data Counter H Register DCTH R/W XXXXXXXXB 0000D8H Serial Mode Register 2 SMR2 W, R/W 00000000B 0000D9H Serial Control Register 2 SCR2 W, R/W 00000000B 0000DAH Reception/Transmission Data Register 2 RDR2/TDR2 R/W 00000000B/ 11111111B 0000DBH Serial Status Register 2 SSR2 R, R/W 0000DCH Extended Communication Control Register 2 ECCR2 R, W, R/W 0000DDH Extended Status Control Register 2 ESCR2 R/W 00000X00B 0000DEH Baud Rate Generator Register 20 BGR20 R, R/W 00000000B 0000DFH Baud Rate Generator Register 21 BGR21 R, R/W 00000000B DMA XXXXXXXXB XXXXXXXXB UART2 00001000B 000000XXB 0000E0H to 0000EFH Reserved for CAN Controller 2. Refer to “CAN Controllers” 0000F0H to 0000FFH External 007900H Reload Register L0 PRLL0 R/W 007901H Reload Register H0 PRLH0 R/W 007902H Reload Register L1 PRLL1 R/W 007903H Reload Register H1 PRLH1 R/W XXXXXXXXB 007904H Reload Register L2 PRLL2 R/W XXXXXXXXB 007905H Reload Register H2 PRLH2 R/W 007906H Reload Register L3 PRLL3 R/W 007907H Reload Register H3 PRLH3 R/W Document Number: 002-04500 Rev. *C XXXXXXXXB 16-bit PPG0/PPG1 16-bit PPG2/PPG3 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Page 29 of 80 CY90950 Series Address Register Abbreviation Access Resource Name Initial Value XXXXXXXXB 007908H Reload Register L4 PRLL4 R/W 007909H Reload Register H4 PRLH4 R/W 00790AH Reload Register L5 PRLL5 R/W 00790BH Reload Register H5 PRLH5 R/W XXXXXXXXB 00790CH Reload Register L6 PRLL6 R/W XXXXXXXXB 00790DH Reload Register H6 PRLH6 R/W 00790EH Reload Register L7 PRLL7 R/W 00790FH Reload Register H7 PRLH7 R/W XXXXXXXXB 007910H Reload Register L8 PRLL8 R/W XXXXXXXXB 007911H Reload Register H8 PRLH8 R/W 007912H Reload Register L9 PRLL9 R/W 007913H Reload Register H9 PRLH9 R/W XXXXXXXXB 007914H Reload Register LA PRLLA R/W XXXXXXXXB 007915H Reload Register HA PRLHA R/W 007916H Reload Register LB PRLLB R/W 007917H Reload Register HB PRLHB R/W XXXXXXXXB 007918H Reload Register LC PRLLC R/W XXXXXXXXB 007919H Reload Register HC PRLHC R/W 00791AH Reload Register LD PRLLD R/W 00791BH Reload Register HD PRLHD R/W XXXXXXXXB 00791CH Reload Register LE PRLLE R/W XXXXXXXXB 00791DH Reload Register HE PRLHE R/W 00791EH Reload Register LF PRLLF R/W 00791FH Reload Register HF PRLHF R/W XXXXXXXXB 007920H Input Capture 0 IPCP0 R 00000000B 007921H Input Capture 0 IPCP0 R 007922H Input Capture 1 IPCP1 R 007923H Input Capture 1 IPCP1 R 00000000B 007924H Input Capture 2 IPCP2 R 00000000B 007925H Input Capture 2 IPCP2 R 007926H Input Capture 3 IPCP3 R 007927H Input Capture 3 IPCP3 R 00000000B 007928H Input Capture 4 IPCP4 R 00000000B 007929H Input Capture 4 IPCP4 R 00792AH Input Capture 5 IPCP5 R 00792BH Input Capture 5 IPCP5 R 00000000B 00792CH Input Capture 6 IPCP6 R 00000000B 00792DH Input Capture 6 IPCP6 R 00792EH Input Capture 7 IPCP7 R 00792FH Input Capture 7 IPCP7 R 16-bit PPG4/PPG5 16-bit PPG6/PPG7 16-bit PPG8/PPG9 16-bit PPGA/PPGB 16-bit PPGC/PPGD 16-bit PPGE/PPGF Input Capture 0/1* Input Capture 2/3* Input Capture 4/5* Input Capture 6/7* XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B 00000000B * : The Initial values of CY90V950AJAS and CY90V950AMAS are XXXXXXXXB. Document Number: 002-04500 Rev. *C Page 30 of 80 CY90950 Series Address Register Abbreviation Access Resource Name Initial Value 007930H Output Compare 0 OCCP0 R/W 007931H Output Compare 0 OCCP0 R/W 007932H Output Compare 1 OCCP1 R/W 007933H Output Compare 1 OCCP1 R/W XXXXXXXXB 007934H Output Compare 2 OCCP2 R/W XXXXXXXXB 007935H Output Compare 2 OCCP2 R/W 007936H Output Compare 3 OCCP3 R/W 007937H Output Compare 3 OCCP3 R/W XXXXXXXXB 007938H Output Compare 4 OCCP4 R/W XXXXXXXXB 007939H Output Compare 4 OCCP4 R/W 00793AH Output Compare 5 OCCP5 R/W XXXXXXXXB Output Compare 0/1 Output Compare 2/3 Output Compare 4/5 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 00793BH Output Compare 5 OCCP5 R/W XXXXXXXXB 00793CH Output Compare 6 OCCP6 R/W XXXXXXXXB 00793DH Output Compare 6 OCCP6 R/W 00793EH Output Compare 7 OCCP7 R/W 00793FH Output Compare 7 OCCP7 R/W XXXXXXXXB 007940H Timer Data 0 TCDT0 R/W 00000000B 007941H Timer Data 0 TCDT0 R/W 007942H Timer Control Status 0 TCCSL0 R/W 007943H Timer Control Status 0 TCCSH0 R/W 01100000B 007944H Timer Data 1 TCDT1 R/W 00000000B 007945H Timer Data 1 TCDT1 R/W 007946H Timer Control Status 1 TCCSL1 R/W 007947H Timer Control Status 1 TCCSH1 R/W 01100000B R/W XXXXXXXXB 007948H 007949H 00794AH 00794BH 00794CH 00794DH 00794EH 00794FH Timer 0/Reload 0 TMR0/TMRLR0 Timer 1/Reload 1 TMR1/TMRLR1 Timer 2/Reload 2 TMR2/TMRLR2 Timer 3/Reload 3 TMR3/TMRLR3 R/W R/W R/W R/W R/W R/W R/W Output Compare 6/7 I/O Timer 0 I/O Timer 1 XXXXXXXXB XXXXXXXXB 00000000B 00000000B 00000000B 00000000B 16-bit Reload Timer 0 XXXXXXXXB 16-bit Reload Timer 1 XXXXXXXXB 16-bit Reload Timer 2 XXXXXXXXB 16-bit Reload Timer 3 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB 007950H Serial Mode Register 3 SMR3 W, R/W 007951H Serial Control Register 3 SCR3 W, R/W 00000000B 007952H Reception/Transmission Data Register 3 RDR3/TDR3 R/W 00000000B/ 11111111B 007953H Serial Status Register 3 SSR3 R, R/W 007954H Extended Communication Control Register 3 ECCR3 R, W, R/W 007955H Extended Status Control Register 3 ESCR3 R/W 00000X00B 007956H Baud Rate Generator Register 30 BGR30 R, R/W 00000000B 007957H Baud Rate Generator Register 31 BGR31 R, R/W 00000000B Document Number: 002-04500 Rev. *C 00000000B UART3 00001000B 000000XXB Page 31 of 80 CY90950 Series Address Register Abbreviation Access Resource Name Initial Value 007958H Serial Mode Register 4 SMR4 W, R/W 007959H Serial Control Register 4 SCR4 W, R/W 00000000B 00795AH Reception/Transmission Data Register 4 RDR4/TDR4 R/W 00000000B/ 11111111B 00795BH Serial Status Register 4 SSR4 R, R/W 00795CH Extended Communication Control Register 4 ECCR4 R, W, R/W 00795DH Extended Status Control Register 4 ESCR4 R/W 00000X00B 00795EH Baud Rate Generator Register 40 BGR40 R, R/W 00000000B 00795FH Baud Rate Generator Register 41 BGR41 R, R/W 00000000B 007960H Clock Supervisor Control Register CSVCR R/W Clock Supervisor 00011100B R/W Clock Monitor 11110000 B CDMR R/W CAN Clock Sync 11111110 B CANSWR R/W CAN 0/1 11111100 B IBSR0 R 00000000B 007961H to 00796BH 00796CH Clock Output Enable Register CAN Direct Mode Register 00796FH CAN Switch Register 007970H I2C Bus Status Register 0 007973H 007974H 00001000B 000000XXB CLKR Reserved 00796EH 007972H UART4 Reserved 00796DH 007971H 00000000B 2 I C Bus Control Register 0 I2C 10-bit Slave Address Register 0 I2 C IBCR0 W, R/W 00000000B ITBAL0 R/W 00000000B ITBAH0 R/W 00000000B ITMKL0 R/W ITMKH0 R/W 00111111B 11111111B 007975H 10-bit Slave Address Mask Register 0 007976H I2 C ISBA0 R/W 00000000B 007977H I2C 7-bit Slave Address Mask Register 0 ISMK0 R/W 01111111B 007978H I2C Data Register 0 IDAR0 R/W 00000000B 7-bit Slave Address Register 0 007979H, 00797AH 00797BH Reserved I2C Clock Control Register 0 00797CH to 00797FH I2C Bus Status Register 1 007981H I2 C 007983H 007984H ICCR0 R/W I2C Interface 0 00011111B Reserved 007980H 007982H I2C Interface 0 Bus Control Register 1 I2C 10-bit Slave Address Register 1 I2 C IBSR1 R 00000000B IBCR1 W, R/W 00000000B ITBAL1 R/W 00000000B ITBAH1 R/W ITMKL1 R/W 00000000B I2C Interface 1 11111111B 007985H 10-bit Slave Address Mask Register 1 ITMKH1 R/W 00111111B 007986H I2C 7-bit Slave Address Register 1 ISBA1 R/W 00000000B 007987H I2C 7-bit Slave Address Mask Register 1 ISMK1 R/W 01111111B IDAR1 R/W 00000000B 007988H 2 I C Data Register 1 007989H, 00798AH Document Number: 002-04500 Rev. *C Reserved Page 32 of 80 CY90950 Series Address 00798BH Register 2 I C Clock Control Register 1 00798CH to 00798FH Abbreviation ICCR1 Access R/W Resource Name 2 I C Interface1 Initial Value 00011111B Reserved 007990H Serial Mode Register 5 SMR5 W, R/W 00000000B 007991H Serial Control Register 5 SCR5 W, R/W 00000000B 007992H Reception/Transmission Data Register 5 RDR5/TDR5 R/W 00000000B/ 11111111B 007993H Serial Status Register 5 SSR5 R, R/W 007994H Extended Communication Control Register 5 ECCR5 R, W, R/W 007995H Extended Status Control Register 5 ESCR5 R/W 00000X00B 007996H Baud Rate Generator Register 50 BGR50 R, R/W 00000000B 007997H Baud Rate Generator Register 51 BGR51 R, R/W 00000000B 007998H Serial Mode Register 6 SMR6 W, R/W 00000000B 007999H Serial Control Register 6 SCR6 W, R/W 00000000B RDR6/TDR6 R/W 00000000B/ 11111111B UART5 00001000B 000000XXB 00799AH Reception/Transmission Data Register 6 00799BH Serial Status Register 6 SSR6 R, R/W 00799CH Extended Communication Control Register 6 ECCR6 R, W, R/W 00799DH Extended Status Control Register 6 ESCR6 R/W 00000X00B 00799EH Baud Rate Generator Register 60 BGR60 R, R/W 00000000B 00799FH Baud Rate Generator Register 61 BGR61 R, R/W 00000000B 0079A0H UART Input Level Setting Register ILSR2 R/W UART 11111100B 0079A1H UART6 00001000B 000000XXB Reserved 0079A2H Flash Write Control Register 0 FWR0 R/W Flash Memory 00000000B 0079A3H Flash Write Control Register 1 FWR1 R/W Flash Memory 00000000B R/W Low Voltage/ CPU Operation Detection Reset 10000111B 0079A4H to 0079B1H 0079B2H Reserved Low Voltage/CPU Operation Detection Setting Register 0079B3H to 0079B7H Reserved 0079B8H Clock Calibration Unit Control 0079B9H CR Oscillation Trimming Setting 0079BAH 0079BBH 0079BCH 0079BDH 0079BEH 0079BFH LVRS CR Oscillation Timer Data Register Main Timer Data Register 1 Main Timer Data Register 2 0079C0H to 0079DFH Document Number: 002-04500 Rev. *C CUCR R/W 00000000B CRTR R/W 11110111B CUTDL R/W 01010000B CUTDH R/W CUTR1L R CUTR1H R 00000000B CUTR2L R 00000000B CUTR2H R 00000000B Clock Calibration Unit 11000011B 00000000B Reserved Page 33 of 80 CY90950 Series Address Register Abbreviation Access Resource Name Initial Value 0079E0H Detect Address Setting 0 PADR0 R/W XXXXXXXXB 0079E1H Detect Address Setting 0 PADR0 R/W XXXXXXXXB 0079E2H Detect Address Setting 0 PADR0 R/W 0079E3H Detect Address Setting 1 PADR1 R/W 0079E4H Detect Address Setting 1 PADR1 R/W XXXXXXXXB 0079E5H Detect Address Setting 1 PADR1 R/W XXXXXXXXB 0079E6H Detect Address Setting 2 PADR2 R/W 0079E7H Detect Address Setting 2 PADR2 R/W 0079E8H Detect Address Setting 2 PADR2 R/W XXXXXXXXB 0079E9H to 0079EFH Address Match Detection 0 Address Match Detection 0 XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Reserved 0079F0H Detect Address Setting 3 PADR3 R/W XXXXXXXXB 0079F1H Detect Address Setting 3 PADR3 R/W XXXXXXXXB 0079F2H Detect Address Setting 3 PADR3 R/W XXXXXXXXB 0079F3H Detect Address Setting 4 PADR4 R/W 0079F4H Detect Address Setting 4 PADR4 R/W 0079F5H Detect Address Setting 4 PADR4 R/W XXXXXXXXB 0079F6H Detect Address Setting 5 PADR5 R/W XXXXXXXXB 0079F7H Detect Address Setting 5 PADR5 R/W XXXXXXXXB 0079F8H Detect Address Setting 5 PADR5 R/W XXXXXXXXB Address Match Detection 1 0079F9H to 0079FFH Reserved 007A00H to 007AFFH Reserved for CAN Controller 0. Refer to “CAN Controllers” 007B00H to 007BFFH Reserved for CAN Controller 0. Refer to “CAN Controllers”” 007C00H to 007CFFH Reserved for CAN Controller 1. Refer to “CAN Controllers”” 007D00H to 007DFFH Reserved for CAN Controller 1. Refer to “CAN Controllers”” 007E00H to 007EFFH Reserved for CAN Controller 2. Refer to “CAN Controllers”” 007F00H to 007FFFH Reserved for CAN Controller 2. Refer to “CAN Controllers”” Notes : XXXXXXXXB XXXXXXXXB  Initial value of “X” represents unknown value.  Any write access to reserved addresses in I/O map should not be performed. A read access to reserved addresses results in reading “X”. Document Number: 002-04500 Rev. *C Page 34 of 80 CY90950 Series 9. CAN Controllers The CAN controller has the following features: ■ Conforms to CAN Specification Version 2.0 Part A and B Supports transmission/reception in standard frame and extended frame formats ■ Supports transmission of data frames by receiving remote frames ■ 16 transmission/reception message buffers 29-bit ID and 8-byte data Multi-level message buffer configuration ■ Provides full-bit comparison, full-bit mask, acceptance register 0/acceptance register 1 for each message buffer as ID acceptance mask Two acceptance mask registers in either standard frame format or extended frame formats ■ Bit rate programmable from 10 kbps to 2 Mbps (when input clock is at 16 MHz) ■ List of Control Registers (1) Address CAN0 CAN1 CAN2 000070H 000080H 0000E0H 000071H 000081H 0000E1H 000072H 000082H 0000E2H 000073H 000083H 0000E3H 000074H 000084H 0000E4H 000075H 000085H 0000E5H 000076H 000086H 0000E6H 000077H 000087H 0000E7H 000078H 000088H 0000E8H 000079H 000089H 0000E9H 00007AH 00008AH 0000EAH 00007BH 00008BH 0000EBH 00007CH 00008CH 0000ECH 00007DH 00008DH 0000EDH 00007EH 00008EH 0000EEH 00007FH 00008FH 0000EFH Document Number: 002-04500 Rev. *C Register Abbreviation Access Initial Value Message Buffer Valid Register BVALR R/W 00000000B 00000000B Transmit Request Register TREQR R/W 00000000B 00000000B Transmit Cancel Register TCANR W 00000000B 00000000B Transmission Complete Register TCR R/W 00000000B 00000000B Receive Complete Register RCR R/W 00000000B 00000000B Remote Request Receiving Register RRTRR R/W 00000000B 00000000B Receive Overrun Register ROVRR R/W 00000000B 00000000B Reception Interrupt Enable Register RIER R/W 00000000B 00000000B Page 35 of 80 CY90950 Series ■ List of Control Registers (2) Address CAN0 CAN1 CAN2 007B00H 007D00H 007F00H 007B01H 007D01H 007F01H 007B02H 007D02H 007F02H 007B03H 007D03H 007F03H 007B04H 007D04H 007F04H 007B05H 007D05H 007F05H 007B06H 007D06H 007F06H 007B07H 007D07H 007F07H 007B08H 007D08H 007F08H 007B09H 007D09H 007F09H 007B0AH 007D0AH 007F0AH 007B0BH 007D0BH 007F0BH 007B0CH 007D0CH 007F0CH 007B0DH 007D0DH 007F0DH 007B0EH 007D0EH 007F0EH 007B0FH 007D0FH 007F0FH 007B10H 007D10H 007F10H 007B11H 007D11H 007F11H 007B12H 007D12H 007F12H 007B13H 007D13H 007F13H 007B14H 007D14H 007F14H 007B15H 007D15H 007F15H 007B16H 007D16H 007F16H 007B17H 007D17H 007F17H 007B18H 007D18H 007F18H 007B19H 007D19H 007F19H 007B1AH 007D1AH 007F1AH 007B1BH 007D1BH 007F1BH Document Number: 002-04500 Rev. *C Register Abbreviation Access Initial Value Control Status Register CSR R/W, W R/W, R 0XXXX0X1B 00XXX000B Last Event Indicator Register LEIR R/W 000X0000B XXXXXXXXB Receive And Transmit Error Counter RTEC R 00000000B 00000000B Bit Timing Register BTR R/W 11111111B X1111111B IDE Register IDER R/W XXXXXXXXB XXXXXXXXB Transmit RTR Register TRTRR R/W 00000000B 00000000B Remote Frame Receive Waiting Register RFWTR R/W XXXXXXXXB XXXXXXXXB Transmit Interrupt Enable Register TIER R/W 00000000B 00000000B Acceptance Mask Select Register Acceptance Mask Register 0 Acceptance Mask Register 1 AMSR R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB AMR0 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB AMR1 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Page 36 of 80 CY90950 Series ■ List of Message Buffers (ID Registers) (1) Address CAN0 CAN1 CAN2 007A00H to 007A1FH 007C00H to 007C1FH 007E00H to 007E1FH 007A20H 007C20H 007E20H 007A21H 007C21H 007E21H 007A22H 007C22H 007E22H 007A23H 007C23H 007E23H 007A24H 007C24H 007E24H 007A25H 007C25H 007E25H 007A26H 007C26H 007E26H 007A27H 007C27H 007E27H 007A28H 007C28H 007E28H 007A29H 007C29H 007E29H 007A2AH 007C2AH 007E2AH 007A2BH 007C2BH 007E2BH 007A2CH 007C2CH 007E2CH 007A2DH 007C2DH 007E2DH 007A2EH 007C2EH 007E2EH 007A2FH 007C2FH 007E2FH 007A30H 007C30H 007E30H 007A31H 007C31H 007E31H 007A32H 007C32H 007E32H 007A33H 007C33H 007E33H 007A34H 007C34H 007E34H 007A35H 007C35H 007E35H 007A36H 007C36H 007E36H 007A37H 007C37H 007E37H 007A38H 007C38H 007E38H 007A39H 007C39H 007E39H 007A3AH 007C3AH 007E3AH 007A3BH 007C3BH 007E3BH 007A3CH 007C3CH 007E3CH 007A3DH 007C3DH 007E3DH 007A3EH 007C3EH 007E3EH 007A3FH 007C3FH 007E3FH Document Number: 002-04500 Rev. *C Register Abbreviation Access Initial Value GeneralPurpose Ram  R/W XXXXXXXXB to XXXXXXXXB ID Register 0 IDR0 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID Register 1 IDR1 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID Register 2 IDR2 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID Register 3 IDR3 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID Register 4 IDR4 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID Register 5 IDR5 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID Register 6 IDR6 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID Register 7 IDR7 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Page 37 of 80 CY90950 Series ■ List of Message Buffers (ID Registers) (2) Address CAN0 CAN1 CAN2 007A40H 007C40H 007E40H 007A41H 007C41H 007E41H 007A42H 007C42H 007E42H 007A43H 007C43H 007E43H 007A44H 007C44H 007E44H 007A45H 007C45H 007E45H 007A46H 007C46H 007E46H 007A47H 007C47H 007E47H 007A48H 007C48H 007E48H 007A49H 007C49H 007E49H 007A4AH 007C4AH 007E4AH 007A4BH 007C4BH 007E4BH 007A4CH 007C4CH 007E4CH 007A4DH 007C4DH 007E4DH 007A4EH 007C4EH 007E4EH 007A4FH 007C4FH 007E4FH 007A50H 007C50H 007E50H 007A51H 007C51H 007E51H 007A52H 007C52H 007E52H 007A53H 007C53H 007E53H 007A54H 007C54H 007E54H 007A55H 007C55H 007E55H 007A56H 007C56H 007E56H 007A57H 007C57H 007E57H 007A58H 007C58H 007E58H 007A59H 007C59H 007E59H 007A5AH 007C5AH 007E5AH 007A5BH 007C5BH 007E5BH 007A5CH 007C5CH 007E5CH 007A5DH 007C5DH 007E5DH 007A5EH 007C5EH 007E5EH 007A5FH 007C5FH 007E5FH Document Number: 002-04500 Rev. *C Register ID Register 8 Abbreviation IDR8 Access R/W Initial Value XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID Register 9 IDR9 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID Register 10 IDR10 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID Register 11 IDR11 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID Register 12 IDR12 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID Register 13 IDR13 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID Register 14 IDR14 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB ID Register 15 IDR15 R/W XXXXXXXXB XXXXXXXXB XXXXXXXXB XXXXXXXXB Page 38 of 80 CY90950 Series ■ List of Message Buffers (DLC Registers and Data Registers) (1) Address Register CAN0 CAN1 CAN2 007A60H 007C60H 007E60H 007A61H 007C61H 007E61H 007A62H 007C62H 007E62H 007A63H 007C63H 007E63H 007A64H 007C64H 007E64H 007A65H 007C65H 007E65H 007A66H 007C66H 007E66H 007A67H 007C67H 007E67H 007A68H 007C68H 007E68H 007A69H 007C69H 007E69H 007A6AH 007C6AH 007E6AH 007A6BH 007C6BH 007E6BH 007A6CH 007C6CH 007E6CH 007A6DH 007C6DH 007E6DH 007A6EH 007C6EH 007E6EH 007A6FH 007C6FH 007E6FH 007A70H 007C70H 007E70H 007A71H 007C71H 007E71H 007A72H 007C72H 007E72H 007A73H 007C73H 007E73H 007A74H 007C74H 007E74H 007A75H 007C75H 007E75H 007A76H 007C76H 007E76H 007A77H 007C77H 007E77H 007A78H 007C78H 007E78H 007A79H 007C79H 007E79H 007A7AH 007C7AH 007E7AH 007A7BH 007C7BH 007E7BH 007A7CH 007C7CH 007E7CH 007A7DH 007C7DH 007E7DH 007A7EH 007C7EH 007E7EH 007A7FH 007C7FH 007E7FH Document Number: 002-04500 Rev. *C Abbreviation Access Initial Value DLC Register 0 DLCR0 R/W XXXXXXXXB DLC Register 1 DLCR1 R/W XXXXXXXXB DLC Register 2 DLCR2 R/W XXXXXXXXB DLC Register 3 DLCR3 R/W XXXXXXXXB DLC Register 4 DLCR4 R/W XXXXXXXXB DLC Register 5 DLCR5 R/W XXXXXXXXB DLC Register 6 DLCR6 R/W XXXXXXXXB DLC Register 7 DLCR7 R/W XXXXXXXXB DLC Register 8 DLCR8 R/W XXXXXXXXB DLC Register 9 DLCR9 R/W XXXXXXXXB DLC Register 10 DLCR10 R/W XXXXXXXXB DLC Register 11 DLCR11 R/W XXXXXXXXB DLC Register 12 DLCR12 R/W XXXXXXXXB DLC Register 13 DLCR13 R/W XXXXXXXXB DLC Register 14 DLCR14 R/W XXXXXXXXB DLC Register 15 DLCR15 R/W XXXXXXXXB Page 39 of 80 CY90950 Series ■ List of Message Buffers (DLC Registers and Data Registers) (2) Address Register CAN0 CAN1 CAN2 Abbreviation Access Initial Value 007A80H to 007A87H 007C80H to 007C87H 007E80H to 007E87H Data Register 0 (8 bytes) DTR0 R/W XXXXXXXXB to XXXXXXXXB 007A88H to 007A8FH 007C88H to 007C8FH 007E88H to 007E8FH Data Register 1 (8 bytes) DTR1 R/W XXXXXXXXB to XXXXXXXXB 007A90H to 007A97H 007C90H to 007C97H 007E90H to 007E97H Data Register 2 (8 bytes) DTR2 R/W XXXXXXXXB to XXXXXXXXB 007A98H to 007A9FH 007C98H to 007C9FH 007E98H to 007E9FH Data Register 3 (8 bytes) DTR3 R/W XXXXXXXXB to XXXXXXXXB 007AA0H to 007AA7H 007CA0H to 007CA7H 007EA0H to 007EA7H Data Register 4 (8 bytes) DTR4 R/W XXXXXXXXB to XXXXXXXXB 007AA8H to 007AAFH 007CA8H to 007CAFH 007EA8H to 007EAFH Data Register 5 (8 bytes) DTR5 R/W XXXXXXXXB to XXXXXXXXB 007AB0H to 007AB7H 007CB0H to 007CB7H 007EB0H to 007EB7H Data Register 6 (8 bytes) DTR6 R/W XXXXXXXXB to XXXXXXXXB 007AB8H to 007ABFH 007CB8H to 007CBFH 007EB8H to 007EBFH Data Register 7 (8 bytes) DTR7 R/W XXXXXXXXB to XXXXXXXXB 007AC0H to 007AC7H 007CC0H to 007CC7H 007EC0H to 007EC7H Data Register 8 (8 bytes) DTR8 R/W XXXXXXXXB to XXXXXXXXB 007AC8H to 007ACFH 007CC8H to 007CCFH 007EC8H to 007ECFH Data Register 9 (8 bytes) DTR9 R/W XXXXXXXXB to XXXXXXXXB 007AD0H to 007AD7H 007CD0H to 007CD7H 007ED0H to 007ED7H Data Register 10 (8 bytes) DTR10 R/W XXXXXXXXB to XXXXXXXXB 007AD8H to 007ADFH 007CD8H to 007CDFH 007ED8H to 007EDFH Data Register 11 (8 bytes) DTR11 R/W XXXXXXXXB to XXXXXXXXB 007AE0H to 007AE7H 007CE0H to 007CE7H 007EE0H to 007EE7H Data Register 12 (8 bytes) DTR12 R/W XXXXXXXXB to XXXXXXXXB 007AE8H to 007AEFH 007CE8H to 007CEFH 007EE8H to 007EEFH Data Register 13 (8 bytes) DTR13 R/W XXXXXXXXB to XXXXXXXXB Document Number: 002-04500 Rev. *C Page 40 of 80 CY90950 Series ■ List of Message Buffers (DLC Registers and Data Registers) (3) Address Register CAN0 CAN1 CAN2 Abbreviation Access Initial Value 007AF0H to 007AF7H 007CF0H to 007CF7H 007EF0H to 007EF7H Data Register 14 (8 bytes) DTR14 R/W XXXXXXXXB to XXXXXXXXB 007AF8H to 007AFFH 007CF8H to 007CFFH 007EF8H to 007EFFH Data Register 15 (8 bytes) DTR15 R/W XXXXXXXXB to XXXXXXXXB Document Number: 002-04500 Rev. *C Page 41 of 80 CY90950 Series 10. Interrupt Factors, Interrupt Vectors, Interrupt Control Register Interrupt Cause EI2OS Support DMA Channel Number Interrupt Vector Number Address #08 FFFFDCH #09 FFFFD8H #10 FFFFD4H #11 FFFFD0H #12 FFFFCCH #13 FFFFC8H #14 FFFFC4H #15 FFFFC0H #16 FFFFBCH Reset N INT9 instruction N Exception N CAN0 RX N CAN0 TX/NS N CAN1 RX/Input Capture 6 Y1 CAN1 TX/NS/Input Capture 7 Y1 CAN2 RX / I2C0 N CAN2 TX / NS / Clock Calibration Unit N          16-bit Reload Timer 0 Y1 0 #17 FFFFB8H 16-bit Reload Timer 1 Y1 1 #18 FFFFB4H 16-bit Reload Timer 2 Y1 2 #19 FFFFB0H 16-bit Reload Timer 3 Y1 #20 FFFFACH PPG0 / PPG1 / PPG4 / PPG5 N #21 FFFFA8H PPG2 / PPG3 / PPG6 / PPG7 N #22 FFFFA4H PPG8 / PPG9 / PPGC / PPGD N #23 FFFFA0H PPGA / PPGB / PPGE / PPGF N #24 FFFF9CH Time Base Timer N       #25 FFFF98H External Interrupt 0 to 3, 8 to 11 Y1 3 #26 FFFF94H Watch Timer N  #27 FFFF90H External Interrupt 4 to 7, 12 to 15 Y1 4 #28 FFFF8CH A/D Converter Y1 5 #29 FFFF88H I/O Timer 0/1 N  #30 FFFF84H Input Capture 4/5 / I2C1 Y1 6 #31 FFFF80H Output Compare 0/1/4/5 Y1 7 #32 FFFF7CH Input Capture 0 to 3 Y1 8 #33 FFFF78H Output Compare 2/3/6/7 Y1 9 #34 FFFF74H UART0 RX Y2 10 #35 FFFF70H UART0 TX Y1 11 #36 FFFF6CH UART1 RX / UART3 RX / UART5 RX Y2 12 #37 FFFF68H UART1 TX / UART3 TX / UART5 TX Y1 13 #38 FFFF64H UART2 RX / UART4 RX / UART6 RX Y2 14 #39 FFFF60H UART2 TX / UART4 TX / UART6 TX Y1 15 #40 FFFF5CH Flash Memory N #41 FFFF58H Delayed Interrupt N #42 FFFF54H   Interrupt Control Register Number Address       ICR00 0000B0H ICR01 0000B1H ICR02 0000B2H ICR03 0000B3H ICR04 0000B4H ICR05 0000B5H ICR06 0000B6H ICR07 0000B7H ICR08 0000B8H ICR09 0000B9H ICR10 0000BAH ICR11 0000BBH ICR12 0000BCH ICR13 0000BDH ICR14 0000BEH ICR15 0000BFH Y1 : Usable Y2 : Usable, with EI2OS stop function N : Unusable Document Number: 002-04500 Rev. *C Page 42 of 80 CY90950 Series Notes :  The peripheral resources sharing the ICR register have the same interrupt level.  When two peripheral resources share the ICR register, only one can use Extended Intelligent I/O Service at a time.  When either of the two peripheral resources sharing the ICR register specifies Extended Intelligent I/O Service, the other one cannot use interrupts. Document Number: 002-04500 Rev. *C Page 43 of 80 CY90950 Series 11. Electrical Characteristics 11.1 Absolute Maximum Ratings Parameter Symbol Rating Min Max Unit Remarks VCC VSS  0.3 VSS  6.0 V AVCC VSS  0.3 VSS  6.0 V VCC  AVCC*2 AVRH, AVRL VSS  0.3 VSS  6.0 V AVCCAVRH, AVCCAVRL, AVRHAVRL Input voltage*1 VI VSS  0.3 VSS  6.0 V *3 Output voltage*1 VO VSS  0.3 VSS  6.0 V *3 ICLAMP 4.0 4.0 mA *5 40 mA *5 Power supply voltage*1 Maximum Clamp Current “L” level average output current IOLAV    “L” level maximum overall output current IOL IOLAV Total Maximum Clamp Current “L” level maximum output current “L” level average overall output current |ICLAMP| IOL 15 mA *4 4 mA *4  100 mA *4  50 mA *4 mA *4 IOHAV   15 “H” level average output current 4 mA *4 “H” level maximum overall output current IOH  100 mA *4 “H” level average overall output current IOHAV  50 mA *4 “H” level maximum output current Power consumption Operating temperature Storage temperature IOH PD TA TSTG  430 mW 40 105 C 40 125 C 55 150 C *6 *1: This parameter is based on VSS  AVSS  0 V *2: Set AVCC and VCC to the same voltage. Make sure that AVCC does not exceed VCC and that the voltage at the analog inputs does not exceed AVCC when the power is switched on. *3: VI and VO should not exceed VCC  0.3 V. VI should not exceed the specified ratings. However if the maximum current to/from an input is limited by some means with external components, the ICLAMP rating supersedes the VI rating. *4: Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P57, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0, PA1 (Continued) Document Number: 002-04500 Rev. *C Page 44 of 80 CY90950 Series (Continued) *5:  Applicable to pins: P00 to P07, P10 to P17, P20 to P27, P30 to P37, P40 to P47, P50 to P55, P60 to P67, P70 to P77, P80 to P87, P90 to P97, PA0 to PA1  Use within recommended operating conditions.  Use with DC voltage (current)  The B signal should always be applied by using a limiting resistance placed between the B signal and the microcontroller.  The value of the limiting resistance should be set so that when the B signal is applied, the input current to the microcontroller pin does not exceed the rated value, either instantaneously or for prolonged periods.  Note that when the microcontroller drive current is low, such as in the power saving modes, the B input potential may pass through the protective diode and increase the potential at the VCC pin, and this may affect other devices.  Note that if a B signal is input when the microcontroller power supply is off (not fixed at 0 V) , the power supply is provided from the pins, so that incomplete operation may result.  Note that if the B input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset.  Care must be taken not to leave the B input pin open.  Sample recommended circuits: • Input/output equivalent circuits Protective diode VCC Limiting resistance P-ch B input (0 V to 16 V) N-ch R *6 : If used exceeding TA =  105C, please consult with us due to the restricted reliability. It is ensured to write/erase data to the Flash memory between TA =  40C and  105C. WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings. Document Number: 002-04500 Rev. *C Page 45 of 80 CY90950 Series 11.2 Recommended Operating Conditions Parameter Power supply voltage Symbol Conditions VCC, AVCC  Smoothing capacitor CS  Operating temperature TA  (VSS  AVSS  0 V) Value Unit Remarks Min Typ Max 3.0 5.0 5.5 V Under normal operation 4.5 5.0 5.5 V When External bus is used. 3.0  5.5 V Maintains RAM data in stop mode 0.1  1.0 F Use a ceramic capacitor or capacitor of better AC characteristics. Capacitor at the VCC should be greater than this capacitor. 40 40   105 125 C CY90F952JDS, CY90F952MDS * * : If used exceeding TA =  105C, please consult with us due to the restricted reliability. It is ensured to write/erase data to the Flash memory between TA =  40C and  105C. C Pin Connection Diagram C CS WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device’s electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their representatives beforehand. Document Number: 002-04500 Rev. *C Page 46 of 80 CY90950 Series 11.3 DC Characteristics Parameter Input H voltage (At VCC  5 V  10) Input L voltage (At VCC  5 V  10) Symbol Pin Name Conditions VIHS  VIHA Value Unit Remarks VCC  0.3 V Port inputs if CMOS hysteresis input levels are selected  VCC  0.3 V Port inputs if Automotive input levels are selected 2.0  VCC  0.3 V Port inputs if TTL input levels are selected 0.7 VCC  VCC  0.3 V Port inputs if CMOS hysteresis input levels are selected VCC  0.3 V RST input pin (CMOS hysteresis) VCC  0.3 V MD input pins Min Typ Max  0.8 VCC    0.8 VCC VIHT   VIHS P12,P15, P44 to P47, P50,P82, P85,P90, P94  VIHR RST VIHM MD0 to MD2   VCC  0.3   VILS   VSS  0.3  0.2 VCC V Port inputs if CMOS hysteresis input levels are selected VILA   VSS  0.3  0.5 VCC V Port inputs if Automotive input levels are selected VILT   VSS  0.3  0.8 V Port inputs if TTL input levels are selected VILS P12,P15, P44 to P47, P50,P82, P85,P90, P94  VSS  0.3  0.3 VCC V Port inputs if CMOS hysteresis input levels are selected VILR RST   VSS  0.3 0.2 VCC V RST input pin (CMOS hysteresis) VSS  0.3 V MD input pins  V 0.8 VCC VOH Normal outputs VCC  4.5 V, IOH  4.0 mA VCC  0.5    Output H voltage VOHI I2C outputs VCC  4.5 V, IOH  3.0 mA VCC  0.5   V Output L voltage VOL Normal outputs VCC  4.5 V, IOL  4.0 mA   0.4 V Output L voltage VOLI I2C outputs VCC  4.5 V, IOL  3.0 mA   0.4 V VILM Output H voltage MD0 to MD2 VSS  0.3 IIL  VCC  5.5 V, VSS  VI  VCC 1  1 A Pull-up resistance RUP P00 to P07, P10 to P17, P20 to P27, P30 to P37, RST  25 50 100 k Pull-down resistance RDOWN MD2  25 50 100 k Input leak current Document Number: 002-04500 Rev. *C Except Flash memory devices Page 47 of 80 CY90950 Series Parameter Symbol Pin Name Unit Remarks Typ Max VCC  5.0 V, Internal frequency : 32 MHz, At normal operation.  40 50 mA VCC  5.0 V, Internal frequency : 32 MHz, At writing Flash memory/erasing.  50 65 mA VCC  5.0 V, Internal frequency : 32 MHz, In Sleep mode.  13 23 mA VCC  5.0 V, Internal frequency : 2 MHz, In Main Timer mode  0.4 1.0  0.3 0.9 VCC  5.0 V, Internal frequency : 32 MHz, In PLL Timer mode, external frequency  4 MHz  4 7 mA ICCL VCC = 5.0 V Internal frequency : 12.5 kHz, In CR sub operation TA = 25C  170 400 A CY90F952JDS ICCLS VCC = 5.0 V Internal frequency : 12.5 kHz, In CR sub sleep TA = 25C  130 250 A CY90F952JDS ICCT VCC = 5.0 V Internal frequency : 12.5 kHz, In CR watch mode TA = 25C  130 250 A CY90F952JDS VCC  5.0 V, In Stop mode, TA  25C  70 170 ICCS ICTS ICTSPLL 6 VCC ICCH Input capacitance Value Min ICC Power supply current* Conditions CIN Other than C, AVCC, AVSS, AVRH, AVRL, VCC, VSS  mA CY90F952JDS, CY90F952MDS CY90F952JDS CY90F952MDS CY90F952JDS A  25 100  5 15 CY90F952MDS pF * : The power supply current is measured with an external clock. Document Number: 002-04500 Rev. *C Page 48 of 80 CY90950 Series 11.4 AC Characteristics 11.4.1 Clock Timing Parameter (TA  40C to 105C, VCC  5.0 V  10, fCP  32 MHz, VSS  AVSS  0 V) Symbol Clock frequency fC Pin Name X0, X1 Conditions  Clock cycle time tCYL X0, X1 Internal operating clock frequency (machine clock) fCP    fCPL  tCP Internal operating clock cycle time (machine clock) Internal CR oscillation frequency Value Min Typ Max Unit Remarks 3 16 1/2 multiplied (PLL stopped) When using an oscillation circuit 4 16 PLL multiplied by 1 When using an oscillation circuit 4 16 PLL multiplied by 2 When using an oscillation circuit 4  10 MHz PLL multiplied by 3 When using an oscillation circuit 4 8 PLL multiplied by 4 When using an oscillation circuit 4 5 PLL multiplied by 6 When using an oscillation circuit 4 4 PLL multiplied by 8 When using an oscillation circuit 1.5    10.625 12.5 14.375 kHz   31.25  666 ns When using main clock tCPL   69.565 80 94.118 s When using CR clock fCCR   85 100 115 kHz 62.5 333 ns When using an oscillation circuit 32 MHz When using main clock When using CR clock When trimming with the clock calibration unit  When oscillation circuit is used tCYL X0, X1 Amplitude: It varies depending on the external resistance, power rating and the different kind of device. Reference values: 1 V to 2.5 V Note: The amplitude of CY90V950AJAS and CY90V950AMAS are the same as VCC. Document Number: 002-04500 Rev. *C Page 49 of 80 CY90950 Series Power supply voltage VCC (V) • Guaranteed PLL operation range Guaranteed operation range 5.5 3.0 Guaranteed operation range 1.5 4 32 Internal clock fCP (MHz) Note: When the power supply voltage is lower than the setting voltage of low voltage detection, CY90F952JDS are reset. Internal clock fCP  External clock fC Guaranteed oscillation frequency range 8 6 4 3 2 1 Internal clock fCP 32 24 ×1/2 16 (PLL off) 12 8 4.0 1.5 3 4 8 12 16 24 32 External clock fC (MHz)* * : When using a crystal oscillator or ceramic oscillator, the maximum oscillation clock frequency is 16 MHz Document Number: 002-04500 Rev. *C Page 50 of 80 CY90950 Series 11.4.2 Reset Standby Input Parameter Reset input time Symbol Pin Name tRSTL Conditions  RST Value Unit Remarks Min Max 500  ns Under normal operation Oscillation time of oscillator*  100 s  s In Stop mode, Sub Clock mode, Sub Sleep mode and Watch mode 100  s In Time Base Timer mode * : The oscillation time of the oscillator is the time it takes for the amplitude of the oscillations to reach 90. For crystal oscillators, this time is between several ms and several tens of ms, for ceramic oscillators the time is between several hundred s and several ms, and for an external clock, the time is 0 ms.  Under normal operation: tRSTL RST VILR VILR  In Stop mode, Sub Clock mode, Sub Sleep mode, Watch mode: tRSTL RST VILR X0 VILR 90% of amplitude Internal operation clock 100 µs Oscillation time of oscillator Oscillation stabilization waiting time Instruction execution Internal reset Document Number: 002-04500 Rev. *C Page 51 of 80 CY90950 Series 11.4.3 Power On Reset Parameter Power on rise time Power off time Symbol Pin Name tR VCC tOFF VCC Value Conditions  Unit Min Max 0.05 30 ms 1  ms Remarks Due to repetitive operation tR VCC 2.7 V 0.2 V 0.2 V 0.2 V tOFF Note: If you change the power supply voltage too rapidly, a power on reset may occur. We recommend that you startup smoothly by restraining voltages when changing the power supply voltage during operation, as shown in the figure below. Perform while not using the PLL clock. However, if voltage drops are within 1 V/s, you can operate while using the PLL clock. VCC We recommend a rise of 50 mV/ms maximum. 3V Holds RAM data VSS 11.4.4 Clock Output Timing Parameter Cycle time CLK   CLK  Symbol Pin Name Conditions tCYC CLK  tCHCL Value Min  CLK Max Unit Remarks tcp*  ns tcp* / 2  15 tcp* / 2  15 ns fCP  25 MHz tcp* / 2  20 tcp* / 2  20 ns fCP  16 MHz * : tcp is the Internal clock cycle time. Refer to “ (1) Clock Timing”. tCYC tCHCL CLK 2.4 V 2.4 V 0.8 V Document Number: 002-04500 Rev. *C Page 52 of 80 CY90950 Series 11.4.5 Bus Timing (Read) Parameter ALE pulse width Symbol Pin Name tLHLL Conditions ALE  Value Unit Remarks Min Max tcp*/ 2  15  ns 16MHz < fcp  25 MHz tcp*/ 2  20  ns 8 MHz < fcp  16 MHz tcp*/ 2  35  ns fcp  8 MHz tcp*/ 2  17  ns tcp*/ 2  40  ns tAVLL Address, ALE  ALE   Address valid time tLLAX ALE , Address  tcp*/ 2  15  ns Valid address  RD  time tAVRL RD , Address  tcp*  25  ns Valid address  Valid data input tAVDV Address/ Data   tcp* / 2  55 ns  tcp* / 2  80 ns fcp  8 MHz Valid address  ALE  time RD pulse width tRLRH RD 3 tcp* / 2  25  ns 16 MHz < fcp  25 MHz 3 tcp* / 2  20  ns 8 MHz < fcp  16 MHz 3 tcp* / 2  55 ns 3 tcp* / 2  80 ns  tRLDV RD , Data  RD   Data hold time tRHDX RD , Data  0  ns RD   ALE  time tRHLH RD , ALE  tcp* / 2  15  ns RD   Address valid time tRHAX Address, RD  tcp* / 2  10  ns Valid address  CLK  time tAVCH Address, CLK  tcp* / 2  17  ns RD   CLK  time tRLCH RD,CLK  tcp* / 2  17  ns ALE   RD  time tLLRL RD,ALE  tcp* / 2  15  ns RD   Valid data input fcp  8 MHz fcp  8 MHz * : tcp is the Internal cycle time. Refer to “Clock Timing”. Document Number: 002-04500 Rev. *C Page 53 of 80 CY90950 Series tWLCH 2.4 V tWHLH 2.4 V tWLWH 2.4 V 0.8 V tWHAX tAVWL 2.4 V 2.4 V 0.8 V 0.8 V tDVWH tWHDX 2.4 V 2.4 V 2.4 V 0.8 V 0.8 V 0.8 V Document Number: 002-04500 Rev. *C Page 54 of 80 CY90950 Series 11.4.6 Bus Timing (Write) Parameter Valid address  WR  time WR pulse width Valid data output  WR  time Symbol Pin Name Conditions tAVWL Address, WR  tWLWH WRL, WRH tDVWH Data, WR   Value Unit Max tcp*  15  ns 3 tcp* / 2  25  ns 16 MHz < fcp  25 MHz 3 tcp* / 2  20  ns 8 MHz < fcp  16 MHz 3 tcp* / 2  15  ns 10  ns 16 MHz < fcp  25 MHz 20  ns 8 MHz < fcp  16 MHz 30  ns fcp  8 MHz tWHDX WR , Data WR   A ddress valid time tWHAX WR , Address  tcp* / 2  10  ns WR   ALE  time tWHLH WR , ALE  tcp* / 2  15  ns WR   CLK  time tWLCH WR , CLK  tcp* / 2  17  ns WR   Data hold time Remarks Min  *: tcp is the Internal operating clock cycle time. Refer to “Clock Timing”. Document Number: 002-04500 Rev. *C Page 55 of 80 CY90950 Series tWLCH 2.4 V CLK tWHLH 2.4 V ALE tWLWH 2.4 V 0.8 V WR (WRL, WRH) tWHAX tAVWL 2.4 V 2.4 V 0.8 V 0.8 V tDVWH A23 to A16 AD15 to AD00 Document Number: 002-04500 Rev. *C tWHDX 2.4 V 2.4 V 2.4 V 0.8 V 0.8 V 0.8 V Address Write data Page 56 of 80 CY90950 Series 11.4.7 Ready Input Timing Parameter Symbol Pin Name RDY setup time tRYHS RDY RDY hold time tRYHH RDY Rated Value Test Condition Min  70 Unit Max    35 0 Remarks ns ns fCP  8 MHz ns Note : If the RDY setup time is insufficient, use the auto-ready function. CLK 2.4 V 2.4 V ALE RD/WR tRYHS RDY When WAIT is not used. RDY When WAIT is used. (1 cycle) Document Number: 002-04500 Rev. *C tRYHH VIHT VILT VIHT VILT tRYHS Page 57 of 80 CY90950 Series 11.4.8 Hold Timing Parameter Symbol Pin Name Conditions Pin floating  HAK  time tXHAL HAK HAK   time  Pin valid time tHAHV HAK  Value Min Max Unit 30 tCP* ns tCP* 2 tCP* ns * : tcp is the Internal operating clock cycle time. Refer to “Clock Timing”. Note : There is more than 1 cycle from when HRQ reads in until the HAK is changed. 2.4 V HAK 0.8 V tHAHV tXHAL Each pin Document Number: 002-04500 Rev. *C 2.4 V 0.8 V Hi-Z 2.4 V 0.8 V Page 58 of 80 CY90950 Series 11.4.9 UART ■ ESCR : SCES = 0, ECCR : SCDE = 0 Parameter Symbol Serial clock cycle time tSCYC SCK   SOT delay time tSLOVI Conditions Internal shift clock operation CL = 80 pF + 1 TTL. Value Unit Min Max 5 tcp*  ns  50  50 ns tcp*  80  ns 0  ns SIN  SCK  setup time tIVSHI SCK   SIN hold time tSHIXI Serial clock “H” pulse width tSLSH 3 tcp*  tR  ns Serial clock “L” pulse width tSHSL tcp*  10  ns SCK   SOT delay time tSLOVE SIN  SCK  setup time tIVSHE SCK   SIN hold time tSHIXE External shift clock operation CL = 80 pF + 1 TTL.  2 tcp*  60 ns 30  ns tcp*  30  ns SCK fall time tF  10 ns SCK rise time tR  10 ns *: tcp indicates the machine clock time tSCYC 2.4 V SCK 0.8 V tSLOVI 2.4 V SOT 0.8 V tIVSHI tSHIXI VIH SIN VIL Internal Clock Shift Operation Document Number: 002-04500 Rev. *C Page 59 of 80 CY90950 Series tSHSL tSLSH VIH SCK VIL tR tF tSLOVE 2.4V SOT 0.8V tIVSHE tSHIXE VIH SIN VIL External Clock Shift Operation Document Number: 002-04500 Rev. *C Page 60 of 80 CY90950 Series ■ ESCR : SCES = 1, ECCR : SCDE = 0 Parameter Symbol Serial clock cycle time tSCYC SCK   SOT delay time tSHOVI SIN  SCK  setup time tIVSLI SCK   SIN hold time tSLIXI Conditions Internal shift clock operation CL = 80 pF + 1 TTL. Value Min Max Unit 5 tcp*  ns  50  50 ns tcp*  80  ns 0  ns Serial clock “H” pulse width tSHSL 3 tcp*  tR  ns Serial clock “L” pulse width tSLSH tcp*  10  ns SCK   SOT delay time tSHOVE  2 tcp*  60 ns SIN  SCK  setup time tIVSLE 30  ns SCK   SIN hold time tSLIXE External shift clock operation CL = 80 pF + 1 TTL. tcp*  30  ns SCK fall time tF  10 ns SCK rise time tR  10 ns *: tcp indicates the machine clock time tSCYC 2.4 V SCK 0.8 V tSHOVI 2.4 V SOT 0.8 V tIVSLI tSLIXI VIH SIN VIL Internal Clock Shift Operation Document Number: 002-04500 Rev. *C Page 61 of 80 CY90950 Series tSLSH tSHSL VIH SCK VIL tSHOVE tF tR 2.4 V SOT 0.8 V tIVSLE tSLIXE VIH SIN VIL External Clock Shift Operation Document Number: 002-04500 Rev. *C Page 62 of 80 CY90950 Series ■ ESCR : SCES = 0, ECCR : SCDE = 1 Parameter Symbol Serial clock cycle time tSCYC SCK   SOT delay time tSHOVI SIN  SCK  setup time tIVSLI SCK   SIN hold time tSLIXI SOT  SCK  delay time tSOVLI Value Conditions Internal shift clock operation CL = 80 pF + 1 TTL. Unit Min Max 5 tcp*  ns  50  50 ns tcp*  80  ns 0  ns 3 tcp*  70  ns *: tcp indicates the machine clock time tSCYC 2.4 V SCK 0.8 V SOT 2.4 V 0.8 V 2.4 V 0.8 V tIVSLI SIN VIH VIL Document Number: 002-04500 Rev. *C 0.8 V tSHOVI tSOVLI tSLIXI VIH VIL Page 63 of 80 CY90950 Series ■ ESCR : SCES = 1, ECCR : SCDE = 1 Parameter Symbol Serial clock cycle time tSCYC SCK   SOT delay time tSLOVI SIN  SCK  setup time tIVSHI SCK   SIN hold time tSHIXI SOT  SCK  delay time tSOVHI Value Conditions Unit Min Max 5 tcp*  ns  50  50 ns tcp*  80  ns 0  ns 3 tcp*  70  ns Internal clock operation CL = 80 pF + 1 TTL. *: tcp indicates the machine clock time tSCYC 2.4 V SCK 2.4 V 0.8 V tSLOVI tSOVHI 2.4 V 2.4 V SOT 0.8 V 0.8 V tIVSHI SIN tSHIXI VIH VIH VIL VIL 11.4.10 rigger Input Timing Parameter Symbol Pin Name Conditions tTRGH tTRGL INT0 to INT15, INT8R to INT15R, ADTG  Input pulse width INT0 to INT15, INT8R to INT15R, ADTG Document Number: 002-04500 Rev. *C Value Min Max 5 tCP  Unit ns VIH VIH VIL VIL tTRGH tTRGL Page 64 of 80 CY90950 Series 11.4.11 Timer Related Resource Input Timing Parameter Input pulse width Symbol Pin Name Conditions tTIWH TIN0 to TIN3, IN0 to IN7  tTIWL Min Max 4 tCP  Unit ns VIH VIH TIN0 to TIN3, IN0 to IN7 Value VIL VIL tTIWH tTIWL 11.4.12 Timer Related Resource Output Timing Parameter CLK   TOUT change time CLK Symbol Pin Name Conditions tTO TOT0 to TOT3, PPG0 to PPGF  Value Min Max 30  Unit ns 2.4 V 2.4 V TOT0 to TOT3, PPG0 to PPGF 0.8 V tTO Document Number: 002-04500 Rev. *C Page 65 of 80 CY90950 Series 11.4.13 Low voltage detection Value Parameter Symbol Pin Name Conditions Min Typ Max Detection voltage initial value VDL VCC  3.8 4.0 4.2 V During voltage drop VHYS VCC  169 173 177 mV During voltage rise  0.1   0.1 V/s dV/dt at low voltage reset  0.004   0.004 V/s dV/dt at standard value of low voltage detection/release voltage   3.2 s Hysteresis width Power supply voltage change rate dV/dt VCC  Detection delay time td   Note: Unit Remarks When | dV/dt |  0.004 V/s The power supply voltage change rate is at 0.004 V/s